Semiconductor device

Abstract

A semiconductor device (A10) comprises: a semiconductor element (1); an island (31) on which the semiconductor element has been mounted; at least one extension (34) extending from an outer margin of the island as seen in the thickness direction of the island; and a sealing part (2) covering the semiconductor element. The at least one extension comprises an extension principal surface (34a) facing one way in the thickness direction, an extension reverse surface facing the opposite side from the extension principal surface, and an extension side surface (34c, 34d) arranged between the extension principal surface and the extension reverse surface. The extension side surface is covered by the sealing part.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, semiconductor devices in which semiconductor elements such as diodes, transistors, and ICs are covered with a resin package have been known. Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device described in Patent Document 1 includes a semiconductor element, leads, and a resin package. In this semiconductor device, the semiconductor element is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) chip. The semiconductor element is bonded to the leads. The leads mount the semiconductor element and are electrically connected to the semiconductor element. The resin package covers a portion of the leads and the semiconductor element.

[0003] Japanese Patent Application Laid-Open No. 2008-300492

[0004] Semiconductor devices are used in a variety of applications, including automobiles such as electric vehicles and hybrid vehicles, industrial equipment, and home appliances, and depending on the application, semiconductor elements may be required to have, for example, higher output power. Increasing the output power of such semiconductor elements may result in an increase in the size of the semiconductor elements in plan view.

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that is preferable for increasing the size of a semiconductor element in a plan view.

[0006] A semiconductor device according to a first aspect of the present disclosure includes a semiconductor element, an island on which the semiconductor element is mounted, at least one extending portion extending from a periphery of the island as viewed in a thickness direction of the island, and an encapsulating portion covering the semiconductor element. The at least one extending portion has an extending main surface facing one side in the thickness direction, an extending back surface facing the opposite side from the extending main surface in the thickness direction, and an extending side surface disposed between the extending main surface and the extending back surface in the thickness direction. The extending side surface is covered by the encapsulating portion.

[0007] According to the above configuration, the size of the semiconductor element in a plan view can be increased in the semiconductor device.

[0008] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment. FIG. 2 is a perspective view showing the semiconductor device according to the first embodiment, as seen from the bottom side. FIG. 3 is a plan view showing the semiconductor device according to the first embodiment. FIG. 4 is a view showing the sealing portion in phantom lines in the plan view of FIG. 3. FIG. 5 is an enlarged view of a main part of FIG. 4, in which the sealing portion and multiple connecting members are omitted and the semiconductor element and conductive bonding material are shown in phantom lines. FIG. 6 is a front view showing the semiconductor device according to the first embodiment. FIG. 7 is a bottom view showing the semiconductor device according to the first embodiment. FIG. 8 is a right side view showing the semiconductor device according to the first embodiment. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 4. FIG. 10 is a partially enlarged cross-sectional view of a portion of FIG. 9. FIG. 11 is a partially enlarged cross-sectional view of a portion of FIG. 9. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 4. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 4. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 4 , with multiple connecting members omitted. FIG. 15 is a schematic diagram showing a vehicle equipped with the semiconductor device according to the first embodiment. FIG. 16 is a plan view showing a process during the manufacturing of the semiconductor device according to the first embodiment. FIG. 17 is a plan view showing a semiconductor device according to a first modified example of the first embodiment. FIG. 18 is an enlarged view of a main portion of a semiconductor device according to a second modified example of the first embodiment, corresponding to FIG. 5 . FIG. 19 is an enlarged view of a main portion of a semiconductor device according to a third modified example of the first embodiment, corresponding to FIG. 5 . FIG. 20 is a plan view showing a semiconductor device according to the second embodiment, with the sealing portion indicated by an imaginary line. FIG. 21 is a cross-sectional view showing a semiconductor device according to the second embodiment, taken along line XXI-XXI in FIG. 20 . FIG. 22 is a plan view showing a semiconductor device according to a third embodiment, with the sealing portion indicated by an imaginary line.

[0009] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant descriptions will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Unless otherwise specified, "When viewed from a certain direction, an object A overlaps an object B" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." "An object A (is made of) a certain material C" includes "an object A (is made of) a certain material C" and "an object A (is made of) a certain material C as its main component."

[0011] 1 to 4 show a semiconductor device A10 according to a first embodiment. The semiconductor device A10 includes a semiconductor element 1, a conductive bonding material 19, a sealing portion 2, a plurality of leads 3, 4, and 5, and a plurality of connecting members 61 and 62. In the illustrated example, the semiconductor device A10 is a lead-through type TO (Transistor Outline) package. The package structure of the semiconductor device A10 is not limited to a TO package.

[0012] In the following description, reference is made to the thickness direction z, the first direction y, and the second direction x, which are perpendicular to each other. As an example, the thickness direction z corresponds to the thickness direction of the semiconductor device A10. "Planar view" refers to the view in the thickness direction z. The z1 side of the thickness direction z is sometimes referred to as the bottom, and the z2 side of the thickness direction z is sometimes referred to as the top. Terms such as "top," "bottom," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component, etc. in the thickness direction z, and do not necessarily define the relationship with the direction of gravity.

[0013] The semiconductor element 1 is the core of the semiconductor device A10. The semiconductor element 1 is mounted on leads 3. The semiconductor element 1 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). Unlike this example, the semiconductor element 1 may be another transistor, such as a bipolar transistor or an insulated gate bipolar transistor (IGBT), or may be a diode or an integrated circuit (IC) instead of a transistor. The semiconductor element 1 includes, for example, silicon (Si) or silicon carbide (SiC), but may also include other semiconductor materials (such as gallium nitride and diamond).

[0014] The semiconductor element 1 has an element main surface 10a and an element back surface 10b. The element main surface 10a and the element back surface 10b are spaced apart from each other in the thickness direction z. The element main surface 10a faces the z2 side in the thickness direction z (upward in the thickness direction z), and the element back surface 10b faces the z1 side in the thickness direction z (downward in the thickness direction z). The element back surface 10b faces the leads 3. The thickness of the semiconductor element 1 (dimension in the thickness direction z) is not particularly limited, but is, for example, 20 μm or more and 500 μm or less. The thickness of the semiconductor element 1 corresponds to the distance along the thickness direction z between the element main surface 10a and the element back surface 10b.

[0015] The semiconductor element 1 has a first electrode 11, a second electrode 12, and a third electrode 13. The first electrode 11 is disposed on the element back surface 10b. The second electrode 12 and the third electrode 13 are each disposed on the element main surface 10a. In the semiconductor element 1, the first electrode 11 and the second electrode 12 are switched between a conductive state and a cut-off state in response to a drive signal input to the third electrode 13. In an example in which the semiconductor element 1 is a MOSFET, the first electrode 11 is, for example, a drain electrode, the second electrode 12 is, for example, a source electrode, and the third electrode 13 is, for example, a gate electrode.

[0016] The conductive bonding material 19 bonds the semiconductor element 1. As shown in FIGS. 9 to 14 , the conductive bonding material 19 is interposed between the semiconductor element 1 and the leads 3 (islands 31 described later) and electrically bonds them together. In this embodiment, the back surface 10b of the semiconductor element 1 faces the leads 3 (islands 31 described later), so the conductive bonding material 19 electrically connects the first electrodes 11 of the semiconductor element 1 and the leads 3 (islands 31 described later). The conductive bonding material 19 is, for example, solder. Unlike this example, the conductive bonding material 19 may be a metal paste (for example, silver paste) or a sintered metal (for example, sintered silver).

[0017] As shown in Figures 9 to 14, the sealing portion 2 covers the semiconductor element 1. The sealing portion 2 covers the conductive bonding material 19, portions of the leads 3, 4, and 5, and the connecting members 61 and 62. The sealing portion 2 contains an electrically insulating resin material. The resin material is not limited to any particular material, but is, for example, epoxy resin. The method for forming the sealing portion 2 is not limited to any particular material, but is, for example, mold molding (insert molding). The sealing portion 2 has a resin main surface 21, a resin back surface 22, multiple resin side surfaces 23 and 24, and multiple recesses 25 and 26.

[0018] As shown in Figures 6, 8, 9, and 12 to 14, the resin main surface 21 and the resin back surface 22 are spaced apart from each other in the thickness direction z. The resin main surface 21 faces the z2 side in the thickness direction z (upward in the thickness direction z), and the resin back surface 22 faces the z1 side in the thickness direction z (downward in the thickness direction z). The resin main surface 21 faces the same direction as the element main surface 10a in the thickness direction z, and the resin back surface 22 faces the same direction as the element back surface 10b in the thickness direction z. The thickness of the encapsulation portion 2 (dimension in the thickness direction z) is not particularly limited, but is, for example, 250 µm or more and 7 mm or less. The thickness of the encapsulation portion 2 corresponds to the distance between the resin main surface 21 and the resin back surface 22 in the thickness direction z.

[0019] 3, 4, 7 to 9, 12, and 13, the pair of resin side surfaces 23 are spaced apart from each other in the first direction y and face opposite directions. The pair of resin side surfaces 23 are connected to the resin main surface 21 and the resin back surface 22. As shown in FIGS. 1, 3, 4, 6, and 7, each of the multiple leads 3 to 5 protrudes from one of the pair of resin side surfaces 23 (the resin side surface 23 on the y1 side in the first direction y).

[0020] 3 , 4 , 6 , 7 , and 14 , the pair of resin side surfaces 24 are spaced apart from each other in the second direction x and face opposite directions. The pair of resin side surfaces 24 are connected to the resin main surface 21 and the resin back surface 22.

[0021] As shown in FIGS. 1, 3, and 7, each of the multiple recesses 25 is formed on one of the pair of resin side surfaces 23 (the resin side surface 23 on the y1 side in the first direction y). Each of the multiple recesses 25 is recessed from the corresponding resin side surface 23. The multiple recesses 25 include one formed between the two leads 3 and 4 and one formed between the two leads 3 and 5 in the second direction x. The multiple recesses 25 can increase the creepage distance along the resin side surface 23 for two adjacent leads among the multiple leads 3 to 5. In a configuration different from that of the semiconductor device A10, the sealing portion 2 may not include any of the multiple recesses 25.

[0022] 1 and 3 , the plurality of recesses 26 are recessed from the resin main surface 21 in the thickness direction z, and are individually connected from the resin side surface 23 on the y2 side in the first direction y to a pair of resin side surfaces 24. In this embodiment, a portion of the lead 3 (an extension portion 34 and a portion of the island 31, which will be described later) is exposed from the plurality of recesses 26. In a configuration different from that of the semiconductor device A10, the sealing portion 2 may not include any of the plurality of recesses 26.

[0023] The leads 3 to 5 form a conductive path between the semiconductor element 1 and a circuit board (not shown) on which the semiconductor device A10 is mounted. The leads 3 to 5 are formed, for example, from the same lead frame. The lead frame is made of copper (Cu) or a copper alloy. Therefore, the composition of each of the leads 3 to 5 includes copper. Each of the leads 3 to 5 (lead frame) may also include a metal other than copper. The leads 3 to 5 are spaced apart from one another. As shown in FIGS. 3, 4, 6, and 7, the leads 3 to 5 each protrude from one of a pair of resin side surfaces 23 (the resin side surface 23 on the y1 side in the first direction y).

[0024] The lead 3 has the semiconductor element 1 mounted thereon and is electrically connected to the first electrode 11 of the semiconductor element 1. As shown in Figures 4 and 5, the lead 3 includes an island 31, a terminal portion 32, a relay portion 33, and two extending portions 34. In the illustrated example, the lead 3 includes two extending portions 34, but may include three or more extending portions 34. In the lead 3, the island 31, the terminal portion 32, the relay portion 33, and the two extending portions 34 are integrally formed.

[0025] The semiconductor element 1 is mounted on the island 31. The island 31 has, for example, a rectangular shape in a plan view. Therefore, a periphery 31c of the island 31 has a rectangular shape in a plan view. For ease of understanding, the periphery 31c is indicated by a thick dashed line in Fig. 5. As shown in Fig. 5, the island 31 includes a base portion 311 and an outer periphery portion 312.

[0026] In a plan view, the base 311 overlaps the semiconductor element 1. The base 311 has a rectangular shape in a plan view. There are no limitations on the thickness t311 of the base 311 (see FIGS. 10 and 11), but it is, for example, not less than 100 μm and not more than 5 mm.

[0027] The outer peripheral portion 312 is disposed around the base portion 311 in a plan view and surrounds the base portion 311. In an example where the base portion 311 is rectangular in a plan view, the outer peripheral portion 312 is rectangular annular in a plan view. The outer peripheral portion 312 does not overlap the semiconductor element 1 in a plan view. Unlike this example, a portion of the semiconductor element 1 may overlap the outer peripheral portion 312 in a plan view. The outer peripheral portion 312 includes a thin-walled portion 313.

[0028] As shown in FIG. 11 and other figures, the thin portion 313 is covered by the sealing portion 2. The thin portion 313 is thinner than the portions of the base portion 311 and the outer peripheral portion 312 other than the thin portion 313. Therefore, the thickness t313 of the thin portion 313 (dimension in the thickness direction z) is smaller than the thickness t311 of the base portion 311 (dimension in the thickness direction z). The thickness t313 of the thin portion 313 is, for example, 15% to 20% of the thickness t311 of the base portion 311. The thickness t313 of the thin portion 313 is, for example, 100 μm to 4.9 mm. As shown in FIGS. 4 and 5 , the thin portion 313 includes, for example, a portion extending along the edge of the outer peripheral portion 312 on the y1 side in the first direction y, and a pair of portions connected to both ends of the portion in the second direction x and extending along the edge in the second direction x. Unlike this example, the thin-walled portion 313 may be formed only on either one of the edges of the outer peripheral portion 312 in the first direction y or the edges of the outer peripheral portion 312 in the second direction x, or may be formed around the entire periphery of the outer peripheral portion 312. The thin-walled portion 313 is not limited to being continuous (see FIGS. 5 and 7 ) and may be divided into multiple portions. It is preferable that the thin-walled portion 313 does not overlap the semiconductor element 1 in a plan view, but it may overlap.

[0029] As shown in FIG. 11 , the thin portion 313 includes a protrusion 313a. The protrusion 313a protrudes outward in a plan view. The protrusion 313a is formed on the z1 side of the thin portion 313 in the thickness direction z. For example, the thin portion 313 is formed by crushing a portion of the outer circumferential portion 312, and the protrusion 313a is a portion of this crushed portion that protrudes outward. In a configuration different from that of the semiconductor device A10, the thin portion 313 may not include the protrusion 313a.

[0030] The island 31 has an island main surface 31a and an island back surface 31b. The island main surface 31a and the island back surface 31b are spaced apart from each other in the thickness direction z. The island main surface 31a faces the z2 side in the thickness direction z (upward in the thickness direction z), and the island back surface 31b faces the z1 side in the thickness direction z (downward in the thickness direction z). The island main surface 31a corresponds to the upper surface of the base 311 (the surface facing the z2 side in the thickness direction z) and the upper surface of the outer periphery 312 (the surface facing the z2 side in the thickness direction z). The island back surface 31b corresponds to the lower surface of the base 311 (the surface facing the z2 side in the thickness direction z) and the lower surface of the outer periphery 312 excluding the thin-walled portion 313 (the surface facing the z1 side in the thickness direction z). The semiconductor element 1 is mounted on the island main surface 31a. The island back surface 31b is exposed from the resin back surface 22. In the illustrated example, the island back surface 31b is flush with the resin back surface 22. The thickness t311 of the base 311 corresponds to the distance from the island main surface 31a to the island back surface 31b in the thickness direction z.

[0031] The terminal portion 32 is exposed from the sealing portion 2. The terminal portion 32 is a terminal of the semiconductor device A10, and is joined to the circuit board when the semiconductor device A10 is mounted on the circuit board. The terminal portion 32 is a portion of the lead 3 that protrudes from the resin side surface 23 of the sealing portion 2. As shown in FIG. 4, the terminal portion 32 is spaced apart from the island 31. In the illustrated example, the terminal portion 32 is located on the y1 side of the island 31 in the first direction y. As shown in FIG. 12, the terminal portion 32 is located on the z2 side of the island 31 in the thickness direction z. The terminal portion 32 is an example of a "first terminal portion."

[0032] As shown in Figures 4 and 12, the relay portion 33 is connected to the island 31 and the terminal portion 32. The relay portion 33 is interposed between the island 31 and the terminal portion 32. The relay portion 33 is covered by the sealing portion 2. A portion of the relay portion 33 is bent. This connects the island 31 and the terminal portion 32 that are located at different positions in the thickness direction z. The relay portion 33 is an example of a "first relay portion." The lead 3 does not need to include the relay portion 33. In this case, the island 31 and the terminal portion 32 are electrically connected by a conductive member (for example, a metal plate or a bonding wire).

[0033] As shown in FIG. 5 , each of the two extension portions 34 extends outward from the periphery 31 c of the island 31. In this embodiment, each of the two extension portions 34 extends from the edge of the periphery 31 c of the island 31 on the y2 side in the first direction y to the y2 side in the first direction y. Each of the two extension portions 34 is connected to the island 31 and formed integrally therewith. In the illustrated example, each of the two extension portions 34 is rectangular in a plan view, but the planar shape of each extension portion 34 is not limited in any way. The two extension portions 34 are spaced apart from each other. The two extension portions 34 are arranged along the second direction x. When the lead 3 includes three or more extension portions 34, the three or more extension portions 34 are arranged spaced apart from each other along the second direction x. 5 , the two extension portions 34 are connected to a pair of corners 31d of the periphery 31c of the island 31 that are farther from the terminal portion 32 in the first direction y. The two extension portions 34 do not overlap the semiconductor element 1 or the conductive bonding material 19 in a plan view.

[0034] As shown in FIGS. 5 and 10, each of the two extension portions 34 has an extension main surface 34a, an extension back surface 34b, and a plurality of extension side surfaces 34c and 34d.

[0035] As shown in FIG. 10 , the extended main surface 34a and the extended back surface 34b are spaced apart from each other in the thickness direction z. The extended main surface 34a and the extended back surface 34b face opposite each other in the thickness direction z. The extended main surface 34a faces the z2 side in the thickness direction z (upward in the thickness direction z), and the extended back surface 34b faces the z1 side in the thickness direction z (downward in the thickness direction z). As shown in FIG. 10 , the extended main surface 34a is flush with the island main surface 31a. The extended back surface 34b is located closer to the z2 side in the thickness direction z than the island back surface 31b. In this embodiment, a portion of the extended main surface 34a is exposed from the sealing portion 2 due to the recess 26, but the entire extended main surface 34a may be covered by the sealing portion 2. The extended back surface 34b is covered by the sealing portion 2.

[0036] Each of the multiple extending side surfaces 34c, 34d is located between the extending main surface 34a and the extending back surface 34b in the thickness direction z. Each of the multiple extending side surfaces 34c, 34d extends from the extending main surface 34a toward the z1 side in the thickness direction z. The extending side surface 34c faces the extending direction in which the extending portion 34 extends relative to the island 31 (in this embodiment, the y2 side in the first direction y). The extending side surface 34c is sandwiched between a pair of extending side surfaces 34d in the second direction x. The pair of extending side surfaces 34d are individually connected to both end edges of the extending side surface 34c in the thickness direction and in a direction perpendicular to the aforementioned extending direction. The pair of extending side surfaces 34d are spaced apart from each other in the second direction x and face opposite directions in the second direction x. The pair of extending side surfaces 34d are each connected to the extending main surface 34a and the extending back surface 34b. The plurality of extending side surfaces 34c, 34d are each covered with a sealing portion 2.

[0037] As shown in FIG. 10 , the thickness t34 (dimension in the thickness direction z) of each extension portion 34 is smaller than the thickness of the island 31 (thickness t311 of the base portion 311). As shown in FIG. 10 , the thickness t34 of each extension portion 34 corresponds to the distance along the thickness direction z from the extension main surface 34a to the extension back surface 34b. The thickness t34 of each extension portion 34 is smaller than the thickness t313 of the thin-walled portion 313. The thickness t34 of each extension portion 34 is not limited in any way, but is 15% to 75% of the thickness t311 of the base portion 311. In one example, the thickness t34 of each extension portion 34 is 50 μm to 4.8 mm.

[0038] 5 and 10, each of the two extension portions 34 includes a protrusion 341. The protrusion 341 described below is common to both extension portions 34 unless otherwise specified.

[0039] As shown in FIGS. 5 and 10 , the protrusions 341 protrude outward from the island 31 in a plan view. The protrusions 341 protrude from the extending side surface 34c of the corresponding extending portion 34 toward the y2 side in the first direction y. As shown in FIG. 10 , the protrusions 341 are formed on the end of the extending side surface 34c of the corresponding extending portion 34 on the z1 side in the thickness direction z. During the manufacturing process of the semiconductor device A10, each extending portion 34 initially has the same thickness as the base portion 311. By crushing each extending portion 34 that has the same thickness as the base portion 311, each extending portion 34 becomes thinner than the base portion 311. The protrusions 341 are formed by a portion of this crushed portion protruding outward. In a configuration different from the semiconductor device A10, each extending portion 34 may not include the protrusions 341. The protrusion 341 may be formed on the end of the extending side surface 34c of the corresponding extending portion 34 on the z1 side in the thickness direction z as well as on the end on the z2 side in the thickness direction z.

[0040] The width w34 of each extending portion 34 shown in Fig. 5 may be the same as or different from the width w313 of the thin-walled portion 313 shown in Fig. 5. In the present embodiment, the width w34 of each extending portion 34 is the dimension of the extending main surface 34a in the first direction y. The width w313 of the thin-walled portion 313 and the width w34 of each extending portion 34 are not limited in any way, but in one example, the width w34 of each extending portion 34 is 100 µm or more and 1.5 mm or less, and in another example, the width w313 of the thin-walled portion 313 is 100 µm or more and 1 mm or less.

[0041] Research by the present inventors has revealed the following: The larger the width w34 of each extension portion 34, the less thermal stress is applied to the extension portion 34. Similarly, the larger the width w313 of the thin-walled portion 313, the less thermal stress is applied to the thin-walled portion 313. Therefore, in order to reduce the thermal stress applied to the thin-walled portion 313 and each extension portion 34, it is preferable that the width w313 of the thin-walled portion 313 and the width w34 of each extension portion 34 are larger. However, increasing the width w313 of the thin-walled portion 313 reduces the area of ​​the island back surface 31b, which reduces heat dissipation. Increasing the width w313 of the thin-walled portion 313 reduces the planar size of the base portion 311, thereby hindering the expansion of the planar size of the semiconductor element 1. Therefore, there is a limit to how much the width w313 of the thin-walled portion 313 can be increased. On the other hand, increasing the width w34 of each extension portion 34 does not reduce the area of ​​the island back surface 31b, so heat dissipation is hardly reduced. Increasing the width w34 of each extension portion 34 does not reduce the planar size of the base portion 311, so it does not affect the enlargement of the planar size of the semiconductor element 1. Therefore, by increasing the width w34 of each extension portion 34, it is possible to alleviate stress on each extension portion 34 while suppressing a reduction in heat dissipation. However, increasing the width w34 of each extension portion 34 increases the product size (dimension in the first direction y) of the semiconductor device A10. Therefore, the lower limit of the width w34 of each extension portion 34 should be set taking into account the thermal stress on each extension portion 34, and the upper limit should be set according to the specifications (dimension in the first direction y) of the semiconductor device A10.

[0042] The lead 4 is electrically connected to the second electrode 12 of the semiconductor element 1 via the connection member 61. As shown in Fig. 4, the lead 4 includes a pad portion 41, a terminal portion 42, and a relay portion 43. In the lead 4, the pad portion 41, the terminal portion 42, and the relay portion 43 are integrally formed.

[0043] The pad portion 41 is covered by the sealing portion 2. A plurality of connection members 61 are bonded to the pad portion 41. Each connection member 61 is bonded to the upper surface of the pad portion 41 (the surface facing the z2 side in the thickness direction z). The pad portion 41 is located on the z2 side in the thickness direction z of the island 31. In a plan view, the pad portion 41 is disposed on the y1 side of the island 31 in the first direction y.

[0044] The terminal portion 42 is exposed from the sealing portion 2. The terminal portion 42 is a terminal of the semiconductor device A10, and is joined to the circuit board when the semiconductor device A10 is mounted on the circuit board. The terminal portion 42 is spaced apart from the pad portion 41. In the illustrated example, the terminal portion 42 is located on the y1 side in the first direction y relative to the pad portion 41. In the thickness direction z, the terminal portion 42 is arranged at the same position as the pad portion 41. In the illustrated example, the terminal portion 42 is located on the x2 side in the second direction x relative to the terminal portion 32. In the thickness direction z, the terminal portion 42 is arranged at the same position as the terminal portion 32. The terminal portion 42 is an example of a "second terminal portion."

[0045] The relay portion 43 is connected to the pad portion 41 and the terminal portion 42. The relay portion 43 is interposed between the pad portion 41 and the terminal portion 42. The relay portion 43 is covered by the sealing portion 2. In the illustrated example, a through hole is formed in the relay portion 43, but unlike this example, the relay portion 43 does not necessarily have to have a through hole. However, in a configuration in which a through hole is formed, the sealing portion 2 can move through the through hole when the sealing portion 2 is formed. Filling the through hole with the sealing portion 2 can prevent the lead 4 from coming out of the sealing portion 2. The relay portion 43 is an example of a "second relay portion."

[0046] The lead 5 is electrically connected to the third electrode 13 of the semiconductor element 1 via the connection member 62. As shown in Fig. 4, the lead 5 includes a pad portion 51, a terminal portion 52, and a relay portion 53. In the lead 5, the pad portion 51, the terminal portion 52, and the relay portion 53 are integrally formed.

[0047] The pad portion 51 is covered by the sealing portion 2. A connection member 62 is bonded to the pad portion 51. The connection member 62 is bonded to the upper surface of the pad portion 51 (the surface facing the z2 side in the thickness direction z). The pad portion 51 is located on the z2 side in the thickness direction z of the island 31. In a plan view, the pad portion 51 is disposed on the y1 side of the island 31 in the first direction y.

[0048] The terminal portion 52 is exposed from the sealing portion 2. The terminal portion 52 is a terminal of the semiconductor device A10 and is bonded to the circuit board when the semiconductor device A10 is mounted on the circuit board. The terminal portion 52 is a portion of the lead 5 that protrudes from the resin side surface 23 of the sealing portion 2. The terminal portion 52 is spaced from the pad portion 51. In the illustrated example, the terminal portion 52 is located on the y1 side of the pad portion 51 in the first direction y. In the thickness direction z, the terminal portion 52 is located at the same position as the pad portion 51. In the illustrated example, the terminal portion 52 is located on the x1 side of the terminal portion 32 in the second direction x. Therefore, in the second direction x, the terminal portion 32 is located between the terminal portion 42 and the terminal portion 52. The arrangement order of the terminal portions 32, 42, and 52 in the second direction x is not limited to the illustrated example. In the thickness direction z, the terminal portion 52 is located at the same position as the terminal portion 32. Therefore, in the thickness direction z, the terminal portion 32, the terminal portion 42, and the terminal portion 52 are arranged at the same positions as one another.

[0049] The relay portion 53 is connected to the pad portion 51 and the terminal portion 52. The relay portion 53 is interposed between the pad portion 51 and the terminal portion 52. The relay portion 53 is covered by the sealing portion 2. In the illustrated example, a through hole is formed in the relay portion 53, but unlike this example, the relay portion 53 does not necessarily have to have a through hole. However, in a configuration in which a through hole is formed, the sealing portion 2 can move through the through hole when the sealing portion 2 is formed. By filling the through hole with the sealing portion 2, it is possible to prevent the lead 5 from coming out of the sealing portion 2.

[0050] The multiple connection members 61, 62 electrically connect two parts spaced apart from each other. In the illustrated example, the multiple connection members 61, 62 are each bonding wires. The multiple connection members 61, 62 include a metal, and the metal may be, but is not limited to, gold, aluminum, copper, silver, or an alloy containing any of these. The multiple connection members 61, 62 may also be metal plates instead of bonding wires.

[0051] The multiple connection members 61 are bonded to the second electrode 12 and the pad portion 41, establishing electrical continuity between them. Therefore, the second electrode 12 is electrically connected to the lead 4 via the multiple connection members 61. In the illustrated example, the semiconductor device A10 includes four connection members 61, but the number of connection members 61 is not limited in any way. It can be changed as appropriate depending on factors such as the magnitude of the current to be conducted between the second electrode 12 and the lead 4.

[0052] The connection member 62 is joined to the third electrode 13 and the pad portion 51 to establish electrical continuity therebetween. Therefore, the third electrode 13 is electrically connected to the lead 5 via the connection member 62.

[0053] Next, a vehicle V including the semiconductor device A10 will be described with reference to Fig. 15. The vehicle V is, for example, an electric vehicle (EV).

[0054] As shown in FIG. 15 , a vehicle V includes an on-board charger 91, a storage battery 92, and a drive system 93. The on-board charger 91 is supplied with power wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 91 via a wired connection. The on-board charger 91 is configured with a step-up DC-DC converter. As shown in FIG. 15 , the semiconductor device A10 is part of the on-board charger 91 and is used, for example, in the DC-DC converter described above. The voltage of the power supplied to the on-board charger 91 is stepped up by the converter and then supplied to the storage battery 92. The stepped-up voltage is, for example, 600 V.

[0055] The drive system 93 drives the vehicle V. The drive system 93 includes an inverter 931 and a drive source 932. The power stored in the storage battery 92 is supplied to the inverter 931. The power supplied from the storage battery 92 to the inverter 931 is DC power. Alternatively, unlike the power system shown in FIG. 15 , a step-up DC-DC converter may be further provided between the storage battery 92 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931 is electrically connected to the drive source 932. The drive source 932 includes an AC motor and a transmission. When the AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle V. This drives the vehicle V. When driving the vehicle V, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, the inverter 931 is necessary to output AC power whose frequency is appropriately changed so as to correspond to the required rotation speed of the AC motor.

[0056] The functions and effects of the semiconductor device A10 are as follows.

[0057] The semiconductor device A10 includes an island 31 on which a semiconductor element 1 is mounted and an extension 34 extending from a periphery 31c of the island 31. FIG. 16 illustrates a process during the manufacturing of the semiconductor device A10, showing a state in which multiple leads 3-5 are connected to each other by tie bars 70 to form a single lead frame 7. In the state illustrated in FIG. 15, the lead frame 7 is fixed with a clamping member. This is to suppress swinging of the lead frame 7 due to vibrations that occur during transport of the lead frame 7, bonding of the semiconductor element 1, bonding to multiple connecting members 61 and 62, and formation of the sealing portion 2. For example, for the lead frame 7 illustrated in FIG. 15, the clamping member can press a region R1 (shown by a dotted pattern in FIG. 15). In this way, in the semiconductor device A10, the extension 34 ensures a location for fixing with the clamping member, thereby reducing the area in which the clamping member interferes with the island 31. This also suppresses interference between the semiconductor element 1 and the clamp member, making it possible to increase the planar size of the semiconductor element 1 in the semiconductor device A10. For example, the planar size of the semiconductor element 1 can be made the same (or approximately the same) as the planar size of the island 31.

[0058] In the semiconductor device A10, the multiple extending side surfaces 34c, 34d of each extending portion 34 are each covered with the sealing portion 2. This configuration allows the semiconductor device A10 to have an appearance that is the same (or substantially the same) as a conventional TO package. In other words, the semiconductor device A10 allows the size of the semiconductor element 1 in a plan view to be increased without changing the appearance from a conventional one.

[0059] In the semiconductor device A10, the extended rear surface 34b is covered with the sealing portion 2. With this configuration, the leads 3 can be prevented from coming out of the sealing portion 2.

[0060] In the semiconductor device A10, the thickness t34 of each extension portion 34 is smaller than the thickness t311 of the base portion 311 (corresponding to the thickness of the island 31). The extension main surface 34a of each extension portion 34 is flush with the island main surface 31a. In this configuration, even if the island back surface 31b is exposed from the resin back surface 22, the extension back surface 34b of each extension portion 34 is covered by the sealing portion 2. Therefore, the semiconductor device A10 can prevent the island 31 from coming out of the sealing portion 2.

[0061] In the semiconductor device A10, the outer peripheral portion 312 of the island 31 includes a thin portion 313. The thickness t313 of the thin portion 313 is smaller than the thickness t311 of the base portion 311. The lower surface of the thin portion 313 (the surface facing the z1 side in the thickness direction z) is covered with the sealing portion 2. This configuration can prevent the island 31 from coming out of the sealing portion 2.

[0062] In the semiconductor device A10, the island back surface 31b is exposed from the sealing portion 2 (resin back surface 22). In this configuration, the heat dissipation performance for the heat generated from the semiconductor element 1 can be improved.

[0063] In the semiconductor device A10, the extension portions 34 do not overlap the semiconductor element 1 in a planar view. In this configuration, the semiconductor element 1 does not protrude from the island 31 in a planar view. Therefore, the semiconductor device A10 can suppress a decrease in the conduction area between the first electrode 11 of the semiconductor element 1 and the island 31.

[0064] In the semiconductor device A10, each extension 34 extends in the first direction y from the edge of the periphery 31c of the island 31 on the y2 side in the first direction y. When the lead frame 7 is fixed with the clamping member described above, the extension 34 (region R1 in FIG. 15 ) and the vicinity of the tie bar 70 (region R2 in FIG. 15 ) may be pressed. In such a case, the areas pressed by the clamping member can be separated in the first direction y, which is preferable in terms of suppressing swinging of the lead frame 7.

[0065] The semiconductor device A10 includes two extending portions 34 spaced apart from each other. With this configuration, the lead frame 7 can be fixed by clamping both of the extending portions 34 (both of the two regions R1 in FIG. 15 ) with the aforementioned clamping members and by clamping the vicinity of the tie bar 70 (at least one of the three regions R2 in FIG. 15 ). This further suppresses swinging of the lead frame 7 during manufacturing of the semiconductor device A10. In particular, in the semiconductor device A10, the two extending portions 34 are connected to a pair of corners 31d of the periphery 31c of the island 31, as viewed in the thickness direction z, that are farthest from the terminal portion 32 in the first direction y. In this case, the planar area of ​​the three points clamped by the clamping members can be increased. This is advantageous for fixing the lead frame 7, i.e., for suppressing swinging of the lead frame 7 during manufacturing of the semiconductor device A10.

[0066] Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other as long as no technical contradiction occurs.

[0067] 17 shows a semiconductor device A11 according to a first modification of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the following respect: the sealing portion 2 does not include any of the multiple recesses 26.

[0068] 17 , in the semiconductor device A11, the sealing portion 2 does not include any of the multiple recesses 26, and therefore the upper surface of the island 31 (island main surface 31 a) and the upper surfaces of each extension portion 34 (extension main surfaces 34 a) are all covered with the sealing portion 2. Therefore, all of the leads 3 of the semiconductor device A11 except for the terminal portions 32 are covered with the sealing portion 2, and unintended short circuits can be suppressed.

[0069] Similar to the semiconductor device A10, the semiconductor device A11 includes an island 31 on which a semiconductor element 1 is mounted, and an extension 34 extending from a periphery 31c of the island 31. Therefore, similar to the semiconductor device A10, the semiconductor device A11 can suppress interference between the semiconductor element 1 and the clamping member, thereby enabling an increase in the size of the semiconductor element 1 in a plan view. In addition, the semiconductor device A11 has a common configuration with the semiconductor device A10, and thus achieves the same effects as the semiconductor device A10.

[0070] 18 shows a semiconductor device A12 according to a second modification of the first embodiment. The semiconductor device A12 differs from the semiconductor device A10 in the following respect: the island 31 includes a groove 314.

[0071] The groove 314 is recessed from the island main surface 31a. For example, the groove 314 has a rectangular ring shape in a plan view. In a plan view, the groove 314 is formed along the boundary between the base 311 and the outer periphery 312. In a plan view, the groove 314 surrounds the semiconductor element 1 and the conductive bonding material 19. The groove 314 can prevent the conductive bonding material 19 from flowing out. By filling the groove 314 with the sealing portion 2, the adhesion between the sealing portion 2 and the leads 3 is increased.

[0072] Similar to the semiconductor device A10, the semiconductor device A12 includes an island 31 on which a semiconductor element 1 is mounted, and an extension 34 extending from a periphery 31c of the island 31. Therefore, similar to the semiconductor device A10, the semiconductor device A12 can suppress interference between the semiconductor element 1 and the clamping member, thereby enabling an increase in the size of the semiconductor element 1 in a planar view. In addition, the semiconductor device A12 has a configuration in common with the semiconductor devices A10 and A11, and thus achieves the same effects as the semiconductor devices A10 and A11.

[0073] 19 shows a semiconductor device A13 according to a third modification of the first embodiment. The semiconductor device A13 differs from the semiconductor device A10 in the following respect: when viewed in the thickness direction z, the two extension portions 34 are not connected to a pair of corner portions 31 d of the periphery 31 c of the island 31 that are far from the terminal portion 32 in the first direction y.

[0074] In the semiconductor device A13, the extension portion 34 on the x1 side of the second direction x is arranged closer to the x2 side of the second direction x than the semiconductor device A10, and the extension portion 34 on the x2 side of the second direction x is arranged closer to the x1 side of the second direction x than the semiconductor device A10.

[0075] Similar to the semiconductor device A10, the semiconductor device A13 includes an island 31 on which a semiconductor element 1 is mounted, and an extension 34 extending from a periphery 31c of the island 31. Therefore, similar to the semiconductor device A10, the semiconductor device A13 can suppress interference between the semiconductor element 1 and the clamping member, thereby enabling an increase in the size of the semiconductor element 1 in a plan view. In addition, the semiconductor device A13 has a configuration in common with the semiconductor devices A10 to A12, and thus achieves the same effects as the semiconductor devices A10 to A12.

[0076] As can be seen from the semiconductor device A13, in the semiconductor device of the present disclosure, there is no limitation as to whether each extension portion 34 is connected to either of the pair of corner portions 31d of the periphery 31c of the island 31.

[0077] 20 and 21 show a semiconductor device A20 according to the second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in the following respect: two extension portions 34 extend in the second direction x from respective edges of the periphery 31c of the island 31 in the second direction x. For ease of understanding, the periphery 31c of the island 31 is indicated by a thick dashed line in FIG.

[0078] 20 , in the semiconductor device A20, one of the two extending portions 34 (the extending portion 34 on the x1 side in the second direction x) extends from the edge of the periphery 31c on the x1 side in the second direction x to the x1 side in the second direction x. The other of the two extending portions 34 (the extending portion 34 on the x2 side in the second direction x) extends from the edge of the periphery 31c on the x2 side in the second direction x to the x2 side in the second direction x. In the example shown in FIG. 20 , the two extending portions 34 of the semiconductor device A20 are respectively connected to a pair of corners 31d of the periphery 31c of the island 31. Unlike this example, the two extension portions 34 do not have to be connected to a pair of corners 31d of the periphery 31c of the island 31, but may be disposed at the center of each edge of the periphery 31c in the second direction x, or may be connected to a pair of corners of the periphery 31c of the island 31 on opposite sides from the terminal portion 32 in the first direction y. As shown in Fig. 20 , in this embodiment, each extension portion 34 extends in the second direction x relative to the island 31, and therefore the extending side surface 34c of each extension portion 34 faces either side of the second direction x.

[0079] Similar to the semiconductor device A10, the semiconductor device A20 includes an island 31 on which a semiconductor element 1 is mounted, and an extension 34 extending from a periphery 31c of the island 31. Therefore, similar to the semiconductor device A10, the semiconductor device A20 can suppress interference between the semiconductor element 1 and the clamping member, thereby enabling an increase in the size of the semiconductor element 1 in a plan view. In addition, the semiconductor device A20 has a configuration in common with the semiconductor devices A10 to A13, and thus achieves the same effects as the semiconductor devices A10 to A13.

[0080] As can be seen from the semiconductor device A20, in the semiconductor device of the present disclosure, each of the extending portions 34 is not limited to extending from an edge of the periphery 31c of the island 31 in the first direction y, but may extend from an edge in the second direction x. Furthermore, in the semiconductor device of the present disclosure, the multiple extending portions 34 are not limited in any way as long as they each extend from the periphery 31c of the island 31 outward from the island 31. For example, the multiple extending portions 34 may include a mixture of those extending from an edge of the periphery 31c in the first direction y and those extending from an edge in the second direction x.

[0081] 22 shows a semiconductor device A30 according to the third embodiment. The semiconductor device A30 differs from the semiconductor device A10 in the following respect: the number of extension portions 34 is one. That is, the lead 3 of the semiconductor device A30 includes one extension portion 34. For ease of understanding, the periphery 31c of the island 31 is indicated by a thick dashed line in FIG. 21.

[0082] 22 , the extension portion 34 extends from the edge of the periphery 31c of the island 31 on the y2 side in the first direction y. In contrast to this example, the extension portion 34 may extend from the edge of the periphery 31c on the x1 side in the second direction x, or from the edge of the periphery 31c on the x2 side in the second direction x.

[0083] Similar to the semiconductor device A10, the semiconductor device A30 includes an island 31 on which a semiconductor element 1 is mounted, and an extension 34 extending from a periphery 31c of the island 31. Therefore, similar to the semiconductor device A10, the semiconductor device A30 can suppress interference between the semiconductor element 1 and the clamping member, thereby enabling an increase in the size of the semiconductor element 1 in a planar view. In addition, the semiconductor device A30 has a configuration in common with the semiconductor devices A10 to A13, A20, and thus achieves the same effects as the semiconductor devices A10 to A13, A20.

[0084] As can be seen from the semiconductor device A30, in the semiconductor device of the present disclosure, the number of extension portions 34 may be one or more.

[0085] The semiconductor device according to the present disclosure is not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. For example, the semiconductor device according to the present disclosure includes the embodiments described in the following supplementary notes. Supplementary note 1. A semiconductor device comprising: a semiconductor element; an island on which the semiconductor element is mounted; at least one extending portion extending from the periphery of the island when viewed in the thickness direction of the island; and a sealing portion covering the semiconductor element, wherein the at least one extending portion has an extending main surface facing one side in the thickness direction, an extending back surface facing the opposite side to the extending main surface in the thickness direction, and an extending side surface arranged between the extending main surface and the extending back surface in the thickness direction, and the extending side surface is covered by the sealing portion. Supplementary note 2. The semiconductor device according to Supplementary Note 1, wherein the island includes a base portion at least a portion of which overlaps the semiconductor element when viewed in the thickness direction, and an outer periphery portion which surrounds the base portion when viewed in the thickness direction, and the outer periphery portion includes a thin portion whose dimension in the thickness direction is smaller than the dimension in the thickness direction of the base. Supplementary Note 3. The semiconductor device according to Supplementary Note 2, wherein the dimension in the thickness direction of the at least one extension portion is smaller than the dimension in the thickness direction of the thin portion. Supplementary Note 4. The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, wherein the island has an island main surface which faces the same direction as the extending main surface in the thickness direction and on which the semiconductor element is mounted, and the island main surface and the extending main surface are flush with each other. Supplementary Note 5. The semiconductor device according to Supplementary Note 4, wherein the dimension in the thickness direction of the at least one extension portion is smaller than the dimension in the thickness direction of the island. Supplementary Note 6. The semiconductor device according to Supplementary Note 5, wherein the dimension in the thickness direction of the at least one extension portion is smaller than the dimension in the thickness direction of the island. Supplementary Note 7. The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 7, wherein the island has a back surface facing the opposite side to the island main surface in the thickness direction, and the back surface is exposed from the sealing portion.Appendix 9. The semiconductor device according to any one of Appendix 1 to Appendix 8, wherein the at least one extending portion does not overlap the semiconductor element when viewed in the thickness direction. Appendix 10. The semiconductor device according to any one of Appendix 1 to Appendix 9, further comprising a first terminal portion spaced apart from the island and exposed from the sealing portion, the first terminal portion being electrically connected to the semiconductor element. Appendix 11. The semiconductor device according to Appendix 10, wherein the first terminal portion is located on one side of the island in a first direction perpendicular to the thickness direction when viewed in the thickness direction. Appendix 12. The semiconductor device according to Appendix 11, wherein the at least one extending portion extends from an edge of the island opposite the first terminal portion in the first direction when viewed in the thickness direction. Appendix 13. The semiconductor device according to Appendix 11, wherein the at least one extending portion extends from an edge of the island in a second direction perpendicular to the thickness direction and the first direction when viewed in the thickness direction. Appendix 14. The semiconductor device according to any one of Supplementary Notes 11 to 13, wherein the island is rectangular when viewed in the thickness direction, and the at least one extending portion is connected to a corner of the island that is farthest from the first terminal portion in the first direction when viewed in the thickness direction. Supplementary Note 15. The semiconductor device according to any one of Supplementary Notes 10 to 14, further comprising: a second terminal portion spaced apart from the island and the first terminal portion and exposed from the sealing portion, and the second terminal portion being electrically connected to the semiconductor element. Supplementary Note 16. The semiconductor device according to Supplementary Note 15, further comprising: a connection member bonded to the semiconductor element; and a pad portion to which the connection member is bonded, and the second terminal portion being electrically connected to the semiconductor element via the connection member and the pad portion. Supplementary Note 17. 17. The semiconductor device according to claim 16, further comprising: a first relay portion connected to each of the first terminal portions and the island and integrally formed with each of the first terminal portions and the island; and a second relay portion connected to each of the second terminal portions and the pad portion and integrally formed with each of the second terminal portions and the pad portion.Supplementary Note 18. A vehicle comprising: a drive source; a storage battery that stores power to be supplied to the drive source; and an on-board charger that converts power input from an external source and supplies the power to the storage battery, wherein the on-board charger comprises the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 17.

[0086] A10, A11, A12, A13, A20, A30: semiconductor device 1: semiconductor element 10a: element main surface 10b: element back surface 11: first electrode 12: second electrode 13: third electrode 19: conductive bonding material 2: sealing portion 21: resin main surface 22: resin back surface 23: resin side surface 24: resin side surface 25: recess 26: recess 3: lead 31: island 311: base 312: outer periphery 313: thin portion 313a: protrusion 314: groove 31a: island main surface 31b: island back surface 31c: periphery 31d: corner 32: terminal portion 33: relay portion 34: extension portion 34a: extension main surface 34b: extension back surface 34c, 34d: extension side surface 341: protrusion 4: lead 41: Pad portion 42: Terminal portion 43: Relay portion 5: Lead 51: Pad portion 52: Terminal portion 53: Relay portion 61, 62: Connection member 7: Lead frame 70: Tie bar 91: On-board charger 92: Storage battery 93: Drive system 931: Inverter 932: Drive source V: Vehicle

Claims

1. A semiconductor element; an island on which the semiconductor element is mounted; At least one extension portion extending from a periphery of the island when viewed in a thickness direction of the island; a sealing portion that covers the semiconductor element; Equipped with The at least one extension portion has an extension main surface facing one side in the thickness direction, an extension back surface facing the opposite side to the extension main surface in the thickness direction, and an extension side surface arranged between the extension main surface and the extension back surface in the thickness direction, The extending side surface is covered by the sealing portion.

2. the island includes a base portion at least a portion of which overlaps with the semiconductor element when viewed in the thickness direction, and an outer periphery portion that surrounds the base portion when viewed in the thickness direction, 2. The semiconductor device according to claim 1, wherein said outer peripheral portion includes a thin portion whose dimension in said thickness direction is smaller than the dimension in said thickness direction of said base portion.

3. The semiconductor device according to claim 2 , wherein a dimension of said at least one extension portion in said thickness direction is smaller than a dimension of said thin portion in said thickness direction.

4. the island has an island main surface facing the same direction as the extended main surface in the thickness direction and on which the semiconductor element is mounted; The semiconductor device according to claim 1 , wherein said island main surface and said extended main surface are flush with each other.

5. The semiconductor device according to claim 4 , wherein a dimension of said at least one extension in said thickness direction is smaller than a dimension of said island in said thickness direction.

6. The semiconductor device according to claim 5 , wherein the extended rear surface is covered with the sealing portion.

7. the island has an island back surface facing the opposite side to the island main surface in the thickness direction, The semiconductor device according to claim 6 , wherein the back surface of said island is exposed from said sealing portion.

8. the at least one extension portion includes a plurality of extension portions, The semiconductor device according to claim 1 , wherein the plurality of extensions are spaced apart from each other.

9. The semiconductor device according to claim 1 , wherein the at least one extending portion does not overlap the semiconductor element when viewed in the thickness direction.

10. a first terminal portion spaced apart from the island and exposed from the sealing portion; The semiconductor device according to claim 1 , wherein the first terminal portion is electrically connected to the semiconductor element.

11. The semiconductor device according to claim 10 , wherein the first terminal portion is located on one side of the island in a first direction perpendicular to the thickness direction when viewed in the thickness direction.

12. 12 . The semiconductor device according to claim 11 , wherein the at least one extending portion extends from an edge of the island on an opposite side to the first terminal portion in the first direction, as viewed in the thickness direction.

13. 12 . The semiconductor device according to claim 11 , wherein the at least one extending portion extends from an edge of the island in a second direction perpendicular to the thickness direction and the first direction, as viewed in the thickness direction.

14. The island has a rectangular shape when viewed in the thickness direction, The semiconductor device according to claim 11 , wherein the at least one extending portion is connected to a corner portion of the island that is farther from the first terminal portion in the first direction when viewed in the thickness direction.

15. a second terminal portion spaced apart from the island and the first terminal portion and exposed from the sealing portion; The semiconductor device according to claim 10 , wherein the second terminal is electrically connected to the semiconductor element.

16. a connecting member joined to the semiconductor element; a pad portion to which the connection member is joined, The semiconductor device according to claim 15 , wherein the second terminal portion is electrically connected to the semiconductor element via the connection member and the pad portion.

17. a first relay portion connected to each of the first terminal portion and the island and integrally formed with each of the first terminal portion and the island; 17. The semiconductor device according to claim 16, further comprising: a second relay portion connected to each of said second terminal portion and said pad portion and formed integrally with each of said second terminal portion and said pad portion.

18. A driving source; a storage battery that stores power to be supplied to the driving source; an on-board charger that converts power input from an external source and supplies the converted power to the storage battery; Equipped with A vehicle, wherein the on-board charger comprises the semiconductor device according to any one of claims 1 to 17.