Laminated structure, quantum device, and method for producing laminated structure

Abstract

This laminated structure comprises: a cooling member; a wiring substrate which is provided on the cooling member and in which a through hole is formed; a device which is provided on the wiring substrate and which includes a quantum bit; and a joining material which joins the wiring substrate and the device to each other. The joining material has: a portion which is exposed from the through hole at an upper surface of the cooling member; a first joining part which contacts an upper surface of the wiring substrate and a lower surface of the device; and a second joining part which is provided in the periphery of the first joining part in a planar view, and which contacts at least the upper surface of the wiring substrate and the lower surface of the device. The thermal conductivity of the first joining part is higher than the thermal conductivity of the second joining part. The elastic modulus of the second joining part is lower than the elastic modulus of the first joining part. The laminated structure can be used for quantum computing, for example.

Description

Stacked structure, quantum device, and method for manufacturing stacked structure

[0001] The present disclosure relates to a stacked structure, a quantum device, and a method for manufacturing the stacked structure.

[0002] In recent years, research and development of quantum computers using qubits has been underway. For example, a qubit substrate containing qubits is provided on a die that is provided on a printed wiring board. The die is bonded to the printed wiring board with a bonding material. Because qubits operate at extremely low temperatures of around −270°C, not only the qubit substrate but also the laminated structure including the die, bonding material, and printed wiring board is cooled.

[0003] Japanese Patent Application Publication No. 2013-38375, Japanese Patent Publication No. 61-42431, U.S. Patent No. 6,190,941, Japanese Patent Application Publication No. 2007-81064, U.S. Patent Application Publication No. 2002 / 0079573

[0004] In order to maintain the temperature of the quantum bits at extremely low temperatures, it is desirable to efficiently remove heat generated in a device (hereinafter sometimes referred to as a "die") including the quantum bits. When a metal material such as silver is used as a bonding material, it is believed that heat generated in the die is transferred to a wiring substrate, such as a printed wiring board, with high efficiency. However, in this case, there is a large difference in the thermal expansion coefficient between the bonding material, the die, and the printed wiring board, and large thermal stresses due to temperature changes are likely to act on the die. Thermal stress acting on the die may change the characteristics of the circuitry inside the die or cause cracks in the die. To suppress thermal stress, it is possible to use a resin such as epoxy as a bonding material. However, in this case, heat generated in the die is not easily transferred to the printed wiring board, making it difficult to maintain the temperature of the quantum bits at extremely low temperatures. As such, conventional laminate structures are unable to simultaneously improve thermal conductivity and mitigate thermal stress.

[0005] An object of the present disclosure is to provide a stacked structure, a quantum device, and a method for manufacturing a stacked structure that can achieve both improved thermal conductivity and reduced thermal stress.

[0006] According to one embodiment of the present disclosure, there is provided a laminated structure comprising: a cooling member; a wiring substrate provided on the cooling member and having a through hole formed therein; a device including a quantum bit provided on the wiring substrate; and a bonding material bonding the wiring substrate and the device to each other, wherein the bonding material has a portion of an upper surface of the cooling member exposed from the through hole, a first bonding portion contacting the upper surface of the wiring substrate and the lower surface of the device, and a second bonding portion provided around the first bonding portion in a planar view and contacting at least the upper surface of the wiring substrate and the lower surface of the device, wherein the thermal conductivity of the first bonding portion is higher than the thermal conductivity of the second bonding portion, and the elastic modulus of the second bonding portion is lower than the elastic modulus of the first bonding portion.

[0007] According to the present disclosure, it is possible to achieve both improved thermal conductivity and reduced thermal stress.

[0008] FIG. 1 is a plan view showing a stacked structure according to the first embodiment. FIG. 2 is a cross-sectional view showing the stacked structure according to the first embodiment. FIG. 3 is a cross-sectional view (part 1) showing a method for manufacturing a stacked structure according to the first embodiment. FIG. 4 is a cross-sectional view (part 2) showing a method for manufacturing a stacked structure according to the first embodiment. FIG. 5 is a cross-sectional view (part 3) showing a method for manufacturing a stacked structure according to the first embodiment. FIG. 6 is a cross-sectional view (part 4) showing a method for manufacturing a stacked structure according to the first embodiment. FIG. 7 is a cross-sectional view (part 5) showing a method for manufacturing a stacked structure according to the first embodiment. FIG. 8 is a cross-sectional view (part 6) showing a method for manufacturing a stacked structure according to the first embodiment. FIG. 9 is a cross-sectional view showing a quantum device according to a second embodiment.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description may be omitted.

[0010] (First embodiment) A first embodiment will be described. The first embodiment relates to a stacked structure used in a quantum computer. FIG. 1 is a plan view showing the stacked structure according to the first embodiment. FIG. 2 is a cross-sectional view showing the stacked structure according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II in FIG. 1.

[0011] As shown in FIGS. 1 and 2, the laminated structure 1 according to the first embodiment includes a cold plate 10, a printed wiring board 20, a semiconductor chip 30, and a bonding material 40.

[0012] The cold plate 10 has an upper surface 10A and a lower surface 10B. For example, the cold plate 10 is made of metal. The cold plate 10 is an example of a cooling member.

[0013] The printed wiring board 20 is provided on the cold plate 10. The printed wiring board 20 has an upper surface 20A and a lower surface 20B. The printed wiring board 20 has a base 21 and metal pads 22. The base 21 has, for example, a wiring layer and an insulating layer. The metal pads 22 are connected to the wiring layer and are provided on the upper surface 20A of the printed wiring board 20. For example, the metal pads 22 have a gold layer or copper layer on their surfaces. A through hole 25 is formed in the printed wiring board 20. The upper end of the through hole 25 is on the upper surface 20A and the lower end is on the lower surface 20B. The through hole 25 penetrates the metal pad 22. The aspect ratio (depth / diameter) of the through hole 25 is, for example, 1 or less. The printed wiring board 20 is an example of a wiring board.

[0014] The semiconductor chip 30 is provided on the printed wiring board 20. The semiconductor chip 30 includes a quantum bit. In a plan view, the semiconductor chip 30 overlaps with the through-hole 25 formed in the printed wiring board 20. The semiconductor chip 30 has an upper surface 30A and a lower surface 30B. The semiconductor chip 30 has a rectangular planar shape with a side length of approximately 15 mm to 40 mm. The semiconductor chip 30 may also have a square planar shape. The semiconductor chip 30 has a base 31, metal pads 32, and an internal circuit 33. The base 31 includes, for example, silicon. The metal pads 32 are provided on the lower surface 30B of the semiconductor chip 30. For example, the metal pads 32 include a titanium layer and a gold layer covering the titanium layer. A nickel layer may be provided between the titanium layer and the gold layer. The internal circuit 33 is provided within the base 31. The internal circuit 33 constitutes a circuit for controlling quantum bits included in a quantum bit substrate mounted on the semiconductor chip 30, such as an inductor and an antenna. The internal circuit 33 includes a material that becomes a superconductor at a temperature at which the quantum bit operates, for example, a temperature of about −270° C. The semiconductor chip 30 is an example of a device (die), and the semiconductor chip 30 may be provided with transistors and interlayer connection vias.

[0015] The bonding material 40 bonds the printed wiring board 20 and the semiconductor chip 30 to each other. The bonding material 40 has a first bonding portion 41 and a second bonding portion 42. The first bonding portion 41 and the second bonding portion 42 are in contact with each other in a direction perpendicular to the stacking direction of the printed wiring board 20 and the semiconductor chip 30. The thermal conductivity of the first bonding portion 41 is higher than the thermal conductivity of the second bonding portion 42, and the elastic modulus of the second bonding portion 42 is lower than the elastic modulus of the first bonding portion 41.

[0016] The first bonding portion 41 contacts at least a portion of the upper surface 10A of the cold plate 10 exposed from the through-hole 25, the upper surface 20A of the printed wiring board 20, and the lower surface 30B of the semiconductor chip 30. The through-hole 25 is filled with the first bonding portion 41. The first bonding portion 41 has a base 50, a first intermetallic compound layer 51, a second intermetallic compound layer 52, and a third intermetallic compound layer 53. The base 50 occupies the majority of the first bonding portion 41.

[0017] The base 50 contains a metal, such as indium, tin, lead, silver, copper, bismuth, or aluminum, or any combination thereof. For example, the thermal conductivity of the base 50 is 100 W / m·K or more.

[0018] The first intermetallic compound layer 51 is in contact with the upper surface 10A of the cold plate 10. The first intermetallic compound layer 51 is provided between the base 50 and the cold plate 10. For example, the first intermetallic compound layer 51 includes an intermetallic compound of a metal contained in the base 50 and a metal contained in the cold plate 10. The first intermetallic compound layer 51 includes, for example, an In—Au-based intermetallic compound, an In—Sn-based intermetallic compound, an Ag—Sn-based intermetallic compound, a Bi—In-based intermetallic compound, a Sn—Cu-based intermetallic compound, a Ni—Cu-based intermetallic compound, a Ni—Al-based intermetallic compound, a Ni—Sn-based intermetallic compound, or an Au—Sn-based intermetallic compound.

[0019] The second intermetallic compound layer 52 contacts the lower surface 30B of the semiconductor chip 30. More specifically, the second intermetallic compound layer 52 contacts the metal pads 32 of the semiconductor chip 30. The second intermetallic compound layer 52 is provided between the base 50 and the metal pads 32. For example, the second intermetallic compound layer 52 includes an intermetallic compound of a metal contained in the base 50 and a metal contained in the metal pads 32. The second intermetallic compound layer 52 includes, for example, an In—Au-based intermetallic compound, an In—Sn-based intermetallic compound, an Ag—Sn-based intermetallic compound, a Bi—In-based intermetallic compound, a Sn—Cu-based intermetallic compound, a Ni—Cu-based intermetallic compound, a Ni—Al-based intermetallic compound, a Ni—Sn-based intermetallic compound, or an Au—Sn-based intermetallic compound.

[0020] The third intermetallic compound layer 53 is in contact with the upper surface 20A of the printed wiring board 20. More specifically, the third intermetallic compound layer 53 is in contact with the metal pad 22 of the printed wiring board 20. The third intermetallic compound layer 53 is provided between the base 50 and the metal pad 22. For example, the third intermetallic compound layer 53 includes an intermetallic compound of a metal contained in the base 50 and a metal contained in the metal pad 22. The third intermetallic compound layer 53 includes, for example, an In—Au-based intermetallic compound, an In—Sn-based intermetallic compound, an Ag—Sn-based intermetallic compound, a Bi—In-based intermetallic compound, a Sn—Cu-based intermetallic compound, a Ni—Cu-based intermetallic compound, a Ni—Al-based intermetallic compound, a Ni—Sn-based intermetallic compound, or an Au—Sn-based intermetallic compound.

[0021] The second bonding portion 42 is provided around the first bonding portion 41 in a plan view. The second bonding portion 42 contacts at least the upper surface 20A of the printed wiring board 20 and the lower surface 30B of the semiconductor chip 30. The second bonding portion 42 contains a resin. The second bonding portion 42 partially contains, for example, epoxy, polyethylene terephthalate (PET), polyether ether ketone (PEEK), polypropylene (PP), polyimide, or any combination thereof. For example, the elastic modulus of the second bonding portion 42 is 1 GPa or less.

[0022] In a plan view, the outer edge of the first bonding portion 41 becomes smaller as it is further away from the lower surface 30B of the semiconductor chip 30, in other words, as it is closer to the upper surface 20A of the printed wiring board 20. Therefore, in a plan view, the outer edge 41A of the surface of the first bonding portion 41 that contacts the lower surface 30B of the semiconductor chip 30 is located outside the outer edge 41B of the surface of the first bonding portion 41 that contacts the upper surface 20A of the printed wiring board 20. In Figure 2, the side surface of the first bonding portion 41 is schematically shown as a flat inclined surface, but the side surface of the first bonding portion 41 may also have irregularities.

[0023] Next, a method for manufacturing the laminated structure 1 according to the first embodiment will be described. Figures 3 to 8 are cross-sectional views showing the method for manufacturing the laminated structure 1 according to the first embodiment.

[0024] 3, a printed wiring board 20 having a base 21 and metal pads 22 is prepared, and a through hole 25 is formed in the printed wiring board 20. The through hole 25 can be formed by, for example, drilling, laser processing, sandblasting, or the like.

[0025] Next, as shown in FIG. 4 , a first die bond agent 61, which is a bonding member containing metal, is provided on a portion of the metal pad 22 so as to cover the through-hole 25. The first die bond agent 61 can be applied using, for example, a dispenser. The first die bond agent 61 may also be applied by squeegee printing. The first die bond agent 61 contains, for example, indium, tin, lead, silver, copper, bismuth, or aluminum, or any combination thereof. The first die bond agent 61 is provided to a thickness of, for example, 30 μm or more. The first die bond agent 61 is an example of a first bonding member.

[0026] 5, a second die bonding agent 62 containing a thermosetting resin is applied to the portion of the metal pad 22 where the first die bonding agent 61 is not applied. The second die bonding agent 62 is applied around the first die bonding agent 61 in a plan view. The second die bonding agent 62 can be applied using, for example, a dispenser. The second die bonding agent 62 may also be applied by attaching a film. The second die bonding agent 62 contains, for example, epoxy, PET, PEEK, or polyimide, or any combination thereof. The second die bonding agent 62 is applied thinner than the first die bonding agent 61. The second die bonding agent 62 is applied to a thickness of, for example, approximately 10 μm to 20 μm. The second die bonding agent 62 is an example of a second bonding member.

[0027] 6, the semiconductor chip 30 is placed on the first die bonding agent 61. At this time, the metal pads 32 are brought into contact with the first die bonding agent 61.

[0028] Next, the structure shown in FIG. 6 is heated to a temperature at which the first die bonding agent 61 melts or softens and the thermosetting resin contained in the second die bonding agent 62 hardens. As a result, as shown in FIG. 7 , the first die bonding agent 61 flows into the through-hole 25, the semiconductor chip 30 comes into contact with the second die bonding agent 62, and the second die bonding agent 62 thermally hardens to form the second bonding portion 42. That is, the printed wiring board 20 and the semiconductor chip 30 are bonded by the second bonding portion 42. Furthermore, in a plan view, the outer edge 41A of the surface of the first die bonding agent 61 that contacts the bottom surface 30B of the semiconductor chip 30 is positioned outside the outer edge 41B of the surface of the first die bonding agent 61 that contacts the top surface 20A of the printed wiring board 20. For example, if the metal contained in the first die bonding agent 61 is silver and the thermosetting resin contained in the second die bonding agent 62 is epoxy, the heating temperature is approximately 100° C. For example, when the metal contained in the first die bonding agent 61 is indium and the thermosetting resin contained in the second die bonding agent 62 is epoxy, the heating temperature is set to about 120°C.

[0029] 7 is then fixed to the cold plate 10, heated to a temperature at which the first die bond agent 61 melts, held for about 10 seconds, and cooled. As a result, the first bond portion 41 is formed from the first die bond agent 61, and the printed wiring board 20, the semiconductor chip 30, and the cold plate 10 are bonded to each other by the first bond portion 41. At this time, a first intermetallic compound layer 51, a second intermetallic compound layer 52, and a third intermetallic compound layer 53 are formed.

[0030] In this manner, the laminated structure 1 according to the first embodiment can be manufactured.

[0031] In the laminated structure 1, heat generated in the semiconductor chip 30 is transferred to the cold plate 10 mainly via the first bonding portion 41 and then discharged to the outside from the cold plate 10. This improves thermal conductivity. Furthermore, even if there is a large difference in the thermal expansion coefficient between the first bonding portion 41 and the printed wiring board 20, the second bonding portion 42 is provided around the first bonding portion 41 in a plan view, thereby alleviating thermal stress caused by the difference in the thermal expansion coefficient. Thus, according to the first embodiment, it is possible to achieve both improved thermal conductivity and alleviation of thermal stress.

[0032] In particular, in a plan view, the outer edge 41A of the surface of the first bonding portion 41 that contacts the lower surface 30B of the semiconductor chip 30 is located outside the outer edge 41B of the surface of the first bonding portion 41 that contacts the upper surface 20A of the printed wiring board 20, which makes it easier for the first bonding portion 41 to remove heat from the semiconductor chip 30 and for the second bonding portion 42 to relieve thermal stress. The angle formed by a line passing through a first point on the outer edge 41A and a second point on the outer edge 41B closest to the first point and the lower surface 30B of the semiconductor chip 30 is preferably 20° to 80°, more preferably 30° to 70°, and even more preferably 40° to 60°. If this angle is excessively large or small, it may be difficult to achieve both improved thermal conductivity and thermal stress relief.

[0033] Furthermore, since indium becomes a superconductor at extremely low temperatures, indium, when used as the metal contained in the first junction 41, is suitable for improving the stability of the operation of the quantum bit.

[0034] Furthermore, the formation of the first intermetallic compound layer 51 provides excellent adhesion between the first bonding portion 41 and the cold plate 10, resulting in good thermal conductivity. The formation of the second intermetallic compound layer 52 provides excellent adhesion between the first bonding portion 41 and the semiconductor chip 30, resulting in good thermal conductivity. The formation of the third intermetallic compound layer 53 provides excellent adhesion between the first bonding portion 41 and the printed wiring board 20. However, the first intermetallic compound layer 51, the second intermetallic compound layer 52, and the third intermetallic compound layer 53 do not necessarily have to be formed.

[0035] Furthermore, when the thickness of the second die bonding agent 62 is 10 μm to 20 μm, air bubbles are less likely to be trapped in the bonding material 40, and thermal stress can be more easily alleviated.

[0036] A metal layer containing gold, tin, bismuth, copper, silver, or any combination thereof may be formed on the inner wall surface of the through hole 25. In this case, the wettability and adhesion of the first die bonding agent 61 can be improved.

[0037] A plurality of through holes 25 may be formed in the printed wiring board 20 .

[0038] Second Embodiment Next, a second embodiment will be described. The second embodiment relates to a quantum device including the stacked structure 1 according to the first embodiment. Fig. 9 is a cross-sectional view showing the quantum device according to the second embodiment.

[0039] As shown in Figure 9, the quantum device 2 according to the second embodiment includes a stacked structure 1, a quantum bit substrate 70, and a refrigerator 80. The quantum bit substrate 70 includes a quantum bit. The quantum bit is, for example, a color center in diamond. The quantum bit substrate 70 is flip-chip mounted to the semiconductor chip 30 of the stacked structure 1 via a conductive bonding material 71. The stacked structure 1 and the quantum bit substrate 70 are then housed in the refrigerator 80. The refrigerator 80 cools the stacked structure 1 and the quantum bit substrate 70 to an extremely low temperature of approximately -270°C.

[0040] In the quantum device 2 , the heat generated in the semiconductor chip 30 is transferred to the cold plate 10 with high efficiency and is then discharged into the refrigerator 80 .

[0041] The layered structures and quantum devices according to the present disclosure can be used, for example, in quantum computing.

[0042] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0043] 1: Laminated structure 2: Quantum device 10: Cold plate 20: Printed wiring board 22: Metal pad 25: Through hole 30: Semiconductor chip 32: Metal pad 40: Bonding material 41: First bonding portion 41A, 41B: Outer edge 42: Second bonding portion 50: Base 51: First intermetallic compound layer 52: Second intermetallic compound layer 53: Third intermetallic compound layer 61: First die bond agent 62: Second die bond agent 70: Quantum bit substrate 80: Refrigerator

Claims

1. A cooling member; a wiring substrate provided on the cooling member and having a through hole formed therein; a device including a quantum bit provided on the wiring substrate; a bonding material that bonds the wiring board and the device together; and The bonding material is a first bonding portion in contact with a portion of the upper surface of the cooling member exposed through the through hole, an upper surface of the wiring substrate, and a lower surface of the device; a second bonding portion provided around the first bonding portion in a plan view and in contact with at least an upper surface of the wiring substrate and a lower surface of the device; and the thermal conductivity of the first joint portion is higher than the thermal conductivity of the second joint portion; A laminated structure, characterized in that the elastic modulus of the second joint portion is lower than the elastic modulus of the first joint portion.

2. The laminated structure according to claim 1, characterized in that, in a planar view, the outer edge of the surface of the first bonding portion that contacts the lower surface of the device is outside the outer edge of the surface of the first bonding portion that contacts the upper surface of the wiring substrate.

3. The laminated structure according to claim 1 or 2, wherein the first bonding portion contains a metal.

4. 4. The laminated structure according to claim 3, wherein the metal is indium.

5. The laminated structure according to claim 3 , wherein the first joint portion has a first intermetallic compound layer in contact with the upper surface of the cooling member.

6. 4. The laminated structure according to claim 3, wherein the first joint portion has a second intermetallic compound layer in contact with the bottom surface of the device.

7. The laminated structure according to claim 1 or 2, wherein the second bonding portion contains a resin.

8. 3. The laminated structure according to claim 1, wherein the device has a circuit containing a material that becomes a superconductor.

9. The laminated structure according to claim 1 or 2; a qubit substrate mounted on the device; A quantum device comprising:

10. forming a through hole in the wiring substrate; providing a first bonding member on the wiring substrate so as to cover the through hole; providing a second bonding member around the first bonding member on the wiring substrate; flowing the first bonding material into the through hole while bonding the quantum bit-including device and the wiring substrate together with the second bonding material; a step of fixing the wiring substrate to a cooling member and bonding the device and the cooling member to each other by the first bonding member flowing into the through-hole; and a thermal conductivity of a first joint portion formed from the first joint member is higher than a thermal conductivity of a second joint portion formed from the second joint member; A method for manufacturing a laminated structure, characterized in that the elastic modulus of the second joint portion is lower than the elastic modulus of the first joint portion.

11. the first bonding member contains a metal, The method for manufacturing a laminated structure according to claim 10, wherein the second bonding member contains a thermosetting resin.