Semiconductor device, power conversion device, and method of manufacturing the semiconductor device

Abstract

Electrode melting is suppressed even when high voltages are applied. A semiconductor device related to the technology disclosed in the Description of the present application comprises: in a cell region, at least one first trench formed reaching into a drift layer from the upper surface of a base region; in a terminal region that surrounds the cell region in plan view, a second trench formed reaching into the drift layer from the upper surface of the base region; a source region; a source electrode; and a drain electrode. A first gate electrode and a second gate electrode are electrically connected, and the depth of the second trench is greater than the depth of the first trench.

Description

Semiconductor device, power conversion device, semiconductor device manufacturing method, and power conversion device manufacturing method

[0001] The technology disclosed in this specification relates to semiconductor technology.

[0002] A semiconductor device using a silicon carbide (SiC) substrate (hereinafter referred to as an "SiC semiconductor device") has superior voltage resistance and heat resistance compared to a semiconductor device using a silicon (Si) substrate (hereinafter referred to as an "Si semiconductor device").

[0003] In order to increase the breakdown voltage of semiconductor devices, reduce loss, or enable use in high-temperature environments, SiC semiconductor devices have conventionally been applied to power semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs).

[0004] SiC has a higher breakdown field strength than Si. Therefore, the SiC semiconductor device can have a thinner breakdown voltage layer (drift layer) than a Si semiconductor device to achieve the same breakdown voltage. Furthermore, the SiC semiconductor device can have a higher impurity doping amount in the breakdown voltage layer than a Si semiconductor device.

[0005] For these reasons, SiC semiconductor devices have a significantly smaller on-resistance than Si semiconductor devices. For example, the on-resistance of a SiC-MOSFET with a breakdown voltage of 1 kV or more and 1.2 kV or less is 5 mΩcm. ２ This is less than half the on-resistance of a Si-MOSFET or Si-IGBT with the same breakdown voltage.

[0006] In the future, with the reduction in manufacturing costs, improvements in process technology, and other performance improvements, it is expected that the majority of Si-IGBTs used as inverter components will be replaced by SiC semiconductor devices.

[0007] Currently, trench gate type SiC-MOSFETs or SiC-IGBTs are being developed to reduce losses during current flow in SiC semiconductor devices.

[0008] However, trench gate SiC-MOSFETs or SiC-IGBTs have a problem in that an electric field concentrates at the corners of the bottom of the trench in the cell region, destroying the gate insulating film.

[0009] In this regard, for example, Patent Document 1 discloses a method of forming a p-type diffusion layer surrounding the trench bottom to reduce the electric field at the trench bottom, which can suppress the electric field concentration at the trench bottom and prevent the gate insulating film from being destroyed.

[0010] Japanese Patent Application Laid-Open No. 2007-173319

[0011] In trench-gate SiC-MOSFETs or SiC-IGBTs, when switching is performed under conditions of high current and high voltage, the gate insulating film breaks down at the electric field concentration point at the bottom of the trench in the cell region, and energy is concentrated at the breakdown point, generating heat and melting the electrodes. This melting then causes molten metal to adhere to the measuring device, requiring maintenance of the measuring device and making it difficult to measure other chips.

[0012] The structure shown in Patent Document 1 makes the gate insulating film less susceptible to destruction, but the electric field concentrates at the bottom of the trench in the cell region, so if the chip is destroyed, energy concentrates at the destruction point, generating heat and melting the electrodes.

[0013] The technology disclosed in the present specification has been made in consideration of the problems described above, and is a technology that can suppress melting of electrodes even when a high voltage is applied.

[0014] A semiconductor device according to a first aspect of the technology disclosed in the present specification includes a SiC substrate of a first conductivity type, a drift layer of the first conductivity type formed on an upper surface of the SiC substrate, a base region of a second conductivity type different from the first conductivity type formed in a surface layer of the drift layer, at least one first trench formed in a cell region from an upper surface of the base region to reach into the drift layer, a second trench formed in a termination region surrounding the cell region in a plan view from the upper surface of the base region to reach into the drift layer, and two trenches partially formed in the surface layer of the base region on either side of the first trench. The semiconductor device comprises a source region of one conductivity type, a first gate electrode formed in the first trench and surrounded by a gate insulating film, at least one second gate electrode formed in the second trench and surrounded by a gate insulating film, an interlayer insulating film formed to cover the first gate electrode and the second gate electrode, a source electrode formed in contact with the source region, and a drain electrode formed on the lower surface of the SiC substrate, which is the surface opposite to the upper surface, wherein the first gate electrode and the second gate electrode are electrically connected, and the depth of the second trench is deeper than the depth of the first trench.

[0015] According to at least a first aspect of the technology disclosed in the present specification, when a high voltage is applied, the electric field at the bottom of the second trench in the termination region becomes larger than the electric field at the bottom of the first trench in the cell region, which makes breakdown of the gate insulating film more likely to occur in the termination region and relatively less likely to occur in the cell region where a large current flows, thereby suppressing heat generation at the breakdown site and, as a result, suppressing electrode melting.

[0016] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below.

[0017] 17 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment. FIG. 18 is a flowchart showing an example of a manufacturing process for a SiC semiconductor device according to an embodiment. FIG. 19 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to an embodiment. FIG. 20 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to an embodiment. FIG. 21 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to an embodiment. FIG. 22 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to an embodiment. FIG. 23 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to an embodiment. FIG. 24 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to an embodiment. FIG. 25 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to an embodiment. FIG. 26 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to an embodiment. FIG. 27 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to an embodiment. FIG. 28 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to an embodiment. 1 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment; FIG. 2 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment; FIG. 3 is a diagram combining a plan view and a cross-sectional view showing an example of a manufacturing process of a SiC semiconductor device according to an embodiment; FIG. 4 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment; FIG. 5 is a cross-sectional view showing an example of the manufacturing process of a SiC semiconductor device according to an embodiment; FIG. 6 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment; FIG. 7 is a cross-sectional view showing an example of the manufacturing process of a SiC semiconductor device according to an embodiment; FIG. 8 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to an embodiment; FIG. 9 is a diagram conceptually showing an example of the configuration of a power conversion system including a power conversion device according to an embodiment.

[0018] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0019] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0020] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0021] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0022] Furthermore, in the description of this specification, even if ordinal numbers such as "first" or "second" are used, these terms are used for convenience to make it easier to understand the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0023] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0024] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude the interposition of another component "C" between A and B.

[0025] First Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described below.

[0026] <Configuration of the Semiconductor Device> Fig. 1 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment. The SiC semiconductor device shown in Fig. 1 is an example of a SiC-n-type MOSFET with a trench gate structure, and shows a cell region 11 and a termination region 12 of the main part of the SiC semiconductor device.

[0027] Although the following description will be given for a SiC n-type MOSFET, the present invention can also be applied to a SiC p-type MOSFET or a SiC IGBT. The overall configuration of the SiC semiconductor device is a continuous configuration of the main cell region 11 shown in Figure 1. The larger the magnitude of the current flowing through the SiC semiconductor device, the larger the proportion of the cell region 11 in the overall configuration of the SiC semiconductor device.

[0028] As shown in FIG. 1 , the SiC semiconductor device includes an n-type SiC substrate 1, an n-type drift layer 2 formed on the upper surface of the n-type SiC substrate 1, a p-type base region 3 formed in a surface layer of the n-type drift layer 2, a plurality of trenches 102 formed in a cell region 11 from the upper surface of the p-type base region 3 to reach the n-type drift layer 2, a trench 104 formed in a termination region 12 surrounding the cell region 11 in a plan view from the upper surface of the p-type base region 3 to reach the n-type drift layer 2, a p-type base region 5 formed on a bottom surface of the trench 102 facing the n-type drift layer 2, a p-type base region 5 formed on a bottom surface of the trench 104 facing the n-type drift layer 2, and n-type source regions 4 partially formed on either side of the trench 102 in the surface layer of the p-type base region 3. a gate insulating film 6 formed inside the trench 102 in contact with the side and bottom surfaces, in contact with a part of the upper surface of the p-type base region 3, and in contact with the side and bottom surfaces inside the trench 104; a gate electrode 7 formed inside the trench 102 and surrounded by the gate insulating film 6; a gate electrode 70 formed inside the trench 104 and surrounded by the gate insulating film 6; a gate electrode 71 formed inside the trench 104 and surrounded by the gate insulating film 6 but spaced apart from the gate electrode 70; an interlayer insulating film 8 formed to cover the gate electrode 7, the gate electrode 70, and the gate electrode 71; a source electrode 9 formed to cover the interlayer insulating film 8, the p-type base region 3, and the n-type source region 4; and a drain electrode 10 formed on the lower surface (the surface opposite to the upper surface) of the n-type SiC substrate 1.

[0029] Here, the depth of the groove 104 is formed to be deeper than the depth of the groove 102 .

[0030] Fig. 2 is a flowchart showing an example of a manufacturing process for a SiC semiconductor device according to this embodiment. Also, Figs. 3 to 14 are cross-sectional views showing an example of a manufacturing process for a SiC semiconductor device according to this embodiment. The SiC semiconductor device shown in Fig. 1 is manufactured according to the manufacturing process shown in Fig. 2.

[0031] First, as shown in an example in FIG. 3 , an n-type drift layer 2 made of n-type SiC is formed as an epitaxial film on a first main surface (hereinafter referred to as the upper surface) of an n-type SiC substrate 1 (step ST1).

[0032] 4, a mask (not shown) made of resist or the like is formed, and then p-type impurities are ion-implanted into the surface layer of the n-type drift layer 2 to form p-type base regions 3 in the surface layer of the n-type drift layer 2 (step ST2). Examples of p-type impurities include boron (B) and aluminum (Al).

[0033] 5, a resist mask 13 is formed on each of the p-type base regions 3, and then n-type impurities are ion-implanted into the surface layers of the p-type base regions 3 to form n-type source regions 4 in the surface layers of the p-type base regions 3 (step ST3). Examples of n-type impurities include phosphorus (P) and nitrogen (N).

[0034] Thereafter, the SiC wafer is heat-treated at high temperature in a heat treatment device (not shown) to activate the p-type base region 3 and the n-type source region 4. As a result, the p-type ions implanted in the p-type base region 3 and the n-type ions implanted in the n-type source region 4 are electrically activated.

[0035] Next, as shown in an example in FIG. 6, a mask 14 is formed using resist for the cell region, and then trench-type grooves 102 for the cell region are formed on the upper surfaces of the p-type base region 3 and the n-type source region 4 by dry etching using plasma or the like (step ST4).

[0036] 7, a mask 15, which is different from the mask 14, is formed from a resist for the termination region, and then trench-type grooves 104 for the termination region are formed in the upper surface of the p-type base region 3 by dry etching using plasma or the like. The depth of the grooves 104 is formed to be deeper than the depth of the grooves 102.

[0037] If it is not possible to provide a mask capable of forming the trench 102 in the cell region 11 or the trench 104 in the termination region 12, a deeper trench can be formed by depositing an oxide film made of, for example, TEOS on the upper surface of the p-type base region 3 in Figure 5 and dry etching the oxide film with a resist mask.

[0038] 8, in order to reduce the electric field applied to the bottom of the trench gate, a p-type base region 5 may be formed at the bottom of the grooves 102 and 104. Examples of p-type impurities include boron (B) and aluminum (Al).

[0039] Next, in order to remove plasma damage that may have occurred during the formation of the trench gate, the top and side surfaces of the structure shown in FIG. 8 are oxidized using thermal oxidation.

[0040] To remove plasma damage, it is desirable to increase the amount of oxidation on the top and side surfaces of the structure shown in FIG. 8 . However, this thermal oxidation reduces the impurity layer (p-type base region 3, n-type source region 4, and p-type base region 5) formed in the surface layer of the n-type drift layer 2. Therefore, it is sufficient to thermally oxidize the surface layer of the SiC n-type drift layer 2 to a thickness of, for example, 20 nm or more and 80 nm or less, more preferably, to a thickness of, for example, 30 nm or more and 70 nm or less. The inventors confirmed that plasma damage caused by thermal oxidation to this thickness was sufficiently removed when forming the trench gate by measuring the leakage current between the gate electrode 7 and the source electrode 9.

[0041] Next, as shown in FIG. 9, a gate insulating film 6 is formed by a deposition method such as thermal oxidation or chemical vapor deposition (step ST5).

[0042] Next, as shown in FIG. 10, an electrode layer 72 is formed on the upper surface of the gate insulating film 6 so as to fill the grooves 102 and 104 (step ST6).

[0043] 11 , the electrode layer 72 is patterned to remove excess portions of the electrode layer 72. Here, highly anisotropic etching, such as dry etching using plasma, is used to etch the electrode layer 72. By performing highly anisotropic etching, the gate electrode 7 is formed inside the groove 102 that becomes the trench, the gate electrode 70 (a separate gate electrode formed separate from the inner circumferential side surface of the groove 104) is formed directly below the mask 16 formed in the termination region, and the gate electrode 71 (a contact gate electrode formed in contact with the inner circumferential side surface of the groove 104) is formed at a location in the termination region adjacent to the cell region.

[0044] Figure 12 shows a combination of a schematic plan view and a cross-sectional view of the structure shown in Figure 11. As shown in the example of Figure 12, the gate electrode 7 in the trench 102, the gate electrode 70 immediately below the mask 16 formed in the termination region, and the gate electrode 71 in the termination region adjacent to the cell region are all connected.

[0045] Next, the interlayer insulating film 8 is formed by chemical vapor deposition (CVD). Thereafter, as shown in FIG. 13, patterning is performed by photolithography and etching to remove the remaining portion of the interlayer insulating film 8 together with the gate insulating film 6 (step ST7).

[0046] The corners of the interlayer insulating film 8 can be rounded by introducing impurities such as B (boron) or P (phosphorus). As described above, the interlayer insulating film 8 is formed by deposition and patterning. The deposited material is, for example, silicon nitride (SixNy) or silicon oxide (SiO ２ ) and the thickness of interlayer insulating film 8 is preferably, for example, not less than 0.5 μm and not more than 2.0 μm.

[0047] Next, as shown in FIG. 14, a source electrode 9 is formed using a barrier metal made of aluminum, an aluminum alloy made of aluminum and silicon, an aluminum alloy made of aluminum and copper, or nickel, etc., and an appropriate barrier metal made of titanium or a titanium compound such as titanium nitride (TiN) (step ST8).

[0048] Thereafter, if necessary, the n-type SiC substrate 1 is thinned by machining a second main surface (hereinafter referred to as the lower surface), which is the surface opposite to the first main surface of the n-type SiC substrate 1 of the SiC semiconductor device, using a grinding wheel (step ST9).

[0049] Then, a nickel film of about 600 nm is formed on the lower surface of n-type SiC substrate 1 by appropriately using a sputtering method or the like to form drain electrode 10 (step ST10). As a result, a SiC semiconductor device having a structure such as that shown in FIG.

[0050] In addition, the upper surface of the nickel film that will become the drain electrode 10 will be oxidized, which will reduce the wettability of the solder alloy and nickel, resulting in a poor bonding condition during chip bonding. Therefore, a protective film made of a metal that is poorly reactive with the outside, such as gold or silver, can be formed on the upper surface of the nickel film, and a laminated film made of the nickel film and gold or silver can be used as the drain electrode 10.

[0051] FIG. 15 is a cross-sectional view schematically showing an example of a current path when a current is passed through the SiC semiconductor device according to this embodiment.

[0052] In Figure 15, a solid line A shows the path of current when a voltage equal to or higher than the threshold voltage, which is a guideline for the voltage at which current begins to flow in the SiC semiconductor device, is applied to gate electrode 7 so that the potential of source electrode 9 becomes higher than the potential of drain electrode 10.

[0053] 15 , the current flowing across the entire electrode surface of drain electrode 10 is concentrated in n-type source region 4 on the top surface side of the SiC semiconductor device. As a result, on the top surface side of the SiC semiconductor device, the current flows only in cell region 11, and no current flows in termination region 12.

[0054] When the difference between the potential of the source electrode 9 and the potential of the drain electrode 10 becomes large and the electric field of the gate insulating film 6 reaches the breakdown electric field, the gate insulating film 6 is destroyed. If the destruction location of the gate insulating film 6 is in the cell region 11, the area is a location where current flows, so the amount of heat generated at the time of destruction is large and the gate electrode 7 melts. On the other hand, if the destruction location of the gate insulating film 6 is in the termination region 12, the area is a location where no current flows, so the amount of heat generated at the time of destruction is small and melting of the gate electrode 7 is suppressed.

[0055] Fig. 16 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment. Fig. 17 is a schematic diagram showing the electric field distribution in the B-B' cross section and the C-C' cross section in Fig. 16. In Fig. 17, the vertical axis represents the electric field, and the horizontal axis represents the depth. In Fig. 17, the electric field distribution in the B-B' cross section is shown by a dotted line, and the electric field distribution in the C-C' cross section is shown by a solid line.

[0056] In FIG. 16, the distance between the bottom of the groove 102 in the cell region 11 and the lower surface of the n-type drift layer 2 is L １ The distance between the bottom of the trench 104 in the termination region 12 and the lower surface of the n-type drift layer 2 is L ２ In this case, L １ >L ２ That is, of the grooves 102 and 104 similarly formed on the upper surface of the p-type base region 3, the groove 104 is deeper than the groove 102.

[0057] 17, if the electric field applied to the bottom of trench 102 in cell region 11 is E1 and the electric field applied to the bottom of trench 104 in termination region 12 is E2, then E1<E2.

[0058] Therefore, since the gate insulating film 6 in the termination region 12 reaches the breakdown field at a voltage lower than that of the gate insulating film 6 in the cell region 11, in the SiC semiconductor device according to this embodiment, the gate insulating film 6 is always broken down in a portion where no current flows. This reduces the amount of heat generated at the time of breakdown, and makes it possible to suppress melting of the gate electrode 7.

[0059] When the operating voltage resistance of the SiC semiconductor device is V1, the gate insulating film 6 must not be broken down at a voltage lower than V1. For this reason, when the impurity concentration of the n-type drift layer 2 is N1, the dielectric breakdown field of the gate insulating film 6 is Ec, the elementary charge is q, and the dielectric constant of SiC is εc, Gauss's law dictates that V1<Ec×L ２ -(q×N1 / εc)×L ２ ×L ２ Satisfying L ２ The value must be set to L. ２ If is too short (too small), the above formula will not be satisfied.

[0060] Second Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0061] <Configuration of the Semiconductor Device> Compared to the first embodiment, even if the trench 102 in the cell region 11 and the trench 104 in the termination region 12 are processed in the same process, the L １ >L ２ A method for manufacturing a SiC semiconductor device that can achieve the above will be described.

[0062] First, steps ST1 to ST3 are performed in the same manufacturing process as in the first embodiment, thereby forming the structure shown in FIG.

[0063] Next, a resist mask 17 is formed in cell region 11 and termination region 12. Thereafter, as shown in Fig. 18, trench 102 in cell region 11 and trench 104 in termination region 12 are formed in the same process by dry etching using plasma or the like (step ST4). Fig. 18 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to this embodiment.

[0064] Here, the same dry etching process is used to １ >L ２To achieve this, if the width (width in a plan view) of the bottom of the groove 102 in the cell region 11 is W1 and the width (width in a plan view) of the bottom of the groove 104 in the termination region 12 is W2, the mask pattern of the mask 17 is formed so that W1 < W2.

[0065] The wider the width of the bottom of the groove, the easier it is for the etching gas to react. Therefore, if W1 < W2, the L １ >L ２ The groove 102 in the cell region 11 and the groove 104 in the termination region 12 can be formed in one step.

[0066] As in the first embodiment, if it is not possible to provide a mask capable of forming the trench 102 in the cell region 11 or the trench 104 in the termination region 12, a deeper trench can be formed by depositing an oxide film made of, for example, TEOS on the upper surface of the p-type base region 3 in Figure 5 and dry-etching the oxide film with a resist mask.

[0067] According to the manufacturing method described above, it is possible to form the structure shown in Fig. 7 of the first embodiment. Thereafter, as shown in Fig. 8, p-type base regions 5 may be formed at the bottoms of the trenches 102 and 104 in order to reduce the electric field applied to the bottoms of the trench gates. Examples of p-type impurities include boron (B) and aluminum (Al).

[0068] Then, by going through the same steps as steps ST5 to ST10 shown in the first embodiment, a SiC semiconductor device having a structure such as that shown in FIG. 1 is formed.

[0069] The manufacturing method of this embodiment makes it possible to omit the steps of forming a resist mask, dry etching, and resist washing, which are required to form groove 104 in termination region 12, as compared to the first embodiment. This allows the SiC semiconductor device to be manufactured at low manufacturing costs.

[0070] Here, when the trench 102 in the cell region 11 and the trench 104 in the termination region 12 are formed in the same process using the manufacturing method of this embodiment, the L １ and the length of L ２ It is difficult to control both the length of the short L. ２ = V1 < Ec × L ２ -(q×N1 / εc)×L ２ ×L ２ It is necessary to control the process conditions such as the type of gas, pressure, or temperature of the dry etching so as to achieve the desired V1.

[0071] L ２ = V1 < Ec × L ２ -(q×N1 / εc)×L ２ ×L ２ If W1<W2 is satisfied, the desired V1 is realized and L １ >L ２ It is possible to manufacture a SiC semiconductor device having the above structure.

[0072] Third Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0073] <Regarding the configuration of the semiconductor device> In comparison with the first embodiment, a SiC semiconductor device will be described in which, where α is the angle between the bottom surface and the side surface of groove 104A in termination region 12, 90°<α is satisfied; and further, where A is the depth of groove 104A in termination region 12 formed to surround cell region 11 in a planar view, and B is the distance between outermost groove 102 in cell region 11 and groove 104A in termination region 12, and β=arctan(B / A), the condition for groove 104A to be formed spaced apart from outermost groove 102 in cell region 11 satisfies 90°<α<90°+β.

[0074] First, steps ST1 to ST3 are performed in the same manufacturing process as in the first embodiment, thereby forming the structure shown in FIG.

[0075] Next, as shown in FIG. 6, a mask 14 is formed using a resist for the cell region, and then trench-type grooves 102 in the cell region are formed by dry etching using plasma or the like (step ST4).

[0076] Next, a resist mask 18 is formed in cell region 11 and termination region 12. Mask 18 has an inclined surface 18A at a position corresponding to the boundary between termination region 12 and cell region 11. Thereafter, as shown in an example in Figure 19, groove 104A is formed in termination region 12 by dry etching using plasma or the like. Here, Figure 19 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to this embodiment.

[0077] Groove 104A has sloped side surfaces corresponding to sloped surface 18A. Specifically, groove 104A can be formed such that the angle α between the bottom and side surfaces of groove 104A in termination region 12 satisfies the following relationship: 90°<α<90°+β.

[0078] As in the first embodiment, if it is not possible to provide a mask capable of forming the groove 102 in the cell region 11 or the groove 104A in the termination region 12, a deeper groove can be formed by depositing an oxide film made of, for example, TEOS on the upper surface of the p-type base region 3 in Figure 5 and dry etching the oxide film with a resist mask.

[0079] When forming the oxide film mask, the use of a sloped mask 18 allows the oxide film mask to also be sloped. Thereafter, p-type base regions 5 may be formed at the bottoms of the grooves 102 and 104 to reduce the electric field applied to the bottoms of the trench gates. Examples of p-type impurities include boron (B) and aluminum (Al).

[0080] Then, by undergoing the same processes as steps ST5 to ST10 shown in the first embodiment, a SiC semiconductor device that satisfies 90°<α<90°+β is formed, as shown in Fig. 20. Here, Fig. 20 is a cross-sectional view showing an example of the configuration of the SiC semiconductor device according to this embodiment.

[0081] In the SiC semiconductor device of this embodiment, compared to the first embodiment, the angle α between the bottom and side of the groove 104A in the termination region 12 is larger than 90°, so that the electric field concentrating at the corners on the inner periphery of the groove 104 can be alleviated.

[0082] The electric field applied to the corner of gate electrode 71A in contact with the side surface of trench 104A in termination region 12 can be approximately considered as an electric field due to a circular electrode.

[0083] 21 is a cross-sectional view showing an example of the configuration of a SiC semiconductor device according to this embodiment. As shown in the example in FIG. 21 , considering a circular electrode of radius R that passes through the perpendicular bisector of the bottom of gate electrode 71A, which contacts the side surface of trench 104A in termination region 12, and that is in contact with the bottom and sidewall of trench 104A, and where V2 is the potential difference between source electrode 9 and drain electrode 10, Gauss's law determines the magnitude of the electric field as E∝V2 / R, so that the larger R, the smaller the electric field. Furthermore, since the relationship between α and R is R / (d / 2)=tan(α / 2), the larger α, the smaller the electric field.

[0084] As a result, the electric field applied to the gate insulating film 6 becomes smaller as α increases, and therefore breakdown of the gate insulating film 6 is suppressed.

[0085] Fourth Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0086] <Regarding the configuration of the semiconductor device> In comparison with the first embodiment, a SiC semiconductor device will be described that is capable of controlling the distance between the gate electrode 70 formed in the trench 104 in the termination region 12 that is formed to surround the cell region 11 in a planar view and the side surface of the trench 104.

[0087] First, steps ST1 to ST6 are performed in the same manufacturing process as in the first embodiment, thereby forming the structure shown in FIG.

[0088] Next, in order to remove the portion of gate electrode 71 in contact with the side surface of trench 104, as shown in FIG. 22 , patterning is performed using a resist mask 19, and the portion of gate electrode 71 in contact with the side surface of trench 104 is removed by wet etching or dry etching, as shown in FIG. 22 . Alternatively, the portion of gate electrode 71 in contact with the side surface of trench 104 is removed by dry etching using resist mask 19, and then wet etching or dry etching (i.e., by performing etching multiple times). In this way, gate electrode 70 can be formed so as to be spaced apart from the inner side surface of trench 104. FIG. 22 is a combination of plan views and cross-sectional views illustrating an example of a manufacturing process for a SiC semiconductor device according to this embodiment.

[0089] Then, by going through the same processes as steps ST7 to ST10 shown in the first embodiment, a SiC semiconductor device having a structure as shown in Fig. 23 is formed. Note that Fig. 23 is a cross-sectional view showing an example of the configuration of the SiC semiconductor device according to this embodiment.

[0090] According to the manufacturing method of this embodiment, the size of W3, which is the distance between the gate electrode 70 and the side of the trench 104, can be set by adjusting the mask pattern in the process of forming the gate electrode 70 in the termination region 12 shown in Figure 11.

[0091] Increasing W3 makes it possible to increase the distance between the cell region 11 (see FIG. 15 ) through which current flows and the electric field concentration point in the trench 104 of the termination region 12. Therefore, melting of the gate electrode 7 can be suppressed compared to the case shown in the first embodiment.

[0092] On the other hand, increasing W3 also increases the surface area of ​​the SiC semiconductor device, resulting in an increase in the manufacturing cost of the SiC semiconductor device.

[0093] According to the manufacturing method of this embodiment, W3 can be controlled to any length, so that W3 can be adjusted to an optimum value by comparing manufacturing costs and resistance to melting.

[0094] The inner peripheral side surface of the trench 104 in which only the gate electrode 70 shown in FIGS. 22 and 23 is formed may be an inclined surface as shown in FIGS.

[0095] Fifth Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0096] <Configuration of the semiconductor device> A SiC semiconductor device will be described that, compared to the first embodiment, can reduce the current density of the current flowing in the source electrode adjacent to termination region 12 and suppress heat generation in termination region 12 where the electric field concentrates.

[0097] First, steps ST1 to ST3 are performed in the same manufacturing process as in the first embodiment. Then, in step ST4, a mask 15A, which is different from mask 14, is formed using a resist for the termination region. Then, a trench-shaped groove 104 for the termination region is formed on the upper surface of p-type base region 3 by dry etching using plasma or the like (see FIG. 24 ). Here, the distance between groove 104 formed by mask 15A and groove 102 is greater than the distance between grooves 102. Furthermore, the depth of groove 104 in cell region 11 is formed deeper than the depth of groove 102. Note that FIG. 24 is a cross-sectional view showing an example of a manufacturing process for a SiC semiconductor device according to this embodiment.

[0098] Then, by going through the same processes as steps ST5 to ST10 shown in the first embodiment, a SiC semiconductor device having a structure as shown in Fig. 25 is formed. Note that Fig. 25 is a cross-sectional view showing an example of the configuration of the SiC semiconductor device according to this embodiment.

[0099] 25, the distance (W4) between the interlayer insulating film 8 formed on the trench 104 and the interlayer insulating film 8 formed on the trench 102 is greater than the distance (W5) between the interlayer insulating films 8 on the trenches 102. If W4 is made larger, the current density in the source electrode 9 between the cell region 11 and the termination region 12, through which a current flows, can be reduced. Therefore, heat generated by the current in the termination region 12 can be reduced, and melting can be suppressed.

[0100] On the other hand, if W4 is increased, the surface area of ​​the SiC semiconductor device also increases, resulting in an increase in the manufacturing cost of the SiC semiconductor device.

[0101] According to the manufacturing method of this embodiment, W4 can be controlled to any length depending on the shape of the mask 15A, so that the optimum value of W4 can be adjusted by comparing manufacturing cost and resistance to melting.

[0102] The inner peripheral side surface of the groove 104 shown in FIGS. 24 and 25 may be an inclined surface as shown in FIGS. 19, 20 and 21.

[0103] Sixth Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0104] <Regarding the configuration of the semiconductor device> In comparison with the first embodiment, a SiC semiconductor device will be described that can suppress heat generation in the termination region 12 where the electric field is concentrated by blocking the current flowing on the sidewall of the trench 104 in the termination region 12.

[0105] First, steps ST1 to ST6 are performed in the same manufacturing process as in the first embodiment. Then, in step ST7, the photolithography and etching patterning for forming the interlayer insulating film 8 are changed so that the adjacent interlayer insulating film 8 in the termination region 12 and the interlayer insulating film 8 in the cell region 11 are connected. This forms the structure shown in Fig. 26. Note that Fig. 26 is a cross-sectional view showing an example of the manufacturing process of the SiC semiconductor device according to this embodiment.

[0106] Then, by going through the same processes as steps ST8 to ST10 shown in the first embodiment, a SiC semiconductor device having a structure as shown in Fig. 27 is formed. Note that Fig. 27 is a cross-sectional view showing an example of the configuration of the SiC semiconductor device according to this embodiment.

[0107] 27 , the source electrode 9 adjacent to the termination region 12 is blocked without contacting the p-type base region 3. This structure can block the current density between the cell region 11 and the termination region 12. This reduces heat generation due to the current in the termination region 12, thereby preventing melting.

[0108] The inner peripheral side surface of the groove 104 shown in FIGS. 26 and 27 may be an inclined surface as shown in FIGS. 19, 20 and 21.

[0109] Seventh Embodiment A power conversion device and a method for manufacturing the power conversion device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0110] <Configuration of the Power Conversion Device> In this embodiment, the semiconductor device according to the above-described embodiment is applied to a power conversion device. The power conversion device to which the present invention is applied is not limited to a specific application, but the following describes a case where the present invention is applied to a three-phase inverter.

[0111] FIG. 28 is a diagram conceptually illustrating an example of the configuration of a power conversion system including the power conversion device of this embodiment.

[0112] As shown in the example of FIG. 28 , the power conversion system includes a power supply 2100, a power conversion device 2200, and a load 2300. The power supply 2100 is a DC power supply and supplies DC power to the power conversion device 2200. The power supply 2100 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery. The power supply 2100 can also be configured from a rectifier circuit connected to an AC system or an AC-DC converter. The power supply 2100 can also be configured from a DC-DC converter that converts DC power output from a DC system into a predetermined power.

[0113] The power conversion device 2200 is a three-phase inverter connected between the power supply 2100 and the load 2300. The power conversion device 2200 converts DC power supplied from the power supply 2100 into AC power, and further supplies the AC power to the load 2300.

[0114] As shown in an example in Figure 28, the power conversion device 2200 also includes a conversion circuit 2201 that converts DC power into AC power and outputs it, a drive circuit 2202 that outputs drive signals for driving each switching element of the conversion circuit 2201, and a control circuit 2203 that outputs a control signal to the drive circuit 2202 for controlling the drive circuit 2202.

[0115] The load 2300 is a three-phase electric motor driven by AC power supplied from the power conversion device 2200. The load 2300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, such as a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0116] The power conversion device 2200 will be described in detail below. The conversion circuit 2201 includes a switching element and a freewheeling diode (not shown). The switching element performs a switching operation to convert DC power supplied from the power supply 2100 into AC power, which is then supplied to the load 2300.

[0117] There are various specific circuit configurations for the conversion circuit 2201, but the conversion circuit 2201 according to this embodiment is a two-level three-phase full-bridge circuit, and includes six switching elements and six freewheeling diodes connected in anti-parallel to each of the switching elements.

[0118] The semiconductor device according to any of the above-described embodiments is applied to at least one of the switching elements and freewheeling diodes in the conversion circuit 2201. Six switching elements are connected in series in groups of two to form upper and lower arms, each of which constitutes a phase (i.e., U phase, V phase, and W phase) of a full-bridge circuit. The output terminals of each of the upper and lower arms (i.e., the three output terminals of the conversion circuit 2201) are connected to the load 2300.

[0119] The drive circuit 2202 generates drive signals for driving the switching elements of the conversion circuit 2201, and further supplies the drive signals to the control electrodes of the switching elements of the conversion circuit 2201. Specifically, based on control signals output from a control circuit 2203 (described later), the drive circuit 2202 outputs drive signals for turning the switching elements on and off to the control electrodes of the respective switching elements.

[0120] When the switching element is maintained in the on state, the drive signal is a voltage signal (i.e., an on signal) that is equal to or greater than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal is a voltage signal (i.e., an off signal) that is equal to or less than the threshold voltage of the switching element.

[0121] The control circuit 2203 controls the switching elements of the conversion circuit 2201 so that a desired power is supplied to the load 2300. Specifically, the control circuit 2203 calculates the time (i.e., on-time) that each switching element of the conversion circuit 2201 should be in the on-state based on the power to be supplied to the load 2300. For example, the conversion circuit 2201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output.

[0122] Then, the control circuit 2203 outputs a control command (i.e., a control signal) to the drive circuit 2202 so that an ON signal is output to a switching element that should be in an ON state at each point in time, and an OFF signal is output to a switching element that should be in an OFF state at each point in time. Based on the control signal, the drive circuit 2202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.

[0123] In the power conversion device 2200 according to this embodiment, a semiconductor device according to any of the embodiments described above is applied as the switching element of the conversion circuit 2201, and therefore the on-resistance can be stabilized after a current cycle.

[0124] In this embodiment, an example has been described in which the semiconductor device in any of the above-described embodiments is applied to a two-level three-phase inverter, but the application example is not limited to this, and the semiconductor device in any of the above-described embodiments can be applied to various power conversion devices.

[0125] Although the present embodiment has been described with respect to a two-level power conversion device, the semiconductor device according to any of the above-described embodiments may be applied to a three-level or multilevel power conversion device. When power is supplied to a single-phase load, the semiconductor device according to any of the above-described embodiments may be applied to a single-phase inverter.

[0126] Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to any of the above-described embodiments can be applied to a DC-DC converter or an AC-DC converter.

[0127] Furthermore, a power conversion device to which the semiconductor device according to any of the above-described embodiments is applied is not limited to a case in which the load is an electric motor, and can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, for example. Furthermore, a power conversion device to which the semiconductor device according to any of the above-described embodiments is applied can also be used as a power conditioner in a solar power generation system, a power storage system, or the like.

[0128] The semiconductor switching elements used in the embodiments described above are not limited to switching elements made of silicon (Si) semiconductors. For example, the semiconductor switching elements may be made of a non-Si semiconductor material having a wider band gap than a Si semiconductor.

[0129] Examples of wide band gap semiconductors that are non-Si semiconductor materials include silicon carbide, gallium nitride-based materials, and diamond.

[0130] Switching elements made of wide bandgap semiconductors can be used in high voltage regions where unipolar operation is difficult with Si semiconductors, and can significantly reduce the switching loss that occurs during switching operation, thereby enabling a significant reduction in power loss.

[0131] Furthermore, switching elements made of wide bandgap semiconductors have low power loss and high heat resistance, which means that when configuring a power module with a cooling unit, it is possible to reduce the size of the heat dissipation fins of the heat sink, thereby enabling further miniaturization of the semiconductor module.

[0132] Furthermore, switching elements made of wide bandgap semiconductors are suitable for high-frequency switching operations. Therefore, when applied to converter circuits that require higher frequencies, increasing the switching frequency also enables the size of reactors or capacitors connected to the converter circuit to be reduced.

[0133] Therefore, the same effect can be obtained even when the semiconductor switching elements in the above-described embodiments are made of a wide-gap semiconductor such as silicon carbide.

[0134] <Regarding the Effects Produced by the Multiple Embodiments Described Above> Next, examples of the effects produced by the multiple embodiments described above will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the multiple embodiments described above, but these may be replaced with other specific configurations exemplified in the present specification to the extent that similar effects are produced. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0135] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0136] According to the embodiment described above, the semiconductor device includes an n-type SiC substrate 1, an n-type drift layer 2, a p-type base region 3, at least one first trench, a second trench, an n-type source region 4, a first gate electrode, at least one second gate electrode, an interlayer insulating film 8, a source electrode 9, and a drain electrode 10. Here, the first trench corresponds to, for example, trench 102. The second trench corresponds to, for example, trench 104, trench 104A, etc. The first gate electrode corresponds to, for example, gate electrode 7. The second gate electrode corresponds to, for example, gate electrode 70, gate electrode 71, gate electrode 71A, etc. The n-type drift layer 2 is formed on the upper surface of the n-type SiC substrate 1. The p-type base region 3 is formed in a surface layer of the n-type drift layer 2. The trench 102 is formed in the cell region 11 from the upper surface of the p-type base region 3 to reach the inside of the n-type drift layer 2. The trench 104 is formed in the termination region 12 surrounding the cell region 11 in a planar view, extending from the upper surface of the p-type base region 3 to the inside of the n-type drift layer 2. The n-type source region 4 is partially formed on either side of the trench 102 in the surface layer of the p-type base region 3. The gate electrode 7 is formed within the trench 102 and surrounded by the gate insulating film 6. The gate electrode 70 is formed within the trench 104 and surrounded by the gate insulating film 6. The interlayer insulating film 8 is formed covering the gate electrodes 7 and 70. The source electrode 9 is formed in contact with the n-type source region 4. The drain electrode 10 is formed on the lower surface, which is the surface opposite the upper surface of the n-type SiC substrate 1. The gate electrode 7 and the gate electrode 70 are electrically connected. The depth of the trench 104 is deeper than the depth of the trench 102.

[0137] With this configuration, when a high voltage is applied, the electric field at the bottom of the trench 104 in the termination region 12 becomes larger than the electric field at the bottom of the trench 102 in the cell region 11. Therefore, breakdown of the gate insulating film 6 is more likely to occur in the termination region 12 and is relatively less likely to occur in the cell region 11 through which a large current flows. This suppresses heat generation at the breakdown site, and as a result, it is possible to suppress melting of the gate electrode 7.

[0138] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0139] Furthermore, according to the embodiment described above, the width (W1) of the groove 102 in a plan view is narrower than the width (W2) of the groove 104 in a plan view. With this configuration, the wider the width of the bottom of the groove, the easier it is for the etching gas to react. Therefore, if W1<W2, the L １ >L ２ The groove 102 in the cell region 11 and the groove 104 in the termination region 12 can be formed in one step rather than as separate steps.

[0140] Furthermore, according to the embodiment described above, when the angle between the bottom surface and the side surface of trench 104A in termination region 12 is α, the relationship 90°<α is satisfied. With this configuration, it is possible to reduce the electric field concentrating at the corners on the inner periphery of trench 104. Breakdown of gate insulating film 6 is suppressed.

[0141] Furthermore, according to the embodiment described above, gate electrode 70 is formed at a distance from the inner peripheral side surface of trench 104. With such a configuration, it is possible to compare the manufacturing cost of the SiC semiconductor device with the resistance to melting and adjust the value of W3 to an optimum value.

[0142] Furthermore, according to the embodiment described above, the second gate electrode includes a spaced gate electrode (gate electrode 70) formed spaced apart from the inner peripheral side surface of trench 104, and a contact gate electrode (gate electrode 71, gate electrode 71A) formed in contact with the inner peripheral side surface of trench 104. With this configuration, when a high voltage is applied, the electric field at the bottom of trench 104 in termination region 12 becomes larger than the electric field at the bottom of trench 102 in cell region 11. Therefore, breakdown of gate insulating film 6 is more likely to occur in termination region 12, and is relatively less likely to occur in cell region 11, where a large current flows.

[0143] Furthermore, according to the embodiment described above, the power conversion device includes the semiconductor device described above, and also includes a conversion circuit 2201 that converts and outputs input power, a drive circuit 2202 that outputs a drive signal to the semiconductor device for driving the semiconductor device, and a control circuit 2203 that outputs a control signal to the drive circuit 2202 for controlling the drive circuit 2202. With this configuration, when a high voltage is applied, the electric field at the bottom of the trench 104 in the termination region 12 becomes larger than the electric field at the bottom of the trench 102 in the cell region 11. Therefore, breakdown of the gate insulating film 6 is more likely to occur in the termination region 12 and is relatively less likely to occur in the cell region 11 through which a large current flows. This suppresses heat generation at the breakdown site, and as a result, it is possible to suppress melting of the gate electrode 7.

[0144] According to the embodiment described above, in the method for manufacturing a semiconductor device, an n-type drift layer 2 is formed on the upper surface of an n-type SiC substrate 1 of a first conductivity type. Then, a p-type base region 3 of a second conductivity type different from the first conductivity type is formed in the surface layer of the n-type drift layer 2. Then, an n-type source region 4 of the first conductivity type is partially formed in the surface layer of the p-type base region 3. Then, at least one trench 102 is formed in the cell region 11 so as to extend from the upper surface of the n-type source region 4 to the inside of the n-type drift layer 2. Then, in the termination region 12 surrounding the cell region 11 in a planar view, a trench 104 is formed so as to extend from the upper surface of the n-type source region 4 to the inside of the n-type drift layer 2. Then, a gate electrode 7 is formed in the trench 102 so as to be surrounded by a gate insulating film 6. Then, at least one gate electrode 70 is formed in the trench 104 so as to be surrounded by a gate insulating film 6. Then, an interlayer insulating film 8 is formed covering the gate electrode 7 and the gate electrode 70. Then, a source electrode 9 is formed so as to contact the n-type source region 4. Then, a drain electrode 10 is formed on the lower surface, which is the surface opposite to the upper surface of the n-type SiC substrate 1. Here, the gate electrode 7 and the gate electrode 70 are electrically connected. The depth of the groove 104 is deeper than the depth of the groove 102.

[0145] With this configuration, when a high voltage is applied, the electric field at the bottom of the trench 104 in the termination region 12 becomes larger than the electric field at the bottom of the trench 102 in the cell region 11. Therefore, breakdown of the gate insulating film 6 is more likely to occur in the termination region 12 and is relatively less likely to occur in the cell region 11 through which a large current flows. This suppresses heat generation at the breakdown site, and as a result, it is possible to suppress melting of the gate electrode 7.

[0146] Unless otherwise specified, the order in which the processes are performed can be changed.

[0147] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0148] Furthermore, according to the embodiment described above, forming trench 102 means forming trench 102 using a first mask (e.g., mask 14). Forming trench 104 means forming trench 104 using a second mask (e.g., mask 15) different from mask 14. With this configuration, trench 104 can be formed deeper in termination region 12 than trench 102 in cell region 11.

[0149] Furthermore, according to the embodiment described above, forming the second gate electrode means etching the inside of trench 104 to form gate electrode 70 so as to be spaced apart from the inner peripheral side surface of trench 104. With this configuration, W3 can be controlled to any length, and therefore W3 can be adjusted to an optimal value by comparing the manufacturing cost of the SiC semiconductor device with the resistance to melting.

[0150] Furthermore, according to the embodiment described above, forming the second gate electrode involves dry etching the inside of the trench 104, and then removing the gate electrode 71 that contacts the inner circumferential side surface of the trench 104 by further dry etching or wet etching, thereby forming the gate electrode 70 so as to be spaced apart from the inner circumferential side surface of the trench 104. With this configuration, by removing the gate electrode 71 on the inner circumferential side surface of the trench 104 that is close to the trench 102 by an arbitrary width, it is possible to adjust the distance (W3) between the gate electrode 70 in the trench 104 and the inner corner of the trench 104. In other words, since W3 can be controlled to an arbitrary length, it is possible to compare manufacturing cost and resistance to melting and adjust W3 to an optimal value.

[0151] Furthermore, according to the embodiment described above, a method for manufacturing a power converter includes a conversion circuit 2201 having a semiconductor device manufactured by the above-described manufacturing method, and converting and outputting input power. A drive circuit 2202 is also provided for outputting a drive signal to the semiconductor device for driving the semiconductor device. A control circuit 2203 is also provided for outputting a control signal to the drive circuit 2202 for controlling the drive circuit 2202. With this configuration, when a high voltage is applied, the electric field at the bottom of the trench 104 in the termination region 12 is greater than the electric field at the bottom of the trench 102 in the cell region 11. Therefore, breakdown of the gate insulating film 6 is more likely to occur in the termination region 12 and less likely to occur in the cell region 11 through which a large current flows. This suppresses heat generation at the breakdown site, thereby suppressing melting of the gate electrode 7.

[0152] <Regarding Modifications of the Multiple Embodiments Described Above> In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0153] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component from at least one embodiment and combining it with a component from another embodiment.

[0154] Furthermore, in at least one embodiment described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0155] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, "one or more" of that component may be provided.

[0156] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to a part of a structure, and even cases where multiple components are provided in one structure.

[0157] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0158] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0159] Various aspects of the present disclosure are summarized below as appendices.

[0160] a first conductivity type SiC substrate; a first conductivity type drift layer formed on an upper surface of the SiC substrate; a second conductivity type base region formed in a surface layer of the drift layer, the second conductivity type being different from the first conductivity type; at least one first trench formed in a cell region from an upper surface of the base region to reach into the drift layer; a second trench formed in a termination region surrounding the cell region in a plan view from the upper surface of the base region to reach into the drift layer; a first conductivity type source region partially formed on either side of the first trench in the surface layer of the base region; a first gate electrode formed in the first trench and surrounded by a gate insulating film; at least one second gate electrode formed in the second trench and surrounded by a gate insulating film; an interlayer insulating film formed to cover the first gate electrode and the second gate electrode; a source electrode formed in contact with the source region; and a drain electrode formed on a lower surface of the SiC substrate, the lower surface being the surface opposite to the upper surface, a first gate electrode and a second gate electrode electrically connected to each other; and a depth of the second trench is greater than a depth of the first trench.

[0161] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein the width of the first groove in a plan view is narrower than the width of the second groove in a plan view.

[0162] (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein, when an angle between a bottom surface and a side surface of the second trench in the termination region is α, 90°<α is satisfied.

[0163] (Supplementary Note 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the second gate electrode is formed spaced apart from a side surface on an inner periphery side of the second trench.

[0164] (Supplementary Note 5) The semiconductor device according to Supplementary Note 4, wherein the second gate electrode includes a spaced gate electrode formed spaced apart from the inner peripheral side surface of the second trench, and a contact gate electrode formed in contact with the inner peripheral side surface of the second trench.

[0165] (Supplementary Note 6) The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein a distance between the interlayer insulating film formed to cover the second gate electrode and the interlayer insulating film formed to cover the first gate electrode is greater than a distance between the interlayer insulating films formed to cover the first gate electrodes.

[0166] (Supplementary Note 7) The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the interlayer insulating film formed to cover the first gate electrode adjacent to the second gate electrode is connected to the interlayer insulating film formed to cover the second gate electrode.

[0167] (Supplementary Note 8) A power conversion device comprising: a conversion circuit having the semiconductor device according to any one of Supplementary Notes 1 to 7, and converting and outputting input power; a drive circuit outputting a drive signal to the semiconductor device for driving the semiconductor device; and a control circuit outputting a control signal to the drive circuit for controlling the drive circuit.

[0168] (Supplementary Note 9) A drift layer of a first conductivity type is formed on an upper surface of a SiC substrate of a first conductivity type, a base region of a second conductivity type different from the first conductivity type is formed in a surface layer of the drift layer, a source region of a first conductivity type is partially formed in a surface layer of the base region, at least one first trench is formed in a cell region so as to extend from an upper surface of the source region into the drift layer, a second trench is formed in a termination region surrounding the cell region in a planar view so as to extend from the upper surface of the source region into the drift layer, a first gate electrode is formed in the first trench so as to be surrounded by a gate insulating film, at least one second gate electrode is formed in the second trench so as to be surrounded by a gate insulating film, an interlayer insulating film is formed covering the first gate electrode and the second gate electrode, a source electrode is formed so as to be in contact with the source region, a drain electrode is formed on a lower surface, which is a surface opposite to the upper surface of the SiC substrate, and the first gate electrode and the second gate electrode are electrically connected, a depth of the second trench is greater than a depth of the first trench.

[0169] (Supplementary Note 10) The method for manufacturing a semiconductor device according to Supplementary Note 9, wherein forming the first groove is forming the first groove using a first mask, and forming the second groove is forming the second groove using a second mask different from the first mask.

[0170] (Appendix 11) The method for manufacturing a semiconductor device according to appendix 9 or 10, wherein forming the second gate electrode comprises etching the inside of the second trench to form the second gate electrode so as to be spaced apart from the side surface on the inner periphery of the second trench.

[0171] (Appendix 12) The method for manufacturing a semiconductor device according to Appendix 11, wherein forming the second gate electrode comprises dry etching the inside of the second trench, and further removing the second gate electrode in contact with the inner circumferential side surface of the second trench by dry etching or wet etching, and forming the second gate electrode so as to be spaced apart from the inner circumferential side surface of the second trench.

[0172] (Supplementary Note 13) A method for manufacturing a power conversion device, comprising: a semiconductor device manufactured by the manufacturing method described in any one of Supplementary Notes 9 to 12; a conversion circuit that converts input power and outputs it; a drive circuit that outputs a drive signal to the semiconductor device for driving the semiconductor device; and a control circuit that outputs a control signal to the drive circuit for controlling the drive circuit.

[0173] 1 SiC substrate, 2 drift layer, 3 base region, 4 source region, 5 base region, 6 gate insulating film, 7 gate electrode, 8 interlayer insulating film, 9 source electrode, 10 drain electrode, 11 cell region, 12 termination region, 13 mask, 14 mask, 15 mask, 15A mask, 16 mask, 17 mask, 18 mask, 18A inclined surface, 19 mask, 70 gate electrode, 71 gate electrode, 71A gate electrode, 72 electrode layer, 102 groove, 104 groove, 104A groove, 2100 power supply, 2200 power conversion device, 2201 conversion circuit, 2202 drive circuit, 2203 control circuit, 2300 load.

Claims

1. A SiC substrate of a first conductivity type, A drift layer of the first conductivity type formed on the upper surface of the SiC substrate, A base region of a second conductivity type different from the first conductivity type formed on the surface layer of the drift layer, At least one first groove formed to reach into the drift layer from the upper surface of the base region in the cell region, In a termination region surrounding the cell region in a plan view, a second groove formed to reach into the drift layer from the upper surface of the base region, A source region of the first conductivity type partially formed sandwiching the first groove in the surface layer of the base region, In the first groove, a first gate electrode formed surrounded by a gate insulating film, In the second groove, at least one second gate electrode formed surrounded by a gate insulating film, An interlayer insulating film formed covering the first gate electrode and the second gate electrode, A source electrode formed in contact with the source region, A drain electrode formed on the lower surface which is the opposite surface of the upper surface of the SiC substrate, and comprising, The first gate electrode and the second gate electrode are electrically connected, The depth of the second groove is deeper than the depth of the first groove, The width of the first groove in a plan view is narrower than the width of the second groove in a plan view, A semiconductor device.

2. The semiconductor device according to Claim 1, The first gate electrode in contact with the upper surface of the gate insulating film formed on the bottom surface of the first groove, The second gate electrode in contact with the upper surface of the gate insulating film formed on the bottom surface of the second groove, and comprising, A semiconductor device.

3. The semiconductor device according to Claim 1 or 2, When the angle of the corner between the bottom surface and the side surface of the second groove in the termination region is α, satisfying 90° < α, A semiconductor device.

4. The semiconductor device according to Claim 1 or 2, The second gate electrode is formed spaced apart from the side surface on the inner circumferential side of the second groove, A semiconductor device.

5. The semiconductor device according to Claim 4, The second gate electrode includes a spaced gate electrode formed spaced apart from the side surface on the inner circumferential side of the second groove and a contact gate electrode formed in contact with the side surface on the inner circumferential side of the second groove, A semiconductor device.

6. The semiconductor device according to Claim 1 or 2, The distance between the interlayer insulating film formed to cover the second gate electrode and the interlayer insulating film formed to cover the first gate electrode is greater than the distance between the interlayer insulating films formed to cover the first gate electrode. Semiconductor device. **Claim 7** The semiconductor device according to claim 1 or 2, the interlayer insulating film formed to cover the first gate electrode adjacent to the second gate electrode is connected to the interlayer insulating film formed to cover the second gate electrode. Semiconductor device. **Claim 8** having the semiconductor device according to claim 1 or 2, and a conversion circuit that converts input power and outputs it, a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device, and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit. Power conversion device. **Claim 9** Form a drift layer of the first conductivity type on the upper surface of a SiC substrate of the first conductivity type, form a base region of the second conductivity type different from the first conductivity type on the surface layer of the drift layer, partially form a source region of the first conductivity type on the surface layer of the base region, form at least one first groove in the cell region so as to reach into the drift layer from the upper surface of the source region, form a second groove in the terminal region surrounding the cell region in plan view so as to reach into the drift layer from the upper surface of the source region, form a first gate electrode in the first groove so as to be surrounded by a gate insulating film, form at least one second gate electrode in the second groove so as to be surrounded by a gate insulating film, form an interlayer insulating film to cover the first gate electrode and the second gate electrode, form a source electrode so as to contact the source region, form a drain electrode on the lower surface, which is the surface opposite to the upper surface of the SiC substrate, the first gate electrode and the second gate electrode are electrically connected, the depth of the second groove is deeper than the depth of the first groove, the width of the first groove in plan view is narrower than the width of the second groove in plan view. [[ID= ​ ​ ​ ​ Method for manufacturing a semiconductor device.

11. A method for manufacturing a semiconductor device according to claim 9 or 10, wherein forming the second gate electrode is to form the second gate electrode so as to be separated from the side surface on the inner circumferential side of the second groove by etching the inside of the second groove. Method for manufacturing a semiconductor device.

12. A method for manufacturing a semiconductor device according to claim 11, wherein forming the second gate electrode is to dry-etch the inside of the second groove, and further remove the second gate electrode in contact with the side surface on the inner circumferential side of the second groove by dry-etching or wet-etching, and then form the second gate electrode so as to be separated from the side surface on the inner circumferential side of the second groove. Method for manufacturing a semiconductor device.