Semiconductor device

Abstract

This semiconductor device includes: a chip that has a first main surface; an IGBT region that is formed on the first main surface of the chip; a diode region that is formed on the first main surface of the chip and is adjacent to the IGBT region in a first direction; a gate extension electrode that extends in a region on the first main surface by continuously across the IGBT region and the diode region in the first direction; and a trench gate structure that is formed on the first main surface of the chip and extends across the gate extension electrode. The gate extension electrode selectively has a gate resistor in a portion crossing the diode region while avoiding a portion immediately above the trench gate structure.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2023-084043 filed with the Japan Patent Office on May 22, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) as an example of a semiconductor device. The RC-IGBT includes an IGBT region and a diode region built in a common semiconductor layer. The IGBT region includes an IGBT. The diode region includes a diode.

[0004] International Publication No. 2020 / 080476

[0005] One embodiment of the present disclosure provides a semiconductor device having a gate resistance without compromising the effective area of ​​the IGBT region.

[0006] One embodiment of the present disclosure provides a semiconductor device including: a chip having a first main surface; an IGBT region formed on the first main surface of the chip; a diode region formed on the first main surface of the chip and adjacent to the IGBT region in a first direction; a gate extension electrode extending through a region on the first main surface, continuously across the IGBT region and the diode region in the first direction; and a trench gate structure formed on the first main surface of the chip and extending across the gate extension electrode, wherein the gate extension electrode avoids a portion directly above the trench gate structure and selectively has a gate resistor in a portion that crosses the diode region.

[0007] According to an embodiment of the present disclosure, it is possible to provide a semiconductor device having a gate resistor without reducing the effective area of ​​the IGBT region.

[0008] FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a schematic plan view illustrating the internal structure of the semiconductor device. FIG. 3 is an enlarged view of a portion surrounded by III in FIG. 2. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 3. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 3. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 3. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 3. FIG. 12 is an enlarged view of a portion surrounded by XII in FIG. 2. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 12. FIG. 14 is a diagram showing a modified example of the gate-assist trench structure of FIG. 12. FIG. 15 is a diagram showing a modified example of the gate-assist trench structure of FIG. 12. FIG. 16 is a diagram showing a modified example of the gate-assist trench structure of FIG. 12. FIG. 17 is an enlarged view of a portion surrounded by XVII in FIG. 2. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 17. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 17. FIG. 20 is a diagram showing a modified example of the arrangement pattern of the IGBT regions and the diode regions. FIG. 21 is an enlarged view of a portion surrounded by XXI in FIG. 20.

[0009] Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0010] FIG. 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present disclosure.

[0011] The semiconductor device 1 is an electronic component having an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) that integrates an IGBT and a diode. The semiconductor device 1 includes a rectangular parallelepiped semiconductor chip 2. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D that connect the first main surface 3 and the second main surface 4.

[0012] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") seen from their normal direction Z. The first main surface 3 and the second main surface 4 may be referred to as the front and back surfaces of the semiconductor chip 2, respectively. The side surface 5A and the side surface 5C extend along the first direction X and face each other in a second direction Y that intersects with the first direction X. The side surface 5B and the side surface 5D extend along the second direction Y and face each other in the first direction X. Specifically, the second direction Y is perpendicular to the first direction X.

[0013] An electrode film 6 is formed on the first main surface 3. The electrode film 6 includes a plurality of terminal electrodes 7 to 12 and a plurality of wirings 13 to 15. The plurality of terminal electrodes 7 to 11 are arranged at intervals along the side surface of the semiconductor chip 2. The plurality of terminal electrodes 7 to 11 are concentrated on one side surface of the semiconductor chip 2 (side surface 5B in FIG. 1 ) and lined up in a row along side surface 5B.

[0014] The electrode film 6 includes, as components related to the gate of the RC-IGBT, a gate terminal electrode 7 and a gate wiring 13. The gate wiring 13 transmits a gate signal applied to the gate terminal electrode 7 to the gate of the IGBT.

[0015] The gate terminal electrode 7 is disposed at the center of the multiple terminal electrodes 7 to 11. The gate wiring 13 integrally includes an annular first portion 16 extending from the gate terminal electrode 7 along the side surfaces 5A to 5D of the semiconductor chip 2, and a second portion 17 extending across an active region 18 surrounded by the first portion 16. The gate wiring 13 may also be referred to as a gate finger. The first portion 16 and the second portion 17 of the gate wiring 13 may also be referred to as an outer gate finger and an inner gate finger, respectively. The first portion 16 and the second portion 17 of the gate wiring 13 may also be referred to as an outer extension electrode and an inner extension electrode, respectively.

[0016] The active region 18 is a region in which the RC-IGBT is formed. The region outside the active region 18 is a peripheral region 19. The peripheral region 19 extends in a strip shape along the periphery of the active region 18. Specifically, the peripheral region 19 is set in an endless shape (a square ring shape) surrounding the active region 18 in a plan view.

[0017] The active region 18 is divided into a plurality of partitioned regions 20 by the second portions 17 of the gate wiring 13. Each of the plurality of partitioned regions 20 has a rectangular shape extending along the first direction X. The plurality of partitioned regions 20 are adjacent to each other with the second portions 17 of the gate wiring 13 sandwiched therebetween.

[0018] In this embodiment, second portions 17 of the plurality of gate wirings 13 cross the active region 18. The plurality of second portions 17 are arranged at intervals in the second direction Y and are formed in stripes extending in the first direction X. One end and the other end of each second portion 17 are connected to different positions in the first portion 16. Each second portion 17 has a base end (which may be referred to as a terminal-side end or a pad-side end) on the side of the plurality of terminal electrodes 7 to 11 connected to the first portion 16, and the opposite end may be a termination portion without being connected to the first portion 16.

[0019] The plurality of second portions 17 include a central wiring 21 extending from the vicinity of the gate terminal electrode 7, and a plurality of side wirings 22 extending from positions spaced apart from the gate terminal electrode 7 in the second direction Y. In Fig. 1, one central wiring 21 and two side wirings 22 are provided on each side of the central wiring 21 in the second direction Y. This divides the active region 18 into six partitioned regions 20.

[0020] The electrode film 6 includes an emitter terminal electrode 12 as a component related to the emitter of the RC-IGBT. The emitter terminal electrode 12 is disposed in each partition region 20. In this embodiment, one emitter terminal electrode 12 is provided in each partition region 20. A plurality of emitter terminal electrodes 12 are provided, the same number as the number of partition regions 20. Of course, a plurality of emitter terminal electrodes 12 that are physically separated from one another may be provided in each partition region 20.

[0021] The electrode film 6 further includes a first sense terminal electrode 8, a second sense terminal electrode 9, a current detection terminal electrode 10, and an open terminal electrode 11. The first sense terminal electrode 8 and the second sense terminal electrode 9 transmit control signals that control a sensor region 23 (temperature sensor) located in the center of the active region 18. The current detection terminal electrode 10 is an electrode that detects the current flowing through the active region 18 and extracts it to the outside. The open terminal electrode 11 is in an electrically floating state.

[0022] The electrode film 6 includes a first sense wiring 14 and a second sense wiring 15. The first sense wiring 14 is electrically connected to the first sense terminal electrode 8. The first sense wiring 14 extends from the outer periphery region 19 toward the sensor region 23. The first sense wiring 14 transmits a control signal for the temperature sensor. The second sense wiring 15 is electrically connected to the second sense terminal electrode 9. The second sense wiring 15 extends from the outer periphery region 19 toward the sensor region 23. The second sense wiring 15 transmits a control signal for the temperature sensor. The gate wiring 13 (central wiring 21), the first sense wiring 14, and the second sense wiring 15 run parallel to each other at intervals in the first direction X.

[0023] 2 is a schematic plan view for explaining the internal structure of the semiconductor device 1. For clarity, in FIG. 2, the terminal electrodes 7 to 11 and the gate wiring 13 of the electrode film 6 are shown, and other parts of the electrode film 6 are omitted.

[0024] The active region 18 includes an IGBT region 24 and a diode region 25. In FIG. 2 , for clarity, the IGBT region 24 is shown by hatching. The IGBT region 24 is a region in which an IGBT is formed. The diode region 25 is a region in which a diode is formed. The diode region 25 is adjacent to the IGBT region 24.

[0025] Specifically, the active region 18 includes an RC-IGBT array 26. A plurality of the RC-IGBT arrays 26 (six in this embodiment) are formed at intervals in the second direction Y. Adjacent RC-IGBT arrays 26 are separated by gate wiring 13. The RC-IGBT array 26 has a first end on one side (side surface 5B side) and a second end on the other side (side surface 5D side). The first end of the RC-IGBT array 26 may also be referred to as a terminal-side end or a pad-side end. The second end of the RC-IGBT array 26 may also be referred to as a termination-side end.

[0026] The RC-IGBT array 26 has a loop arrangement including a repeating series of diode regions 25, IGBT regions 24, diode regions 25, IGBT regions 24, diode regions 25, ... arranged in a line along the first direction X from a first end to a second end. In this embodiment, the first end of the RC-IGBT array 26 is formed by the diode regions 25. In this embodiment, the second end of the RC-IGBT array 26 is formed by the diode regions 25. The first end of the RC-IGBT array 26 may be formed by the IGBT regions 24. The second end of the RC-IGBT array 26 may be formed by the IGBT regions 24.

[0027] In this manner, a plurality of IGBT regions 24 are dispersed and arranged in the active region 18. The IGBT regions 24 are formed at intervals along the first direction X and the second direction Y. In this embodiment, the IGBT regions 24 are arranged in a matrix in plan view. The IGBT regions 24 face each other along the first direction X and face each other along the second direction Y.

[0028] In this embodiment, each of the IGBT regions 24 is formed in a quadrangular shape in plan view. Specifically, each of the IGBT regions 24 is formed in a rectangular shape extending along the second direction Y.

[0029] The width WI of each IGBT region 24 in the first direction X may be 10 μm or more and 1000 μm or less. The width WI may be 10 μm or more and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, 400 μm or more and 500 μm or less, 500 μm or more and 600 μm or less, 600 μm or more and 700 μm or less, 700 μm or more and 800 μm or less, 800 μm or more and 900 μm or less, or 900 μm or more and 1000 μm or less. The width WI is preferably 100 μm or more. The width WI is more preferably 200 μm or more.

[0030] A plurality of diode regions 25 are dispersed and arranged in the active region 18. The plurality of diode regions 25 are formed at intervals along the first direction X and the second direction Y. In this embodiment, the plurality of diode regions 25 are arranged in a matrix in plan view. The plurality of diode regions 25 face each other along the first direction X and face each other along the second direction Y.

[0031] Specifically, each of the plurality of diode regions 25 is formed adjacent to an IGBT region 24 in the first direction X. In this embodiment, each of the plurality of diode regions 25 is formed in a quadrangular shape in plan view. Specifically, each of the plurality of diode regions 25 is formed in a rectangular shape extending along the second direction Y.

[0032] The planar area of ​​each diode region 25 is preferably equal to or smaller than the planar area of ​​each IGBT region 24. It is more preferable that the planar area of ​​each diode region 25 is smaller than the planar area of ​​each IGBT region 24. It is preferable that the width WD of each diode region 25 in the first direction X is equal to or smaller than the width WI of each IGBT region 24. It is more preferable that the width WD of each diode region 25 is smaller than the width WI of each IGBT region 24.

[0033] The width WD may be 5 μm or more and less than 1000 μm. The width WD may be 5 μm or more and less than 100 μm, 100 μm or more and less than 200 μm, 200 μm or more and less than 300 μm, 300 μm or more and less than 400 μm, 400 μm or more and less than 500 μm, 500 μm or more and less than 600 μm, 600 μm or more and less than 700 μm, 700 μm or more and less than 800 μm, 800 μm or more and less than 900 μm, or 900 μm or more and less than 1000 μm. The width WD is preferably 100 μm or more. The width WD is more preferably 200 μm or more.

[0034] Next, one form of the planar structure of the active region 18 will be described. Fig. 3 is an enlarged view of the portion surrounded by III in Fig. 2, showing some of the multiple IGBT regions 24 and multiple diode regions 25. The planar structure of the IGBT regions 24 and diode regions 25 described below may be applied to all of the IGBT regions 24 and all of the diode regions 25 of the semiconductor chip 2, or may be applied selectively to some of the IGBT regions 24 and diode regions 25. In other words, the planar structure described below is a structure that can be applied to at least one IGBT region 24 and diode region 25.

[0035] 3, multiple types of trench electrode structures 27-29 are formed in a stripe pattern on the first main surface 3 of the semiconductor chip 2. The multiple trench electrode structures 27-29 extend parallel to each other along the second direction Y. In this embodiment, the multiple trench electrode structures 27-29 are a trench gate structure 27, an emitter trench structure 28, and a diode-side trench structure 29. In FIG. 3, the trench gate structure 27, the emitter trench structure 28, and the diode-side trench structure 29 are indicated by hatching.

[0036] The plurality of trench gate structures 27 are formed in the IGBT region 24. The trench gate structures 27 are formed in a band shape extending along the second direction Y in a plan view. The plurality of trench gate structures 27 are formed in a stripe shape as a whole. The plurality of trench gate structures 27 cross from one side to the other side in the second direction Y directly below the gate wiring 13. As a result, the common trench gate structure 27 straddles the plurality of partitioned regions 20. The trench gate structure 27 has an end portion 30 on each of one side and the other side in the second direction Y. In FIG. 3, the end portion 30 on one side is shown.

[0037] The termination portions 30 of the trench gate structures 27 are formed one for each pair of trench gate structures 27. The termination portions 30 connect adjacent trench gate structures 27 at the outer periphery region 19. The termination portions 30 are formed in a round shape in plan view.

[0038] A plurality of emitter trench structures 28 are formed in the IGBT region 24. The emitter trench structures 28 are formed in a band shape extending along the second direction Y in a plan view. The plurality of emitter trench structures 28 extend parallel to the trench gate structures 27, and the emitter trench structures 28 and the trench gate structures 27 as a whole are formed in a stripe shape. The plurality of emitter trench structures 28 are sandwiched between the plurality of trench gate structures 27 in the first direction X. In this embodiment, a pair of emitter trench structures 28 is sandwiched between the plurality of trench gate structures 27 in the first direction X.

[0039] The multiple emitter trench structures 28 do not cross the gate wiring 13, and have termination portions 31 inside the IGBT region 24 away from the gate wiring 13 in the second direction Y. One termination portion 31 of the emitter trench structures 28 is formed for each pair of emitter trench structures 28. The termination portions 31 connect adjacent emitter trench structures 28 within the IGBT region 24. The termination portions 31 are formed in a rounded shape in a plan view.

[0040] A plurality of diode-side trench structures 29 are formed in the diode region 25. The diode-side trench structures 29 are formed in a band shape extending along the second direction Y in a plan view. The plurality of diode-side trench structures 29 are formed in a stripe shape as a whole. The plurality of diode-side trench structures 29 cross from one side to the other in the second direction Y directly below the gate wiring 13. As a result, the common diode-side trench structure 29 spans a plurality of partitioned regions 20. The diode-side trench structure 29 has an end portion 32 on each of one side and the other side in the second direction Y. In FIG. 3 , the end portion 32 on one side is shown.

[0041] The termination portions 32 of the diode-side trench structures 29 are formed one for each pair of diode-side trench structures 29. The termination portions 32 connect adjacent diode-side trench structures 29 at the outer circumferential region 19. The termination portions 32 are formed in a round shape in plan view.

[0042] The gate wiring 13 is an electrode that extends across the plurality of trench gate structures 27 in the first direction X. The gate wiring 13 may also be referred to as a gate extension electrode 33. The gate extension electrode 33 includes a first electrode layer 34 and a second electrode layer 35.

[0043] The second electrode layer 35 is a layer stacked on the first electrode layer 34. The second electrode layer 35 is an electrode layer that appears on the outermost surface of the gate extension electrode 33 and may be referred to as a surface layer. The second electrode layer 35 is a layer with lower resistance than the first electrode layer 34. The contour of the second electrode layer 35 coincides with the contour of the gate extension electrode 33. In this embodiment, the second electrode layer 35 is formed in the shape of a single strip that extends continuously across the multiple IGBT regions 24 and multiple diode regions 25 that are alternately arranged. The second electrode layer 35 is strip-shaped and has a constant width in the second direction Y.

[0044] The first electrode layer 34 is formed to avoid the region directly above the diode-side trench structure 29. Specifically, the first electrode layer 34 is selectively divided by a non-contact section 36 where the second electrode layer 35 and the diode region 25 face each other. As a result, the first electrode layer 34 is selectively disposed in a contact section 37 where the second electrode layer 35 and the IGBT region 24 face each other. In other words, the gate extension electrode 33 does not include the first electrode layer 34 directly above the trench gate structure 27, but selectively includes the second electrode layer 35. The first electrode layer 34 is formed in a strip shape that is long in the first direction X and collectively covers the multiple trench gate structures 27. The first electrode layer 34 is a layer electrically connected to the multiple trench gate structures 27 and may be referred to as a first contact layer 38.

[0045] A second contact layer 39 is formed on the first main surface 3 of the semiconductor chip 2. The second contact layer 39 is a layer electrically connected to the plurality of diode-side trench structures 29. The second contact layer 39 is formed in a strip shape that is long in the first direction X, and collectively covers the plurality of diode-side trench structures 29. In this embodiment, the second contact layer 39 is spaced apart from the gate extension electrode 33 toward the inside of the diode region 25 and extends parallel to the gate extension electrode 33.

[0046] A third contact layer 40 is formed on the first main surface 3 of the semiconductor chip 2. The third contact layer 40 is a layer that is electrically connected to the plurality of emitter trench structures 28. The third contact layer 40 is formed in an island shape in a plan view, and collectively covers the termination portions 31 of a pair of emitter trench structures 28.

[0047] Next, one embodiment of the cross-sectional structure of the active region 18 will be described. Fig. 4 is a cross-sectional view taken along line IV-IV in Fig. 3. Fig. 5 is a cross-sectional view taken along line V-V in Fig. 3. First, the basic cross-sectional structures of the IGBT region 24 and the diode region 25 will be described with reference to Figs. 4 and 5.

[0048] The semiconductor device 1 is a semiconductor device including n －The drift region 41 includes an n-type drift region 41. Specifically, the drift region 41 is formed over the entire area of ​​the semiconductor chip 2 in the first direction X and the second direction Y. The drift region 41 is formed in the surface layer portion of the first main surface 3 of the semiconductor chip 2 in the normal direction Z (thickness direction of the semiconductor chip 2). The n-type impurity concentration of the drift region 41 is 1.0×10 １３ cm －３ Above 1.0 x 10 １５ cm －３ It may be the following:

[0049] In this embodiment, the semiconductor chip 2 is － The drift region 41 has a single-layer structure including a semiconductor substrate 42. The semiconductor substrate 42 may be a silicon FZ (Floating Zone) substrate formed through an FZ method. The drift region 41 is formed by the semiconductor substrate 42.

[0050] The semiconductor device 1 includes a collector terminal electrode 43 formed on the second main surface 4 of the semiconductor chip 2. The collector terminal electrode 43 is electrically connected to the second main surface 4. Specifically, the collector terminal electrode 43 is electrically connected to the IGBT region 24 (a collector region 45 described later) and the diode region 25 (a cathode region 58 described later). The collector terminal electrode 43 forms ohmic contact with the second main surface 4. The collector terminal electrode 43 transmits a collector signal to the IGBT region 24 and the diode region 25.

[0051] The collector terminal electrode 43 may include at least one of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer. The collector terminal electrode 43 may have a single-layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer, or an Al layer. The collector terminal electrode 43 may have a multilayer structure in which at least two of a Ti layer, a Ni layer, an Au layer, an Ag layer, and an Al layer are stacked in any manner.

[0052] The semiconductor device 1 includes an n-type buffer layer 44 formed in the surface layer portion of the second main surface 4 of the semiconductor chip 2. The buffer layer 44 may be formed over the entire surface layer portion of the second main surface 4. The n-type impurity concentration of the buffer layer 44 is higher than the n-type impurity concentration of the drift region 41. The n-type impurity concentration of the buffer layer 44 is 1.0×10 １５ cm －３ Above 1.0 x 10 １７ cm －３ It may be the following:

[0053] The thickness of the buffer layer 44 may be 0.5 μm or more and 30 μm or less, 0.5 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or more and 30 μm or less.

[0054] Each IGBT region 24 includes a p-type collector region 45 formed in a surface layer portion of the second main surface 4 of the semiconductor chip 2. The collector region 45 is exposed from the second main surface 4. The collector region 45 may be formed in the entire IGBT region 24 in the surface layer portion of the second main surface 4. The p-type impurity concentration of the collector region 45 is 1.0×10 １５ cm －３ Above 1.0 x 10 １８ cm －３ The collector region 45 forms an ohmic contact with the collector terminal electrode 43 .

[0055] Each IGBT region 24 includes a FET structure 46 formed on the first main surface 3 of the semiconductor chip 2. In this embodiment, each IGBT region 24 includes a trench gate type FET structure 46. Specifically, the FET structure 46 includes a trench gate structure 27 formed on the first main surface 3.

[0056] A plurality of trench gate structures 27 are formed at intervals along the first direction X in the IGBT region 24. The distance between two adjacent trench gate structures 27 in the first direction X may be 1 μm or more and 8 μm or less. The distance between two trench gate structures 27 may be 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, or 7 μm or more and 8 μm or less.

[0057] Each trench gate structure 27 includes a gate trench 47, a gate insulating layer 48, and a gate electrode layer 49. The gate trench 47 is formed in the first main surface 3. The gate trench 47 includes sidewalls and a bottom wall. The sidewalls of the gate trench 47 may be formed perpendicular to the first main surface 3.

[0058] The sidewalls of the gate trench 47 may slope downward from the first main surface 3 toward the bottom wall. The gate trench 47 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The bottom wall of the gate trench 47 may be formed parallel to the first main surface 3. The bottom wall of the gate trench 47 may be formed in a curved shape toward the second main surface 4. The gate trench 47 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewalls and bottom wall of the gate trench 47. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4.

[0059] The depth D1 of the gate trench 47 may be 2 μm or more and 10 μm or less. The depth D1 of the gate trench 47 may be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less. The depth D1 of the gate trench 47 may be defined as the distance between the deepest depth position of the bottom wall of the gate trench 47 and the first main surface 3.

[0060] The width of the gate trench 47 may be 0.5 μm or more and 3 μm or less. The width of the gate trench 47 is the width of the gate trench 47 in the first direction X. The width of the gate trench 47 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0061] The gate insulating layer 48 is formed in a film shape along the inner wall of the gate trench 47. The gate insulating layer 48 defines a recess space within the gate trench 47. In this embodiment, the gate insulating layer 48 includes a silicon oxide film. The gate insulating layer 48 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0062] The gate electrode layer 49 is embedded in the gate trench 47 with the gate insulating layer 48 sandwiched therebetween. Specifically, the gate electrode layer 49 is embedded in a recess space defined by the gate insulating layer 48 in the gate trench 47. The gate electrode layer 49 is controlled by a gate signal. The gate electrode layer 49 may include conductive polysilicon.

[0063] The FET structure 46 includes a p-type body region 50 formed in the surface layer portion of the first main surface 3 of the semiconductor chip 2. The p-type impurity concentration of the body region 50 is 1.0×10 １７ cm －３ Above 1.0 x 10 １８ cm －３ The body region 50 may be formed on both sides of the trench gate structure 27. The body region 50 is formed in a strip shape extending along the trench gate structure 27 in a plan view. The body region 50 is exposed from the sidewall of the gate trench 47. The bottom of the body region 50 is formed in a region between the first main surface 3 and the bottom wall of the gate trench 47 in the normal direction Z.

[0064] The FET structure 46 is formed in the surface layer of the body region 50. ＋The n-type impurity concentration of the emitter region 51 is greater than the n-type impurity concentration of the drift region 41. The n-type impurity concentration of the emitter region 51 is 1.0×10 １９ cm －３ Above 1.0 x 10 ２０ cm －３ It may be the following:

[0065] In this embodiment, the FET structure 46 includes a plurality of emitter regions 51 formed on both sides of the trench gate structure 27. The emitter regions 51 are formed in strip shapes extending along the trench gate structure 27 in a plan view. The emitter regions 51 are exposed from the first main surface 3 and the sidewalls of the gate trench 47. The bottoms of the emitter regions 51 are formed in a region between the upper end of the gate electrode layer 49 and the bottom of the body region 50 in the normal direction Z.

[0066] In this embodiment, the FET structure 46 is an n-type FET formed in a region on the second main surface 4 side of the body region 50 in the semiconductor chip 2. ＋ The n-type impurity concentration of the carrier storage region 52 is greater than the n-type impurity concentration of the drift region 41. The n-type impurity concentration of the carrier storage region 52 is 1.0×10 １５ cm －３ Above 1.0 x 10 １７ cm －３ It may be the following:

[0067] In this embodiment, the FET structure 46 includes a plurality of carrier storage regions 52 formed on both sides of the trench gate structure 27. The carrier storage regions 52 are formed in strip shapes extending along the trench gate structure 27 in a plan view. The carrier storage regions 52 are exposed from the sidewalls of the gate trench 47. The bottoms of the carrier storage regions 52 are formed in regions between the bottom of the body region 50 and the bottom wall of the gate trench 47 in the normal direction Z.

[0068] The carrier storage region 52 prevents carriers (holes) supplied to the semiconductor chip 2 from being drawn back (discharged) to the body region 50. This causes holes to accumulate in the region directly below the FET structure 46 in the semiconductor chip 2. As a result, the on-resistance and the on-voltage are reduced.

[0069] The FET structure 46 includes a contact trench 53 formed in the first main surface 3 of the semiconductor chip 2. In this embodiment, the FET structure 46 includes a plurality of contact trenches 53 formed on both sides of the trench gate structure 27. The contact trench 53 exposes the emitter region 51. In this embodiment, the contact trench 53 penetrates the emitter region 51.

[0070] The contact trench 53 is formed at a distance from the trench gate structure 27 in the first direction X. The contact trench 53 extends in a strip shape along the trench gate structure 27 in a plan view.

[0071] The FET structure 46 includes a p-type semiconductor layer formed in the body region 50 along the bottom wall of the contact trench 53. ＋ The p-type impurity concentration of the contact region 54 is greater than the p-type impurity concentration of the body region 50. The p-type impurity concentration of the contact region 54 is 1.0×10 １９ cm －３ Above 1.0 x 10 ２０ cm －３ It may be the following:

[0072] The contact region 54 is exposed from the bottom wall of the contact trench 53. In a plan view, the contact region 54 extends in a strip shape along the contact trench 53. The bottom of the contact region 54 is formed in a region between the bottom wall of the contact trench 53 and the bottom of the body region 50 in the normal direction Z.

[0073] Thus, in the FET structure 46, the gate electrode layer 49 faces the body region 50 and the emitter region 51, with the gate insulating layer 48 sandwiched therebetween. In this configuration, the gate electrode layer 49 also faces the carrier storage region 52, with the gate insulating layer 48 sandwiched therebetween. The channel of the IGBT is formed in the region in the body region 50 between the emitter region 51 and the drift region 41 (carrier storage region 52). The on / off of the channel is controlled by a gate signal.

[0074] Each IGBT region 24 includes an emitter trench structure 28 in the first main surface 3 of the semiconductor chip 2. Specifically, each IGBT region 24 includes a plurality of emitter trench structures 28 formed on both sides of an FET structure 46. The emitter trench structures 28 are formed in regions adjacent to the FET structures 46 in the surface layer portion of the first main surface 3. The emitter trench structures 28 are formed in a strip shape extending along the second direction Y in a plan view. The emitter trench structures 28 may be strip-shaped and parallel to the trench gate structures 27.

[0075] The emitter trench structure 28 includes an emitter trench 55, an emitter insulating layer 56, and an emitter potential electrode layer 57. The emitter trench 55 is formed in the first main surface 3 of the semiconductor chip 2. The emitter trench 55 includes sidewalls and a bottom wall. The sidewalls of the emitter trench 55 may be formed perpendicular to the first main surface 3.

[0076] The sidewalls of the emitter trench 55 may slope downward from the first main surface 3 toward the bottom wall. The emitter trench 55 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The emitter region 51, the body region 50, and the carrier storage region 52 are exposed from the sidewalls (outer sidewalls) of the emitter trench 55 facing the FET structure 46. The bottom wall of the emitter trench 55 may be formed parallel to the first main surface 3. The bottom wall of the emitter trench 55 may be formed in a curved shape toward the second main surface 4. The emitter trench 55 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewalls and bottom wall of the emitter trench 55. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4 of the semiconductor chip 2.

[0077] The depth D3 of the emitter trench 55 may be 2 μm or more and 10 μm or less. The depth D3 of the emitter trench 55 may be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less. The depth D3 of the emitter trench 55 may be equal to the depth D1 of the gate trench 47.

[0078] The width of the emitter trench 55 may be 0.5 μm or more and 3 μm or less. The width of the emitter trench 55 is the width of the emitter trench 55 in the first direction X. The width of the emitter trench 55 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the emitter trench 55 may be equal to the width of the gate trench 47.

[0079] The emitter insulating layer 56 is formed in a film shape along the inner wall of the emitter trench 55. The emitter insulating layer 56 defines a recess space within the emitter trench 55. In this embodiment, the emitter insulating layer 56 includes a silicon oxide film. The emitter insulating layer 56 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0080] The emitter potential electrode layer 57 is embedded in the emitter trench 55 with the emitter insulating layer 56 sandwiched therebetween. Specifically, the emitter potential electrode layer 57 is embedded in a recess space defined by the emitter insulating layer 56 in the emitter trench 55. The emitter potential electrode layer 57 may include conductive polysilicon. The emitter potential electrode layer 57 is controlled by an emitter signal.

[0081] 5, each diode region 25 is formed in the surface layer portion of the second main surface 4 of the semiconductor chip 2. ＋ The n-type impurity concentration of the cathode region 58 is greater than the n-type impurity concentration of the drift region 41. The n-type impurity concentration of the cathode region 58 is 1.0×10 １９ cm －３ Above 1.0 x 10 ２０ cm －３ The cathode region 58 is exposed from the second main surface 4. The cathode region 58 forms an ohmic contact with the collector terminal electrode 43.

[0082] Each diode region 25 includes a cell isolation structure 60 that defines a diode cell region 59. Specifically, each diode region 25 includes a plurality of cell isolation structures 60 that define the plurality of diode cell regions 59. The cell isolation structures 60 correspond to the diode-side trench structures 29 in FIG. 3 .

[0083] The cell isolation structure 60 includes a cell isolation trench 61, a cell isolation insulating layer 62, and a cell isolation electrode layer 63. The cell isolation trench 61 is formed in the first main surface 3. The cell isolation trench 61 includes a sidewall and a bottom wall. The sidewall of the cell isolation trench 61 may be formed perpendicular to the first main surface 3.

[0084] The sidewalls of the cell separation trench 61 may slope downward from the first main surface 3 toward the bottom wall. The cell separation trench 61 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The bottom wall of the cell separation trench 61 may be formed parallel to the first main surface 3. The bottom wall of the cell separation trench 61 may be formed in a curved shape toward the second main surface 4. The cell separation trench 61 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewalls and bottom wall of the cell separation trench 61. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4.

[0085] The depth D2 of the cell isolation trench 61 may be 2 μm or more and 10 μm or less. The depth D2 of the cell isolation trench 61 may be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less. The depth D2 of the cell isolation trench 61 may be equal to the depth D1 of the gate trench 47. The depth D2 of the cell isolation trench 61 may be defined as the distance between the deepest depth position of the bottom wall of the cell isolation trench 61 and the first main surface 3.

[0086] The width of the cell isolation trench 61 may be 0.5 μm or more and 3 μm or less. The width of the cell isolation trench 61 is the width of the cell isolation trench 61 in the first direction X. The width of the cell isolation trench 61 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the cell isolation trench 61 may be equal to the width of the gate trench 47.

[0087] The cell isolation insulating layer 62 is formed in the form of a film along the inner wall of the cell isolation trench 61. The cell isolation insulating layer 62 defines a recess space within the cell isolation trench 61. In this embodiment, the cell isolation insulating layer 62 includes a silicon oxide film. The cell isolation insulating layer 62 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0088] The cell isolation electrode layer 63 is embedded in the cell isolation trench 61 with the cell isolation insulating layer 62 sandwiched therebetween. Specifically, the cell isolation electrode layer 63 is embedded in a recess space defined by the cell isolation insulating layer 62 in the cell isolation trench 61. The cell isolation electrode layer 63 is controlled by an emitter signal. The cell isolation electrode layer 63 may include conductive polysilicon.

[0089] Each diode region 25 is formed in the surface layer of the first main surface 3 of the semiconductor chip 2. － The anode region 64 includes a p-type anode region 64 (first impurity region). The p-type impurity concentration of the anode region 64 may be equal to or lower than the p-type impurity concentration of the body region 50. The p-type impurity concentration of the anode region 64 is preferably lower than the p-type impurity concentration of the body region 50. The p-type impurity concentration of the anode region 64 is 1.0×10 １５ cm －３ Above 1.0 x 10 １８ cm －３ It may be less than.

[0090] The anode regions 64 are formed in each diode cell region 59. Therefore, the plurality of anode regions 64 are arranged at equal intervals in the first direction X, and are formed in a striped pattern as a whole.

[0091] The anode region 64 forms a pn junction 65 with the semiconductor chip 2. This forms a pn junction diode D with the anode region 64 as the anode and the semiconductor chip 2 (cathode region 58) as the cathode.

[0092] The anode region 64 includes a diode trench 66 formed in the first main surface 3 of the semiconductor chip 2. In this embodiment, the anode region 64 includes a plurality of diode trenches 66 formed on both sides of the cell isolation structure 60. The diode trenches 66 expose the anode region 64. The diode trenches 66 are formed at intervals from the cell isolation structure 60 in the first direction X. The diode trenches 66 extend in a strip shape along the cell isolation structure 60 in a plan view.

[0093] The semiconductor device 1 includes an interlayer insulating layer 67 formed on the first main surface 3 of the semiconductor chip 2. The interlayer insulating layer 67 is formed in a film shape along the first main surface 3, and selectively covers the first main surface 3. Specifically, the interlayer insulating layer 67 selectively covers the IGBT region 24 and the diode region 25.

[0094] The interlayer insulating layer 67 may contain silicon oxide or silicon nitride, or may contain at least one of non-doped silicate glass (NSG), phosphorus silicate glass (PSG), and boron phosphorus silicate glass (BPSG).

[0095] The thickness of the interlayer insulating layer 67 may be 0.1 μm or more and 1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, or 0.8 μm or more and 1 μm or less.

[0096] In this embodiment, the interlayer insulating layer 67 has a stacked structure including a first insulating layer 68, a second insulating layer 69, and a third insulating layer 70, stacked in this order from the first main surface 3 side. The first insulating layer 68 preferably includes silicon oxide (e.g., a thermal oxide film). The second insulating layer 69 preferably includes an NGS layer. The second insulating layer 69 may include a PSG layer or a BPSG layer instead of the NGS layer. The third insulating layer 70 preferably includes a BPSG layer. The third insulating layer 70 may include an NGS layer or a PSG layer instead of the BPSG layer. The third insulating layer 70 preferably includes an insulating material having properties different from those of the second insulating layer 69.

[0097] The first insulating layer 68 is formed in the form of a film on the first main surface 3. The first insulating layer 68 is continuous with the gate insulating layer 48, the emitter insulating layer 56, and the cell isolation insulating layer 62. The second insulating layer 69 is formed in the form of a film on the first insulating layer 68. The third insulating layer 70 is formed in the form of a film on the second insulating layer 69.

[0098] The thickness of the first insulating layer 68 may be 500 Å to 2000 Å, 500 Å to 1000 Å, 1000 Å to 1500 Å, or 1500 Å to 2000 Å.

[0099] The thickness of the second insulating layer 69 may be 500 Å to 4000 Å, 500 Å to 1000 Å, 1000 Å to 1500 Å, 1500 Å to 2000 Å, 2000 Å to 2500 Å, 2500 Å to 3000 Å, 3000 Å to 3500 Å, or 3500 Å to 4000 Å.

[0100] The thickness of the third insulating layer 70 may be 1000 Å to 8000 Å, 1000 Å to 2000 Å, 2000 Å to 4000 Å, 4000 Å to 6000 Å, or 6000 Å to 8000 Å.

[0101] The interlayer insulating layer 67 includes an emitter opening 71. The emitter opening 71 exposes the contact trench 53. The emitter opening 71 communicates with the contact trench 53. In this embodiment, the contact trench 53 is formed on the first main surface 3, penetrating the first insulating layer 68 and the second insulating layer 69. The emitter opening 71 penetrates the third insulating layer 70 and exposes the contact trench 53. The emitter opening 71 forms an opening with the contact trench 53. The edge of the emitter opening 71 is curved inward in the interlayer insulating layer 67. As a result, the emitter opening 71 has an opening width greater than the opening width of the contact trench 53.

[0102] 5 , the interlayer insulating layer 67 includes a diode opening 72. The diode opening 72 exposes the diode trench 66. The diode opening 72 is in communication with the diode trench 66. In this embodiment, the diode opening 72 is formed on the first main surface 3, penetrating the first insulating layer 68 and the second insulating layer 69. The diode opening 72 penetrates the third insulating layer 70 and exposes the diode trench 66. The diode opening 72 forms an opening between itself and the diode trench 66. The edge of the diode opening 72 is curved inward in the interlayer insulating layer 67. As a result, the diode opening 72 has a width greater than the width of the diode trench 66.

[0103] The semiconductor device 1 includes an emitter plug electrode 73 embedded in a portion of the interlayer insulating layer 67 that covers the IGBT region 24. The emitter plug electrode 73 penetrates the interlayer insulating layer 67 and is electrically connected to the emitter region 51 and the contact region 54. Specifically, the emitter plug electrode 73 is embedded in the contact trench 53. The emitter plug electrode 73 is electrically connected to the emitter region 51 and the contact region 54 within the contact trench 53.

[0104] In this embodiment, the emitter plug electrode 73 has a layered structure including a barrier electrode layer 74 and a main electrode layer 75. The barrier electrode layer 74 is formed in a film shape along the inner wall of the contact trench 53 so as to be in contact with the interlayer insulating layer 67. The barrier electrode layer 74 defines a recess space within the contact trench 53.

[0105] The barrier electrode layer 74 may have a single-layer structure including a titanium layer or a titanium nitride layer, or may have a laminated structure including a titanium layer and a titanium nitride layer, in which case the titanium nitride layer may be laminated on the titanium layer.

[0106] The main electrode layer 75 is embedded in the contact trench 53 with the barrier electrode layer 74 sandwiched therebetween. Specifically, the main electrode layer 75 is embedded in a recess space defined by the barrier electrode layer 74 in the contact trench 53. The main electrode layer 75 may contain tungsten.

[0107] The semiconductor device 1 includes a diode plug electrode 76 embedded in the diode opening 72. The diode plug electrode 76 is electrically connected to the anode region 64 within the diode opening 72. The diode plug electrode 76 has a structure corresponding to that of the emitter plug electrode 73. The description of the emitter plug electrode 73 applies mutatis mutandis to the description of the diode plug electrode 76. Structures of the diode plug electrode 76 that correspond to those described for the emitter plug electrode 73 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0108] The emitter terminal electrode 12 is formed on the interlayer insulating layer 67. The emitter terminal electrode 12 may contain at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy.

[0109] The emitter terminal electrode 12 may have a single layer structure containing any one of these conductive materials, or may have a multilayer structure in which at least two of these conductive materials are laminated in any order.

[0110] The thickness of the emitter terminal electrode 12 may be 1.0 μm or more and 6.0 μm or less, 1.0 μm or more and 2.0 μm or less, 2.0 μm or more and 4.0 μm or less, or 4.0 μm or more and 6.0 μm or less.

[0111] In this embodiment, the emitter terminal electrode 12 has a layered structure including a first electrode layer 77, a second electrode layer 78, and a third electrode layer 79, which are layered in this order from the first main surface 3 side. The first electrode layer 77 preferably contains an aluminum-silicon-copper alloy (Al—Si—Cu). The second electrode layer 78 preferably contains titanium nitride (TiN). The second electrode layer 78 may also be referred to as a barrier layer. The third electrode layer 79 preferably contains an aluminum-copper alloy (Al—Cu).

[0112] The emitter terminal electrode 12 is electrically connected to the emitter region 51 and the contact region 54 via an emitter plug electrode 73 on the interlayer insulating layer 67. Specifically, the emitter terminal electrode 12 extends from above the interlayer insulating layer 67 into the emitter opening 71. The emitter terminal electrode 12 is electrically connected to the emitter plug electrode 73 in the emitter opening 71. As a result, the emitter terminal electrode 12 is electrically connected to the emitter region 51 and the contact region 54 via the emitter plug electrode 73.

[0113] 5 , the emitter terminal electrode 12 is further electrically connected to the anode region 64 via a diode plug electrode 76 on the interlayer insulating layer 67. Specifically, the emitter terminal electrode 12 extends into the diode opening 72 from above the interlayer insulating layer 67. The emitter terminal electrode 12 functions as an anode terminal electrode in the diode region 25.

[0114] The emitter terminal electrode 12 is in contact with the inner wall of the diode opening 72. The emitter terminal electrode 12 is electrically connected to the anode region 64 in the diode opening 72. The emitter terminal electrode 12 is electrically connected to the diode plug electrode 76 in the diode opening 72.

[0115] Although specific illustrations are omitted, the gate terminal electrode 7, the first sense terminal electrode 8, the second sense terminal electrode 9, the current detection terminal electrode 10 and the open terminal electrode 11 are formed on the interlayer insulating layer 67, similar to the emitter terminal electrode 12.

[0116] The terminal electrodes 7 to 12 may each contain at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy. The terminal electrodes 7 to 12 may each have a single-layer structure containing one of these conductive materials. The terminal electrodes 7 to 12 may each have a layered structure in which at least two of these conductive materials are layered in any order. In this embodiment, the terminal electrodes 7 to 12 contain the same conductive material as the emitter terminal electrode 12.

[0117] When conducting wires (e.g., bonding wires) are connected to each of the terminal electrodes 7 to 12, a single-layer electrode made of a nickel layer or a gold layer, or a laminated electrode including a nickel layer and a gold layer, may be formed on each of the terminal electrodes 7 to 12. In the laminated electrode, the gold layer may be formed on the nickel layer.

[0118] Furthermore, the plurality of wirings 13 to 15 may each contain at least one of aluminum, copper, an aluminum-silicon-copper alloy, an aluminum-silicon alloy, and an aluminum-copper alloy. The plurality of wirings 13 to 15 may each have a single-layer structure containing any one of these conductive materials. The plurality of wirings 13 to 15 may each have a layered structure in which at least two of these conductive materials are layered in any order. In this embodiment, the plurality of terminal electrode wirings 13 to 15 contain the same conductive material as the emitter terminal electrode 12.

[0119] Next, other embodiments of the cross-sectional structure of the active region 18 will be described. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 3. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 3. The connection between the third contact layer 40 and the emitter terminal electrode 12, and the connection between the second contact layer 39 and the emitter terminal electrode 12 will be described with reference to Figs. 6 and 7. In the following, structures corresponding to those already described with respect to the semiconductor device 1 will be designated by the same reference numerals, and descriptions thereof will be omitted.

[0120] 6 , the emitter potential electrode layer 57 of the emitter trench structure 28 has an extraction electrode layer 80 that is extracted from the emitter trench 55 onto the first main surface 3. The extraction electrode layer 80 corresponds to the third contact layer 40 of FIG. 3 . Specifically, the extraction electrode layer 80 is formed inside the interlayer insulating layer 67. The extraction electrode layer 80 is extracted onto the first insulating layer 68 and is located in the region between the first insulating layer 68 and the third insulating layer 70. The extraction electrode layer 80 is electrically connected to the emitter terminal electrode 12. An emitter signal applied to the extraction electrode layer 80 is transmitted to the emitter potential electrode layer 57 via the extraction electrode layer 80.

[0121] The interlayer insulating layer 67 includes a first opening 81. The first opening 81 exposes the extraction electrode layer 80 in the IGBT region 24. The first opening 81 is formed so that the opening width narrows from the opening side toward the bottom wall side.

[0122] The semiconductor device 1 includes a first plug electrode 82 embedded in the first opening 81. The first plug electrode 82 is electrically connected to the extraction electrode layer 80 within the first opening 81. The first plug electrode 82 has a structure corresponding to that of the emitter plug electrode 73. The description of the emitter plug electrode 73 applies mutatis mutandis to the description of the first plug electrode 82. The structures of the first plug electrode 82 that correspond to those described for the emitter plug electrode 73 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0123] The emitter terminal electrode 12 is electrically connected to the emitter potential electrode layer 57 via a first plug electrode 82 and an extraction electrode layer 80 on the interlayer insulating layer 67 .

[0124] 7 , the cell isolation electrode layer 63 of the cell isolation structure 60 has an extraction electrode layer 83 that is extended from the cell isolation trench 61 onto the first main surface 3. The extraction electrode layer 83 corresponds to the second contact layer 39 in FIG. 3 . Specifically, the extraction electrode layer 83 is formed inside the interlayer insulating layer 67. The extraction electrode layer 83 is extended onto the first insulating layer 68 and is located in the region between the first insulating layer 68 and the third insulating layer 70. The extraction electrode layer 83 is electrically connected to the emitter terminal electrode 12. An emitter signal applied to the extraction electrode layer 83 is transmitted to the cell isolation electrode layer 63 via the extraction electrode layer 83.

[0125] The interlayer insulating layer 67 includes a second opening 84. The second opening 84 exposes the extraction electrode layer 83 in the diode region 25. The second opening 84 is formed so that the opening width narrows from the opening side toward the bottom wall side. The second opening 84 is formed in a strip shape extending in the first direction X.

[0126] The semiconductor device 1 includes a second plug electrode 85 embedded in the second opening 84. The second plug electrode 85 is electrically connected to the extraction electrode layer 83 within the second opening 84. The second plug electrode 85 has a structure corresponding to that of the emitter plug electrode 73. The description of the emitter plug electrode 73 applies mutatis mutandis to the description of the second plug electrode 85. The structures of the second plug electrode 85 that correspond to those described for the emitter plug electrode 73 are given the same reference numerals, and descriptions thereof will be omitted.

[0127] The emitter terminal electrode 12 is electrically connected to the cell separation electrode layer 63 via a second plug electrode 85 and an extraction electrode layer 83 on the interlayer insulating layer 67 .

[0128] Next, other embodiments of the cross-sectional structure of the active region 18 will be described. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 3. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 3. FIG. 10 is a cross-sectional view taken along line X-X in FIG. 3. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 3. With reference to FIGS. 8 to 11, the connection between the first contact layer 38 and the gate extension electrode 33 (gate wiring 13), and the structure of the semiconductor chip 2 directly below the gate extension electrode 33 will be described. In the following, structures corresponding to those already described with respect to the semiconductor device 1 will be assigned the same reference numerals, and descriptions thereof will be omitted.

[0129] 8 to 11 , the semiconductor device 1 includes a p-type well region 87 formed in a surface layer portion of the first main surface 3 in a region (a boundary region 86 between adjacent partition regions 20) directly below the gate extension electrode 33. In this embodiment, the well region 87 has a higher p-type impurity concentration than the body region 50. Of course, the well region 87 may have a lower p-type impurity concentration than the body region 50.

[0130] The well region 87 is formed in a strip shape extending in the first direction X along the boundary region 86 in a plan view. The well region 87 is formed in a layer shape extending along the first main surface 3 and is exposed from the first main surface 3. With reference to FIG. 8 , the well region 87 is formed in a region sandwiched between a plurality of trench gate structures 27 and a region sandwiched between a plurality of emitter trench structures 28. With reference to FIG. 9 , the well region 87 is formed in a region sandwiched between a plurality of cell isolation structures 60.

[0131] The well region 87 is preferably formed deeper than the body region 50 and the anode region 64. It is particularly preferable that the well region 87 is formed deeper than the trench gate structures 27, the emitter trench structures 28, and the cell isolation structures 60.

[0132] 8 and 9 , the well region 87 has portions that cover the bottom walls of the plurality of trench gate structures 27 and the plurality of emitter trench structures 28. The well region 87 traverses the plurality of trench gate structures 27 and the plurality of emitter trench structures 28 in the first direction X, collectively covering these bottom walls.

[0133] 9 , the well region 87 has a portion covering the bottom walls of the plurality of cell isolation structures 60. The well region 87 traverses the plurality of cell isolation structures 60 in the first direction X, collectively covering these bottom walls. The well region 87 also traverses the plurality of trench gate structures 27 and the plurality of cell isolation structures 60 in the first direction X, collectively covering these bottom walls. Referring to FIG. 9 , the well region 87 straddles the boundary between the IGBT region 24 and the diode region 25 in the first direction X.

[0134] 10 and 11 , the well region 87 crosses the gate extension electrode 33 in the second direction Y. In this embodiment, the well region 87 has a width in the second direction Y that is greater than the width of the boundary region 86. The well region 87 has lead-out portions 88 that are led out from the boundary region 86 into the multiple partition regions 20.

[0135] 10 , well region 87 is integrally connected to body region 50 of IGBT region 24. An extension portion 88 of well region 87 is connected to the side portion of body region 50. Well region 87 has an upper protrusion 89 that protrudes above the upper end of body region 50 (the boundary between body region 50 and emitter region 51).

[0136] 11 , the well region 87 is integrally connected to the anode region 64 of the diode region 25. An extension portion 88 of the well region 87 is connected to the side portion of the anode region 64. The well region 87 has an upper end at the same height as the upper end (first main surface 3) of the anode region 64.

[0137] 8 to 11 , the gate electrode layer 49 of the trench gate structure 27 has an extraction electrode layer 90 that is extracted from the gate trench 47 onto the first main surface 3. The extraction electrode layer 90 is the first contact layer 38 (first electrode layer 34) in FIG. 3 . Specifically, the extraction electrode layer 90 is formed inside the interlayer insulating layer 67. The extraction electrode layer 90 is extracted onto the first insulating layer 68 and is interposed in the region between the first insulating layer 68 and the third insulating layer 70. The extraction electrode layer 90 is electrically connected to the gate extension electrode 33. A gate signal applied to the extraction electrode layer 90 is transmitted to the gate electrode layer 49 via the extraction electrode layer 90.

[0138] 9 to 11 , the interlayer insulating layer 67 includes gate openings 91. The gate openings 91 expose the extraction electrode layer 90 in the IGBT region 24. The gate openings 91 are formed so that the opening width narrows from the opening side toward the bottom wall side. In this embodiment, a pair of gate openings 91 is formed along the gate extension electrode 33. Referring to FIG. 9 , each gate opening 91 extends in a strip shape in the first direction X, and has an end directly above the boundary between the IGBT region 24 and the diode region 25.

[0139] The semiconductor device 1 includes a gate plug electrode 92 embedded in a gate opening 91. The gate plug electrode 92 is electrically connected to the extraction electrode layer 90 within the gate opening 91. The gate plug electrode 92 has a structure corresponding to that of the emitter plug electrode 73. The description of the emitter plug electrode 73 applies mutatis mutandis to the description of the gate plug electrode 92. Structures of the gate plug electrode 92 that correspond to those described for the emitter plug electrode 73 are given the same reference numerals, and descriptions thereof will be omitted.

[0140] The gate extension electrode 33 is electrically connected to the gate electrode layer 49 on the interlayer insulating layer 67 via a gate plug electrode 92 and an extraction electrode layer 90. The second electrode layer 35 of the gate extension electrode 33 has a structure corresponding to that of the emitter terminal electrode 12. The description of the emitter terminal electrode 12 applies mutatis mutandis to the description of the second electrode layer 35 of the gate extension electrode 33. Structures in the second electrode layer 35 of the gate extension electrode 33 that correspond to the structures described for the emitter terminal electrode 12 are given the same reference numerals, and descriptions thereof will be omitted.

[0141] 3 to 11, the multiple diode-side trench structures 29 are formed in a stripe pattern as a whole. The multiple diode-side trench structures 29 cross from one side to the other in the second direction Y directly below the gate wiring 13. In other words, the multiple diode-side trench structures 29 are not separated into partitioned regions 20. This makes it possible to reduce the number of terminations 32 of the multiple diode-side trench structures 29. In this embodiment, the terminations 32 of the multiple diode-side trench structures 29 are selectively formed only in the peripheral region 19.

[0142] Because the terminations 32 of the multiple diode-side trench structures 29 have a rounded shape, they are more likely to have shape abnormalities due to recess variations than striped trench structures. Therefore, by reducing the number of terminations 32 of the multiple diode-side trench structures 29, it is possible to suppress dielectric breakdown at the terminations 32. As a result, it is possible to improve the ESD (Electro-Static Discharge) resistance of the semiconductor device 1.

[0143] Next, another form of the planar structure of the active region 18 will be described. Fig. 12 is an enlarged view of the portion surrounded by XII in Fig. 2, showing some of the multiple IGBT regions 24 and multiple diode regions 25. The planar structure of the IGBT regions 24 and diode regions 25 described below may be applied to all of the IGBT regions 24 and all of the diode regions 25 of the semiconductor chip 2, or may be applied selectively to some of the IGBT regions 24 and diode regions 25. In other words, the planar structure described below is a structure that can be applied to at least one IGBT region 24 and one diode region 25.

[0144] 12 , the multiple diode-side trench structures 29 do not cross the gate wiring 13, but have termination portions 32 inside the diode region 25 away from the gate wiring 13 in the second direction Y. The second contact layer 39 collectively covers the termination portions 32 of the multiple diode-side trench structures 29. The second contact layer 39 is electrically connected to the diode-side trench structures 29 via the termination portions 32.

[0145] The semiconductor device 1 includes a plurality of gate-auxiliary trench structures 93 formed on the first main surface 3. The plurality of gate-auxiliary trench structures 93 are formed directly below the gate extension electrodes 33 and are covered by the gate extension electrodes 33 in plan view. The plurality of gate-auxiliary trench structures 93 are trench structures that are long along the second direction Y.

[0146] 12 , the multiple gate-assist trench structures 93 are multiple elliptical trench structures whose major axis direction coincides with the second direction Y. The multiple gate-assist trench structures 93 may be formed in a band shape extending along the second direction Y in a plan view. The multiple gate-assist trench structures 93 are formed in a stripe shape as a whole. The multiple gate-assist trench structures 93 have termination portions 94 on both sides in the second direction Y.

[0147] The termination portions 94 of the gate-assist trench structures 93 are formed one for each pair of gate-assist trench structures 93. The termination portions 94 connect adjacent gate-assist trench structures 93 in the region (boundary region 86 in FIGS. 10 and 11 ) directly below the gate extension electrode 33. The termination portions 94 are formed in a round shape in plan view.

[0148] The diode-side trench structure 29 and the gate-assist trench structure 93 are formed on the same imaginary straight line 99 (the line shown by the dashed dotted line in FIG. 12 ) extending in the second direction Y. Therefore, the gate-assist trench structure 93 may be a trench structure formed on an extension of the diode-side trench structure 29 in the second direction Y.

[0149] The first electrode layer 34 of the gate extension electrode 33 is formed in a strip shape that extends continuously across the alternatingly arranged IGBT regions 24 and diode regions 25. The first electrode layer 34 is strip-shaped and has a constant width in the second direction Y. Unlike the structure in FIG. 3 , the first electrode layer 34 is disposed directly below the second electrode layer 35 in both the non-contact section 36 and the contact section 37. As a result, the first electrode layer 34 collectively covers the trench gate structures 27 and the gate-assist trench structures 93. In this configuration, the entire gate-assist trench structure 93 from one end to the other in the second direction Y is covered by the first electrode layer 34.

[0150] Next, a cross-sectional structure of the gate-assist trench structure 93 will be described. Fig. 13 is a cross-sectional view taken along line XIII-XIII in Fig. 12. In the following, structures corresponding to those already described with respect to the semiconductor device 1 will be denoted by the same reference numerals, and descriptions thereof will be omitted.

[0151] The gate-auxiliary trench structure 93 includes a gate-auxiliary trench 95, a gate-auxiliary insulating layer 96, and a gate-auxiliary electrode layer 97. The gate-auxiliary trench 95 is formed on the first main surface 3 of the semiconductor chip 2. The gate-auxiliary trench 95 includes a sidewall and a bottom wall. The sidewall of the gate-auxiliary trench 95 may be formed perpendicular to the first main surface 3.

[0152] The sidewalls of the gate-auxiliary trench 95 may slope downward from the first main surface 3 toward the bottom wall. The gate-auxiliary trench 95 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The well region 87 is exposed from the sidewalls of the gate-auxiliary trench 95. The bottom wall of the gate-auxiliary trench 95 may be formed parallel to the first main surface 3. The bottom wall of the gate-auxiliary trench 95 may be formed in a curved shape toward the second main surface 4. The gate-auxiliary trench 95 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewall and bottom wall of the gate-auxiliary trench 95. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4 of the semiconductor chip 2.

[0153] The depth D4 of the gate-assist trench 95 may be 2 μm or more and 10 μm or less. The depth D4 of the gate-assist trench 95 may be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less. The depth D4 of the gate-assist trench 95 may be equal to the depth D1 of the gate trench 47.

[0154] The width of the gate-assist trench 95 may be 0.5 μm or more and 3 μm or less. The width of the gate-assist trench 95 is the width of the gate-assist trench 95 in the first direction X. The width of the gate-assist trench 95 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the gate-assist trench 95 may be equal to the width of the gate trench 47.

[0155] The gate auxiliary insulating layer 96 is formed in the form of a film along the inner wall of the gate auxiliary trench 95. The gate auxiliary insulating layer 96 defines a recess space within the gate auxiliary trench 95. In this embodiment, the gate auxiliary insulating layer 96 includes a silicon oxide film. The gate auxiliary insulating layer 96 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0156] The gate auxiliary electrode layer 97 is embedded in the gate auxiliary trench 95 with the gate auxiliary insulating layer 96 sandwiched therebetween. Specifically, the gate auxiliary electrode layer 97 is embedded in a recess space defined by the gate auxiliary insulating layer 96 in the gate auxiliary trench 95. The gate auxiliary electrode layer 97 may include conductive polysilicon. The gate auxiliary electrode layer 97 is controlled to the gate potential.

[0157] The extraction electrode layer 90 extended from the gate trench 47 onto the first main surface 3 is integrally connected to the gate auxiliary electrode layer 97. In other words, the extraction electrode layer 90 is extended onto the first main surface 3 integrally from the gate electrode layer 49 and the gate auxiliary electrode layer 97, and collectively covers the gate trench 47 and the gate auxiliary trench 95.

[0158] Next, variations in the pattern of the gate-assist trench structure 93 will be described with reference to FIGS.

[0159] 14 , the plurality of gate-assist trench structures 93 may be formed in the shape of independent strips. Each gate-assist trench structure 93 is a strip-shaped trench structure whose length direction coincides with the second direction Y. In this form, the terminal end 98 of each gate-assist trench structure 93 is located inside both side edges of the first electrode layer 34 in the second direction Y and is covered by the first electrode layer 34.

[0160] 15 , the plurality of gate-assist trench structures 93 may be formed in the shape of independent strips. Each gate-assist trench structure 93 is a strip-shaped trench structure whose length direction coincides with the second direction Y. In this form, the terminal end 98 of each gate-assist trench structure 93 protrudes outward beyond both side edges of the first electrode layer 34 in the second direction Y and is exposed from the first electrode layer 34.

[0161] 16, the plurality of gate-assist trench structures 93 are long trench structures extending along the first direction X. While Fig. 16 shows a structure obtained by rotating the elliptical trench structure of Fig. 12 by 90 degrees, it goes without saying that the structure may also be a structure obtained by rotating the strip-shaped trench structure of Figs. 14 and 15 by 90 degrees.

[0162] As described above, according to the structure shown in FIGS. 12 to 16, a plurality of gate-assist trench structures 93 controlled by the gate potential are formed. This increases the gate capacitance, thereby improving the ESD tolerance of the gate. Furthermore, the plurality of gate-assist trench structures 93 are arranged in the empty space directly below the gate extension electrode 33 sandwiched between the plurality of diode-side trench structures 29. This makes it possible to avoid an increase in chip area or gate trench density due to the gate-assist trench structures 93. This makes it possible to suppress an increase in chip cost and an increase in process difficulty.

[0163] Furthermore, as shown in Figures 12, 14, and 15, if the multiple gate auxiliary trench structures 93 are long trenches along the second direction Y, the gate extension electrode 33 can be reliably connected to the gate auxiliary trench structure 93 even if the gate extension electrode 33 is misaligned in the second direction Y.

[0164] Next, one embodiment of the planar structure near the gate terminal electrode 7 will be described. Fig. 17 is an enlarged view of the portion surrounded by XVII in Fig. 2, showing a portion of the multiple IGBT regions 24 and multiple diode regions 25. The planar structure of the IGBT regions 24 and diode regions 25 described below may be applied to all of the IGBT regions 24 and all of the diode regions 25 of the semiconductor chip 2, or may be applied selectively to some of the IGBT regions 24 and diode regions 25. In other words, the planar structure described below is a structure that can be applied to at least one IGBT region 24 and diode region 25.

[0165] In this embodiment, a first end (the end on the side of the side surface 5B) of the RC-IGBT array 26 is formed by a diode region 25. This diode region 25 is a region adjacent to the multiple terminal electrodes 7 to 11, and may be referred to as a pad-adjacent diode region 25A. The pad-adjacent diode region 25A is adjacent to the gate terminal electrode 7 in the first direction X. "Adjacent to the gate terminal electrode 7" may mean that no other diode region 25 or IGBT region 24 is interposed between the gate terminal electrode 7 and the pad-adjacent diode region 25A in the first direction X.

[0166] In the pad-adjacent diode region 25A, the multiple diode-side trench structures 29 do not cross the gate wiring 13 and have termination portions 32 inside the diode region 25 away from the gate wiring 13 in the second direction Y. The second contact layer 39 collectively covers the termination portions 32 of the multiple diode-side trench structures 29. The second contact layer 39 is electrically connected to the diode-side trench structures 29 via the termination portions 32.

[0167] The gate extension electrode 33 includes an annular peripheral portion 100 that surrounds the gate terminal electrode 7 and an extension portion 101 that extends in a strip shape in the first direction X from the peripheral portion 100 .

[0168] The peripheral portion 100 surrounds the entire periphery of the gate terminal electrode 7, but may be partially separated. The end of the peripheral portion 100 on the side surface 5B side is integrally connected to the first portion 16 of the gate wiring 13. An annular gap region 102 is formed between the peripheral portion 100 and the gate terminal electrode 7.

[0169] The extension portion 101 extends in the first direction X from an end portion of the peripheral portion 100 opposite to the end portion on the side surface 5B side. The extension portion 101 extends in the first direction X in a strip shape.

[0170] 17 , the peripheral portion 100 and the extending portion 101 are formed by a laminated structure of a resistive layer 103 and a wiring layer 104. The lower resistive layer 103 in the laminated structure is the white region, and the upper wiring layer 104 is the hatched region. The resistive layer 103 also serves as the first electrode layer 34 and first contact layer 38 described above. The wiring layer 104 also serves as the second electrode layer 35 described above.

[0171] The laminated structure of the resistance layer 103 and the wiring layer 104 may constitute the gate extension electrode 33, and a part of it may also constitute the gate terminal electrode 7. In Fig. 17, a part of the resistance layer 103 forms an island-shaped pad support layer 105, and the second electrode layer 35 constituting the peripheral portion 100 and the gate terminal electrode 7 is formed on the pad support layer 105 independently of each other.

[0172] The second electrode layer 35 of the peripheral portion 100 is connected to the pad support layer 105 via peripheral contacts 106. In this embodiment, a pair of peripheral contacts 106 are formed facing each other across the gate terminal electrode 7 in the first direction X. One of the pair of peripheral contacts 106 is formed at the end of the peripheral portion 100 on the side surface 5B side and the other at the opposite end.

[0173] The second electrode layer 35 of the gate terminal electrode 7 is connected to the pad support layer 105 via pad contacts 107. In this embodiment, a pair of pad contacts 107 are formed adjacent to the peripheral contacts 106 in the first direction X. One of the pair of pad contacts 107 is formed at a position adjacent to each peripheral contact 106.

[0174] The semiconductor device 1 includes a gate resistor 108 adjacent to the gate terminal electrode 7. The gate resistor 108 is selectively formed in a portion of the gate extension electrode 33 that crosses the diode region 25, avoiding a portion directly above the trench gate structure 27. In this embodiment, the gate resistor 108 is formed in the extension portion 101 at a position adjacent to the termination portion 32 of the diode-side trench structure 29 in the second direction Y. More specifically, the gate resistor 108 is formed in a region sandwiched between a plurality of diode-side trench structures 29 that face each other with the gate extension electrode 33 in between.

[0175] In a region adjacent to the terminal end 32, the wiring layer 104 of the gate extension electrode 33 (extension 101) is divided into one side and the other side in the first direction X. The gate resistor 108 is formed by a portion of the resistance layer 103 sandwiched between the divided wiring layers 104.

[0176] The extension portion 101 includes a first extension portion 109 close to the gate terminal electrode 7 and a second extension portion 110 on the opposite side. The first extension portion 109 and the second extension portion 110 are each connected to the resistive layer 103 via a resistive contact 111.

[0177] The gate resistor 108 is disposed between the first extending portion 109 and the second extending portion 110. The gate resistor 108 is formed in a band shape of a constant width extending in the first direction X in a plan view.

[0178] The gate resistor 108 may further include a plurality of trench resistance structures 112. The plurality of trench resistance structures 112 are formed in the shape of long stripes in the second direction Y between the first extension portion 109 and the second extension portion 110. Each trench resistance structure 112 is formed in the shape of a long strip in a plan view in a direction crossing the gate extension electrode 33.

[0179] Next, a description will be given of the cross-sectional structure of Fig. 17. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII in Fig. 17. Fig. 19 is a cross-sectional view taken along line XIX-XIX in Fig. 17.

[0180] First, the cross-sectional structure of the gate terminal electrode 7 will be described with reference to Fig. 18. A well region 87 extends directly below the gate terminal electrode 7. A pad support layer 105 (resistance layer 103, first electrode layer 34) is formed in the well region 87 via a first insulating layer 68. The pad support layer 105 is covered with a third insulating layer 70.

[0181] A peripheral contact 106 and a pad contact 107 are embedded in the third insulating layer 70. The peripheral contact 106 and the pad contact 107 may also be referred to as a peripheral plug electrode and a pad plug electrode, respectively. The peripheral contact 106 and the pad contact 107 have structures corresponding to those of the emitter plug electrode 73. The description of the emitter plug electrode 73 applies mutatis mutandis to the description of the peripheral contact 106 and the pad contact 107. The structures of the peripheral contact 106 and the pad contact 107 that correspond to those described for the emitter plug electrode 73 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0182] The gate terminal electrode 7 and the peripheral portion 100 are formed on the third insulating layer 70. The gate terminal electrode 7 and the peripheral portion 100 are electrically connected to each other via the pad contact 107, the pad support layer 105, and the peripheral contact 106.

[0183] Next, the cross-sectional structure of the gate resistor 108 will be described with reference to Fig. 19. A trench resistor structure 112 is formed on the first main surface 3.

[0184] The trench resistor structure 112 includes a resistor trench 113, a resistor insulating layer 114, and a resistor electrode layer 115. The resistor trench 113 is formed on the first main surface 3 of the semiconductor chip 2. The resistor trench 113 includes sidewalls and a bottom wall. The sidewalls of the resistor trench 113 may be formed perpendicular to the first main surface 3.

[0185] The sidewalls of the resistor trench 113 may slope downward from the first main surface 3 toward the bottom wall. The resistor trench 113 may be formed in a tapered shape in which the opening area on the opening side is larger than the bottom area. The well region 87 is exposed from the sidewalls of the resistor trench 113. The bottom wall of the resistor trench 113 may be formed parallel to the first main surface 3. The bottom wall of the resistor trench 113 may be formed in a curved shape toward the second main surface 4. The resistor trench 113 includes a bottom wall edge portion. The bottom wall edge portion connects the sidewalls and bottom wall of the resistor trench 113. The bottom wall edge portion may be formed in a curved shape toward the second main surface 4 of the semiconductor chip 2.

[0186] The depth D5 of the resistor trench 113 may be 2 μm or more and 10 μm or less. The depth D5 of the resistor trench 113 may be 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, 4 μm or more and 5 μm or less, 5 μm or more and 6 μm or less, 6 μm or more and 7 μm or less, 8 μm or more and 9 μm or less, or 9 μm or more and 10 μm or less. The depth D5 of the resistor trench 113 may be equal to the depth D1 of the gate trench 47.

[0187] The width of the resistor trench 113 may be 0.5 μm or more and 3 μm or less. The width of the resistor trench 113 is the width of the resistor trench 113 in the first direction X. The width of the resistor trench 113 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less. The width of the resistor trench 113 may be equal to the width of the gate trench 47.

[0188] The resistive insulating layer 114 is formed in the form of a film along the inner wall of the resistive trench 113. The resistive insulating layer 114 defines a recess space within the resistive trench 113. In this embodiment, the resistive insulating layer 114 includes a silicon oxide film. The resistive insulating layer 114 may include a silicon nitride film instead of or in addition to the silicon oxide film.

[0189] The resistive electrode layer 115 is embedded in the resistive trench 113 with the resistive insulating layer 114 sandwiched therebetween. Specifically, the resistive electrode layer 115 is embedded in a recess space defined by the resistive insulating layer 114 in the resistive trench 113. The resistive electrode layer 115 may include conductive polysilicon. The resistive electrode layer 115 is controlled to a gate potential.

[0190] The gate resistor 108 has an extraction resistive layer 116 that is drawn out from the resistive trench 113 onto the first main surface 3. The extraction resistive layer 116 is integrally connected to the resistive electrode layer 115. That is, the extraction electrode layer 90 is drawn out integrally from the resistive electrode layer 115 onto the first main surface 3, collectively covering the plurality of resistive trenches 113. The pad support layer 105 is covered with the third insulating layer 70.

[0191] Resistor contacts 111 are embedded in the third insulating layer 70. The resistor contacts 111 may also be referred to as resistor plug electrodes. The resistor contacts 111 have a structure corresponding to that of the emitter plug electrode 73. The description of the emitter plug electrode 73 applies mutatis mutandis to the description of the resistor contacts 111. Structures of the resistor contacts 111 that correspond to those described for the emitter plug electrode 73 are given the same reference numerals, and descriptions thereof will be omitted.

[0192] A first extension portion 109 and a second extension portion 110 are formed on the third insulating layer 70. The first extension portion 109 and the second extension portion 110 are electrically connected to each other via a resistive contact 111, an extraction resistive layer 116, and a resistive electrode layer 115.

[0193] The portion of the resistive layer 103 where the first extending portion 109 and the second extending portion 110 are stacked is short-circuited by the first extending portion 109 and the second extending portion 110 formed by the wiring layer 104 having a lower resistance than the resistive layer 103. As a result, the portion of the resistive layer 103 exposed between the first extending portion 109 and the second extending portion 110 forms the gate resistor 108.

[0194] Fig. 20 is a diagram showing a modified example of the arrangement pattern of the IGBT regions 24 and the diode regions 25. Fig. 21 is an enlarged view of the portion surrounded by XXI in Fig. 20.

[0195] 20 and 21 , a first end portion (an end portion on the side surface 5B side) of the RC-IGBT array 26 is formed by a diode region 25. This diode region 25 is a region adjacent to the plurality of terminal electrodes 7 to 11, and may be referred to as a pad-adjacent diode region 25A. The pad-adjacent diode region 25A is adjacent to the gate terminal electrode 7 in the second direction Y.

[0196] In the pad-adjacent diode region 25A, the multiple diode-side trench structures 29 do not cross the gate wiring 13, and have termination portions 32 inside the diode region 25 away from the gate wiring 13 in the second direction Y. The second contact layer 39 collectively covers the termination portions 32 of the multiple diode-side trench structures 29. The second contact layer 39 is electrically connected to the diode-side trench structure 29 via the termination portions 32. The termination portions 32 of the multiple diode-side trench structures 29 face each other in the second direction Y, sandwiching the gate terminal electrode 7 and the peripheral portion 100 therebetween.

[0197] The gate resistor 108 is selectively formed in the gate extension electrode 33 in a portion that crosses the diode region 25, avoiding a portion directly above the trench gate structure 27. In this embodiment, the gate resistor 108 is formed in the peripheral portion 100 at a position adjacent to the termination portion 32 of the diode-side trench structure 29 in the second direction Y. More specifically, the gate resistor 108 is formed in a region sandwiched between a plurality of diode-side trench structures 29 that face each other with the gate terminal electrode 7 and the peripheral portion 100 in between. A pair of gate resistors 108 face each other in the second direction Y, with the gate terminal electrode 7 sandwiched between them.

[0198] In a region adjacent to the termination portion 32, the wiring layer 104 of the gate extension electrode 33 (peripheral portion 100) is divided into one side and the other side in the first direction X. The gate resistor 108 is formed by a portion of the resistance layer 103 (pad support layer 105) sandwiched between the divided wiring layers 104.

[0199] The peripheral portion 100 includes a first peripheral portion 117 that is continuous with the first portion 16 of the gate wiring 13, and a second peripheral portion 118 on the opposite side thereof. The first peripheral portion 117 and the second peripheral portion 118 are each connected to the resistive layer 103 via a resistive contact 111.

[0200] The gate resistor 108 is disposed between the first peripheral portion 117 and the second peripheral portion 118. The gate resistor 108 is formed in a band shape extending in the first direction X and having a constant width in a plan view.

[0201] The gate resistor 108 may further include a plurality of trench resistance structures 112. The plurality of trench resistance structures 112 are formed in the shape of long stripes in the second direction Y between the first peripheral portion 117 and the second peripheral portion 118. Each trench resistance structure 112 is formed in the shape of a long strip in a plan view in a direction crossing the gate extension electrode 33.

[0202] As described above, according to the structure shown in FIGS. 17 to 21, the gate resistor 108 is formed on the gate extension electrode 33. The gate resistor 108 constitutes a gate resistance for the gate of the IGBT. For example, the gate resistor 108 is effective in suppressing oscillation (noise) caused by parasitic inductance during turn-off. Furthermore, the gate resistor 108 is disposed in the empty space directly below the gate extension electrode 33, which is sandwiched between multiple diode-side trench structures 29. This prevents an increase in chip area due to the gate resistor 108. Therefore, a semiconductor device 1 having the gate resistor 108 can be provided without compromising the effective area of ​​the IGBT region 24.

[0203] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0204] For example, in each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted, i.e., a p-type portion may be formed as n-type, and an n-type portion may be formed as p-type.

[0205] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0206] The following appended features can be extracted from the description of this specification and the drawings. Hereinafter, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each appended clause to the embodiments.

[0207] [Supplementary Note 1-1] A chip (2) having a first main surface (3) and a second main surface (4); an insulating layer (67) covering the first main surface (3); an extended electrode (33) extending in a first direction (X) in a region on the first main surface (3), the extended electrode (33) including a first electrode layer (34) formed between the insulating layer (67) and the first main surface (3), and a second electrode layer (35) formed on the insulating layer (67) and electrically connected to the first electrode layer (34); a first element region (24) including an element electrically connected to the extended electrode (33); and second element regions (25) adjacent to the first element region (24) in the first direction (X) and formed on one side and the other side of the extended electrode (33) in a second direction (Y) intersecting the first direction (X). and a second trench electrode structure (29) formed on the first main surface (3) of the chip (2), crossing the extension electrode (33), and spanning a plurality of the second element regions (25) adjacent to each other with the extension electrode (33) in between, wherein the extension electrode (33) does not have the first electrode layer (34) directly above the second trench electrode structure (29), and selectively has the second electrode layer (35).

[0208] According to this configuration, the second trench electrode structure (29) crosses the extension electrode (33) and spans a plurality of adjacent second element regions (25) sandwiching the extension electrode (33). In other words, the second trench electrode structure (29) is not divided into second element regions (25). This makes it possible to reduce the number of termination portions of the second trench electrode structure (29).

[0209] For example, if the terminal end of the second trench electrode structure (29) is rounded, shape abnormalities are likely to occur due to variations in the recess. Therefore, by reducing the number of terminal ends of the second trench electrode structure (29), it is possible to suppress dielectric breakdown at the terminal end. As a result, it is possible to improve the ESD (Electro-Static Discharge) resistance of the semiconductor device (1).

[0210] [Supplementary Note 1-2] The semiconductor device (1) according to Supplementary Note 1-1, wherein the first element regions (24) are formed on one side and the other side of the extended electrode (33) in the second direction (Y), and include a first trench electrode structure (27) that is formed on the first main surface (3) of the chip (2), crosses the extended electrode (33), spans a plurality of the first element regions (24) adjacent to each other with the extended electrode (33) in between, and is physically and electrically separated from the second trench electrode structure (29), and the extended electrode (33) selectively has a stacked structure of the first electrode layer (34) and the second electrode layer (35) electrically connected to the first trench electrode structure (27) directly above the first trench electrode structure (27).

[0211] [Supplementary Note 1-3] The semiconductor device (1) according to Supplementary Note 1-2, wherein a plurality of the first element regions (24) and a plurality of the second element regions (25) are alternately arranged in the first direction (X), and the extended electrode (33) includes one second electrode layer (35) extending continuously across the plurality of first element regions (24) and the plurality of second element regions (25), and a plurality of the first electrode layers (34) selectively arranged in contact sections (37) where the second electrode layer (35) and the first element region (24) are opposed by being selectively divided by non-contact sections (36) where the second electrode layer (35) and the second element region (25) are opposed.

[0212] [Supplementary Note 1-4] The semiconductor device (1) according to Supplementary Note 1-3, wherein the first trench electrode structure (27) includes a first trench (47) and a first buried electrode (49) buried in the first trench (47), the second trench electrode structure (29) includes a second trench (61) and a second buried electrode (63) buried in the second trench (61) and covered by the insulating layer (67), and the first electrode layer (34) includes a first contact layer (38) that is integrally drawn out from the first buried electrode (49) onto the first main surface (3) and collectively covers the plurality of first trench electrode structures (27).

[0213] [Appendix 1-5] The semiconductor device (1) according to Appendix 1-4 further includes a second contact layer (39) that is formed adjacent to the extended electrode (33) in the second direction (Y), is drawn out integrally from the second buried electrode (63) onto the first main surface (3), and collectively covers the plurality of second trench electrode structures (29).

[0214] [Supplementary Note 1-6] The semiconductor device (1) according to Supplementary Note 1-5, wherein the second contact layer (39) has a shape extending in a strip shape in the first direction (X) alongside the extension electrode (33).

[0215] [Appendix 1-7] The semiconductor device (1) according to Appendix 1-5 further includes a third trench electrode structure (28) that extends in parallel with the first trench electrode structure (27) in the first element region (24), does not cross the extension electrode (33), and has a termination portion (31) inside the first element region (24) away from the extension electrode (33) in the second direction (Y).

[0216] [Appendix 1-8] The semiconductor device (1) according to appendix 1-7, wherein the third trench electrode structure (28) includes a third trench (55) and a third buried electrode (57) buried in the third trench (55) and covered by the insulating layer (67), and further includes a third contact layer (40) drawn out integrally from the third buried electrode (57) onto the first main surface (3) at the termination portion (31) of the third trench electrode structure (28), and a surface electrode layer (12) covering the second contact layer (39) and the third contact layer (40) and connected to the second contact layer (39) and the third contact layer (40).

[0217] [Appendix 1-9] The semiconductor device (1) according to Appendix 1-8, wherein a plurality of the extension electrodes (33) are formed at intervals in the second direction (Y), and the surface electrode layer (12) covers at least one of the first element regions (24) and one of the second element regions (25) in a partitioned region (20) sandwiched between adjacent extension electrodes (33).

[0218] [Supplementary Note 1-10] The chip (2) includes a drift region (41) of a first conductivity type formed in the chip (2), the first element region (24) including an IGBT region (24) having a body region (50) of a second conductivity type formed in the first main surface (3), an emitter region (51) of the first conductivity type formed in a surface layer portion of the body region (50), a collector region (45) of the second conductivity type formed in the second main surface (4), and a trench gate structure (27) as the first trench electrode structure (27), the second element region (25) including a first impurity region (64) of the second conductivity type formed in the first main surface (3), a second impurity region (58) of the first conductivity type formed in the second main surface (4), and a diode region (25) having a diode-side trench structure (29) as the second trench electrode structure (29) electrically connected to the emitter region (51), The semiconductor device (1) according to any one of Supplementary Notes 1-2 to 1-9, wherein the extension electrode (33) includes a gate extension electrode (33) electrically connected to the trench gate structure (27).

[0219] [Appendix 1-11] The semiconductor device (1) according to appendix 1-10, including a well region (87) of a second conductivity type formed on the first main surface (3) directly below the gate extension electrode (33), the well region (87) being deeper than the trench gate structure (27) and the diode-side trench structure (29).

[0220] [Appendix 1-12] The semiconductor device (1) according to Appendix 1-11, wherein the well region (87) straddles a boundary between the IGBT region (24) and the diode region (25) in the first direction (X), crosses the gate extension electrode (33) in the second direction (Y), and is integrally connected to the body region (50) of the IGBT region (24) and the first impurity region (64) of the diode region (25).

[0221] [Appendix 1-13] The semiconductor device (1) according to any one of Appendices 1-10 to 1-12, further comprising a fourth trench electrode structure (29) formed in the diode region (25A), not crossing the gate extension electrode (33), and having a termination portion (32) inside the diode region (25A) away from the gate extension electrode (33) in the second direction (Y), wherein the gate extension electrode (33) selectively has a gate resistor (108) in a portion adjacent to the fourth trench electrode structure (29).

[0222] [Appendix 1-14] The semiconductor device (1) according to Appendix 1-13, further comprising a gate pad electrode (7) electrically connected to the gate extension electrode (33), wherein the diode region (25A) is adjacent to the gate pad electrode (7) in the first direction (X) and includes a pad-adjacent diode region (25A) in which the fourth trench electrode structure (29) is formed, wherein the gate extension electrode (33) includes a plurality of the second electrode layers (35, 109, 110) that are separated at a portion crossing the pad-adjacent diode region (25A), and wherein the gate resistor (108) is formed by a portion of the first electrode layer (34) that is sandwiched between the plurality of second electrode layers (35, 109, 110).

[0223] [Appendix 1-15] The semiconductor device (1) according to Appendix 1-13, further comprising a gate pad electrode (7) electrically connected to the gate extension electrode (33), wherein the diode region (25) is adjacent to the gate pad electrode (7) in the second direction (Y) and includes a pad-adjacent diode region (25) in which the fourth trench electrode structure (29) is formed, wherein the gate extension electrode (33) includes a plurality of the second electrode layers (35, 109, 110) that are separated at a portion crossing the pad-adjacent diode region (25), and wherein the gate resistor (108) is formed by a portion of the first electrode layer (34) that is sandwiched between the plurality of second electrode layers (35, 109, 110).

[0224] [Supplementary Note 2-1] A semiconductor device (1) comprising: a chip (2) having a first main surface (3); an IGBT region (24) formed on the first main surface (3) of the chip (2); a diode region (25) formed on the first main surface (3) of the chip (2) and adjacent to the IGBT region (24) in a first direction (X); a gate extension electrode (33) extending in the first direction (X) through a region on the first main surface (3) continuously across the IGBT region (24) and the diode region (25); and a trench gate structure (27) formed on the first main surface (3) of the chip (2) and extending across the gate extension electrode (33), wherein the gate extension electrode (33) avoids a portion directly above the trench gate structure (27) and selectively has a gate resistor (108) in a portion crossing the diode region (25).

[0225] According to this configuration, the gate extension electrode (33) includes a gate resistor (108). The gate resistor (108) constitutes a gate resistance for the IGBT gate. For example, the gate resistor (108) is effective in suppressing oscillation (noise) caused by parasitic inductance during turn-off. Furthermore, the gate resistor (108) is selectively disposed in a portion of the gate extension electrode (33) that crosses the diode region (25), avoiding the portion directly above the trench gate structure (27). This prevents the gate resistor (108) from increasing the chip (2) area. Therefore, a semiconductor device (1) having the gate resistor (108) can be provided without compromising the effective area of ​​the IGBT region (24).

[0226] [Supplementary Note 2-2] The semiconductor device (1) according to Supplementary Note 2-1 includes an insulating layer (67) covering the first main surface (3), wherein a plurality of the IGBT regions (24) are formed sandwiching the diode region (25) in the first direction (X), the gate extension electrode (33) includes a resistive layer (103) formed between the insulating layer (67) and the first main surface (3) and extending continuously across the IGBT region (24) and the diode region (25) in the first direction (X), and a plurality of wiring layers (104) formed on the insulating layer (67), divided at a portion crossing the diode region (25), and having a lower resistance than the resistive layer (103), and the gate resistor (108) is formed by a portion of the resistive layer (103) sandwiched between the plurality of wiring layers (104).

[0227] [Supplementary Note 2-3] The semiconductor device (1) according to Supplementary Note 2-2, wherein the trench gate structure (27) includes a gate trench (47) and a buried gate electrode (49) buried in the gate trench (47), and the resistive layer (103) is formed in a band shape of a constant width in a plan view, and is drawn out onto the first main surface (3) integrally from the buried gate electrode (49).

[0228] [Appendix 2-4] The semiconductor device (1) according to Appendix 2-2, wherein the gate resistor (108) further includes a resistive trench (113) formed in the first main surface (3) of the chip (2), and a resistive electrode layer (115) embedded in the resistive trench (113) and integral with the resistive layer (103).

[0229] [Supplementary Note 2-5] The semiconductor device (1) according to Supplementary Note 2-4, wherein the resistive trench (113) is formed in a strip shape in a plan view that is long in a direction crossing the gate extension electrode (33).

[0230] [Supplementary Note 2-6] The present invention includes a gate pad electrode (7) electrically connected to the gate extension electrode (33), the gate extension electrode (33) including an annular peripheral portion (100) surrounding the gate pad electrode (7) and an extension portion (101) extending in a strip shape from the peripheral portion (100) in the first direction (X), the diode region (25) including a pad-adjacent diode region (25A) adjacent to the gate pad electrode (7) in the first direction (X), and a diode-side trench structure (29) formed in the pad-adjacent diode region (25A) and having a termination portion (32) inside the pad-adjacent diode region (25A) away from the extension portion (101) in a second direction (Y) intersecting the first direction (X), The semiconductor device (1) according to any one of Supplementary Notes 2-1 to 2-5, wherein the gate resistor (108) is formed adjacent to the termination portion (32) of the diode-side trench structure (29) in the extension portion (101).

[0231] [Supplementary Note 2-7] The semiconductor device (1) according to Supplementary Note 2-6, wherein a plurality of the IGBT regions (24) and a plurality of the diode regions (25) are alternately arranged in the first direction (X), the pad-adjacent diode region (25A) is selectively formed in a portion adjacent to the gate pad electrode (7) in the first direction (X), and a diode-side second trench structure (29) is formed in the diode region (25) excluding the pad-adjacent diode region (25A), the diode region (25) being formed on the first main surface (3) of the chip (2) and crossing the extension portion (101).

[0232] [Supplementary Note 2-8] The semiconductor device (1) according to Supplementary Note 2-6 or Supplementary Note 2-7, wherein the gate pad electrode (7) is disposed on the periphery of the chip (2), the gate extension electrode (33) is formed from the gate pad electrode (7) along the periphery of the chip (2) and includes an outer extension electrode (16) surrounding an active region (18), and an inner extension electrode (17, 33) that crosses the active region (18) and has one end and the other end connected to different positions on the outer extension electrode (16), and the gate resistor (108) is formed on the inner extension electrode (17, 33).

[0233] [Supplementary Note 2-9] The present invention includes a gate pad electrode (7) electrically connected to the gate extension electrode (33), the gate extension electrode (33) including an annular peripheral portion (100) surrounding the gate pad electrode (7) and an extension portion (101) extending in a strip shape from the peripheral portion (100) in the first direction (X), the diode region (25) including a pad-adjacent diode region (25A) adjacent to the gate pad electrode (7) in a second direction (Y) intersecting the first direction (X), and a diode-side trench structure (29) formed in the pad-adjacent diode region (25A) and having a termination portion (32) inside the pad-adjacent diode region (25A) away from the peripheral portion (100) in the second direction (Y), The semiconductor device (1) according to any one of Supplementary Notes 2-1 to 2-5, wherein the gate resistor (108) is formed adjacent to the terminal portion (32) of the diode-side trench structure (29) in the peripheral portion (100) of the gate extension electrode (33).

[0234] [Supplementary Note 2-10] The semiconductor device (1) according to Supplementary Note 2-9, wherein a plurality of the IGBT regions (24) and a plurality of the diode regions (25) are alternately arranged in the first direction (X), the pad-adjacent diode region (25A) is selectively formed in a portion adjacent to the gate pad electrode (7) in the second direction (Y), and a diode-side second trench structure (29) is formed in the diode region (25) excluding the pad-adjacent diode region (25A), the diode region (25) being formed on the first main surface (3) of the chip (2) and crossing the extension portion (101).

[0235] [Supplementary Note 2-11] The semiconductor device (1) according to any one of Supplementary Note 2-1 to Supplementary Note 2-10, wherein the gate resistor (108) is formed of polysilicon.

[0236] [Supplementary Note 3-1] A chip (2) having a first main surface (3) and a second main surface (4); a first element region (24) formed on the first main surface (3) of the chip (2); a second element region (25) formed on the first main surface (3) of the chip (2) and adjacent to the first element region (24) in a first direction (X); a gate extension electrode (33) extending continuously across the first element region (24) and the second element region (25) in the first direction (X) in an area on the first main surface (3); and a trench gate structure (27) formed on the first main surface (3) of the first element region (24) and extending across the gate extension electrode (33). a second trench electrode structure (29) formed on the first main surface (3) of the second element region (25), not crossing the gate extension electrode (33), and having an end portion (32) inside the second element region (25) away from the gate extension electrode (33) in a second direction (Y) intersecting the first direction (X); a gate auxiliary trench (95) formed directly below the gate extension electrode (33) in a portion adjacent to the second element region (25) in the second direction (Y); and a gate auxiliary buried electrode (97) buried in the gate auxiliary trench (95) via a gate insulating film (96) and electrically connected to the gate extension electrode (33).

[0237] According to this configuration, a gate auxiliary buried electrode (97) electrically connected to the gate extension electrode (33) is formed. This increases the gate capacitance, thereby improving the gate's ESD tolerance. Furthermore, the gate auxiliary buried electrode (97) is disposed in the empty space directly below the gate extension electrode (33). This avoids an increase in the chip (2) area or an increase in the gate trench (47) density due to the gate auxiliary buried electrode (97). This prevents an increase in chip cost and process difficulty.

[0238] [Supplementary Note 3-2] The semiconductor device (1) according to Supplementary Note 3-1, wherein the gate-assist trench (95) is a trench that is long along the second direction (Y).

[0239] [Supplementary Note 3-3] The semiconductor device (1) according to Supplementary Note 3-2, wherein the gate-assist trench (95) includes a plurality of elliptical trenches whose major axis direction coincides with the second direction (Y).

[0240] [Supplementary Note 3-4] The semiconductor device (1) according to Supplementary Note 3-2, wherein the gate-assist trench (95) includes a plurality of strip-shaped trenches whose length direction coincides with the second direction (Y).

[0241] [Appendix 3-5] The semiconductor device (1) according to any one of Appendices 3-2 to 3-4, wherein the gate auxiliary trench (95) has an end (98) that protrudes outward beyond the gate extension electrode (33) in the second direction (Y).

[0242] [Supplementary Note 3-6] The semiconductor device (1) according to any one of Supplementary Note 3-1 to Supplementary Note 3-5, wherein the trench gate structure (27) includes a gate trench (47) and a buried gate electrode (49) buried in the gate trench (47), and the gate extension electrode (33) includes: a first electrode layer (34) that is integrally drawn out onto the first main surface (3) from the buried gate electrode (49) and the buried gate auxiliary electrode (97) and collectively covers the gate trench (47) and the gate auxiliary trench (95), and a second electrode layer (35) that is formed on the first electrode layer (34) via an insulating layer (67) and extends in the first direction (X) across the gate trench (47) and the gate auxiliary trench (95).

[0243] [Supplementary Note 3-7] The semiconductor device (1) according to Supplementary Note 3-6, wherein the first electrode layer (34) is strip-shaped and extends with a constant width in the first direction (X), and the second electrode layer (35) is strip-shaped and extends with a constant width in the first direction (X).

[0244] [Supplementary Note 3-8] The semiconductor device (1) according to any one of Supplementary Note 3-1 to Supplementary Note 3-7, comprising: a drift region (41) of a first conductivity type formed in the chip (2); the first element region (24) comprising: a body region (50) of a second conductivity type formed in the first main surface (3); an emitter region (51) of the first conductivity type formed in a surface layer portion of the body region (50); a collector region (45) of the second conductivity type formed in the second main surface (4); and an IGBT region (24) having the trench gate structure (27); and the second element region (25) comprising: a first impurity region (64) of the second conductivity type formed in the first main surface (3); a second impurity region (58) of the first conductivity type formed in the second main surface (4); and a diode region (25) having a diode-side trench structure (29) as the second trench electrode structure (29) electrically connected to the emitter region (51).

[0245] [Appendix 3-9] The semiconductor device (1) according to appendix 3-8, wherein the diode-side trench structure (29) and the gate auxiliary trench (95) are formed on the same imaginary straight line (99) extending along the second direction (Y).

[0246] [Appendix 3-10] The semiconductor device (1) according to appendix 3-8 or appendix 3-9, wherein the gate extension electrode (33) further has a gate resistor (108) selectively in a portion crossing the diode region (25) while avoiding a portion directly above the trench gate structure (27).

[0247] [Appendix 3-11] The semiconductor device (1) according to Appendix 3-10 includes an insulating layer (67) covering the first main surface (3), wherein a plurality of the IGBT regions (24) are formed sandwiching the diode region (25) in the first direction (X), the gate extension electrode (33) includes a resistive layer (103) formed between the insulating layer (67) and the first main surface (3) and extending continuously across the IGBT region (24) and the diode region (25) in the first direction (X), and a plurality of wiring layers (104) formed on the insulating layer (67), divided at a portion crossing the diode region (25), and having a lower resistance than the resistive layer (103), and the gate resistor (108) is formed by a portion of the resistive layer (103) sandwiched between the plurality of wiring layers (104).

[0248] [Appendix 3-12] The semiconductor device (1) according to Appendix 3-11, wherein the gate resistor (108) further includes a resistive trench (113) formed in the first main surface (3) of the chip (2), and a resistive embedded electrode (115) embedded in the resistive trench (113) and integral with the resistive layer (103).

[0249] [Supplementary Note 3-13] The semiconductor device (1) according to Supplementary Note 3-12, wherein the resistive trench (113) is formed in a strip shape in a plan view that is long in a direction crossing the gate extension electrode (33).

[0250] [Appendix 3-14] The semiconductor device (1) according to any one of Appendices 3-10 to 3-13, further comprising a gate pad electrode (7) electrically connected to the gate extension electrode (33), wherein the diode region (25) includes a pad-adjacent diode region (25A) adjacent to the gate pad electrode (7) in the first direction (X), and the gate resistor (108) is formed in the gate extension electrode (33) at a position adjacent to the pad-adjacent diode region (25A).

[0251] [Appendix 3-15] The semiconductor device (1) according to any one of Appendices 3-10 to 3-13, further comprising a gate pad electrode (7) electrically connected to the gate extension electrode (33), wherein the diode region (25) includes a pad-adjacent diode region (25A) adjacent to the gate pad electrode (7) in the second direction (Y), and the gate resistor (108) is formed in the gate extension electrode (33) at a position adjacent to the pad-adjacent diode region (25A).

[0252] 1: Semiconductor device 2: Semiconductor chip 3: First main surface 4: Second main surface 5A: Side surface 5B: Side surface 5C: Side surface 5D: Side surface 6: Electrode film 7: Gate terminal electrode 8: First sense terminal electrode 9: Second sense terminal electrode 10: Current detection terminal electrode 11: Open terminal electrode 12: Emitter terminal electrode 13: Gate wiring 14: First sense wiring 15: Second sense wiring 16: First portion 17: Second portion 18: Active region 19: Peripheral region 20: Partition region 21: Central wiring 22: Side wiring 23: Sensor region 24: IGBT region 25: Diode region 25A: Pad-adjacent diode region 26: RC-IGBT array 27: Trench gate structure 28 : Emitter trench structure 29 : Diode-side trench structure 30 : Termination portion 31 : Termination portion 32 : Termination portion 33 : Gate extension electrode 34 : First electrode layer 35 : Second electrode layer 36 : Non-contact section 37 : Contact section 38 : First contact layer 39 : Second contact layer 40 : Third contact layer 41 : Drift region 42 : Semiconductor substrate 43 : Collector terminal electrode 44 : Buffer layer 45 : Collector region 46 : FET structure 47 : Gate trench 48 : Gate insulating layer 49 : Gate electrode layer 50 : Body region 51 : Emitter region 52 : Carrier storage region 53 : Contact trench 54 : Contact region 55 : Emitter trench 56 : Emitter insulating layer 57 : Emitter potential electrode layer 58 : Cathode region 59 : Diode cell region 60 : Cell isolation structure 61 : Cell isolation trench 62 : Cell isolation insulating layer 63 : Cell isolation electrode layer 64 : Anode region 65 : pn junction 66 : Diode trench 67 : Interlayer insulating layer 68 : First insulating layer 69 : Second insulating layer 70 : Third insulating layer 71 : Emitter opening 72 : Diode opening 73 : Emitter plug electrode 74 : Barrier electrode layer 75 : Main electrode layer 76 : Diode plug electrode 77 : First electrode layer78: Second electrode layer 79: Third electrode layer 80: Lead electrode layer 81: First opening 82: First plug electrode 83: Lead electrode layer 84: Second opening 85: Second plug electrode 86: Boundary region 87: Well region 88: Lead portion 89: Upper protrusion 90: Lead electrode layer 91: Gate opening 92: Gate plug electrode 93: Gate auxiliary trench structure 94: Termination portion 95: Gate auxiliary trench 96: Gate auxiliary insulating layer 97: Gate auxiliary electrode layer 98: Termination portion 99: Virtual straight line 100: Peripheral portion 101: Extension portion 102: Gap region 103: Resistance layer 104: Wiring layer 105: Pad support layer 106: Peripheral contact 107: Pad contact 108: Gate resistor 109: First extension portion 110: Second extension portion 111: Resistor contact 112: Trench resistor structure 113: Resistor trench 114: Resistor insulating layer 115: Resistor electrode layer 116: Lead-out resistor layer 117: First peripheral portion 118: Second peripheral portion

Claims

1. a chip having a first major surface; an IGBT region formed on the first main surface of the chip; a diode region formed on the first main surface of the chip and adjacent to the IGBT region in a first direction; a gate extension electrode extending in the first direction through a region on the first main surface, continuously crossing the IGBT region and the diode region; a trench gate structure formed on the first main surface of the chip and extending across the gate extension electrode; The semiconductor device, wherein the gate extension electrode has a gate resistor selectively in a portion crossing the diode region, avoiding a portion directly above the trench gate structure.

2. an insulating layer covering the first main surface; a plurality of the IGBT regions are formed to sandwich the diode region in the first direction, the gate extension electrode includes: a resistive layer formed between the insulating layer and the first main surface and extending continuously across the IGBT region and the diode region in the first direction; and a plurality of wiring layers formed on the insulating layer, divided at portions across the diode region, and having a lower resistance than the resistive layer, 2. The semiconductor device according to claim 1, wherein said gate resistor is formed by a portion of said resistance layer sandwiched between said plurality of wiring layers.

3. the trench gate structure includes a gate trench and a buried gate electrode buried in the gate trench; 3. The semiconductor device according to claim 2, wherein said resistive layer is formed in a band shape of a constant width in a plan view, and is extended integrally from said buried gate electrode onto said first main surface.

4. 3. The semiconductor device according to claim 2, wherein said gate resistor further includes: a resistive trench formed in said first main surface of said chip; and a resistive buried electrode buried in said resistive trench and integral with said resistive layer.

5. The semiconductor device according to claim 4 , wherein the resistive trench is formed in a strip shape in a plan view that is long in a direction crossing the gate extension electrode.

6. a gate pad electrode electrically connected to the gate extension electrode; the gate extension electrode includes an annular peripheral portion surrounding the gate pad electrode and an extension portion extending in a strip shape in the first direction from the peripheral portion, the diode region includes a pad-adjacent diode region adjacent to the gate pad electrode in the first direction, a diode-side trench structure formed in the pad-adjacent diode region and having a termination portion inside the pad-adjacent diode region spaced apart from the extension portion in a second direction intersecting the first direction; 6. The semiconductor device according to claim 1, wherein the gate resistor is formed adjacent to the terminal end of the diode-side trench structure in the extension portion.

7. a plurality of the IGBT regions and a plurality of the diode regions are alternately arranged in the first direction, the pad-adjacent diode region is selectively formed in a portion adjacent to the gate pad electrode in the first direction, 7. The semiconductor device according to claim 6, wherein a diode-side second trench structure is formed in the first main surface of the chip and crosses the extension portion in the diode region excluding the pad-adjacent diode region.

8. the gate pad electrode is disposed on the periphery of the chip, the gate extension electrode includes an outer extension electrode formed along the periphery of the chip from the gate pad electrode and surrounding an active area, and an inner extension electrode that crosses the active area and has one end and the other end connected to different positions on the outer extension electrode; The semiconductor device according to claim 6 , wherein the gate resistor is formed on the inner extension electrode.

9. a gate pad electrode electrically connected to the gate extension electrode; the gate extension electrode includes an annular peripheral portion surrounding the gate pad electrode and an extension portion extending in a strip shape in the first direction from the peripheral portion, the diode region includes a pad-adjacent diode region adjacent to the gate pad electrode in a second direction intersecting the first direction, a diode-side trench structure formed in the pad-adjacent diode region and having a termination portion inside the pad-adjacent diode region spaced apart from the periphery in the second direction; 6. The semiconductor device according to claim 1, wherein the gate resistor is formed adjacent to the terminal end of the diode-side trench structure in the peripheral portion of the gate extension electrode.

10. a plurality of the IGBT regions and a plurality of the diode regions are alternately arranged in the first direction, the pad-adjacent diode region is selectively formed in a portion adjacent to the gate pad electrode in the second direction, 10. The semiconductor device according to claim 9, wherein a diode-side second trench structure is formed in the first main surface of the chip and crosses the extension portion in the diode region excluding the pad-adjacent diode region.

11. 6. The semiconductor device according to claim 1, wherein the gate resistor is made of polysilicon.