Semiconductor device and vehicle

Abstract

This semiconductor device comprises a semiconductor element, a first lead that includes a die pad part, and a sealing resin that covers part of the semiconductor element and the first lead. The die pad part has: a first main surface, which faces one side in the thickness direction and on which the semiconductor element is mounted; a first reverse surface that faces the other side in the thickness direction; a first side surface that faces one side in a first direction orthogonal to the thickness direction; and a plurality of first recesses that are recessed from the first reverse surface and the first side surface. The first reverse surface is exposed from the sealing resin, and the plurality of first recesses are arranged at intervals in a second direction orthogonal to the thickness direction and the first direction.

Description

Semiconductor device and vehicle

[0001] The present disclosure relates to a semiconductor device and a vehicle equipped with the semiconductor device.

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes leads, a semiconductor element, and an encapsulating resin. The semiconductor element is mounted on the leads (die pad). The encapsulating resin covers part of the leads and the semiconductor element. The semiconductor element is mounted on the main surface of the die pad. The back surface of the die pad, facing the opposite side to the main surface, is exposed from the encapsulating resin. This structure allows heat generated by the semiconductor element to be efficiently dissipated from the back surface of the die pad.

[0003] In the semiconductor device described above, each part thermally expands and contracts due to heat generated by the semiconductor element. The linear expansion coefficient of the encapsulating resin is larger than that of the semiconductor element and the leads. Due to this difference in linear expansion coefficient, relatively large stress may act near the periphery of the semiconductor element due to thermal contraction of the encapsulating resin. In this case, there is a concern that problems such as peeling may occur between the die pad on which the semiconductor element is mounted and the encapsulating resin in contact with it.

[0004] International Publication No. 2022 / 014387

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device suitable for improving adhesion between a die pad portion on which a semiconductor element is mounted and a sealing resin.

[0006] A semiconductor device provided by a first aspect of the present disclosure includes a semiconductor element, a first lead including a die pad portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The die pad portion has a first main surface facing one side in a thickness direction and on which the semiconductor element is mounted, a first back surface facing the other side in the thickness direction, a first side surface facing one side in a first direction perpendicular to the thickness direction, and a plurality of first recesses recessed from the first back surface and the first side surface. The first back surface is exposed from the sealing resin. The plurality of first recesses are arranged at intervals in a second direction perpendicular to the thickness direction and the first direction.

[0007] A vehicle provided by a second aspect of the present disclosure includes a power conversion device configured to include the semiconductor device according to the first aspect of the present disclosure.

[0008] According to the above configuration, it is possible to improve the adhesion between the die pad portion on which the semiconductor element is mounted and the sealing resin.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 4 is a perspective view showing a main portion of the semiconductor device according to the first embodiment of the present disclosure. FIG. 5 is a perspective view showing a main portion of the semiconductor device according to the first embodiment of the present disclosure. FIG. 6 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 7 is a bottom view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 8 is a front view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a plan view showing a main portion of the semiconductor device according to the first embodiment of the present disclosure. FIG. 11 is a bottom view showing a main portion of the semiconductor device according to the first embodiment of the present disclosure. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 11. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 11. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 11. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 11. FIG. 16 is a cross-sectional view showing a state in which the semiconductor device according to the first embodiment of the present disclosure is in use. FIG. 17 is a schematic diagram of a vehicle including the semiconductor device according to the first embodiment of the present disclosure. FIG. 18 is a perspective view showing a semiconductor device according to a first modified example of the first embodiment of the present disclosure. FIG. 19 is a perspective view of a main portion showing a semiconductor device according to a first modified example of the first embodiment of the present disclosure. FIG. 20 is a plan view of a main portion showing a semiconductor device according to a first modified example of the first embodiment of the present disclosure. FIG. 21 is a perspective view of a semiconductor device according to a second modified example of the first embodiment of the present disclosure. FIG. 22 is a plan view of a main portion showing a semiconductor device according to a second modified example of the first embodiment of the present disclosure. FIG. 23 is a plan view of a main portion showing a semiconductor device according to a second modified example of the first embodiment of the present disclosure. FIG. 24 is a bottom view of a main portion showing a semiconductor device according to a second modified example of the first embodiment of the present disclosure. FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 24. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 24. FIG. 27 is a perspective view showing a semiconductor device according to a second embodiment of the present disclosure. 28 and 29 are perspective and plan views of a main portion of a semiconductor device according to a second embodiment of the present disclosure, respectively.FIG. 30 is a bottom view of a main portion showing a semiconductor device according to a second embodiment of the present disclosure. FIG. 31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 30. FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. 30. FIG. 33 is a perspective view of a main portion showing a semiconductor device according to a first modified example of the second embodiment. FIG. 34 is a plan view of a main portion showing a semiconductor device according to a first modified example of the second embodiment. FIG. 35 is a cross-sectional view of a semiconductor device according to a first modified example of the second embodiment, showing a cross section similar to that of FIG. 31. FIG. 36 is a cross-sectional view of a semiconductor device according to a first modified example of the second embodiment, showing a cross section similar to that of FIG. 32.

[0011] Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0012] Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not necessarily intended to dictate any ordering of their objects.

[0013] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0014] 1 to 16 show a semiconductor device according to a first embodiment of the present disclosure. The use of the semiconductor device A10 according to this embodiment is not limited in any way, and it may be used in electronic devices equipped with a power conversion circuit, such as a DC-DC converter. The semiconductor device A10 includes a conductive member 10, a semiconductor element 20, connecting members 31, 32, and 33, and a sealing resin 40.

[0015] 1 to 3 are perspective views showing the semiconductor device A10. FIGS. 4 and 5 are perspective views of a main portion of the semiconductor device A10. In FIGS. 4 and 5, the outer shape of the sealing resin 40 is indicated by an imaginary line (two-dot chain line). FIG. 6 is a plan view showing the semiconductor device A10. FIG. 7 is a bottom view showing the semiconductor device A10. FIG. 8 is a front view showing the semiconductor device A10. FIG. 9 is a side view showing the semiconductor device A10. FIG. 10 is a plan view of a main portion of the semiconductor device A10. FIG. 11 is a bottom view of a main portion of the semiconductor device A10. In FIGS. 10 and 11, the outer shape of the sealing resin 40 is indicated by an imaginary line (two-dot chain line). FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 11. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 11. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 11. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 11. FIG. 16 is a cross-sectional view showing the semiconductor device A10 in use.

[0016] In these figures, for example, an example of the thickness direction in the present disclosure is referred to as the "thickness direction z." An example of a direction perpendicular to the thickness direction z is referred to as the "first direction x." A direction perpendicular to the thickness direction z and the first direction x is referred to as the "second direction y." Furthermore, one side of the thickness direction z is an example of the "one side of the thickness direction" in the present disclosure and is referred to as the "z1 side of the thickness direction z." The other side of the thickness direction z is an example of the "other side of the thickness direction" in the present disclosure and is referred to as the "z2 side of the thickness direction z." One side of the first direction x is an example of the "one side of the first direction" in the present disclosure and is referred to as the "x1 side of the first direction x." The other side of the first direction x is an example of the "other side of the first direction" in the present disclosure and is referred to as the "x2 side of the first direction x." One side of the second direction y is an example of "one side of the second direction" in the present disclosure and is referred to as "the y1 side of the second direction y," and the other side of the second direction y is an example of "the other side of the second direction" in the present disclosure and is referred to as "the y2 side of the second direction y."

[0017] The conductive member 10 is a member that constitutes a conductive path to the semiconductor element 20. The conductive member 10 of this embodiment includes a first lead 11, a second lead 12, a third lead 13, and a fourth lead 14. The materials of the first lead 11, the second lead 12, the third lead 13, and the fourth lead 14 are not limited in any way and include, for example, copper (Cu) or a copper alloy. Furthermore, the first lead 11, the second lead 12, the third lead 13, and the fourth lead 14 may be plated in appropriate locations with silver (Ag), nickel (Ni), tin (Sn), or the like.

[0018] 1 to 15, the first lead 11 has a die pad portion 111 and a first terminal portion 112. The die pad portion 111 has a first main surface 1111 and a first back surface 1112. The first main surface 1111 is a surface facing the z1 side in the thickness direction z. The first back surface 1112 is a surface facing the z2 side in the thickness direction z. A semiconductor element 20 is mounted on the first main surface 1111.

[0019] The die pad portion 111 has a first side surface 1113, a second side surface 1114, a third side surface 1115, and a fourth side surface 1116. Each of the first side surface 1113, the second side surface 1114, the third side surface 1115, and the fourth side surface 1116 is located between the first main surface 1111 and the first back surface 1112 in the thickness direction z. The first side surface 1113 and the second side surface 1114 are spaced apart in the first direction x. The first side surface 1113 is located on the x1 side of the first direction x and faces the x1 side of the first direction x. The second side surface 1114 is located on the x2 side of the first direction x and faces the x2 side of the first direction x. The third side surface 1115 and the fourth side surface 1116 are spaced apart in the second direction y. The third side surface 1115 is located on the y1 side in the second direction y and faces the y1 side in the second direction y. The fourth side surface 1116 is located on the y2 side in the second direction y and faces the y2 side in the second direction y.

[0020] 10 , the die pad portion 111 further has a first corner 1117a, a second corner 1117b, a third corner 1117c, and a fourth corner 1117d. The first corner 1117a is the portion where the first side surface 1113 and the third side surface 1115 meet. The second corner 1117b is the portion where the first side surface 1113 and the fourth side surface 1116 meet. The third corner 1117c is the portion where the second side surface 1114 and the third side surface 1115 meet. The fourth corner 1117d is the portion where the second side surface 1114 and the fourth side surface 1116 meet.

[0021] In this embodiment, the die pad portion 111 has a plurality of first recesses 1113a, a plurality of second recesses 1114a, a plurality of third recesses 1115a, and a plurality of fourth recesses 1116a.

[0022] The multiple first recesses 1113a are recessed from the first back surface 1112 and the first side surface 1113. The multiple first recesses 1113a are arranged at intervals in the second direction y. In this embodiment, three first recesses 1113a are provided in the die pad portion 111. The three first recesses 1113a are arranged at regular intervals in the second direction y. The distance (first dimension L1) between two adjacent first recesses 1113a in the second direction y is 1 / 5 to 5 times the length (second dimension L2) of the first recesses 1113a in the second direction y. In the illustrated example, the distance (first dimension L1) between two adjacent first recesses 1113a is approximately 1.0 times the length (second dimension L2) of the first recesses 1113a.

[0023] Each of the first recesses 1113 a has a first intermediate surface 1113 b. The first intermediate surface 1113 b is located between the first main surface 1111 and the first back surface 1112 in the thickness direction z and faces the z2 side in the thickness direction z (the same side as the first back surface 1112).

[0024] The multiple second recesses 1114a are recessed from the first back surface 1112 and the second side surface 1114. The multiple second recesses 1114a are arranged at intervals in the second direction y. In this embodiment, three second recesses 1114a are provided in the die pad portion 111. The three second recesses 1114a are arranged at regular intervals in the second direction y. The distance (third dimension L3) between two adjacent second recesses 1114a in the second direction y is 1 / 5 to 5 times the length (fourth dimension L4) of the second recesses 1114a in the second direction y. In the illustrated example, the distance (third dimension L3) between two adjacent second recesses 1114a is approximately 1.0 times the length (fourth dimension L4) of the second recesses 1114a.

[0025] Each of the second recesses 1114 a has a second intermediate surface 1114 b. The second intermediate surface 1114 b is located between the first main surface 1111 and the first back surface 1112 in the thickness direction z and faces the z2 side in the thickness direction z (the same side as the first back surface 1112).

[0026] The plurality of third recesses 1115a are recessed from the first rear surface 1112 and the third side surface 1115. The plurality of third recesses 1115a are arranged at intervals in the first direction x. In this embodiment, two third recesses 1115a are provided in the die pad portion 111. The interval (fifth dimension L5) between two adjacent third recesses 1115a in the first direction x is 1 / 5 to 5 times the length (sixth dimension L6) of the third recesses 1115a in the first direction x. In the illustrated example, the interval (fifth dimension L5) between two adjacent third recesses 1115a is approximately 1.0 times the length (sixth dimension L6) of the third recesses 1115a.

[0027] Each of the third recesses 1115 a has a third intermediate surface 1115 b. The third intermediate surface 1115 b is located between the first main surface 1111 and the first back surface 1112 in the thickness direction z and faces the z2 side in the thickness direction z (the same side as the first back surface 1112).

[0028] The plurality of fourth recesses 1116a are recessed from the first back surface 1112 and the fourth side surface 1116. The plurality of fourth recesses 1116a are arranged at intervals in the first direction x. In this embodiment, two fourth recesses 1116a are provided in the die pad portion 111. The interval (seventh dimension L7) between two adjacent fourth recesses 1116a in the first direction x is 1 / 5 to 5 times the length (eighth dimension L8) of the fourth recesses 1116a in the first direction x. In the illustrated example, the interval (seventh dimension L7) between two adjacent fourth recesses 1116a is approximately 1.0 times the length (eighth dimension L8) of the fourth recesses 1116a.

[0029] Each of the plurality of fourth recesses 1116 a has a fourth intermediate surface 1116 b. The fourth intermediate surface 1116 b is located between the first main surface 1111 and the first back surface 1112 in the thickness direction z and faces the z2 side in the thickness direction z (the same side as the first back surface 1112).

[0030] In the illustrated example, the multiple first recesses 1113a are provided at positions that avoid both ends of the first side surface 1113 in the second direction y. As a result, each of the multiple first recesses 1113a does not contact either the first corner 1117a or the second corner 1117b. Furthermore, the multiple second recesses 1114a are provided at positions that avoid both ends of the second side surface 1114 in the second direction y. As a result, each of the multiple second recesses 1114a does not contact either the third corner 1117c or the fourth corner 1117d. The multiple third recesses 1115a are provided at positions that avoid both ends of the third side surface 1115 in the first direction x. As a result, each of the multiple third recesses 1115a does not contact either the first corner 1117a or the third corner 1117c. The plurality of fourth recesses 1116a are provided at positions that avoid both ends in the first direction x of the fourth side surface 1116. As a result, each of the plurality of fourth recesses 1116a is not in contact with either the second corner 1117b or the fourth corner 1117d.

[0031] In the illustrated example, the die pad portion 111 has a plurality of first protruding portions 1113c, a plurality of second protruding portions 1114c, a plurality of third protruding portions 1115c, and a plurality of fourth protruding portions 1116c.

[0032] The multiple first protrusions 1113c are individually connected to the multiple first recesses 1113a. Each first protrusion 1113c protrudes from the first side surface 1113 toward the x1 side in the first direction x. The multiple second protrusions 1114c are individually connected to the multiple second recesses 1114a. Each second protrusion 1114c protrudes from the second side surface 1114 toward the x2 side in the first direction x. The multiple third protrusions 1115c are individually connected to the multiple third recesses 1115a. Each third protrusion 1115c protrudes from the third side surface 1115 toward the y1 side in the second direction y. The multiple fourth protrusions 1116c are individually connected to the multiple fourth recesses 1116a. Each fourth protrusion 1116c protrudes from the fourth side surface 1116 toward the y2 side in the second direction y.

[0033] The plurality of first to fourth recesses 1113a to 1116a and the plurality of first to fourth protrusions 1113c to 1116c configured as described above are formed, for example, by pressing toward the z1 side in the thickness direction z at appropriate positions on the first back surface 1112 of the die pad portion 111. The plurality of first to fourth recesses 1113a to 1116a and the plurality of first to fourth protrusions 1113c to 1116c are covered with and in contact with sealing resin 40, which will be described later.

[0034] The first terminal portion 112 has a first portion 1121, two second portions 1122, and two third portions 1123. The first portion 1121 is connected to the die pad portion 111 and extends from the die pad portion 111 toward the x1 side in the first direction x. In the illustrated example, the first portion 1121 is parallel (or approximately parallel) to the xy plane. In this embodiment, the die pad portion 111 is larger in the thickness direction z than the first portion 1121. The first terminal portion 112 of this embodiment has only one first portion 1121. The shape of the first portion 1121 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z. The first portion 1121 is separated from the first back surface 1112 in the thickness direction z and, in the illustrated example, is in contact with the first main surface 1111. One side of the first portion 1121 is flush with the first main surface 1111.

[0035] The two second portions 1122 are located on the z1 side in the thickness direction z with respect to the first portion 1121. The two second portions 1122 are used when the semiconductor device A10 is surface-mounted on a circuit board or the like.

[0036] The two third portions 1123 are interposed between the first portion 1121 and the two second portions 1122. The third portions 1123 extend from the first portions 1121 toward the z1 side in the thickness direction z. In the example shown, the third portions 1123 are inclined with respect to the thickness direction z so as to extend outward from the first portions 1121 in the second direction y. The shape of the third portions 1123 is not limited in any way, and in the example shown, they are rectangular when viewed in the first direction x.

[0037] In this embodiment, the two second portions 1122 extend outward in the second direction y from the two third portions 1123. The two second portions 1122 are parallel (or approximately parallel) to the second direction y. The two second portions 1122 do not extend beyond the two third portions 1123 on the x1 side in the first direction x. In the illustrated example, the two second portions 1122 and the two third portions 1123 are at the same (or approximately the same) position in the first direction x.

[0038] The second lead 12 is located away from the first lead 11 (die pad portion 111) on the x2 side in the first direction x. The second lead 12 has a pad portion 121 and a plurality of second terminal portions 122.

[0039] The pad portion 121 has a second main surface 1211 and a second back surface 1212. The second main surface 1211 faces the z1 side in the thickness direction z. The second back surface 1212 faces the z2 side in the thickness direction z. A connecting member 31 is connected to the second main surface 1211. The shape of the pad portion 121 is not limited in any way, and in the illustrated example, it is an elongated rectangle with the second direction y as its longitudinal direction. Furthermore, as viewed in the thickness direction z, the pad portion 121 is smaller than the die pad portion 111. Furthermore, the size of the pad portion 121 in the thickness direction z is smaller than that of the die pad portion 111 and is the same (or approximately the same) as that of the first terminal portion 112. In the illustrated example, the position of the second main surface 1211 in the thickness direction z is the same (or approximately the same) as that of the first main surface 1111 of the die pad portion 111.

[0040] The second terminals 122 are arranged side by side in the second direction y. Each second terminal 122 has a fourth portion 1221, a fifth portion 1222, and a sixth portion 1223.

[0041] The fourth portion 1221 is connected to the pad portion 121, extends from the pad portion 121 to the x2 side in the first direction x, and is parallel (or approximately parallel) to the xy plane in the illustrated example. The shape of the fourth portion 1221 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z.

[0042] The fifth portion 1222 is located on the z1 side in the thickness direction z with respect to the fourth portion 1221. The fifth portion 1222 is used when surface-mounting the semiconductor device A10 on a circuit board or the like. The fifth portion 1222 has a shape that extends along the first direction x.

[0043] The sixth portion 1223 is interposed between the fourth portion 1221 and the fifth portion 1222. The sixth portion 1223 extends from the fourth portion 1221 toward the z1 side in the thickness direction z. In the example shown, the sixth portion 1223 is inclined with respect to the thickness direction z (yz plane). The shape of the sixth portion 1223 is not limited in any way, and in the example shown, it is rectangular when viewed in the first direction x.

[0044] The third lead 13 is located away from the first lead 11 (die pad portion 111) on the x2 side in the first direction x. The third lead 13 is also aligned with the second lead 12 in the second direction y. The third lead 13 has a pad portion 131 and a third terminal portion 132.

[0045] The pad portion 131 has a third main surface 1311 and a third back surface 1312. The third main surface 1311 faces the z1 side in the thickness direction z. The third back surface 1312 faces the z2 side in the thickness direction z. A connecting member 32 is connected to the third main surface 1311. The shape of the pad portion 131 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z. Furthermore, when viewed in the thickness direction z, the pad portion 131 is smaller than the pad portion 121. Furthermore, the size of the pad portion 131 in the thickness direction z is smaller than that of the die pad portion 111 and is the same (or approximately the same) as that of the pad portion 121. In the illustrated example, the position of the third main surface 1311 in the thickness direction z is the same (or approximately the same) as that of the first main surface 1111 of the die pad portion 111.

[0046] The third terminal portion 132 has a seventh portion 1321 , an eighth portion 1322 and a ninth portion 1323 .

[0047] The seventh portion 1321 is connected to the pad portion 131, extends from the pad portion 131 to the x2 side in the first direction x, and is parallel (or approximately parallel) to the xy plane in the illustrated example. The shape of the seventh portion 1321 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z.

[0048] The eighth portion 1322 is located on the z1 side in the thickness direction z with respect to the seventh portion 1321. The eighth portion 1322 is used when surface-mounting the semiconductor device A10 on a circuit board or the like. The eighth portion 1322 has a shape that extends along the first direction x.

[0049] The ninth portion 1323 is interposed between the seventh portion 1321 and the eighth portion 1322. The ninth portion 1323 extends from the seventh portion 1321 toward the z1 side in the thickness direction z. In the example shown, the ninth portion 1323 is inclined with respect to the thickness direction z (yz plane). The shape of the ninth portion 1323 is not limited in any way, and in the example shown, it is rectangular when viewed in the first direction x.

[0050] The fourth lead 14 is located away from the first lead 11 (die pad portion 111) on the other side in the x direction. The fourth lead 14 is also located between the second lead 12 and the third lead 13 in the y direction. The fourth lead 14 has a pad portion 141 and a fourth terminal portion 142.

[0051] The pad portion 141 has a fourth main surface 1411 and a fourth back surface 1412. The fourth main surface 1411 faces the z1 side in the thickness direction z. The fourth back surface 1412 faces the z2 side in the thickness direction z. A connecting member 33 is connected to the fourth main surface 1411. The shape of the pad portion 141 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z. When viewed in the thickness direction z, the pad portion 141 is smaller than the pad portion 121 and is approximately the same size as the pad portion 131. The pad portion 141 is smaller in size in the thickness direction z than the die pad portion 111 and is the same (or approximately the same) as the pad portion 121 and the pad portion 131. In the illustrated example, the position of the fourth main surface 1411 in the thickness direction z is the same (or approximately the same) as the first main surface 1111 of the die pad portion 111.

[0052] The fourth terminal portion 142 has a tenth portion 1421 , an eleventh portion 1422 , and a twelfth portion 1423 .

[0053] The tenth portion 1421 is connected to the pad portion 141, extends from the pad portion 141 to the x2 side in the first direction x, and is parallel (or approximately parallel) to the xy plane in the illustrated example. The shape of the tenth portion 1421 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z.

[0054] The eleventh portion 1422 is located on the z1 side in the thickness direction z with respect to the tenth portion 1421. The eleventh portion 1422 is used when surface-mounting the semiconductor device A10 on a circuit board or the like. The eleventh portion 1422 has a shape that extends along the first direction x.

[0055] The twelfth portion 1423 is interposed between the tenth portion 1421 and the eleventh portion 1422. The twelfth portion 1423 extends from the tenth portion 1421 toward the z1 side in the thickness direction z. In the example shown, the twelfth portion 1423 is inclined with respect to the thickness direction z (yz plane). The shape of the twelfth portion 1423 is not limited in any way, and in the example shown, it is rectangular when viewed in the first direction x.

[0056] As shown in FIGS. 5 and 11 to 15 , the semiconductor element 20 is mounted on the first main surface 1111 of the die pad portion 111. In the semiconductor device A10, the semiconductor element 20 is an n-channel, vertically structured metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor element 20 is not limited to a MOSFET. The semiconductor element 20 may be another type of transistor, such as an insulated gate bipolar transistor (IGBT). The semiconductor element 20 may also be a diode. The semiconductor element 20 is rectangular in the thickness direction z. The semiconductor element 20 does not overlap any of the first recesses 1113a, the second recesses 1114a, the third recesses 1115a, or the fourth recesses 1116a in the thickness direction z. The semiconductor element 20 includes a semiconductor layer 205, a first electrode 201, a second electrode 202, and a third electrode 203.

[0057] The semiconductor layer 205 includes a compound semiconductor substrate. The main material of the compound semiconductor substrate is silicon carbide (SiC). Alternatively, silicon (Si) may be used as the main material of the compound semiconductor substrate.

[0058] The first electrode 201 is provided on a portion of the semiconductor layer 205 in the thickness direction z, on a side (z1 side) facing the first main surface 1111 of the die pad portion 111 of the first lead 11. The first electrode 201 corresponds to a source electrode of the semiconductor element 20.

[0059] The second electrode 202 is provided on a portion of the semiconductor layer 205 opposite to the first electrode 201 in the thickness direction z. The second electrode 202 faces the first main surface 1111 of the die pad portion 111 of the first lead 11. The second electrode 202 corresponds to the drain electrode of the semiconductor element 20. In this embodiment, the second electrode 202 is conductively joined to the first main surface 1111 via a joining layer 29. The joining layer 29 is, for example, a conductive joining material such as solder, silver (Ag) paste, or baked silver.

[0060] The third electrode 203 is provided in a portion of the semiconductor layer 205 on the same side as the first electrode 201 in the thickness direction z (the z1 side in the thickness direction z), and is located away from the first electrode 201. The third electrode 203 corresponds to the gate electrode of the semiconductor element 20. When viewed in the thickness direction z, the area of ​​the third electrode 203 is smaller than the area of ​​the first electrode 201.

[0061] The connection member 31 is bonded to the first electrode 201 of the semiconductor element 20 and the second main surface 1211 of the pad portion 121 of the second lead 12. The material of the connection member 31 is not limited in any way and includes metals such as aluminum (Al), copper (Cu), and gold (Au). The number of connection members 31 is also not limited in any way and multiple connection members 31 may be provided. In the illustrated example, the connection member 31 is a flat, strip-shaped member that contains aluminum (Al).

[0062] The connecting member 32 is connected to the third electrode 203 of the semiconductor element 20 and the third main surface 1311 of the pad portion 131 of the third lead 13. In the illustrated example, the connecting member 32 contains gold (Au) and is a linear member that is thinner than the connecting member 31.

[0063] The connection member 33 is connected to the first electrode 201 of the semiconductor element 20 and the fourth main surface 1411 of the pad portion 141 of the fourth lead 14. In the illustrated example, the connection member 33 contains gold (Au) and is a linear member that is thinner than the connection member 31.

[0064] In this embodiment, the first terminal portion 112 of the first lead 11 is a drain terminal, the second terminal portion 122 of the second lead 12 is a source terminal, the third terminal portion 132 of the third lead 13 is a gate terminal, and the fourth terminal portion 142 of the fourth lead 14 is a source sense terminal.

[0065] 1 to 15 , the sealing resin 40 covers the semiconductor element 20, the connection members 31, 32, and 33, and portions of the first lead 11, the second lead 12, the third lead 13, and the fourth lead 14. The sealing resin 40 has electrical insulation properties. The sealing resin 40 is made of a material containing, for example, black epoxy resin. The sealing resin 40 has a first resin surface 41, a second resin surface 42, a third resin surface 43, a fourth resin surface 44, a fifth resin surface 45, and a sixth resin surface 46.

[0066] The first resin surface 41 faces the same side (z1 side) as the first main surface 1111 of the die pad portion 111 of the first lead 11 in the thickness direction z. The second resin surface 42 faces the opposite side (z2 side) from the first resin surface 41 in the thickness direction z. A first back surface 1112 of the die pad portion 111 of the first lead 11 is exposed from the second resin surface 42. The second resin surface 42 and the first back surface 1112 are flush with each other. The first back surface 1112 is separated from the third resin surface 43 in the first direction x.

[0067] The third resin surface 43 faces the x1 side in the first direction x. The first portion 1121 of the first terminal portion 112 of the first lead 11 penetrates the third resin surface 43. In this embodiment, only one first portion 1121 penetrates the third resin surface 43. In addition, the first portion 1121 is separated from the second resin surface 42 in the thickness direction z.

[0068] The fourth resin surface 44 faces the opposite side in the first direction x to the third resin surface 43 (the x2 side in the first direction x). In the present embodiment, the second terminal portions 122 of the plurality of second terminal portions 122 of the second lead 12, the seventh portion 1321 of the third terminal portion 132 of the third lead 13, and the tenth portion 1421 of the fourth terminal portion 142 of the fourth lead 14 penetrate the fourth resin surface 44.

[0069] The fifth resin surface 45 and the sixth resin surface 46 are surfaces facing in opposite directions to each other in the second direction y.

[0070] 7 , the second direction y end portions of the two second portions 1122 of the second terminal portion 122 of the first lead 11 are located at approximately the same positions in the y direction as the fifth resin surface 45 and the sixth resin surface 46 of the sealing resin 40. The two second portions 1122 do not protrude from the fifth resin surface 45 and the sixth resin surface 46 in the second direction y.

[0071] In the illustrated example, the sealing resin 40 has a groove 49. The groove 49 is recessed from the second resin surface 42 in the first direction x and extends along the second direction y. The groove 49 reaches the fifth resin surface 45 and the sixth resin surface 46. The groove 49 is located between the first back surface 1112 and the fourth resin surface 44.

[0072] Next, an example of use of the semiconductor device A10 will be described with reference to FIGS.

[0073] 16 shows the semiconductor device A10 in use. In this example, the semiconductor device A10 is surface-mounted on a circuit board 92. That is, the second portion 1122 of the first terminal 112, the fifth portion 1222 of the second terminal 122, the eighth portion 1322 of the third terminal 132, and the eleventh portion 1422 of the fourth terminal 142 are conductively joined to a wiring pattern (not shown) of the circuit board 92, for example, by solder 921. In addition, a heat sink 91 is disposed opposite the first back surface 1112 of the die pad 111. In the illustrated example, a sheet material 919 is disposed between the first back surface 1112 and the heat sink 91. The sheet material 919 is, for example, an insulating sheet.

[0074] FIG. 17 is a schematic diagram of a vehicle B1 equipped with a semiconductor device A10. The vehicle B1 is, for example, an electric vehicle (EV). As shown in FIG. 17, the vehicle B1 includes a drive system 84 including an AC-DC converter 81, a power receiving device 82, and a storage battery 83. The semiconductor device A10 constitutes part of the AC-DC converter 81. When the vehicle B1 receives AC power from a charging facility 80, which is an AC power source installed outdoors, the AC-DC converter 81 converts the AC power into high-voltage DC power. The AC-DC converter 81 supplies the high-voltage DC power to the storage battery 83. The power receiving device 82 supplies power to the storage battery 83 via a contactless charging system, and power is supplied via electromagnetic induction from a contactless charger (not shown) installed in a parking lot, etc. The power stored in the storage battery 83 is supplied to a drive system 84 including an inverter, an AC motor, and a transmission. The drive system 84 drives the vehicle B1. The AC-DC converter 81 is an example of the "power converter" of the present disclosure.

[0075] Next, the operation of the semiconductor device A10 will be described.

[0076] In the semiconductor device A10, the die pad portion 111 on which the semiconductor element 20 is mounted has a first back surface 1112 facing the z2 side in the thickness direction z and a first side surface 1113 facing the x1 side in the first direction x. The first back surface 1112 is exposed from the sealing resin 40. The die pad portion 111 also has a plurality of first recesses 1113a. Each of the plurality of first recesses 1113a is recessed from the first back surface 1112 and the first side surface 1113. The plurality of first recesses 1113a are arranged at intervals in the second direction y. By configuring the die pad portion 111 to have the above-described plurality of first recesses 1113a, the contact area between the die pad portion 111 on which the semiconductor element 20 is mounted and the sealing resin 40 can be efficiently increased, thereby improving the adhesion between the die pad portion 111 and the sealing resin 40.

[0077] In this embodiment, the distance (first dimension L1) between two adjacent first recesses 1113a in the second direction y is 1 / 5 to 5 times the length (second dimension L2) of the first recesses 1113a in the second direction y. With this configuration, even if partial peeling occurs in the sealing resin 40 in contact with the first recesses 1113a, the multiple first recesses 1113a are appropriately dispersed in the second direction y, so that the peeling of the sealing resin 40 can be prevented from progressing.

[0078] The die pad portion 111 further has a plurality of second recesses 1114a, a plurality of third recesses 1115a, and a plurality of fourth recesses 1116a. Each of the plurality of second recesses 1114a is recessed from the first back surface 1112 and the second side surface 1114. The plurality of second recesses 1114a are arranged at intervals in the second direction y. Each of the plurality of third recesses 1115a is recessed from the first back surface 1112 and the third side surface 1115. The plurality of third recesses 1115a are arranged at intervals in the first direction x. Each of the plurality of fourth recesses 1116a is recessed from the first back surface 1112 and the fourth side surface 1116. The plurality of fourth recesses 1116a are arranged at intervals in the first direction x. According to a configuration in which the die pad portion 111 has the above-mentioned multiple second recesses 1114a, multiple third recesses 1115a, and multiple fourth recesses 1116a, the contact area between the die pad portion 111 on which the semiconductor element 20 is mounted and the sealing resin 40 is increased more efficiently, and the adhesion between the die pad portion 111 and the sealing resin 40 can be further improved.

[0079] In this embodiment, the distance (third dimension L3) between two adjacent second recesses 1114a in the second direction y is 1 / 5 to 5 times the length (fourth dimension L4) of the second recesses 1114a in the second direction y. With this configuration, even if partial peeling occurs in the sealing resin 40 in contact with the second recesses 1114a, the multiple second recesses 1114a are appropriately dispersed in the second direction y, preventing the peeling of the sealing resin 40 from progressing. Similarly, the distance (fifth dimension L5) between two adjacent third recesses 1115a in the first direction x is 1 / 5 to 5 times the length (sixth dimension L6) of the third recesses 1115a in the first direction x. The distance (seventh dimension L7) between two adjacent fourth recesses 1116a in the first direction x is 1 / 5 to 5 times the length (eighth dimension L8) of the fourth recesses 1116a in the first direction x. This makes it possible to appropriately prevent the peeling of the sealing resin 40 from progressing even if partial peeling occurs in the sealing resin 40 that contacts the third recess 1115a and the fourth recess 1116a.

[0080] Each of the multiple first recesses 1113a does not contact either the first corner 1117a or the second corner 1117b. Similarly, each of the multiple second recesses 1114a does not contact either the third corner 1117c or the fourth corner 1117d. Each of the multiple third recesses 1115a does not contact either the first corner 1117a or the third corner 1117c. Each of the multiple fourth recesses 1116a does not contact either the second corner 1117b or the fourth corner 1117d. This configuration can appropriately prevent peeling of the sealing resin 40 from the four corners (first corner 1117a to fourth corner 1117d) of the die pad portion 111. This is preferable in terms of improving adhesion between the die pad portion 111 and the sealing resin 40.

[0081] The semiconductor element 20 does not overlap any of the first recesses 1113a, the second recesses 1114a, the third recesses 1115a, or the fourth recesses 1116a as viewed in the thickness direction z. When the first recesses 1113a to the fourth recesses 1116a are formed by press working, the flatness of the portions of the first main surface 1111 opposite the press-worked surface that overlap with the first recesses 1113a to the fourth recesses 1116a as viewed in the thickness direction z may decrease. In this embodiment, the semiconductor element 20 is positioned so as not to overlap any of the first recesses 1113a to the fourth recesses 1116a as viewed in the thickness direction z, thereby maintaining a good bonded state with the first main surface 1111.

[0082] 18 to 36 show modified examples and other embodiments of the semiconductor device of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals as in the above-described embodiment, and redundant explanations will be omitted. Furthermore, the configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0083] First Modification: Figures 18 to 20 show a first modification of the semiconductor device A10. Figure 18 is a perspective view showing a semiconductor device A11 according to the first modification. Figure 19 is a perspective view of a main part of the semiconductor device A11. Figure 20 is a plan view of a main part of the semiconductor device A11. In Figures 19 and 20, the outline of the sealing resin 40 is shown by an imaginary line (two-dot chain line). The semiconductor device A11 of this modification differs from the semiconductor device A10 in the arrangement of the first recess 1113a, the second recess 1114a, the third recess 1115a, and the fourth recess 1116a in the die pad portion 111.

[0084] In the semiconductor device A11, the number of first recesses 1113a, second recesses 1114a, third recesses 1115a, and fourth recesses 1116a formed in the die pad portion 111 is greater than that of the semiconductor device A10. The die pad portion 111 is provided with five first recesses 1113a, five second recesses 1114a, three third recesses 1115a, and three fourth recesses 1116a.

[0085] The five first recesses 1113a are arranged at regular intervals in the second direction y. The distance (first dimension L1) between two adjacent first recesses 1113a in the second direction y is 1 / 5 to 5 times the length (second dimension L2) of the first recesses 1113a in the second direction y. In the illustrated example, the distance (first dimension L1) between two adjacent first recesses 1113a is approximately 0.63 times the length (second dimension L2) of the first recesses 1113a. The five second recesses 1114a are arranged at regular intervals in the second direction y. The distance (third dimension L3) between two adjacent second recesses 1114a in the second direction y is 1 / 5 to 5 times the length (fourth dimension L4) of the second recesses 1114a in the second direction y. In the illustrated example, the distance between two second recesses 1114a (third dimension L3) is approximately 0.63 times the length (fourth dimension L4) of the second recesses 1114a. The three third recesses 1115a are arranged at regular intervals in the first direction x. The distance between two adjacent third recesses 1115a in the first direction x (fifth dimension L5) is 1 / 5 to 5 times the length (sixth dimension L6) of the third recesses 1115a in the first direction x. In the illustrated example, the distance between two adjacent third recesses 1115a (fifth dimension L5) is approximately 0.93 times the length (sixth dimension L6) of the third recesses 1115a. The three fourth recesses 1116a are arranged at regular intervals in the first direction x. The distance (seventh dimension L7) between two adjacent fourth recesses 1116a in the first direction x is 1 / 5 to 5 times the length (eighth dimension L8) of the fourth recesses 1116a in the first direction x. In the illustrated example, the distance (seventh dimension L7) between two adjacent fourth recesses 1116a is approximately 0.93 times the length (eighth dimension L8) of the fourth recesses 1116a.

[0086] In the semiconductor device A11, the die pad portion 111 on which the semiconductor element 20 is mounted has a plurality of first recesses 1113a. Each of the plurality of first recesses 1113a is recessed from the first back surface 1112 and the first side surface 1113. The plurality of first recesses 1113a are arranged at intervals in the second direction y. When the die pad portion 111 has the above-described plurality of first recesses 1113a, the contact area between the die pad portion 111 on which the semiconductor element 20 is mounted and the sealing resin 40 is efficiently increased, and the adhesion between the die pad portion 111 and the sealing resin 40 can be improved.

[0087] In this modification, the distance (first dimension L1) between two adjacent first recesses 1113a in the second direction y is 1 / 5 to 5 times the length (second dimension L2) of the first recesses 1113a in the second direction y. With this configuration, even if partial peeling occurs in the sealing resin 40 in contact with the first recesses 1113a, the multiple first recesses 1113a are appropriately dispersed in the second direction y, so that the peeling of the sealing resin 40 can be prevented from progressing. In addition, the semiconductor device A11 exhibits the same effects as the semiconductor device A10 of the above embodiment.

[0088] Furthermore, in the semiconductor device A11, the number of first recesses 1113a, second recesses 1114a, third recesses 1115a, and fourth recesses 1116a formed in the die pad portion 111 is greater than that of the semiconductor device A10. This configuration can further increase the contact area between the die pad portion 111 and the sealing resin 40. This is preferable in terms of improving the adhesion between the die pad portion 111 and the sealing resin 40.

[0089] Second Modification: FIGS. 21 to 26 show a second modification of the semiconductor device A10. FIG. 21 is a perspective view showing a semiconductor device A12 according to the second modification. FIG. 22 is a perspective view of a main portion of the semiconductor device A12. FIG. 23 is a plan view of a main portion of the semiconductor device A12. FIG. 24 is a bottom view of a main portion of the semiconductor device A12. In FIGS. 22 to 24, the outline of the sealing resin 40 is indicated by an imaginary line (two-dot chain line). FIG. 25 is a cross-sectional view taken along line XXV-XXV in FIG. 24. FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 24. The semiconductor device A12 of this modification differs from the semiconductor device A10 in the configurations of the first recess 1113a, the second recess 1114a, the third recess 1115a, and the fourth recess 1116a in the die pad portion 111, and in the arrangement of the semiconductor element 20.

[0090] In the semiconductor device A12, the length in the thickness direction z of the first recess 1113a (the distance in the thickness direction z between the first back surface 1112 and the first intermediate surface 1113b) is greater than that of the semiconductor device A10. Similarly, the lengths in the thickness direction z of the second recess 1114a, the third recess 1115a, and the fourth recess 1116a are each greater than that of the semiconductor device A10. Furthermore, in the semiconductor device A12, the length in the first direction x of the first recess 1113a is greater than that of the semiconductor device A10. Similarly, the length in the first direction x of the second recess 1114a is greater than that of the semiconductor device A10, and the lengths in the second direction y of the third recess 1115a and the fourth recess 1116a are each greater than that of the semiconductor device A10. The first dimension L1 to the eighth dimension L8 described for the semiconductor device A10 are the same (or approximately the same) as those of the semiconductor device A10 in the semiconductor device A12.

[0091] In the semiconductor device A12, unlike the semiconductor device A10 of the above embodiment, the die pad portion 111 does not have the first protrusion 1113 c, the second protrusion 1114 c, the third protrusion 1115 c, or the fourth protrusion 1116 c. The first recesses 1113 a, the second recesses 1114 a, the third recesses 1115 a, and the fourth recesses 1116 a of this modification are formed by a chemical process such as etching.

[0092] In the semiconductor device A12, the size of the semiconductor element 20 in a plan view (as viewed in the thickness direction z) is larger than that of the semiconductor device A10. When viewed in the thickness direction z, the semiconductor element 20 overlaps with a portion of each of the plurality of first recesses 1113 a, the plurality of second recesses 1114 a, the plurality of third recesses 1115 a, and the plurality of fourth recesses 1116 a.

[0093] In the semiconductor device A12, the die pad portion 111 on which the semiconductor element 20 is mounted has a plurality of first recesses 1113a. Each of the plurality of first recesses 1113a is recessed from the first back surface 1112 and the first side surface 1113. The plurality of first recesses 1113a are arranged at intervals in the second direction y. When the die pad portion 111 has the above-described plurality of first recesses 1113a, the contact area between the die pad portion 111 on which the semiconductor element 20 is mounted and the sealing resin 40 is efficiently increased, and the adhesion between the die pad portion 111 and the sealing resin 40 can be improved.

[0094] In this modification, the distance (first dimension L1) between two adjacent first recesses 1113a in the second direction y is 1 / 5 to 5 times the length (second dimension L2) of the first recesses 1113a in the second direction y. With this configuration, even if partial peeling occurs in the sealing resin 40 in contact with the first recesses 1113a, the multiple first recesses 1113a are appropriately dispersed in the second direction y, preventing the peeling of the sealing resin 40 from progressing. Additionally, the semiconductor device A12 has the same effects as the semiconductor device A10 of the above embodiment within the same configuration range.

[0095] Second Embodiment: FIGS. 27 to 32 show a semiconductor device according to a second embodiment of the present disclosure. FIG. 27 is a perspective view showing a semiconductor device A20 according to this embodiment. FIG. 28 is a perspective view of a main portion of the semiconductor device A20. FIG. 29 is a plan view of a main portion of the semiconductor device A20. FIG. 30 is a bottom view of a main portion of the semiconductor device A20. In FIGS. 28 to 30, the outline of the sealing resin 40 is shown by an imaginary line (two-dot chain line). FIG. 31 is a cross-sectional view taken along line XXXI-XXXI in FIG. 30. FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. 30. The semiconductor device A20 of this embodiment differs from the semiconductor device A10 in the configuration of the die pad portion 111.

[0096] In the semiconductor device A20, the die pad portion 111 has a plurality of fifth protrusions 1113 d, a plurality of sixth protrusions 1114 d, a plurality of seventh protrusions 1115 d, and a plurality of eighth protrusions 1116 d. On the other hand, in the semiconductor device A20, unlike the above embodiment, the die pad portion 111 does not have the first recess 1113 a, the second recess 1114 a, the third recess 1115 a, or the fourth recess 1116 a.

[0097] The plurality of fifth protrusions 1113d each protrude from the first side surface 1113 toward the x1 side in the first direction x. The plurality of fifth protrusions 1113d are located closer to the z2 side in the thickness direction z of the first side surface 1113. The plurality of fifth protrusions 1113d are arranged at intervals in the second direction y. In this embodiment, three fifth protrusions 1113d are provided on the die pad portion 111. The three fifth protrusions 1113d are arranged at regular intervals in the second direction y.

[0098] Each of the fifth protrusions 1113d has a fifth intermediate surface 1113e. The fifth intermediate surface 1113e is located between the first main surface 1111 and the first back surface 1112 in the thickness direction z and faces the z2 side in the thickness direction z (the same side as the first back surface 1112).

[0099] The multiple sixth protrusions 1114d each protrude from the second side surface 1114 toward the x2 side in the first direction x. The multiple sixth protrusions 1114d are located closer to the z2 side in the thickness direction z of the second side surface 1114. The multiple sixth protrusions 1114d are arranged at intervals in the second direction y. In this embodiment, three sixth protrusions 1114d are provided on the die pad portion 111. The three sixth protrusions 1114d are arranged at regular intervals in the second direction y.

[0100] Each of the sixth protrusions 1114d has a sixth intermediate surface 1114e. The sixth intermediate surface 1114e is located between the first main surface 1111 and the first back surface 1112 in the thickness direction z and faces the z2 side in the thickness direction z (the same side as the first back surface 1112).

[0101] The seventh protrusions 1115d each protrude from the third side surface 1115 toward the y1 side in the second direction y. The seventh protrusions 1115d are located closer to the z2 side in the thickness direction z of the third side surface 1115. The seventh protrusions 1115d are arranged at intervals in the first direction x. In this embodiment, the die pad portion 111 is provided with two seventh protrusions 1115d.

[0102] Each of the seventh protrusions 1115d has a seventh intermediate surface 1115e. The seventh intermediate surface 1115e is located between the first main surface 1111 and the first back surface 1112 in the thickness direction z and faces the z2 side in the thickness direction z (the same side as the first back surface 1112).

[0103] The multiple eighth protrusions 1116d each protrude from the fourth side surface 1116 toward the y2 side in the second direction y. The multiple eighth protrusions 1116d are located closer to the z2 side in the thickness direction z of the fourth side surface 1116. The multiple eighth protrusions 1116d are arranged at intervals in the first direction x. In this embodiment, the die pad portion 111 is provided with two eighth protrusions 1116d.

[0104] Each of the eighth protrusions 1116d has an eighth intermediate surface 1116e. The eighth intermediate surface 1116e is located between the first main surface 1111 and the first back surface 1112 in the thickness direction z and faces the z2 side in the thickness direction z (the same side as the first back surface 1112).

[0105] In the illustrated example, the multiple fifth protrusions 1113d are provided at positions that avoid both ends of the first side surface 1113 in the second direction y. As a result, each of the multiple fifth protrusions 1113d does not contact either the first corner 1117a or the second corner 1117b. Furthermore, the multiple sixth protrusions 1114d are provided at positions that avoid both ends of the second side surface 1114 in the second direction y. As a result, each of the multiple sixth protrusions 1114d does not contact either the third corner 1117c or the fourth corner 1117d. The multiple seventh protrusions 1115d are provided at positions that avoid both ends of the third side surface 1115 in the first direction x. As a result, each of the multiple seventh protrusions 1115d does not contact either the first corner 1117a or the third corner 1117c. The eighth protrusions 1116d are provided at positions that avoid both ends in the first direction x of the fourth side surface 1116. As a result, each of the eighth protrusions 1116d is not in contact with either the second corner 1117b or the fourth corner 1117d.

[0106] The plurality of fifth to eighth protrusions 1113d to 1116d configured as described above are formed, for example, by pressing the die pad portion 111 from the first back surface 1112 side toward the z1 side in the thickness direction z. The die pad portion 111 before pressing has convex portions corresponding to the plurality of fifth to eighth protrusions 1113d to 1116d. Each convex portion is connected to the first back surface 1112 and protrudes from a corresponding one of the first to fourth side surfaces 1113 to 1116. In this embodiment, the press working is performed on each convex portion along the boundary line of the first back surface 1112. As a result, fifth to eighth intermediate surfaces 1113e to 1116e are formed on the fifth to eighth protrusions 1113d to 1116d, respectively. All of the plurality of fifth to eighth protrusions 1113d to 1116d are covered with and in contact with the sealing resin 40.

[0107] In the semiconductor device A20, the die pad portion 111 on which the semiconductor element 20 is mounted has a plurality of fifth protrusions 1113d. Each of the plurality of fifth protrusions 1113d protrudes from the first side surface 1113 toward the x1 side in the first direction x. The plurality of fifth protrusions 1113d are arranged at intervals in the second direction y. When the die pad portion 111 has the above-described plurality of fifth protrusions 1113d, the contact area between the die pad portion 111 on which the semiconductor element 20 is mounted and the sealing resin 40 is efficiently increased, and the adhesion between the die pad portion 111 and the sealing resin 40 can be improved.

[0108] The die pad portion 111 further has a plurality of sixth protrusions 1114d, a plurality of seventh protrusions 1115d, and a plurality of eighth protrusions 1116d. Each of the sixth protrusions 1114d protrudes from the second side surface 1114 toward the x2 side in the first direction x. The sixth protrusions 1114d are arranged at intervals in the second direction y. Each of the seventh protrusions 1115d protrudes from the third side surface 1115 toward the y1 side in the second direction y. The seventh protrusions 1115d are arranged at intervals in the first direction x. Each of the eighth protrusions 1116d protrudes from the fourth side surface 1116 toward the y2 side in the second direction y. The eighth protrusions 1116d are arranged at intervals in the first direction x. According to a configuration in which the die pad portion 111 has the above-mentioned multiple sixth protrusions 1114d, multiple seventh protrusions 1115d, and multiple eighth protrusions 1116d, the contact area between the die pad portion 111 on which the semiconductor element 20 is mounted and the sealing resin 40 is increased more efficiently, and the adhesion between the die pad portion 111 and the sealing resin 40 can be further improved.

[0109] Each of the plurality of fifth protrusions 1113d does not contact either the first corner 1117a or the second corner 1117b. Similarly, each of the plurality of sixth protrusions 1114d does not contact either the third corner 1117c or the fourth corner 1117d. Each of the plurality of seventh protrusions 1115d does not contact either the first corner 1117a or the third corner 1117c. Each of the plurality of eighth protrusions 1116d does not contact either the second corner 1117b or the fourth corner 1117d. This configuration can appropriately prevent peeling of the sealing resin 40 from the four corners (first corner 1117a to fourth corner 1117d) of the die pad portion 111. This is preferable in terms of improving adhesion between the die pad portion 111 and the sealing resin 40.

[0110] In the semiconductor device A20, each of the plurality of fifth to eighth protrusions 1113d to 1116d is covered with the sealing resin 40. Therefore, as shown in Fig. 27, on the z2 side in the thickness direction z of the die pad portion 111, the rectangular first back surface 1112 is exposed from the sealing resin 40. As a result, the appearance of the semiconductor device A20 when the die pad portion 111 is viewed from the z2 side in the thickness direction z is unchanged from the conventional semiconductor device.

[0111] First Modification of Second Embodiment: FIGS. 33 to 36 show a first modification of the semiconductor device A20. FIG. 33 is a perspective view of a main portion of a semiconductor device A21 according to this modification. FIG. 34 is a plan view of a main portion of the semiconductor device A21. In FIGS. 33 and 34, the outline of the sealing resin 40 is indicated by an imaginary line (two-dot chain line). FIG. 35 is a cross-sectional view of the semiconductor device A21, showing a cross-section similar to that of FIG. 31. FIG. 36 is a cross-sectional view of the semiconductor device A21, showing a cross-section similar to that of FIG. 32. The semiconductor device A21 of this modification differs from the semiconductor device A20 in the shapes of the fifth protrusion 1113d, the sixth protrusion 1114d, the seventh protrusion 1115d, and the seventh protrusion 1115d in the die pad portion 111.

[0112] In the semiconductor device A21, each of the plurality of fifth to eighth protrusions 1113d to 1116d has a portion connected to the first back surface 1112. In this modification, the plurality of fifth to eighth protrusions 1113d to 1116d are formed, for example, by pressing from the first back surface 1112 side of the die pad portion 111 toward the z1 side in the thickness direction z. In this modification, the pressing is performed on the portions of each protrusion before pressing that are outside the boundary line of the first back surface 1112.

[0113] In the semiconductor device A21, the die pad portion 111 on which the semiconductor element 20 is mounted has a plurality of fifth protrusions 1113d. Each of the plurality of fifth protrusions 1113d protrudes from the first side surface 1113 toward the x1 side in the first direction x. The plurality of fifth protrusions 1113d are arranged at intervals in the second direction y. When the die pad portion 111 has the above-described plurality of fifth protrusions 1113d, the contact area between the die pad portion 111 on which the semiconductor element 20 is mounted and the sealing resin 40 is efficiently increased, thereby improving the adhesion between the die pad portion 111 and the sealing resin 40. In addition, the semiconductor device A21 achieves the same effects as the semiconductor device A20 within the same configuration as the semiconductor device A20 of the above embodiment.

[0114] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways. The package structure of the semiconductor device according to the present disclosure is not limited to the structure shown in the semiconductor device A10 of the above embodiment, and the present disclosure can be applied to various package structures.

[0115] The present disclosure includes embodiments described in the following appendices. Appendix 1. A semiconductor device comprising: a semiconductor element; a first lead including a die pad portion; and a sealing resin covering the semiconductor element and a portion of the first lead, wherein the die pad portion has a first main surface facing one side in a thickness direction and on which the semiconductor element is mounted, a first back surface facing the other side in the thickness direction, a first side surface facing one side in a first direction orthogonal to the thickness direction, and a plurality of first recesses recessed from the first back surface and the first side surface, wherein the first back surface is exposed from the sealing resin, and the plurality of first recesses are arranged at intervals in the thickness direction and a second direction orthogonal to the first direction. Appendix 2. The semiconductor device described in Appendix 1, wherein each of the plurality of first recesses has a first intermediate surface facing the other side in the thickness direction. Appendix 3. The semiconductor device according to Supplementary Note 1 or 2, wherein a first dimension that is a distance between two of the first recesses adjacent to each other in the second direction is 1 / 5 to 5 times a second dimension that is a length of the first recesses in the second direction.Supplementary Note 4. The semiconductor device according to any of Supplementary Note 1 to 3, wherein the die pad portion has three or more of the first recesses, and the multiple first recesses are arranged at intervals in the second direction.Supplementary Note 5. The semiconductor device according to any of Supplementary Note 1 to 4, wherein the die pad portion has multiple first protrusions that are connected to the multiple first recesses, respectively, and that protrude from the first side surface to one side in the first direction.Supplementary Note 6. the die pad portion has a second side surface facing the other side in the first direction, a third side surface facing one side in the second direction, a fourth side surface facing the other side in the second direction, a plurality of second recesses recessed from the first back surface and the second side surface, a plurality of third recesses recessed from the first back surface and the third side surface, and a plurality of fourth recesses recessed from the first back surface and the fourth side surface, wherein the plurality of second recesses are arranged at intervals in the second direction, the plurality of third recesses are arranged at intervals in the first direction, and the plurality of fourth recesses are arranged at intervals in the first direction.Supplementary Note 7. The semiconductor device according to Supplementary Note 6, wherein each of the second recesses has a second intermediate surface facing the other side in the thickness direction, each of the third recesses has a third intermediate surface facing the other side in the thickness direction, and each of the fourth recesses has a fourth intermediate surface facing the other side in the thickness direction. Supplementary Note 8. The semiconductor device according to Supplementary Note 6 or 7, wherein a third dimension that is the spacing between two adjacent second recesses in the second direction is 1 / 5 to 5 times a fourth dimension that is the length of the second recesses in the second direction, a fifth dimension that is the spacing between two adjacent third recesses in the first direction is 1 / 5 to 5 times a sixth dimension that is the length of the third recesses in the first direction, and a seventh dimension that is the spacing between two adjacent fourth recesses in the first direction is 1 / 5 to 5 times an eighth dimension that is the length of the fourth recesses in the first direction. Supplementary Note 9. the die pad portion has three or more of the second recesses, three or more of the third recesses, and three or more of the fourth recesses, the plurality of second recesses being arranged at intervals in the second direction, the plurality of third recesses being arranged at intervals in the first direction, and the plurality of fourth recesses being arranged at intervals in the first direction.Supplementary Note 10. The semiconductor device according to any of Supplementary Note 6 to 9, the die pad portion has a plurality of second protruding portions connected to each of the plurality of second recesses and protruding from the second side surface to the other side in the first direction, a plurality of third protruding portions connected to each of the plurality of third recesses and protruding from the third side surface to one side in the second direction, and a plurality of fourth protruding portions connected to each of the plurality of fourth recesses and protruding from the fourth side surface to the other side in the second direction.Appendix 11. The semiconductor device according to any one of Appendixes 6 to 10, wherein the die pad portion has a first corner where the first side surface and the third side surface meet, a second corner where the first side surface and the fourth side surface meet, a third corner where the second side surface and the third side surface meet, and a fourth corner where the second side surface and the fourth side surface meet, wherein each of the plurality of first recesses does not meet either the first corner or the second corner, each of the plurality of second recesses does not meet either the third corner or the fourth corner, each of the plurality of third recesses does not meet either the first corner or the third corner, and each of the plurality of fourth recesses does not meet either the second corner or the fourth corner. Appendix 12. The semiconductor device according to any one of Appendixes 6 to 11, wherein the semiconductor element does not overlap any of the plurality of first recesses, the plurality of second recesses, the plurality of third recesses, or the plurality of fourth recesses when viewed in the thickness direction. Appendix 13. The semiconductor device according to any one of Supplementary Notes 1 to 12, wherein the semiconductor element has a first electrode and a third electrode arranged on one side in the thickness direction and a second electrode arranged on the other side in the thickness direction, and the second electrode is conductively joined to the first main surface.Supplementary Note 14. The semiconductor device according to Supplementary Note 13, wherein the semiconductor element is a switching element having a drain electrode, a source electrode, and a gate electrode, and the first electrode is the source electrode, the second electrode is the drain electrode, and the third electrode is the gate electrode.Supplementary Note 15. A vehicle comprising a power conversion device configured including the semiconductor device according to Supplementary Note 14.Appendix 16. A semiconductor device comprising: a semiconductor element; a first lead including a die pad portion; and a sealing resin covering the semiconductor element and a portion of the first lead, wherein the die pad portion has a first main surface facing one side in a thickness direction and on which the semiconductor element is mounted, a first back surface facing the other side in the thickness direction, a first side surface facing one side in a first direction orthogonal to the thickness direction, and a plurality of fifth protrusions protruding from the first side surface to one side in the first direction, wherein the first back surface is exposed from the sealing resin, and the plurality of fifth protrusions are located closer to the other side in the thickness direction of the first side surface and are arranged at intervals in a second direction orthogonal to the thickness direction and the first direction. Appendix 17. The semiconductor device according to Appendix 16, wherein each of the plurality of fifth protrusions has a fifth intermediate surface facing the other side in the thickness direction. Appendix 18. The semiconductor device according to claim 16 or 17, wherein the die pad portion has a second side surface facing the other side in the first direction, a third side surface facing one side in the second direction, a fourth side surface facing the other side in the second direction, a plurality of sixth protrusions protruding from the second side surface to the other side in the first direction, a plurality of seventh protrusions protruding from the third side surface to one side in the second direction, and a plurality of eighth protrusions protruding from the fourth side surface to the other side in the second direction, wherein the sixth protrusions are located closer to the other side in the thickness direction of the second side surface and are spaced apart in the second direction, the seventh protrusions are located closer to the other side in the thickness direction of the third side surface and are spaced apart in the first direction, and the eighth protrusions are located closer to the other side in the thickness direction of the fourth side surface and are spaced apart in the first direction. 19. The semiconductor device of claim 18, wherein each of the sixth protrusions has a sixth intermediate surface facing the other side in the thickness direction, each of the seventh protrusions has a seventh intermediate surface facing the other side in the thickness direction, and each of the eighth protrusions has an eighth intermediate surface facing the other side in the thickness direction.Supplementary Note 20. The semiconductor device according to Supplementary Note 18 or 19, wherein the die pad portion has a first corner where the first side surface and the third side surface meet, a second corner where the first side surface and the fourth side surface meet, a third corner where the second side surface and the third side surface meet, and a fourth corner where the second side surface and the fourth side surface meet, wherein each of the plurality of fifth protrusions does not meet either the first corner or the second corner, each of the plurality of sixth protrusions does not meet either the third corner or the fourth corner, each of the plurality of seventh protrusions does not meet either the first corner or the third corner, and each of the plurality of eighth protrusions does not meet either the second corner or the fourth corner.

[0116] A10, A11, A12, A20, A21: semiconductor device B1: vehicle 10: conductive member 11: first lead 111: die pad portion 1111: first main surface 1112: first back surface 1113: first side surface 1113a: first recess 1113b: first intermediate surface 1113c: first protrusion 1113d: fifth protrusion 1113e: fifth intermediate surface 1114: second side surface 1114a: second recess 1114b: second intermediate surface 1114c: second protrusion 1114d: sixth protrusion 1114e: sixth intermediate surface 1115: third side surface 1115a: third recess 1115b: third intermediate surface 1115c: third protrusion 1115d: seventh protrusion 1115e: Seventh intermediate surface 1116: Fourth side surface 1116a: Fourth recess 1116b: Fourth intermediate surface 1116c: Fourth protrusion 1116d: Eighth protrusion 1116e: Eighth intermediate surface 1117a: First corner 1117b: Second corner 1117c: Third corner 1117d: Fourth corner 112: First terminal 1121: First portion 1122: Second portion 1123: Third portion 113: Connecting portion 12: Second lead 121: Pad portion 122: Second terminal 1211: Second main surface 1212: Second back surface 1221: Fourth portion 1222: Fifth portion 1223: Sixth portion 13: Third lead 131: Pad portion 132: Third terminal portion 1311: Third main surface 1312: Third back surface 1321: Seventh portion 1322: Eighth portion 1323: Ninth portion 14: Fourth lead 141: Pad portion 142: Fourth terminal portion 1411: Fourth main surface 1412: Fourth back surface 1421: Tenth portion 1422: Eleventh portion 1423: Twelfth portion 20: Semiconductor element 201: First electrode 202: Second electrode 203: Third electrode 205: Semiconductor layer 29: Bonding layer 31: Connecting member 32: Connecting member 33: Connecting member 40: Sealing resin 41: First resin surface 42: Second resin surface 43: Third resin surface 44: Fourth resin surface 45: Fifth resin surface 46: Sixth resin surface 49: Groove 80: Charging facility 81: AC-DC converter (power converter) 82: Power receiving device 83: Storage battery 84: Drive system 91: Heat sink 92: Circuit board 919: Sheet material921: Solder L1: 1st dimension L2: 2nd dimension L3: 3rd dimension L4: 4th dimension L5: 5th dimension L6: 6th dimension L7: 7th dimension L8: 8th dimension

Claims

1. A semiconductor element; a first lead including a die pad portion; a sealing resin that covers the semiconductor element and a portion of the first lead, the die pad portion has a first main surface facing one side in a thickness direction and on which the semiconductor element is mounted, a first back surface facing the other side in the thickness direction, a first side surface facing one side in a first direction orthogonal to the thickness direction, and a plurality of first recesses recessed from the first back surface and the first side surface, the first rear surface is exposed from the sealing resin, The semiconductor device, wherein the plurality of first recesses are arranged at intervals in the thickness direction and in a second direction perpendicular to the first direction.

2. The semiconductor device according to claim 1 , wherein each of the plurality of first recesses has a first intermediate surface facing the other side in the thickness direction.

3. 2. The semiconductor device according to claim 1, wherein a first dimension, which is the distance between two adjacent first recesses in the second direction, is 1 / 5 to 5 times a second dimension, which is the length of the first recesses in the second direction.

4. the die pad portion has three or more of the first recessed portions, The semiconductor device according to claim 1 , wherein the plurality of first recesses are arranged at intervals in the second direction.

5. 2 . The semiconductor device according to claim 1 , wherein the die pad portion has a plurality of first protrusions that are connected to the plurality of first recesses, respectively, and that protrude from the first side surface to one side in the first direction.

6. the die pad portion has a second side surface facing the other side in the first direction, a third side surface facing one side in the second direction, a fourth side surface facing the other side in the second direction, a plurality of second recesses recessed from the first back surface and the second side surface, a plurality of third recesses recessed from the first back surface and the third side surface, and a plurality of fourth recesses recessed from the first back surface and the fourth side surface, the plurality of second recesses are arranged at intervals in the second direction, the third recesses are arranged at intervals in the first direction, The semiconductor device according to claim 1 , wherein the plurality of fourth recesses are arranged at intervals in the first direction.

7. Each of the plurality of second recesses has a second intermediate surface facing the other side in the thickness direction, each of the plurality of third recesses has a third intermediate surface facing the other side in the thickness direction; The semiconductor device according to claim 6 , wherein each of said plurality of fourth recesses has a fourth intermediate surface facing the other side in said thickness direction.

8. a third dimension that is a distance between two adjacent second recesses in the second direction is 1 / 5 to 5 times a fourth dimension that is a length of the second recesses in the second direction; a fifth dimension that is a distance between two of the third recesses that are adjacent to each other in the first direction is 1 / 5 to 5 times a sixth dimension that is a length of the third recesses in the first direction; 7. The semiconductor device according to claim 6, wherein a seventh dimension, which is the distance between two adjacent fourth recesses in the first direction, is 1 / 5 to 5 times an eighth dimension, which is the length of the fourth recesses in the first direction.

9. the die pad portion has three or more of the second recesses, three or more of the third recesses, and three or more of the fourth recesses, the second recesses are arranged at intervals in the second direction, the third recesses are arranged at intervals in the first direction, The semiconductor device according to claim 6 , wherein the plurality of fourth recesses are arranged at intervals in the first direction.

10. 7. The semiconductor device of claim 6, wherein the die pad portion has a plurality of second protrusions connected to each of the plurality of second recesses and protruding from the second side surface to the other side in the first direction, a plurality of third protrusions connected to each of the plurality of third recesses and protruding from the third side surface to one side in the second direction, and a plurality of fourth protrusions connected to each of the plurality of fourth recesses and protruding from the fourth side surface to the other side in the second direction.

11. the die pad portion has a first corner where the first side surface and the third side surface are in contact, a second corner where the first side surface and the fourth side surface are in contact, a third corner where the second side surface and the third side surface are in contact, and a fourth corner where the second side surface and the fourth side surface are in contact, each of the plurality of first recesses is not in contact with either the first corner portion or the second corner portion; each of the plurality of second recesses is not in contact with either the third corner portion or the fourth corner portion; each of the plurality of third recesses is not in contact with either the first corner portion or the third corner portion; The semiconductor device according to claim 6 , wherein each of the plurality of fourth recesses is not in contact with either the second corner portion or the fourth corner portion.

12. 7. The semiconductor device according to claim 6, wherein the semiconductor element does not overlap any of the plurality of first recesses, the plurality of second recesses, the plurality of third recesses, and the plurality of fourth recesses when viewed in the thickness direction.

13. the semiconductor element has a first electrode and a third electrode arranged on one side in the thickness direction, and a second electrode arranged on the other side in the thickness direction; The semiconductor device according to claim 1 , wherein the second electrode is electrically connected to the first main surface.

14. the semiconductor element is a switching element having a drain electrode, a source electrode, and a gate electrode; 14. The semiconductor device according to claim 13, wherein the first electrode is the source electrode, the second electrode is the drain electrode, and the third electrode is the gate electrode.

15. A vehicle comprising a power conversion device including the semiconductor device according to claim 14.

16. A semiconductor element; a first lead including a die pad portion; a sealing resin that covers the semiconductor element and a portion of the first lead, the die pad portion has a first main surface facing one side in a thickness direction and on which the semiconductor element is mounted, a first back surface facing the other side in the thickness direction, a first side surface facing one side in a first direction orthogonal to the thickness direction, and a plurality of fifth protrusions protruding from the first side surface to one side in the first direction, the first rear surface is exposed from the sealing resin, A semiconductor device, wherein the plurality of fifth protrusions are located toward the other side of the first side in the thickness direction and are arranged at intervals in a second direction perpendicular to the thickness direction and the first direction.

17. The semiconductor device according to claim 16 , wherein each of the plurality of fifth protrusions has a fifth intermediate surface facing the other side in the thickness direction.

18. the die pad portion has a second side surface facing the other side in the first direction, a third side surface facing one side in the second direction, a fourth side surface facing the other side in the second direction, a plurality of sixth protruding portions protruding from the second side surface toward the other side in the first direction, a plurality of seventh protruding portions protruding from the third side surface toward one side in the second direction, and a plurality of eighth protruding portions protruding from the fourth side surface toward the other side in the second direction, the sixth protrusions are located closer to the other side in the thickness direction of the second side surface and are arranged at intervals in the second direction, the seventh protrusions are located closer to the other side in the thickness direction of the third side surface and are spaced apart in the first direction, 17. The semiconductor device according to claim 16, wherein the eighth protrusions are located closer to the other side of the fourth side surface in the thickness direction and are spaced apart in the first direction.

19. each of the sixth protrusions has a sixth intermediate surface facing the other side in the thickness direction; each of the seventh protrusions has a seventh intermediate surface facing the other side in the thickness direction; 19. The semiconductor device according to claim 18, wherein each of the plurality of eighth protrusions has an eighth intermediate surface facing the other side in the thickness direction.

20. the die pad portion has a first corner where the first side surface and the third side surface are in contact, a second corner where the first side surface and the fourth side surface are in contact, a third corner where the second side surface and the third side surface are in contact, and a fourth corner where the second side surface and the fourth side surface are in contact, each of the plurality of fifth protrusions is not in contact with either the first corner portion or the second corner portion; each of the sixth protrusions is not in contact with either the third corner portion or the fourth corner portion; each of the seventh protrusions is not in contact with either the first corner portion or the third corner portion; 20 . The semiconductor device according to claim 18 , wherein each of the eighth protrusions is not in contact with either the second corner or the fourth corner.