Semiconductor device

Abstract

This semiconductor device comprises: a first metal plate that has electrical conductivity; a semiconductor chip that is disposed on the first metal plate and is electrically connected to the first metal plate; and a control circuit metal plate that is disposed at a position different from that of the first metal plate in the thickness direction of the semiconductor chip, has electrical conductivity, and constitutes a control circuit for controlling the semiconductor device. The control circuit includes at least one of a gate circuit, an auxiliary source circuit, a temperature characteristic detection circuit, and an electrical characteristic detection circuit.

Description

Semiconductor Devices

[0001] This disclosure relates to a semiconductor device. This application claims priority to Japanese Application No. 2023-088226, filed May 29, 2023, and incorporates by reference all of the contents of said Japanese application.

[0002] Techniques relating to semiconductor devices including control circuit boards have been disclosed (see, for example, Patent Documents 1, 2 and 3).

[0003] JP 2007-234753 A JP 2014-194014 A JP 2018-170362 A

[0004] A semiconductor device according to the present disclosure includes a first metal plate having conductivity, a semiconductor chip disposed on the first metal plate and electrically connected to the first metal plate, and a control circuit metal plate having conductivity and disposed at a position different from the first metal plate in a thickness direction of the semiconductor chip, the control circuit including at least one of a gate circuit, an auxiliary source circuit, a temperature characteristic detection circuit, and an electrical characteristic detection circuit.

[0005] FIG. 1 is a schematic perspective view of a semiconductor device in a first embodiment. FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a schematic bottom view of the semiconductor device shown in FIG. 1. FIG. 4 is a schematic front view of the semiconductor device shown in FIG. 1. FIG. 5 is a schematic rear view of the semiconductor device shown in FIG. 1. FIG. 6 is a schematic left side view of the semiconductor device shown in FIG. 1. FIG. 7 is a schematic right side view of the semiconductor device shown in FIG. 1. FIG. 8 is a schematic perspective view showing the semiconductor device shown in FIG. 1 in a state where a first resin member (described later) has been removed. FIG. 9 is a schematic plan view of the semiconductor device shown in FIG. 8. FIG. 10 is a schematic cross-sectional view taken along the line X-X in FIG. 9. FIG. 11 is a schematic plan view of a DBC substrate on which eight semiconductor chips (described later) are mounted. FIG. 12 is a schematic cross-sectional view of the DBC substrate shown in FIG. 11 taken along the line XII-XII in FIG. 12. FIG. 13 is a schematic perspective view showing an enlarged region where an insert metal is disposed. Fig. 14 is a schematic plan view showing an enlarged view of a portion of a semiconductor device when a solder resist is provided on a control circuit metal plate. Fig. 15 is a schematic perspective view showing a state in which a first resin member has been removed in a semiconductor device according to a second embodiment of the present disclosure. Fig. 16 is a schematic plan view of the semiconductor device shown in Fig. 15. Fig. 17 is a schematic bottom view of the semiconductor device shown in Fig. 15. Fig. 18 is a schematic bottom view showing an enlarged view of a portion of the interior of the semiconductor device shown in Fig. 15. Fig. 19 is a schematic perspective view showing a semiconductor device according to a third embodiment of the present disclosure.

[0006] [Problem to be Solved by the Present Disclosure] Recently, there has been a demand for semiconductor devices to be made compact so as to reduce their size while still ensuring stable operation.

[0007] Therefore, one object is to provide a semiconductor device that can ensure stable operation while being made compact.

[0008] Effect of the Present Disclosure According to such a semiconductor device, it is possible to ensure stable operation while achieving compactness.

[0009] [Description of Embodiments of the Present Disclosure] (1) A semiconductor device according to the present disclosure includes a first metal plate having conductivity, a semiconductor chip disposed on the first metal plate and electrically connected to the first metal plate, and a control circuit metal plate having conductivity and configured to configure a control circuit for controlling the semiconductor device, the control circuit including at least one of a gate circuit, an auxiliary source circuit, a temperature characteristic detection circuit, and an electrical characteristic detection circuit.

[0010] According to the semiconductor device disclosed herein, the control circuit formed by the control circuit metal plate includes at least one of a gate circuit, an auxiliary source circuit, a temperature characteristic detection circuit, and an electrical characteristic detection circuit, enabling more precise control of the semiconductor device. The control circuit metal plate constituting the control circuit including at least one of the gate circuit, the auxiliary source circuit, the temperature characteristic detection circuit, and the electrical characteristic detection circuit is positioned at a different position in the thickness direction of the semiconductor chip from the first metal plate on which the semiconductor chip is mounted. This allows the first metal plate to be expanded while suppressing an increase in the overall size of the semiconductor device in a direction perpendicular to the thickness direction of the first metal plate. In other words, regardless of the size of the control circuit metal plate, the area of ​​the first metal plate that contributes to improving the heat dissipation of the semiconductor chip can be increased. Furthermore, because the control circuit metal plate is positioned at a different position from the semiconductor chip, which becomes hot, thermal interference from the semiconductor chip can be prevented. Therefore, stable operation can be ensured while achieving a compact semiconductor device.

[0011] In this case, the control circuit metal plate does not necessarily have to have a substrate configuration including an insulating layer, and therefore is not subject to the heat resistance constraints of an insulating layer when an insulating layer is included during the manufacture of a semiconductor device, etc. Furthermore, if the insulating layer can be omitted, costs can be reduced. Furthermore, if the insulating layer is omitted, the constraints on the thickness direction of the control circuit metal plate are relaxed, allowing the thickness of the control circuit metal plate to be increased, reducing parasitic resistance and parasitic inductance and ensuring more stable operation. Furthermore, if the insulating layer can be omitted, the control circuit metal plate can be metal-bonded to other metal components, improving productivity.

[0012] (2) In the above (1), the control circuit metal plate may include an area overlapping the first metal plate when viewed in the thickness direction of the semiconductor chip. This allows the first metal plate to be enlarged while effectively utilizing the area where the control circuit metal plate is located in the thickness direction of the semiconductor chip. Therefore, it is possible to more reliably achieve compactness while improving heat dissipation.

[0013] (3) In the above (1) or (2), a first resin member that encapsulates the semiconductor chip may be further provided. The control circuit metal plate may include a first terminal having a portion exposed from the first resin member and a first frame having a portion covered by the first resin member. The first terminal and the first frame may be integrally formed. In this manner, the first frame, which is included in the control circuit metal plate and integrally formed with the first terminal, can be held by the second resin member described below, allowing the first terminal to be positioned at the same time, thereby improving assembly during manufacturing. Here, "integral" means that the first terminal and the first frame are manufactured from a single member, rather than being manufactured by combining multiple members by bonding, connecting with screws, or the like.

[0014] (4) In the above (1) or (2), a first resin member may be further provided to seal the semiconductor chip. The control circuit metal plate may include a first terminal having a portion exposed from the first resin member and a first frame having a portion covered by the first resin member. The first terminal and the first frame may be configured as separate bodies. The first terminal may be held by a second resin member. In this manner, by metal-joining the first frame, the first frame can be fixed and electrically connected at the same time. Here, "separate bodies" is a concept opposite to the above-mentioned "integral body," and the first terminal and the first frame are not manufactured from a single member, but are manufactured by combining multiple members by bonding, connecting with screws, or the like.

[0015] (5) In any of (1) to (4) above, the semiconductor device may further include a first resin member that seals the semiconductor chip and a second resin member that is provided separately from the first resin member. The control circuit metal plate may be disposed on the second resin member. In this manner, the control circuit metal plate can be positioned and fixed using the second resin member. This eliminates the need for a manufacturing jig, thereby improving productivity. Furthermore, when bonding wires to the control circuit metal plate by ultrasonic bonding, the second resin member functions as a base. Therefore, ultrasonic vibrations are applied efficiently, ensuring stable bonding. Furthermore, because the second resin member is an insulator, it can be disposed while being reliably insulated from the first metal plate, ensuring stable operation.

[0016] (6) In any of (1) to (5) above, the semiconductor device may further include a first resin member that encapsulates the semiconductor chip and a second resin member that is provided separately from the first resin member. The control circuit metal plate may include a first terminal having a protruding portion protruding from the second resin member and a retaining portion retained by the second resin member, and a first frame having a portion covered by the first resin member. The retaining portion may include a terminal exposed portion exposed from the second resin member. The first frame may be bonded to the first terminal in a region where the terminal exposed portion is located when viewed in the thickness direction of the semiconductor chip. This allows the metals of the first terminal and the first frame to overlap at the terminal exposed portion, enabling metal bonding such as fusion bonding by laser welding or liquid phase bonding by solder or brazing material, thereby achieving electrical connection simultaneously with fixation. This reduces bonding time and improves productivity.

[0017] (7) In any of (1) to (6) above, the semiconductor device may further include a first resin member encapsulating the semiconductor chip, a second resin member provided separately from the first resin member, and an insert metal held by the second resin member and bonded to the control circuit metal plate. The insert metal may include a first exposed portion exposed from the second resin member. The insert metal may be bonded to the control circuit metal plate in a region where the first exposed portion is located when viewed in the thickness direction of the semiconductor chip. This allows the metals of the insert metal and the control circuit metal plate to overlap at the first exposed portion, enabling metal bonding such as fusion bonding using laser welding or liquid phase bonding using solder or brazing material, thereby fixing the second resin member to the control circuit metal plate. This reduces bonding time and improves productivity. Furthermore, in the temperature characteristic detection circuit, the control circuit metal plate and the first metal plate can be connected via the insert metal, improving thermal conduction between the control circuit metal plate and the first metal plate. Therefore, when a thermistor is attached to the temperature characteristic detection circuit, the temperature of the semiconductor chip and the water-cooling temperature of the semiconductor device can be monitored with higher accuracy.

[0018] (8) In any of (1) to (6) above, the semiconductor device may further include a first resin member encapsulating the semiconductor chip, a second resin member provided separately from the first resin member, and an insert metal held in the second resin member and bonded to the first metal plate and the control circuit metal plate. The insert metal may include a second exposed portion exposed from the second resin member. The insert metal may be bonded to the first metal plate in a region where the second exposed portion is located when viewed in the thickness direction of the semiconductor chip. This allows the metals of the insert metal and the first metal plate to overlap at the second exposed portion, enabling metal bonding such as fusion bonding using laser welding or liquid phase bonding using solder or brazing material, thereby fixing the second resin member to the first metal plate. This reduces bonding time and improves productivity. Furthermore, the temperature characteristic detection circuit can perform temperature monitoring using a thermistor with high accuracy, as described above.

[0019] (9) In any of the above (1) to (8), a solder resist may be provided on a portion of the control circuit metal plate. By doing so, when joining electronic components to the control circuit metal plate, the solder resist can prevent the outflow of joining material when joining the electronic components, thereby ensuring reliable positioning and electrical connection of the electronic components.

[0020] (10) In any of (1) to (9) above, the semiconductor device may further include electronic components electrically connected to the control circuit metal plate. This allows for highly accurate control of the semiconductor device using electronic components, such as suppressing ringing and oscillation when the transistor is operating when the semiconductor chip is used as a transistor chip, and monitoring the temperature of the transistor chip, the temperature of the diode chip when the semiconductor chip is used as a diode chip, and the water-cooling temperature of the semiconductor device. Furthermore, if a control circuit metal plate with electronic components already installed is prepared, a circuit including the electronic components can be manufactured simply by placing the control circuit metal plate, thereby improving productivity.

[0021] (11) In any of (1) to (10) above, the semiconductor device may further include a first resin member that encapsulates the semiconductor chip and a second resin member that is provided separately from the first resin member. The second resin member may be provided with an engaging portion that engages with the control circuit metal plate. This allows the control circuit metal plate to be positioned relative to the second resin member using the engaging portion. Therefore, a jig used for positioning the control circuit metal plate is not required, thereby improving productivity.

[0022] (12) In any of the above (1) to (11), the first metal plate may be a lead frame or an electrode on a substrate having an insulating layer on the surface opposite to the surface on which the semiconductor chip is disposed in the thickness direction of the semiconductor chip. If the first metal plate is a lead frame, there is no need to provide an insulating layer, which allows for a reduction in the number of components and a simpler configuration. Furthermore, by using the first metal plate as an electrode on the substrate, the above configuration can be achieved using, for example, a DBC (Direct Bonded Copper) substrate, thereby improving production efficiency and reducing costs.

[0023] (13) In any of (1) to (12) above, the semiconductor device may further include a first resin member that encapsulates the semiconductor chip and a second resin member that is provided separately from the first resin member. The first metal plate may be a lead frame. The first metal plate may include a connection portion that extends in the thickness direction of the semiconductor chip. The first metal plate may be joined to the control circuit metal plate at the connection portion. In this way, the connection portion provided on the first metal plate, which is the lead frame, can be used to join to the control circuit metal plate. This allows for a further reduction in the number of parts and improved productivity.

[0024] (14) In any of (1) to (13) above, the semiconductor device may further include a first resin member that encapsulates the semiconductor chip, a second resin member provided separately from the first resin member, and an insulating layer that is disposed on the surface of the first metal plate opposite the surface on which the semiconductor chip is disposed in the thickness direction of the semiconductor chip. The control circuit metal plate may be disposed on the second resin member. The second resin member may be disposed on the first metal plate or on the insulating layer. The melting point of the second resin member may be higher than the melting point of the first resin member. This reduces the risk of the second resin member melting when the molten first resin member is poured and molded after the second resin member is disposed. Therefore, stable production can be achieved.

[0025] (15) In any of (1) to (14) above, the semiconductor device may further include an insulating layer disposed on a surface of the first metal plate opposite the surface on which the semiconductor chip is disposed in the thickness direction of the semiconductor chip, and a second metal plate disposed on the insulating layer opposite the first metal plate in the thickness direction of the semiconductor chip. The second metal plate may have a slit formed therein and spaced apart from the outer edge of the second metal plate. By doing so, the distance from end to end can be shortened when joining the second metal plate and the heat sink because the second metal plate is divided by the slit. This reduces stress on the end due to differences in linear expansion coefficients during temperature changes. In this case, the bonding material bonding the second metal plate and the heat sink is disposed inside the end face of the slit. Furthermore, because the slit is formed at a distance from the outer edge of the second metal plate, the outer periphery of the second metal plate is pressed by a mold during resin molding, reducing the risk of resin entering the slit. Therefore, stress at the joint can be more reliably alleviated.

[0026] (16) In any of (1) to (14) above, the first metal plate may be a lead frame. A groove may be formed on the surface of the first metal plate opposite the surface on which the semiconductor chip is disposed, spaced apart from the outer edge of the first metal plate. This shortens the distance from one end to the other when joining the first metal plate to the heat sink. This reduces stress on the end due to differences in linear expansion coefficients during temperature changes. In this case, because the groove is formed at a distance from the outer edge of the first metal plate, the risk of resin entering the groove during resin molding can be reduced. Therefore, stress at the joint can be more reliably alleviated.

[0027] (17) In any of (1) to (16) above, the semiconductor device may further include a first resin member encapsulating the semiconductor chip, a first terminal, and a second terminal different from the first terminal. The first terminal and the second terminal may each be one of a P terminal, an N terminal, an O terminal, a gate terminal, an auxiliary source terminal, a temperature characteristic detection terminal, and an electrical characteristic detection terminal. The first resin member may have a rib disposed between the first terminal and the second terminal. At least one of the first terminal and the second terminal may have a notch for receiving the rib. This allows the first terminal and the second terminal to be disposed close to each other while increasing the creepage distance between them. This reduces inductance while minimizing the size of the semiconductor device. Furthermore, the notch for receiving the rib allows the fillet at the base of the rib to be large without increasing the distance between the first terminal and the second terminal, thereby reinforcing the strength of the rib while suppressing an increase in parasitic inductance.

[0028] [Details of the Embodiments of the Present Disclosure] Next, embodiments of the semiconductor device of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference characters, and description thereof will not be repeated.

[0029] (First Embodiment) A semiconductor device according to a first embodiment of the present disclosure will be described. FIG. 1 is a schematic perspective view of the semiconductor device according to the first embodiment. FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1. FIG. 3 is a schematic bottom view of the semiconductor device shown in FIG. 1. FIG. 4 is a schematic front view of the semiconductor device shown in FIG. 1. FIG. 4 is a view seen in the direction indicated by arrow IV in FIG. 2. FIG. 5 is a schematic rear view of the semiconductor device shown in FIG. 1. FIG. 5 is a view seen in the direction indicated by arrow V in FIG. 2. FIG. 6 is a schematic left side view of the semiconductor device shown in FIG. 1. FIG. 6 is a view seen in the direction indicated by arrow VI in FIG. 2. FIG. 7 is a schematic right side view of the semiconductor device shown in FIG. 1. FIG. 7 is a view seen in the direction indicated by arrow VII in FIG. 2. FIG. 8 is a schematic perspective view showing the semiconductor device shown in FIG. 1 with a first resin member, described later, removed. FIG. 9 is a schematic plan view of the semiconductor device shown in FIG. 8. FIG. 10 is a schematic cross-sectional view taken along the line X-X in FIG. 9. 11 is a schematic plan view showing a DBC substrate mounted with eight semiconductor chips (described later). In the drawings shown in FIG. 1 and subsequent figures, the Z direction indicates the thickness direction of the semiconductor chips (described later), the Y direction indicates the direction in which first main terminals and second main terminals (described later) are aligned, and the X direction indicates the direction perpendicular to the Y direction. The X direction, Y direction, and Z direction are all perpendicular to each other.

[0030] 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 and 11 , semiconductor device 10 a in the first embodiment includes first resin member 11 a, second resin member 12 a, DBC (Direct Bonded Copper) substrate 13 a as a base substrate, P terminal 14 a as a first main terminal, N terminal 14 b as a second main terminal, O terminal 14 c as a third main terminal, control circuit metal plate 15 a, and control circuit metal plate 15 b.

[0031] The control circuit metal plate 15a includes a first gate terminal 21a, a first auxiliary source terminal 21b, and an electrical characteristic detection terminal 21d. The control circuit metal plate 15b includes a second gate terminal 22a, a second auxiliary source terminal 22b, a first temperature characteristic detection terminal 21c, and a second temperature characteristic detection terminal 22c. In this embodiment, the P terminal 14a constitutes a positive terminal, the N terminal 14b constitutes a negative terminal, and the O terminal 14c constitutes an AC terminal. The semiconductor device 10a employs a so-called 2-in-1 configuration.

[0032] The semiconductor device 10a includes resistors 23a and 23b as electronic components electrically connected to the control circuit metal plate 15a. Resistors 23a and 23b are attached to the first gate terminal 21a so as to connect the divided regions. The semiconductor device 10a also includes resistors 23c and 23d as electronic components electrically connected to the control circuit metal plate 15b, and a thermistor 24a. Resistors 23c and 23d are attached to the second gate terminal 22a so as to connect the divided regions. The thermistor 24a is attached to a region disposed inside the semiconductor device 10a so as to connect the first temperature characteristic detection terminal 21c and the second temperature characteristic detection terminal 22c. Resistors 23a, 23b, 23c, and 23d contribute to suppressing ringing and oscillation when a transistor such as a semiconductor chip 51a (described later) is used as a transistor chip. The thermistor 24a is effectively used to monitor the temperature of a transistor chip, the temperature of a diode chip when a semiconductor chip 51e (described later) is used as a diode chip, the water-cooling temperature of the semiconductor device 10a, etc. The electrical characteristic detection terminal 21d is, for example, a DESAT terminal that detects overcurrent. The electrical characteristic detection terminal 21d is electrically connected to a first region 41a of a first metal plate 31a (described later) via an insert metal 25a or an insert metal 25b (described later).

[0033] The first resin member 11a encapsulates electronic components included in the semiconductor device 10a, including a semiconductor chip (described later) included in the semiconductor device 10a. The first resin member 11a has a rectangular parallelepiped shape, excluding ribs (described later). The P terminal 14a, N terminal 14b, O terminal 14c, first gate terminal 21a, second gate terminal 22a, first auxiliary source terminal 21b, second auxiliary source terminal 22b, first temperature characteristic detection terminal 21c, second temperature characteristic detection terminal 22c, and electrical characteristic detection terminal 21d are each configured so that a portion thereof is exposed from the side surface of the first resin member 11a. The first resin member 11a functions as a molding resin that exposes a portion of the above-mentioned terminals and covers the entire device. The first resin member 11a is made of a thermosetting resin, such as epoxy resin.

[0034] The first resin member 11a has a rib 17a that protrudes outward. Fillets 18a and 18b are formed at the base of the rib 17a, making it thicker. In this embodiment, the rib 17a is disposed between the P terminal 14a and the N terminal 14b. The X-direction length of the rib 17a is longer than the X-direction length of the P terminal 14a and the N terminal 14b exposed from the first resin member 11a. Four through holes 19a, 19b, 19c, and 19d are formed in the first resin member 11a, penetrating the thickness direction. These through holes 19a, 19b, 19c, and 19d are marks left by pressure pins provided in the molding die used to mold the first resin member 11a. To expose the surface of the second metal plate 32a (described later) from the first resin member 11a, the semiconductor device 10a must be pressed against the lower die of the molding die before encapsulation. If the pressure pin presses the conductive portion of the first metal plate 31a or the like, the conductive portion may be exposed from the first resin member 11a, making insulation difficult. Therefore, by pressing the pressure pin against the second resin member 12a (described later), the portion exposed from the first resin member 11a becomes an insulator, preventing the conductive portion from being exposed. The through holes 19a, 19b, 19c, and 19d are arranged at positions overlapping the second resin member 12a (described later) when viewed in the thickness direction.

[0035] The second resin member 12a is provided separately from the first resin member 11a. The second resin member 12a is a frame-shaped member and is disposed along the outer edge of the insulating layer 33a (described later) when viewed in the thickness direction. The control circuit metal plate 15a and the control circuit metal plate 15b are disposed on the second resin member 12a. The second resin member 12a is formed with an engaging portion 28a that engages with the control circuit metal plate 15a and an engaging portion 28b that engages with the control circuit metal plate 15b. The second resin member 12a also has engaging portions 29a, 29b, and 29c that engage with the respective terminals. The engaging portions 28a, 28b, 29a, 29b, and 29c enable the control circuit metal plate 15a, the control circuit metal plate 15b, the P terminal 14a, the N terminal 14b, and the O terminal 14c to be positioned relative to the second resin member 12a.

[0036] The melting point of the second resin member 12a is higher than that of the first resin member 11a. Examples of materials for the second resin member 12a include polyphenylene sulfide (PPS) and polybutylene terephthalate (PBT). The second resin member 12a is manufactured by, for example, injection molding, cutting, or three-dimensional shaping. The second resin member 12a includes a snap-fit ​​portion 37a that snaps into engagement with the control circuit metal plate 15a and a snap-fit ​​portion 37b that snaps into engagement with the control circuit metal plate 15b. The second resin member 12a, which is disposed along the outer edge, is made of a resin material similar to the first resin member 11a, and thus can be chemically bonded. Furthermore, providing texture, such as a embossed finish, on the surface of the second resin member 12a can provide a mechanical bond through an anchor effect. Furthermore, by adding a protrusion that protrudes from the outer periphery of the second resin member 12a, a mechanical bond can be further achieved through an anchor effect. This increases the adhesion strength between the first resin member 11a and the second resin member 12a, thereby suppressing peeling of the first resin member 11a starting from the outer edge. The second resin member 12a has an anchor effect as a protrusion, but the anchor effect may also be achieved as a recessed shape.

[0037] The DBC substrate 13a includes a first metal plate 31a, a second metal plate 32a, and an insulating layer 33a. That is, the DBC substrate 13a is composed of the first metal plate 31a, the second metal plate 32a, and the insulating layer 33a. The first metal plate 31a is disposed on one surface of the insulating layer 33a in the thickness direction, and the second metal plate 32a is disposed on the other surface of the insulating layer 33a in the thickness direction. That is, the DBC substrate 13a is configured such that the insulating layer 33a is sandwiched between the first metal plate 31a and the second metal plate 32a, which are disposed on both sides in the thickness direction. The insulating layer 33a may be made of, for example, Al. ２ O ３ (alumina), SiN (silicon nitride), and AlN (aluminum nitride) are selected.

[0038] The first metal plate 31a includes a first region 41a, a second region 42a, a third region 43a, a fourth region 44a, a fifth region 45a, a sixth region 46a, a seventh region 47a, an eighth region 48a, and a ninth region 49a (see FIG. 11 in particular). That is, the first metal plate 31a is divided into multiple regions, specifically, nine regions, on the insulating layer 33a. The first region 41a, the second region 42a, and the third region 43a form the main circuit plates through which current flows during operation of the semiconductor device 10a. The other regions are bonded to the control circuit metal plate 15a and the control circuit metal plate 15b and are used for fixation and thermal coupling to the second metal plate 32a. That is, the fourth region 44a, the fifth region 45a, the sixth region 46a, the seventh region 47a, the eighth region 48a and the ninth region 49a are used for the fixation described above, and further the sixth region 46a and the seventh region 47a are also used for the thermal coupling described above.

[0039] The second metal plate 32a is not divided into multiple regions but is formed as a single sheet. Two slits 34a and 34b are formed in the second metal plate 32a (see FIG. 3 in particular). The slits 34a and 34b are formed as a pair extending in the X direction with a gap in the Y direction. The slits 34a and 34b are each formed with a gap from the outer edge 35a of the second metal plate 32a. The slits 34a and 34b are each provided to penetrate the second metal plate 32a in the thickness direction. In other words, in the regions where the slits 34a and 34b are located, the insulating layer 33a is exposed when viewed from the bottom side.

[0040] The P terminal 14a is formed by bending a strip-shaped metal plate. The P terminal 14a has a portion covered by the first resin member 11a and a portion exposed from the first resin member 11a. The P terminal 14a has a circular hole 16a penetrating in the thickness direction in the portion exposed from the first resin member 11a. Like the P terminal 14a, the N terminal 14b and the O terminal 14c are also formed by bending a strip-shaped metal plate, and have circular holes 16b and 16c penetrating in the thickness direction in the portions exposed from the first resin member 11a. The P terminal 14a is bonded to the first region 41a of the first metal plate 31a inside the semiconductor device 10a. The N terminal 14b is bonded to the third region 43a of the first metal plate 31a inside the semiconductor device 10a. The O terminal 14c is bonded to the second region 42a of the first metal plate 31a inside the semiconductor device 10a. As a result, the P terminal 14a is electrically connected to the first region 41a of the first metal plate 31a, the N terminal 14b is electrically connected to the third region 43a of the first metal plate 31a, and the O terminal 14c is electrically connected to the second region 42a of the first metal plate 31a. The electrical bonding is achieved by using a bonding material such as solder or a sintered material, fusion bonding such as laser welding or ultrasonic bonding, or a conductive material such as a wire.

[0041] In this embodiment, the second resin member 12a is provided with engaging portions 29a and 29b that engage with the P terminal 14a, the N terminal 14b, and the O terminal 14c. Therefore, the P terminal 14a, the N terminal 14b, and the O terminal 14c can be positioned relative to the second resin member 12a using the engaging portions 29a and 29b. This eliminates the need for jigs to position the P terminal 14a, the N terminal 14b, and the O terminal 14c, thereby improving productivity. The engaging portions 29b are convex in shape to position the P terminal 14a, the N terminal 14b, and the O terminal 14c, but they may also be concave in shape to position the P terminal 14a, the N terminal 14b, and the O terminal 14c.

[0042] The P terminal 14a, N terminal 14b, and O terminal 14c have a stepped shape at the portion exposed from the first resin member 11a, and are provided with a fastening surface with circular holes 16a, 16b, and 16c, and a pressing surface at the base of the first resin member 11a. When molding the first resin member 11a, the exposed portions of the P terminal 14a, N terminal 14b, and O terminal 14c are crushed by the upper and lower molds of the molding die, which may cause deformation. By separating the pressing surface and the fastening surface, it is possible to avoid changes in the shape of the fastening surface even if the pressing surface is crushed, thereby preventing poor fastening and increased contact resistance during fastening.

[0043] When molding the P terminal 14a, N terminal 14b, and O terminal 14c with the first resin member 11a, they are crushed by the molding die, which may cause displacement and stress to be applied to the joints between the P terminal 14a, N terminal 14b, and O terminal 14c and the first metal plate 31a. The P terminal 14a has a through-hole that fits into an engaging portion 29a provided on the second resin member 12a, creating a catch at this fitting portion and suppressing stress from being applied to the joint. The N terminal 14b is metal-bonded by placing an insert mold (not shown) provided on the second resin member 12a on its bottom surface, creating a catch at this joint and suppressing stress from being applied to the joint. The O terminal 14c is fixed by molding its periphery with the second resin member 12a, creating a catch at this fixing portion and suppressing stress from being applied to the joint. This can improve the reliability of the joints between the P terminal 14a, the N terminal 14b, the O terminal 14c and the first metal plate 31a.

[0044] The P terminal 14a has a notch 36a formed therein to receive the fillet 18a. The N terminal 14b has a notch 36b formed therein to receive the fillet 18b. These notches 36a and 36b allow the fillets 18a and 18b to be large without increasing the distance between the P terminal 14a and the N terminal 14b, thereby reinforcing the strength of the rib 17a while suppressing an increase in parasitic inductance.

[0045] Control circuit metal plate 15a and control circuit metal plate 15b are each disposed at a different position in the thickness direction from first metal plate 31a. That is, control circuit metal plate 15a and control circuit metal plate 15b each overlap first metal plate 31a when viewed in the thickness direction. In this embodiment, the control circuit formed by control circuit metal plate 15a and control circuit metal plate 15b includes all of the gate circuit, auxiliary source circuit, temperature characteristic detection circuit, and electrical characteristic detection circuit.

[0046] The semiconductor device 10a of the first embodiment includes a semiconductor chip (first semiconductor chip) 51a, a semiconductor chip (second semiconductor chip) 51b, a semiconductor chip (third semiconductor chip) 51c, a semiconductor chip (fourth semiconductor chip) 51d, a semiconductor chip (fifth semiconductor chip) 51e, a semiconductor chip (sixth semiconductor chip) 51f, a semiconductor chip (seventh semiconductor chip) 51g, and a semiconductor chip (eighth semiconductor chip) 51h. The semiconductor chips 51a, 51b, 51c, and 51d are each vertical transistor chips. In this embodiment, the semiconductor chips 51a, 51b, 51c, and 51d are each, for example, metal-oxide-semiconductor field effect transistors (MOSFETs). The semiconductor chip 51a, the semiconductor chip 51b, the semiconductor chip 51c, and the semiconductor chip 51d are each a switching element. The semiconductor chip 51a and the semiconductor chip 51b form an upper arm in the semiconductor device 10a, and the semiconductor chip 51c and the semiconductor chip 51d form a lower arm in the semiconductor device 10a. The semiconductor chip 51e, the semiconductor chip 51f, the semiconductor chip 51g, and the semiconductor chip 51h are each a diode chip. In this embodiment, the semiconductor chip 51e, the semiconductor chip 51f, the semiconductor chip 51g, and the semiconductor chip 51h are each a Schottky barrier diode (SBD).

[0047] Figure 12 is a schematic cross-sectional view of the DBC substrate 13a shown in Figure 11 taken along the line XII-XII in Figure 12. Referring also to Figure 12, the drain electrode 52a of the semiconductor chip 51a is bonded to the first metal plate 31a by bonding material 38a. The semiconductor chips 51b, 51c, and 51d are similarly bonded to the first metal plate 31a. The cathode electrode 52b of the semiconductor chip 51e is bonded to the first metal plate 31a by bonding material 38b. The semiconductor chips 51f, 51g, and 51h are similarly bonded to the first metal plate 31a.

[0048] The source electrode 53a of the semiconductor chip 51a, the anode electrode 54a of the semiconductor chip 51e, and the second region 42a of the first metal plate 31a are electrically connected by wire 56a, which is a conductive member. Similarly, the source electrode 53b of the semiconductor chip 51b, the anode electrode 54b of the semiconductor chip 51f, and the second region 42a of the first metal plate 31a are electrically connected by wire 56b. The source electrode 53c of the semiconductor chip 51c, the anode electrode 54c of the semiconductor chip 51g, and the third region 43a of the first metal plate 31a are electrically connected by wire 56c. Similarly, the source electrode 53d of the semiconductor chip 51d, the anode electrode 54d of the semiconductor chip 51h, and the second region 42a of the first metal plate 31a are electrically connected by wire 56d. The wire connections are implemented by wire bonding.

[0049] The gate electrode of the semiconductor chip 51a is electrically connected to the first gate terminal 21a by a wire 57a. The gate electrode of the semiconductor chip 51b is electrically connected to the first gate terminal 21a by a wire 57b. The gate electrode of the semiconductor chip 51c is electrically connected to the second gate terminal 22a by a wire 57c. The gate electrode of the semiconductor chip 51d is electrically connected to the second gate terminal 22a by a wire 57d. The source electrode 53a of the semiconductor chip 51a is electrically connected to the first auxiliary source terminal 21b by a wire 58a. The source electrode 53b of the semiconductor chip 51b is electrically connected to the first auxiliary source terminal 21b by a wire 58b. The source electrode 53c of the semiconductor chip 51c is electrically connected to the second auxiliary source terminal 22b by a wire 58c. The source electrode 53d of the semiconductor chip 51d is electrically connected to the second auxiliary source terminal 22b by a wire 58d.

[0050] The first gate terminal 21a included in the control circuit metal plate 15a includes a first terminal 26a having a portion exposed from the first resin member 11a and a first frame 27a having a portion covered by the first resin member 11a. In this embodiment, the first terminal 26a and the first frame 27a of the first gate terminal 21a are configured separately. The same applies to the first auxiliary source terminal 21b. The second gate terminal 22a is configured integrally with the first terminal 26a and the first frame 27a. The same applies to the second auxiliary source terminal 22b, the first temperature characteristic detection terminal 21c, the second temperature characteristic detection terminal 22c, and the electrical characteristic detection terminal 21d.

[0051] The semiconductor device 10a includes insert metals 25a and 25b. FIG. 13 is a schematic perspective view showing an enlarged view of the regions where the insert metals 25a and 25b are arranged. Also referring to FIG. 13 , the insert metals 25a and 25b are held in the second resin member 12a. In this embodiment, the insert metals 25a and 25b are insert-molded and embedded inside the second resin member 12a during molding. The insert metals 25a and 25b include a first exposed portion 61a and a second exposed portion 62a exposed from the second resin member 12a. The first exposed portion 61a is a surface facing the first temperature characteristic detection terminal 21c and the second temperature characteristic detection terminal 22c, respectively. The second exposed portion 62a is a surface facing the sixth region 46a and the seventh region 47a of the first metal plate 31a, respectively. The insert metal 25a is joined to the first metal plate 31a and the control circuit metal plate 15b. Specifically, the insert metal 25a is joined to the second temperature characteristic detection terminal 22c of the control circuit metal plate 15b in the region where the first exposed portion 61a is located. In this case, the joining is performed by laser welding applied in the thickness direction. The insert metal 25a is also joined to the sixth region 46a of the first metal plate 31a in the region where the second exposed portion 62a is located. In this case, the joining is also performed by laser welding applied in the thickness direction. In this way, the second temperature characteristic detection terminal 22c and the first metal plate 31a are connected by a metal member via the insert metal 25a. Similarly, the first temperature characteristic detection terminal 21c and the first metal plate 31a are joined by a metal member for the insert metal 25b. In addition to the area enlarged in Figure 13, the semiconductor device 10a also includes insert metals that join the first gate terminal 21a and the first metal plate 31a, the first auxiliary source terminal 21b and the first metal plate 31a, the second gate terminal 22a and the first metal plate 31a, the second auxiliary source terminal 22b and the first metal plate 31a, and the electrical characteristic detection terminal 21d and the first metal plate 31a.

[0052] In the semiconductor device 10a, the first gate terminal 21a of the control circuit metal plate 15a includes a first terminal 26a and a first frame 27a (see FIG. 9 in particular). The first terminal 26a has a protruding portion protruding from the second resin member 12a and a retaining portion retained by the second resin member 12a. The retaining portion includes a terminal exposed portion exposed from the second resin member 12a. The first frame 27a is joined to the first terminal 26a in a region where the terminal exposed portion is located when viewed in the thickness direction.

[0053] Next, a brief description of the manufacturing process for the semiconductor device 10a configured as described above will be given. First, a DBC substrate 13a is prepared by forming a circuit pattern, such as the first region 41a, on a first metal plate 31a and forming the slits 34a and the like on a second metal plate 32a. A second resin member 12a having the above-described shape is also prepared, with the first terminal 26a of the control circuit metal plate 15a, the insert metal 25a, and the like inserted therein. The O terminal 14c is also partially molded and attached to the second resin member 12a in advance. Then, a semiconductor chip 51a and the like are bonded to the first metal plate 31a. The second resin member 12a is then attached to the DBC substrate 13a using an adhesive or the like. Next, the P terminal 14a, the N terminal 14b, the control circuit metal plate 15a, and the control circuit metal plate 15b are placed on the second resin member 12a, and the P terminal 14a, the N terminal 14b, and the O terminal 14c are joined to the first metal plate 31a, and the control circuit metal plate 15a and the control circuit metal plate 15b are joined to the first terminal 26a and the insert metal 25a by laser welding. Electronic components such as the resistor 23a are previously joined to the control circuit metal plate 15a and the control circuit metal plate 15b. Then, the semiconductor chip 51a and the like are electrically connected by wire bonding. Then, the semiconductor chip 51a and the like are encapsulated in the first resin member 11a by transfer molding. In this manner, the semiconductor device 10a is manufactured.

[0054] According to the semiconductor device 10a of the present disclosure, the control circuit formed by the control circuit metal plate 15a and the control circuit metal plate 15b includes a gate circuit, an auxiliary source circuit, a temperature characteristic detection circuit, and an electrical characteristic detection circuit, enabling more precise control of the semiconductor device 10a. The control circuit metal plate 15a and the control circuit metal plate 15b, which constitute the control circuit including the gate circuit, the auxiliary source circuit, the temperature characteristic detection circuit, and the electrical characteristic detection circuit, are positioned at a different position in the thickness direction of the semiconductor chip 51a from the first metal plate 31a on which the semiconductor chip 51a is mounted. This allows the first metal plate 31a to be significantly enlarged while preventing the overall size of the semiconductor device 10a from increasing in the direction perpendicular to the thickness direction of the first metal plate 31a. In other words, the area of ​​the first metal plate 31a, which contributes to improving the heat dissipation of the semiconductor chip 51a, can be increased regardless of the size of the control circuit metal plate 15a and the control circuit metal plate 15b. Furthermore, since the control circuit metal plate 15a and the control circuit metal plate 15b are disposed at positions different from the semiconductor chip 51a etc., which become hot, it is possible to prevent thermal interference from the semiconductor chip 51a etc. Therefore, it is possible to ensure stable operation while making the semiconductor device 10a compact.

[0055] In this embodiment, when viewed in the thickness direction of the semiconductor chip 51a, the control circuit metal plate 15a and the control circuit metal plate 15b include an area that overlaps with the first metal plate 31a. Therefore, the first metal plate 31a can be enlarged while effectively utilizing the area where the control circuit metal plate 15a and the control circuit metal plate 15b are located in the thickness direction of the semiconductor chip 51a. This allows for more reliable compactness and improved heat dissipation.

[0056] In this embodiment, control circuit metal plate 15a and control circuit metal plate 15b include first terminals having portions exposed from first resin member 11a and first frames having portions covered by first resin member 11a. The first terminals and the first frames are integrally configured. Therefore, by holding the first frames, which are included in control circuit metal plate 15a and control circuit metal plate 15b and are integral with the first terminals, with second resin member 12a, the first terminals can be positioned at the same time, thereby improving assembly during manufacturing.

[0057] In this embodiment, the control circuit metal plate 15a and the control circuit metal plate 15b include a first terminal having a portion exposed from the first resin member 11a and a first frame having a portion covered by the first resin member 11a. The first terminal and the first frame are configured as separate bodies. Because the first terminal is held by the second resin member 12a, metal-joining the first frame allows the first frame to be fixed and electrically connected at the same time.

[0058] In this embodiment, the control circuit metal plate 15a and the control circuit metal plate 15b are disposed on the second resin member 12a. Therefore, the control circuit metal plate 15a and the control circuit metal plate 15b can be positioned and fixed by the second resin member 12a. This eliminates the need for manufacturing jigs, improving productivity. Furthermore, when ultrasonically bonding wires to the control circuit metal plate 15a and the control circuit metal plate 15b, the second resin member 12a functions as a base. Therefore, ultrasonic vibrations are efficiently applied, ensuring stable bonding. Furthermore, because the second resin member 12a is an insulator, it can be positioned while being reliably insulated from the first metal plate 31a, ensuring stable operation.

[0059] In this embodiment, the control circuit metal plate 15a and the control circuit metal plate 15b include a first terminal having a protruding portion protruding from the second resin member 12a and a retaining portion retained by the second resin member 12a, and a first frame covered by the first resin member 11a. The retaining portion includes a terminal exposed portion exposed from the second resin member 12a. The first frame is bonded to the first terminal in the region where the terminal exposed portion is located when viewed in the thickness direction of the semiconductor chip 51a, etc. This allows the metals of the first terminal and the first frame to overlap at the terminal exposed portion, enabling metal bonding such as fusion bonding (e.g., laser welding) or liquid-phase bonding (e.g., solder or brazing material), thereby achieving electrical connection simultaneously with fixation. This reduces bonding time and improves productivity.

[0060] In this embodiment, the semiconductor device 10a includes insert metals 25a and 25b held by the second resin member 12a and bonded to the first metal plate 31a and the control circuit metal plate 15a and 15b. The insert metals 25a and 25b include first exposed portions exposed from the second resin member 12a. The insert metals 25a and 25b are bonded to the control circuit metal plate 15a and 15b in the region where the first exposed portions are located when viewed in the thickness direction of the semiconductor chip 51a. This allows the insert metals 25a and 25b to overlap with the control circuit metal plate 15a and 15b in the first exposed portions, enabling metal bonding such as fusion bonding using laser welding or liquid-phase bonding using solder or brazing material to secure the second resin member 12a to the control circuit metal plate 15a and 15b. This reduces bonding time and improves productivity. Furthermore, in the first temperature characteristic detection terminal 21c and the second temperature characteristic detection terminal 22c, the control circuit metal plate 15a, the control circuit metal plate 15b, and the first metal plate 31a can be connected via the insert metal 25a, the insert metal 25b, and the first metal plate 31a, thereby improving thermal conduction between the control circuit metal plate 15a, the control circuit metal plate 15b, and the first metal plate 31a. Therefore, when the thermistor 24a is attached to the first temperature characteristic detection terminal 21c and the second temperature characteristic detection terminal 22c, the temperatures of the semiconductor chips 51a and 51e, such as transistor chips and diode chips, and the water-cooling temperature of the semiconductor device 10a can be monitored with higher accuracy.

[0061] In this embodiment, the insert metals 25a and 25b include second exposed portions exposed from the second resin member 12a. The insert metals 25a and 25b are bonded to the first metal plate 31a in the region where the second exposed portions are located when viewed in the thickness direction of the semiconductor chip 51a. This allows the insert metals 25a and 25b and the first metal plate 31a to overlap in the second exposed portions, enabling metal bonding such as fusion bonding using laser welding or liquid-phase bonding using solder or brazing material to secure the second resin member 12a and the first metal plate 31a. This reduces bonding time and improves productivity. Furthermore, the first temperature characteristic detection terminal 21c and the second temperature characteristic detection terminal 22c can perform highly accurate temperature monitoring using the thermistor 24a, as described above.

[0062] In this embodiment, the second resin member 12a is provided with engaging portions 28a and 28b that engage with the control circuit metal plates 15a and 15b. Therefore, the control circuit metal plates 15a and 15b can be positioned relative to the second resin member 12a using the engaging portions 28a and 28b. This eliminates the need for jigs to position the control circuit metal plates 15a and 15b, thereby improving productivity. While the engaging portions 28a and 28b are convex and position the control circuit metal plates 15a and 15b by placing them therebetween, they may also be concave and position the control circuit metal plates 15a and 15b by placing them therein.

[0063] In this embodiment, the melting point of the second resin member 12a is higher than that of the first resin member 11a. Therefore, when the molten first resin member 11a is poured into the mold after the second resin member 12a is placed, the risk of the second resin member 12a melting can be reduced. This allows for stable production. In this embodiment, the second resin member 12a is a thermoplastic resin and the first resin member 11a is a thermosetting resin. However, this is not limited to this. Both resins may be thermoplastic resins as long as they have different melting points (i.e., the melting point of the second resin member 12a is higher than that of the first resin member 11a). Furthermore, if a thermosetting resin is used for the second resin member 12a and is heat-cured once, it will not melt when the thermosetting resin for the first resin member 11a is poured in. Therefore, both resins may be thermosetting resins.

[0064] In this embodiment, the second metal plate 32a has slits 34a and 34b formed at intervals from the outer edge 35a of the second metal plate 32a. Therefore, when joining the second metal plate 32a to the heat sink, the distance from end to end can be shortened because the second metal plate 32a is divided by the slits 34a and 34b. This reduces stress on the end due to differences in linear expansion coefficients during temperature changes. In this case, the bonding material joining the second metal plate 32a to the heat sink is positioned inside the end faces of the slits 34a and 34b. Furthermore, because the slits 34a and 34b are formed at intervals from the outer edge 35a of the second metal plate 32a, the outer periphery of the second metal plate 32a is pressed by a mold during resin molding, reducing the risk of resin entering the slits 34a and 34b. This more reliably reduces stress at the joint.

[0065] In this embodiment, the first resin member 11a is formed with a rib 17a disposed between the P terminal 14a and the N terminal 14b. The P terminal 14a and the N terminal 14b are provided with notches 36a and 36b to accommodate the rib 17a. This allows the P terminal 14a and the N terminal 14b to be positioned close to each other while increasing the creepage distance between them. This reduces inductance while minimizing the size of the semiconductor device 10a. Furthermore, the provision of the notches 36a and 36b to accommodate the rib 17a allows the fillets 18a and 18b to be large without increasing the distance between the P terminal 14a and the N terminal 14b, thereby reinforcing the strength of the rib 17a while suppressing an increase in parasitic inductance.

[0066] (Modification) In the above embodiment, a solder resist may be provided on a portion of the control circuit metal plate. FIG. 14 is a schematic plan view showing an enlarged view of a portion of a semiconductor device in which a solder resist is provided on the control circuit metal plate. Referring to FIG. 14, solder resist 39a and solder resist 39b are provided on a portion of control circuit metal plate 15b. Solder resist 39a is formed so as to surround the area where resistor 23c is to be mounted. Solder resist 39b is formed so as to surround the area where thermistor 24a is to be mounted. By doing so, when joining electronic components such as resistor 23c and thermistor 24a to control circuit metal plate 15b, solder resist 39a and solder resist 39b can prevent the flow of bonding material when joining the electronic components, thereby ensuring reliable positioning and electrical connection of the electronic components.

[0067] (Embodiment 2) Another embodiment, embodiment 2, will now be described. FIG. 15 is a schematic perspective view showing a state in which the first resin member has been removed from a semiconductor device according to embodiment 2 of the present disclosure. FIG. 16 is a schematic plan view of the semiconductor device shown in FIG. 15. FIG. 17 is a schematic bottom view of the semiconductor device shown in FIG. 15. The semiconductor device according to embodiment 2 basically has the same configuration as embodiment 1 and achieves the same effects. However, the semiconductor device according to embodiment 2 differs from embodiment 1 in that a lead frame is used instead of a DBC substrate, the shape of the second resin member is different, and so on.

[0068] 15, 16, and 17, semiconductor device 10b according to the second embodiment includes a first resin member (not shown), a second resin member 12b, a lead frame 13b serving as first metal plate 31a, and control circuit metal plates 15a and 15b. That is, in the second embodiment, first metal plate 31b is formed from lead frame 13b. Semiconductor device 10b includes P terminal 14a, N terminal 14b, O terminal 14c, and first metal plate 31b formed by bending a metal plate having a predetermined shape that constitutes lead frame 13b. Like first metal plate 31a according to the first embodiment, first metal plate 31b includes first region 41b, second region 42b, third region 43b, fourth region 44b, fifth region 45b, sixth region 46b, seventh region 47b, eighth region 48b, and ninth region 49b. The first region 41b and the P terminal 14a are formed by bending a single metal plate, the second region 42b and the O terminal 14c are formed by bending a single metal plate, and the third region 43b and the N terminal 14b are formed by bending a single metal plate. Semiconductor chips 51a and 51b serving as transistor chips, and semiconductor chips 51e and 51f serving as diode chips, are bonded and electrically connected to the first region 41b. Semiconductor chips 51c and 51d serving as transistor chips, and semiconductor chips 51g and 51h serving as diode chips are bonded and electrically connected to the second region 42b. The electrical connections of the components via wires 56a, 56b, 56c, 56d, 57a, 57b, 57c, 57d, 58a, 58b, 58c, and 58d are also similar to those in the first embodiment. The P terminal 14a, the N terminal 14b, and the O terminal 14c are formed integrally with the first metal plate 31b, but may be provided as separate bodies, similar to the case of the semiconductor device 10a in the first embodiment.

[0069] In the lead frame 13b, the metal plates constituting the first region 41b and the P terminal 14a, the metal plates constituting the second region 42b and the O terminal 14c, the metal plates constituting the third region 43b and the N terminal 14b, the first gate terminal 21a, and the first auxiliary source terminal 21b are attached to the second resin member 12b. In this embodiment, the second resin member 12b is manufactured to hold the metal plates constituting the first region 41b and the N terminal 14b, the metal plates constituting the second region 42b and the O terminal 14c, the metal plates constituting the third region 43b and the P terminal 14a, the first gate terminal 21a, and the first auxiliary source terminal 21b. That is, the second resin member 12b is fixed by partially molding the lead frame 13b, such as by hoop molding. The P terminal 14a, the N terminal 14b, and the O terminal 14c are fixed by molding their peripheries with the second resin member 12b. The second resin member 12b is fixed integrally with the first metal plate 31b by partial molding, but may be provided as a separate member as in the case of the semiconductor device 10a in the first embodiment.

[0070] Grooves 63b and 64b are formed on the surface of the first metal plate 31b opposite the surface on which the semiconductor chip 51a and other components are disposed. The grooves 63b and 64b are formed as a pair, extending in the X direction and spaced apart in the Y direction. The grooves 63b and 64b are each spaced apart from the outer edge 35b of the first metal plate 31b. The grooves 63b and 64b are each provided in a manner that avoids the areas where the semiconductor chips 51a, 51b, 51c, 51d, 51e, 51f, 51g, and 51h are disposed, as viewed in the thickness direction. The grooves 63b and 64b are each recessed in the thickness direction of the first metal plate 31b. In other words, the surface on which the semiconductor chips 51a and other components are disposed is elevated in the areas where the grooves 63b and 64b are located. The recessed grooves 63b and 64b of the semiconductor device 10b have the same effect as the slits 34a and 34b of the semiconductor device 10a of the first embodiment.

[0071] 18 is a schematic bottom view showing an enlarged view of a portion of the interior of the semiconductor device shown in FIG. 15 . Also referring to FIG. 18 , the first metal plate 31b includes a connection portion 65b extending in the thickness direction (Z direction) of the semiconductor chip 51a, etc. The first metal plate 31b is joined to the control circuit metal plate 15a at the connection portion 65b. Specifically, the connection portion 65b, which is formed continuous with the first region 41b of the first metal plate 31b, is joined to the electrical characteristic detection terminal 21d of the control circuit metal plate 15a. A connection portion (not shown) provided in another location on the first metal plate 31b is joined to the control circuit metal plate 15a.

[0072] In the semiconductor device 10b of the second embodiment, the first metal plate 31b is the lead frame 13b, so there is no need to provide an insulating layer, which allows for a reduction in the number of components and a simpler configuration.

[0073] In this embodiment, the first metal plate 31b includes the connection portion 65b, and therefore can be joined to the control circuit metal plate 15a using the connection portion 65b provided on the first metal plate 31b, which is the lead frame 13b. This allows for a further reduction in the number of parts, thereby improving productivity.

[0074] In this embodiment, the grooves 63b and 64b are formed. The grooves 63b and 64b divide the first metal plate 31b and the heat sink, shortening the distance from one end to the other. This reduces stress on the end due to differences in the linear expansion coefficient during temperature changes. In this case, the bonding material bonding the lead frame 13b and the heat sink is positioned inside the end faces of the grooves 63b and 64b. Furthermore, the grooves 63b and 64b are spaced apart from the outer edge 35b of the first metal plate 31b. This reduces the risk of resin entering the grooves 63b and 64b during resin molding, as the outer periphery of the lead frame 13b is pressed by a mold. This reduces the risk of resin entering the grooves 63b and 64b. This more reliably reduces stress at the joint.

[0075] Third Embodiment Another embodiment, the third embodiment, will now be described. Fig. 19 is a schematic perspective view showing a semiconductor device according to the third embodiment of the present disclosure. The semiconductor device according to the third embodiment basically has the same configuration as the first embodiment, and achieves the same effects. However, the semiconductor device according to the third embodiment differs from the first embodiment in that a potting resin is used instead of the first resin member constituting the mold resin.

[0076] 19 , a semiconductor device 10c according to the third embodiment includes a potting resin 11c, a second resin member 12c, a DBC substrate 13a, a P terminal 14a, an N terminal 14b, an O terminal 14c, a control circuit metal plate 15a, and a control circuit metal plate 15b. The potting resin 11c is disposed on the DBC substrate 13a inside the frame-shaped second resin member 12c, and seals a semiconductor chip 51a disposed on the DBC substrate 13a. In this embodiment, a rib 17a is formed on the second resin member 12c. The potting resin is made of a thermosetting resin such as silicone gel or epoxy resin.

[0077] The semiconductor device 10c having such a configuration can also ensure stable operation while achieving compactness.

[0078] Other Embodiments In the above embodiment, the electronic components include resistors and thermistors, but the present invention is not limited to this and may include capacitors, diodes, and coils as electronic components.

[0079] In the above embodiment, the transistor chip is a MOSFET, but may be an IGBT (Insulated Gate Bipolar Transistor). The diode chip is an SBD, but may be an FWD (Free Wheeling Diode). Note that a configuration without a diode chip is also possible.

[0080] The transistor chip and the diode chip are bonded to the first metal plate by a bonding material (not shown) such as solder or a sintered material such as Ag (silver) or Cu (copper).

[0081] The conductive members electrically connected to the transistor chip and the diode chip may be electrically connected using copper clips instead of wires.

[0082] It should be understood that the embodiments disclosed herein are illustrative in all respects and are not limiting in any respect. The scope of the present invention is defined not by the above description but by the claims, and it is intended to include all modifications within the meaning and scope of the claims.

[0083] (Preferred Aspects of the Present Disclosure) Preferred aspects of the present disclosure will be additionally described below.

[0084] (Supplementary Note 1) A semiconductor device comprising: an insulating layer; a first metal plate disposed on the insulating layer and having conductivity; a semiconductor chip disposed on the first metal plate and electrically connected to the first metal plate; a first terminal electrically connected to the first metal plate; a second metal plate electrically connected to the semiconductor chip via a conductive member; a second terminal electrically connected to the second metal plate; a first resin member fixed to at least one of the insulating layer, the first metal plate, and the second metal plate; and a second resin member disposed so as to seal the semiconductor chip and cover the first metal plate, wherein the melting point of the first resin member is higher than the melting point of the second resin member.

[0085] (Supplementary Note 2) A semiconductor device comprising: a first metal plate having conductivity; a semiconductor chip arranged on the first metal plate and electrically connected to the first metal plate; a first terminal electrically connected to the first metal plate; a second metal plate electrically connected to the semiconductor chip via a conductive member; a second terminal electrically connected to the second metal plate; a first resin member fixed to at least one of the first metal plate and the second metal plate; and a second resin member arranged to seal the semiconductor chip and cover the first metal plate, wherein at least a portion of a surface of the first metal plate opposite to a surface on which the semiconductor chip is arranged is exposed from the second resin member, and the melting point of the first resin member is higher than the melting point of the second resin member.

[0086] (Appendix 3) A semiconductor device comprising: an insulating layer; a first metal plate disposed on the insulating layer and having electrical conductivity; a second metal plate disposed on the surface of the insulating layer opposite the first metal plate; a semiconductor chip disposed on the first metal plate and electrically connected to the first metal plate; and a second resin member disposed so as to cover the first metal plate and seal the semiconductor chip, wherein at least a portion of a surface of the second metal plate is exposed from the second resin member, and a slit is formed in the second metal plate at a distance from an outer edge of the second metal plate.

[0087] (Appendix 4) A semiconductor device comprising: a first metal plate having electrical conductivity; a semiconductor chip arranged on the first metal plate and electrically connected to the first metal plate; and a second resin member arranged to cover the first metal plate and seal the semiconductor chip, wherein at least a portion of a surface of the first metal plate opposite to a surface on which the semiconductor chip is arranged is exposed from the second resin member, and a recessed groove is formed on the surface of the first metal plate opposite to the surface on which the semiconductor chip is arranged, with a gap between it and the outer edge of the first metal plate.

[0088] (Supplementary Note 5) A semiconductor device comprising: a first metal plate having conductivity; a semiconductor chip arranged on the first metal plate and electrically connected to the first metal plate; a control circuit metal plate arranged at a position different from the first metal plate in a thickness direction of the semiconductor chip, having conductivity, and constituting a control circuit for controlling the semiconductor device; a first resin member encapsulating the semiconductor chip; a first terminal electrically connected to the first metal plate; a second metal plate electrically connected to the semiconductor chip via a conductive member; and a second terminal electrically connected to the second metal plate, wherein the control circuit includes a gate circuit, an auxiliary source circuit, a temperature characteristic detection circuit, and an electrical characteristic detection circuit, and the control circuit metal plate includes a gate terminal that constitutes a part of the gate circuit, an auxiliary source terminal that constitutes a part of the auxiliary source circuit, a temperature characteristic detection terminal that constitutes a part of the temperature characteristic detection circuit, and an electrical characteristic detection terminal that constitutes a part of the electrical characteristic detection circuit, each of which is exposed from the first resin member; a semiconductor device in which a rib is formed in the first resin member and is arranged between any two adjacent terminals of the first terminal, the second terminal, the gate terminal, the auxiliary source terminal, the temperature characteristic detection terminal, and the electrical characteristic detection terminal, and at least one of the first terminal, the second terminal, the gate terminal, the auxiliary source terminal, the temperature characteristic detection terminal, and the electrical characteristic detection terminal that are arranged between the rib has a notch that receives the rib.

[0089] a control circuit metal plate that is disposed at a position different from the first metal plate in a thickness direction of the semiconductor chip, that is conductive, and that constitutes a control circuit for controlling the semiconductor device; a first terminal that is electrically connected to the first metal plate; a second metal plate that is electrically connected to the semiconductor chip via a conductive member; a second terminal that is electrically connected to the second metal plate; and a second resin member that supports the first terminal and the second terminal, wherein the control circuit includes a gate circuit, an auxiliary source circuit, a temperature characteristic detection circuit, and an electrical characteristic detection circuit, and the control circuit metal plate includes a gate terminal that constitutes a part of the gate circuit, an auxiliary source terminal that constitutes a part of the auxiliary source circuit, a temperature characteristic detection terminal that constitutes a part of the temperature characteristic detection circuit, and an electrical characteristic detection terminal that constitutes a part of the electrical characteristic detection circuit, and the first terminal and the second terminal are each any one of a P terminal, an N terminal, and an O terminal, a semiconductor device in which a rib is formed on the second resin member and is arranged between any two adjacent terminals of the first terminal, the second terminal, the gate terminal, the auxiliary source terminal, the temperature characteristic detection terminal, and the electrical characteristic detection terminal, and at least one of the first terminal, the second terminal, the gate terminal, the auxiliary source terminal, the temperature characteristic detection terminal, and the electrical characteristic detection terminal that are arranged between the rib has a notch that receives the rib.

[0090] DESCRIPTION OF SYMBOLS 10a, 10b, 10c Semiconductor device, 11a First resin member, 11c Potting resin member, 12a, 12b, 12c Second resin member, 13a DBC substrate, 13b Lead frame, 14a P terminal, 14b N terminal, 14c O terminal, 15a, 15b Control circuit metal plate, 16a, 16b, 16c Round hole, 17a Rib, 18a, 18b Fillet, 19a, 19b, 19c, 19d Through hole, 21a First gate terminal, 21b First auxiliary source terminal, 21c First temperature characteristic detection terminal, 21d Electrical characteristic detection terminal, 22a Second gate terminal, 22b Second auxiliary source terminal, 22c Second temperature characteristic detection terminal, 23a, 23b, 23c, 23d Resistor, 24a Thermistor, 25a, 25b Insert metal, 26a; First terminal, 27a; First frame, 27b; Exposed frame portion, 28a, 28b, 29a, 29b, 29c; Engagement portion, 31a, 31b; First metal plate, 32a; Second metal plate, 33a; Insulation layer, 34a, 34b; Slit, 35a, 35b; Outer edge, 36a, 36b; Notch, 37a, 37b; Snap-fitting portion, 38a, 38b; Bonding material, 39a, 39b; Solder resist, 41a, 41b; First region, 42a, 42b; Second region, 43a, 43b; Third region, 44a, 44b; Fourth region, 45a, 45b; Fifth region, 46a, 46b; Sixth region, 47a, 47b; Seventh region, 48a, 48b; Eighth region, 49a, 49b Ninth region, 51a, 51b, 51c, 51d, 51e, 51f, 51g, 51h: semiconductor chip, 52a: drain electrode, 52b: cathode electrode, 53a, 53b, 53c, 53d: source electrodes, 54a, 54b, 54c, 54d: anode electrodes, 56a, 56b, 56c, 56d, 57a, 57b, 57c, 57d, 58a, 58b, 58c, 58d: wires, 61a: first exposed portion, 62a: second exposed portion, 63b, 64b: grooves, 65b: connection portion.

Claims

1. A semiconductor device, a first metal plate having electrical conductivity; a semiconductor chip disposed on the first metal plate and electrically connected to the first metal plate; a control circuit metal plate that is disposed at a position different from the first metal plate in a thickness direction of the semiconductor chip, has conductivity, and constitutes a control circuit that controls the semiconductor device; The control circuit includes at least one of a gate circuit, an auxiliary source circuit, a temperature characteristic detection circuit, and an electrical characteristic detection circuit.

2. The semiconductor device according to claim 1 , wherein the control circuit metal plate includes an area overlapping with the first metal plate when viewed in a thickness direction of the semiconductor chip.

3. a first resin member that seals the semiconductor chip; The control circuit metal plate is a first terminal having a portion exposed from the first resin member; a first frame having a portion covered by the first resin member, 3. The semiconductor device according to claim 1, wherein the first terminal and the first frame are integrally formed.

4. a first resin member that seals the semiconductor chip; The control circuit metal plate is a first terminal having a portion exposed from the first resin member; a first frame having a portion covered by the first resin member, the first terminal and the first frame are configured as separate bodies, 3. The semiconductor device according to claim 1, wherein the first terminal is held by the first resin member.

5. a first resin member that seals the semiconductor chip; a second resin member provided separately from the first resin member; 3. The semiconductor device according to claim 1, wherein the control circuit metal plate is disposed on the second resin member.

6. a first resin member that seals the semiconductor chip; a second resin member provided separately from the first resin member, The control circuit metal plate is a first terminal having a protruding portion protruding from the second resin member and a retaining portion retained by the second resin member; a first frame having a portion covered by the first resin member, the holding portion includes a terminal exposed portion exposed from the second resin member, 3. The semiconductor device according to claim 1, wherein the first frame is joined to the first terminal in a region where the terminal exposed portion is located when viewed in a thickness direction of the semiconductor chip.

7. a first resin member that seals the semiconductor chip; a second resin member provided separately from the first resin member; an insert metal that is held by the second resin member and joined to the control circuit metal plate, the insert metal includes a first exposed portion exposed from the second resin member, 3. The semiconductor device according to claim 1, wherein the insert metal is joined to the control circuit metal plate in a region where the first exposed portion is located when viewed in a thickness direction of the semiconductor chip.

8. a first resin member that seals the semiconductor chip; a second resin member provided separately from the first resin member; an insert metal held by the second resin member and joined to the first metal plate, the insert metal includes a second exposed portion exposed from the second resin member, 3 . The semiconductor device according to claim 1 , wherein the insert metal is joined to the first metal plate in a region where the second exposed portion is located when viewed in a thickness direction of the semiconductor chip.

9. 3. The semiconductor device according to claim 1, wherein a solder resist is provided on a portion of said control circuit metal plate.

10. 3. The semiconductor device according to claim 1, further comprising an electronic component electrically connected to said control circuit metal plate.

11. a first resin member that seals the semiconductor chip; a second resin member provided separately from the first resin member, 3. The semiconductor device according to claim 1, wherein the second resin member is provided with an engaging portion that engages with the control circuit metal plate.

12. 3. The semiconductor device according to claim 1, wherein the first metal plate is a lead frame or an electrode on a substrate having an insulating layer on a surface opposite to a surface on which the semiconductor chip is placed in the thickness direction of the semiconductor chip.

13. a first resin member that seals the semiconductor chip; a second resin member provided separately from the first resin member, the first metal plate is a lead frame, the first metal plate includes a connection portion extending in a thickness direction of the semiconductor chip, The semiconductor device according to claim 1 , wherein the first metal plate is joined to the control circuit metal plate at the connection portion.

14. a first resin member that seals the semiconductor chip; a second resin member provided separately from the first resin member; an insulating layer disposed on a surface of the first metal plate opposite to a surface on which the semiconductor chip is disposed in a thickness direction of the semiconductor chip, the control circuit metal plate is disposed on the second resin member, the second resin member is disposed on the first metal plate or the insulating layer, 3. The semiconductor device according to claim 1, wherein the second resin member has a melting point higher than the melting point of the first resin member.

15. an insulating layer disposed on a surface of the first metal plate opposite to a surface on which the semiconductor chip is disposed in a thickness direction of the first metal plate; a second metal plate disposed on the insulating layer on the opposite side of the first metal plate in the thickness direction of the semiconductor chip, 3. The semiconductor device according to claim 1, wherein a slit is formed in said second metal plate at a distance from an outer edge of said second metal plate.

16. the first metal plate is a lead frame, 3. The semiconductor device according to claim 1, wherein a recessed groove is formed on a surface of said first metal plate opposite to a surface on which said semiconductor chip is arranged, said recessed groove being spaced apart from an outer edge of said first metal plate.

17. a first resin member that seals the semiconductor chip; A first terminal; a second terminal different from the first terminal, the first terminal and the second terminal are each one of a P terminal, an N terminal, an O terminal, a gate terminal, an auxiliary source terminal, a temperature characteristic detection terminal, and an electrical characteristic detection terminal; the first resin member has a rib formed thereon and disposed between the first terminal and the second terminal; 3. The semiconductor device according to claim 1, wherein at least one of the first terminal and the second terminal is provided with a notch for receiving the rib.