Semiconductor device and method for manufacturing same

Abstract

A semiconductor device comprises: a chip that has a main surface; a plurality of planar gate structures each including a gate insulating film that covers the main surface, a gate electrode that is disposed on the gate insulating film, and a side wall insulating film that covers a side wall of the gate electrode, said gate structures being disposed on the main surface at intervals; an opening that is defined by the plurality of side wall insulating films in a region between the plurality of gate structures; and a main electrode that is mechanically connected to the plurality of side wall insulating films in the opening and electrically connected to the main surface.

Description

Semiconductor device and manufacturing method thereof

[0001] This application claims priority to Patent Application No. 2023-089176 filed with the Japan Patent Office on May 30, 2023, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device and a manufacturing method thereof.

[0002] Patent Document 1 (US2022 / 0093491A1) discloses a semiconductor device having a plurality of planar gate structures.

[0003] US Patent Application Publication No. 2022 / 0093491

[0004] [Summary] The present disclosure provides a semiconductor device capable of improving electrical characteristics and a method for manufacturing the same.

[0005] The present disclosure provides a semiconductor device including: a chip having a main surface; a plurality of planar gate structures each including a gate insulating film covering the main surface, a gate electrode disposed on the gate insulating film, and a sidewall insulating film covering a sidewall of the gate electrode, and arranged at intervals on the main surface; openings partitioned by the plurality of sidewall insulating films in regions between the plurality of gate structures and exposing the main surface; and a main electrode mechanically connected to the plurality of sidewall insulating films within the opening and electrically connected to the main surface within the opening.

[0006] the base insulating film covering the plurality of gate electrodes; selectively removing the base insulating film so as to leave covering portions of the base insulating film on side walls of the plurality of gate electrodes, and forming a plurality of sidewall insulating films covering the side walls of the plurality of gate electrodes, the base insulating film being selectively removed so as to leave covering portions of the base insulating film on side walls of the plurality of gate electrodes, and forming a plurality of sidewall insulating films covering the side walls of the plurality of gate electrodes, the base insulating film being selectively removed so as to leave covering portions of the lower insulating film covered by the plurality of gate electrodes as a plurality of gate insulating films, and forming an opening exposing the main surface; and forming a main electrode on the main surface so as to be mechanically connected to the plurality of sidewall insulating films in the opening and electrically connected to the main surface in the opening.

[0007] The above and other objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0008] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing a layout example of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of the first main surface. FIG. 5 is an enlarged plan view showing further main portions of the first main surface. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5. FIG. 7 is an enlarged cross-sectional view showing the main portion of FIG. 6 together with a gate structure according to a first example. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5. FIG. 9 is an enlarged cross-sectional view showing the main portion of FIG. 8 together with the wiring structure according to the first example. FIG. 10A is an enlarged cross-sectional view showing a gate structure according to a second example. FIG. 10B is an enlarged cross-sectional view showing a gate structure according to a third example. FIG. 10C is an enlarged cross-sectional view showing a gate structure according to a fourth example. FIG. 10D is an enlarged cross-sectional view showing a gate structure according to a fifth example. FIG. 10E is an enlarged cross-sectional view showing a gate structure according to a sixth example. FIG. 10F is an enlarged cross-sectional view showing a gate structure according to a seventh example. FIG. 10G is an enlarged cross-sectional view showing a gate structure according to an eighth example. FIG. 10H is an enlarged cross-sectional view showing a gate structure according to a ninth example. FIG. 10I is an enlarged cross-sectional view showing a gate structure according to a tenth example. FIG. 10J is an enlarged cross-sectional view showing a gate structure according to an eleventh example. FIG. 11A is an enlarged cross-sectional view showing an interconnect structure according to a second example. FIG. 11B is an enlarged cross-sectional view showing an interconnect structure according to a third example. FIG. 11C is an enlarged cross-sectional view showing an interconnect structure according to a fourth example. FIG. 11D is an enlarged cross-sectional view showing an interconnect structure according to a fifth example. FIG. 11E is an enlarged cross-sectional view showing an interconnect structure according to a sixth example. FIG. 11F is an enlarged cross-sectional view showing an interconnect structure according to a seventh example. FIG. 11G is an enlarged cross-sectional view showing an interconnect structure according to an eighth example. FIG. 11H is an enlarged cross-sectional view showing an interconnect structure according to a ninth example. FIG. 11I is an enlarged cross-sectional view showing an interconnect structure according to a tenth example. FIG. 12 is a schematic diagram showing a wafer used in manufacturing a semiconductor device. FIG. 13A is a cross-sectional view showing a method for manufacturing a semiconductor device. Fig. 13B is a cross-sectional view showing a step after Fig. 13A. Fig. 13C is a cross-sectional view showing a step after Fig. 13B. Fig. 13D is a cross-sectional view showing a step after Fig. 13C. Fig. 13E is a cross-sectional view showing a step after Fig. 13D. Fig. 13F is a cross-sectional view showing a step after Fig. 13E. Fig. 13G is a cross-sectional view showing a step after Fig. 13F.13H is a cross-sectional view showing a step after FIG. 13G. FIG. 13I is a cross-sectional view showing a step after FIG. 13H. FIG. 13J is a cross-sectional view showing a step after FIG. 13I. FIG. 13K is a cross-sectional view showing a step after FIG. 13J. FIG. 13L is a cross-sectional view showing a step after FIG. 13K. FIG. 13M is a cross-sectional view showing a step after FIG. 13L. FIG. 13N is a cross-sectional view showing a step after FIG. 13M. FIG. 13O is a cross-sectional view showing a step after FIG. 13N. FIG. 13P is a cross-sectional view showing a step after FIG. 13O. FIG. 13Q is a cross-sectional view showing a step after FIG. 13P. FIG. 13R is a cross-sectional view showing a step after FIG. 13Q. FIG. 14 is an enlarged cross-sectional view showing a gate structure of a semiconductor device according to the second embodiment. FIG. 15 is an enlarged cross-sectional view showing an interconnect structure of the semiconductor device shown in FIG. 14. FIG. 16A is a cross-sectional view showing a manufacturing method of the semiconductor device shown in FIG. 14. FIG. 16B is a cross-sectional view showing a step after FIG. 16A. Fig. 16C is a cross-sectional view showing a step after Fig. 16B. Fig. 17 is a cross-sectional view showing a semiconductor device according to a third embodiment. Fig. 18 is a cross-sectional view showing a first modified example of a source main electrode. Fig. 19 is a cross-sectional view showing a second modified example of a source main electrode.

[0009] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a first main surface 3. Fig. 4 is an enlarged plan view showing a main portion of the first main surface 3. Fig. 5 is an enlarged plan view showing a further main portion of the first main surface 3.

[0013] Fig. 6 is a cross-sectional view taken along line VI-VI shown in Fig. 5. Fig. 7 is an enlarged cross-sectional view showing the main part of Fig. 6 together with a gate structure 20 according to a first example. Fig. 8 is a cross-sectional view taken along line VIII-VIII shown in Fig. 5. Fig. 9 is an enlarged cross-sectional view showing the main part of Fig. 8 together with a wiring structure 50 according to a first example.

[0014] 1 to 9, semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical type structure. Semiconductor device 1A is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip."

[0015] In this embodiment, the chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of another polytype.

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0018] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0019] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0020] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off-axis direction by the off-axis angle. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off-axis angle.

[0021] The off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0022] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0023] In this embodiment, the chip 2 has a stacked structure including a first semiconductor layer 6 and a second semiconductor layer 7. The first semiconductor layer 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal) and has the off direction and off angle described above. The first semiconductor layer 6 forms the second main surface 4 and forms parts of the first to fourth side surfaces 5A to 5D.

[0024] The first semiconductor layer 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or more, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0025] The second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and is stacked on the first semiconductor layer 6. The second semiconductor layer 7 has the off direction and off angle described above. The second semiconductor layer 7 forms the first main surface 3 and forms parts of the first to fourth side surfaces 5A to 5D. The second semiconductor layer 7 preferably has a thickness less than that of the first semiconductor layer 6. The thickness of the second semiconductor layer 7 may be greater than that of the first semiconductor layer 6.

[0026] The thickness of the second semiconductor layer 7 may be 5 μm or more and 50 μm or less. The thickness of the second semiconductor layer 7 may have a value belonging to at least one of the ranges of 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or more and 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or more, and 45 μm or more and 50 μm or less.

[0027] The semiconductor device 1A includes an active region 8 set in an inner portion of the chip 2 (first main surface 3). The active region 8 includes a transistor structure Tr (device structure) and is a region where an output current (drain current) is generated.

[0028] The active region 8 is set in the interior of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in plan view. The active region 8 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view. The plane area of ​​the active region 8 is preferably 50% to 90% of the plane area of ​​the first main surface 3.

[0029] The semiconductor device 1A includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include a device structure (transistor structure Tr). The peripheral region 9 is set in the peripheral portion of the chip 2 (first main surface 3). That is, the peripheral region 9 is provided in the region between the periphery of the chip 2 and the active region 8 in a planar view. The peripheral region 9 extends in a strip shape along the active region 8 in a planar view, and is set in the shape of a polygonal ring (a square ring in this embodiment) that surrounds the active region 8.

[0030] The semiconductor device 1A includes an n-type first semiconductor region 10 formed in a surface layer portion of the second main surface 4 in the active region 8. A drain potential is applied to the first semiconductor region 10 as a first potential (high potential). The first semiconductor region 10 may also be referred to as a "drain region," a "first region," or the like.

[0031] The first semiconductor region 10 extends in a layer shape along the second main surface 4. The first semiconductor region 10 is formed over the entire area of ​​the active region 8. The first semiconductor region 10 is drawn out from the active region 8 to the peripheral region 9, and has a portion in the peripheral region 9 that is located in a surface layer portion of the second main surface 4. The first semiconductor region 10 is drawn out from the active region 8 to the peripheral region 9 over the entire periphery. The first semiconductor region 10 is exposed from at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 10 is exposed from the entire periphery of the first to fourth side surfaces 5A to 5D.

[0032] The first semiconductor region 10 is formed in the first semiconductor layer 6. The first semiconductor region 10 is formed throughout the thickness range between the lower end (second major surface 4) of the first semiconductor layer 6 and the upper end (second semiconductor layer 7) of the first semiconductor layer 6, and is connected to the second semiconductor layer 7. The first semiconductor region 10 is formed using the n-type first semiconductor layer 6, and has a thickness corresponding to the thickness of the first semiconductor layer 6. The first semiconductor region 10 may be formed by introducing n-type impurities into a surface layer portion of the second major surface 4.

[0033] The semiconductor device 1A includes an n-type second semiconductor region 11 formed in the active region 8 in a surface layer portion of the first main surface 3. The second semiconductor region 11 may also be referred to as a "drift region" or a "second region," etc. The second semiconductor region 11 has an impurity concentration lower than the impurity concentration of the first semiconductor region 10.

[0034] The second semiconductor region 11 extends in a layer shape along the first main surface 3 and is electrically connected to the first semiconductor region 10 inside the chip 2. The second semiconductor region 11 is formed over the entire active region 8. In this embodiment, the second semiconductor region 11 extends from the active region 8 to the peripheral region 9, and has a portion in the peripheral region 9 that is located in a surface layer portion of the first main surface 3.

[0035] The second semiconductor region 11 is drawn out from the active region 8 to the peripheral region 9 along the entire periphery. The second semiconductor region 11 is preferably exposed from at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 11 is exposed from the entire periphery of the first to fourth side surfaces 5A to 5D.

[0036] The second semiconductor region 11 is formed in the second semiconductor layer 7. The second semiconductor region 11 is formed throughout the thickness range between the upper end (first semiconductor region 10) of the first semiconductor layer 6 and the upper end (first major surface 3) of the second semiconductor layer 7, and is connected to the first semiconductor layer 6 (first semiconductor region 10). In this embodiment, the second semiconductor region 11 is formed using the n-type second semiconductor layer 7, and has a thickness corresponding to the thickness of the second semiconductor layer 7. The second semiconductor region 11 may be formed by introducing n-type impurities into a surface layer portion of the first major surface 3.

[0037] The semiconductor device 1A includes a plurality of p-type body regions 12 formed at intervals in a surface layer portion of the first main surface 3 in the active region 8. The plurality of body regions 12 are each formed in a surface layer portion of a second semiconductor region 11. The plurality of body regions 12 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 11. A source potential is applied to the body regions 12 as a second potential (low potential) different from a first potential (high potential).

[0038] The body regions 12 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the body regions 12 are arranged in stripes extending in the second direction Y. The extending direction of the body regions 12 also coincides with the off-direction of the SiC single crystal.

[0039] The plurality of body regions 12 are formed at intervals from the bottom of the second semiconductor region 11 toward the first main surface 3, and face the first semiconductor region 10 across a part of the second semiconductor region 11. The plurality of body regions 12 are preferably formed at intervals from the middle of the second semiconductor region 11 toward the first main surface 3.

[0040] The plurality of body regions 12 may traverse in the thickness direction a depth position of an intermediate portion of the second semiconductor region 11. The plurality of body regions 12 are exposed from the first main surface 3. The plurality of body regions 12 form pn junctions (pn junction diodes: body diodes) with the second semiconductor region 11, respectively, and expand a depletion layer into the second semiconductor region 11 when a reverse bias voltage is applied.

[0041] Each of the body regions 12 may have a width of 1 μm to 10 μm. The width of the body region 12 may be a value belonging to at least one of the following ranges: 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, 4 μm to 5 μm, 5 μm to 6 μm, 6 μm to 7 μm, 7 μm to 8 μm, 8 μm to 9 μm, and 9 μm to 10 μm. The width of the body region 12 is preferably 1.5 μm to 2.5 μm.

[0042] Each of the body regions 12 may have a thickness (depth) of 0.1 μm to 2.5 μm. The thickness of the body region 12 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, and 2 μm to 2.5 μm. The thickness of the body region 12 is preferably 0.5 μm to 1.5 μm.

[0043] The semiconductor device 1A includes a plurality of n-type surface drift regions 13 formed in a surface portion of the first main surface 3. In this embodiment, the plurality of surface drift regions 13 are each made of a part of the second semiconductor region 11. The plurality of surface drift regions 13 may have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 11, or may have an n-type impurity concentration lower than the n-type impurity concentration of the second semiconductor region 11.

[0044] The surface drift regions 13 are each partitioned into regions between the body regions 12 adjacent in the first direction X in the surface layer portion of the second semiconductor region 11. That is, the surface drift regions 13 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. The surface drift regions 13 are also formed in a stripe shape extending in the second direction Y. The surface drift region 13 forms a pnp-type JFET structure together with the body regions 12 located on both sides.

[0045] The width of the surface drift region 13 is preferably smaller than the width of the body region 12. The width of the surface drift region 13 may be larger than the width of the body region 12. The surface drift region 13 has a width of 0.1 μm or more and 5 μm or less in the horizontal direction (first direction X in this embodiment).

[0046] The width of the surface drift region 13 may be in at least one of the following ranges: 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The width of the surface drift region 13 is preferably 0.5 μm to 2 μm.

[0047] The semiconductor device 1A includes a plurality of n-type source regions 14, 15 formed in the surface layer portions of the plurality of body regions 12. The plurality of source regions 14, 15 have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 11. A source potential is applied to the plurality of source regions 14, 15.

[0048] The plurality of source regions 14, 15 include a first source region 14 located on one side (third side surface 5C side) in the first direction X in a surface layer portion of each body region 12 and a second source region 15 located on the other side (fourth side surface 5D side) in the first direction X. In this embodiment, one first source region 14 is formed on one end side of the body region 12, and one second source region 15 is formed on the other end side of the body region 12.

[0049] The first source region 14 is formed at an interval from one end to the other end of the body region 12. The second source region 15 is formed at an interval from the first source region 14 to the other end of the body region 12. The second source region 15 is formed at an interval from the other end to one end of the body region 12.

[0050] The source regions 14, 15 extend in a strip shape along the extension direction of the body region 12. The source regions 14, 15 are formed spaced apart inward from both ends of the body region 12 in the second direction Y, and both ends of the body region 12 are exposed from the first main surface 3 (see FIG. 5 ).

[0051] The plurality of source regions 14, 15 are formed at intervals from the bottom of the body region 12 toward the first main surface 3, and face the second semiconductor region 11 across a part of the body region 12. The plurality of source regions 14, 15 are preferably formed at intervals from the middle of the body region 12 toward the first main surface 3.

[0052] When multiple first source regions 14 are formed in one body region 12, the multiple first source regions 14 may be formed at intervals in the extension direction of the body region 12. In this case, each first source region 14 may be formed in a strip shape extending in the second direction Y. When multiple second source regions 15 are formed in one body region 12, the multiple second source regions 15 may be formed at intervals in the extension direction of the body region 12. In this case, each second source region 15 may be formed in a strip shape extending in the second direction Y.

[0053] The semiconductor device 1A includes a plurality of p-type contact regions 16 formed in a surface layer portion of the body region 12 in a region different from the plurality of source regions 14, 15. The contact regions 16 may also be referred to as "back gate regions." The plurality of contact regions 16 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 12. A source potential is applied to the plurality of contact regions 16.

[0054] In this embodiment, one contact region 16 is interposed in a region between the first source region 14 and the second source region 15 in a surface layer portion of one body region 12 and is electrically connected to the body region 12. The contact region 16 extends in a strip shape along the extension direction of the body region 12 (the source regions 14, 15). The contact region 16 is formed spaced apart inward from both end portions of the body region 12 in the second direction Y, exposing both end portions of the body region 12 from the first main surface 3 (see FIG. 5 ).

[0055] In this embodiment, the contact region 16 has a width smaller than that of the source regions 14, 15. The width of the contact region 16 may be larger than that of the source regions 14, 15. The contact region 16 is formed at a distance from the bottom of the body region 12 toward the first main surface 3, and faces the second semiconductor region 11 with a part of the body region 12 interposed therebetween.

[0056] Contact region 16 is preferably formed at a distance from the middle of body region 12 toward first main surface 3. In this embodiment, contact region 16 has a thickness (depth) greater than the thicknesses (depths) of source regions 14, 15, and has a bottom located closer to the bottom of body region 12 than the bottoms of source regions 14, 15.

[0057] When multiple contact regions 16 are formed in one body region 12, the multiple contact regions 16 may be formed at intervals in the extension direction of the body region 12. In this case, each contact region 16 may be formed in a strip shape extending in the second direction Y.

[0058] The semiconductor device 1A includes a plurality of p-type channel regions 17, 18 formed in a surface layer portion of the first main surface 3. The plurality of channel regions 17, 18 are formed in surface layer portions of the plurality of body regions 12. The plurality of channel regions 17, 18 include a first channel region 17 on one side in the first direction X and a second channel region 18 on the other side in the first direction X.

[0059] The first channel region 17 is formed in a region between the second semiconductor region 11 (surface drift region 13) and the first source region 14 in the surface portion of the body region 12. The second channel region 18 is formed in a region between the second semiconductor region 11 (surface drift region 13) and the second source region 15 in the surface portion of the body region 12.

[0060] In this embodiment, the plurality of channel regions 17, 18 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of channel regions 17, 18 are arranged in a stripe shape extending in the second direction Y.

[0061] The semiconductor device 1A includes a plurality of gate structures 20 of a planar electrode type arranged on the first main surface 3 in the active region 8. The plurality of gate structures 20 constitute gates of a vertical transistor structure Tr.

[0062] The multiple gate structures 20 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the multiple gate structures 20 are arranged in stripes extending in the second direction Y. Furthermore, the extending direction of the multiple gate structures 20 coincides with the off-direction of the SiC single crystal.

[0063] Each of the plurality of gate structures 20 includes a gate insulating film 21, a gate electrode 22, a first planar insulating film 23, and a plurality of sidewall insulating films 24 and 25. The configuration of one gate structure 20 will be described below.

[0064] The gate insulating film 21 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 21 has a single-layer structure made of a silicon oxide film. The gate insulating film 21 preferably includes a silicon oxide film made of an oxide of the chip 2.

[0065] The gate insulating film 21 covers the first main surface 3 in a film-like shape. The gate insulating film 21 extends in a strip shape in the second direction Y in a plan view. The gate insulating film 21 covers at least one of the channel regions 17, 18. In this embodiment, the gate insulating film 21 crosses one surface drift region 13 and spans two adjacent body regions 12, covering the surface drift region 13 and the plurality of channel regions 17, 18.

[0066] Specifically, the gate insulating film 21 spans the first source region 14 on one body region 12 side and the second source region 15 on the other body region 12 side, and covers the surface drift region 13, the first source region 14, the second source region 15, the first channel region 17, and the second channel region 18.

[0067] The gate insulating film 21 partially covers the first source region 14 at a distance from the contact region 16, and exposes a part of the first source region 14 and the contact region 16 from the first main surface 3. The gate insulating film 21 partially covers the second source region 15 at a distance from the contact region 16, and exposes a part of the second source region 15 and the contact region 16 from the first main surface 3.

[0068] The gate insulating film 21 may have a thickness of 10 nm to 150 nm. The thickness of the gate insulating film 21 may have a value belonging to at least one of the ranges of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm. The thickness of the gate insulating film 21 is preferably 25 nm to 75 nm.

[0069] The gate electrode 22 is disposed on the gate insulating film 21. A gate potential is applied to the gate electrode 22 as a control potential. The gate electrode 22 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The conductivity type of the gate electrode 22 is adjusted according to the gate threshold voltage to be achieved.

[0070] The gate electrode 22 extends in a strip shape in the second direction Y in a plan view. In this embodiment, the gate electrode 22 is formed at an interval inward from both ends of the gate insulating film 21 in the first direction X, exposing both ends of the gate insulating film 21. In other words, the gate electrode 22 exposes the plurality of source regions 14, 15 and the plurality of contact regions 16.

[0071] The gate electrode 22 is disposed on the gate insulating film 21 so as to face at least one of the channel regions 17, 18. In this embodiment, the gate electrode 22 crosses one surface drift region 13 and straddles two adjacent body regions 12, and faces the surface drift region 13 and the plurality of channel regions 17, 18 with the gate insulating film 21 interposed therebetween.

[0072] Specifically, the gate electrode 22 spans the first source region 14 on one body region 12 side and the second source region 15 on the other body region 12 side, and faces the surface drift region 13, the first source region 14, the second source region 15, the first channel region 17, and the second channel region 18 across the gate insulating film 21.

[0073] The gate electrode 22 has an electrode surface 26, a first sidewall 27 on one side in the first direction X, and a second sidewall 28 on the other side in the first direction X. The electrode surface 26 extends flat along the gate insulating film 21 (first main surface 3). The electrode surface 26 may extend substantially parallel to the gate insulating film 21 (first main surface 3).

[0074] The first sidewall 27 is formed at a distance from one end of the gate insulating film 21 to the other end in the first direction X, and extends in the vertical direction Z. The second sidewall 28 is formed at a distance from the other end of the gate insulating film 21 to the one end in the first direction X, and extends in the vertical direction Z.

[0075] The first sidewall 27 and the second sidewall 28 may extend substantially perpendicular to the gate insulating film 21. That is, the gate electrode 22 may be formed in a quadrangular shape (a flattened rectangular shape) in a cross-sectional view. The first sidewall 27 and the second sidewall 28 may be obliquely inclined toward the electrode surface 26. That is, the gate electrode 22 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view.

[0076] The gate electrode 22 may have a width of 1 μm or more and 10 μm or less. The width of the gate electrode 22 is the width in a direction perpendicular to the extending direction (i.e., the first direction X). The width of the gate electrode 22 may have a value belonging to at least one of the ranges of 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, and 7.5 μm or more and 10 μm or less. The width of the gate electrode 22 is preferably 1.5 μm or more and 2.5 μm or less.

[0077] The gate electrode 22 may have a thickness of 0.1 μm or more and 2 μm or less. The thickness of the gate electrode 22 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The thickness of the gate electrode 22 is preferably 0.2 μm or more and 1 μm or less.

[0078] The first planar insulating film 23 is disposed on the gate electrode 22. Specifically, the first planar insulating film 23 covers the electrode surface 26 in a film-like manner, and exposes both the first sidewall 27 and the second sidewall 28. The first planar insulating film 23 does not have a portion that covers the gate insulating film 21. The first planar insulating film 23 extends in a strip shape in the second direction Y in a plan view.

[0079] The first planar insulating film 23 has a first insulating surface 29, a first insulating sidewall 30 on one side in the first direction X, and a second insulating sidewall 31 on the other side in the first direction X. The first insulating surface 29 extends flat along the electrode surface 26. The first insulating surface 29 may extend substantially parallel to the electrode surface 26.

[0080] The first insulating sidewall 30 extends in the vertical direction Z above the gate electrode 22 and is connected to the first sidewall 27 of the gate electrode 22. The first insulating sidewall 30 may be formed flush with the first sidewall 27.

[0081] The first insulating sidewall 30 may be located outward from the first sidewall 27 and may face the gate insulating film 21 in the stacking direction. The first insulating sidewall 30 may be located on the electrode surface 26 at a distance from the first sidewall 27 and may expose a peripheral portion of the electrode surface 26. In this case, the first insulating sidewall 30 may be connected to the first sidewall 27 via the peripheral portion of the electrode surface 26.

[0082] The second insulating sidewall 31 extends in the vertical direction Z above the gate electrode 22 and is connected to the second sidewall 28 of the gate electrode 22. The second insulating sidewall 31 may be formed flush with the second sidewall 28.

[0083] The second insulating sidewall 31 may be located outward from the second sidewall 28 and may face the gate insulating film 21 in the stacking direction. The second insulating sidewall 31 may be located on the electrode surface 26 at a distance from the second sidewall 28 and may expose the peripheral portion of the electrode surface 26. In this case, the second insulating sidewall 31 may be connected to the second sidewall 28 via the peripheral portion of the electrode surface 26.

[0084] The first insulating sidewall 30 and the second insulating sidewall 31 may extend substantially perpendicular to the gate insulating film 21. That is, the first planar insulating film 23 may be formed in a quadrangular shape (a flattened rectangular shape) in cross section. The first insulating sidewall 30 and the second insulating sidewall 31 may be obliquely inclined toward the first insulating surface 29. That is, the first planar insulating film 23 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in cross section.

[0085] The first planar insulating film 23 may have a thickness of 0.1 μm or more and 2 μm or less. The thickness of the first planar insulating film 23 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The thickness of the first planar insulating film 23 is preferably 0.2 μm or more.

[0086] The first planar insulating film 23 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first planar insulating film 23 may have a single-layer structure consisting of a single insulating film. The first planar insulating film 23 may have a stacked structure including multiple insulating films. In this embodiment, the first planar insulating film 23 has a stacked structure including a first oxide film 32 (first insulating film) and a second oxide film 33 (second insulating film) stacked in this order from the gate electrode 22 side.

[0087] The first oxide film 32 has a single-layer structure made of an undoped silicon oxide film. The undoped silicon oxide film may also be referred to as an NSG (nondoped silicate glass) film. The first oxide film 32 directly covers the electrode surface 26 in a film-like manner, exposing both the first sidewall 27 and the second sidewall 28. The first oxide film 32 extends in a strip-like shape in the second direction Y in a plan view and forms a portion of the first insulating sidewall 30 and a portion of the second insulating sidewall 31.

[0088] The first oxide film 32 may have a thickness of 0.01 μm or more and 0.2 μm or less. The thickness of the first oxide film 32 may have a value belonging to at least one of the ranges of 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.15 μm or less, and 0.15 μm or more and 0.2 μm or less. The thickness of the first oxide film 32 is preferably 0.05 μm or more.

[0089] The second oxide film 33 may have a single-layer structure made of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus. The silicon oxide film containing phosphorus may contain boron. The silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass Film). The silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass Film).

[0090] The second oxide film 33 may have a single layer structure made of a PSG film or a BPSG film stacked on the first oxide film 32. The second oxide film 33 may have a layered structure including a PSG film stacked on the first oxide film 32 and a BPSG film stacked on the PSG film. The second oxide film 33 may have a layered structure including a BPSG film stacked on the first oxide film 32 and a PSG film stacked on the BPSG film. In this embodiment, the second oxide film 33 has a single layer structure made of a PSG film, for example.

[0091] The second oxide film 33 directly covers the first oxide film 32 in a film-like manner, exposing both the first side wall 27 and the second side wall 28. The second oxide film 33 extends in a strip shape in the second direction Y in a plan view, and forms the first insulating surface 29, a part of the first insulating side wall 30, and a part of the second insulating side wall 31.

[0092] The second oxide film 33 preferably has a thickness greater than that of the first oxide film 32. The thickness of the second oxide film 33 may be less than that of the first oxide film 32. The thickness of the second oxide film 33 may be 0.05 μm or more and 1.8 μm or less.

[0093] The thickness of the second oxide film 33 may be in at least one of the ranges of 0.05 μm to 0.1 μm, 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, and 1.5 μm to 1.8 μm. The thickness of the second oxide film 33 is preferably 0.1 μm or greater.

[0094] The second oxide film 33 improves the flatness of the first planar insulating film 23 (i.e., the film formability of the first planar insulating film 23 on the electrode surface 26). Fluctuations in the electrical characteristics of the gate electrode 22 due to impurity diffusion in the second oxide film 33 are suppressed by the first oxide film 32 with no impurities added. Fluctuations in the insulating characteristics of the second oxide film 33 due to impurity diffusion in the gate electrode 22 are suppressed by the first oxide film 32 with no impurities added.

[0095] The plurality of sidewall insulating films 24, 25 respectively cover the first sidewall 27 and the second sidewall 28. Specifically, the plurality of sidewall insulating films 24, 25 include a first sidewall insulating film 24 covering the first sidewall 27 and a second sidewall insulating film 25 covering the second sidewall 28.

[0096] The first sidewall insulating film 24 covers the first sidewall 27 on the gate insulating film 21. The first sidewall insulating film 24 is formed on the gate insulating film 21 at a distance from the contact region 16, and exposes a part of the second source region 15 and the contact region 16. Specifically, the first sidewall insulating film 24 is disposed only on the gate insulating film 21, and does not have a portion that directly covers the second source region 15 or a portion that directly covers the contact region 16.

[0097] The first sidewall insulating film 24 faces a part of the second source region 15 across the gate insulating film 21. The first sidewall insulating film 24 is formed at a distance from the second channel region 18 inwardly of the body region 12. The first sidewall insulating film 24 does not have a portion facing the second channel region 18 across the gate insulating film 21.

[0098] In this embodiment, the first sidewall insulating film 24 extends from the first sidewall 27 to the first insulating sidewall 30 side of the first planar insulating film 23 and covers the first insulating sidewall 30. That is, the first sidewall insulating film 24 has a portion that covers the first sidewall 27 and a portion that covers the first insulating sidewall 30. The first sidewall insulating film 24 also has a portion that covers the boundary between the gate electrode 22 and the first planar insulating film 23.

[0099] The first sidewall insulating film 24 covers the first sidewall 27 and the first insulating sidewall 30 in a film shape, following the inclination angles of the first sidewall 27 and the first insulating sidewall 30. The first sidewall insulating film 24 extends at an inclination angle substantially equal to the inclination angle of the first sidewall 27 in the covering portion relative to the first sidewall 27, and has a film surface extending substantially parallel to the first sidewall 27. The first sidewall insulating film 24 extends at an inclination angle substantially equal to the inclination angle of the first insulating sidewall 30 in the covering portion relative to the first insulating sidewall 30, and has a film surface extending substantially parallel to the first insulating sidewall 30.

[0100] In this embodiment, the first sidewall insulating film 24 extends substantially vertically in the region between the gate insulating film 21 (first main surface 3) and the first insulating surface 29. That is, the first sidewall insulating film 24 has a film surface extending in the vertical direction Z in the portion covering the first sidewall 27, and has a film surface extending in the vertical direction Z in the portion covering the first insulating sidewall 30.

[0101] The first sidewall insulating film 24 covers both the first oxide film 32 and the second oxide film 33 on the first insulating sidewall 30 side. That is, the first sidewall insulating film 24 has a portion that covers the boundary between the first oxide film 32 and the second oxide film 33. The first sidewall insulating film 24 is formed on the first main surface 3 side of the first insulating surface 29, and exposes the first insulating surface 29. That is, the first sidewall insulating film 24 exposes the second oxide film 33 from the first insulating surface 29.

[0102] The second sidewall insulating film 25 covers the second sidewall 28 on the gate insulating film 21. The second sidewall insulating film 25 is formed on the gate insulating film 21 at a distance from the contact region 16, and exposes a part of the first source region 14 and the contact region 16. Specifically, the second sidewall insulating film 25 is disposed only on the gate insulating film 21, and does not have a portion that directly covers the first source region 14 or a portion that directly covers the contact region 16.

[0103] The second sidewall insulating film 25 faces a part of the first source region 14 across the gate insulating film 21. The second sidewall insulating film 25 is formed at a distance from the first channel region 17 inwardly of the body region 12. The second sidewall insulating film 25 does not have a part facing the first channel region 17 across the gate insulating film 21.

[0104] In this embodiment, the second sidewall insulating film 25 extends from the second sidewall 28 to the second insulating sidewall 31 side of the first planar insulating film 23 and covers the second insulating sidewall 31. That is, the second sidewall insulating film 25 has a portion that covers the second sidewall 28 and a portion that covers the second insulating sidewall 31. The second sidewall insulating film 25 also has a portion that covers the boundary between the gate electrode 22 and the first planar insulating film 23.

[0105] The second sidewall insulating film 25 covers the second sidewall 28 and the second insulating sidewall 31 in a film shape in accordance with the inclination angles of the second sidewall 28 and the second insulating sidewall 31. The second sidewall insulating film 25 extends at an inclination angle substantially equal to the inclination angle of the second sidewall 28 in the covering portion relative to the second sidewall 28, and has a film surface extending substantially parallel to the second sidewall 28. The second sidewall insulating film 25 extends at an inclination angle substantially equal to the inclination angle of the second insulating sidewall 31 in the covering portion relative to the second insulating sidewall 31, and has a film surface extending substantially parallel to the second insulating sidewall 31.

[0106] In this embodiment, the second sidewall insulating film 25 extends substantially vertically in the region between the gate insulating film 21 (first main surface 3) and the first insulating surface 29. That is, the second sidewall insulating film 25 has a film surface extending in the vertical direction Z in the portion covering the second sidewall 28, and has a film surface extending in the vertical direction Z in the portion covering the second insulating sidewall 31.

[0107] The second sidewall insulating film 25 covers both the first oxide film 32 and the second oxide film 33 on the second insulating sidewall 31 side. That is, the second sidewall insulating film 25 has a portion that covers the boundary between the first oxide film 32 and the second oxide film 33. The second sidewall insulating film 25 has a portion facing the first sidewall insulating film 24 with the first oxide film 32 interposed therebetween, and a portion facing the first sidewall insulating film 24 with the second oxide film 33 interposed therebetween.

[0108] The second sidewall insulating film 25 is formed on the first main surface 3 side of the first insulating surface 29, and exposes the first insulating surface 29. In other words, the second sidewall insulating film 25 exposes the second oxide film 33 from the first insulating surface 29.

[0109] The sidewall insulating films 24, 25 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The sidewall insulating films 24, 25 may each have a single-layer structure made of a single insulating film. The sidewall insulating films 24, 25 may each have a stacked structure including a plurality of insulating films.

[0110] In this embodiment, the sidewall insulating films 24, 25 each have a single-layer structure made of a silicon oxide film with no added impurities. That is, the sidewall insulating films 24, 25 each consist of an NSG film. In this embodiment, the sidewall insulating films 24, 25 each consist of a tetraethyl orthosilicate film, which is an example of an NSG film. The tetraethyl orthosilicate film may also be called a "TEOS film (Tetraethyl orthosilicate film)."

[0111] When the plurality of sidewall insulating films 24, 25 are made of an NSG film (TEOS film), fluctuations in the electrical characteristics of the gate electrode 22 caused by impurity diffusion in the second oxide film 33 are suppressed by the plurality of sidewall insulating films 24, 25. In addition, fluctuations in the insulating characteristics of the second oxide film 33 caused by impurity diffusion in the gate electrode 22 are suppressed by the plurality of sidewall insulating films 24, 25.

[0112] The sidewall insulating films 24, 25 each have a thickness less than the thickness of the gate electrode 22. The thickness of the sidewall insulating films 24, 25 is the horizontal thickness of the sidewall insulating films 24, 25 based on the first sidewall 27 or the second sidewall 28 of the gate electrode 22. The thickness of the sidewall insulating films 24, 25 is less than the thickness (total thickness) of the first planar insulating film 23.

[0113] The thickness of the sidewall insulating films 24, 25 is preferably less than the thickness of the second oxide film 33. The thickness of the sidewall insulating films 24, 25 is preferably less than the thickness of the first oxide film 32. The thickness of the sidewall insulating films 24, 25 is preferably greater than the thickness of the gate insulating film 21. The thickness of the sidewall insulating films 24, 25 may be less than the thickness of the gate insulating film 21.

[0114] The thickness of the sidewall insulating films 24, 25 may be 0.05 μm or more and 0.5 μm or less. The thickness of the sidewall insulating films 24, 25 may have a value belonging to at least one of the ranges of 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.15 μm or less, 0.15 μm or more and 0.2 μm or less, 0.2 μm or more and 0.25 μm or less, 0.25 μm or more and 0.3 μm or less, 0.3 μm or more and 0.35 μm or less, 0.35 μm or more and 0.4 μm or less, 0.4 μm or more and 0.45 μm or less, and 0.45 μm or more and 0.5 μm or less. The thickness of the sidewall insulating films 24, 25 is preferably 0.1 μm or more and 0.3 μm or less.

[0115] The gate structure 20 controls the inversion and non-inversion of the channel regions 17, 18 in response to a gate potential applied to the gate electrode 22. When a gate potential is applied to the gate electrode 22, the channel regions 17, 18 are turned on, and a drain current flows between the second semiconductor region 11 and the source regions 14, 15 via the channel regions 17, 18 (body region 12). In this way, a planar gate type transistor structure Tr is formed in the inner part (active region 8) of the chip 2.

[0116] The semiconductor device 1A includes a p-type outer body region 40 formed in a surface layer portion of the first main surface 3 in the peripheral region 9. The outer body region 40 is formed in a surface layer portion of the second semiconductor region 11. The outer body region 40 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 11.

[0117] The outer body region 40 preferably has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 12. The p-type impurity concentration of the outer body region 40 may be less than the p-type impurity concentration of the body region 12 or may be higher than the p-type impurity concentration of the body region 12.

[0118] The outer body region 40 is formed at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the active region 8, and extends in a strip shape along the active region 8. The outer body region 40 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view, and partitions the body regions 12 (active regions 8) from multiple directions.

[0119] In this embodiment, the outer body region 40 collectively surrounds multiple body regions 12 (active regions 8) in a planar view and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0120] That is, the outer body region 40 forms the boundary between the active region 8 and the peripheral region 9. The outer body region 40 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ).

[0121] The outer body region 40 is exposed from the first main surface 3. The outer body region 40 is formed at a distance from the bottom of the second semiconductor region 11 toward the first main surface 3, and faces the first semiconductor region 10 across a part of the second semiconductor region 11. The outer body region 40 is preferably formed at a distance from the middle of the second semiconductor region 11 toward the first main surface 3. The outer body region 40 may cross the depth position of the middle of the second semiconductor region 11 in the thickness direction.

[0122] The outer body region 40 has an inner edge portion on the active region 8 side and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer body region 40 is connected to the plurality of body regions 12 in a portion extending in the first direction X, and defines the plurality of body regions 12 and the plurality of surface drift regions 13 in the surface portion of the second semiconductor region 11.

[0123] That is, the outer body region 40 is electrically connected to the plurality of body regions 12. As a result, a source potential is applied to the outer body region 40 via the plurality of body regions 12. The outer body region 40 forms a pn junction with the second semiconductor region 11, and expands a depletion layer into the second semiconductor region 11 when a reverse bias voltage is applied.

[0124] The outer body region 40 is connected to the plurality of body regions 12 at intervals from the source regions 14, 15 in the second direction Y. Therefore, the outer body region 40 does not have the source regions 14, 15 in its surface portion (see FIG. 5 ). Furthermore, the outer body region 40 is connected to the plurality of body regions 12 at intervals from the contact region 16 in the second direction Y. Therefore, the outer body region 40 does not have the contact region 16 in its surface portion (see FIG. 5 ).

[0125] The outer body region 40 preferably has a width greater than that of the body region 12. The width of the outer body region 40 is the width in a direction perpendicular to the extension direction. The width of the outer body region 40 may be approximately equal to the width of the body region 12, or may be less than the width of the body region 12.

[0126] The ratio of the width of the outer body region 40 to the width of the body region 12 may be 1 or greater and 50 or less. The width ratio may have a value belonging to at least one of the ranges of 1 or greater and 10 or less, 10 or greater and 20 or less, 20 or greater and 30 or less, 30 or greater and 40 or less, and 40 or greater and 50 or less. The width ratio is preferably 10 or greater. The width ratio is preferably 20 or greater and 40 or less.

[0127] The outer body region 40 preferably has a thickness (depth) approximately equal to the thickness (depth) of the body region 12. The thickness of the outer body region 40 may be less than the thickness of the body region 12 or may be greater than the thickness of the body region 12.

[0128] The semiconductor device 1A includes a p-type termination region 41 formed on the first main surface 3 in the peripheral region 9. The termination region 41 may also be referred to as a "well region" or "termination well region." The termination region 41 is formed in a surface layer portion of the second semiconductor region 11.

[0129] Termination region 41 has a p-type impurity concentration different from the p-type impurity concentration of body region 12. The p-type impurity concentration of termination region 41 is preferably higher than the p-type impurity concentration of body region 12. The p-type impurity concentration of termination region 41 may be lower than the p-type impurity concentration of body region 12. Alternatively, the p-type impurity concentration of termination region 41 may be approximately equal to the p-type impurity concentration of body region 12.

[0130] The termination region 41 has a p-type impurity concentration different from the p-type impurity concentration of the outer body region 40. The p-type impurity concentration of the termination region 41 is preferably higher than the p-type impurity concentration of the outer body region 40. The p-type impurity concentration of the termination region 41 may be lower than the p-type impurity concentration of the outer body region 40. Alternatively, the p-type impurity concentration of the termination region 41 may be approximately equal to the p-type impurity concentration of the outer body region 40.

[0131] Termination region 41 is spaced inward from the periphery of first main surface 3 and is formed in a region between the periphery of first main surface 3 and outer body region 40. Termination region 41 extends in a band shape along outer body region 40 in a plan view. Termination region 41 has a portion that extends in a band shape in first direction X and a portion that extends in a band shape in second direction Y in a plan view, and defines active region 8 from multiple directions.

[0132] In this embodiment, termination region 41 surrounds outer body region 40 (active region 8 and multiple body regions 12) in plan view and is defined in the shape of a polygonal ring (a quadrangular ring in this embodiment) having four sides parallel to the periphery of first main surface 3. Termination region 41 may have an edge portion that connects the portion extending in first direction X and the portion extending in second direction Y in plan view in an arc shape (preferably a quadrant arc shape) (see FIG. 4 ).

[0133] The termination region 41 is formed at a distance from the bottom of the second semiconductor region 11 toward the first main surface 3, and faces the first semiconductor region 10 across a part of the second semiconductor region 11. The termination region 41 is preferably formed at a distance from the middle of the second semiconductor region 11 toward the first main surface 3.

[0134] The termination region 41 may cross the depth position of the middle part of the second semiconductor region 11 in the thickness direction. The termination region 41 may have a thickness (depth) substantially equal to the thickness (depth) of the outer body region 40. The thickness of the termination region 41 may be greater than the thickness of the outer body region 40, or may be less than the thickness of the outer body region 40.

[0135] The termination region 41 has an inner edge portion on the active region 8 side and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the termination region 41 is connected to the outer edge portion of the outer body region 40 in the surface layer portion of the second semiconductor region 11.

[0136] As a result, the termination region 41 is electrically connected to the outer body region 40, and is electrically connected to the plurality of body regions 12 via the outer body region 40. The termination region 41 forms a pn junction with the second semiconductor region 11, and expands a depletion layer into the second semiconductor region 11 when a reverse bias voltage is applied.

[0137] In this embodiment, the inner edge of the termination region 41 is connected around the entire periphery to the outer edge of the outer body region 40. When the termination region 41 has a p-type impurity concentration substantially equal to the p-type impurity concentration of the outer body region 40, the termination region 41 may be considered as part (the lead-out portion) of the outer body region 40.

[0138] The termination region 41 (inner edge portion) has an overlap region 42 that overlaps the outer edge portion of the outer body region 40 in the surface layer portion of the second semiconductor region 11. The overlap region 42 is a high-concentration region that includes the outer edge portion of the outer body region 40 and the inner edge portion of the termination region 41. In other words, the overlap region 42 includes both the p-type impurities of the outer body region 40 and the p-type impurities of the termination region 41, and has a p-type impurity concentration that is higher than both the p-type impurity concentrations of the outer body region 40 and the termination region 41.

[0139] The p-type impurity concentration of the overlap region 42 is preferably higher than the p-type impurity concentration of the body region 12. The p-type impurity concentration of the overlap region 42 may be lower than the p-type impurity concentration of the contact region 16. The p-type impurity concentration of the overlap region 42 may be higher than the p-type impurity concentration of the contact region 16.

[0140] The overlap region 42 extends in a band shape along the outer body region 40 in a plan view. The overlap region 42 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions. In this embodiment, the overlap region 42 is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0141] The overlap region 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ). The width of the overlap region 42 is preferably greater than the width of the body region 12. The width of the overlap region 42 may be less than the width of the body region 12.

[0142] The semiconductor device 1A may have a relatively high-concentration p-type well region (42) instead of the overlap region 42. In this case, the well region (42) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 40 and the p-type impurity concentration of the termination region 41.

[0143] The p-type impurity concentration of the well region (42) is preferably higher than the p-type impurity concentration of the body region 12. The p-type impurity concentration of the well region (42) may be approximately equal to the p-type impurity concentration of the contact region 16. The p-type impurity concentration of the well region (42) may be lower than the p-type impurity concentration of the contact region 16 or higher than the p-type impurity concentration of the contact region 16.

[0144] The well region (42) may be formed in either or both of the surface layer portion of the outer body region 40 and the surface layer portion of the termination region 41. The well region (42) is effective when the termination region 41 has a p-type impurity concentration substantially equal to the p-type impurity concentration of the outer body region 40 and is formed as part of the outer body region 40 (draw-out portion).

[0145] The semiconductor device 1A includes at least one p-type field region 43 formed in the outer peripheral region 9 in a surface layer portion of the first main surface 3. The plurality of field regions 43 may be formed in an electrically floating state. The plurality of field regions 43 may be fixed to the source potential.

[0146] The number of field regions 43 is arbitrary. The number of field regions 43 may be 1 or more and 20 or less. The number of field regions 43 may be a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less. The number of field regions 43 is typically 1 or more and 8 or less. In this embodiment, the semiconductor device 1A includes three field regions 43.

[0147] The plurality of field regions 43 are formed in a surface layer portion of the second semiconductor region 11. The plurality of field regions 43 are formed inwardly from the periphery of the first main surface 3 at intervals in a region between the periphery of the first main surface 3 and the plurality of body regions 12 (active regions 8).

[0148] Specifically, the field regions 43 are formed in the region between the periphery of the first main surface 3 and the outer body region 40. Even more specifically, the field regions 43 are arranged in the region between the periphery of the first main surface 3 and the termination region 41, at intervals from the outer edge of the termination region 41 toward the periphery of the first main surface 3.

[0149] The field regions 43 are formed in a strip shape extending along the body regions 12 (termination regions 41) in a plan view. Each of the field regions 43 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y.

[0150] In this embodiment, the field regions 43 are formed in polygonal ring shapes (square ring shapes in this embodiment) surrounding the body regions 12 (termination regions 41) in a plan view. The field regions 43 may have edge portions that connect the portions extending in the first direction X and the portions extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 4 ).

[0151] The plurality of field regions 43 are formed at intervals from the depth position of the bottom of the second semiconductor region 11 toward the first main surface 3. The plurality of field regions 43 are preferably formed at intervals from the depth position of the middle of the second semiconductor region 11 toward the first main surface 3. The plurality of field regions 43 may cross the depth position of the middle of the second semiconductor region 11 in the thickness direction. The plurality of field regions 43 each form a pn junction with the second semiconductor region 11, and expand a depletion layer toward the second semiconductor region 11 when a reverse bias voltage is applied.

[0152] The width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 43 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 43 may be approximately constant or may be non-uniform. The width of the multiple field regions 43 may gradually increase toward the periphery of the first main surface 3. The width of the multiple field regions 43 may gradually decrease toward the periphery of the first main surface 3.

[0153] The depth of the field regions 43 may be substantially uniform or may be non-uniform. The depth of the field regions 43 may gradually increase toward the periphery of the first main surface 3. The depth of the field regions 43 may gradually decrease toward the periphery of the first main surface 3.

[0154] The field regions 43 may have shallow portions that are relatively shallow and deep portions that are deeper than the shallow portions. The shallow portions may be formed on the inner side and the deep portions may be formed on the peripheral edge side. Alternatively, the shallow portions may be formed on the peripheral edge side and the deep portions may be formed on the inner side.

[0155] The spacing between the multiple field regions 43 may be substantially uniform or may be non-uniform. The spacing between the multiple field regions 43 may gradually increase toward the periphery of the first main surface 3. The spacing between the multiple field regions 43 may gradually decrease toward the periphery of the first main surface 3.

[0156] The p-type impurity concentrations of the plurality of field regions 43 may be approximately constant or may be non-uniform. The p-type impurity concentrations of the plurality of field regions 43 may gradually increase toward the periphery of the first main surface 3. The p-type impurity concentrations of the plurality of field regions 43 may gradually decrease toward the periphery of the first main surface 3.

[0157] The plurality of field regions 43 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 12. The p-type impurity concentration of the plurality of field regions 43 may be higher than the p-type impurity concentration of the body region 12 or may be lower than the p-type impurity concentration of the body region 12.

[0158] The p-type impurity concentrations of the plurality of field regions 43 may be approximately equal to the p-type impurity concentration of the outer body region 40. The p-type impurity concentrations of the plurality of field regions 43 may be higher than the p-type impurity concentration of the outer body region 40, or may be lower than the p-type impurity concentration of the outer body region 40.

[0159] The p-type impurity concentrations of the plurality of field regions 43 may be approximately equal to the p-type impurity concentration of the termination region 41. The p-type impurity concentrations of the plurality of field regions 43 may be higher than the p-type impurity concentration of the termination region 41, or may be lower than the p-type impurity concentration of the termination region 41.

[0160] The semiconductor device 1A includes a main surface insulating film 44 that covers the first main surface 3 in the peripheral region 9. The main surface insulating film 44 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 44 has a single-layer structure made of a silicon oxide film.

[0161] The main surface insulating film 44 preferably includes a silicon oxide film made of an oxide of the chip 2. The main surface insulating film 44 is preferably made of the same type of insulating material as the insulating material of the gate insulating film 21. The main surface insulating film 44 preferably has a thickness approximately equal to that of the gate insulating film 21.

[0162] The main surface insulating film 44 covers the first main surface 3 in the peripheral region 9 in a film-like manner. The main surface insulating film 44 collectively covers the second semiconductor region 11, the outer body region 40, the termination region 41, and the plurality of field regions 43. The main surface insulating film 44 is connected to the plurality of gate insulating films 21 on the active region 8 side. Specifically, the main surface insulating film 44 is formed integrally with the plurality of gate insulating films 21, and forms a single insulating film together with the plurality of gate insulating films 21.

[0163] The semiconductor device 1A includes a planar wiring structure 50 arranged on the first main surface 3 in the peripheral region 9. The wiring structure 50 is selectively routed on the first main surface 3 in the peripheral region 9 in a layout different from the layout of the plurality of gate structures 20, and is connected to the plurality of gate structures 20 on the active region 8 side. The wiring structure 50 may also be referred to as a "gate wiring structure." The wiring structure 50 applies a gate potential to the plurality of gate structures 20.

[0164] The wiring structure 50 includes the aforementioned main surface insulating film 44, a gate wiring 51, a second planar insulating film 52, and a plurality of third sidewall insulating films 53. The gate wiring 51 may be referred to as a "second gate electrode" or the like. The gate wiring 51 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The gate wiring 51 preferably has the same conductivity type as the gate electrode 22.

[0165] The gate wiring 51 is arranged on the main surface insulating film 44 in the outer periphery region 9 at a distance from the periphery of the first main surface 3 toward the active region 8. In this embodiment, the gate wiring 51 is arranged at a distance from the termination region 41 toward the active region 8, and is arranged on a portion of the main surface insulating film 44 that covers the outer body region 40. In other words, the gate wiring 51 faces the outer body region 40 with the main surface insulating film 44 in between. The gate wiring 51 may face the termination region 41 in the stacking direction.

[0166] The gate wiring 51 has a portion that extends in a direction different from the direction of the plurality of gate electrodes 22. The gate wiring 51 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view, and separates the plurality of gate electrodes 22 (active regions 8) from multiple directions.

[0167] In this embodiment, the gate wiring 51 surrounds the plurality of gate electrodes 22 (active regions 8) in a plan view and is defined in the shape of a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The gate wiring 51 may be either terminated or endless.

[0168] In this embodiment, the gate wiring 51 extends in a strip shape (annular shape in this embodiment) along the outer body region 40 in a plan view, and faces the outer body region 40 across the entire area in the stacking direction, sandwiching the main surface insulating film 44. The gate wiring 51 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ).

[0169] In this embodiment, the gate wiring 51 has a width less than that of the outer body region 40 in a plan view, and is disposed on the outer body region 40 at a distance from the inner and outer edges of the outer body region 40. That is, in this embodiment, the multiple gate electrodes 22 are extended onto the outer body region 40, and the gate wiring 51 is connected to the multiple gate electrodes 22 on the outer body region 40. The width of the gate wiring 51 may be greater than the width of the outer body region 40.

[0170] The width of the gate wiring 51 is preferably larger than the width of the gate electrode 22. The width of the gate wiring 51 is the width in a direction perpendicular to the extending direction. The width of the gate wiring 51 may be equal to or smaller than the width of the gate electrode 22. For example, the ratio of the width of the gate wiring 51 to the width of the gate electrode 22 may be 0.5 or more and 50 or less.

[0171] The width ratio may have a value belonging to at least one of the ranges of 0.5 to 1, 1 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50. The width ratio may be 5 or greater. The width ratio may be 20 to 40.

[0172] The gate wiring 51 has a wiring surface 54, a first wiring sidewall 55 on the inner edge side, and a second wiring sidewall 56 on the outer edge side. The wiring surface 54 extends flatly along the main surface insulating film 44 (first main surface 3). The wiring surface 54 may extend substantially parallel to the main surface insulating film 44 (first main surface 3).

[0173] The first wiring sidewall 55 extends in the vertical direction Z on the main surface insulating film 44. The first wiring sidewall 55 is connected to the plurality of gate electrodes 22 (the first sidewall 27 and the second sidewall 28) in a portion extending in the first direction X.

[0174] That is, the gate wiring 51 has a plurality of portions connected in a T-shape to the plurality of gate electrodes 22, and is electrically connected to the plurality of gate electrodes 22. The second wiring sidewall 56 extends in the vertical direction Z on the main surface insulating film 44. The second wiring sidewall 56 is formed as an open end in the peripheral region 9.

[0175] The first wiring sidewall 55 and the second wiring sidewall 56 may extend perpendicular to the main surface insulating film 44. That is, the gate wiring 51 may be formed in a quadrangular shape (a flat rectangular shape) in a cross-sectional view. The first wiring sidewall 55 and the second wiring sidewall 56 may be obliquely inclined toward the wiring surface 54. That is, the gate wiring 51 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view.

[0176] The gate wiring 51 preferably has a thickness approximately equal to that of the gate electrode 22. The thickness of the gate wiring 51 may be greater than or less than that of the gate electrode 22.

[0177] The gate wiring 51 may have a thickness of 1 μm or more and 10 μm or less. The thickness of the gate wiring 51 may have a value belonging to at least one of the ranges of 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, and 7.5 μm or more and 10 μm or less. The thickness of the gate wiring 51 is preferably 1 μm or more and 5 μm or less.

[0178] The second planar insulating film 52 is disposed on the gate wiring 51 and covers the wiring surface 54 in a film form. The second planar insulating film 52 exposes the first wiring sidewall 55 of the gate wiring 51 and covers the second wiring sidewall 56 of the gate wiring 51. The second planar insulating film 52 directly covers the wiring surface 54 and the second wiring sidewall 56 over the entire area of ​​the gate wiring 51 and exposes the first wiring sidewall 55.

[0179] The second planar insulating film 52 is connected to the first planar insulating films 23 at the connection portions between the gate electrodes 22 and the gate wirings 51. That is, the second planar insulating film 52 has a plurality of portions connected in a T-shape to the first planar insulating films 23. The second planar insulating film 52 has an arc corner portion curved in an arc shape in the covering portion corresponding to the corner on the second wiring sidewall 56 side.

[0180] The second planar insulating film 52 has a second insulating surface 57 and a third insulating sidewall 58 on the side of the first wiring sidewall 55. The second insulating surface 57 extends flatly along the wiring surface 54. The second insulating surface 57 may extend substantially parallel to the wiring surface 54.

[0181] The third insulating sidewall 58 extends in the vertical direction Z on the gate wiring 51 and is connected to the first wiring sidewall 55 of the gate wiring 51. The third insulating sidewall 58 is connected to the first insulating sidewalls 30 and second insulating sidewalls 31 of the plurality of first planar insulating films 23 at the connection portion between the plurality of gate electrodes 22 and the gate wiring 51. In other words, the third insulating sidewall 58 has a portion connected to the first sidewall insulating film 24 in an L-shape and a portion connected to the second sidewall insulating film 25 in an L-shape.

[0182] The third insulating sidewall 58 may be formed flush with the first wiring sidewall 55. The third insulating sidewall 58 may be located closer to the active region 8 than the first wiring sidewall 55 and may face the main surface insulating film 44 in the stacking direction.

[0183] The third insulating sidewall 58 may be located on the wiring surface 54 at a distance from the first wiring sidewall 55, and may expose the peripheral portion of the wiring surface 54. In this case, the third insulating sidewall 58 may be connected to the first wiring sidewall 55 via the peripheral portion of the wiring surface 54. The third insulating sidewall 58 may extend approximately perpendicular to the main surface insulating film 44. The third insulating sidewall 58 may be inclined obliquely toward the second insulating surface 57.

[0184] The second planar insulating film 52 preferably has a thickness approximately equal to that of the first planar insulating film 23. The thickness of the second planar insulating film 52 may be greater than the thickness of the first planar insulating film 23 or may be less than the thickness of the first planar insulating film 23.

[0185] The thickness of the second planar insulating film 52 may be 0.1 μm or more and 2 μm or less. The thickness of the second planar insulating film 52 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The thickness of the second planar insulating film 52 is preferably 0.2 μm or more.

[0186] The second planar insulating film 52 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second planar insulating film 52 may have a single-layer structure made of a single insulating film. The second planar insulating film 52 may have a multilayer structure including multiple insulating films.

[0187] In this embodiment, the second planar insulating film 52, like the first planar insulating film 23, has a laminated structure including a first oxide film 59 (first insulating film) and a second oxide film 60 (second insulating film) laminated in this order from the gate wiring 51 side.

[0188] The first oxide film 59 has a single-layer structure made of an NSG film. The first oxide film 59 directly covers the wiring surface 54 and the second wiring sidewall 56 of the gate wiring 51 in a film form, and exposes the first wiring sidewall 55 of the gate wiring 51. The first oxide film 59 forms a part of the third insulating sidewall 58 on the gate wiring 51.

[0189] The first oxide film 59 extends flatly in the horizontal direction in the covering portion on the wiring surface 54. The first oxide film 59 is connected to the plurality of first oxide films 32 at the connection portion between the plurality of gate electrodes 22 and the gate wiring 51. In other words, the first oxide film 59 has a plurality of portions connected to the plurality of first oxide films 32 in a T-shape.

[0190] The first oxide film 59 extends in the vertical direction Z in the portion covering the second wiring sidewall 56. The first oxide film 59 preferably extends at an inclination angle substantially equal to the inclination angle of the second wiring sidewall 56 in the portion covering the second wiring sidewall 56. The film surface of the first oxide film 59 preferably has a portion that extends substantially parallel to the second wiring sidewall 56. The first oxide film 59 preferably has an arc corner portion that is curved in an arc shape in the portion covering the corner of the gate wiring 51 on the side of the second wiring sidewall 56.

[0191] The first oxide film 59 preferably has a thickness approximately equal to the thickness of the first oxide film 32 of the first planar insulating film 23. The thickness of the first oxide film 59 may be greater than the thickness of the first oxide film 32 or may be less than the thickness of the first oxide film 32.

[0192] The first oxide film 59 may have a thickness of 0.01 μm or more and 0.2 μm or less. The thickness of the first oxide film 59 may have a value belonging to at least one of the ranges of 0.01 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.15 μm or less, and 0.15 μm or more and 0.2 μm or less. The thickness of the first oxide film 59 is preferably 0.05 μm or more.

[0193] The second oxide film 60 may have a single layer structure or a multilayer structure including either or both of a PSG film and a BPSG film. The second oxide film 60 may have a multilayer structure including a PSG film stacked on the first oxide film 59 and a BPSG film stacked on the PSG film. The second oxide film 60 may have a multilayer structure including a BPSG film stacked on the first oxide film 59 and a PSG film stacked on the BPSG film. In this embodiment, the second oxide film 60 has a single layer structure made of a PSG film, for example.

[0194] The second oxide film 60 directly covers the first oxide film 59. The second oxide film 60 covers the wiring surface 54 and the second wiring sidewall 56 with the first oxide film 59 in between, exposing the first wiring sidewall 55 of the gate wiring 51.

[0195] The second oxide film 60 extends flatly in the horizontal direction in the covering portion relative to the wiring surface 54, and forms part of the third insulating sidewall 58 on the first oxide film 59. The second oxide film 60 is connected to the second oxide films 33 at the connection portions of the gate electrodes 22 and the gate wirings 51. In other words, the second oxide film 60 has a plurality of portions connected to the second oxide films 33 in a T-shape.

[0196] The second oxide film 60 extends in the vertical direction Z in the portion covering the second wiring sidewall 56. Preferably, the second oxide film 60 extends at an inclination angle substantially equal to the inclination angle of the second wiring sidewall 56 in the portion covering the second wiring sidewall 56. The film surface of the second oxide film 60 preferably has a portion that extends substantially parallel to the second wiring sidewall 56. The second oxide film 60 preferably has an arc corner portion that is curved in an arc shape in the portion covering the corner of the gate wiring 51 on the side of the second wiring sidewall 56.

[0197] The second oxide film 60 preferably has a thickness greater than that of the first oxide film 59. The thickness of the second oxide film 60 may be less than that of the first oxide film 59. The thickness of the second oxide film 60 is preferably approximately equal to the thickness of the second oxide film 33 of the first planar insulating film 23. The thickness of the second oxide film 60 may be greater than that of the second oxide film 33 or may be less than that of the second oxide film 33.

[0198] The thickness of the second oxide film 60 may be 0.05 μm or more and 1.8 μm or less. The thickness of the second oxide film 60 may have a value belonging to at least one of the ranges of 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 1.8 μm or less. The thickness of the second oxide film 60 is preferably 0.1 μm or more.

[0199] The second oxide film 60 improves the flatness of the second planar insulating film 52 (i.e., the film formability of the second planar insulating film 52 on the wiring surface 54). Fluctuations in the electrical characteristics of the gate wiring 51 due to impurity diffusion in the second oxide film 60 are suppressed by the first oxide film 59 containing no impurities. Fluctuations in the insulating characteristics of the second oxide film 60 due to impurity diffusion in the gate wiring 51 are suppressed by the first oxide film 59 containing no impurities.

[0200] The plurality of third sidewall insulating films 53 respectively cover the first wiring sidewalls 55 of the gate wiring 51. Specifically, the plurality of third sidewall insulating films 53 respectively cover the first wiring sidewalls 55 except for the connection portions of the plurality of gate electrodes 22 and the gate wiring 51. The configuration of one third sidewall insulating film 53 will be described below.

[0201] The third sidewall insulating film 53 covers the first wiring sidewall 55 on the main surface insulating film 44 and faces a part of the outer body region 40 across the main surface insulating film 44. The third sidewall insulating film 53 is formed at a distance from the plurality of source regions 14, 15 and the contact region 16 on the gate wiring 51 side. The third sidewall insulating film 53 does not have a portion facing the plurality of source regions 14, 15 and the contact region 16.

[0202] In this embodiment, the third sidewall insulating film 53 extends from the first wiring sidewall 55 to the third insulating sidewall 58 side of the second planar insulating film 52 and covers the third insulating sidewall 58. That is, the third sidewall insulating film 53 has a portion that covers the first wiring sidewall 55 and a portion that covers the third insulating sidewall 58. The third sidewall insulating film 53 also has a portion that covers the boundary between the gate wiring 51 and the second planar insulating film 52.

[0203] The third sidewall insulating film 53 covers the first wiring sidewall 55 and the third insulating sidewall 58 in a film shape, following the inclination angles of the first wiring sidewall 55 and the third insulating sidewall 58. The third sidewall insulating film 53 extends at an inclination angle substantially equal to the inclination angle of the first wiring sidewall 55 in the covering portion relative to the first wiring sidewall 55, and has a film surface extending substantially parallel to the first wiring sidewall 55. The third sidewall insulating film 53 extends at an inclination angle substantially equal to the inclination angle of the third insulating sidewall 58 in the covering portion relative to the third insulating sidewall 58, and has a film surface extending substantially parallel to the third insulating sidewall 58.

[0204] In this embodiment, the third sidewall insulating film 53 extends substantially vertically in the region between the main surface insulating film 44 (first main surface 3) and the second insulating surface 57. That is, the third sidewall insulating film 53 has a film surface extending in the vertical direction Z in the portion covering the first wiring sidewall 55, and has a film surface extending in the vertical direction Z in the portion covering the third insulating sidewall 58.

[0205] The third sidewall insulating film 53 covers both the first oxide film 59 and the second oxide film 60 on the third insulating sidewall 58 side. The third sidewall insulating film 53 also has a portion that covers the boundary between the first oxide film 59 and the second oxide film 60. The third sidewall insulating film 53 is formed on the first main surface 3 side of the second insulating surface 57, and exposes the second insulating surface 57. In other words, the third sidewall insulating film 53 exposes the second oxide film 60 from the second insulating surface 57.

[0206] The third sidewall insulating film 53 is connected to the plurality of sidewall insulating films 24, 25 at the connection portion between the gate electrode 22 and the gate wiring 51. That is, the third sidewall insulating film 53 has a portion connected to the first sidewall insulating film 24 in an L-shape and a portion connected to the second sidewall insulating film 25 in an L-shape.

[0207] The third sidewall insulating film 53 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The third sidewall insulating film 53 may have a single-layer structure made of a single insulating film. The third sidewall insulating film 53 may have a stacked structure including a plurality of insulating films.

[0208] The third sidewall insulating film 53 is preferably made of the same insulating material as the insulating material of the plurality of sidewall insulating films 24, 25. In this embodiment, the third sidewall insulating film 53 has a single-layer structure made of an NSG film. In this embodiment, the third sidewall insulating film 53 is made of a TEOS film, which is an example of an NSG film.

[0209] When the third sidewall insulating film 53 is made of an NSG film, fluctuations in the electrical characteristics of the gate wiring 51 (gate electrode 22) caused by impurity diffusion in the second oxide film 60 (second oxide film 33) are suppressed by the third sidewall insulating film 53. In addition, fluctuations in the insulating characteristics of the second oxide film 60 (second oxide film 33) caused by impurity diffusion in the gate wiring 51 (gate electrode 22) are suppressed by the third sidewall insulating film 53.

[0210] The third sidewall insulating film 53 preferably has a thickness substantially equal to the thicknesses of the plurality of sidewall insulating films 24 and 25. The thickness of the third sidewall insulating film 53 is the horizontal thickness of the third sidewall insulating film 53 with the first wiring sidewall 55 as the reference.

[0211] The third sidewall insulating films 53 each have a thickness that is less than the thickness of the gate wiring 51. The thickness of the third sidewall insulating films 53 is less than the thickness (total thickness) of the second planar insulating film 52. The thickness of the third sidewall insulating films 53 is less than the thickness of the gate electrode 22. The thickness of the third sidewall insulating films 53 is less than the thickness (total thickness) of the first planar insulating film 23.

[0212] The thickness of the third sidewall insulating film 53 is preferably less than the thickness of the second oxide film 60 (second oxide film 33). The thickness of the third sidewall insulating film 53 is preferably less than the thickness of the first oxide film 59 (first oxide film 32). The thickness of the third sidewall insulating film 53 is preferably greater than the thickness of the gate insulating film 21. The thickness of the third sidewall insulating film 53 may be less than the thickness of the gate insulating film 21.

[0213] The thickness of the third sidewall insulating film 53 is preferably approximately equal to the thickness of the sidewall insulating films 24 and 25. The thickness of the third sidewall insulating film 53 may be greater than the thickness of the sidewall insulating films 24 and 25, or may be less than the thickness of the sidewall insulating films 24 and 25. The thickness of the third sidewall insulating film 53 may be 0.1 μm or more and 0.5 μm or less.

[0214] The thickness of the third sidewall insulating film 53 may be a value belonging to at least one of the ranges of 0.1 μm to 0.15 μm, 0.15 μm to 0.2 μm, 0.2 μm to 0.25 μm, 0.25 μm to 0.3 μm, 0.3 μm to 0.35 μm, 0.35 μm to 0.4 μm, 0.4 μm to 0.45 μm, and 0.45 μm to 0.5 μm. The thickness of the third sidewall insulating film 53 is preferably 0.15 μm to 0.25 μm.

[0215] The semiconductor device 1A includes an outer insulating film 61 that covers the main surface insulating film 44 in the peripheral region 9. The outer insulating film 61 is formed in the region between the periphery of the chip 2 and the gate structure 20 (gate wiring 51) in the peripheral region 9, and covers the outer body region 40, the termination region 41, and the plurality of field regions 43 with the main surface insulating film 44 sandwiched therebetween.

[0216] The outer insulating film 61 is continuous with the first to fourth side surfaces 5A to 5D on the peripheral side of the chip 2. The outer insulating film 61 may be formed at an interval inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral portion (second semiconductor region 11) of the first main surface 3. The outer insulating film 61 is connected to the second planar insulating film 52 on the wiring structure 50 side.

[0217] Specifically, the outer insulating film 61, like the second planar insulating film 52, has a laminated structure including a first oxide film 59 and a second oxide film 60, and is formed integrally with the second planar insulating film 52. The outer insulating film 61 may be considered to be an extension portion of the second planar insulating film 52 that is extended from the covering portion for the gate wiring 51 to the peripheral edge side of the chip 2.

[0218] The semiconductor device 1A includes a plurality of source openings 65 that are respectively partitioned in regions between the plurality of gate structures 20 on the active region 8 side. In this embodiment, the plurality of source openings 65 are formed at intervals in the first direction X according to the arrangement of the plurality of gate structures 20, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of source openings 65 are formed in stripes extending in the second direction Y.

[0219] The multiple source openings 65 are each defined in an area surrounded by the multiple gate structures 20 and the wiring structure 50. Specifically, the multiple source openings 65 are each defined in the first direction X by the first sidewall insulating film 24 of one gate structure 20 and the second sidewall insulating film 25 of the other gate structure 20. The multiple source openings 65 have both ends defined in the second direction Y by the third sidewall insulating film 53 of the wiring structure 50.

[0220] The plurality of source openings 65 are defined directly above the plurality of body regions 12, respectively, and penetrate the plurality of gate insulating films 21 and the main surface insulating film 44. That is, the plurality of source openings 65 expose the plurality of gate insulating films 21 and the main surface insulating film 44 at their lower ends. The plurality of source openings 65 each expose a portion of the first main surface 3 (chip 2).

[0221] Specifically, the plurality of source openings 65 expose the plurality of source regions 14, 15 and contact regions 16 formed in the corresponding body regions 12. In this embodiment, the plurality of source openings 65 expose both end portions of the body region 12.

[0222] The multiple source openings 65 each have an opening width W in the first direction X that is equal to or greater than the thickness of the multiple sidewall insulating films 24, 25. The opening width W is also the distance between the multiple gate structures 20. The opening width W is preferably greater than the thickness of the multiple sidewall insulating films 24, 25. The opening width W is preferably equal to or less than the width of the gate electrode 22. It is particularly preferable that the width of the source opening 65 is less than the width of the gate electrode 22.

[0223] The opening width W may be 0.2 μm or more and 0.6 μm or less. The opening width W may have a value belonging to at least one of the ranges of 0.2 μm or more and 0.25 μm or less, 0.25 μm or more and 0.3 μm or less, 0.3 μm or more and 0.35 μm or more and 0.35 μm or more and 0.4 μm or less, 0.4 μm or more and 0.45 μm or less, 0.45 μm or more and 0.5 μm or more and 0.55 μm or less, and 0.55 μm or more and 0.6 μm or less. The opening width W is preferably 0.25 μm or more and 0.45 μm or less.

[0224] The source opening 65 may have an opening depth D of 0.1 μm to 2 μm. The opening depth D may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm. The opening depth D is preferably 0.5 μm to 1 μm.

[0225] The source opening 65 preferably has an aspect ratio D / W of 0.5 to 3. The aspect ratio D / W is defined as the ratio of the opening depth D to the opening width W. The aspect ratio D / W may have a value belonging to at least one of the ranges of 0.5 to 0.75, 0.75 to 1, 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3.

[0226] The semiconductor device 1A includes a plurality of source recesses 66 formed in portions of the first main surface 3 that are exposed from the plurality of source openings 65. The plurality of source recesses 66 may be considered to be components of the first main surface 3. The semiconductor device 1A does not necessarily have to include the source recesses 66. Therefore, a configuration that does not include the source recesses 66 may be adopted.

[0227] The plurality of source recesses 66 each have a planar shape that matches the planar shape of the corresponding source opening 65, and are recessed from the first main surface 3 toward the second main surface 4. The plurality of source recesses 66 are formed at intervals from the bottom of the corresponding body region 12 toward the first main surface 3, and expose the corresponding plurality of source regions 14, 15 and contact regions 16, respectively.

[0228] Specifically, the source recesses 66 are formed at intervals from the bottoms of the corresponding source regions 14, 15 (contact regions 16) toward the first main surface 3. In this embodiment, the source recesses 66 expose both end portions of the body region 12.

[0229] The semiconductor device 1A includes at least one outer opening 67 (a plurality of outer openings 67 in this embodiment) formed in the outer insulating film 61 in the peripheral region 9. The plurality of outer openings 67 are formed in a portion of the outer insulating film 61 that covers the termination region 41.

[0230] The plurality of outer openings 67 penetrate the outer insulating film 61 and expose the termination region 41. In this embodiment, the plurality of outer openings 67 are formed in portions of the outer insulating film 61 that cover the overlap region 42 of the termination region 41, and expose the overlap region 42.

[0231] The outer openings 67 may expose either or both of the outer body region 40 and the end region 41 instead of or in addition to the end region 41 (overlap region 42).

[0232] The outer openings 67 penetrate both the first oxide film 59 and the second oxide film 60, and have wall surfaces defined by both the first oxide film 59 and the second oxide film 60. The outer openings 67 each have an opening end defined by an arc corner portion of the outer insulating film 61.

[0233] The outer openings 67 are spaced apart along the terminal region 41 (overlapping region 42) (see FIGS. 4 and 5). The outer openings 67 may be quadrangular (square), rectangular, hexagonal, circular, or other shapes in plan view. The outer openings 67 may be strip-shaped and extend along the terminal region 41 (overlapping region 42) in plan view. The outer openings 67 may have an aspect ratio of 0.5 to 3 (preferably greater than 1).

[0234] The semiconductor device 1A may have a single outer opening 67. The single outer opening 67 may be formed in a strip shape extending along the termination region 41 (overlap region 42). The single outer opening 67 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0235] The single outer opening 67 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single outer opening 67 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) following the termination region 41 (overlapping region 42) in a plan view (see FIG. 4 ).

[0236] The semiconductor device 1A includes a plurality of outer recesses 68 formed in portions of the first main surface 3 that are exposed from the plurality of outer openings 67. The plurality of outer recesses 68 may be considered to be components of the first main surface 3. The semiconductor device 1A does not necessarily have to have the outer recesses 68. Therefore, a configuration that does not have the outer recesses 68 may be adopted.

[0237] The outer recesses 68 each have a planar shape that matches the planar shape of the corresponding outer opening 67, and are recessed from the first main surface 3 toward the second main surface 4. The outer recesses 68 are formed at intervals from the bottom of the termination region 41 (overlap region 42) toward the first main surface 3, and each exposes the termination region 41 (overlap region 42).

[0238] The outer recess 68 may have a depth approximately equal to the depth of the source recess 66. When a single outer opening 67 is formed, a single outer recess 68 that matches the planar shape of the single outer opening 67 is formed.

[0239] The semiconductor device 1A includes at least one gate opening 69 (in this embodiment, multiple gate openings 69) formed in the second planar insulating film 52 in the peripheral region 9. The multiple gate openings 69 penetrate the second planar insulating film 52 and expose the gate wiring 51. The multiple gate openings 69 are formed at intervals along the gate wiring 51 (see FIGS. 4 and 5 ).

[0240] The plurality of gate openings 69 penetrate both the first oxide film 59 and the second oxide film 60, and have wall surfaces defined by both the first oxide film 59 and the second oxide film 60. The plurality of gate openings 69 may each have an opening end defined by a circular arc corner portion of the second planar insulating film 52.

[0241] The plurality of gate openings 69 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in plan view. The plurality of gate openings 69 may be formed in a strip shape extending along the gate wiring 51 in plan view. The gate openings 69 may have an aspect ratio of 0.5 to 3 (preferably greater than 1).

[0242] The semiconductor device 1A may have a single gate opening 69. The single gate opening 69 may be formed in a strip shape extending along the gate wiring 51. The single gate opening 69 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in plan view.

[0243] The single gate opening 69 may be formed in the shape of an ended or endless polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The single gate opening 69 may have an edge portion that connects a portion extending in the first direction X and a portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in plan view, following the gate wiring 51 (see FIG. 4 ).

[0244] 1 and other figures, the semiconductor device 1A includes a source main electrode 70 disposed on a plurality of gate structures 20. The source main electrode 70 is a terminal electrode to which a source potential is applied from the outside. The source main electrode 70 may also be referred to as a "first main electrode," a "first terminal electrode," a "first pad electrode," or the like.

[0245] The source main electrode 70 collectively covers the plurality of gate structures 20 in the active region 8. The source main electrode 70 covers the plurality of gate electrodes 22 with the plurality of first planar insulating films 23 interposed therebetween, and is electrically isolated from the plurality of gate electrodes 22 by the plurality of first planar insulating films 23.

[0246] The source main electrode 70 has a peripheral portion that covers the wiring structure 50 in a film-like manner. The peripheral portion of the source main electrode 70 covers the gate wiring 51 with the second planar insulating film 52 sandwiched therebetween, and is electrically separated from the gate wiring 51 by the second planar insulating film 52. The source main electrode 70 extends into the multiple source openings 65 from above the multiple gate structures 20 and the wiring structure 50.

[0247] The source main electrode 70 is mechanically connected to the plurality of first sidewall insulating films 24, the plurality of second sidewall insulating films 25, and the plurality of third sidewall insulating films 53 in the plurality of source openings 65, and is electrically connected to the first major surface 3 in the plurality of source openings 65. Specifically, the source main electrode 70 is electrically connected to the plurality of body regions 12, the plurality of source regions 14 and 15, the plurality of contact regions 16, etc. in the plurality of source openings 65.

[0248] The source main electrode 70 includes a first pad portion 70 a, a second pad portion 70 b, and a third pad portion 70 c in plan view. The first pad portion 70 a has a relatively large planar area and forms the main body of the source main electrode 70.

[0249] In this embodiment, the first pad portion 70a is located closer to the fourth side surface 5D than the center of the active region 8 in a plan view, and is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2. The first pad portion 70a is electrically isolated from the gate electrodes 22 by the first planar insulating films 23, and is electrically connected to the body regions 12 and the like via the source openings 65.

[0250] The second pad portion 70b has a plane area smaller than that of the first pad portion 70a, and extends in a strip shape (rectangular shape) from one end of the first pad portion 70a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The second pad portion 70b is electrically isolated from the gate electrodes 22 by the first planar insulating films 23, and is electrically connected to the body regions 12 and the like via the source openings 65.

[0251] The third pad portion 70c has a plane area smaller than that of the first pad portion 70a, and is drawn out in a strip shape (quadrilateral shape) from the other end of the first pad portion 70a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 70b in the second direction Y. The third pad portion 70c is electrically isolated from the plurality of gate electrodes 22 by the plurality of first planar insulating films 23, and is electrically connected to the plurality of body regions 12 etc. via the plurality of source openings 65.

[0252] The planar area of ​​the third pad portion 70c may be approximately equal to the planar area of ​​the second pad portion 70b. The planar area of ​​the third pad portion 70c may be larger than the planar area of ​​the second pad portion 70b, or may be smaller than the planar area of ​​the second pad portion 70b. Either or both of the second pad portion 70b and the third pad portion 70c may be used as a terminal portion for monitoring current.

[0253] The source main electrode 70 does not necessarily have to have both the second pad portion 70b and the third pad portion 70c at the same time. The source main electrode 70 may have only one of the second pad portion 70b and the third pad portion 70c. The source main electrode 70 may be composed of only the first pad portion 70a, and may not have the second pad portion 70b or the third pad portion 70c.

[0254] 6 and 7, the source main electrode 70 includes a first lower electrode film 71, a plurality of first buried electrodes 72, and a first upper electrode film 73. The first lower electrode film 71 may be referred to as a "first lower electrode."

[0255] The first upper electrode film 73 may be referred to as a “first upper electrode.” The first lower electrode film 71 forms a lower layer of the source main electrode 70 (the first pad portion 70 a, the second pad portion 70 b, and the third pad portion 70 c), and collectively covers the multiple gate structures 20 in the active region 8 in the form of a film.

[0256] In this embodiment, the first lower electrode film 71 has a layered structure including a first electrode film 74 layered on the plurality of gate structures 20 and a second electrode film 75 layered on the first electrode film 74. In this embodiment, the first electrode film 74 includes a Ti film, and the second electrode film 75 includes a TiN film. The first lower electrode film 71 does not necessarily have to have a layered structure, and may have a single-layer structure including either the first electrode film 74 (Ti film) or the second electrode film 75 (TiN film).

[0257] The first electrode film 74 directly covers the plurality of gate structures 20 collectively in a film form in the active region 8. The first electrode film 74 covers the plurality of gate electrodes 22 with a plurality of first planar insulating films 23 in between, and is electrically isolated from the plurality of gate electrodes 22 by the plurality of first planar insulating films 23. The first electrode film 74 has a peripheral portion that directly covers the wiring structure 50 in a film form. The peripheral portion of the first electrode film 74 covers the gate wiring 51 with a second planar insulating film 52 in between, and is electrically isolated from the gate wiring 51 by the second planar insulating film 52.

[0258] The first electrode film 74 has a portion that directly covers the first insulating surface 29 and the second insulating surface 57 in a film-like manner, and extends into the multiple source openings 65 from above the first insulating surface 29 and the second insulating surface 57. The first electrode film 74 directly covers the first main surface 3, the multiple first sidewall insulating films 24, the multiple second sidewall insulating films 25, and the multiple third sidewall insulating films 53 in a film-like manner within the multiple source openings 65. The configuration of the first electrode film 74 within one source opening 65 will be described below.

[0259] The first electrode film 74 extends along the sidewall insulating films 24, 25 and faces the gate electrodes 22 and the first planar insulating films 23 with the sidewall insulating films 24, 25 interposed therebetween. In this embodiment, the first electrode film 74 faces the first oxide film 32 and the second oxide film 33 with the sidewall insulating films 24, 25 interposed therebetween.

[0260] It is preferable that the first electrode film 74 extends at an inclination angle substantially equal to the inclination angle of the sidewall insulating films 24, 25 in the covering portion relative to the sidewall insulating films 24, 25, and has a film surface extending substantially parallel to the sidewall insulating films 24, 25. The first electrode film 74 extends along the third sidewall insulating film 53, and faces the gate wiring 51 and the second planar insulating film 52 with the third sidewall insulating film 53 interposed therebetween.

[0261] In this embodiment, the first electrode film 74 faces the first oxide film 59 and the second oxide film 60 with the third sidewall insulating film 53 interposed therebetween. The first electrode film 74 preferably has a film surface that extends at an inclination angle substantially equal to the inclination angle of the third sidewall insulating film 53 in the covering portion with respect to the third sidewall insulating film 53 and extends substantially parallel to the third sidewall insulating film 53.

[0262] The first electrode film 74 covers the first main surface 3 in a film-like manner at the bottom of the source opening 65, and is electrically connected to the first main surface 3. Specifically, the first electrode film 74 has a portion that covers the source recess 66 in a film-like manner at the bottom of the source opening 65, and is electrically connected to the body region 12, the plurality of source regions 14 and 15, and the contact region 16.

[0263] The first electrode film 74 may cover the source recess 66 in a film-like manner at a distance from the height position of the first main surface 3 toward the bottom of the source recess 66. The first electrode film 74 may have a portion located on the bottom side of the source recess 66 relative to the height position of the first main surface 3, and a portion located on the gate insulating film 21 side relative to the height position of the first main surface 3.

[0264] The first electrode film 74 has a thickness less than the thickness of the gate electrode 22 (gate wiring 51). The thickness of the first electrode film 74 is less than the thickness (total thickness) of the first planar insulating film 23 (second planar insulating film 52). The thickness of the first electrode film 74 may be less than the thickness of the second oxide film 33 (second oxide film 60). The thickness of the first electrode film 74 may be less than the thickness of the first oxide film 32 (first oxide film 59).

[0265] The thickness of the first electrode film 74 may be less than the thickness of the sidewall insulating films 24, 25. The thickness of the first electrode film 74 may be greater than the thickness of the sidewall insulating films 24, 25. The thickness of the first electrode film 74 is preferably greater than the thickness of the gate insulating film 21. The thickness of the first electrode film 74 may be less than the thickness of the gate insulating film 21.

[0266] The thickness of the first electrode film 74 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 74 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or more and 100 nm or less.

[0267] The second electrode film 75 collectively covers the plurality of gate structures 20 in the active region 8, sandwiching the first electrode film 74 therebetween. The second electrode film 75 covers the plurality of first planar insulating films 23 in a film-like manner, sandwiching the first electrode film 74 therebetween. The second electrode film 75 has a peripheral portion that covers the wiring structure 50 in a film-like manner, sandwiching the first electrode film 74 therebetween. The peripheral portion of the second electrode film 75 covers the second planar insulating film 52 (gate wiring 51) with the peripheral portion of the first electrode film 74 sandwiched therebetween.

[0268] The second electrode film 75 has a portion that covers the first insulating surface 29 and the second insulating surface 57 in a film-like manner, sandwiching the first electrode film 74 therebetween, and extends from above the first insulating surface 29 and the second insulating surface 57 into the multiple source openings 65.

[0269] The second electrode film 75 covers the first main surface 3, the plurality of first sidewall insulating films 24, the plurality of second sidewall insulating films 25, and the plurality of third sidewall insulating films 53 in a film-like manner, with the first electrode film 74 sandwiched between them, within the plurality of source openings 65. The configuration of the second electrode film 75 within one source opening 65 will be described below.

[0270] The second electrode film 75 extends along the first electrode film 74 in the portion covering the sidewall insulating films 24, 25, and faces the gate electrodes 22 and the first planar insulating films 23, with the sidewall insulating films 24, 25 and the first electrode film 74 interposed therebetween. In this embodiment, the second electrode film 75 faces the first oxide film 32 and the second oxide film 33, with the sidewall insulating films 24, 25 and the first electrode film 74 interposed therebetween.

[0271] The second electrode film 75 extends along the first electrode film 74 in the portion covering the third sidewall insulating film 53, and faces the gate wiring 51 and the second planar insulating film 52 with the third sidewall insulating film 53 and the first electrode film 74 interposed therebetween. In this embodiment, the second electrode film 75 faces the first oxide film 59 and the second oxide film 60 with the third sidewall insulating film 53 and the first electrode film 74 interposed therebetween.

[0272] It is preferable that the second electrode film 75 has a film surface that extends at an inclination angle substantially equal to the inclination angle of the sidewall insulating films 24, 25 in a covering portion thereof relative to the sidewall insulating films 24, 25, and that extends substantially parallel to the sidewall insulating films 24, 25. It is preferable that the second electrode film 75 has a film surface that extends at an inclination angle substantially equal to the inclination angle of the third sidewall insulating film 53 in a covering portion thereof relative to the third sidewall insulating film 53, and that extends substantially parallel to the third sidewall insulating film 53.

[0273] The second electrode film 75 covers the first main surface 3 in a film state at the bottom of the source opening 65, sandwiching the first electrode film 74 therebetween, and is electrically connected to the first main surface 3 via the first electrode film 74. Specifically, the second electrode film 75 has a portion that covers the source recess 66 in a film state, sandwiching the first electrode film 74 therebetween, and is electrically connected to the body region 12, the plurality of source regions 14 and 15, and the contact region 16 via the first electrode film 74.

[0274] When the first electrode film 74 is located on the bottom side of the source recess 66 relative to the first main surface 3, the second electrode film 75 may have a portion located within the source recess 66. When the first electrode film 74 has a portion located above the first main surface 3, the entire second electrode film 75 is located above the source recess 66.

[0275] The second electrode film 75 has a thickness less than the thickness of the gate electrode 22 (gate wiring 51). The thickness of the second electrode film 75 is less than the thickness (total thickness) of the second planar insulating film 52 (first planar insulating film 23). The thickness of the second electrode film 75 may be less than the thickness of the second oxide film 33 (second oxide film 60). The thickness of the second electrode film 75 may be less than the thickness of the first oxide film 32 (first oxide film 59).

[0276] The thickness of the second electrode film 75 may be less than the thickness of the sidewall insulating films 24, 25. The thickness of the second electrode film 75 may be greater than the thickness of the sidewall insulating films 24, 25. The thickness of the second electrode film 75 is preferably greater than the thickness of the gate insulating film 21. The thickness of the second electrode film 75 may be less than the thickness of the gate insulating film 21. The thickness of the second electrode film 75 is preferably greater than the thickness of the first electrode film 74. The thickness of the second electrode film 75 may be less than the thickness of the first electrode film 74.

[0277] The thickness of the second electrode film 75 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 75 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0278] The multiple first buried electrodes 72 form the middle layer of the source main electrode 70 (the first pad portion 70a, the second pad portion 70b, and the third pad portion 70c) and are buried in the multiple source openings 65, respectively. The first buried electrodes 72 contain a conductive material different from the conductive material of the first lower electrode film 71. The first buried electrodes 72 contain at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. In this embodiment, the first buried electrodes 72 contain tungsten.

[0279] In this embodiment, the multiple first buried electrodes 72 are buried in one-to-one correspondence with the multiple source openings 65 via a single first lower electrode film 71. The multiple first buried electrodes 72 are electrically connected to the first main surface 3 (chip 2) via the first lower electrode film 71 within the multiple source openings 65. Specifically, the multiple first buried electrodes 72 are electrically connected to the multiple body regions 12, the multiple source regions 14 and 15, and the contact region 16. The configuration of one first buried electrode 72 will be described below.

[0280] The first buried electrode 72 is buried in the source opening 65 at a distance from the first insulating surface 29 and the second insulating surface 57 toward the first main surface 3, and exposes a portion of the first lower electrode film 71 (second electrode film 75) that covers the first insulating surface 29 and the second insulating surface 57. In other words, the first buried electrode 72 does not have a portion that faces the electrode surface 26 of the gate electrode 22 across the first insulating surface 29. Furthermore, the first buried electrode 72 does not have a portion that faces the wiring surface 54 of the gate wiring 51 across the second insulating surface 57.

[0281] The first buried electrode 72 faces the plurality of gate electrodes 22 and the plurality of first planar insulating films 23 in the horizontal direction, with the plurality of sidewall insulating films 24, 25 interposed therebetween. In this embodiment, the first buried electrode 72 faces the first oxide film 32 and the second oxide film 33 in the horizontal direction, with the plurality of sidewall insulating films 24, 25 interposed therebetween.

[0282] The first buried electrode 72 faces the gate wiring 51 and the second planar insulating film 52 in the horizontal direction, with the third sidewall insulating film 53 sandwiched therebetween. In this embodiment, the first buried electrode 72 faces the first oxide film 59 and the second oxide film 60 in the horizontal direction, with the plurality of sidewall insulating films 24, 25 sandwiched therebetween. The first buried electrode 72 faces the plurality of source regions 14, 15 and contact regions 16 in the stacking direction, with the first lower electrode film 71 sandwiched therebetween, and is electrically connected to the plurality of source regions 14, 15 and contact regions 16 via the first lower electrode film 71.

[0283] When the first lower electrode film 71 is located on the bottom side of the source recess 66 relative to the first main surface 3, the first buried electrode 72 may have a portion located within the source recess 66. When the first lower electrode film 71 has a portion located above the first main surface 3, the entire first buried electrode 72 is located above the source recess 66.

[0284] The first buried electrode 72 has a first buried electrode surface 76 exposed from the source opening 65. The first buried electrode surface 76 is located closer to the first insulating surface 29 than the height position of the electrode surface 26 of the gate electrode 22.

[0285] The first buried electrode 72 is preferably located closer to the first insulating surface 29 than the height position of the first oxide film 32. The first buried electrode surface 76 is located closer to the second insulating surface 57 than the height position of the wiring surface 54 of the gate wiring 51. The first buried electrode 72 is preferably located closer to the second insulating surface 57 than the height position of the first oxide film 59.

[0286] The first buried electrode surface 76 has a recess in the center that is recessed toward the first main surface 3 (chip 2). The bottom of the recess is preferably located on the first insulating surface 29 (second insulating surface 57) side relative to the height position of the electrode surface 26 (wiring surface 54).

[0287] The bottom of the recess is preferably located closer to the first insulating surface 29 than the height of the first oxide film 32 (first oxide film 59). The bottom of the recess may be located closer to the first main surface 3 than the height of the first oxide film 32 (first oxide film 59). The bottom of the recess may also be located closer to the first main surface 3 than the height of the electrode surface 26 (wiring surface 54).

[0288] The first upper electrode film 73 forms the upper layer of the source main electrode 70 (first pad portion 70a, second pad portion 70b and third pad portion 70c) and covers the first lower electrode film 71 and the multiple first buried electrodes 72 in a film-like manner.

[0289] The first upper electrode film 73 includes a conductive material different from the conductive material of the first lower electrode film 71 and the conductive material of the first buried electrode 72. The first upper electrode film 73 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The first upper electrode film 73 may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0290] The first upper electrode film 73 collectively covers the plurality of gate structures 20 in the active region 8, sandwiching the first lower electrode film 71 therebetween. The first upper electrode film 73 is mechanically and electrically connected to the first lower electrode film 71 in the portions covering the first insulating surface 29 and the second insulating surface 57.

[0291] Specifically, the first upper electrode film 73 covers the plurality of first planar insulating films 23 in a film-like manner, sandwiching the first lower electrode film 71. The first upper electrode film 73 has a peripheral portion that covers the wiring structure 50 in a film-like manner, sandwiching the first lower electrode film 71. The peripheral portion of the first upper electrode film 73 covers the second planar insulating film 52 (gate wiring 51) with the peripheral portion of the first lower electrode film 71 sandwiched therebetween.

[0292] The first upper electrode film 73 is mechanically and electrically connected to the plurality of first buried electrodes 72 in the portions covering the plurality of source openings 65. As a result, the first upper electrode film 73 is electrically connected to the plurality of body regions 12, the plurality of source regions 14, 15, contact region 16, etc. via both the first lower electrode film 71 and the plurality of first buried electrodes 72.

[0293] The first upper electrode film 73 is connected to the first buried electrode 72 (first buried electrode surface 76) at a height position closer to the first main surface 3 than the height positions of the first insulating surface 29 and the second insulating surface 57, and faces the first planar insulating film 23 in the horizontal direction with a plurality of sidewall insulating films 24, 25 interposed therebetween. The first upper electrode film 73 also faces the second planar insulating film 52 in the horizontal direction with the third sidewall insulating film 53 interposed therebetween.

[0294] The first upper electrode film 73 backfills the recess in the first buried electrode surface 76 in the covering portion for the first buried electrode 72. In this form, the first upper electrode film 73 is connected to the first buried electrode surface 76 above the electrode surface 26, and does not have a portion facing the gate electrode 22 in the horizontal direction.

[0295] In this embodiment, the first upper electrode film 73 is connected to the first buried electrode surface 76 at a position higher than the height of the first oxide film 32. When the first buried electrode surface 76 has a portion located lower than the height of the electrode surface 26, the first upper electrode film 73 may have a portion facing the gate electrode 22 in the horizontal direction.

[0296] The first upper electrode film 73 has a thickness greater than the thickness (total thickness) of the first lower electrode film 71. The thickness of the first upper electrode film 73 is greater than both the thickness of the gate electrode 22 and the thickness of the gate wiring 51. The thickness of the first upper electrode film 73 is greater than the thickness of the first buried electrode 72. The thickness of the first upper electrode film 73 is greater than both the thickness of the first planar insulating film 23 and the thickness of the second planar insulating film 52.

[0297] The thickness of the first upper electrode film 73 may be 0.5 μm or more and 5 μm or less. The thickness of the first upper electrode film 73 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0298] The semiconductor device 1A includes source finger electrodes 80 extending from the source main electrode 70 onto the peripheral region 9. The source finger electrodes 80 transmit the source potential applied to the source main electrode 70 to the peripheral region 9. In this embodiment, the source finger electrodes 80 extend onto the peripheral region 9 from a portion of the source main electrode 70 (first pad portion 70a) on the fourth side surface 5D side.

[0299] The source finger electrodes 80 are drawn out from the source main electrode 70 onto the outer insulating film 61 via the wiring structure 50. The source finger electrodes 80 are drawn out to a region of the outer insulating film 61 in which a plurality of outer openings 67 are formed, and are electrically connected to the termination region 41 within the plurality of outer openings 67. Specifically, the source finger electrodes 80 are electrically connected to the overlap region 42 of the termination region 41 via the plurality of outer openings 67.

[0300] The source finger electrodes 80 extend in a strip shape along the termination region 41 (overlapping region 42). The source finger electrodes 80 have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.

[0301] In this embodiment, the source finger electrode 80 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source main electrode 70. The source finger electrode 80 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ).

[0302] Like the source main electrode 70, the source finger electrode 80 includes a first lower electrode film 71, a plurality of first buried electrodes 72, and a first upper electrode film 73. Like the source main electrode 70, the first lower electrode film 71 has a laminated structure including a first electrode film 74 and a second electrode film 75. The first lower electrode film 71 forms a lower layer portion of the source finger electrode 80, and covers the outer insulating film 61 in the peripheral region 9.

[0303] The first lower electrode film 71 covers the entire region of the outer insulating film 61 where the multiple outer openings 67 are formed, and extends from above the first insulating surface 29 into the multiple outer openings 67 .

[0304] The first lower electrode film 71 covers the first main surface 3 in a film-like manner at the bottom of each outer opening 67, and is electrically connected to the first main surface 3 (chip 2). Specifically, the first lower electrode film 71 has a portion that covers the outer recess 68 in a film-like manner at the bottom of each outer opening 67, and is electrically connected to the termination region 41 (overlap region 42) within the outer recess 68.

[0305] The first lower electrode film 71 may cover the outer recess 68 in a film-like manner at a distance from the height position of the first main surface 3 toward the bottom of the outer recess 68. The first lower electrode film 71 may have a portion located on the bottom side of the outer recess 68 relative to the height position of the first main surface 3, and a portion located on the main surface insulating film 44 side relative to the height position of the first main surface 3.

[0306] The multiple first buried electrodes 72 form middle layers of the source finger electrodes 80 and are buried in the multiple outer openings 67. In this embodiment, the multiple first buried electrodes 72 are buried in the multiple outer openings 67 in a one-to-one correspondence via a single first lower electrode film 71. The multiple first buried electrodes 72 are electrically connected to the termination region 41 (overlap region 42) via the first lower electrode film 71.

[0307] The first buried electrode 72 is buried in the outer opening 67 at a distance from the insulating surface of the outer insulating film 61 toward the first main surface 3, and exposes a portion of the first lower electrode film 71 (second electrode film 75) that covers the insulating surface of the outer insulating film 61. The first buried electrode 72 faces the first oxide film 59 and the second oxide film 60 in the horizontal direction, with the first lower electrode film 71 in between. The first buried electrode 72 faces the termination region 41 (overlap region 42) in the stacking direction, with the first lower electrode film 71 in between.

[0308] The first buried electrode 72 has a first buried electrode surface 76 exposed from the outer opening 67. The first buried electrode surface 76 is located closer to the insulating surface of the outer insulating film 61 than the height position of the first oxide film 59 in the outer opening 67. The first buried electrode surface 76 may be located closer to the first main surface 3 than the height position of the first oxide film 59.

[0309] When the first lower electrode film 71 is located closer to the bottom of the outer recess 68 than the first main surface 3, the first buried electrode 72 may have a portion located within the outer recess 68. When the first lower electrode film 71 has a portion located above the first main surface 3, the entire first buried electrode 72 is located above the outer recess 68.

[0310] The first upper electrode film 73 forms an upper layer portion of the source finger electrode 80 and covers the first lower electrode film 71 and the plurality of first buried electrodes 72 in a film-like manner. The first upper electrode film 73 is mechanically and electrically connected to the first lower electrode film 71 in a portion covering the insulating surface of the outer insulating film 61, and is mechanically and electrically connected to the plurality of first buried electrodes 72 in a portion covering the plurality of outer openings 67. The first upper electrode film 73 is electrically connected to the termination region 41 (overlap region 42) via the first lower electrode film 71 and the plurality of first buried electrodes 72.

[0311] The first upper electrode film 73 is connected to the first buried electrode surface 76 at a height position closer to the first main surface 3 than the height position of the insulating surface of the outer insulating film 61. The first upper electrode film 73 is connected to the first buried electrode surface 76 above the height position of the first oxide film 59. When the first buried electrode 72 is buried below the height position of the first oxide film 59, the first upper electrode film 73 may be connected to the first buried electrode surface 76 below the height position of the first oxide film 59.

[0312] The semiconductor device 1A includes a plurality of first silicide portions 81 formed on the surface portions of the first main surface 3 that are exposed from the plurality of source openings 65. The first silicide portions 81 may include at least one of titanium silicide, nickel silicide, cobalt silicide, molybdenum silicide, tungsten silicide, and vanadium silicide. The first silicide portions 81 are preferably made of titanium silicide, nickel silicide, or cobalt silicide.

[0313] In this embodiment, the multiple first silicide portions 81 are formed in the form of a film along the wall surfaces (side walls and bottom walls) of the multiple source recesses 66 in the surface layer portions of the multiple body regions 12, and are mechanically and electrically connected to the source main electrode 70.

[0314] The plurality of first silicide portions 81 are formed at intervals from the bottoms of the plurality of source regions 14, 15 and the bottoms of the plurality of contact regions 16 toward the first main surface 3. The plurality of first silicide portions 81 electrically connect the source main electrode 70 to the plurality of body regions 12, the plurality of source regions 14, 15, and the plurality of contact regions 16.

[0315] The semiconductor device 1A includes a plurality of second silicide portions 82 formed on the surface portions of the first main surface 3 that are exposed from the plurality of outer openings 67. The second silicide portions 82 may include at least one of titanium silicide, nickel silicide, cobalt silicide, molybdenum silicide, tungsten silicide, and vanadium silicide. The second silicide portions 82 are preferably made of titanium silicide, nickel silicide, or cobalt silicide. It is particularly preferable that the second silicide portions 82 are made of the same type of silicide as the first silicide portions 81.

[0316] In this embodiment, the multiple second silicide portions 82 are formed in the form of a film along the wall surfaces (side walls and bottom walls) of the multiple outer recesses 68 in the surface layer portion of the termination region 41 (overlap region 42), and are mechanically and electrically connected to the source finger electrodes 80.

[0317] The second silicide portions 82 are formed at intervals from the bottom of the termination region 41 (overlap region 42) toward the first main surface 3. In other words, the second silicide portions 82 electrically connect the source finger electrodes 80 to the termination region 41 (overlap region 42).

[0318] The semiconductor device 1A includes a gate finger electrode 83 selectively routed on the peripheral region 9. The gate finger electrode 83 is provided in a region between the source main electrode 70 and the source finger electrode 80, and is arranged on the wiring structure 50 at a distance from the source main electrode 70 and the source finger electrode 80.

[0319] The gate finger electrode 83 extends in a strip shape along the wiring structure 50. The gate finger electrode 83 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view. In this embodiment, the gate finger electrode 83 is formed in a polygonal ring shape (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source main electrode 70. The gate finger electrode 83 has a pair of open ends on the fourth side surface 5D side through which the source finger electrode 80 passes.

[0320] The gate finger electrode 83 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4 ). The gate finger electrode 83 enters the multiple gate openings 69 from above the second planar insulating film 52 and is electrically connected to the gate wiring 51.

[0321] The gate finger electrode 83 has a width smaller than the width of the gate wiring 51 , and is disposed on the gate wiring 51 at a distance from the first wiring sidewall 55 and the second wiring sidewall 56 of the gate wiring 51 .

[0322] That is, the gate finger electrode 83 is formed at a distance from the third sidewall insulating film 53 toward the peripheral edge of the chip 2. The width of the gate wiring 51 may be greater than the width of the gate wiring 51. In this case, the gate finger electrode 83 may have a portion that is drawn out closer to the peripheral edge of the chip 2 than the second wiring sidewall 56 of the gate wiring 51.

[0323] 8 and 9 , the gate finger electrode 83 includes a second lower electrode film 84, at least one (in this embodiment, multiple) second buried electrodes 85, and a second upper electrode film 86. The second lower electrode film 84 may be referred to as a "second lower electrode." The second upper electrode film 86 may be referred to as a "second upper electrode." The second lower electrode film 84 forms a lower layer of the gate finger electrode 83 and covers the wiring structure 50 in the peripheral region 9 in a film-like manner.

[0324] In this embodiment, the second lower electrode film 84 has a layered structure including a first electrode film 87 layered on the wiring structure 50 and a second electrode film 88 layered on the first electrode film 87. In this embodiment, the first electrode film 87 includes a Ti film, and the second electrode film 88 includes a TiN film. The second lower electrode film 84 does not necessarily have to have a layered structure, and may have a single-layer structure including either the first electrode film 87 (Ti film) or the second electrode film 88 (TiN film).

[0325] The first electrode film 87 directly covers the wiring structure 50 in the peripheral region 9 in a film-like manner. The first electrode film 87 has a portion that directly covers the second insulating surface 57 of the second planar insulating film 52 in a film-like manner, and extends into the multiple gate openings 69 from above the second insulating surface 57. The first electrode film 87 extends in a film-like manner along the wall surfaces of the multiple gate openings 69, and directly covers the first oxide film 59 and the second oxide film 60. The first electrode film 87 covers the wiring surface 54 in a film-like manner, and is electrically connected to the gate wiring 51.

[0326] The first electrode film 87 has a thickness less than the thickness of the gate wiring 51 (gate electrode 22). The thickness of the first electrode film 87 is less than the thickness (total thickness) of the second planar insulating film 52 (first planar insulating film 23). The thickness of the first electrode film 87 may be less than the thickness of the second oxide film 60 (second oxide film 33). The thickness of the first electrode film 87 may be less than the thickness of the first oxide film 59 (first oxide film 32).

[0327] The thickness of the first electrode film 87 may be less than the thickness of the sidewall insulating films 24, 25. The thickness of the first electrode film 87 may be greater than the thickness of the sidewall insulating films 24, 25. The thickness of the first electrode film 87 is preferably greater than the thickness of the gate insulating film 21. The thickness of the first electrode film 87 may be less than the thickness of the gate insulating film 21. The thickness of the first electrode film 87 is preferably approximately equal to the thickness of the first electrode film 74 on the source side.

[0328] The thickness of the first electrode film 87 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 87 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or more and 100 nm or less.

[0329] The second electrode film 88 covers the wiring structure 50 in a film-like manner, sandwiching the first electrode film 87 in the peripheral region 9. The second electrode film 88 has a portion that covers the second insulating surface 57 of the second planar insulating film 52 in a film-like manner, sandwiching the first electrode film 87, and extends into the multiple gate openings 69 from above the second insulating surface 57.

[0330] The second electrode film 88 extends in a film-like manner along the wall surfaces of the plurality of gate openings 69, and covers the first oxide film 59 and the second oxide film 60 with the first electrode film 87 in between. The second electrode film 88 covers the wiring surface 54 in a film-like manner with the first electrode film 87 in between, and is electrically connected to the gate wiring 51 via the first electrode film 87.

[0331] The second electrode film 88 has a thickness less than the thickness of the gate electrode 22 (gate wiring 51). The thickness of the second electrode film 88 is less than the thickness (total thickness) of the second planar insulating film 52 (first planar insulating film 23). The thickness of the second electrode film 88 may be less than the thickness of the second oxide film 33 (second oxide film 60). The thickness of the second electrode film 88 may be less than the thickness of the first oxide film 32 (first oxide film 59).

[0332] The thickness of the second electrode film 88 may be less than the thickness of the sidewall insulating films 24, 25. The thickness of the second electrode film 88 may be greater than the thickness of the sidewall insulating films 24, 25. The thickness of the second electrode film 88 is preferably greater than the thickness of the gate insulating film 21. The thickness of the second electrode film 88 may be less than the thickness of the gate insulating film 21.

[0333] The thickness of the second electrode film 88 is preferably greater than the thickness of the first electrode film 87. The thickness of the second electrode film 88 may be less than the thickness of the first electrode film 87. The thickness of the second electrode film 88 is preferably approximately equal to the thickness of the second electrode film 75 on the source side.

[0334] The thickness of the second electrode film 88 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 75 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0335] The second buried electrodes 85 form middle layers of the gate finger electrode 83, and are buried in the gate openings 69. The second buried electrodes 85 contain a conductive material different from the conductive material of the second lower electrode film 84.

[0336] The second buried electrode 85 includes at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. The second buried electrode 85 preferably includes the same conductive material as the conductive material of the first buried electrode 72 on the source side. In this embodiment, the second buried electrode 85 includes tungsten.

[0337] In this embodiment, the second buried electrodes 85 are buried in one-to-one correspondence with the gate openings 69 via a single second lower electrode film 84. The second buried electrodes 85 are electrically connected to the gate wiring 51 within the gate openings 69 via the second lower electrode film 84.

[0338] The second buried electrode 85 is buried in the gate opening 69 at a distance from the second insulating surface 57 of the second planar insulating film 52 toward the gate wiring 51, and exposes a portion of the second lower electrode film 84 (second electrode film 88) that covers the second insulating surface 57. In other words, the second buried electrode 85 does not have a portion that faces the wiring surface 54 of the gate wiring 51 across the second planar insulating film 52 in the stacking direction (vertical direction Z).

[0339] The second buried electrode 85 covers the second planar insulating film 52 with the second lower electrode film 84 sandwiched therebetween. In this embodiment, the second buried electrode 85 covers the first oxide film 59 and the second oxide film 60 with the second lower electrode film 84 sandwiched therebetween.

[0340] The second buried electrode 85 has a second buried electrode surface 89 exposed from the gate opening 69. The second buried electrode surface 89 is located closer to the first insulating surface 29 than the second insulating surface 57. The second buried electrode surface 89 has a recess in its center that is recessed toward the first main surface 3 (chip 2). The bottom of the recess is preferably located closer to the second insulating surface 57 than the height position of the first oxide film 59. The bottom of the recess may also be located closer to the gate wiring 51 than the height position of the first oxide film 59.

[0341] The second upper electrode film 86 forms an upper layer of the gate finger electrode 83, and covers the second lower electrode film 84 and the plurality of second buried electrodes 85 in a film-like manner. The second upper electrode film 86 contains a conductive material different from the conductive material of the second lower electrode film 84 and the conductive material of the second buried electrodes 85.

[0342] The second upper electrode film 86 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The second upper electrode film 86 may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The second upper electrode film 86 preferably includes the same type of conductive material as the conductive material of the first upper electrode film 73 on the source side.

[0343] The second upper electrode film 86 is mechanically and electrically connected to the second lower electrode film 84 in a portion covering the second insulating surface 57, and is mechanically and electrically connected to the plurality of second buried electrodes 85 in portions covering the plurality of gate openings 69. As a result, the second upper electrode film 86 is electrically connected to the gate wiring 51 via the second lower electrode film 84 and the plurality of second buried electrodes 85.

[0344] The second upper electrode film 86 is connected to the second buried electrode 85 (second buried electrode surface 89) at a height position closer to the gate wiring 51 than the height position of the second insulating surface 57. The second upper electrode film 86 is connected to the second buried electrode surface 89 above the height position of the first oxide film 59.

[0345] The second upper electrode film 86 backfills the recess in the second buried electrode surface 89 in the covering portion for the second buried electrode 85. When the second buried electrode 85 is buried below the height position of the first oxide film 59, the second upper electrode film 86 may be connected to the second buried electrode surface 89 below the height position of the first oxide film 59.

[0346] The second upper electrode film 86 has a thickness greater than the thickness (total thickness) of the second lower electrode film 84. The thickness of the second upper electrode film 86 is greater than the thickness of the gate wiring 51. The thickness of the second upper electrode film 86 is greater than the thickness of the second buried electrode 85. The thickness of the second upper electrode film 86 is greater than both the thickness of the first planar insulating film 23 and the thickness of the second planar insulating film 52. It is preferable that the thickness of the second upper electrode film 86 is approximately equal to the thickness of the first upper electrode film 73 on the source side.

[0347] The thickness of the second upper electrode film 86 may be 0.5 μm or more and 5 μm or less. The thickness of the second upper electrode film 86 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0348] The semiconductor device 1A includes a main gate electrode 90 disposed on the plurality of gate structures 20. The main gate electrode 90 is a terminal electrode to which a gate potential is applied from the outside. The main gate electrode 90 may also be referred to as a "second main electrode," a "second pad electrode," a "second terminal electrode," or the like. The main gate electrode 90 is disposed in a region between the main source electrode 70 and the source finger electrodes 80 and spaced apart from the main source electrode 70 and the source finger electrodes 80.

[0349] In this embodiment, the main gate electrode 90 is disposed in a region on the third side surface 5C side of the first pad portion 70a, and is sandwiched between the second pad portion 70b and the third pad portion 70c. That is, the main gate electrode 90 faces the first pad portion 70a in the first direction X, and faces the second pad portion 70b and the third pad portion 70c in the second direction Y.

[0350] The main gate electrode 90 is formed in a polygonal shape (a quadrilateral shape in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view. The main gate electrode 90 has a plane area smaller than that of the main source electrode 70 (first pad portion 70a). The main gate electrode 90 may have a plane area smaller than that of the second pad portion 70b (third pad portion 70c).

[0351] The main gate electrode 90 is disposed on a portion covering the active region 8 and the peripheral region 9, and is connected to the gate finger electrode 83. The main gate electrode 90 is disposed on an insulating region in the active region 8 where the plurality of first planar insulating films 23 are integrated, and is electrically isolated from the plurality of body regions 12, the plurality of source regions 14, 15, and the plurality of contact regions 16. The main gate electrode 90 may cover the gate wiring 51 in the peripheral region 9 with the second planar insulating film 52 sandwiched therebetween.

[0352] Like the gate finger electrode 83, the gate main electrode 90 includes a second lower electrode film 84 and a second upper electrode film 86. Like the gate finger electrode 83, the second lower electrode film 84 has a layered structure including a first electrode film 74 and a second electrode film 75. The second lower electrode film 84 forms a lower layer of the gate main electrode 90 and covers the insulating region in a film-like manner. The second upper electrode film 86 forms an upper layer of the gate main electrode 90 and covers the second lower electrode film 84 in a film-like manner.

[0353] Although not specifically shown in the drawings, the main gate electrode 90 may have a plurality of second buried electrodes 85, similar to the gate finger electrodes 83. In this case, the main gate electrode 90 may be electrically connected to the gate wiring 51 via the plurality of second buried electrodes 85, similar to the gate finger electrodes 83.

[0354] When a plurality of gate electrodes 22 are disposed below the main gate electrode 90, the main gate electrode 90 may be electrically connected to the plurality of gate electrodes 22 via a plurality of second buried electrodes 85. The main gate electrode 90 does not have to have a plurality of second buried electrodes 85.

[0355] That is, the main gate electrode 90 does not have to have an electrical connection portion to the plurality of gate electrodes 22 and an electrical connection portion to the gate wiring 51 in the region directly below it. A configuration in which the plurality of gate electrodes 22 are not positioned in the region below the main gate electrode 90 may be employed.

[0356] The gate potential applied to the main gate electrode 90 is applied to the gate wiring 51 via the gate finger electrodes 83. The gate potential is transmitted to the plurality of gate electrodes 22 via a wiring path (current path) along the gate wiring 51. This turns on the plurality of gate electrodes 22, controlling the on / off of the plurality of channel regions 17, 18.

[0357] The semiconductor device 1A includes a drain main electrode 91 covering the second main surface 4. The drain main electrode 91 is a terminal electrode to which a drain potential is applied from the outside. The drain main electrode 91 may also be referred to as a "third main electrode," a "third pad electrode," a "third terminal electrode," or the like.

[0358] The drain main electrode 91 is electrically connected to the first semiconductor region 10. The drain main electrode 91 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain main electrode 91 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0359] The breakdown voltage that can be applied between the source main electrode 70 and the drain main electrode 91 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0360] Other examples of the gate structure 20 will be shown below with reference to FIGS. 10A to 10J. FIGS. 10A to 10J are enlarged cross-sectional views showing gate structures 20 according to second to eleventh examples. The gate structure 20 does not necessarily have to have any one of the configurations of the first to eleventh examples (FIG. 7, FIGS. 10A to 10J). The gate structure 20 may simultaneously include features of at least two of the configurations of the first to eleventh examples. The gate structures 20 according to the first to eleventh examples can all be obtained by adjusting process conditions during the manufacturing process.

[0361] 10A (second example), in this embodiment, the gate electrode 22 is formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view. The gate electrode 22 has a first sidewall 27 and a second sidewall 28 that are obliquely inclined toward the electrode surface 26, and is formed in a tapered shape having a width that gradually narrows from the gate insulating film 21 side toward the electrode surface 26 side. The second sidewall 28 may have an inclination angle (absolute value) different from the inclination angle (absolute value) of the first sidewall 27.

[0362] In this embodiment, the first planar insulating film 23 is stacked on the gate electrode 22 at a tilt angle different from that of the gate electrode 22. The first planar insulating film 23 has a first insulating sidewall 30 having a tilt angle different from that of the first sidewall 27 and a second insulating sidewall 31 having a tilt angle different from that of the second sidewall 28.

[0363] The inclination angle of the first insulating side wall 30 is smaller than the inclination angle of the first side wall 27 when a vertical line along the vertical direction Z is taken as the reference (0°). The inclination angle of the second insulating side wall 31 is smaller than the inclination angle of the second side wall 28 when a vertical line along the vertical direction Z is taken as the reference (0°). In this embodiment, the first insulating side wall 30 and the second insulating side wall 31 extend approximately perpendicular to the first main surface 3.

[0364] The first sidewall insulating film 24 covers the first sidewall 27 and the first insulating sidewall 30 in a film-like manner, following the inclination angles of the first sidewall 27 and the first insulating sidewall 30. The first sidewall insulating film 24 has a film surface that is inclined obliquely with respect to the vertical line in the covering portion corresponding to the first sidewall 27, and a film surface that extends along the vertical line in the covering portion corresponding to the first insulating sidewall 30.

[0365] The second sidewall insulating film 25 covers the second sidewall 28 and the second insulating sidewall 31 in a film-like manner, following the inclination angles of the second sidewall 28 and the second insulating sidewall 31. The second sidewall insulating film 25 has a film surface that is obliquely inclined with respect to the vertical line in the covering portion corresponding to the second sidewall 28, and a film surface that extends along the vertical line in the covering portion corresponding to the second insulating sidewall 31.

[0366] 10B (third example), in this embodiment, the gate electrode 22 has a first sidewall 27 and a second sidewall 28 extending substantially perpendicular to the electrode surface 26 in a cross-sectional view, and is formed in a flat rectangular shape. In this embodiment, the first planar insulating film 23 is stacked on the gate electrode 22 at an inclination angle different from that of the gate electrode 22. Specifically, the first planar insulating film 23 is formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view.

[0367] The first planar insulating film 23 has a first insulating sidewall 30 and a second insulating sidewall 31 that are obliquely inclined toward the first insulating surface 29, and is formed in a tapered shape with a width that gradually narrows from the gate electrode 22 side toward the first insulating surface 29 side. The inclination angle of the first insulating sidewall 30 is larger than the inclination angle of the first sidewall 27 when a vertical line along the vertical direction Z is taken as a reference (0°). The inclination angle of the second insulating sidewall 31 is larger than the inclination angle of the second sidewall 28 when a vertical line along the vertical direction Z is taken as a reference (0°).

[0368] The first sidewall insulating film 24 covers the first sidewall 27 and the first insulating sidewall 30 in a film-like manner, following the inclination angles of the first sidewall 27 and the first insulating sidewall 30. The first sidewall insulating film 24 has a film surface that extends along a vertical line in the covering portion for the first sidewall 27, and a film surface that is obliquely inclined with respect to the vertical line in the covering portion for the first insulating sidewall 30.

[0369] The second sidewall insulating film 25 covers the second sidewall 28 and the second insulating sidewall 31 in a film-like manner in accordance with the inclination angles of the second sidewall 28 and the second insulating sidewall 31. The second sidewall insulating film 25 has a film surface that extends along a vertical line in the covering portion corresponding to the second sidewall 28, and a film surface that is obliquely inclined with respect to the vertical line in the covering portion corresponding to the second insulating sidewall 31.

[0370] 10C (fourth example), the gate electrode 22 is formed in a tapered shape (preferably an isosceles trapezoidal shape) in cross section. The gate electrode 22 may have a first sidewall 27 and a second sidewall 28 that are obliquely inclined toward the electrode surface 26, and may be formed in a tapered shape having a width that gradually narrows from the gate insulating film 21 side toward the electrode surface 26 side.

[0371] The second side wall 28 may have an inclination angle (absolute value) different from the inclination angle (absolute value) of the first side wall 27. The inclination angle (absolute value) of the second side wall 28 may be approximately equal to the inclination angle (absolute value) of the first side wall 27.

[0372] In this embodiment, the first planar insulating film 23 is formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view. The first planar insulating film 23 has a first insulating sidewall 30 and a second insulating sidewall 31 that are obliquely inclined toward the first insulating surface 29, and is formed in a tapered shape whose width gradually narrows from the gate electrode 22 side toward the first insulating surface 29 side.

[0373] The inclination angle of the first insulating side wall 30 may be different from the inclination angle of the first side wall 27 when a vertical line along the vertical direction Z is taken as the reference (0°). The inclination angle of the first insulating side wall 30 may be less than the inclination angle of the first side wall 27 or may be greater than the inclination angle of the first side wall 27. In this embodiment, the first insulating side wall 30 has an inclination angle approximately equal to the inclination angle of the first side wall 27 and is formed approximately flush with the first side wall 27.

[0374] The inclination angle of the second insulating side wall 31 may be different from the inclination angle of the second side wall 28 when a vertical line along the vertical direction Z is taken as the reference (0°). The inclination angle of the second insulating side wall 31 may be less than the inclination angle of the second side wall 28 or may be greater than the inclination angle of the second side wall 28. In this embodiment, the first insulating side wall 30 has an inclination angle approximately equal to the inclination angle of the first side wall 27 and is formed approximately flush with the first side wall 27.

[0375] The first sidewall insulating film 24 covers the first sidewall 27 and the first insulating sidewall 30 in a film-like manner, following the inclination angles of the first sidewall 27 and the first insulating sidewall 30. The first sidewall insulating film 24 has a film surface that is obliquely inclined with respect to the vertical line in the covering portion corresponding to the first sidewall 27, and a film surface that is obliquely inclined with respect to the vertical line in the covering portion corresponding to the first insulating sidewall 30.

[0376] The second sidewall insulating film 25 covers the second sidewall 28 and the second insulating sidewall 31 in a film-like manner in accordance with the inclination angles of the second sidewall 28 and the second insulating sidewall 31. The second sidewall insulating film 25 has a film surface that is obliquely inclined with respect to the vertical line in the covering portion corresponding to the second sidewall 28, and a film surface that is obliquely inclined with respect to the vertical line in the covering portion corresponding to the second insulating sidewall 31.

[0377] 10D (fifth example), the first planar insulating film 23 has a first arc-shaped corner portion and a second arc-shaped corner portion. The first arc-shaped corner portion connects the first insulating surface 29 and the first insulating sidewall 30 in an arc-shaped manner. The second arc-shaped corner portion connects the first insulating surface 29 and the second insulating sidewall 31 in an arc-shaped manner.

[0378] The first sidewall insulating film 24 covers the first sidewall 27 in a film shape following the inclination angle of the first sidewall 27, and covers the first arc corner portion in an arc film shape following the arc surface of the first arc corner portion. The first sidewall insulating film 24 may have a film thickness that gradually increases from the first insulating surface 29 side toward the gate electrode 22 side in the covering portion for the first arc corner portion.

[0379] The second sidewall insulating film 25 covers the second sidewall 28 in a film shape following the inclination angle of the second sidewall 28, and covers the second arc corner portion in an arc film shape following the arc surface of the second arc corner portion. The second sidewall insulating film 25 may have a film thickness that gradually increases from the first insulating surface 29 side toward the gate electrode 22 side in the covering portion for the second arc corner portion.

[0380] Referring to FIG. 10E (sixth example), in this embodiment, the first planar insulating film 23 is stacked on the gate electrode 22 so as to extend horizontally (in the first direction X) from above the gate electrode 22 into an area outside the gate electrode 22.

[0381] In this embodiment, the first planar insulating film 23 has a first insulating sidewall 30 that protrudes in the horizontal direction (first direction X) from the first sidewall 27 and a second insulating sidewall 31 that protrudes in the horizontal direction (first direction X) from the second sidewall 28. In other words, the first planar insulating film 23 has a first overhanging portion that protrudes from above the gate electrode 22 to one side in the first direction X and a second overhanging portion that protrudes from above the gate electrode 22 to one side in the first direction X.

[0382] The first overhang portion is defined by the rear surface of the first planar insulating film 23 and the first insulating sidewall 30, and faces the gate insulating film 21 in the stacking direction without the gate electrode 22 therebetween. The first insulating sidewall 30 is connected to the first sidewall 27 via the rear surface of the first planar insulating film 23.

[0383] The second overhang portion is defined by the rear surface of the first planar insulating film 23 and the second insulating sidewall 31, and faces the gate insulating film 21 in the stacking direction without interposing the gate electrode 22. The second insulating sidewall 31 is connected to the second sidewall 28 via the rear surface of the first planar insulating film 23.

[0384] The first sidewall insulating film 24 covers the first sidewall 27 and the first insulating sidewall 30 in a film-like manner, following the inclination angles of the first sidewall 27 and the first insulating sidewall 30. The first sidewall insulating film 24 may have a portion covering the rear surface of the first planar insulating film 23. The first sidewall insulating film 24 may have a recess in the portion covering the first sidewall 27 that is recessed closer to the gate electrode 22 (first sidewall 27) than the portion covering the first insulating sidewall 30.

[0385] The second sidewall insulating film 25 covers the second sidewall 28 and the second insulating sidewall 31 in a film-like manner, following the inclination angles of the second sidewall 28 and the second insulating sidewall 31. The second sidewall insulating film 25 may have a portion covering the back surface of the first planar insulating film 23. The second sidewall insulating film 25 may have a recess in the portion covering the second sidewall 28 that is recessed closer to the gate electrode 22 (first sidewall 27) than the portion covering the second insulating sidewall 31.

[0386] The first lower electrode film 71 (the first electrode film 74 and the second electrode film 75) of the source main electrode 70 may have a portion extending along the recess of the first sidewall insulating film 24. In this case, either or both of the first electrode film 74 and the second electrode film 75 may face the gate insulating film 21 with a part of the first sidewall insulating film 24 interposed therebetween.

[0387] The first lower electrode film 71 (the first electrode film 74 and the second electrode film 75) of the source main electrode 70 may have a portion extending along the recess of the first sidewall insulating film 24. In this case, either or both of the first electrode film 74 and the second electrode film 75 may face the gate insulating film 21 with a part of the second sidewall insulating film 25 interposed therebetween.

[0388] When the amount of protrusion of the first planar insulating film 23 from the gate electrode 22 is small, the first sidewall insulating film 24 may have no recess and may have a film surface that extends continuously in a vertical line in both the covering portion that covers the first sidewall 27 and the covering portion that covers the first insulating sidewall 30. Similarly, when the amount of protrusion of the first planar insulating film 23 from the gate electrode 22 is small, the second sidewall insulating film 25 may have no recess and may have a film surface that extends continuously in a vertical line in both the covering portion that covers the second sidewall 28 and the covering portion that covers the second insulating sidewall 31.

[0389] 10F (seventh example), in this embodiment, the first sidewall insulating film 24 covers the first insulating sidewall 30 of the first planar insulating film 23 at a distance from the first insulating surface 29 toward the first main surface 3 (gate insulating film 21). In this embodiment, the first sidewall insulating film 24 covers both the first oxide film 32 and the second oxide film 33 across the boundary between them, and exposes the upper end of the second oxide film 33 from the first insulating sidewall 30.

[0390] In this embodiment, the second sidewall insulating film 25 covers the second insulating sidewall 31 of the first planar insulating film 23 at a distance from the first insulating surface 29 toward the first main surface 3 (gate insulating film 21). In this embodiment, the second sidewall insulating film 25 covers both the first oxide film 32 and the second oxide film 33 across the boundary between them, and exposes the upper end of the second oxide film 33 from the first insulating sidewall 30.

[0391] In this embodiment, the first lower electrode film 71 of the source main electrode 70 has portions that directly cover the exposed portions of the first insulating sidewall 30 and the second insulating sidewall 31. Specifically, the first electrode film 74 has portions that directly cover the second oxide film 33 on the first insulating sidewall 30 and the second insulating sidewall 31. On the other hand, the second electrode film 75 has portions that cover the second oxide film 33 on the first insulating sidewall 30 and the second insulating sidewall 31 with the first electrode film 74 sandwiched therebetween.

[0392] Referring to FIG. 10G (eighth example), in this embodiment, the first sidewall insulating film 24 covers the first insulating sidewall 30 at a distance from the boundary between the first oxide film 32 and the second oxide film 33 toward the first main surface 3 (gate insulating film 21), and both the first oxide film 32 and the second oxide film 33 are exposed from the first insulating sidewall 30.

[0393] In this embodiment, the second sidewall insulating film 25 covers the second insulating sidewall 31 at a distance from the boundary between the first oxide film 32 and the second oxide film 33 toward the first main surface 3 (gate insulating film 21), and exposes both the first oxide film 32 and the second oxide film 33 from the second insulating sidewall 31.

[0394] In this embodiment, the first lower electrode film 71 of the source main electrode 70 has a portion that directly covers both the exposed portion of the first insulating sidewall 30 and the exposed portion of the second insulating sidewall 31. Specifically, the first electrode film 74 has a portion that directly covers both the first oxide film 32 and the second oxide film 33 on the first insulating sidewall 30 and the second insulating sidewall 31. On the other hand, the second electrode film 75 has a portion that covers both the first oxide film 32 and the second oxide film 33 on the first insulating sidewall 30 and the second insulating sidewall 31, with the first electrode film 74 sandwiched between them.

[0395] 10H (ninth example), in this embodiment, the plurality of sidewall insulating films 24, 25 each have a protruding portion that protrudes above the first insulating surface 29. The protruding portion has a protruding amount that is less than the thickness of the first planar insulating film 23. The protruding amount of the protruding portion is less than the thickness of the first oxide film 32. The protruding amount of the protruding portion is less than the thickness of the second oxide film 33. The protruding amount of the protruding portion may be less than the thickness of the plurality of sidewall insulating films 24, 25. The protruding amount of the protruding portion may be greater than the thickness of the plurality of sidewall insulating films 24, 25.

[0396] In this embodiment, the first lower electrode film 71 of the source main electrode 70 has portions that directly cover the protruding portions of the plurality of sidewall insulating films 24, 25. Specifically, the first electrode film 74 has portions that directly cover the protruding portions of the plurality of sidewall insulating films 24, 25. On the other hand, the second electrode film 75 has portions that cover the protruding portions of the plurality of sidewall insulating films 24, 25 with the first electrode film 74 sandwiched therebetween.

[0397] 10I (Tenth Example), the sidewall insulating films 24, 25 have a stacked structure including a plurality of insulating films. The number of stacked insulating films may be two, three, four, or five. The sidewall insulating films 24, 25 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film as the insulating films. The silicon oxide film may be any of an NSG film, a TEOS film, a PSG film, and a BPSG film.

[0398] The insulating films may each have a thickness of 0.05 μm or more and 0.5 μm or less. The insulating films may have a thickness that falls within at least one of the ranges of 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.15 μm or less, 0.15 μm or more and 0.2 μm or less, 0.2 μm or more and 0.25 μm or less, 0.25 μm or more and 0.3 μm or less, 0.3 μm or more and 0.35 μm or more and 0.35 μm or more and 0.4 μm or more and 0.4 μm or more and 0.45 μm or less, and 0.45 μm or more and 0.5 μm or less.

[0399] 10I shows an example in which the plurality of sidewall insulating films 24, 25 have a stacked structure (two-layer structure) including a first insulating film 95 and a second insulating film 96. The configuration on the first sidewall insulating film 24 side will be described below. The configuration on the second sidewall insulating film 25 side can be obtained by replacing "first sidewall 27" with "second sidewall 28" and "first insulating sidewall 30" with "second insulating sidewall 31" in the following description.

[0400] The first insulating film 95 covers the first sidewall 27 on the gate insulating film 21. The first insulating film 95 may have a lower end portion extending horizontally on the gate insulating film 21. In this embodiment, the first insulating film 95 extends from the first sidewall 27 toward the first insulating sidewall 30 of the first planar insulating film 23, and has a portion covering the first sidewall 27 and a portion covering the first insulating sidewall 30. The first insulating film 95 has a portion covering the boundary between the gate electrode 22 and the first planar insulating film 23.

[0401] The first insulating film 95 covers the first sidewall 27 and the first insulating sidewall 30 in a film-like manner, following the inclination angles of the first sidewall 27 and the first insulating sidewall 30. The first insulating film 95 extends at an inclination angle substantially equal to the inclination angle of the first sidewall 27 in the covering portion relative to the first sidewall 27, and has a film surface extending substantially parallel to the first sidewall 27. Furthermore, the first insulating film 95 extends at an inclination angle substantially equal to the inclination angle of the first insulating sidewall 30 in the covering portion relative to the first insulating sidewall 30, and has a film surface extending substantially parallel to the first insulating sidewall 30.

[0402] The first insulating film 95 covers both the first oxide film 32 and the second oxide film 33 on the first insulating sidewall 30. The first insulating film 95 has a portion that covers the boundary between the first oxide film 32 and the second oxide film 33. The first insulating film 95 is formed on the first main surface 3 side of the first insulating surface 29, exposing the first insulating surface 29. The first insulating film 95 exposes the second oxide film 33 from the first insulating surface 29.

[0403] The second insulating film 96 covers the first sidewall 27 on the gate insulating film 21, with the first insulating film 95 sandwiched therebetween. The second insulating film 96 has a lower end located above the lower end of the first insulating film 95. The lower end of the second insulating film 96 faces the gate insulating film 21, with the lower end of the first insulating film 95 sandwiched therebetween. The lower end of the second insulating film 96 may be directly connected to the gate insulating film 21.

[0404] In this embodiment, the second insulating film 96 extends from the first sidewall 27 to the first insulating sidewall 30 side of the first planar insulating film 23 and covers the first insulating sidewall 30 with the first insulating film 95 sandwiched between them. The second insulating film 96 has a portion that covers the first sidewall 27 with the first insulating film 95 sandwiched between them, and a portion that covers the first insulating sidewall 30 with the first insulating film 95 sandwiched between them. The second insulating film 96 has a portion that covers the boundary between the gate electrode 22 and the first planar insulating film 23 with the first insulating film 95 sandwiched between them.

[0405] The second insulating film 96 covers the first sidewall 27 and the first insulating sidewall 30 in a film-like manner, following the inclination angles of the first sidewall 27 and the first insulating sidewall 30. The second insulating film 96 extends at an inclination angle substantially equal to the inclination angle of the first sidewall 27 in the covering portion relative to the first sidewall 27, and has a film surface extending substantially parallel to the first sidewall 27. Furthermore, the second insulating film 96 extends at an inclination angle substantially equal to the inclination angle of the first insulating sidewall 30 in the covering portion relative to the first insulating sidewall 30, and has a film surface extending substantially parallel to the first insulating sidewall 30.

[0406] The second insulating film 96 covers both the first oxide film 32 and the second oxide film 33 on the first insulating sidewall 30, sandwiching the first insulating film 95 therebetween. The second insulating film 96 has a portion that covers the boundary between the first oxide film 32 and the second oxide film 33, sandwiching the first insulating film 95 therebetween. The second insulating film 96 is formed on the first main surface 3 side of the first insulating surface 29, and exposes the first insulating surface 29. The second insulating film 96 exposes the second oxide film 33 from the first insulating surface 29.

[0407] 10J (eleventh example), in this embodiment, the plurality of gate structures 20 are arranged at a narrow pitch to define a plurality of vertically elongated source openings 65 having an aspect ratio D / W greater than 1. The plurality of source openings 65 have an opening depth D greater than the opening width W, and are each formed in a vertically elongated shape in cross section.

[0408] In other words, the first sidewall insulating film 24 and the second sidewall insulating film 25 define a vertically elongated source opening 65 having an aspect ratio D / W greater than 1. Such source opening 65 is appropriately formed by the first sidewall insulating film 24, which is a film having no portion bulging in the horizontal direction, and the second sidewall insulating film 25, which is a film having no portion bulging in the horizontal direction.

[0409] The opening width W is preferably 1 to 5 times the thickness of the first sidewall insulating film 24 (second sidewall insulating film 25). It is particularly preferable that the opening width W is 1.5 to 3 times the thickness of the first sidewall insulating film 24 (second sidewall insulating film 25). The opening width W is preferably 0.25 μm to 0.45 μm. The opening depth D is preferably 0.5 μm to 1 μm. The aspect ratio D / W is preferably 3 or less. It is particularly preferable that the aspect ratio D / W is 2 or less.

[0410] In this embodiment, the source main electrode 70 includes a plurality of first buried electrodes 72 extending in a vertically elongated columnar shape in a cross-sectional view, and a first upper electrode film 73 mechanically and electrically connected to the plurality of first buried electrodes 72 extending in a vertically elongated columnar shape. The plurality of first buried electrodes 72 have an aspect ratio D / W greater than 1 in a cross-sectional view, corresponding to the aspect ratio D / W of the corresponding source opening 65.

[0411] In a configuration in which multiple gate structures 20 are arranged at a narrow pitch, the channel area per unit area is increased. Therefore, such a configuration is effective in reducing the on-resistance of the active region 8 (transistor structure Tr). On the other hand, in a configuration in which multiple gate structures 20 are arranged at a narrow pitch, the width of the source opening 65 is reduced due to the layout of the multiple gate structures 20. In this case, the embedding and deposition properties of the source main electrode 70 in the source opening 65 become an issue.

[0412] In this regard, according to the source main electrode 70 including the first buried electrode 72 and the first upper electrode film 73, the first buried electrodes 72 are buried in the source openings 65, which suppresses a decrease in the embedding property of the first upper electrode film 73 in the source openings 65. Furthermore, the steps caused by the source openings 65 are reduced by the first buried electrodes 72, which suppresses a decrease in the film formability of the first upper electrode film 73 in the source openings 65.

[0413] Therefore, the source main electrode 70 can be appropriately electrically connected to the first main surface 3. The configuration of the gate structure 20 according to the eleventh example (aspect ratio D / W) is preferably applied to the gate structures 20 according to the first to tenth examples.

[0414] Other exemplary embodiments of the wiring structure 50 will be described below with reference to FIGS. 11A to 11I. FIGS. 11A to 11I are enlarged cross-sectional views showing the wiring structure 50 according to second to tenth examples. The wiring structures 50 according to the first to tenth examples are all obtained by adjusting process conditions during the manufacturing process. The wiring structure 50 does not necessarily have to have any one of the configurations of the first to tenth examples (FIG. 9, FIGS. 11A to 11I). The wiring structure 50 may simultaneously include features of at least two of the configurations of the first to tenth examples.

[0415] Furthermore, at least one of the wiring structures 50 according to the first to tenth examples can be combined with at least one of the gate structures 20 according to the first to eleventh examples (see FIG. 7 and FIGS. 10A to 10J). A combination of at least two of the wiring structures 50 according to the first to tenth examples may be applied to at least one of the gate structures 20 according to the first to eleventh examples (see FIG. 7 and FIGS. 10A to 10J).

[0416] The wiring structures 50 according to the second to tenth examples shown below (see FIGS. 11A to 11I) have configurations corresponding to the configurations of the gate structures 20 according to the second to tenth examples (see FIGS. 10A to 10I) described above, respectively, in the order of the examples. Therefore, from the viewpoint of uniformity in the layout of the gate structure 20 and the layout of the wiring structure 50, it is preferable that the wiring structures 50 according to the first to tenth examples and the gate structures 20 according to the first to tenth examples be combined with each other in the form examples having the same number.

[0417] 11A (second example), in this embodiment, the gate wiring 51 has a first wiring sidewall 55 that is inclined obliquely toward the wiring surface 54. The gate wiring 51 is formed in a tapered shape having a width that gradually narrows from the main surface insulating film 44 side toward the wiring surface 54 side.

[0418] The second wiring sidewall 56 of the gate wiring 51 may have an inclination angle (absolute value) different from the inclination angle (absolute value) of the first wiring sidewall 55. In this embodiment, the second wiring sidewall 56 extends substantially perpendicular to the wiring surface 54. The second wiring sidewall 56 may be inclined obliquely toward the wiring surface 54.

[0419] In this embodiment, the second planar insulating film 52 includes a third insulating sidewall 58 having an inclination angle different from the inclination angle of the first wiring sidewall 55. The inclination angle of the third insulating sidewall 58 is smaller than the inclination angle of the first wiring sidewall 55 when a vertical line along the vertical direction Z is set as the reference (0°).

[0420] The third sidewall insulating film 53 covers the first wiring sidewall 55 and the third insulating sidewall 58 in a film-like manner, following the inclination angles of the first wiring sidewall 55 and the third insulating sidewall 58. The third sidewall insulating film 53 has a film surface that is obliquely inclined with respect to the vertical line in the covering portion corresponding to the first wiring sidewall 55, and a film surface that extends along the vertical line in the covering portion corresponding to the third insulating sidewall 58.

[0421] 11B (third example), in this embodiment, the gate wiring 51 has a first wiring sidewall 55 that extends substantially perpendicular to the wiring surface 54 in a cross-sectional view. In this embodiment, the second wiring sidewall 56 of the gate wiring 51 extends substantially perpendicular to the wiring surface 54. The second wiring sidewall 56 may be obliquely inclined toward the wiring surface 54.

[0422] In this embodiment, the second planar insulating film 52 includes a third insulating sidewall 58 having an inclination angle different from the inclination angle of the first wiring sidewall 55. Specifically, the third insulating sidewall 58 is inclined obliquely toward the second insulating surface 57 in a cross-sectional view. The inclination angle of the third insulating sidewall 58 is larger than the inclination angle of the first wiring sidewall 55 when a vertical line along the vertical direction Z is set as the reference (0°).

[0423] The third sidewall insulating film 53 covers the first wiring sidewall 55 and the third insulating sidewall 58 in a film-like manner, following the inclination angles of the first wiring sidewall 55 and the third insulating sidewall 58. The third sidewall insulating film 53 has a film surface that extends along a vertical line in the covering portion corresponding to the first wiring sidewall 55, and a film surface that is obliquely inclined with respect to the vertical line in the covering portion corresponding to the third insulating sidewall 58.

[0424] 11C (fourth example), in this embodiment, the gate wiring 51 has a first wiring sidewall 55 that is obliquely inclined toward the wiring surface 54. The gate wiring 51 is formed in a tapered shape having a width that gradually narrows from the main surface insulating film 44 side toward the wiring surface 54 side. In this embodiment, the second wiring sidewall 56 of the gate wiring 51 extends approximately perpendicular to the wiring surface 54. The second wiring sidewall 56 may be obliquely inclined toward the wiring surface 54.

[0425] In this embodiment, the second planar insulating film 52 has a third insulating sidewall 58 that is inclined obliquely toward the second insulating surface 57. The inclination angle of the third insulating sidewall 58 may be different from the inclination angle of the first wiring sidewall 55 when a vertical line along the vertical direction Z is taken as the reference (0°).

[0426] The inclination angle of the third insulating sidewall 58 may be less than the inclination angle of the first wiring sidewall 55 or may be greater than the inclination angle of the first wiring sidewall 55. In this embodiment, the third insulating sidewall 58 has an inclination angle substantially equal to the inclination angle of the first wiring sidewall 55 and is formed substantially flush with the first wiring sidewall 55.

[0427] The third sidewall insulating film 53 covers the first wiring sidewall 55 and the third insulating sidewall 58 in a film-like manner, following the inclination angles of the first wiring sidewall 55 and the third insulating sidewall 58. The third sidewall insulating film 53 has a film surface that is obliquely inclined with respect to the vertical in the covering portion that corresponds to the first wiring sidewall 55, and a film surface that is obliquely inclined with respect to the vertical in the covering portion that corresponds to the third insulating sidewall 58.

[0428] 11D (fifth example), the second planar insulating film 52 has a third arc-shaped corner portion that connects the second insulating surface 57 and the third insulating sidewall 58 in an arc shape.

[0429] The third sidewall insulating film 53 covers the first wiring sidewall 55 in a film shape following the inclination angle of the first wiring sidewall 55, and covers the third arc corner portion in an arc film shape following the arc surface of the third arc corner portion. The third sidewall insulating film 53 may have a film thickness that gradually increases from the second insulating surface 57 side toward the gate wiring 51 side in the covering portion for the third arc corner portion.

[0430] 11E (sixth example), in this embodiment, the second planar insulating film 52 is stacked on the gate wiring 51 so as to extend horizontally (in the second direction Y) from above the gate wiring 51 to an area outside the gate wiring 51. In this embodiment, the second planar insulating film 52 has a third insulating sidewall 58 that extends horizontally (in the second direction Y) from the first wiring sidewall 55.

[0431] That is, the second planar insulating film 52 has a third overhanging portion that extends from above the gate wiring 51 toward the inside of the active region 8. The third overhanging portion is defined by the back surface of the second planar insulating film 52 and the third insulating sidewall 58, and faces the main surface insulating film 44 in the stacking direction without the gate wiring 51 therebetween. The third insulating sidewall 58 is connected to the first wiring sidewall 55 via the back surface of the second planar insulating film 52.

[0432] The third sidewall insulating film 53 covers the first wiring sidewall 55 and the third insulating sidewall 58 in a film-like manner, following the inclination angles of the first wiring sidewall 55 and the third insulating sidewall 58. The third sidewall insulating film 53 may have a portion covering the back surface of the second planar insulating film 52. The third sidewall insulating film 53 may have a recess in the portion covering the first wiring sidewall 55 that is recessed closer to the gate wiring 51 (first wiring sidewall 55) than the portion covering the third insulating sidewall 58.

[0433] The first lower electrode film 71 (the first electrode film 74 and the second electrode film 75) of the source main electrode 70 may have a portion extending along the recess of the third sidewall insulating film 53. In this case, either or both of the first electrode film 74 and the second electrode film 75 may face the main surface insulating film 44 with a part of the third sidewall insulating film 53 interposed therebetween.

[0434] When the protrusion of the second planar insulating film 52 relative to the gate wiring 51 is small, the third sidewall insulating film 53 may have no recess and have a film surface that extends continuously in a vertical line in both the covering portion relative to the first wiring sidewall 55 and the covering portion relative to the third insulating sidewall 58.

[0435] 11F (seventh example), in this embodiment, the third sidewall insulating film 53 covers the third insulating sidewall 58 of the second planar insulating film 52 at a distance from the second insulating surface 57 toward the first main surface 3 (main surface insulating film 44). In this embodiment, the third sidewall insulating film 53 covers both the first oxide film 59 and the second oxide film 60 across the boundary between them, and exposes the upper end of the second oxide film 60 from the third insulating sidewall 58.

[0436] In this embodiment, the first lower electrode film 71 of the source main electrode 70 has a portion that directly covers the exposed portion of the third insulating sidewall 58. Specifically, the first electrode film 74 has a portion that directly covers the second oxide film 60 on the third insulating sidewall 58. On the other hand, the second electrode film 75 has a portion that covers the second oxide film 60 on the third insulating sidewall 58 with the first electrode film 74 sandwiched therebetween.

[0437] Referring to FIG. 11G (eighth example), in this embodiment, the third sidewall insulating film 53 covers the third insulating sidewall 58 at a distance from the boundary between the first oxide film 59 and the second oxide film 60 toward the first main surface 3 (main surface insulating film 44), and both the first oxide film 59 and the second oxide film 60 are exposed from the third insulating sidewall 58.

[0438] In this embodiment, the first lower electrode film 71 of the source main electrode 70 has a portion that directly covers the exposed portion of the third insulating sidewall 58. Specifically, the first electrode film 74 has a portion that directly covers both the first oxide film 59 and the second oxide film 60 on the third insulating sidewall 58. On the other hand, the second electrode film 75 has a portion that covers both the first oxide film 59 and the second oxide film 60 on the third insulating sidewall 58 with the first electrode film 74 sandwiched therebetween.

[0439] 11H (ninth example), in this embodiment, the third sidewall insulating film 53 has a protruding portion that protrudes above the second insulating surface 57. The protruding portion has a protruding amount that is less than the thickness of the second planar insulating film 52. The protruding amount of the protruding portion is less than the thickness of the first oxide film 59. The protruding amount of the protruding portion is less than the thickness of the second oxide film 60. The protruding amount of the protruding portion may be less than the thickness of the third sidewall insulating film 53. The protruding amount of the protruding portion may be greater than the thickness of the third sidewall insulating film 53.

[0440] In this embodiment, the first lower electrode film 71 of the source main electrode 70 has a portion that directly covers the protruding portion of the third sidewall insulating film 53. Specifically, the first electrode film 74 has a portion that directly covers the protruding portion of the third sidewall insulating film 53. On the other hand, the second electrode film 75 has a portion that covers the protruding portion of the third sidewall insulating film 53 with the first electrode film 74 sandwiched therebetween.

[0441] 11I (Tenth Example), in this embodiment, the third sidewall insulating film 53 has a stacked structure including a plurality of insulating films. The number of stacked insulating films may be two, three, four, or five. The third sidewall insulating film 53 may include, as the plurality of insulating films, at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The silicon oxide film may be any of an NSG film, a TEOS film, a PSG film, and a BPSG film.

[0442] The insulating films may each have a thickness of 0.05 μm or more and 0.5 μm or less. The insulating films may have a thickness that falls within at least one of the ranges of 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.15 μm or less, 0.15 μm or more and 0.2 μm or less, 0.2 μm or more and 0.25 μm or less, 0.25 μm or more and 0.3 μm or less, 0.3 μm or more and 0.35 μm or more and 0.35 μm or more and 0.4 μm or more and 0.4 μm or more and 0.45 μm or less, and 0.45 μm or more and 0.5 μm or less.

[0443] 11I shows an example in which the third sidewall insulating film 53 has a stacked structure (two-layer structure) including a first insulating film 97 and a second insulating film 98. The first insulating film 97 covers the first wiring sidewall 55 on the main surface insulating film 44. The first insulating film 97 may have a lower end portion extending horizontally on the main surface insulating film 44. The first insulating film 97 covers the first wiring sidewall 55 and the third insulating sidewall 58 in a film-like manner, following the inclination angles of the first wiring sidewall 55 and the third insulating sidewall 58.

[0444] In this embodiment, the first insulating film 97 extends from the first wiring sidewall 55 toward the third insulating sidewall 58, and has a portion covering the first wiring sidewall 55 and a portion covering the third insulating sidewall 58. The first insulating film 97 has a portion covering the boundary between the gate wiring 51 and the second planar insulating film 52.

[0445] The first insulating film 97 covers the first wiring sidewall 55 and the third insulating sidewall 58 in a film shape, following the inclination angles of the first wiring sidewall 55 and the third insulating sidewall 58. The first insulating film 97 extends at an inclination angle substantially equal to the inclination angle of the first wiring sidewall 55 in the covering portion relative to the first wiring sidewall 55, and has a film surface extending substantially parallel to the first wiring sidewall 55. Furthermore, the first insulating film 97 extends at an inclination angle substantially equal to the inclination angle of the third insulating sidewall 58 in the covering portion relative to the third insulating sidewall 58, and has a film surface extending substantially parallel to the third insulating sidewall 58.

[0446] The first insulating film 97 covers both the first oxide film 59 and the second oxide film 60 at the third insulating sidewall 58. The first insulating film 97 has a portion that covers the boundary between the first oxide film 59 and the second oxide film 60. The first insulating film 97 is formed on the first main surface 3 side of the second insulating surface 57, and exposes the second insulating surface 57. The first insulating film 97 exposes the second oxide film 60 from the second insulating surface 57.

[0447] The second insulating film 98 covers the first wiring sidewall 55 on the main surface insulating film 44, with the first insulating film 97 sandwiched between them. The second insulating film 98 has a lower end located above the lower end of the first insulating film 97. The lower end of the second insulating film 98 faces the main surface insulating film 44, with the lower end of the first insulating film 97 sandwiched between them. The lower end of the second insulating film 98 may be directly connected to the main surface insulating film 44.

[0448] In this embodiment, the second insulating film 98 extends from the first wiring sidewall 55 to the third insulating sidewall 58 and covers the third insulating sidewall 58 with the first insulating film 97 in between. The second insulating film 98 has a portion that covers the first wiring sidewall 55 with the first insulating film 97 in between, and a portion that covers the third insulating sidewall 58 with the first insulating film 97 in between. The second insulating film 98 has a portion that covers the boundary between the gate wiring 51 and the second planar insulating film 52 with the first insulating film 97 in between.

[0449] The second insulating film 98 covers the first wiring sidewall 55 and the third insulating sidewall 58 in a film shape, following the inclination angles of the first wiring sidewall 55 and the third insulating sidewall 58. The second insulating film 98 extends at an inclination angle substantially equal to the inclination angle of the first wiring sidewall 55 in the covering portion relative to the first wiring sidewall 55, and has a film surface extending substantially parallel to the first wiring sidewall 55. Furthermore, the second insulating film 98 extends at an inclination angle substantially equal to the inclination angle of the third insulating sidewall 58 in the covering portion relative to the third insulating sidewall 58, and has a film surface extending substantially parallel to the third insulating sidewall 58.

[0450] The second insulating film 98 covers both the first oxide film 59 and the second oxide film 60 on the third insulating sidewall 58, sandwiching the first insulating film 97 therebetween. The second insulating film 98 has a portion that covers the boundary between the first oxide film 59 and the second oxide film 60, sandwiching the first insulating film 97 therebetween. The second insulating film 98 is formed on the first main surface 3 side of the second insulating surface 57 of the second planar insulating film 52, and exposes the second insulating surface 57. The second insulating film 98 exposes the second oxide film 60 from the second insulating surface 57.

[0451] As described above, the semiconductor device 1A includes a chip 2, a plurality of planar gate structures 20, a source opening 65 (opening), and a source main electrode 70 (main electrode). The chip 2 has a first main surface 3. The plurality of gate structures 20 are arranged at intervals on the first main surface 3. Each of the plurality of gate structures 20 includes a gate insulating film 21, a gate electrode 22, and sidewall insulating films 24 and 25. The gate insulating film 21 covers the first main surface 3. The gate electrode 22 is arranged on the gate insulating film 21. The sidewall insulating films 24 and 25 cover the sidewalls of the gate electrode 22.

[0452] The source opening 65 is defined by a plurality of sidewall insulating films 24, 25 in a region between the plurality of gate structures 20, and exposes the first main surface 3. The source main electrode 70 is mechanically connected to the plurality of sidewall insulating films 24, 25 within the source opening 65, and is electrically connected to the first main surface 3 within the source opening 65.

[0453] This configuration provides a semiconductor device 1A that can improve electrical characteristics. For example, in this semiconductor device 1A, the multiple gate structures 20 are arranged at a narrow pitch, which increases the current path per unit area, thereby reducing the on-resistance.

[0454] The chip 2 preferably contains SiC. This configuration provides a semiconductor device 1A as a SiC semiconductor device. The sidewall insulating films 24, 25 may cover the sidewalls of the gate electrode 22 in a film-like manner in a cross-sectional view and have film surfaces extending along the sidewalls of the gate electrode 22. This configuration reduces the area occupied by the sidewall insulating films 24, 25, thereby reducing the opening width W of the source opening 65. This allows the multiple gate structures 20 to be appropriately arranged at a narrow pitch.

[0455] The sidewall insulating films 24, 25 may cover the sidewalls of the gate electrode 22 on the gate insulating film 21. With this configuration, the formation locations of the sidewall insulating films 24, 25 are limited to above the gate insulating film 21, and therefore the sidewall insulating films 24, 25 are prevented from expanding into regions outside the gate insulating film 21. This prevents the pitch of the multiple gate structures 20 from expanding due to the areas occupied by the sidewall insulating films 24, 25.

[0456] The sidewall insulating films 24, 25 preferably have a thickness less than that of the gate electrode 22. The sidewall insulating films 24, 25 preferably have a single-layer structure made of a single insulating film. The sidewall insulating films 24, 25 preferably consist of an oxide film with no impurities added as a single insulating film. With these configurations, the area occupied by the sidewall insulating films 24, 25 can be reduced.

[0457] Each of the plurality of gate structures 20 may include a first planar insulating film 23 disposed on the gate electrode 22. This configuration improves the insulating properties for the gate electrode 22. In this case, the sidewall insulating films 24 and 25 may cover the sidewalls of the gate electrode 22 and the sidewalls of the first planar insulating film 23. This configuration appropriately improves the insulating properties for the gate electrode 22.

[0458] In this case, the source main electrode 70 may have a portion facing the gate electrode 22 across the first planar insulating film 23 in the stacking direction, and may be electrically isolated from the gate electrode 22 by the first planar insulating film 23. According to this configuration, in a layout in which a plurality of gate structures 20 are arranged at a narrow pitch, the source main electrode 70 is appropriately electrically isolated from the plurality of gate structures 20 by the first planar insulating film 23.

[0459] The first planar insulating film 23 may have a stacked structure including a plurality of insulating films. In this case, the sidewall insulating films 24 and 25 may cover the plurality of insulating films on the sidewalls of the first planar insulating film 23. The first planar insulating film 23 may include, as the plurality of insulating films, a first oxide film 32 with no impurities added that covers the gate electrode 22, and a second oxide film 33 that contains phosphorus and covers the first oxide film 32.

[0460] The source opening 65 may have a width equal to or greater than the thickness of the sidewall insulating films 24, 25. The source opening 65 may have a width equal to or less than the width of the gate electrode 22. The width of the source opening 65 may be equal to or greater than 1 time and equal to or less than 5 times the thickness of the sidewall insulating films 24, 25. The thickness of the sidewall insulating films 24, 25 may be equal to or greater than 0.05 μm and equal to or less than 0.5 μm. The width of the source opening 65 may be equal to or greater than 0.2 μm and equal to or less than 0.6 μm.

[0461] The source main electrode 70 may have a laminated structure including a first buried electrode 72 and a first upper electrode film 73. The first buried electrode 72 is electrically connected to the first main surface 3 within the source opening 65. The first upper electrode film 73 is electrically connected to the first main surface 3 above the first buried electrode 72 via the first buried electrode 72.

[0462] When the plurality of gate structures 20 are arranged at a narrow pitch, the width of the source opening 65 is reduced due to the layout of the plurality of gate structures 20. In this case, the embedding and deposition properties of the source main electrode 70 in the source opening 65 become an issue.

[0463] In this regard, according to the source main electrode 70 including the first buried electrode 72 and the first upper electrode film 73, the step caused by the source openings 65 is reduced by the first buried electrode 72, and therefore deterioration in the embedding property and film formation property of the first upper electrode film 73 in the multiple source openings 65 is suppressed. Therefore, the source main electrode 70 can be appropriately electrically connected to the first major surface 3.

[0464] The semiconductor device 1A may include a first silicide portion 81 formed in a portion of the first main surface 3 exposed from the source opening 65. According to this configuration, the source main electrode 70 can be electrically connected to the chip 2 via the first silicide portion 81. This can improve the ohmic contact of the source main electrode 70 with the chip 2.

[0465] The semiconductor device 1A may include an n-type second semiconductor region 11 (semiconductor region), a p-type body region 12, n-type source regions 14 and 15 (impurity regions), and p-type channel regions 17 and 18 (channels).

[0466] The second semiconductor region 11 may be formed in a surface layer portion of the first main surface 3. The body region 12 may be formed in a surface layer portion of the second semiconductor region 11. The source regions 14, 15 may be formed in a surface layer portion of the body region 12. The channel regions 17, 18 may be formed in a region between the second semiconductor region 11 and the source regions 14, 15 in the surface layer portion of the body region 12.

[0467] In this case, the gate insulating film 21 may cover the channel regions 17 and 18. The gate electrode 22 may face the channel regions 17 and 18 with the gate insulating film 21 interposed therebetween. The source opening 65 may expose the source regions 14 and 15. The source main electrode 70 may be electrically connected to the source regions 14 and 15 within the source opening 65.

[0468] The semiconductor device 1A may include a p-type contact region 16. The contact region 16 may be formed in a region different from the source regions 14, 15 in the surface layer portion of the body region 12. In this case, the source opening 65 may expose the source regions 14, 15 and the contact region 16. The source main electrode 70 may be electrically connected to the source regions 14, 15 and the contact region 16 in the source opening 65.

[0469] Fig. 12 is a schematic diagram showing a wafer 100 used in manufacturing the semiconductor device 1A. Referring to Fig. 12, the wafer 100 is a base material of the chip 2 and includes a SiC single crystal. The wafer 100 is formed in a flat disk shape. The wafer 100 may also be formed in a flat rectangular parallelepiped shape.

[0470] The wafer 100 has a first wafer main surface 101 on one side, a second wafer main surface 102 on the other side, and a wafer side surface 103 connecting the first wafer main surface 101 and the second wafer main surface 102. The first wafer main surface 101 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 102 corresponds to the second main surface 4 of the chip 2.

[0471] The first wafer main surface 101 and the second wafer main surface 102 are formed by the c-plane of a SiC single crystal. The first wafer main surface 101 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 102 is formed by the carbon surface of the SiC single crystal. The wafer 100 (the first wafer main surface 101 and the second wafer main surface 102) has the off-orientation and off-angle described above.

[0472] The wafer 100 has a mark 104 on the wafer side surface 103 that indicates the crystal orientation of the SiC single crystal. The mark 104 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 101 in a plan view.

[0473] The mark 104 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 104 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0474] In this embodiment, wafer 100 has a stacked structure including a first semiconductor layer 6 and a second semiconductor layer 7. First semiconductor layer 6 is made of a semiconductor wafer (SiC wafer) including SiC single crystal (semiconductor single crystal) and has the off-orientation and off-angle described above. First semiconductor layer 6 forms second wafer main surface 102 and wafer side surface 103.

[0475] The second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal) and is stacked on the first semiconductor layer 6. That is, in this embodiment, the wafer 100 is made of an epitaxial wafer (a so-called epi-wafer) having a stacked structure including a semiconductor wafer and an epitaxial layer. The second semiconductor layer 7 has the off direction and off angle described above. The second semiconductor layer 7 forms the first wafer main surface 101 and wafer side surface 103.

[0476] The wafer 100 includes a first semiconductor region 10 in a region (surface layer portion) on the second wafer main surface 102 side. The first semiconductor region 10 is formed in a layer shape extending along the second wafer main surface 102. In this embodiment, the first semiconductor region 10 is formed by a first semiconductor layer 6.

[0477] The wafer 100 includes a second semiconductor region 11 in a region (surface layer portion) on the first wafer main surface 101 side. The second semiconductor region 11 is formed in a layer shape extending along the first wafer main surface 101 and is electrically connected to the first semiconductor region 10. In this embodiment, the second semiconductor region 11 is formed by the second semiconductor layer 7.

[0478] The wafer 100 includes a plurality of device regions 105 and a plurality of cutting lines 106. For example, the plurality of device regions 105 and the plurality of cutting lines 106 are defined by alignment marks or the like formed on the first wafer main surface 101. Each device region 105 corresponds to a semiconductor device 1A. Each of the plurality of device regions 105 is set to have a quadrangular shape in a plan view.

[0479] In this embodiment, the multiple device regions 105 are set in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 105 are set at intervals inward from the periphery of the first wafer main surface 101 in a plan view. The multiple cutting lines 106 are set in a lattice pattern extending along the first direction X and the second direction Y to partition the multiple device regions 105.

[0480] 13A to 13R are cross-sectional views showing a manufacturing method of semiconductor device 1A. 13A to 13R show cross-sectional views of the region corresponding to Fig. 6. Referring to Fig. 13A, first, the aforementioned wafer 100 (see Fig. 12) preparation step is carried out.

[0481] 13B , a step of forming a plurality of body regions 12 and outer body regions 40 is performed. In this step, first, a first mask 110 having a predetermined layout is formed on first wafer main surface 101.

[0482] The first mask 110 may include either or both of an inorganic mask (a so-called hard mask) and an organic mask (a so-called soft mask). The first mask 110 exposes regions where the body regions 12 and the outer body region 40 are to be formed, and covers the other regions.

[0483] Next, a p-type impurity (trivalent element) is implanted into the surface layer of the second semiconductor region 11 by ion implantation through the first mask 110. The p-type impurity (trivalent element) is preferably aluminum. This forms a plurality of body regions 12 and an outer body region 40. The first mask 110 is then removed.

[0484] 13C , a step of forming a plurality of source regions 14, 15 is performed. In this step, a second mask 111 having a predetermined layout is first formed on the first wafer main surface 101. The second mask 111 may include either or both of an inorganic mask (a so-called hard mask) and an organic mask (a so-called soft mask). The second mask 111 exposes regions where the plurality of source regions 14, 15 are to be formed and covers other regions.

[0485] Next, an n-type impurity (pentavalent element) is implanted into the surface layer of the body region 12 by ion implantation through the second mask 111. The n-type impurity (pentavalent element) is preferably phosphorus. This forms a plurality of source regions 14, 15. The second mask 111 is then removed.

[0486] 13D , a step of forming the plurality of contact regions 16 is performed. In this step, a third mask 112 having a predetermined layout is first formed on the first wafer main surface 101. The third mask 112 may include either or both of an inorganic mask (a so-called hard mask) and an organic mask (a so-called soft mask). The third mask 112 exposes regions where the plurality of contact regions 16 are to be formed and covers the other regions.

[0487] Next, a p-type impurity (trivalent element) is implanted into the surface layer of the body region 12 by ion implantation through a third mask 112. The p-type impurity (trivalent element) is preferably aluminum. This results in the formation of multiple contact regions 16. After the contact region 16 formation step, the third mask 112 is removed.

[0488] Although not specifically shown in the drawings, termination region 41 is formed by introducing p-type impurities (trivalent elements) into a surface layer portion of second semiconductor region 11 by ion implantation using a mask (not shown) having a predetermined layout. The step of forming termination region 41 may be performed after the step of forming body region 12 (outer body region 40) or before the step of forming body region 12 (outer body region 40).

[0489] Similarly, the plurality of field regions 43 are formed by introducing p-type impurities (trivalent elements) into the surface layer portion of the second semiconductor region 11 by ion implantation using a mask (not shown) having a predetermined layout. The step of forming the field regions 43 may be performed after the step of forming the body region 12 (outer body region 40) or before the step of forming the body region 12 (outer body region 40).

[0490] The order of the process of forming the body region 12 (outer body region 40), the process of forming the source regions 14 and 15, the process of forming the contact region 16, the process of forming the termination region 41, and the process of forming the field region 43 is arbitrary and may be reversed as appropriate.

[0491] 13E , a step of forming a lower base insulating film 113 (lower insulating film) is performed. The lower base insulating film 113 serves as a base for the plurality of gate insulating films 21 and the main surface insulating film 44. The lower base insulating film 113 is formed in the form of a film on the first wafer main surface 101. The gate insulating film 21 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (for example, a thermal oxidation treatment method).

[0492] 13F , a step of forming a base gate electrode 114 is performed. The base gate electrode 114 serves as a base for the plurality of gate electrodes 22. The base gate electrode 114 is formed in the form of a film on the lower base insulating film 113. The base gate electrode 114 may be formed by a CVD method.

[0493] 13G , a first patterning step (pretreatment step) of the base gate electrode 114 is performed. In this step, a fourth mask 115 having a predetermined layout is first formed on the base gate electrode 114. The fourth mask 115 covers the covering portion of the base gate electrode 114 that corresponds to the active region 8, and selectively exposes the covering portion of the base gate electrode 114 that corresponds to the peripheral region 9.

[0494] Next, unnecessary portions of the base gate electrode 114 (portions covering the outer peripheral region 9) are removed by etching using the fourth mask 115. The unnecessary portions of the base gate electrode 114 are removed until the lower base insulating film 113 is exposed.

[0495] The etching method may be either or both of wet etching and dry etching. By this process, the outer edge portion of the base gate electrode 114 as the second wiring sidewall 56 of the gate wiring 51 is formed on the outer periphery region 9 (see also FIGS. 8 and 9 ).

[0496] 13H, a step of forming an upper base insulating film 116 (upper insulating film) is performed. The upper base insulating film 116 serves as a base for the plurality of first planar insulating films 23, second planar insulating films 52, and outer insulating film 61.

[0497] In this embodiment, the upper base insulating film 116 includes a first base oxide film 117 and a second base oxide film 118. The first base oxide film 117 serves as a base for the plurality of first oxide films 32 and first oxide films 59. The second base oxide film 118 serves as a base for the plurality of second oxide films 33 and second oxide films 60.

[0498] In this embodiment, the first base oxide film 117 is made of an NSG film and is laminated in the form of a film on the lower base insulating film 113 and the base gate electrode 114. The first base oxide film 117 may be formed by a CVD method.

[0499] The second base oxide film 118 includes a silicon oxide film containing phosphorus and is laminated in a film form on the first base oxide film 117. The second base oxide film 118 is formed by a CVD method. After the step of forming the second base oxide film 118, a reflow step (heat treatment step) is performed, which smoothes the upper base insulating film 116.

[0500] 13I, a process is performed to form a plurality of first planar insulating films 23, a second planar insulating film 52, an outer insulating film 61, a plurality of outer openings 67, and a plurality of gate openings 69. This process also serves as a patterning process for the upper base insulating film 116.

[0501] In this step, first, a fifth mask 119 having a predetermined layout is formed on the upper base insulating film 116. The fifth mask 119 covers regions of the upper base insulating film 116 where the plurality of first planar insulating films 23, the second planar insulating film 52, and the outer insulating film 61 are to be formed, and exposes regions where the plurality of outer openings 67 and the plurality of gate openings 69 are to be formed.

[0502] Next, unnecessary portions of the upper base insulating film 116 are removed by etching using the fifth mask 119. The unnecessary portions of the upper base insulating film 116 are removed until the upper base insulating film 116 is exposed. The etching method may be either or both of wet etching and dry etching.

[0503] The wet etching method may be isotropic or anisotropic. The dry etching method may be isotropic or anisotropic. By this process, a plurality of first planar insulating films 23, a second planar insulating film 52, an outer insulating film 61, a plurality of outer openings 67, and a plurality of gate openings 69 are formed.

[0504] The etching step for the outer openings 67 may include a step of digging down a portion of the first wafer main surface 101 toward the second wafer main surface 102. In this step, a plurality of outer recesses 68 are formed in the portions of the first wafer main surface 101 exposed from the outer openings 67. The fifth mask 119 is then removed.

[0505] The configuration of the first planar insulating film 23 according to the first to eleventh examples (see FIG. 7 and FIG. 10A to FIG. 10J) and the configuration of the second planar insulating film 52 according to the first to tenth examples (see FIG. 9 and FIG. 11A to FIG. 11I) are obtained by a process of appropriately adjusting the etching process conditions for the upper base insulating film 116.

[0506] 13J , a second patterning step (post-processing step) of the base gate electrode 114 is performed. The second patterning step of the base gate electrode 114 is also a step of forming the plurality of gate electrodes 22 and the gate wiring 51. In this step, unnecessary portions of the base gate electrode 114 are removed by etching via the plurality of first planar insulating films 23, the second planar insulating film 52, and the outer insulating film 61.

[0507] That is, in this step, a plurality of exposed portions of the base gate electrode 114 that are partitioned by the plurality of first planar insulating films 23 and the second planar insulating films 52 are removed. Unnecessary portions of the base gate electrode 114 may be removed by etching via the fifth mask 119 described above.

[0508] The unnecessary portion of the base gate electrode 114 is removed until the lower base insulating film 113 is exposed. The etching method may be either a wet etching method or a dry etching method, or both. The wet etching method may be isotropic or anisotropic. The dry etching method may be isotropic or anisotropic.

[0509] By this process, a plurality of gate electrodes 22 and gate wirings 51 are formed on the lower base insulating film 113 (see also FIGS. 6 to 9). In this process, the plurality of gate electrodes 22 are formed in a self-aligned manner with the plurality of first planar insulating films 23.

[0510] As a result, a plurality of gate electrodes 22 each covered with a plurality of first planar insulating films 23 are formed on the lower base insulating film 113. Also, in this process, the gate wiring 51 is formed in a self-aligned manner with the second planar insulating film 52. As a result, the gate wiring 51 covered with the second planar insulating film 52 is formed on the lower base insulating film 113.

[0511] The configurations of the gate electrode 22 according to the first to eleventh examples (see FIG. 7 and FIGS. 10A to 10J) and the configurations of the gate wiring 51 according to the first to tenth examples (see FIG. 9 and FIGS. 11A to 11I) are obtained by a process of appropriately adjusting the etching process conditions for the base gate electrode 114.

[0512] 13K, a step of forming a base sidewall insulating film 120 is performed. The base sidewall insulating film 120 serves as a base for the plurality of first sidewall insulating films 24, the plurality of second sidewall insulating films 25, and the plurality of third sidewall insulating films 53. The base sidewall insulating film 120 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0513] The base sidewall insulating film 120 may have a single-layer structure made of a single insulating film. Alternatively, the base sidewall insulating film 120 may have a layered structure including a plurality of insulating films. In this embodiment, the base sidewall insulating film 120 is made of a TEOS film, which is an example of an NSG film. The base sidewall insulating film 120 may be formed by a CVD method.

[0514] The base sidewall insulating film 120 collectively covers the plurality of gate electrodes 22 , the plurality of first planar insulating films 23 , the gate wiring 51 , the second planar insulating film 52 and the outer insulating film 61 on the lower base insulating film 113 .

[0515] Specifically, the base sidewall insulating film 120 coats the lower base insulating film 113, the first sidewall 27 and the second sidewall 28 of the gate electrode 22, the first insulating sidewall 30 and the second insulating sidewall 31 of the first planar insulating film 23, the first wiring sidewall 55 of the gate wiring 51, the third insulating sidewall 58 of the second planar insulating film 52, and the outer insulating film 61 in a film-like manner.

[0516] 13L , a step of forming a plurality of first sidewall insulating films 24, a plurality of second sidewall insulating films 25, and a plurality of third sidewall insulating films 53 is performed. In this step, unnecessary portions of the base sidewall insulating film 120 are selectively removed by etching (etch-back). The unnecessary portions of the base sidewall insulating film 120 are portions of the base sidewall insulating film 120 that extend in the horizontal direction. That is, the portions of the base sidewall insulating film 120 that extend in the horizontal direction are removed so that the portions that extend in the vertical direction Z remain.

[0517] Specifically, in this process, the covering portions of the base sidewall insulating film 120 covering the first insulating surface 29, the covering portion of the second insulating surface 57, and the covering portion of the insulating surface of the outer insulating film 61 are removed so as to leave the covering portions covering the first sidewall 27 and the second sidewall 28 of the gate electrode 22, the covering portions covering the first insulating sidewall 30 and the second insulating sidewall 31 of the first planar insulating film 23, the covering portion of the first wiring sidewall 55 of the gate wiring 51, and the covering portion of the third insulating sidewall 58 of the second planar insulating film 52.

[0518] The etching method may be either or both of a wet etching method and a dry etching method. The wet etching method is preferably anisotropic. The dry etching method is preferably anisotropic. The etching method is particularly preferably a reactive ion etching method (RIE).

[0519] This process forms a plurality of first sidewall insulating films 24, a plurality of second sidewall insulating films 25, and a plurality of third sidewall insulating films 53. The plurality of first sidewall insulating films 24 and the plurality of second sidewall insulating films 25 are formed in a self-aligned manner with the plurality of gate electrodes 22 (the plurality of first planar insulating films 23), and the plurality of third sidewall insulating films 53 are formed in a self-aligned manner with the gate wiring 51 (the second planar insulating film 52).

[0520] 13M , a step of forming the plurality of gate insulating films 21, the main surface insulating film 44, and the plurality of source openings 65 is performed. In this step, a plurality of exposed portions of the lower base insulating film 113 defined by the plurality of first sidewall insulating films 24, the plurality of second sidewall insulating films 25, and the plurality of third sidewall insulating films 53 are removed by etching.

[0521] In this step, the concealed portions of the lower base insulating film 113 that are covered by the gate electrodes 22 (the first planar insulating films 23) remain as the gate insulating films 21. The concealed portions of the lower base insulating film 113 that are covered by the gate wiring 51 (the second planar insulating film 52) and the outer insulating film 61 remain as the main surface insulating film 44.

[0522] The etching method may be either or both of a wet etching method and a dry etching method. The wet etching method is preferably anisotropic. The dry etching method is preferably anisotropic. The etching method is particularly preferably RIE.

[0523] The etching step for the base sidewall insulating film 120 described above may also serve as the etching step for the lower base insulating film 113. In this case, the unnecessary portion of the base sidewall insulating film 120 is removed simultaneously with the unnecessary portion of the lower base insulating film 113. The etching step for the lower base insulating film 113 may be performed separately from the etching step for the base sidewall insulating film 120 described above.

[0524] This forms a plurality of gate insulating films 21 and a main surface insulating film 44. This also forms a plurality of source openings 65 that expose the first wafer main surface 101. The etching step for the plurality of source openings 65 may include a step of digging down part of the first wafer main surface 101 toward the second wafer main surface 102. In this step, a plurality of source recesses 66 are formed in the portions of the first wafer main surface 101 that are exposed from the plurality of source openings 65.

[0525] 13N, a base lower electrode film 121 formation step is performed. The base lower electrode film 121 is the base of the first lower electrode film 71 and the second lower electrode film 84. The base lower electrode film 121 has a laminated structure including a first base lower electrode film 122 and a second base lower electrode film 123. The first base lower electrode film 122 is the base of the first electrode film 74 and the first electrode film 87. The second base lower electrode film 123 is the base of the second electrode film 75 and the second electrode film 88.

[0526] In this embodiment, the first base lower electrode film 122 includes a Ti film. The first base lower electrode film 122 may be formed by sputtering or vapor deposition. The first base lower electrode film 122 is formed in a film shape along the first insulating surface 29, the second insulating surface 57, the wall surfaces of the source openings 65, the wall surfaces of the outer openings 67, and the wall surfaces of the gate openings 69.

[0527] In this embodiment, the second base lower electrode film 123 includes a TiN film. The second base lower electrode film 123 may be formed by sputtering or vapor deposition. The second base lower electrode film 123 is formed in a film shape along the first insulating surface 29, the second insulating surface 57, the wall surfaces of the plurality of source openings 65, the wall surfaces of the plurality of outer openings 67, and the wall surfaces of the plurality of gate openings 69.

[0528] After the step of forming the first base lower electrode film 122, the first base lower electrode film 122 reacts (silicide reaction) with SiC on the first wafer main surface 101 to form a plurality of first silicide portions 81 and a plurality of second silicide portions 82. The silicide reaction may be performed by an annealing method such as an RTA method.

[0529] The step of forming the first silicide portion 81 (second silicide portion 82) may be performed prior to the step of forming the second base lower electrode film 123. The step of forming the first silicide portion 81 (second silicide portion 82) may be performed after the step of forming the second base lower electrode film 123.

[0530] The first silicide portion 81 (second silicide portion 82) may be formed to include a silicide other than titanium silicide. In this case, a step of silicidating the wafer 100 with a metal film (not shown) is performed prior to the step of forming the first base lower electrode film 122. The metal film may include at least one of a nickel film, a cobalt film, a molybdenum film, a tungsten film, and a vanadium film.

[0531] 13O, a base intermediate electrode film 124 is formed on the base lower electrode film 121. The base intermediate electrode film 124 includes at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. In this embodiment, the base intermediate electrode film 124 includes tungsten.

[0532] The base intermediate electrode film 124 may be formed by a CVD method (e.g., a low-pressure CVD method). The base intermediate electrode film 124 backfills the source openings 65, the outer openings 67, and the gate openings 69, and coats the first insulating surface 29, the second insulating surface 57, and the insulating surfaces of the outer insulating film 61 in a film-like manner.

[0533] 13P, a step of removing the base intermediate electrode film 124 is performed. In this step, an unnecessary portion of the base intermediate electrode film 124 is removed by etching (etch-back). The etching may be wet etching and / or dry etching.

[0534] Unnecessary portions of the base intermediate electrode film 124 are removed until the base lower electrode film 121 is exposed. As a result, a plurality of first buried electrodes 72 are buried in the plurality of source openings 65. Furthermore, a plurality of first buried electrodes 72 are buried in the plurality of outer openings 67. Furthermore, a plurality of second buried electrodes 85 are buried in the plurality of gate openings 69.

[0535] 13Q, a process for forming the base upper electrode film 125 is performed. The base upper electrode film 125 is a base for the first upper electrode film 73 and the second upper electrode film 86. The base upper electrode film 125 is laminated in the form of a film on the base lower electrode film 121, the plurality of first buried electrodes 72, and the plurality of second buried electrodes 85.

[0536] The upper base electrode film 125 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The upper base electrode film 125 may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The upper base electrode film 125 may be formed by sputtering or vapor deposition.

[0537] Next, the base upper electrode film 125 is divided into the source main electrodes 70, the source finger electrodes 80, the gate finger electrodes 83, and the gate main electrodes 90. In this process, a mask (not shown) having a predetermined layout is formed on the base upper electrode film 125. The mask (not shown) covers regions where the source main electrodes 70, the source finger electrodes 80, the gate finger electrodes 83, and the gate main electrodes 90 are to be formed, and leaves regions other than these regions exposed.

[0538] Next, unnecessary portions of the base upper electrode film 125 are removed by etching using a mask (not shown). The unnecessary portions of the base upper electrode film 125 are removed until the base lower electrode film 121 is exposed. The etching method may be wet etching and / or dry etching. The mask (not shown) is removed after the etching process of the base upper electrode film 125.

[0539] Next, unnecessary portions of the base lower electrode film 121 are removed by etching via the base upper electrode film 125. The unnecessary portions of the base lower electrode film 121 are removed until the second planar insulating film 52 and the outer insulating film 61 are exposed.

[0540] The step of removing the base lower electrode film 121 includes a step of removing the second base lower electrode film 123 by an etching method and a step of removing the first base lower electrode film 122 by an etching method. The etching method may be a wet etching method and / or a dry etching method.

[0541] The unnecessary portions of the base lower electrode film 121 may be removed by etching through a mask (not shown) in the etching step of the base upper electrode film 125. As a result, the source main electrode 70, the source finger electrodes 80, the gate finger electrodes 83, and the gate main electrode 90 are formed.

[0542] 13R, a drain main electrode 91 is formed on the second wafer main surface 102. The drain main electrode 91 may be formed by sputtering or vapor deposition. Thereafter, the wafer 100 is cut along the cutting lines 106 to cut out a plurality of semiconductor devices 1A. Through the steps including those described above, the semiconductor device 1A is manufactured.

[0543] Fig. 14 is an enlarged cross-sectional view showing a gate structure 20 of a semiconductor device 1B according to the second embodiment. Fig. 15 is an enlarged cross-sectional view showing a wiring structure 50 of the semiconductor device 1B shown in Fig. 14. Referring to Fig. 14, similar to the semiconductor device 1A, the semiconductor device 1B includes a first sidewall insulating film 24 covering the first sidewall 27 and a second sidewall insulating film 25 covering the second sidewall 28.

[0544] In this embodiment, the first sidewall insulating film 24 has a single-layer structure made of a silicon oxide film. The first sidewall insulating film 24 is preferably made of a silicon oxide film containing an oxide of the gate electrode 22 (polysilicon).

[0545] In this embodiment, the first sidewall insulating film 24 covers the first sidewall 27 in the region between the gate insulating film 21 and the first planar insulating film 23. The first sidewall insulating film 24 covers the first sidewall 27 and exposes the first insulating sidewall 30. Specifically, the first sidewall insulating film 24 covers the entire first sidewall 27 and exposes the entire first insulating sidewall 30.

[0546] That is, the first sidewall insulating film 24 has a lower end connected to the gate insulating film 21 and an upper end connected to the first planar insulating film 23. The first sidewall insulating film 24 covers the first sidewall 27 in a film shape following the inclination angle of the first sidewall 27. The first sidewall insulating film 24 extends at an inclination angle substantially equal to the inclination angle of the first sidewall 27 and has a film surface extending substantially parallel to the first sidewall 27.

[0547] In this embodiment, the first sidewall insulating film 24 extends substantially vertically in the region between the gate insulating film 21 and the first planar insulating film 23. When the gate electrode 22 is formed in a tapered shape and the first sidewall 27 is obliquely inclined, the first sidewall insulating film 24 may have a film surface that is obliquely inclined with respect to the vertical line in the covering portion of the first sidewall 27.

[0548] In this embodiment, the second sidewall insulating film 25 has a single-layer structure made of a silicon oxide film. The second sidewall insulating film 25 is preferably made of a silicon oxide film containing an oxide of the gate electrode 22 (polysilicon).

[0549] In this embodiment, the second sidewall insulating film 25 covers the second sidewall 28 in the region between the gate insulating film 21 and the first planar insulating film 23. The second sidewall insulating film 25 covers the second sidewall 28 and exposes the second insulating sidewall 31. Specifically, the second sidewall insulating film 25 covers the entire second sidewall 28 and exposes the entire second insulating sidewall 31.

[0550] The second sidewall insulating film 25 has a lower end connected to the gate insulating film 21 and an upper end connected to the first planar insulating film 23. The second sidewall insulating film 25 covers the second sidewall 28 in a film shape following the inclination angle of the second sidewall 28. The second sidewall insulating film 25 extends at an inclination angle substantially equal to the inclination angle of the second sidewall 28 and has a film surface extending substantially parallel to the second sidewall 28.

[0551] In this embodiment, the second sidewall insulating film 25 extends substantially vertically in the region between the gate insulating film 21 and the first planar insulating film 23. When the gate electrode 22 is formed in a tapered shape and the second sidewall 28 is obliquely inclined, the second sidewall insulating film 25 may have a film surface that is obliquely inclined with respect to the vertical line in the covering portion of the second sidewall 28.

[0552] 15 , similar to semiconductor device 1A, semiconductor device 1B includes third sidewall insulating film 53 covering first wiring sidewall 55. In this embodiment, third sidewall insulating film 53 has a single-layer structure made of a silicon oxide film. Third sidewall insulating film 53 is preferably made of a silicon oxide film containing an oxide of gate wiring 51 (polysilicon).

[0553] In this embodiment, the third sidewall insulating film 53 covers the first wiring sidewall 55 in the region between the main surface insulating film 44 and the second planar insulating film 52. The third sidewall insulating film 53 covers the first wiring sidewall 55 and exposes the third insulating sidewall 58. Specifically, the third sidewall insulating film 53 covers the entire first wiring sidewall 55 and exposes the entire third insulating sidewall 58.

[0554] That is, the third sidewall insulating film 53 has a lower end connected to the main surface insulating film 44 and an upper end connected to the second planar insulating film 52. The third sidewall insulating film 53 covers the first wiring sidewall 55 in a film shape following the inclination angle of the first wiring sidewall 55. The third sidewall insulating film 53 extends at an inclination angle substantially equal to the inclination angle of the first wiring sidewall 55 and has a film surface extending substantially parallel to the first wiring sidewall 55.

[0555] In this embodiment, the third sidewall insulating film 53 extends substantially vertically in the region between the main surface insulating film 44 and the second planar insulating film 52. When the gate wiring 51 is formed in a tapered shape and the first wiring sidewall 55 is obliquely inclined, the third sidewall insulating film 53 may have a film surface that is obliquely inclined with respect to the vertical in the covering portion thereof relative to the first wiring sidewall 55.

[0556] Similar to the semiconductor device 1A, the multiple source openings 65 are each defined in an area surrounded by the multiple gate structures 20 and wiring structures 50. In this embodiment, the multiple source openings 65 are defined in the first direction X by the first planar insulating film 23 and the first sidewall insulating film 24 of one gate structure 20 and the first planar insulating film 23 and the second sidewall insulating film 25 of the other gate structure 20. The multiple source openings 65 have both ends defined in the second direction Y by the second planar insulating film 52 and the third sidewall insulating film 53 of the wiring structure 50.

[0557] In this embodiment, the first lower electrode film 71 of the source main electrode 70 has a portion that directly covers both the exposed portion of the first insulating sidewall 30 and the exposed portion of the second insulating sidewall 31. Specifically, the first electrode film 74 directly covers the entire first insulating sidewall 30 and the entire second insulating sidewall 31. That is, the first electrode film 74 directly covers both the first oxide film 32 and the second oxide film 33 on the first insulating sidewall 30, and directly covers both the first oxide film 32 and the second oxide film 33 on the second insulating sidewall 31.

[0558] On the other hand, the second electrode film 75 covers the entire first insulating sidewall 30 and the entire second insulating sidewall 31 with the first electrode film 74 sandwiched between them. That is, the second electrode film 75 covers both the first oxide film 32 and the second oxide film 33 with the first electrode film 74 sandwiched between them on the first insulating sidewall 30 side, and covers both the first oxide film 32 and the second oxide film 33 with the first electrode film 74 sandwiched between them on the second insulating sidewall 31 side.

[0559] The configuration of the sidewall insulating films 24, 25 of the semiconductor device 1B may be applied to any one of the gate structures 20 (gate electrodes 22) of the first to eleventh examples (FIG. 7, FIGS. 10A to 10J) described above. The configuration of the sidewall insulating films 24, 25 of the semiconductor device 1B may be applied to any one of the wiring structures 50 (gate wiring 51) of the first to tenth examples (FIG. 9, FIGS. 11A to 11I) described above.

[0560] The configuration of the third sidewall insulating film 53 of the semiconductor device 1B may be applied to any one of the gate structures 20 (gate electrodes 22) of the first to eleventh examples (FIG. 7, FIGS. 10A to 10J) described above. The configuration of the third sidewall insulating film 53 of the semiconductor device 1B may be applied to any one of the wiring structures 50 (gate wiring 51) of the first to tenth examples (FIG. 9, FIGS. 11A to 11I) described above.

[0561] 16A to 16C are cross-sectional views showing a method for manufacturing semiconductor device 1B shown in Fig. 14. Referring to Fig. 16A, in the method for manufacturing semiconductor device 1B, wafer 100 is prepared after the second patterning step (see Fig. 13J) of base gate electrode 114 described above.

[0562] 16B , a step of forming a plurality of first sidewall insulating films 24, a plurality of second sidewall insulating films 25, and a plurality of third sidewall insulating films 53 is performed. In this step, instead of the step of forming base sidewall insulating film 120, an oxidation treatment step is performed on the plurality of gate electrodes 22 and gate wiring 51. The oxidation treatment step may be either or both of a thermal oxidation treatment step and a wet oxidation treatment step.

[0563] This process oxidizes the portions of the gate electrodes 22 exposed from the first planar insulating films 23 (i.e., the first sidewalls 27 and the second sidewalls 28), and oxidizes the portions of the gate wiring 51 exposed from the second planar insulating film 52 (i.e., the first wiring sidewalls 55). As a result, the first sidewall insulating films 24, the second sidewall insulating films 25, and the third sidewall insulating films 53 are formed.

[0564] 16C , a step of forming the plurality of gate insulating films 21, the main surface insulating film 44, and the plurality of source openings 65 is performed. In this step, a plurality of exposed portions of the lower base insulating film 113 defined by the plurality of first sidewall insulating films 24, the plurality of second sidewall insulating films 25, and the plurality of third sidewall insulating films 53 are removed by etching.

[0565] In this step, the concealed portions of the lower base insulating film 113 that are covered by the gate electrodes 22 (the first planar insulating films 23) remain as the gate insulating films 21. The concealed portions of the lower base insulating film 113 that are covered by the gate wiring 51 (the second planar insulating film 52) and the outer insulating film 61 remain as the main surface insulating film 44.

[0566] The etching method may be either or both of a wet etching method and a dry etching method. The wet etching method is preferably anisotropic. The dry etching method is preferably anisotropic. The etching method is particularly preferably RIE.

[0567] Through this process, there are formed a plurality of gate insulating films 21, a main surface insulating film 44, and a plurality of source openings 65. Thereafter, through the same processes as those shown in FIGS.

[0568] 17 is a cross-sectional view showing a semiconductor device 1C according to a third embodiment. The semiconductor device 1C includes a plurality of p-type column regions 130 formed in the second semiconductor region 11 within a thickness range below a plurality of body regions 12.

[0569] The plurality of column regions 130 have a p-type impurity concentration lower than the p-type impurity concentration of the contact region 16. The p-type impurity concentration of the plurality of column regions 130 may be higher than the p-type impurity concentration of the body region 12. The p-type impurity concentration of the plurality of column regions 130 may be lower than the p-type impurity concentration of the body region 12.

[0570] The column regions 130 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. That is, the column regions 130 are formed in stripes extending in the second direction Y along the body regions 12. The extending direction of the body regions 12 also coincides with the off-direction of the SiC single crystal.

[0571] The multiple column regions 130 are formed in a columnar shape extending in the thickness direction in a cross-sectional view, and overlap the multiple body regions 12 in a one-to-one correspondence. The multiple column regions 130 may have a single-layer structure consisting of a single p-type impurity region, or may have a layered structure in which multiple p-type impurity regions are layered in the thickness direction. The configuration of one column region 130 will be specifically described below.

[0572] The column region 130 crosses the intermediate portion of the second semiconductor region 11 in the thickness direction. The column region 130 has a lower end and an upper end. The lower end of the column region 130 is located closer to the bottom of the second semiconductor region 11 than the intermediate portion of the second semiconductor region 11. The lower end of the column region 130 may be formed with a gap from the bottom of the second semiconductor region 11 toward the body region 12. The lower end of the column region 130 may cross the bottom of the second semiconductor region 11 and be located in the surface layer portion of the first semiconductor region 10.

[0573] The upper end of the column region 130 is located closer to the bottom (lower end) of the body region 12 than the intermediate portion of the second semiconductor region 11. The upper end of the column region 130 is preferably connected to the bottom of the body region 12.

[0574] That is, it is preferable that the column region 130 is electrically connected to the body region 12. The upper end of the column region 130 may be formed at a distance from the bottom of the body region 12 toward the bottom of the second semiconductor region 11, and may face the body region 12 with a part of the second semiconductor region 11 in between.

[0575] The column region 130 has a width less than that of the body region 12, and is formed at a distance inward from the peripheral edge of the body region 12. The width of the column region 130 may be greater than the width of the contact region 16. The column region 130 has a thickness greater than that of the body region 12. The thickness of the column region 130 may be less than the thickness of the second semiconductor region 11. The thickness of the column region 130 may be greater than the thickness of the second semiconductor region 11.

[0576] The semiconductor device 1C includes a plurality of n-type intermediate drift regions 131 formed in the second semiconductor region 11. Each of the plurality of intermediate drift regions 131 is made up of a region partitioned between a plurality of column regions 130 in the second semiconductor region 11.

[0577] The intermediate drift region 131 may have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 11, or may have an n-type impurity concentration lower than the n-type impurity concentration of the second semiconductor region 11. The intermediate drift region 131 may have an n-type impurity concentration higher than the n-type impurity concentration of the surface drift region 13, or may have an n-type impurity concentration lower than the n-type impurity concentration of the surface drift region 13.

[0578] The intermediate drift regions 131 are arranged alternately with the column regions 130 in the first direction X, and are each formed in a strip shape extending in the second direction Y. That is, the intermediate drift regions 131 are formed in stripes extending in the second direction Y along the column regions 130. The extending direction of the intermediate drift regions 131 coincides with the off-direction of the SiC single crystal.

[0579] The intermediate drift regions 131 are formed in a columnar shape extending in the thickness direction in a cross-sectional view, and are connected in one-to-one correspondence to the surface drift regions 13. Each of the intermediate drift regions 131 has a width greater than the width of the surface drift regions 13, and has both ends connected to two body regions 12 adjacent to each other in the first direction X.

[0580] The intermediate drift regions 131 form charge-balanced pn junctions together with the column regions 130 in a thickness range below the body region 12. The charge-balanced state means that, for adjacent column regions 130, a depletion layer extending from one pn junction and a depletion layer extending from the other pn junction are connected within the intermediate drift regions 131. As a result, the intermediate drift regions 131 form a superjunction structure with the column regions 130 in a region below the body region 12.

[0581] The process of forming the plurality of column regions 130 includes a mask formation process and a p-type impurity implantation process. In the mask formation process, a mask having openings that expose regions where the plurality of column regions 130 are to be formed is formed on the first wafer main surface 101. In the p-type impurity implantation process, p-type impurities are implanted into the second semiconductor region 11 by ion implantation through the mask.

[0582] The ion implantation method is preferably a channeling ion implantation method. In the channeling ion implantation step, p-type impurities are implanted along a channel axis (e.g., the c-axis) of the crystal axes of the wafer 100 (second semiconductor layer 7) along which atomic rows are sparse. The p-type impurities are implanted deep into the second semiconductor region 11 while repeatedly undergoing small-angle scattering due to the channeling effect. In other words, the channeling implantation method reduces the probability of collision of trivalent elements with atomic rows of the SiC single crystal. This results in the formation of multiple column regions 130.

[0583] The step of forming the column region 130 may be performed after the step of forming the body region 12. In this case, the column region 130 is formed inside the second semiconductor region 11 so as to be connected to the body region 12 in the thickness direction. The step of forming the column region 130 may be performed before the step of forming the body region 12. In this case, in the step of forming the body region 12, the body region 12 is formed in the surface layer portion of the second semiconductor region 11 so as to be connected to the column region 130 in the thickness direction.

[0584] As described above, the semiconductor device 1C includes a p-type column region 130 in addition to the configuration of the semiconductor device 1A. The column region 130 is formed in the second semiconductor region 11 within a thickness range below the body region 12. This configuration provides a superjunction type semiconductor device 1C. When the chip 2 includes a SiC single crystal, a superjunction type SiC semiconductor device having a novel configuration for the body region 12 is provided.

[0585] In this embodiment, an example has been shown in which the plurality of column regions 130 (the plurality of intermediate drift regions 131) are formed in stripes extending in the second direction Y along the plurality of body regions 12. However, the plurality of column regions 130 may be formed in stripes extending in the first direction X and arranged at intervals in the second direction Y. In other words, the extension direction of the plurality of column regions 130 may intersect (specifically, be perpendicular to) the off-direction of the SiC single crystal. In this case, the plurality of column regions 130 intersect (specifically, be perpendicular to) the plurality of body regions 12.

[0586] The column regions 130 (the intermediate drift regions 131) may be arranged at intervals in an intersecting direction that intersects both the first direction X and the second direction Y, and may each be formed in a strip shape extending in an orthogonal direction that is perpendicular to the intersecting direction. In other words, the extending direction of the column regions 130 may intersect with the off-direction of the SiC single crystal. In this case, the column regions 130 intersect with the body regions 12.

[0587] In this embodiment, an example has been shown in which the plurality of body regions 12 (body regions 12) are formed in stripes extending in the second direction Y. However, the plurality of body regions 12 may be formed in stripes extending in the first direction X and arranged at intervals in the second direction Y. That is, the plurality of body regions 12 may be formed in stripes extending in the first direction X. Furthermore, the extending direction of the plurality of body regions 12 may intersect (specifically, be perpendicular to) the off-direction of the SiC single crystal.

[0588] In this case, the multiple column regions 130 (multiple intermediate drift regions 131) may be formed in stripes extending in the first direction X and arranged at intervals in the second direction Y. In other words, the multiple column regions 130 (multiple intermediate drift regions 131) may be formed in stripes extending in the first direction X along the multiple body regions 12.

[0589] The column regions 130 may be arranged at intervals in the first direction X and may each be formed in a band shape extending in the second direction Y. In other words, the column regions 130 may be formed in a stripe shape extending in the second direction Y. Furthermore, the extending direction of the column regions 130 may coincide with the off-direction of the SiC single crystal.

[0590] In this case, the plurality of column regions 130 intersect (specifically, are perpendicular to) the plurality of body regions 12. The plurality of column regions 130 (the plurality of intermediate drift regions 131) may be arranged at intervals in an intersecting direction that intersects both the first direction X and the second direction Y, and may each be formed in a strip shape extending in an intersecting direction that is perpendicular to the intersecting direction.

[0591] In this embodiment, an example has been shown in which the plurality of column regions 130 (the plurality of intermediate drift regions 131) are applied to the configuration of the semiconductor device 1A. However, the plurality of column regions 130 (the plurality of intermediate drift regions 131) may also be applied to the semiconductor device 1B according to the second embodiment.

[0592] Modified examples applicable to the semiconductor devices 1A to 1C according to the first to third embodiments are shown below. Fig. 18 is a cross-sectional view showing a first modified example of the source main electrode 70. Fig. 18 illustrates a configuration in which the source main electrode 70 according to the modified example is applied to the semiconductor device 1A. The source main electrode 70 according to the first modified example is applicable to the semiconductor device 1B and the semiconductor device 1C.

[0593] In each of the above-described embodiments, the source main electrode 70 includes a plurality of first buried electrodes 72. However, as shown in FIG. 18 , the source main electrode 70 may include an intermediate electrode film 132 instead of the plurality of first buried electrodes 72.

[0594] The intermediate electrode film 132 includes a conductive material different from the conductive material of the first lower electrode film 71. The intermediate electrode film 132 includes at least one of a tungsten film, a molybdenum film, a tungsten alloy film, and a molybdenum alloy film. In this embodiment, the intermediate electrode film 132 includes a tungsten film.

[0595] The intermediate electrode film 132 is stacked on the first lower electrode film 71 as an intermediate layer of the source main electrode 70, and collectively covers the plurality of gate structures 20 in the active region 8 in the form of a film. The intermediate electrode film 132 is mechanically and electrically connected to the first lower electrode film 71 on the first insulating surface 29 and the second insulating surface 57.

[0596] Specifically, the intermediate electrode film 132 covers the plurality of first planar insulating films 23 in a film-like manner, sandwiching the first lower electrode film 71. The intermediate electrode film 132 has a peripheral portion that covers the wiring structure 50 in a film-like manner, sandwiching the first lower electrode film 71. The peripheral portion of the intermediate electrode film 132 covers the second planar insulating film 52, sandwiching the peripheral portion of the first lower electrode film 71.

[0597] The intermediate electrode film 132 extends into the plurality of source openings 65 from above the first insulating surface 29 and the second insulating surface 57. The intermediate electrode film 132 is mechanically connected to the plurality of first sidewall insulating films 24, the plurality of second sidewall insulating films 25, and the plurality of third sidewall insulating films 53 within the plurality of source openings 65, and is electrically connected to the first main surface 3 via the first lower electrode film 71 within the plurality of source openings 65.

[0598] Specifically, the source main electrode 70 is electrically connected to the body regions 12, the source regions 14 and 15, the contact region 16, etc. via the first lower electrode film 71 inside the source openings 65. In other words, the intermediate electrode film 132 is electrically connected to the body regions 12, etc. via the first lower electrode film 71 inside and outside the source openings 65.

[0599] The intermediate electrode film 132 faces the plurality of gate electrodes 22 and the plurality of first planar insulating films 23 in the horizontal direction, with the plurality of sidewall insulating films 24, 25 sandwiched therebetween. In this embodiment, the intermediate electrode film 132 faces the first oxide film 32 and the second oxide film 33 in the horizontal direction, with the plurality of sidewall insulating films 24, 25 sandwiched therebetween.

[0600] The intermediate electrode film 132 faces the gate wiring 51 and the second planar insulating film 52 in the horizontal direction, with the third sidewall insulating film 53 sandwiched therebetween. In this embodiment, the intermediate electrode film 132 faces the first oxide film 32 and the second oxide film 33 in the horizontal direction, with a plurality of sidewall insulating films 24, 25 sandwiched therebetween.

[0601] In this embodiment, the first upper electrode film 73 is laminated in the form of a film on the intermediate electrode film 132 and is mechanically and electrically connected to the intermediate electrode film 132. The first upper electrode film 73 covers the first insulating surface 29, the second insulating surface 57, and the plurality of source openings 65 with the intermediate electrode film 132 in between. The first upper electrode film 73 is connected to the intermediate electrode film 132 above the plurality of source openings 65. In this embodiment, the first upper electrode film 73 does not have a mechanical connection to the first lower electrode film 71.

[0602] The source finger electrodes 80 may include an intermediate electrode film 132 instead of the plurality of first buried electrodes 72. Similarly, the source finger electrodes 80 may include an intermediate electrode film 132 instead of the plurality of second buried electrodes 85. Similarly, the main gate electrode 90 may include an intermediate electrode film 132.

[0603] The intermediate electrode film 132 is formed by adjusting the amount of etching for the base intermediate electrode film 124 in the above-described process of forming the base intermediate electrode film 124 (see FIG. 13O). For example, the intermediate electrode film 132 is formed by omitting the etching treatment for the base intermediate electrode film 124. For example, the intermediate electrode film 132 can also be formed by completing the etching treatment for the base intermediate electrode film 124 before the base underlying electrode film is exposed.

[0604] Fig. 19 is a cross-sectional view showing a second modified example of the source main electrode 70. Fig. 19 illustrates a configuration in which the source main electrode 70 according to the modified example is applied to the semiconductor device 1A. The source main electrode 70 according to the second modified example is applicable to the semiconductor device 1B and the semiconductor device 1C.

[0605] In each of the above-described embodiments, the source main electrode 70 has a plurality of first buried electrodes 72. However, as shown in Fig. 19, the source main electrode 70 does not necessarily have to have the first buried electrodes 72. In this case, the first upper electrode film 73 of the source main electrode 70 extends from above the first planar insulating film 23 (first insulating surface 29) and the second planar insulating film 52 (second insulating surface 57) into the plurality of source openings 65, and is electrically connected to the body region 12 and the like within the plurality of source openings 65.

[0606] Similarly, the source finger electrodes 80 do not necessarily have to have the first buried electrodes 72. In this case, the first upper electrode film 73 of the source finger electrodes 80 enters the outer openings 67 from above the outer insulating film 61 and is electrically connected to the termination region 41 (overlap region 42) within the outer openings 67.

[0607] Similarly, the gate finger electrode 83 does not necessarily have to have the second buried electrode 85. In this case, the second upper electrode film 86 of the gate finger electrode 83 enters the multiple gate openings 69 from above the second planar insulating film 52 (second insulating surface 57) and is electrically connected to the gate wiring 51 within the multiple gate openings 69.

[0608] The semiconductor device 1A may have the first buried electrode 72 associated with the source main electrode 70, but may not have the first buried electrode 72 associated with the source finger electrode 80. The semiconductor device 1A may have the first buried electrode 72 associated with the source finger electrode 80, but may not have the first buried electrode 72 associated with the source main electrode 70.

[0609] The semiconductor device 1A may have the first buried electrode 72 associated with the source main electrode 70, but may not have the second buried electrode 85 associated with the gate finger electrode 83. The semiconductor device 1A may have the second buried electrode 85 associated with the gate finger electrode 83, but may not have the first buried electrode 72 associated with the source main electrode 70.

[0610] The semiconductor device 1A may have the first buried electrode 72 associated with the source finger electrode 80, but may not have the second buried electrode 85 associated with the gate finger electrode 83. The semiconductor device 1A may have the second buried electrode 85 associated with the gate finger electrode 83, but may not have the first buried electrode 72 associated with the source finger electrode 80.

[0611] The above-described embodiments (including variations) can be implemented in other forms. For example, in each of the above-described embodiments, a structure may be adopted in which the conductivity type of an "n-type" semiconductor region is inverted to "p-type" and the conductivity type of a "p-type" semiconductor region is inverted to "n-type." A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

[0612] In the above-described embodiments, the chip 2 includes a SiC single crystal. However, the chip 2 may include a wide bandgap semiconductor single crystal other than a SiC single crystal. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. Examples of wide bandgap semiconductor single crystals include gallium nitride, gallium oxide, and diamond. The chip 2 may also include a silicon single crystal.

[0613] Similarly, the first semiconductor layer 6 may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal. The first semiconductor layer 6 may include gallium nitride, gallium oxide, diamond, etc. The first semiconductor layer 6 may include a silicon single crystal.

[0614] Similarly, the second semiconductor layer 7 may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal. The second semiconductor layer 7 may include gallium nitride, gallium oxide, diamond, etc. The second semiconductor layer 7 may include a silicon single crystal.

[0615] In the above-described embodiments, the n-type first semiconductor region 10 is shown. However, a p-type first semiconductor region 10 may be employed as a collector region instead of the n-type first semiconductor region 10. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure.

[0616] A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description and the accompanying drawings. The p-type collector region may be an impurity region containing p-type impurities implanted into the surface layer of the second main surface 4 of the n-type chip 2 by ion implantation.

[0617] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following descriptions may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0618] [A1] A semiconductor device (1A, 1B, 1C) including: a chip (2) having a main surface (3); a plurality of planar gate structures (20) arranged at intervals on the main surface (3), each including a gate insulating film (21) covering the main surface (3), a gate electrode (22) arranged on the gate insulating film (21), and sidewall insulating films (24, 25) covering sidewalls (27, 28) of the gate electrode (22); openings (65) defined by the plurality of sidewall insulating films (24, 25) in regions between the plurality of gate structures (20) and exposing the main surface (3); and a main electrode (70) mechanically connected to the plurality of sidewall insulating films (24, 25) within the openings (65) and electrically connected to the main surface (3) within the openings (65).

[0619] [A2] The semiconductor device (1A, 1B, 1C) according to A1, wherein the chip (2) includes SiC.

[0620] [A3] The semiconductor device (1A, 1B, 1C) described in A1 or A2, wherein the sidewall insulating film (24, 25) coats the sidewall (27, 28) of the gate electrode (22) in a film-like manner in a cross-sectional view and has a film surface extending along the sidewall (27, 28) of the gate electrode (22).

[0621] [A4] A semiconductor device (1A, 1B, 1C) according to any one of A1 to A3, wherein the sidewall insulating films (24, 25) cover the sidewalls (27, 28) of the gate electrode (22) on the gate insulating film (21).

[0622] [A5] The semiconductor device (1A, 1B, 1C) according to any one of A1 to A4, wherein the sidewall insulating film (24, 25) has a thickness less than the thickness of the gate electrode (22).

[0623] [A6] The semiconductor device (1A, 1B, 1C) according to any one of A1 to A5, wherein the sidewall insulating film (24, 25) has a single-layer structure made of a single insulating film.

[0624] [A7] The semiconductor device (1A, 1B, 1C) according to A6, wherein the single insulating film is made of an oxide film with no impurities added.

[0625] [A8] A semiconductor device (1A, 1B, 1C) according to any one of A1 to A7, wherein the plurality of gate structures (20) each include a planar insulating film (23) arranged on the gate electrode (22), and sidewall insulating films (24, 25) covering sidewalls (27, 28) of the gate electrode (22) and sidewalls (30, 31) of the planar insulating film (23), and the main electrode (70) has a portion facing the gate electrode (22) across the planar insulating film (23) in the stacking direction (Z), and is electrically isolated from the gate electrode (22) by the planar insulating film (23).

[0626] [A9] The semiconductor device (1A, 1B, 1C) according to A8, wherein the planar insulating film (23) has a laminated structure including a plurality of insulating films (32, 33).

[0627] [A10] The semiconductor device (1A, 1B, 1C) according to A9, wherein the sidewall insulating film (24, 25) covers a plurality of the insulating films (32, 33) on the sidewalls (30, 31) of the planar insulating film (23).

[0628] [A11] The semiconductor device (1A, 1B, 1C) according to A9 or A10, wherein the plurality of insulating films (32, 33) include a first oxide film (32) with no added impurities that covers the gate electrode (22), and a second oxide film (33) that contains phosphorus and covers the first oxide film (32).

[0629] [A12] A semiconductor device (1A, 1B, 1C) according to any one of A1 to A11, wherein the opening (65) has a width (W) that is equal to or greater than the thickness of the sidewall insulating film (24, 25) and equal to or less than the width of the gate electrode (22).

[0630] [A13] A semiconductor device (1A, 1B, 1C) according to A12, wherein the thickness of the sidewall insulating film (24, 25) is 0.05 μm or more and 0.5 μm or less, and the width (W) of the opening (65) is 0.2 μm or more and 0.6 μm or less.

[0631] [A14] The semiconductor device (1A, 1B, 1C) described in any one of A1 to A13, wherein the main electrode (70) has a laminated structure including a buried electrode (72) electrically connected to the main surface (3) within the opening (65), and an upper electrode (73) on the buried electrode (72) and electrically connected to the main surface (3) via the buried electrode (72).

[0632] [A15] A semiconductor device (1A, 1B, 1C) according to any one of A1 to A14, further including a silicide portion (81) formed in the portion of the main surface (3) exposed from the opening (65) and electrically connecting the main electrode (70) to the chip (2).

[0633] [A16] A semiconductor region (11) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3), a body region (12) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (11), impurity regions (14, 15) of the first conductivity type (n-type) formed in a surface layer portion of the body region (12), and a channel (1) formed in a region between the semiconductor region (11) and the impurity regions (14, 15) in the surface layer portion of the body region (12). The semiconductor device (1A, 1B, 1C) according to any one of A1 to A15, further comprising: a gate insulating film (21) covering the channel (17, 18); the gate electrode (22) facing the channel (17, 18) with the gate insulating film (21) interposed therebetween; the opening (65) exposing the impurity regions (14, 15); and the main electrode (70) electrically connected to the impurity regions (14, 15) within the opening (65).

[0634] [A17] A semiconductor device (1A, 1B, 1C) according to A16, further including a contact region (16) of a second conductivity type (p-type) formed in a region different from the impurity regions (14, 15) in a surface layer portion of the body region (12), the opening (65) exposing the impurity regions (14, 15) and the contact region (16), and the main electrode (70) electrically connected to the impurity regions (14, 15) and the contact region (16) within the opening (65).

[0635] [A18] A process of forming a lower insulating film (113) on a main surface (101) of a wafer (100), a process of forming a plurality of gate electrodes (22) on the lower insulating film (113), a process of forming a base insulating film (120) covering the plurality of gate electrodes (22) on the lower insulating film (113), a process of selectively removing the base insulating film (120) so as to leave covering portions of the base insulating film (120) on side walls (27, 28) of the plurality of gate electrodes (22), and a process of forming a plurality of side wall insulating films (24, 25) covering the side walls (27, 28) of the plurality of gate electrodes (22), respectively; a step of forming an opening (65) exposing the main surface (101) by removing exposed portions of the lower insulating film (113) partitioned by the plurality of sidewall insulating films (24, 25) so as to leave portions of the lower insulating film (113) covered by the plurality of gate electrodes (22) as a plurality of gate insulating films (21); and a step of forming a main electrode (70) on the main surface (101) so as to be mechanically connected to the plurality of sidewall insulating films (24, 25) within the opening (65) and electrically connected to the main surface (101) within the opening (65).

[0636] [A19] A method for manufacturing a semiconductor device (1A, 1B, 1C) according to A18, wherein the wafer (100) contains SiC.

[0637] [A20] The method further includes a step of forming a base gate electrode (114) on the lower insulating film (113), a step of forming an upper insulating film (116) on the base gate electrode (114), and a step of selectively removing the upper insulating film (116) and forming a plurality of planar insulating films (23) on the base gate electrode (114), wherein the step of forming the gate electrode (22) includes a step of removing exposed portions of the base gate electrode (114) that are partitioned by the plurality of planar insulating films (23), and forming a plurality of the gate electrodes (22) that are respectively covered by the plurality of planar insulating films (23) on the lower insulating film (113), and the step of forming the base insulating film (120) includes a step of selectively removing the exposed portions of the base gate electrode (114) that are partitioned by the plurality of planar insulating films (23), and forming a plurality of the gate electrodes (22) that are respectively covered by the plurality of planar insulating films (23) on the lower insulating film (113), a step of forming the base insulating film (120) that collectively covers the gate electrode (22) and the plurality of planar insulating films (23), and the step of forming the sidewall insulating films (24, 25) includes a step of selectively removing the base insulating film (120) so as to leave covering portions of the base insulating film (120) on sidewalls (27, 28) of the plurality of gate electrodes (22) and sidewalls (30, 31) of the plurality of planar insulating films (23), and forming a plurality of t...

Claims

1. a chip having a major surface; a plurality of planar gate structures each including a gate insulating film covering the main surface, a gate electrode disposed on the gate insulating film, and a sidewall insulating film covering a sidewall of the gate electrode, the plurality of planar gate structures being disposed at intervals on the main surface; a plurality of openings defined by the sidewall insulating films in regions between the plurality of gate structures; a main electrode mechanically connected to the plurality of sidewall insulating films in the opening and electrically connected to the main surface.

2. The semiconductor device according to claim 1 , wherein the chip comprises SiC.

3. 2. The semiconductor device according to claim 1, wherein said sidewall insulating film covers the sidewall of said gate electrode in a film-like manner in cross section and has a film surface extending along the sidewall of said gate electrode.

4. 2. The semiconductor device according to claim 1, wherein said sidewall insulating film covers a sidewall of said gate electrode on said gate insulating film.

5. 2. The semiconductor device according to claim 1, wherein said sidewall insulating film has a thickness less than a thickness of said gate electrode.

6. 2. The semiconductor device according to claim 1, wherein said sidewall insulating film has a single-layer structure made of a single insulating film.

7. 7. The semiconductor device according to claim 6, wherein said single insulating film is made of an oxide film containing no impurities.

8. each of the plurality of gate structures includes a planar insulating film disposed on the gate electrode, and the sidewall insulating film covering a sidewall of the gate electrode and a sidewall of the planar insulating film; 2. The semiconductor device according to claim 1, wherein said main electrode has a portion facing said gate electrode across said planar insulating film in the stacking direction, and is electrically separated from said gate electrode by said planar insulating film.

9. 9. The semiconductor device according to claim 8, wherein said planar insulating film has a laminated structure including a plurality of insulating films.

10. 10. The semiconductor device according to claim 9, wherein said sidewall insulating film covers a plurality of said insulating films on the sidewalls of said planar insulating film.

11. 10. The semiconductor device according to claim 9, wherein said plurality of insulating films include a first oxide film with no impurities added thereto that covers said gate electrode, and a second oxide film that contains phosphorus and covers said first oxide film.

12. 2. The semiconductor device according to claim 1, wherein said opening has a width equal to or greater than the thickness of said sidewall insulating film and equal to or less than the width of said gate electrode.

13. the thickness of the sidewall insulating film is 0.05 μm or more and 0.5 μm or less; 13. The semiconductor device according to claim 12, wherein the width of the opening is not less than 0.2 [mu]m and not more than 0.6 [mu]m.

14. 2. The semiconductor device according to claim 1, wherein the main electrode has a layered structure including a buried electrode electrically connected to the main surface within the opening, and an upper electrode on the buried electrode and electrically connected to the main surface via the buried electrode.

15. 15. The semiconductor device according to claim 1, further comprising a silicide portion that electrically connects said main electrode to said chip within said opening.

16. a first conductivity type semiconductor region formed in a surface layer portion of the main surface; a body region of a second conductivity type formed in a surface layer portion of the semiconductor region; an impurity region of a first conductivity type formed in a surface layer portion of the body region; a channel formed in a region between the semiconductor region and the impurity region in a surface layer portion of the body region, the gate insulating film covers the channel; the gate electrode faces the channel with the gate insulating film interposed therebetween; the opening is formed along the impurity region, 15. The semiconductor device according to claim 1, wherein said main electrode is electrically connected to said impurity region within said opening.

17. a contact region of a second conductivity type formed in a surface layer portion of the body region in a region different from the impurity region, the opening is formed along the impurity region and the contact region; 17. The semiconductor device according to claim 16, wherein said main electrode is electrically connected to said impurity region and said contact region within said opening.

18. forming a lower insulating film on a main surface of the wafer; forming a plurality of gate electrodes on the lower insulating film; forming a base insulating film on the lower insulating film to cover the plurality of gate electrodes; selectively removing the base insulating film so as to leave covering portions of the base insulating film on side walls of the plurality of gate electrodes, thereby forming a plurality of side wall insulating films respectively covering the side walls of the plurality of gate electrodes; removing exposed portions of the lower insulating film partitioned by the plurality of sidewall insulating films so as to leave portions of the lower insulating film covered by the plurality of gate electrodes as a plurality of gate insulating films, thereby forming openings that expose the main surface; forming a main electrode on the main surface so as to be mechanically connected to the plurality of sidewall insulating films in the openings and electrically connected to the main surface.

19. The method for manufacturing a semiconductor device according to claim 18 , wherein the wafer comprises SiC.

20. forming a base gate electrode on the lower insulating film; forming an upper insulating film on the base gate electrode; selectively removing the upper insulating film and forming a plurality of planar insulating films on the base gate electrode; the step of forming the gate electrode includes a step of removing exposed portions of the base gate electrode that are partitioned by the plurality of planar insulating films, and forming the plurality of gate electrodes, each covered with the plurality of planar insulating films, on the lower insulating film; the base insulating film forming step includes a step of forming the base insulating film so as to collectively cover the plurality of gate electrodes and the plurality of planar insulating films, 20. The method for manufacturing a semiconductor device according to claim 18, wherein the sidewall insulating film forming step includes the step of selectively removing the base insulating film so as to leave covering portions of the base insulating film on sidewalls of the plurality of gate electrodes and sidewalls of the plurality of planar insulating films, and forming a plurality of the sidewall insulating films respectively covering the sidewalls of the plurality of gate electrodes and the sidewalls of the plurality of planar insulating films.