Method for manufacturing semiconductor device, and semiconductor device

Abstract

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes preparing, for example, four semiconductor wafers 40, 50, 60, 70. In this manufacturing method, the semiconductor wafer 40 and the semiconductor wafer 50 are bonded by hybrid bonding to produce a laminated wafer 100. Similarly, the semiconductor wafer 60 and the semiconductor wafer 70 are bonded by hybrid bonding to produce another laminated wafer 110. Subsequently, the laminated wafer 100 and the other laminated wafer 110 are further bonded by hybrid bonding to produce a laminated wafer 120. With this method, processes can be shortened as compared with a case of laminating layers one by one in order, and the effect of the shortening is remarkable especially when the number of layers to be laminated is large.

Description

Semiconductor device manufacturing method and semiconductor device

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device.

[0002] Non-Patent Documents 1 and 2 disclose a method of bonding semiconductor wafers together (wafer-to-wafer bonding) and a method of bonding singulated semiconductor chips to a semiconductor wafer (chip-to-wafer bonding). The method of bonding semiconductor wafers together involves stacking wafers on which multiple semiconductor dies are formed, and has better manufacturing efficiency than a method of bonding singulated semiconductor chips from one semiconductor wafer to another semiconductor wafer. Non-Patent Document 3 discloses a method of sequentially stacking semiconductor wafers one by one as a method of bonding such semiconductor wafers together. Non-Patent Document 4 discloses that 176 semiconductor layers are stacked in a stacked memory using a wire bonding method.

[0003] Adel Elsherbini et al., “Enabling Hybrid Bonding on Intel Process”, 2021 IEEE International Electron Devices Meeting(IEDM), IEDM21-729 to 732Fumihiro Inoue et al., “Advanced Dicing Technologies for Combination of Wafer to Wafer and Collective Die to Wafer Direct Bonding”, 2019 IEEE 69th Electronic Components and Technology Conference(ECTC), pp.437-445TaeSeong Kim et al., “Multi-Stack Wafer Bonding Demonstration utilizing Cu to Cu Hybrid Bonding and TSV enabling Diverse 3D Integration”, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), pp. 415-419“Micron B47R 3D CTF CuA NAND Die, World’s First 176L’195T”, [online], August 19, 2021, [searched on May 14, 2023], Internet <URL : https: / / semiengineering.com / micron-b47r-3d-ctf-cua-nand-die-worlds-first-176l-195t / >S. Yoneda et al., “A Novel Photosensitive Polyimide Adhesive Material for Hybrid Bonding Processing”, 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2021, pp.680-686 Yoshiyuki Nozawa, "Deep Silicon Etching Technology Using a Bosch-Type Etcher," Journal of the Vacuum Society of Japan, Vol. 53, No. 7, pp. 446-453, 2010.

[0004] As described above, in the method of bonding semiconductor wafers, semiconductor wafers are stacked one by one in order, and therefore the time required to fabricate a stack of semiconductor wafers increases in proportion to the number of layers. In particular, when a large number of semiconductor wafers (e.g., 10 or more layers) are stacked, the time required to fabricate the stack becomes significantly longer. Therefore, there is a need for a method that can shorten the time required to fabricate a stack of semiconductor wafers.

[0005] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can shorten the time required to fabricate a stack of semiconductor wafers.

[0006] [1] One aspect of the present disclosure relates to a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the steps of: preparing a first semiconductor wafer having a first semiconductor substrate, a first electrode provided on a first surface of the first semiconductor substrate, a second electrode provided on a second surface of the first semiconductor substrate, and wiring including a first through-electrode that penetrates the first semiconductor substrate and connects the first electrode and the second electrode to each other; preparing a second semiconductor wafer having a second semiconductor substrate, a third electrode provided on the first surface of the second semiconductor substrate, a fourth electrode provided on the second surface of the second semiconductor substrate, and wiring including a second through-electrode that penetrates the second semiconductor substrate and connects the third electrode and the fourth electrode to each other; preparing a fourth semiconductor wafer having a fourth semiconductor substrate, a seventh electrode provided on a first surface of the fourth semiconductor substrate, an eighth electrode provided on a second surface of the fourth semiconductor substrate, and wiring including a fourth through electrode that penetrates the fourth semiconductor substrate and connects the seventh electrode and the eighth electrode to each other; stacking and integrating the first semiconductor wafer and the second semiconductor wafer and connecting the second electrode and the third electrode to prepare a first laminated wafer; stacking and integrating the third semiconductor wafer and the fourth semiconductor wafer and connecting the sixth electrode and the seventh electrode to prepare a second laminated wafer; and stacking and integrating the first laminated wafer and the second laminated wafer and connecting the fourth electrode and the fifth electrode to prepare a third laminated wafer.

[0007] In this semiconductor device manufacturing method, a first semiconductor wafer and a second semiconductor wafer are first stacked to form a first laminated wafer, and a third semiconductor wafer and a fourth semiconductor wafer are stacked to form a second laminated wafer. The first laminated wafer and the second laminated wafer are then further stacked to form a multilayered third laminated wafer. In this case, the number of layers can be doubled, thereby shortening the time required to manufacture a multilayered semiconductor device compared to a method in which layers are stacked one by one.

[0008] [2] In the semiconductor device manufacturing method described in [1] above, a first insulating layer may be provided on the first surface of the first semiconductor substrate, and a second insulating layer may be provided on the second surface of the first semiconductor substrate. Alternatively, a third insulating layer may be provided on the first surface of the second semiconductor substrate, and a fourth insulating layer may be provided on the second surface of the second semiconductor substrate. In the process of fabricating the first laminated wafer, the second insulating layer and the third insulating layer may be bonded and integrated, and the second electrode and the third electrode may be bonded, by applying at least one of heat and pressure. In this case, a so-called hybrid bonding method may be used when stacking and integrating the first semiconductor wafer and the second semiconductor wafer. This allows fine electrodes to be bonded together, and also enables the height of the laminated body to be reduced.

[0009] [3] In the semiconductor device manufacturing method described in [2] above, a fifth insulating layer may be provided on the first surface of the third semiconductor substrate, and a sixth insulating layer may be provided on the second surface of the third semiconductor substrate. A seventh insulating layer may be provided on the first surface of the fourth semiconductor substrate, and an eighth insulating layer may be provided on the second surface of the fourth semiconductor substrate. In the process of fabricating the second laminated wafer, the sixth insulating layer and the seventh insulating layer may be bonded and integrated together, and the sixth electrode and the seventh electrode may be bonded together, by applying at least one of heat and pressure. In the process of fabricating the third laminated wafer, the fourth insulating layer and the fifth insulating layer may be bonded and integrated together, and the fourth electrode and the fifth electrode may be bonded together, by applying at least one of heat and pressure. In this case, a so-called hybrid bonding method may be used when stacking and integrating the third semiconductor wafer and the fourth semiconductor wafer, and when stacking and integrating the first laminated wafer and the second laminated wafer. This allows for bonding of fine electrodes and also enables a low-profile laminate.

[0010] [4] In the semiconductor device manufacturing method of [2] or [3] above, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may contain at least one of an organic insulating material and an inorganic insulating material. When each insulating layer contains an organic insulating material, even if unexpected particles or debris adhere to the bonding surface during hybrid bonding, the organic insulating material can absorb them, reducing bonding defects (see, for example, Non-Patent Document 5). Furthermore, when each insulating layer contains an inorganic insulating material, it is easier to form fine insulating layers and electrodes by using back-end of line (BEOL) wiring technology for connecting semiconductor transistors. Note that the fifth insulating layer, sixth insulating layer, seventh insulating layer, and eighth insulating layer may also contain at least one of an organic insulating material and an inorganic insulating material.

[0011] [5] In the method for manufacturing a semiconductor device according to [4] above, the organic insulating material preferably includes bismaleimide, polyimide, a polyimide precursor, polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or a PBO precursor. In this case, even if the heating temperature when bonding the electrodes in the hybrid bonding method becomes high, softening of the insulating layer, etc., which would hinder bonding between the electrodes, can be suppressed.

[0012] [6] In the method for manufacturing a semiconductor device according to [1] above, in the step of fabricating the first laminated wafer, the second electrode and the third electrode may be joined by solder bumps. In this case, the second electrode and the third electrode can be more reliably joined. Note that in the steps of fabricating the second laminated wafer and the third laminated wafer, the electrodes may be joined by solder bumps in the same manner. Note that solder bump joining using an NCF (Non Conductive Film) may also be used.

[0013] [7] The method for manufacturing a semiconductor device according to any one of [1] to [6] above may further include a step of inspecting the first and second stacked wafers before fabricating the third stacked wafer. In this case, defective semiconductor wafers or semiconductor wafers with a high defect rate are removed, and non-defective semiconductor wafers or semiconductor wafers with a high yield rate are advanced to the next step, thereby improving the yield rate of semiconductor devices overall.

[0014] [8] In the method for manufacturing a semiconductor device according to [7] above, the first stacked wafer may include a plurality of first semiconductor chip regions, the second stacked wafer may include a plurality of second semiconductor chip regions, and in the inspecting step, each of the plurality of first semiconductor chip regions may be inspected and each of the plurality of second semiconductor chip regions may be inspected, and in the step of fabricating the third stacked wafer, a combination of each of the plurality of first semiconductor chip regions and each of the plurality of second semiconductor chip regions may be selected based on the inspection results of the inspecting step. This allows the overall yield rate of semiconductor devices to be further improved by excluding defective semiconductor wafers or semiconductor wafers with a high defect rate and proceeding to the next step with non-defective semiconductor wafers or semiconductor wafers with a high defect rate.

[0015] [9] In the method for manufacturing a semiconductor device according to [8] above, in the step of fabricating the third stacked wafer, the semiconductor chip regions determined to be non-defective in the inspection step may be selected to be superimposed on each other. In this case, the yield rate of the semiconductor device can be further improved.

[0016]

[10] The method for manufacturing a semiconductor device according to any one of [1] to [9] above may further include a step of fabricating a plurality of third laminated wafers by performing the step of fabricating a third laminated wafer two or more times, and a step of fabricating a fourth laminated wafer by stacking the plurality of third laminated wafers. In this case, the time required to fabricate a multilayer semiconductor device can be shortened compared to a method of stacking layers one by one.

[0017]

[11] The method for manufacturing a semiconductor device according to any one of [1] to

[10] above may further include a step of dicing the stack including the third stacked wafer into chip-sized individual pieces to obtain at least one stacked semiconductor chip.

[0018]

[12] One aspect of the present disclosure relates to a semiconductor device, including at least one stacked semiconductor chip manufactured by the semiconductor device manufacturing method according to

[11] above, and a substrate on which the stacked semiconductor chip is mounted.

[0019] According to the present disclosure, the time required to fabricate a stack of semiconductor wafers can be shortened.

[0020] FIG. 1 is a cross-sectional view showing an example of the cross-sectional configuration of a semiconductor device according to one embodiment of the present invention. FIGS. 2A and 2B are cross-sectional views showing a method for manufacturing the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. 1, showing a step performed after the step shown in FIG. 2. FIG. 4 is a diagram for explaining a bonding step that reflects the results of an inspection step. FIG. 5 is a diagram for explaining a bonding step that reflects the results of an inspection step. FIG. 6 is a perspective view for explaining the bonding step of FIGS. 4 and 5.

[0021] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same or equivalent parts will be denoted by the same reference numerals, and duplicate explanations will be omitted. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0022] In this specification, the term "layer" includes not only a structure having a shape formed over the entire surface when observed in a plan view, but also a structure having a shape formed on a portion thereof. In this specification, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes as long as the intended effect of the process is achieved.

[0023] In this specification, numerical ranges indicated using "to" indicate ranges that include the numerical values ​​before and after "to" as the minimum and maximum values, respectively. In numerical ranges described in stages in this specification, the upper or lower limit of a numerical range in one stage may be replaced with the upper or lower limit of a numerical range in another stage. In numerical ranges described in this specification, the upper or lower limit of the numerical range may be replaced with a value shown in the examples.

[0024] FIG. 1 is a diagram illustrating an example of a semiconductor device manufactured by a manufacturing method according to an embodiment of the present invention. As shown in FIG. 1, semiconductor device 1 (corresponding to third stacked wafer 120) is a three-dimensional stack of four semiconductor wafers. Semiconductor device 1 includes five layers of wiring electrodes 11-15, five layers of insulating layers 21-25, and semiconductor substrates 31-34. Wiring electrode 11 is formed in insulating layer 21, wiring electrode 12 is formed in insulating layer 22, wiring electrode 13 is formed in insulating layer 23, wiring electrode 14 is formed in insulating layer 24, and wiring electrode 15 is formed in insulating layer 25. Each of semiconductor substrates 31-34 is, for example, a silicon wafer, and corresponds to semiconductor substrates 41, 51, 61, and 71, described below (see FIG. 2). While semiconductor device 1 illustrated in FIG. 1 illustrates an example in which, for example, four semiconductor wafers are stacked, the present invention is not limited thereto, and a stack of even more semiconductor wafers (e.g., eight-layer semiconductor wafers or sixteen-layer semiconductor wafers) may also be used.

[0025] The semiconductor device 1 is further provided with through electrodes 36 to 39 that penetrate each semiconductor wafer. The through electrode 36 penetrates the semiconductor substrate 31 and connects the wiring electrode 11 to the wiring electrode 12. The through electrode 37 penetrates the semiconductor substrate 32 and connects the wiring electrode 12 to the wiring electrode 13. The through electrode 38 penetrates the semiconductor substrate 33 and connects the wiring electrode 13 to the wiring electrode 14. The through electrode 39 penetrates the semiconductor substrate 34 and connects the wiring electrode 14 to the wiring electrode 15. Each of the through electrodes 36 to 39 is, for example, a through silicon via (TSV). Furthermore, each of the through electrodes 36 to 39 may be configured to directly connect the corresponding wiring electrodes, or may be configured to connect the corresponding wiring electrodes as wiring including two or more through electrodes and electrodes connecting them.

[0026] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Figures 2 and 3. Figures 2(a) and 2(b) are cross-sectional views showing the method for manufacturing the semiconductor device shown in Figure 1. Figure 3 is a cross-sectional view showing the method for manufacturing the semiconductor device shown in Figure 1, illustrating a step performed after the step shown in Figure 2. This manufacturing method includes the following steps [A] to [G].

[0027] Step A: Preparing a first semiconductor wafer having a first semiconductor substrate, a first electrode provided on a first surface of the first semiconductor substrate, a second electrode provided on a second surface of the first semiconductor substrate, and wiring including a first through-electrode that penetrates the first semiconductor substrate and connects the first electrode and the second electrode to each other; Step B: Preparing a second semiconductor wafer having a second semiconductor substrate, a third electrode provided on the first surface of the second semiconductor substrate, a fourth electrode provided on the second surface of the second semiconductor substrate, and wiring including a second through-electrode that penetrates the second semiconductor substrate and connects the third electrode and the fourth electrode to each other; Step C: Preparing a third semiconductor wafer having a third semiconductor substrate, a fifth electrode provided on the first surface of the third semiconductor substrate, a sixth electrode provided on the second surface of the third semiconductor substrate, and wiring including a third through-electrode that penetrates the third semiconductor substrate and connects the fifth electrode and the sixth electrode to each other. Step D: A step of preparing a fourth semiconductor wafer having a fourth semiconductor substrate, a seventh electrode provided on a first surface of the fourth semiconductor substrate, an eighth electrode provided on a second surface of the fourth semiconductor substrate, and wiring including a fourth through-electrode that penetrates the fourth semiconductor substrate and connects the seventh electrode and the eighth electrode to each other. Step E: A step of stacking and integrating the first semiconductor wafer and the second semiconductor wafer, and connecting the second electrode and the third electrode to produce a first laminated wafer. Step F: A step of stacking and integrating the third semiconductor wafer and the fourth semiconductor wafer, and connecting the sixth electrode and the seventh electrode to produce a second laminated wafer. Step G: A step of stacking and integrating the first laminated wafer and the second laminated wafer, and connecting the fourth electrode and the fifth electrode to produce a third laminated wafer.

[0028] 2A, a first semiconductor wafer 40 is prepared. The first semiconductor wafer 40 includes a semiconductor substrate 41 (first semiconductor substrate), a plurality of electrodes 42 (first electrodes) provided on a first surface 41 a of the semiconductor substrate 41, an insulating layer 43 (first insulating layer) provided on the first surface 41 a of the semiconductor substrate 41, a plurality of electrodes 44 (second electrodes) provided on a second surface 41 b of the semiconductor substrate 41, an insulating layer 45 (second insulating layer) provided on the second surface 41 b of the semiconductor substrate 41, and wiring including through electrodes 46 (first through electrodes) that penetrate the semiconductor substrate 41 and connect the electrodes 42, 44 to each other.

[0029] In step A, first, a semiconductor substrate 41 is prepared, which is a silicon substrate on which an integrated circuit consisting of semiconductor elements and wiring connecting them is formed. The thickness of this semiconductor substrate 41 is, for example, 4 μm to 775 μm. Once the semiconductor substrate 41 is prepared, holes are then formed through the semiconductor substrate 41 by a predetermined method, and a plurality of through electrodes 46 are formed to fill the holes. The through electrodes 46 are so-called TSVs, and a known method such as the Bosch process (Non-Patent Document 6) can be used to form them.

[0030] Next, in step A, a plurality of electrodes 42 that will become the wiring electrodes 11 and an insulating layer 43 that will become the insulating layer 21 are formed on the first surface 41a of a semiconductor substrate 41 made of silicon or the like. Each electrode 42 can be formed by, for example, forming resist openings and depositing a conductive material such as copper in the openings by electroplating. The insulating layer 43 can be formed, for example, from an organic insulating material. For example, the insulating layer 43 can be formed by applying liquid polyimide (PI) by spin coating onto the first surface 41a of the semiconductor substrate 41 on which the electrodes 42 are formed and then curing the liquid. The electrodes 42 and the insulating layer 43 may also be formed using other methods. The thickness of the electrodes 42 and the insulating layer 43 is, for example, 1 μm or more and 10 μm or less.

[0031] The organic insulating material used for the insulating layer 43 may be, other than polyimide, a polyimide precursor (e.g., polyimide ester or polyamic acid), polyamideimide, bismaleimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or a PBO precursor. These organic insulating materials including polyimide may be, for example, silicon oxide (SiO ２ ) and is a soft material. By using such an organic material, when bonding organic insulating layers together in steps E to G described below, even if there is fine debris on the insulating layer, it is absorbed into the organic insulating layer, preventing bonding defects caused by the debris, and making it possible to reliably bond the organic insulating layers together. Note that insulating layer 43 may be formed from an inorganic material such as silicon oxide.

[0032] In step A, a plurality of electrodes 44 that will become part of the wiring electrodes 12 and an insulating layer 45 that will become part of the insulating layer 22 are formed on the second surface 41b of the semiconductor substrate 41 made of silicon or the like. The method for forming the electrodes 44 and the insulating layer 45 can be the same as the method for forming the electrodes 42 and the insulating layer 43 described above, and therefore a description thereof will be omitted. In this manner, the first semiconductor wafer 40 is formed. In the example shown in FIG. 2 , the electrodes 42 and 44 are directly connected by the through electrodes 46 in the first semiconductor wafer 40. However, the electrodes 42 and 44 may be connected by wiring including a plurality of through electrodes and electrodes connecting them. The same may be true for the other semiconductor wafers described below.

[0033] [Step B] In step B, a second semiconductor wafer 50 is prepared. The second semiconductor wafer 50 includes a semiconductor substrate 51 (second semiconductor substrate), a plurality of electrodes 52 (third electrodes) provided on a first surface 51 a of the semiconductor substrate 51, an insulating layer 53 (third insulating layer) provided on the first surface 51 a of the semiconductor substrate 51, a plurality of electrodes 54 (fourth electrodes) provided on a second surface 51 b of the semiconductor substrate 51, an insulating layer 55 (fourth insulating layer) provided on the second surface 51 b of the semiconductor substrate 51, and wiring including a plurality of through electrodes 56 (second through electrodes) that penetrate the semiconductor substrate 51 and connect the electrodes 52 and 54 to each other. In step B, the materials and methods of forming the electrodes 52 and 54, the insulating layers 53 and 55, and the through electrodes 56 in the second semiconductor wafer 50 are the same as those in the first semiconductor wafer 40, and therefore detailed description thereof will be omitted. 1, the electrodes 52 on the second semiconductor wafer 50 form part of the wiring electrodes 12 of the semiconductor device 1 shown in Fig. 1, and the insulating layer 53 forms part of the insulating layer 22. The electrodes 54 on the second semiconductor wafer 50 form part of the wiring electrodes 13 of the semiconductor device 1 shown in Fig. 1, and the insulating layer 55 forms part of the insulating layer 23.

[0034] [Step C] In step C, a third semiconductor wafer 60 is prepared. The third semiconductor wafer 60 includes a semiconductor substrate 61 (third semiconductor substrate), a plurality of electrodes 62 (fifth electrodes) provided on a first surface 61 a of the semiconductor substrate 61, an insulating layer 63 (fifth insulating layer) provided on the first surface 61 a of the semiconductor substrate 61, a plurality of electrodes 64 (sixth electrodes) provided on a second surface 61 b ​​of the semiconductor substrate 61, an insulating layer 65 (sixth insulating layer) provided on the second surface 61 b ​​of the semiconductor substrate 61, and wiring including a plurality of through electrodes 66 (third through electrodes) that penetrate the semiconductor substrate 61 and connect the electrodes 62, 64 to each other. In step C, the materials and methods of forming the electrodes 62, 64, the insulating layers 63, 65, and the through electrodes 66 in the third semiconductor wafer 60 are the same as those in the first semiconductor wafer 40, and therefore detailed description thereof will be omitted. 1, the electrode 62 on the third semiconductor wafer 60 constitutes a part of the wiring electrode 13 of the semiconductor device 1 shown in Fig. 1, and the insulating layer 63 constitutes a part of the insulating layer 23. Furthermore, the electrode 64 on the third semiconductor wafer 60 constitutes a part of the wiring electrode 14 of the semiconductor device 1 shown in Fig. 1, and the insulating layer 65 constitutes a part of the insulating layer 24.

[0035] [Step D] In step D, a fourth semiconductor wafer 70 is prepared. The fourth semiconductor wafer 70 includes a semiconductor substrate 71 (fourth semiconductor substrate), a plurality of electrodes 72 (seventh electrodes) provided on a first surface 71 a of the semiconductor substrate 71, an insulating layer 73 (seventh insulating layer) provided on the first surface 71 a of the semiconductor substrate 71, a plurality of electrodes 74 (eighth electrodes) provided on a second surface 71 b of the semiconductor substrate 71, an insulating layer 75 (eighth insulating layer) provided on the second surface 71 b of the semiconductor substrate 71, and wiring including a plurality of through electrodes 76 (fourth through electrodes) that penetrate the semiconductor substrate 71 and connect the electrodes 72 and 74 to each other. In step D, the materials and methods of forming the electrodes 72 and 74, the insulating layers 73 and 75, and the through electrodes 76 in the fourth semiconductor wafer 70 are the same as those in the first semiconductor wafer 40, and therefore detailed description thereof will be omitted. 1, the electrodes 72 on the fourth semiconductor wafer 70 form part of the wiring electrodes 14 of the semiconductor device 1 shown in Fig. 1, and the insulating layer 73 forms part of the insulating layer 24. The electrodes 74 on the fourth semiconductor wafer 70 form part of the wiring electrodes 15 of the semiconductor device 1 shown in Fig. 1, and the insulating layer 75 forms part of the insulating layer 25.

[0036] [Step E] In step E, as shown in FIGS. 2A and 2B, once the preparation of the first semiconductor wafer 40 and the second semiconductor wafer 50 is complete, the first semiconductor wafer 40 and the second semiconductor wafer 50 are stacked and integrated, and the electrodes 44 and the electrodes 52 are connected to produce the first stacked wafer 100. That is, the first semiconductor wafer 40 and the second semiconductor wafer 50 are heated and pressurized to integrate them through hybrid bonding. The heating temperature for the first semiconductor wafer 40 and the second semiconductor wafer 50 is, for example, 150°C to 400°C, and the pressure is 0.04 MPa to 10 MPa. This bonding firmly bonds (connects) the insulating layer 45 of the first semiconductor wafer 40 to the insulating layer 53 of the second semiconductor wafer 50, and also firmly bonds (connects) the electrodes 44 of the first semiconductor wafer 40 to the electrodes 52 of the second semiconductor wafer. The electrode 44 and the electrode 52 are joined to form the electrode 104 shown in Fig. 2(b). The electrode 104 is connected to both the through electrodes 46 and 56, and electrically connects the electrode 42 and the electrode 54. The electrode 104 corresponds to the wiring electrode 12 shown in Fig. 1.

[0037] [Step F] In step F, as shown in FIGS. 2A and 2B, once the preparation of the third semiconductor wafer 60 and the fourth semiconductor wafer 70 is complete, the third semiconductor wafer 60 and the fourth semiconductor wafer 70 are stacked and integrated, and the electrodes 64 and 72 are connected to form the second laminated wafer 110. That is, the third semiconductor wafer 60 and the fourth semiconductor wafer 70 are heated and pressurized to integrate them through hybrid bonding. The heating temperature for the third semiconductor wafer 60 and the fourth semiconductor wafer 70 is, for example, 150°C to 400°C, and the pressure is 0.04 MPa to 10 MPa. This bonding firmly bonds (connects) the insulating layer 65 of the third semiconductor wafer 60 to the insulating layer 73 of the fourth semiconductor wafer 70, and also firmly bonds (connects) the electrodes 64 of the third semiconductor wafer 60 to the electrodes 72 of the fourth semiconductor wafer 70. The electrode 64 and the electrode 72 are joined to form the electrode 114 shown in Fig. 2(b). The electrode 114 is connected to both the through electrodes 66 and 76, and electrically connects the electrode 62 and the electrode 74. The electrode 114 corresponds to the wiring electrode 14 shown in Fig. 1.

[0038] [Process G] In Process G, as shown in FIG. 3 , once the preparation of the first laminated wafer 100 and the second laminated wafer 110 is complete, the first laminated wafer 100 and the second laminated wafer 110 are stacked and integrated, and the electrodes 54 and 62 are connected to form the third laminated wafer 120. That is, the first laminated wafer 100 and the second laminated wafer 110 are heated and pressurized to integrate the two through hybrid bonding. The heating temperature for the first laminated wafer 100 and the second laminated wafer 110 is, for example, 150°C to 400°C, and the pressure is 0.04 MPa to 10 MPa. This bonding firmly bonds (connects) the insulating layer 55 of the first laminated wafer 100 to the insulating layer 63 of the second laminated wafer 110, and also firmly bonds (connects) the electrodes 54 of the first laminated wafer 100 to the electrodes 62 of the second laminated wafer 110. The electrode 54 and the electrode 62 are joined to form the wiring electrode 13 shown in Fig. 1. The wiring electrode 13 is connected to both the through electrodes 56 and 66, and the electrodes 42, 44, 52, 54, 62, 64, 72, and 74 are electrically connected to one another.

[0039] In this way, a semiconductor device 1 is formed, which is a stack of four semiconductor wafers (see also FIG. 1 ). After the semiconductor device 1 is formed, the semiconductor device 1 may be diced into individual chip-sized pieces by dicing or the like to obtain a large number of stacked semiconductor chips (at least one stacked semiconductor chip). In this case, the individual stacked semiconductor chips can be mounted on another semiconductor substrate or the like to form a semiconductor device.

[0040] As described above, in the method for manufacturing a semiconductor device according to this embodiment, first, the first semiconductor wafer 40 and the second semiconductor wafer 50 are stacked together to produce the first laminated wafer 100, and then the third semiconductor wafer 60 and the fourth semiconductor wafer 70 are stacked together to produce the second laminated wafer 110. The first laminated wafer 100 and the second laminated wafer 110 are then stacked together to produce the multilayered third laminated wafer 120. According to this manufacturing method, the number of layers can be multiplied in increments, and therefore the time required to manufacture a multilayered semiconductor device can be shortened compared to a method in which layers are stacked one by one in order.

[0041] In the semiconductor device manufacturing method according to this embodiment, an insulating layer 43 is provided on the first surface 41a of the semiconductor substrate 41, an insulating layer 45 is provided on the second surface 41b of the semiconductor substrate 41, an insulating layer 53 is provided on the first surface 51a of the semiconductor substrate 51, and an insulating layer 55 is provided on the second surface 51b of the semiconductor substrate 51. In this manufacturing method, in the process of fabricating the first laminated wafer 100, heat and pressure are applied to bond and integrate the insulating layer 45 and the insulating layer 53, and also to bond the electrode 44 and the electrode 52. This allows the so-called hybrid bonding method to be used when stacking and integrating the first semiconductor wafer 40 and the second semiconductor wafer 50. This allows for bonding of fine electrodes and also enables the achievement of a low-profile laminate.

[0042] In the method for manufacturing a semiconductor device according to this embodiment, an insulating layer 63 is further provided on the first surface 61a of the semiconductor substrate 61, an insulating layer 65 is provided on the second surface 61b of the semiconductor substrate 61, an insulating layer 73 is provided on the first surface 71a of the semiconductor substrate 71, and an insulating layer 75 is provided on the second surface 71b of the semiconductor substrate 71. In the process of fabricating the second laminated wafer 110, heat and pressure are applied to bond and integrate the insulating layer 65 and the insulating layer 73, and to bond the electrode 64 and the electrode 72. In the process of fabricating the third laminated wafer 120, heat and pressure are applied to bond and integrate the insulating layer 55 and the insulating layer 63, and to bond the electrode 54 and the electrode 62. This allows a so-called hybrid bonding method to be used when stacking and integrating the third semiconductor wafer 60 and the fourth semiconductor wafer 70, and when stacking and integrating the first laminated wafer 100 and the second laminated wafer 110. Therefore, it is possible to bond fine electrodes to each other, and also to realize a low-profile laminate.

[0043] In the semiconductor device manufacturing method according to this embodiment, each of the insulating layers 43, 45, 53, 55, 63, 65, 73, and 75 contains an organic insulating material. This allows the organic insulating material to absorb debris that adheres to the bonding surfaces during hybrid bonding, thereby reducing bonding defects. Furthermore, if each of the insulating layers 43, 45, 53, 55, 63, 65, 73, and 75 contains an inorganic insulating material, it becomes easier to form fine insulating layers and electrodes.

[0044] In the method for manufacturing a semiconductor device according to this embodiment, the organic insulating material constituting each of the insulating layers 43, 45, 53, 55, 63, 65, 73, and 75 preferably includes bismaleimide, polyimide, a polyimide precursor, polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or a PBO precursor. In this case, even if the heating temperature when bonding each electrode in the hybrid bonding method becomes high, softening of the insulating layer, which would hinder bonding between each electrode, can be suppressed.

[0045] It is also possible to produce two or more third laminated wafers 120 (see FIG. 3 ) by bonding the first laminated wafer 100 and the second laminated wafer 110 together (two or more times), and then further stack the two third laminated wafers 120 using hybrid bonding, as in the bonding of the first laminated wafer 100 and the second laminated wafer 110, to form a fourth laminated wafer. In this case, a semiconductor device (fourth laminated wafer) in which eight semiconductor wafers are stacked can be obtained, and this can be produced efficiently.

[0046] Although the embodiments of the present disclosure have been described above, the present invention is not limited to the above-described embodiments and may be modified as appropriate without departing from the spirit of the present disclosure. For example, in the above-described embodiments, examples have been described in which the stacking and bonding of semiconductor wafers and the stacking and bonding of laminated semiconductor wafers are performed using hybrid bonding, but the present disclosure is not limited to this. For example, in the process of producing the first laminated wafer 100, the electrodes 44 and 52 may be bonded using solder bumps. This method also ensures reliable bonding of the electrodes 44 and 52. In this case, solder bump bonding using a non-conductive film (NCF) may be used, or underfill may be injected between the wafers where the electrodes are bonded. Furthermore, in the process of producing the second laminated wafer 110 and the process of producing the third laminated wafer 120, the electrodes may be bonded using solder bumps in the same manner.

[0047] Furthermore, in the semiconductor device manufacturing method described above, each semiconductor wafer is laminated and bonded together as a unit. Therefore, in the semiconductor device manufacturing method according to this embodiment, before fabricating the wafer stack (e.g., before laminating the first laminated wafer 100 and the second laminated wafer 110 as shown in FIG. 6 ), a continuity test may be performed on the semiconductor chip regions 100a-100h (plurality of first semiconductor chip regions) and the semiconductor chip regions 110a-110h (plurality of second semiconductor chip regions) included in each laminated wafer, as shown in FIG. 4 . In this case, each laminated wafer is a large-sized wafer including multiple semiconductor chip regions (regions that will become semiconductor chips when singulated), and the continuity test is performed by testing the continuity and insulation of each semiconductor chip region from both sides of the laminated wafer using a fraying probe or the like. If the continuity test results in a semiconductor chip region being determined to be defective (Fail) (see FIG. 5 ), the overall yield rate can be improved by not manufacturing that portion or not using that substrate. Fig. 4 shows a case where all semiconductor chip areas are good (OK), while Fig. 5 shows a case where some wiring portions are defective (Fail). In the example of Fig. 5, for example, selection is performed so that semiconductor chip areas determined to be good (OK) are overlapped with each other, and for example, semiconductor chip areas 100d, 110d, semiconductor chip areas 100e, 110e, semiconductor chip areas 100f, 110f, and semiconductor chip areas 100g, 110g can be used in subsequent products, while the other semiconductor chip areas can be prevented from being used in subsequent manufacturing.

[0048] Alternatively, multiple first laminated wafers 100 and multiple second laminated wafers 110 may be prepared, and combinations of the first laminated wafers 100 and the second laminated wafers 110 may be selected to increase the number of combinations in which the semiconductor chip regions are determined to be good overall. For example, in FIG. 5 , only four semiconductor chip regions were determined to be good overall because one first laminated wafer 100 and one second laminated wafer 110 were simply combined. However, by preparing a larger number of laminated wafers, the rate of good combinations can be increased, thereby increasing the overall yield of combinations. This selection process may be performed by using a computer to calculate the yield (yield) of all semiconductor wafers or laminated semiconductor wafers combined, or other processing methods may be used. In this way, by eliminating defective semiconductor wafers or semiconductor wafers with a high defect rate and proceeding to the next process with good semiconductor wafers or semiconductor wafers with a high defect rate, the overall yield of semiconductor devices can be improved.

[0049] Furthermore, when the third laminated wafer 120 thus inspected and fabricated is further laminated, a continuity test may be similarly performed in advance, and the optimal combination may be selected and laminated based on the test results. The inspection process and non-defective product selection process described above have been described using the example of bonding the first laminated wafer 100 and the second laminated wafer 110 together, but this is not limiting, and the process may also be applied when bonding the first semiconductor wafer 40 and the second semiconductor wafer 50 together, or when bonding the third semiconductor wafer 60 and the fourth semiconductor wafer 70 together. By performing such inspection and selection processes, the yield rate can be reliably improved.

[0050] 1...semiconductor device (third laminated wafer), 40...first semiconductor wafer, 41...semiconductor substrate (first semiconductor substrate), 41a...first surface, 41b...second surface, 42...electrode (first electrode), 43...insulating layer (first insulating layer), 44...electrode (second electrode), 45...insulating layer (second insulating layer), 46...through electrode (first through electrode), 50...second semiconductor wafer, 51...semiconductor substrate (second semiconductor substrate), 51a...first surface, 51b...second surface, 52...electrode (third electrode), 53...insulating layer (third insulating layer), 54...electrode (fourth electrode), 55...insulating layer (fourth insulating layer), 56...through electrode (second through electrode), 60...third semiconductor wafer Eha, 61...semiconductor substrate (third semiconductor substrate), 61a...first surface, 61b...second surface, 62...electrode (fifth electrode), 63...insulating layer (fifth insulating layer), 64...electrode (sixth electrode), 65...insulating layer (sixth insulating layer), 66...through electrode (third through electrode), 70...fourth semiconductor wafer, 71...semiconductor substrate (fourth semiconductor substrate), 71a...first surface, 71b...second surface, 72...electrode (seventh electrode), 73...insulating layer (seventh insulating layer), 74...electrode (eighth electrode), 75...insulating layer (eighth insulating layer), 76...through electrode (fourth through electrode), 100...first laminated wafer, 110...second laminated wafer, 120...third laminated wafer.

Claims

1. A step of preparing a first semiconductor wafer having a first semiconductor substrate, a first electrode provided on a first surface of the first semiconductor substrate, a second electrode provided on a second surface of the first semiconductor substrate, and wiring including a first through electrode that penetrates the first semiconductor substrate and connects the first electrode and the second electrode to each other, A step of preparing a second semiconductor wafer having a second semiconductor substrate, a third electrode provided on the first surface of the second semiconductor substrate, a fourth electrode provided on the second surface of the second semiconductor substrate, and wiring including a second through-electrode that penetrates the second semiconductor substrate and connects the third electrode and the fourth electrode to each other, A step of preparing a third semiconductor wafer having a third semiconductor substrate, a fifth electrode provided on the first surface of the third semiconductor substrate, a sixth electrode provided on the second surface of the third semiconductor substrate, and wiring including a third through-electrode that penetrates the third semiconductor substrate and connects the fifth electrode and the sixth electrode to each other, A step of preparing a fourth semiconductor wafer having a fourth semiconductor substrate, a seventh electrode provided on the first surface of the fourth semiconductor substrate, an eighth electrode provided on the second surface of the fourth semiconductor substrate, and wiring including a fourth through-electrode that penetrates the fourth semiconductor substrate and connects the seventh electrode and the eighth electrode to each other, A process of stacking the first semiconductor wafer and the second semiconductor wafer together to form a single unit, and connecting the second electrode and the third electrode to produce a first stacked wafer, A step of stacking the third semiconductor wafer and the fourth semiconductor wafer together to form a single unit, and connecting the sixth electrode and the seventh electrode to produce a second stacked wafer, A step of stacking the first stacked wafer and the second stacked wafer together to form a single unit, and connecting the fourth electrode and the fifth electrode to produce a third stacked wafer, A method for manufacturing a semiconductor device, comprising:

2. A first insulating layer is provided on the first surface of the first semiconductor substrate, and a second insulating layer is provided on the second surface of the first semiconductor substrate. A third insulating layer is provided on the first surface of the second semiconductor substrate, and a fourth insulating layer is provided on the second surface of the second semiconductor substrate. In the process of manufacturing the first stacked wafer, the second insulating layer and the third insulating layer are joined and integrated by applying at least one of heating and / or pressurizing, and the second electrode and the third electrode are joined together. A method for manufacturing a semiconductor device according to claim 1.

3. A fifth insulating layer is provided on the first surface of the third semiconductor substrate, and a sixth insulating layer is provided on the second surface of the third semiconductor substrate. A seventh insulating layer is provided on the first surface of the fourth semiconductor substrate, and an eighth insulating layer is provided on the second surface of the fourth semiconductor substrate. In the process of manufacturing the second stacked wafer, the sixth insulating layer and the seventh insulating layer are joined and integrated by applying at least one of heating and / or pressurizing, and the sixth electrode and the seventh electrode are joined together. In the process of manufacturing the third stacked wafer, the fourth insulating layer and the fifth insulating layer are joined and integrated by applying at least one of heating and / or pressurizing, and the fourth electrode and the fifth electrode are joined together. The method for manufacturing a semiconductor device according to claim 2.

4. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer each contain at least one of an organic insulating material and an inorganic insulating material. The method for manufacturing a semiconductor device according to claim 2.

5. The aforementioned organic insulating material includes bismaleimide, polyimide, polyimide precursor, polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or PBO precursor. The method for manufacturing a semiconductor device according to claim 4.

6. In the process of manufacturing the first stacked wafer, the second electrode and the third electrode are joined by solder bumps. A method for manufacturing a semiconductor device according to claim 1.

7. The process further includes inspecting the first and second stacked wafers before manufacturing the third stacked wafer. A method for manufacturing a semiconductor device according to any one of claims 1 to 6.

8. The first stacked wafer includes a plurality of first semiconductor chip regions, The second stacked wafer includes a plurality of second semiconductor chip regions, In the inspection process described above, each of the plurality of first semiconductor chip regions is inspected, and each of the plurality of second semiconductor chip regions is inspected. In the process of manufacturing the third stacked wafer, a combination of each of the plurality of first semiconductor chip regions and each of the plurality of second semiconductor chip regions is selected based on the inspection results in the inspection process. The method for manufacturing a semiconductor device according to claim 7.

9. In the process of manufacturing the third stacked wafer, selection is made so that the semiconductor chip regions that were judged to be good products in the inspection process are superimposed on each other. The method for manufacturing a semiconductor device according to claim 8.

10. A step of producing multiple third stacked wafers by performing the above-mentioned step of producing a third stacked wafer two or more times, The process further comprises stacking the aforementioned plurality of third stacked wafers to produce a fourth stacked wafer. A method for manufacturing a semiconductor device according to any one of claims 1 to 6.

11. The method further comprises the step of separating the stack including the third stacked wafer into chip-sized pieces to obtain at least one stacked semiconductor chip. A method for manufacturing a semiconductor device according to any one of claims 1 to 6.

12. At least one stacked semiconductor chip manufactured by the semiconductor device manufacturing method described in claim 11, A substrate on which the aforementioned multilayer semiconductor chip is mounted, A semiconductor device equipped with a semiconductor device.