Electronic device and method for manufacturing electronic device

Abstract

An electronic device (1) includes: a substrate (110) having a recess (112) on a first surface; a first superconducting wire (121), a portion of which contacts the first surface; a second superconducting wire (122) that, in plan view from above the recess, intersects the first superconducting wire and a portion of which contacts the first surface; an insulating film (130) provided between the first superconducting wire and the second superconducting wire; and a first support member (151) that is provided in the recess and supports at least one of the first superconducting wire and the second superconducting wire. In plan view, a space between a region, where the first superconducting wire intersects the second superconducting wire, and the bottom surface (145) of the recess is hollow.

Description

Electronic device and method for manufacturing the same

[0001] The present disclosure relates to electronic devices and methods for manufacturing electronic devices.

[0002] Quantum computers may use electronic devices with qubits that include Josephson junctions. In conventional electronic devices, Josephson junctions are formed on a substrate such as a silicon substrate.

[0003] Special table 2020-503690 Publication Special table 2022-528146 Publication Special table 2020-535461

[0004] To improve the fidelity of quantum computers, longer coherence times are required for quantum bits containing Josephson junctions (JJs). However, in conventional electronic devices, JJs are susceptible to defects called two-level systems (TLS) present in the substrate, making it difficult to extend the coherence time.

[0005] An object of the present disclosure is to provide an electronic device capable of suppressing the influence of a two-level system and a method for manufacturing the electronic device.

[0006] According to one aspect of the present disclosure, there is provided an electronic device comprising: a substrate having a recessed portion on a first surface; a first superconducting wiring having a portion in contact with the first surface; a second superconducting wiring that intersects with the first superconducting wiring above the recessed portion in a planar view and has a portion in contact with the first surface; an insulating film provided between the first superconducting wiring and the second superconducting wiring; and a first support member provided within the recessed portion and supporting at least one of the first superconducting wiring or the second superconducting wiring, wherein a hollow is provided between a region where the first superconducting wiring and the second superconducting wiring intersect in a planar view and a bottom surface of the recessed portion.

[0007] According to the present disclosure, the influence of the two-level system can be suppressed.

[0008] FIG. 1 is a perspective view showing an electronic device according to a first embodiment. FIG. 2 is a cross-sectional view (part 1) showing the electronic device according to the first embodiment. FIG. 3 is a cross-sectional view (part 2) showing the electronic device according to the first embodiment. FIG. 4 is a plan view (part 1) showing a method for manufacturing an electronic device according to the first embodiment. FIG. 5 is a plan view (part 2) showing a method for manufacturing an electronic device according to the first embodiment. FIG. 6 is a plan view (part 3) showing a method for manufacturing an electronic device according to the first embodiment. FIG. 7 is a plan view (part 4) showing a method for manufacturing an electronic device according to the first embodiment. FIG. 8 is a plan view (part 5) showing a method for manufacturing an electronic device according to the first embodiment. FIG. 9 is a plan view (part 6) showing a method for manufacturing an electronic device according to the first embodiment. FIG. 10 is a plan view (part 7) showing a method for manufacturing an electronic device according to the first embodiment. FIG. 11 is a plan view (part 8) showing a method for manufacturing an electronic device according to the first embodiment. FIG. 12 is a plan view (part 9) showing a method for manufacturing an electronic device according to the first embodiment. FIG. 13 is a plan view (part 10) showing a method for manufacturing an electronic device according to the first embodiment. FIG. 14 is a plan view (part 11) illustrating the method for manufacturing an electronic device according to the first embodiment. FIG. 15 is a cross-sectional view (part 1) illustrating the method for manufacturing an electronic device according to the first embodiment. FIG. 16 is a cross-sectional view (part 2) illustrating the method for manufacturing an electronic device according to the first embodiment. FIG. 17 is a cross-sectional view (part 3) illustrating the method for manufacturing an electronic device according to the first embodiment. FIG. 18 is a cross-sectional view (part 4) illustrating the method for manufacturing an electronic device according to the first embodiment. FIG. 19 is a cross-sectional view (part 5) illustrating the method for manufacturing an electronic device according to the first embodiment. FIG. 20 is a cross-sectional view (part 6) illustrating the method for manufacturing an electronic device according to the first embodiment. FIG. 21 is a cross-sectional view (part 7) illustrating the method for manufacturing an electronic device according to the first embodiment. FIG. 22 is a cross-sectional view (part 8) illustrating the method for manufacturing an electronic device according to the first embodiment. FIG. 23 is a cross-sectional view (part 9) illustrating the method for manufacturing an electronic device according to the first embodiment. FIG. 24 is a cross-sectional view (part 10) illustrating the method for manufacturing an electronic device according to the first embodiment. FIG. 25 is a cross-sectional view (part 11) illustrating the method for manufacturing an electronic device according to the first embodiment.Fig. 26 is a perspective view showing an electronic device according to a second embodiment, Fig. 27 is a perspective view showing an electronic device according to a third embodiment, and Fig. 28 is a diagram showing a quantum processing device according to a fourth embodiment.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that in this specification and drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In this disclosure, the X1-X2 direction, the Y1-Y2 direction, and the Z1-Z2 direction are defined as mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction will be referred to as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction will be referred to as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction will be referred to as the ZX plane. For convenience, the Z1-Z2 direction will be defined as the up-down direction, with the Z1 side referred to as the upper side and the Z2 side referred to as the lower side. Furthermore, a planar view refers to viewing an object from the Z1 side, and a planar shape refers to the shape of an object viewed from the Z1 side.

[0010] First Embodiment A first embodiment will be described. The first embodiment relates to an electronic device. Fig. 1 is a perspective view showing an electronic device according to the first embodiment. Figs. 2 and 3 are cross-sectional views showing the electronic device according to the first embodiment.

[0011] As shown in FIGS. 1 to 3, the electronic device 1 according to the first embodiment includes a substrate 110, superconducting wiring 121, superconducting wiring 122, an insulating film 130, a support member 151, and a support member 152.

[0012] The substrate 110 is, for example, a silicon substrate or a sapphire substrate. A recess 112 is formed on the top surface 111 of the substrate 110. The top surface 111 is a surface parallel to the XY plane. The recess 112 has a rectangular planar shape with two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction. For example, the depth of the recess 112 (dimension in the Z1-Z2 direction) is constant. The recess 112 has sidewall surfaces 141 and 142 parallel to the YZ plane, sidewall surfaces 143 and 144 parallel to the ZX plane, and a bottom surface 145 parallel to the XY plane. The sidewall surface 141 is located closer to the X1 side than the sidewall surface 142, and the sidewall surface 143 is located closer to the Y1 side than the sidewall surface 144. The top surface 111 is an example of a first surface.

[0013] The support members 151 and 152 are made of, for example, silicon oxide (SiO ２ ) membranes. Support members 151 and 152 are provided in recess 112. The height (thickness) of support members 151 and 152 is preferably equal to the depth of recess 112, but may be greater or less than the depth of recess 112. Support member 151 is disposed near side wall surface 141, and support member 152 is disposed near side wall surface 144. The distance between support member 151 and side wall surface 141 is smaller than the distance between support member 151 and side wall surface 142, and the distance between support member 151 and side wall surface 143 is larger than the distance between support member 151 and side wall surface 144. The distance between support member 152 and side wall surface 143 is larger than the distance between support member 152 and side wall surface 144, and the distance between support member 152 and side wall surface 141 is smaller than the distance between support member 152 and side wall surface 142. Furthermore, the distance between support member 151 and side wall surface 141 is smaller than the distance between support member 152 and side wall surface 141, and the distance between support member 152 and side wall surface 144 is smaller than the distance between support member 151 and side wall surface 144. Support member 151 is an example of a first support member, and support member 152 is an example of a second support member.

[0014] The superconducting wiring 121 and the superconducting wiring 122 are, for example, aluminum (Al) films. The superconducting wiring 121 extends along the X1-X2 direction. A portion of the superconducting wiring 121 contacts a portion of the upper surface 111 of the substrate 110 that is closer to the X2 side than the side wall surface 142. In a plan view, the superconducting wiring 121 is spaced apart from the side wall surfaces 141, 143, and 144 and does not overlap with the side wall surfaces 141, 143, and 144. The X1-side end of the superconducting wiring 121 is supported by a support member 151. The superconducting wiring 122 extends along the Y1-Y2 direction. A portion of the superconducting wiring 122 contacts a portion of the upper surface 111 of the substrate 110 that is closer to the Y1 side than the side wall surface 143. The superconducting wiring 122 is separated from the side wall surfaces 141, 142, and 144 in plan view and does not overlap with the side wall surfaces 141, 142, and 144. The end of the superconducting wiring 122 on the Y2 side is supported by a support member 152.

[0015] In plan view, the superconducting wiring 121 and the superconducting wiring 122 intersect with each other. That is, in plan view, a portion of the superconducting wiring 121 between the support member 151 and the side wall surface 142 and a portion of the superconducting wiring 122 between the support member 152 and the side wall surface 143 overlap with each other in the Z1-Z2 direction. The superconducting wiring 121 is an example of a first superconducting wiring, and the superconducting wiring 122 is an example of a second superconducting wiring.

[0016] The insulating film 130 is made of, for example, aluminum oxide (Al ２ O ３ ) film. The insulating film 130 is provided between the superconducting wiring 121 and the superconducting wiring 122. The insulating film 130 is provided between the superconducting wiring 121 and the superconducting wiring 122 in a region where the superconducting wirings 121 and 122 overlap each other. The insulating film 130 contacts the superconducting wiring 121 and the superconducting wiring 122. The insulating film 130 may cover other parts of the superconducting wiring 121. The thickness of the insulating film 130 is such that a tunnel effect can occur between the superconducting wiring 121 and the superconducting wiring 122. The insulating film 130 covers the top and side surfaces of the superconducting wiring 121, but is not shown in FIG. 1 except for the portion between the superconducting wiring 121 and the superconducting wiring 122.

[0017] In the electronic device 1, the region where the superconducting wires 121 and 122 intersect in a plan view functions as a superconducting Josephson junction element in an extremely low temperature environment of, for example, about 10 mK. A space 113 exists between the region functioning as the superconducting Josephson junction element and the bottom surface 145 of the recess 112. In other words, there is a hollow space between the region functioning as the superconducting Josephson junction element and the bottom surface 145 of the recess 112.

[0018] If the recess 112 is not formed in the substrate 110 and the superconducting wiring 121 and the superconducting wiring 122 are formed directly on the upper surface 111, the region functioning as a superconducting Josephson junction element will be in direct contact with the substrate 110. If the substrate 110 is a silicon substrate, oxides will inevitably be present on the upper surface 111 due to natural oxidation. The oxides act as defects known as two-level systems (TLS) with respect to the Josephson junction element, absorbing energy from the Josephson junction element and shortening the coherence time of the quantum bit having the Josephson junction element. A shorter coherence time shortens the time for which the quantum entanglement state is maintained, shortening the time during which quantum calculations can be performed in a quantum computer having quantum bits, and reducing fidelity.

[0019] On the other hand, in this embodiment, there is a hollow space between the region that functions as a superconducting Josephson junction element and the bottom surface 145 of the recess 112. Therefore, even if an oxide exists on the bottom surface 145, the influence of TLS can be suppressed.

[0020] Furthermore, because the superconducting wire 121 is supported by the support member 151 and the superconducting wire 122 is supported by the support member 152, the shapes of the superconducting wires 121 and 122 are stable even above the recessed portion 112. Furthermore, the relative dielectric constant of the material of the support member 151 and the support member 152, for example, silicon oxide, is lower than the relative dielectric constant of the material of the substrate 110, for example, silicon, so that the parasitic capacitance between the superconducting wire 121 and the substrate 110 and the parasitic capacitance between the superconducting wire 122 and the substrate 110 can be kept low. Furthermore, even if the material of the support member 151 and the support member 152 is an oxide, the support member 151 and the support member 152 are separated from the Josephson junction device, and therefore the influence of the TLS present in the support member 151 and the support member 152 is unlikely to affect the Josephson junction device.

[0021] Furthermore, since the superconducting wires 121 and 122 intersect with each other in a plan view, the superconducting wires 121 and 122 can be easily formed with high precision as described below.

[0022] Next, a method for manufacturing an electronic device according to the first embodiment will be described. Figures 4 to 14 are plan views illustrating the method for manufacturing an electronic device according to the first embodiment, and Figures 15 to 25 are cross-sectional views illustrating the method for manufacturing an electronic device according to the first embodiment.

[0023] First, as shown in Figures 4 and 15, a substrate 110 is prepared, and a mask 191 is formed on the upper surface 111 of the substrate 110. The mask 191 has an opening 191A that exposes an area in which the recessed portion 112 of the substrate 110 will be formed. The mask 191 is, for example, a resist mask. Figure 15 corresponds to a cross-sectional view taken along line XV-XV in Figure 4.

[0024] 5 and 16, the portion of the substrate 110 exposed from the opening 191A is etched to form a recess 112 in the upper surface 111. The etching of the substrate 110 may be either wet etching or dry etching. FIG. 16 corresponds to a cross-sectional view taken along line XVI-XVI in FIG. 5.

[0025] 6 and 17, the mask 191 is removed, and a resin layer 160 is formed on the substrate 110 so as to fill the inside of the recessed portion 112. The resin layer 160 is, for example, a polyimide layer. To form the resin layer 160, for example, a polyimide resin is applied and thermally cured. FIG. 17 corresponds to a cross-sectional view taken along line XVII-XVII in FIG. 6.

[0026] 7 and 18, the resin layer 160 is etched back so that the resin layer 160 remains in the recessed portion 112. As a result, a filling member 161 made of the resin layer 160 is formed in the recessed portion 112. In the etch back of the resin layer 160, for example, oxygen (O ２ 18 corresponds to a cross-sectional view taken along line XVIII-XVIII in FIG.

[0027] Next, as shown in FIGS. 8 and 19 , a mask 192 is formed on the substrate 110 and the filling member 161. The mask 192 has an opening 192A exposing the region where the support member 151 is to be formed and an opening 192B exposing the region where the support member 152 is to be formed. The mask 192 is, for example, a resist mask. Thereafter, the portions of the filling member 161 exposed from the opening 192A and the portions exposed from the opening 192B are etched to form openings 171 and 172 in the filling member 161. The opening 171 is connected to the opening 192A, and the opening 172 is connected to the opening 192B. The filling member 161 is etched by, for example, dry etching. FIG. 19 corresponds to a cross-sectional view taken along line XIX-XIX in FIG. 8 .

[0028] 9 and 20, the mask 192 is removed, and a film 155 of the material of the support members 151 and 152 is formed on the substrate 110 and the filling member 161 so as to fill the inside of the opening 171 and the inside of the opening 172. The film 155 is made of, for example, SiO ２ The film 155 can be formed by, for example, sputtering or by applying and curing spin-on glass (SOG). Fig. 20 corresponds to a cross-sectional view taken along line XX-XX in Fig. 9.

[0029] 10 and 21, the film 155 is etched back so that the film 155 remains in the openings 171 and 172. As a result, the support member 151 made of the film 155 is formed in the opening 171, and the support member 152 is formed in the opening 172. In the etch back of the film 155, for example, tetrafluoromethane (CF ４ 21 corresponds to a cross-sectional view taken along line XXI-XXI in FIG.

[0030] Thereafter, as shown in FIGS. 11 and 22 , a mask 193 is formed on the substrate 110 and the filling member 161. The mask 193 has a two-layer structure and includes a lower layer 194 and an upper layer 195. The lower layer 194 is formed on the substrate 110 and the filling member 161, and the upper layer 195 is formed on the lower layer 194. The upper layer 195 includes an opening 195A that exposes the regions where the superconducting wiring 121 and the superconducting wiring 122 will be formed. The opening 195A has a cross-shaped planar shape. The lower layer 194 includes an opening 194A that is wider than the opening 195A. The opening 194A also has a cross-shaped planar shape. FIG. 22 corresponds to a cross-sectional view taken along line XXII-XXII in FIG. 11 .

[0031] 12 and 23, aluminum is evaporated from a direction tilted from the Z1 side toward the X1 side when viewed from the top surface 111, thereby forming an aluminum film on the support member 151, the embedded member 161, and the substrate 110. Next, the surface of this aluminum film is oxidized. As a result, the superconducting wiring 121 and the insulating film 130 are formed from the aluminum film. FIG. 23 corresponds to a cross-sectional view taken along line XXIII-XXIII in FIG. 12.

[0032] 13 and 24, aluminum is evaporated from a direction tilted from the Z1 side toward the Y2 side when viewed from the upper surface 111, thereby forming superconducting wiring 122 on the support member 152, the filling member 161, the insulating film 130, and the substrate 110. Fig. 24 corresponds to a cross-sectional view taken along line XXIV-XXIV in Fig. 13.

[0033] 14 and 25, the mask 193 is removed by, for example, a lift-off method. Then, the filling member 161 is removed. The filling member 161 is removed by, for example, oxygen (O ２ ) is used for dry etching. At this time, by increasing the gas pressure, it is possible to easily remove the embedded member 161 below the superconducting wiring 121 and the superconducting wiring 122. Figure 25 corresponds to a cross-sectional view taken along line XXV-XXV in Figure 14.

[0034] According to this manufacturing method, since the lift-off method is employed, the support members 151 and 152, the superconducting wires 121 and 122 can be formed with high precision.

[0035] Second Embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the structure of the superconducting wiring and the arrangement of the support members. The second embodiment relates to an electronic device. Fig. 26 is a perspective view showing an electronic device according to the second embodiment.

[0036] 26 , the electronic device 2 according to the second embodiment has a substrate 210, superconducting wiring 221, superconducting wiring 222, an insulating film 230, two support members 251, two support members 252, four support members 253, and four support members 254. Although this embodiment discloses a structure having two support members 251, two support members 252, four support members 253, and four support members 254, the number of each support member is not limited to this.

[0037] The substrate 210 is, for example, a silicon substrate or a sapphire substrate. A recess 212 is formed on an upper surface 211 of the substrate 210. The upper surface 211 is a surface parallel to the XY plane. The recess 212 has a cross-shaped planar shape. For example, the depth of the recess 212 (the dimension in the Z1-Z2 direction) is constant. The upper surface 211 is an example of a first surface.

[0038] The support members 251, 252, 253 and 254 are made of, for example, SiO ２The support members 251, 252, 253, and 254 are provided in the recess 212. The height (thickness) of the support members 251, 252, 253, and 254 is preferably equal to the depth of the recess 212, but may be greater or smaller than the depth of the recess 212.

[0039] The two support members 251 are arranged side by side in the X1-X2 direction in a portion of the recessed portion 212 that extends parallel to the X1-X2 direction. The four support members 253 are arranged on the X2 side of the two support members 251, and are arranged in a square lattice pattern parallel to the X1-X2 and Y1-Y2 directions.

[0040] The two support members 252 are arranged side by side in the Y1-Y2 direction in a portion of the recessed portion 212 that extends parallel to the Y1-Y2 direction. The four support members 254 are arranged on the Y1 side of the two support members 252, and are arranged in a square lattice pattern parallel to the X1-X2 and Y1-Y2 directions.

[0041] The superconducting wiring 221 and the superconducting wiring 222 are, for example, Al films. The superconducting wiring 221 extends along the X1-X2 direction. The superconducting wiring 221 has a thin wire portion 221A with a width W1A in the Y1-Y2 direction and a thick wire portion 221B with a width W1B in the Y1-Y2 direction. The width W1B is larger than the width W1A. The thin wire portion 221A and the thick wire portion 221B are connected to each other. The thin wire portion 221A is supported by two support members 251, and the thick wire portion 221B is supported by four support members 253. The superconducting wiring 222 extends along the Y1-Y2 direction. The superconducting wiring 222 has a thin wire portion 222A with a width W2A in the X1-X2 direction and a thick wire portion 222B with a width W2B in the X1-X2 direction. The width W2B is larger than the width W2A. The thin line portion 222A and the thick line portion 222B are connected to each other. The thin line portion 222A is supported by two support members 252, and the thick line portion 222B is supported by four support members 254. The thin line portions 221A and 222A are an example of a first portion, and the thick line portions 221B and 222B are an example of a second portion.

[0042] In a plan view, the thin wire portion 221A of the superconducting wiring 221 and the thin wire portion 222A of the superconducting wiring 222 intersect with each other. In a plan view, a portion of the thin wire portion 221A between the two support members 251 and a portion of the thin wire portion 222A between the two support members 252 overlap in the Z1-Z2 direction. The superconducting wiring 221 is an example of a first superconducting wiring, and the superconducting wiring 222 is an example of a second superconducting wiring.

[0043] The insulating film 230 is made of, for example, Al ２ O ３ The insulating film 230 is a film. The insulating film 230 is provided between the thin wire portion 221A and the thin wire portion 222A. The insulating film 230 is provided between the thin wire portion 221A and the thin wire portion 222A in the region where the thin wire portion 221A and the thin wire portion 222A overlap each other. The insulating film 230 is in contact with the thin wire portion 221A and the thin wire portion 222A. The insulating film 230 may cover other portions of the superconducting wiring 221. The thickness of the insulating film 230 is such that a tunnel effect can occur between the thin wire portion 221A and the thin wire portion 222A. Note that the insulating film 230 covers the top and side surfaces of the superconducting wiring 221, but is not shown in FIG. 26 except for the portion between the superconducting wiring 121 and the superconducting wiring 122.

[0044] In the electronic device 2, the region where the thin wire portion 221A and the thin wire portion 222A intersect in a plan view functions as a superconducting Josephson junction element in an extremely low temperature environment of, for example, about 10 mK. A space 213 exists between the region functioning as the superconducting Josephson junction element and the bottom surface 245 of the recess 212. In other words, there is a hollow space between the region functioning as the superconducting Josephson junction element and the bottom surface 245 of the recess 212. Therefore, even if an oxide exists on the bottom surface 245, the influence of TLS can be suppressed.

[0045] Furthermore, in the electronic device 2, not only between the region functioning as the superconducting Josephson junction element and the bottom surface 245 of the recessed portion 212, but also between the thick line portion 221B and the bottom surface 245 and between the thick line portion 222B and the bottom surface 245 are hollow. This makes it possible to further reduce the parasitic capacitance between the superconducting wiring 221 and the substrate 210 and between the superconducting wiring 222 and the substrate 210. The thick line portion 221B and the thick line portion 222B are used for electrical connection with other elements, etc.

[0046] The electronic device 2 according to the second embodiment can be manufactured by a method similar to that of the first embodiment. For example, the electronic device 2 according to the second embodiment can be manufactured by changing the pattern of the mask used for etching from that of the first embodiment.

[0047] Although not shown, the thick line portion 221B may be in contact with the upper surface 211 of the substrate 210, and the thick line portion 222B may be in contact with the upper surface 211 of the substrate 210.

[0048] Third Embodiment Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the arrangement of the support members. Fig. 27 is a perspective view showing an electronic device according to the third embodiment.

[0049] As shown in FIG. 27, the electronic device 3 according to the third embodiment has a support member 351 instead of the support member 151 and a support member 352 instead of the support member 152 .

[0050] The support members 351 and 352 are made of, for example, SiO ２ The support members 351 and 352 are films. The thickness of the support members 351 and 352 is about 100 nm. The support members 351 and 352 are provided on the upper surface 111 of the substrate 110. The support member 351 is provided on a portion of the upper surface 111 of the substrate 110 that is closer to the X1 side than the side wall surface 141. The support member 352 is provided on a portion of the upper surface 111 of the substrate 110 that is closer to the Y2 side than the side wall surface 144. The X1 side end of the superconducting wiring 121 is supported by the support member 351. The Y2 side end of the superconducting wiring 122 is supported by the support member 352.

[0051] The other configurations are the same as those of the first embodiment.

[0052] In the third embodiment, too, there is a hollow space between the region that functions as a superconducting Josephson junction element and the bottom surface 145 of the recess 112, so that even if an oxide is present on the bottom surface 145, the influence of TLS can be suppressed.

[0053] In the present disclosure, from the viewpoint of reducing parasitic capacitance, it is preferable that the dielectric constant of the support member is lower than that of the substrate, but the material of the support member is not limited to silicon oxide. For example, the support member may include silicon oxide, silicon nitride, aluminum oxide, or a resin. An example of the resin is benzocyclobutene (BCB). Furthermore, the material of the superconducting wiring is not limited to aluminum. For example, the superconducting wiring may include a superconducting material other than Al, such as niobium (Nb), niobium nitride (NbN), tantalum (Ta), tantalum nitride (TaN), or titanium nitride (TiN). The material of the insulating film sandwiched between two superconducting wirings is not limited to aluminum oxide.

[0054] Fourth Embodiment Next, a fourth embodiment will be described. The fourth embodiment relates to a quantum processing device including Josephson junction devices. Fig. 28 is a diagram showing a quantum processing device according to the fourth embodiment.

[0055] As shown in Fig. 28 , a quantum processing device 800 according to the fourth embodiment includes a quantum bit chip 810, a signal generator 820, a signal demodulator 830, and a cryogenic dilution refrigerator 840, as shown in Fig. 30 . The quantum bit chip 810 is housed in the cryogenic dilution refrigerator 840 and cooled to a temperature of 10 mK or less. The signal generator 820 generates a microwave pulse signal, and the microwave pulse signal is input to the quantum bit chip 810. The quantum bit chip 810 outputs a signal corresponding to the microwave pulse signal, and the signal demodulator 830 demodulates the signal output from the quantum bit chip 810. The signal generator 820 and the signal demodulator 830 are used at a temperature of, for example, about room temperature.

[0056] The quantum bit chip 810 includes a plurality of superconducting quantum bits (transmons) 850, and each superconducting quantum bit 850 has a Josephson junction device 851 and a capacitor 852 electrically connected in parallel to the Josephson junction device 851. The Josephson junction device 851 is an electronic device according to any one of the first to third embodiments, and one superconducting wiring and the other superconducting wiring are connected to the capacitor 852.

[0057] Because the Josephson junction device 851 included in the quantum computing device 800 according to the fourth embodiment is an electronic device according to any one of the first to third embodiments, a long coherence time can be obtained for the superconducting quantum bit 850, thereby suppressing errors in quantum computing and improving fidelity.

[0058] Electronic devices according to the present disclosure can be used, for example, in quantum computing.

[0059] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0060] 1, 2, 3: Electronic device 110, 210: Substrate 111, 211: Top surface 112, 212: Recessed portion 113, 213: Space 121, 122, 221, 222: Superconducting wiring 130, 230: Insulating film 145, 245: Bottom surface 151, 152, 251, 252, 253, 254, 351, 352: Support member 160: Resin layer 161: Embedded member 221A, 222A: Thin line portion 221B, 222B: Thick line portion

Claims

1. A substrate having a recessed portion on the first surface, A first superconducting wiring, part of which is in contact with the first surface, A second superconducting wiring intersects the first superconducting wiring in a plan view above the recess and a portion of it is in contact with the first surface, An insulating film is provided between the first superconducting wiring and the second superconducting wiring, A first support member provided within the recessed portion and supporting at least one of the first superconducting wiring or the second superconducting wiring, It has, An electronic device characterized in that, in a plan view, the area between the region where the first superconducting wiring and the second superconducting wiring intersect and the bottom surface of the recess is hollow.

2. The electronic device according to claim 1, characterized in that the relative permittivity of the first support member is lower than the relative permittivity of the substrate.

3. The first superconducting wiring is supported by the first support member, The second superconducting wiring is supported by the second support member, The electronic device according to claim 1 or 2, characterized in that the second support member is provided within the recessed portion.

4. The first superconducting wiring and the second superconducting wiring are both, Part 1 and, In plan view, the second part is wider than the first part, It has, The first portion of the first superconducting wiring is supported by the first support member, the second portion of the first superconducting wiring is supported by the third support member, the first portion of the second superconducting wiring is supported by the second support member, and the second portion of the second superconducting wiring is supported by the fourth support member. The electronic device according to claim 3, characterized in that the first portion of the first superconducting wiring and the first portion of the second superconducting wiring intersect in a plan view.

5. The electronic device according to claim 1 or 2, characterized in that the first support member supports at least one end of the first superconducting wiring or the second superconducting wiring.

6. The electronic device according to claim 1 or 2, characterized in that the first support member includes silicon oxide, silicon nitride, aluminum oxide, or resin.

7. The electronic device according to claim 1 or 2, characterized in that the substrate is a silicon substrate or a sapphire substrate.

8. A step of forming a recess on the first surface of the substrate, The process of forming an embedded member in the recessed portion, The step of forming an opening in the embedded member, The step of forming a support member in the opening, A step of forming a first superconducting wiring on the first surface and the embedded member, A step of forming an insulating film on the first superconducting wiring, A step of forming a second superconducting wiring on the first surface, the embedded member, and the insulating film, which intersects the first superconducting wiring in a plan view, A step of removing the embedding member between the region where the first superconducting wiring and the second superconducting wiring intersect in a plan view and the bottom surface of the recess, It has, A method for manufacturing an electronic device, characterized in that at least one of the first superconducting wiring or the second superconducting wiring is formed on the support member.

9. The method for manufacturing an electronic device according to claim 8, characterized in that the relative permittivity of the support member is lower than the relative permittivity of the substrate.

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