Semiconductor device and vehicle

JPWO2024252830A5Pending Publication Date: 2026-03-05
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Filing Date
2024-05-07
Publication Date
2026-03-05

AI Technical Summary

Technical Problem

Conventional semiconductor devices face challenges in being surface-mounted effectively, particularly due to issues with terminal design and resin coverage, which affects mounting strength and leads to resin burrs and processing defects.

Method used

The semiconductor device features a first lead with a metal layer covering a terminal portion, including a terminal tip with a concave surface and exposed tip surface, and a sealing resin configuration that enhances mounting strength and prevents resin burrs, allowing for reliable surface mounting on circuit boards.

Benefits of technology

The solution improves the mounting strength and reduces resin burrs, enabling efficient surface mounting of semiconductor devices and enhancing heat radiation efficiency while minimizing processing defects.

✦ Generated by Eureka AI based on patent content.
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Abstract

This semiconductor device comprises a semiconductor element, a first lead, and a sealing resin. The first lead comprises a die pad part that has a first lead back surface, and a first terminal part. The sealing resin has a second resin surface that faces the z direction and a third resin surface that faces the x direction. The first lead comprises a metal layer. The first lead back surface is exposed from the second resin surface. The first terminal part has a first terminal root part and a first terminal tip part. The first terminal root part traverses the third resin surface, and is separated from the first resin surface in the z direction. The first terminal tip part is positioned below the first terminal root part. The first terminal tip part has a tip surface that is exposed from the metal layer, and a recessed surface that is covered by the metal layer.
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Description

Semiconductor device and vehicle

[0001] The present disclosure relates to a semiconductor device and a vehicle.

[0002] Patent Document 1 discloses an example of a semiconductor device. The semiconductor device described in Patent Document 1 includes a first lead including a first pad having a main pad surface and a back pad surface, a second lead, a third lead, a semiconductor element mounted on the main pad surface, and a sealing resin in contact with the main pad surface and covering the semiconductor element. The first lead, the second lead, and the third lead have a first terminal, a second terminal, and a third terminal extending in the same direction. The first terminal, the second terminal, and the third terminal are inserted into through holes in a circuit board or the like, thereby mounting the semiconductor device on the circuit board. When the semiconductor device is attached to a heat sink, for example, an insulating sheet is provided between the back pad surface and the heat sink.

[0003] Japanese Patent Application Laid-Open No. 2017-174951

[0004] In addition to the mounting form in which terminal portions are inserted into a circuit board, there are cases in which a semiconductor device is required to be surface-mounted on a circuit board, for example.

[0005] An object of the present disclosure is to provide an improved semiconductor device. In particular, in view of the above-described circumstances, an object of the present disclosure is to provide a surface-mountable semiconductor device. Another object of the present disclosure is to provide a vehicle equipped with a surface-mountable semiconductor device.

[0006] A first aspect of the present disclosure provides a semiconductor device comprising: a semiconductor element; a die pad portion having a first lead main surface facing one side of a thickness direction and on which the semiconductor element is mounted, and a first lead back surface facing the other side of the thickness direction; a first terminal portion; and a sealing resin having a first resin surface facing one side of the thickness direction, a second resin surface facing the other side of the thickness direction, and a third resin surface facing one side of a first direction perpendicular to the thickness direction, the sealing resin covering the semiconductor element and a portion of the die pad portion. The first lead includes a metal layer covering a portion of the first terminal portion. The first lead back surface is exposed from the second resin surface. The first terminal portion has a first terminal root portion and at least one first terminal tip portion. The first terminal root portion penetrates the third resin surface and is spaced from the first resin surface in the thickness direction. The at least one first terminal tip portion is located on the one side of the thickness direction relative to the first terminal root portion and is used for mounting. The at least one first terminal tip portion has a first tip surface and a concave surface connected to the first tip surface, the first tip surface being exposed from the metal layer, and the concave surface being covered by the metal layer.

[0007] A vehicle provided by a second aspect of the present disclosure includes a drive source, a storage battery that stores power to be supplied to the drive source, and an on-board charger that converts externally input power and supplies the converted power to the storage battery. The on-board charger includes the semiconductor device provided by the first aspect.

[0008] According to the above configuration, it is possible to provide a surface-mountable semiconductor device and a vehicle equipped with a surface-mountable semiconductor device.

[0009] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment. FIG. 2 is a perspective view of FIG. 1 in which a sealing resin is shown by imaginary lines and multiple connecting members are omitted. FIG. 3 is a perspective view showing a semiconductor device according to the first embodiment. FIG. 4 is a view showing the sealing resin by imaginary lines in the perspective view of FIG. 3. FIG. 5 is a perspective view showing a semiconductor device according to the first embodiment. FIG. 6 is a plan view showing a semiconductor device according to the first embodiment. FIG. 7 is a view showing the sealing resin by imaginary lines in the plan view of FIG. 6. FIG. 8 is a bottom view showing a semiconductor device according to the first embodiment. FIG. 9 is a view showing the sealing resin by imaginary lines in the bottom view of FIG. 8. FIG. 10 is a front view showing a semiconductor device according to the first embodiment. FIG. 11 is a right side view showing a semiconductor device according to the first embodiment. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 9. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 9. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 9. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 9 . FIG. 16 is a perspective view of a main portion of FIG. 5 , enlarging a portion (first terminal tip portion) of FIG. 5 . FIG. 17 is a bottom view of a main portion of FIG. 8 , enlarging a portion (first terminal tip portion). FIG. 18 is a front view of a main portion of FIG. 10 , enlarging a portion (first terminal tip portion). FIG. 19 is a cross-sectional view showing a state in which the semiconductor device according to the first embodiment is in use. FIG. 20 is a schematic diagram showing a vehicle equipped with the semiconductor device according to the first embodiment. FIG. 21 is a bottom view showing a step of a manufacturing method of the semiconductor device according to the first embodiment. FIG. 22 is a perspective view of a semiconductor device according to a second embodiment, corresponding to FIG. 3 . FIG. 23 is a perspective view of a main portion of FIG. 22 (first terminal tip portion), enlarging a portion of FIG. 22 , corresponding to FIG. 16 . FIG. 24 is a bottom view of a main portion of the semiconductor device according to the second embodiment, corresponding to FIG. 17 . FIG. 25 is a front view of a main portion of the semiconductor device according to the second embodiment, corresponding to FIG. 18 . Fig. 26 is a perspective view showing a semiconductor device according to a third embodiment, and corresponds to Fig. 3. Fig. 27 is a perspective view of a main part in which a part (a tip portion of a first terminal) of Fig. 26 is enlarged, and corresponds to Fig. 16. Fig. 28 is a bottom view of a main part showing the semiconductor device according to the third embodiment, and corresponds to Fig. 17. Fig. 29 is a front view of a main part showing the semiconductor device according to the third embodiment, and corresponds to Fig. 18.FIG. 30 is a perspective view showing a semiconductor device according to a fourth embodiment and corresponds to FIG. 3 . FIG. 31 is a perspective view of a main portion of FIG. 30 (a tip portion of a first terminal) enlarged, and corresponds to FIG. 16 . FIG. 32 is a bottom view of a main portion of a semiconductor device according to the fourth embodiment and corresponds to FIG. 17 . FIG. 33 is a front view of a main portion of a semiconductor device according to the fourth embodiment and corresponds to FIG. 18 . FIG. 34 is a perspective view of a semiconductor device according to a fifth embodiment and corresponds to FIG. 5 . FIG. 35 is a perspective view of a semiconductor device according to a modified example of the fifth embodiment and corresponds to FIG. 5 . FIG. 36 is a plan view of a semiconductor device according to a first modified example, in which the sealing resin is indicated by an imaginary line. FIG. 37 is a plan view of a semiconductor device according to a second modified example, in which the sealing resin is indicated by an imaginary line. FIG. 38 is a bottom view showing a step of a method for manufacturing the semiconductor device shown in FIG. 37 and corresponds to FIG. 21 . FIG. 39 is a perspective view of a semiconductor device according to a third modified example and corresponds to FIG. 5 . Fig. 40 is a perspective view showing a semiconductor device according to a third modified example, and corresponds to Fig. 3. Fig. 41 is a perspective view showing a semiconductor device according to a fourth modified example, and corresponds to Fig. 5. Fig. 42 is a right side view showing a semiconductor device according to a fifth modified example, and corresponds to Fig. 11.

[0011] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant descriptions will be omitted. Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not intended to necessarily assign any order to their objects.

[0012] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Unless otherwise specified, "object A overlaps object B when viewed in a certain direction" includes "object A overlaps the entire object B" and "object A overlaps part of object B." "Object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is mainly composed of material C." "A surface A faces in a certain direction B (one side or the other side of a certain direction B)" does not necessarily mean that surface A is at a 90° angle with respect to direction B, but also includes surface A being tilted relative to direction B. "A surface A is perpendicular to surface B" does not necessarily mean that surface A is at a 90° angle with respect to surface B, but also includes surface A being tilted relative to surface B, unless otherwise specified.

[0013] 1 to 18 show a semiconductor device A10 according to Embodiment 1. The semiconductor device A10 includes a conductive member 10, a semiconductor element 20, a plurality of connecting members 31, 32, 33, and a sealing resin 40.

[0014] As an example, for convenience of explanation, the thickness direction of the semiconductor device A10 will be referred to as the "thickness direction z." In the following explanation, one side of the thickness direction z may be referred to as the bottom, and the other side as the top. Terms such as "top," "bottom," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component, etc. in the thickness direction z, and do not necessarily define the relationship with the direction of gravity. One direction perpendicular to the thickness direction z will be referred to as the "first direction x." A direction perpendicular to the thickness direction z and the first direction x will be referred to as the "second direction y."

[0015] The conductive member 10 is a member that forms a conductive path to the semiconductor element 20. The conductive member 10 of this embodiment includes a first lead 11, a second lead 12, a third lead 13, and a fourth lead 14. The materials of the first lead 11, the second lead 12, the third lead 13, and the fourth lead 14 are not limited in any way and include, for example, copper (Cu) or a copper alloy. The first lead 11, the second lead 12, the third lead 13, and the fourth lead 14 are plated in appropriate locations with silver (Ag), nickel (Ni), tin (Sn), or the like. This plating corresponds to each of the metal layers 110, 120, 130, and 140, which will be described in detail later. In FIGS. 1 to 11 , this plating (each of the metal layers 110, 120, 130, and 140, which will be described later) is omitted from illustration.

[0016] As shown in FIGS. 1 to 18, the first lead 11 includes a metal layer 110 , a die pad portion 111 and a first terminal portion 112 .

[0017] The metal layer 110 covers a portion of the first lead 11. As described above, the metal layer 110 is a plating of silver (Ag), nickel (Ni), tin (Sn), or the like. The material of the metal layer 110 is not limited to these, but it is preferable that the material has a higher bonding strength with the bonding layer 29 (described later) than the material of the first lead 11 (e.g., Cu).

[0018] The die pad portion 111 has a first lead main surface 1111 and a first lead back surface 1112. The first lead main surface 1111 is a surface facing one side (downward) in the thickness direction z. The first lead back surface 1112 is a surface facing the other side (upward) in the thickness direction z. A semiconductor element 20 is mounted on the first lead main surface 1111.

[0019] The die pad portion 111 of this embodiment further has a first lead side surface 1113 and a first intermediate surface 1114. The first lead side surface 1113 is located between the first lead main surface 1111 and the first lead back surface 1112 in the thickness direction z and is a surface facing downward in the first direction x. The first intermediate surface 1114 is located between the first lead main surface 1111 and the first lead back surface 1112 in the thickness direction z and is a surface facing downward in the thickness direction z (the same side as the first lead main surface 1111).

[0020] The shape of the die pad portion 111 is not limited in any way. In the illustrated example, the die pad portion 111 is rectangular when viewed in the thickness direction z. The shapes of the first lead main surface 1111 and the first lead back surface 1112 are not limited in any way and are rectangular when viewed in the thickness direction z in the illustrated example.

[0021] 12, the entire surface of the die pad portion 111 is covered with a metal layer 110. The metal layer 110 may not be formed in the region where the semiconductor element 20 is bonded (the region in contact with a bonding layer 29 described later), or may be made of a different material from that in other regions.

[0022] The first terminal portion 112 is connected to the die pad portion 111. A large portion of the first terminal portion 112 is exposed from the sealing resin 40. The first terminal portion 112 protrudes toward one side in the first direction x with respect to the sealing resin 40. The first terminal portion 112 is bent in a gull-wing shape. The first terminal portion 112 has a first terminal root portion 1121, two first terminal tip portions 1122, and two first terminal middle portions 1123.

[0023] The first terminal root portion 1121 is connected to the die pad portion 111 and extends from the die pad portion 111 in one direction in the first direction x. In the illustrated example, the first terminal root portion 1121 is parallel to a plane (x-y plane) perpendicular to the thickness direction z. In this embodiment, the thickness (dimension along the thickness direction z) of the die pad portion 111 is greater than the thickness (dimension along the thickness direction z) of the first terminal root portion 1121. The first terminal portion 112 in this embodiment has one first terminal root portion 1121. The shape of the first terminal root portion 1121 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z. The first terminal root portion 1121 is separated from the first lead back surface 1112 in the thickness direction z and is in contact with the first lead main surface 1111 in the illustrated example. The lower surface (the surface facing downward in the thickness direction z) of the first terminal base portion 1121 is flush with the first lead main surface 1111 .

[0024] A partial region of the surface of the first terminal base portion 1121 facing one side in the first direction x is exposed from the metal layer 110. This partial region corresponds to a portion connected to a frame body 81 (see FIG. 21 ) of the lead frame 80, which will be described in detail later.

[0025] As shown in FIGS. 6 and 7 , the first terminal root portion 1121 has a pair of root side surfaces 1121a. The pair of root side surfaces 1121a are spaced apart in the second direction y and face opposite each other in the second direction y. The pair of root side surfaces 1121a are parallel to a plane (x-z plane) perpendicular to the second direction y. The pair of root side surfaces 1121a may be slightly inclined or curved with respect to the x-z plane. A recess 113 is formed in each of the pair of root side surfaces 1121a. In other words, the first lead 11 has a pair of recesses 113. In the semiconductor device A10, the pair of recesses 113 are individually recessed in the second direction y from the pair of root side surfaces 1121a. In a configuration different from the semiconductor device A10, the recess 113 may not be formed in the first terminal portion 112.

[0026] The two first terminal tip portions 1122 are each located below the first terminal root portion 1121 in the thickness direction z. The two first terminal root portions 1121 are each used when surface-mounting the semiconductor device A10 on a circuit board or the like.

[0027] 16 to 18, each of the two first terminal tip portions 1122 has a first tip surface 1122a and a concave surface 1122d. Unless otherwise specified, the first tip surface 1122a and the concave surface 1122d described below are common to all first terminal tip portions 1122. For ease of understanding, the first tip surface 1122a is depicted as a dot in FIGS.

[0028] The first tip surface 1122a is the end surface of each first terminal tip portion 1122 opposite the end connected to the first terminal intermediate portion 1123, that is, the end surface farthest from the first terminal root portion 1121. The first tip surface 1122a is exposed from the metal layer 110. The first tip surface 1122a includes two exposed regions 1122b.

[0029] The two exposed regions 1122b are spaced apart in the first direction x and are connected to the upper surface (the surface facing upward in the thickness direction z) of the first terminal tip portion 1122 and the lower surface (the surface facing downward in the thickness direction z), respectively.

[0030] The concave surface 1122d is connected to the first tip surface 1122a. The concave surface 1122d is sandwiched between the two exposed regions 1122b. In this embodiment, the concave surface 1122d is connected to the upper surface (surface facing upward in the thickness direction z) of the first terminal tip portion 1122 and the lower surface (facing downward in the thickness direction z) of the first terminal tip portion 1122. The concave surface 1122d is recessed from the two exposed regions 1122b in the second direction y. The concave surface 1122d has a sidewall connected to one of the two exposed regions 1122b, a sidewall connected to the other of the two exposed regions 1122b, and a bottom connected to the two sidewalls. In this embodiment, the bottom is flat but may be curved. In this embodiment, each sidewall is flat but may be curved or may be inclined with respect to a plane perpendicular to the first direction x (the y-z plane). The concave surface 1122 d is covered with the metal layer 110 .

[0031] The two first terminal intermediate portions 1123 are individually interposed between the first terminal root portion 1121 and the two first terminal tip portions 1122. Each first terminal intermediate portion 1123 extends downward in the thickness direction z from the first terminal root portion 1121. In the illustrated example, each first terminal intermediate portion 1123 is inclined with respect to the thickness direction z so as to extend outward from the first terminal root portion 1121 in the second direction y. Alternatively, each first terminal intermediate portion 1123 may be parallel to the thickness direction z. This configuration allows the dimension of the semiconductor device A10 in the first direction x to be reduced. On the other hand, a configuration in which the first terminal intermediate portions 1123 are inclined with respect to the thickness direction z facilitates the manufacture of the semiconductor device A10 (e.g., bending the first terminal portion 112). The shape of each first terminal intermediate portion 1123 is not limited in any way.

[0032] In this embodiment, the two first terminal tip portions 1122 extend outward in the second direction y, independently from the two second terminal intermediate portions 1223. The two first terminal tip portions 1122 are each parallel to the second direction y. In the illustrated example, the two first terminal tip portions 1122 and the two first terminal intermediate portions 1123 are at the same position in the first direction x. In the illustrated example, as shown in FIG. 11 , the two first terminal tip portions 1122 are each inclined with respect to the xy plane. Alternatively, the two first terminal tip portions 1122 may each be parallel to the xy plane.

[0033] The first terminal 112 is covered with the metal layer 110 except for two exposed regions 1122b on the first tip surface 1122a. That is, in the first terminal 112, the two exposed regions 1122b are exposed from the metal layer 110. The concave surface 1122d is covered with the metal layer 110.

[0034] The second lead 12 is located on the other side in the first direction x and spaced apart from the first lead 11 (die pad portion 111). The second lead 12 includes a metal layer 120, a pad portion 121, and a plurality of second terminal portions 122.

[0035] The metal layer 120 covers a part of the second lead 12. As described above, the metal layer 120 is a plating of Ag, Ni, Sn, etc. The material of the metal layer 120 is not limited to these.

[0036] The pad portion 121 has a second lead main surface 1211 and a second lead back surface 1212. The second lead main surface 1211 faces downward (one side) in the thickness direction z. The second lead back surface 1212 faces upward (the other side) in the thickness direction z. A connection member 31 is connected to the second lead main surface 1211. The shape of the pad portion 121 is not limited in any way, and in the illustrated example, it is an elongated rectangle with the second direction y as its longitudinal direction. When viewed in the thickness direction z, the pad portion 121 is smaller than the die pad portion 111. The dimension of the pad portion 121 in the thickness direction z is smaller than the dimension of the die pad portion 111 in the thickness direction z and is the same as the dimension of the first terminal portion 112 in the thickness direction z. In the illustrated example, the position of the second lead main surface 1211 in the thickness direction z is the same as the first lead main surface 1111 of the die pad portion 111.

[0037] Each of the multiple second terminals 122 is connected to a pad portion 121. A large portion of each second terminal 122 is exposed from the sealing resin 40. Each second terminal 122 protrudes toward the other side of the sealing resin 40 in the first direction x. Therefore, each of the multiple second terminals 122 is disposed on the opposite side of the sealing resin 40 from the first terminal 112 in the first direction x. The multiple second terminals 122 are disposed side by side in the second direction y. Each of the multiple second terminals 122 is bent in a gull-wing shape. As can be seen from FIG. 12 , each of the multiple second terminals 122 has a second terminal root portion 1221, a second terminal tip portion 1222, and a second terminal intermediate portion 1223. The second terminal root portion 1221, the second terminal tip portion 1222, and the second terminal middle portion 1223 described below are common to all second terminal portions 122 unless otherwise specified.

[0038] The second terminal root portion 1221 is connected to the pad portion 121, extends from the pad portion 121 to the other side in the first direction x, and is parallel to the xy plane in the illustrated example. The shape of the second terminal root portion 1221 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z.

[0039] The second terminal tip portion 1222 is located below the second terminal root portion 1221 in the thickness direction z. The second terminal tip portion 1222 is used when surface-mounting the semiconductor device A10 on a circuit board or the like. The second terminal tip portion 1222 has a shape that extends along the first direction x. In the illustrated example, as shown in FIG. 12, the second terminal tip portion 1222 is inclined with respect to the xy plane. However, unlike this example, the second terminal tip portion 1222 may be parallel to the xy plane.

[0040] The second terminal intermediate portion 1223 is interposed between the second terminal root portion 1221 and the second terminal tip portion 1222. The second terminal intermediate portion 1223 extends downward in the thickness direction z from the second terminal root portion 1221. In the illustrated example, the second terminal intermediate portion 1223 is inclined with respect to the thickness direction z (y-z plane). Alternatively, the second terminal intermediate portion 1223 may be parallel to the thickness direction z. This configuration allows the dimension of the semiconductor device A10 in the first direction x to be reduced. On the other hand, a configuration in which the second terminal intermediate portion 1223 is inclined with respect to the thickness direction z facilitates the manufacture of the semiconductor device A10 (for example, bending the second terminal portion 122). The shape of the second terminal intermediate portion 1223 is not limited in any way.

[0041] Each second terminal 122 is covered with the metal layer 120 except for the tip surface of the second terminal tip portion 1222. That is, in each second terminal 122, the tip surface of the second terminal tip portion 1222 is exposed from the metal layer 120. This tip surface refers to the end surface of the second terminal tip portion 1222 opposite to the end connected to the second terminal intermediate portion 1223.

[0042] The third lead 13 is located away from the first lead 11 (die pad portion 111) on the other side in the first direction x. The third lead 13 is aligned with the second lead 12 in the second direction y. The third lead 13 includes a metal layer 130, a pad portion 131, and a third terminal portion 132.

[0043] The pad portion 131 has a third lead main surface 1311 and a third lead back surface 1312. The third lead main surface 1311 faces downward in the thickness direction z. The third lead back surface 1312 faces upward in the thickness direction z. A connecting member 32 is connected to the third lead main surface 1311. The shape of the pad portion 131 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z. When viewed in the thickness direction z, the pad portion 131 is smaller than the pad portion 121. The thickness (dimension in the thickness direction z) of the pad portion 131 is smaller than the thickness (dimension in the thickness direction z) of the die pad portion 111 and is the same as the thickness (dimension in the thickness direction z) of the pad portion 121. In the illustrated example, the position of the third lead main surface 1311 in the thickness direction z is the same as that of the first lead main surface 1111 of the die pad portion 111.

[0044] The third terminal portion 132 is connected to the pad portion 131. A large portion of the third terminal portion 132 is exposed from the sealing resin 40. The third terminal portion 132 protrudes toward the other side in the first direction x with respect to the sealing resin 40. Therefore, the third terminal portion 132 is disposed on the opposite side of the first terminal portion 112 in the first direction x, with the sealing resin 40 sandwiched therebetween. The third terminal portion 132 is disposed on the other side in the second direction y of the plurality of second terminal portions 122. The third terminal portion 132 is bent in a gull-wing shape. As shown in FIG. 14 , the third terminal portion 132 includes a root portion 1321, a tip portion 1322, and an intermediate portion 1323.

[0045] The root portion 1321 is connected to the pad portion 131 and extends from the pad portion 131 to the other side in the first direction x. In the illustrated example, the root portion 1321 is parallel to the xy plane. The shape of the root portion 1321 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z. The root portion 1321 includes a portion covered with the sealing resin 40 and a portion exposed from the sealing resin 40.

[0046] The tip portion 1322 is located below the base portion 1321 in the thickness direction z. The tip portion 1322 is used when surface-mounting the semiconductor device A10 on a circuit board or the like. The tip portion 1322 extends along the first direction x when viewed in the thickness direction z. In the illustrated example, the tip portion 1322 is inclined with respect to the xy plane, as shown in FIG. 14 . Alternatively, the tip portion 1322 may be parallel to the xy plane.

[0047] The intermediate portion 1323 is interposed between the root portion 1321 and the tip portion 1322. The intermediate portion 1323 extends downward in the thickness direction z from the root portion 1321. In the illustrated example, the intermediate portion 1323 is inclined with respect to the thickness direction z (y-z plane). Unlike this example, the intermediate portion 1323 may be parallel to the thickness direction z. In this configuration, the dimension of the semiconductor device A10 in the first direction x can be reduced. On the other hand, a configuration in which the intermediate portion 1323 is inclined with respect to the thickness direction z facilitates the manufacture of the semiconductor device A10 (for example, bending the third terminal portion 132). The shape of the intermediate portion 1323 is not limited in any way.

[0048] The third terminal portion 132 is covered with the metal layer 130 except for the tip surface of the tip portion 1322. In other words, the tip surface of the tip portion 1322 is exposed from the metal layer 130. This tip surface is the end surface of the tip portion 1322 opposite to the end portion connected to the intermediate portion 1323.

[0049] The fourth lead 14 is located away from the first lead 11 (die pad portion 111) on the other side in the first direction x. The fourth lead 14 is located between the second lead 12 and the third lead 13 in the second direction y. The fourth lead 14 includes a metal layer 140, a pad portion 141, and a fourth terminal portion 142.

[0050] The pad portion 141 has a fourth lead main surface 1411 and a fourth lead back surface 1412. The fourth lead main surface 1411 faces downward in the thickness direction z. The fourth lead back surface 1412 faces upward in the thickness direction z. A connecting member 33 is connected to the fourth lead main surface 1411. The shape of the pad portion 141 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z. When viewed in the thickness direction z, the pad portion 141 is smaller than the pad portion 121 and is approximately the same size as the pad portion 131. The thickness (dimension in the thickness direction z) of the pad portion 141 is smaller than the thickness (dimension in the thickness direction z) of the die pad portion 111 and is the same as the thicknesses (dimension in the thickness direction z) of the pad portion 121 and the pad portion 131. In the illustrated example, the position of the fourth lead main surface 1411 in the thickness direction z is the same as the first lead main surface 1111 of the die pad portion 111.

[0051] The fourth terminal portion 142 is connected to the pad portion 141. A large portion of the fourth terminal portion 142 is exposed from the sealing resin 40. The fourth terminal portion 142 protrudes toward the other side of the first direction x relative to the sealing resin 40. Thus, the fourth terminal portion 142 is disposed on the opposite side of the first terminal portion 112 in the first direction x, across the sealing resin 40. The fourth terminal portion 142 is disposed on the other side of the second terminal portions 122 in the second direction y, and is positioned between the second terminal portions 122 and the third terminal portion 132 in the second direction y. The fourth terminal portion 142 is bent in a gull-wing shape. As shown in FIG. 13 , the fourth terminal portion 142 includes a root portion 1421, a tip portion 1422, and an intermediate portion 1423.

[0052] The root portion 1421 is connected to the pad portion 141 and extends from the pad portion 141 to the other side in the first direction x. In the illustrated example, the root portion 1421 is parallel to the xy plane. The shape of the root portion 1421 is not limited in any way, and in the illustrated example, it is rectangular when viewed in the thickness direction z. The root portion 1421 includes a portion covered with the sealing resin 40 and a portion exposed from the sealing resin 40.

[0053] The tip portion 1422 is located below the base portion 1421 in the thickness direction z. The tip portion 1422 is used when surface-mounting the semiconductor device A10 on a circuit board or the like. The tip portion 1422 extends along the first direction x when viewed in the thickness direction z. In the illustrated example, as shown in FIG. 13 , the tip portion 1422 is inclined with respect to the xy plane. Alternatively, the tip portion 1422 may be parallel to the xy plane.

[0054] The intermediate portion 1423 is interposed between the root portion 1421 and the tip portion 1422. The intermediate portion 1423 extends downward in the thickness direction z from the root portion 1421. In the illustrated example, the intermediate portion 1423 is inclined with respect to the thickness direction z (y-z plane). Unlike this example, the intermediate portion 1423 may be parallel to the thickness direction z, and in this configuration, the dimension of the semiconductor device A10 in the first direction x can be reduced. On the other hand, a configuration in which the intermediate portion 1423 is inclined with respect to the thickness direction z facilitates the manufacture of the semiconductor device A10 (for example, bending the fourth terminal portion 142). The shape of the intermediate portion 1423 is not limited in any way.

[0055] The fourth terminal portion 142 is covered with the metal layer 140 except for the tip surface of the tip portion 1422. In other words, the tip surface of the tip portion 1422 is exposed from the metal layer 140. This tip surface is the end surface of the tip portion 1422 opposite to the end portion connected to the intermediate portion 1423.

[0056] In the semiconductor device A10, as shown in FIG. 6 , the width W1123 of each first terminal intermediate portion 1123 of the first lead 11 is, for example, 0.5 to 2 times the width W1223 of each second terminal intermediate portion 1223 of the second lead 12. The width W1123 of the first terminal intermediate portion 1123 is a dimension along the following direction and is an example of the "first dimension" described in the claims. This direction is perpendicular to the thickness direction z and the extension direction of the first terminal intermediate portion 1123 as viewed in the thickness direction z, which is the first direction x in this embodiment. That is, in this embodiment, the width W1123 of the first terminal intermediate portion 1123 is a dimension along the first direction x of the first terminal intermediate portion 1123. The width W1223 of the second terminal intermediate portion 1223 is a dimension along the following direction and is an example of the "second dimension" described in the claims. This direction is a direction perpendicular to the thickness direction z and the extension direction of the second terminal intermediate portion 1223 as viewed in the thickness direction z, which is the second direction y in this embodiment. That is, in this embodiment, the width W1223 of the second terminal intermediate portion 1223 is the dimension of the second terminal intermediate portion 1223 along the second direction y. The relationship between the width W1123 of the first terminal intermediate portion 1123 and the width W1223 of each second terminal intermediate portion 1223 is not limited to the above.

[0057] In the semiconductor device A10, as shown in FIG. 6 , the width W1223 of each second terminal intermediate portion 1223 of the second lead 12, the width W1323 of the intermediate portion 1323 of the third lead 13, and the width W1423 of the intermediate portion 1423 of the fourth lead 14 are the same. The width W1323 of the intermediate portion 1323 is a dimension along the following direction: This direction is perpendicular to the thickness direction z and the extension direction of the intermediate portion 1323 as viewed in the thickness direction z, which is the second direction y in this embodiment. That is, in this embodiment, the width W1323 of the intermediate portion 1323 is a dimension along the second direction y of the intermediate portion 1323. The width W1423 of the intermediate portion 1423 is a dimension along the following direction: This direction is perpendicular to the thickness direction z and the extension direction of the intermediate portion 1423 as viewed in the thickness direction z, which is the second direction y in this embodiment. That is, in this embodiment, the width W1423 of the intermediate portion 1423 is the dimension along the second direction y of the intermediate portion 1423. The relationship between the width W1223 of each second terminal intermediate portion 1223, the width W1323 of the intermediate portion 1323, and the width W1423 of the intermediate portion 1423 is not limited to the above.

[0058] As shown in FIGS. 4, 9, and 12 to 15, the semiconductor element 20 is mounted on the first lead main surface 1111 of the die pad portion 111. In the semiconductor device A10, the semiconductor element 20 is an n-channel, vertically structured metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor element 20 is not limited to a MOSFET. The semiconductor element 20 may be another transistor such as an insulated gate bipolar transistor (IGBT). Furthermore, the semiconductor element 20 may be a diode. The semiconductor element 20 has a semiconductor layer 205, a first electrode 201, a second electrode 202, and a third electrode 203.

[0059] The semiconductor layer 205 includes a compound semiconductor substrate. The main material of the compound semiconductor substrate is silicon carbide (SiC). Alternatively, silicon (Si) may be used as the main material of the compound semiconductor substrate.

[0060] The first electrode 201 is provided on a portion of the semiconductor layer 205 on the side (lower side) facing the first lead main surface 1111 of the die pad portion 111 of the first lead 11 in the thickness direction z. The first electrode 201 corresponds to the source electrode of the semiconductor element 20.

[0061] The second electrode 202 is provided on a portion of the semiconductor layer 205 opposite to the first electrode 201 in the thickness direction z. The second electrode 202 faces the first lead main surface 1111 of the die pad portion 111 of the first lead 11. The second electrode 202 corresponds to the drain electrode of the semiconductor element 20. In this embodiment, the second electrode 202 is bonded to the first lead main surface 1111 via a bonding layer 29. The bonding layer 29 is, for example, solder, silver (Ag) paste, baked silver, or the like.

[0062] The third electrode 203 is provided on the same side of the semiconductor layer 205 as the first electrode 201 in the thickness direction z, and is located away from the first electrode 201. The third electrode 203 corresponds to the gate electrode of the semiconductor element 20. When viewed in the thickness direction z, the area of ​​the third electrode 203 is smaller than the area of ​​the first electrode 201.

[0063] 9 and 12 , the connection member 31 is bonded to the first electrode 201 of the semiconductor element 20 and the second lead main surface 1211 of the pad portion 121 of the second lead 12. The material of the connection member 31 is not limited in any way and includes metals such as aluminum (Al), copper (Cu), and gold (Au). The number of connection members 31 is not limited in any way and multiple connection members 31 may be provided. In the illustrated example, the connection member 31 is a flat, strip-shaped member that contains aluminum (Al).

[0064] 9 and 14 , the connection member 32 is connected to the third electrode 203 of the semiconductor element 20 and the third lead main surface 1311 of the pad portion 131 of the third lead 13. In the illustrated example, the connection member 32 contains gold (Au) and is a linear member that is thinner than the connection member 31.

[0065] 9 and 13 , the connection member 33 is connected to the first electrode 201 of the semiconductor element 20 and the fourth lead main surface 1411 of the pad portion 141 of the fourth lead 14. In the illustrated example, the connection member 33 contains gold (Au) and is a linear member that is thinner than the connection member 31.

[0066] In this embodiment, the first terminal portion 112 of the first lead 11 is a drain terminal, the multiple second terminal portions 122 of the second lead 12 are source terminals, the third terminal portion 132 of the third lead 13 is a gate terminal, and the fourth terminal portion 142 of the fourth lead 14 is a source sense terminal.

[0067] As shown in FIGS. 1 to 18 , the sealing resin 40 covers the semiconductor element 20, the plurality of connecting members 31, 32, and 33, and portions of the first lead 11, the second lead 12, the third lead 13, and the fourth lead 14. The sealing resin 40 has electrical insulation properties. The sealing resin 40 is made of a material containing, for example, black epoxy resin. The sealing resin 40 has a first resin surface 41, a second resin surface 42, a third resin surface 43, a fourth resin surface 44, a fifth resin surface 45, and a sixth resin surface 46.

[0068] The first resin surface 41 faces the same side (downward) as the first lead main surface 1111 of the die pad portion 111 of the first lead 11 in the thickness direction z. The second resin surface 42 faces the opposite side (upward) from the first resin surface 41 in the thickness direction z. A first lead back surface 1112 of the die pad portion 111 of the first lead 11 is exposed from the second resin surface 42. The second resin surface 42 and the first lead back surface 1112 are flush with each other. The first lead back surface 1112 is separated from the third resin surface 43 in the first direction x.

[0069] The third resin surface 43 faces one side in the first direction x. A first terminal root portion 1121 of the first terminal portion 112 of the first lead 11 penetrates the third resin surface 43. In the present embodiment, one first terminal root portion 1121 penetrates the third resin surface 43. The first terminal root portion 1121 is spaced apart from the second resin surface 42 in the thickness direction z.

[0070] The fourth resin surface 44 faces the opposite side (the other side) in the first direction x to the third resin surface 43. In the present embodiment, second terminal root portions 1221 of the second terminal portions 122 of the second lead 12, root portions 1321 of the third terminal portions 132 of the third lead 13, and root portions 1421 of the fourth terminal portions 142 of the fourth lead 14 penetrate the fourth resin surface 44.

[0071] The fifth resin surface 45 and the sixth resin surface 46 face opposite each other in the second direction y. The sixth resin surface 46 faces one side of the second direction y, and the fifth resin surface 45 faces the other side of the second direction y.

[0072] 8 , the ends in the second direction y of the two first terminal tip portions 1122 of the first terminal portion 112 of the first lead 11 are located at approximately the same positions in the second direction y as the fifth resin surface 45 and the sixth resin surface 46 of the sealing resin 40. The ends in the second direction y of the two first terminal tip portions 1122 may or may not protrude outside the fifth resin surface 45 and the sixth resin surface 46, respectively, in the second direction y.

[0073] FIG. 19 shows the semiconductor device A10 in use. In this example, the semiconductor device A10 is surface-mounted on a circuit board 92. That is, the first terminal tip 1122 of each first terminal 112, the second terminal tip 1222 of each second terminal 122, the tip 1322 of the third terminal 132, and the tip 1422 of the fourth terminal 142 are conductively joined to a wiring pattern (not shown) of the circuit board 92, for example, by solder 921. A heat sink 91 is disposed opposite the first lead back surface 1112 of the die pad 111. In the illustrated example, a sheet material 919 is disposed between the first lead back surface 1112 and the heat sink 91. The sheet material 919 is, for example, an insulating sheet. In the illustrated example, there is a small gap between the sealing resin 40 (first resin surface 41) and the circuit board 92, but the first resin surface 41 may be in contact with the circuit board 92.

[0074] 20 shows a vehicle V equipped with a semiconductor device A10. The vehicle V is, for example, an electric vehicle (EV).

[0075] As shown in FIG. 20 , a vehicle V includes an on-board charger 95, a storage battery 96, and a drive system 97. The on-board charger 95 is supplied with power wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 95 via a wired connection. The on-board charger 95 is configured with a step-up DC-DC converter. As shown in FIG. 20 , the semiconductor device A10 is part of the on-board charger 95 and is used, for example, in the DC-DC converter described above. The voltage of the power supplied to the on-board charger 95 is boosted by the converter and then supplied to the storage battery 96. The boosted voltage is, for example, 600 V.

[0076] The drive system 97 drives the vehicle V. The drive system 97 includes an inverter 971 and a drive source 972. The power stored in the storage battery 96 is supplied to the inverter 971. The power supplied from the storage battery 96 to the inverter 971 is DC power. Alternatively, unlike the power system shown in FIG. 20 , a step-up DC-DC converter may be further provided between the storage battery 96 and the inverter 971. The inverter 971 converts DC power into AC power. The inverter 971 is electrically connected to the drive source 972. The drive source 972 includes an AC motor and a transmission. When the AC power converted by the inverter 971 is supplied to the drive source 972, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle V. This drives the vehicle V. When driving the vehicle V, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, the inverter 971 is necessary to output AC power whose frequency is appropriately changed so as to correspond to the required rotation speed of the AC motor.

[0077] 21 shows a step in the manufacturing method of the semiconductor device A10. In the step shown in Fig. 21, the conductive member 10 is in the form of a lead frame 80 before being separated into the first lead 11, the second lead 12, the third lead 13, and the fourth lead 14.

[0078] As shown in FIG. 21 , the lead frame 80 includes a frame body 81. The frame body 81 connects the first lead 11, the second lead 12, the third lead 13, and the fourth lead 14 to one another. A through hole 1120 is formed at the connection portion between the first lead 11 and the frame body 81. The shape of the through hole 1120 as viewed in the thickness direction z is not limited in any way, but in the illustrated example, it is rectangular. In this state, plating is applied to the lead frame 80. As a result, the surface of the lead frame 80 is covered with a thin metal film by the plating, and the inside of the through hole 1120 is also covered with the thin metal film by the plating. This thin metal film becomes each of the metal layers 110, 120, 130, and 140.

[0079] After this plating, the semiconductor element 20 is mounted, the multiple connection members 31, 32, and 33 are bonded, and the sealing resin 40 is formed. Then, the first lead 11, the second lead 12, the third lead 13, and the fourth lead 14 are separated from the frame body 81 by cutting along the cutting line CL, and the first terminal portion 112 of the first lead 11, the second terminal portion 122 of the second lead 12, the third terminal portion 132 of the third lead 13, and the fourth terminal portion 142 of the fourth lead 14 are bent, respectively. The order of cutting along the cutting line CL and bending the first terminal portion 112 of the first lead 11, the second terminal portion 122 of the second lead 12, the third terminal portion 132 of the third lead 13, and the fourth terminal portion 142 of the fourth lead 14 may be reversed or may be simultaneous. In this manner, each semiconductor device A10 is formed.

[0080] The semiconductor device A10 has the following functions and effects.

[0081] As shown in FIG. 19 , the first lead back surface 1112 is exposed from the second resin surface 42. This allows, for example, a heat sink 91 to be disposed opposite the first lead back surface 1112. The first terminal tip portion 1122 is located lower in the thickness direction z than the first terminal root portion 1121. This allows the semiconductor device A10 to be surface-mounted on a circuit board 92 or the like using the first terminal tip portion 1122. The first lead back surface 1112 is spaced apart from the third resin surface 43 in the first direction x. The first terminal root portion 1121 is spaced apart from the second resin surface 42 in the thickness direction z. Therefore, a portion of the sealing resin 40 exists between the first lead back surface 1112 and the first terminal root portion 1121. This allows the sealing resin 40 to hold the first lead 11 more firmly.

[0082] The first terminal 112 has a first terminal tip 1122, which has a first tip surface 1122a and a concave surface 1122d. The first tip surface 1122a is exposed from the metal layer 110, and the concave surface 1122d is covered by the metal layer 110. With this configuration, the area of ​​the first terminal tip 1122 that is covered by the metal layer 110 is expanded. This can increase the mounting strength of the semiconductor device A10.

[0083] The first tip surface 1122a includes two exposed regions 1122b, which are spaced apart in the first direction x. With this configuration, the concave surface 1122d is connected in the thickness direction z to the upper surface (the surface facing downward in the thickness direction z) and the lower surface (the surface facing upward in the thickness direction z) of the first terminal tip portion 1122, thereby ensuring an appropriate area for the concave surface 1122d. Therefore, an appropriate area of ​​the first terminal portion 112 covered by the metal layer 110 can be ensured, thereby preventing insufficient mounting strength of the semiconductor device A10.

[0084] The first terminal portion 112 has a first terminal intermediate portion 1123. This makes it possible to more reliably support the first terminal tip portion 1122.

[0085] The first terminal portion 112 has two first terminal tip portions 1122. This can increase the mounting strength of the semiconductor device A10.

[0086] The two first terminal tip portions 1122 extend outward in the second direction y from the first terminal intermediate portion 1123. This can further increase the mounting strength of the semiconductor device A10.

[0087] The size of the first terminal root portion 1121 in the second direction y is smaller than the size of the die pad portion 111 in the second direction y. This allows the holding force of the sealing resin 40 to hold the first lead 11 further increased.

[0088] The first terminal tip portion 1122 does not protrude from the first terminal middle portion 1123 in the first direction x, thereby enabling the size of the semiconductor device A10 in the first direction x to be reduced.

[0089] The size of the die pad portion 111 in the thickness direction z is larger than the size of the first terminal root portion 1121 in the thickness direction z. This allows the heat to be conducted over a wider range in the first direction x and the second direction y in the process of heat conduction from the semiconductor element 20 to the first lead back surface 1112. Therefore, the heat from the semiconductor element 20 can be dissipated to the heat sink 91 or the like over an area wider than the first terminal root portion 1121, thereby improving the heat dissipation efficiency.

[0090] The lower surface (the surface facing downward in the thickness direction z) of the first terminal root portion 1121 is flush with the first lead main surface 1111. This makes it possible to increase the distance from the first terminal root portion 1121 to the third resin surface 43 in the thickness direction z, and further increase the holding force of the sealing resin 40 for the first lead 11.

[0091] A recess 113 is formed in the first terminal portion 112. With this configuration, even if the sealing resin 40 extends along the root side surface 1121a during the formation of the sealing resin 40, the recess 113 can be prevented from forming before the recess 113. Therefore, the semiconductor device A10 can suppress resin burrs. In particular, in the semiconductor device A10, the recess 113 is formed on the root side surface 1121a of the first terminal root portion 1121 of the first terminal portion 112, as viewed in the thickness direction z. With this configuration, resin burrs can be prevented from forming on the first terminal tip portion 1122, and therefore, when the semiconductor device A10 is surface-mounted on a circuit board 92 or the like, resin burrs can be prevented from being interposed between the first terminal tip portion 1122 and the circuit board 92 or the like. Therefore, mounting defects of the semiconductor device A10 can be suppressed. Since the formation of resin burrs on first terminal intermediate portion 1123 can be suppressed, processing defects that may occur due to the resin burrs when first terminal intermediate portion 1123 is bent can be suppressed.

[0092] Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other as long as no technical contradiction occurs.

[0093] 22 to 25 show a semiconductor device A20 according to a second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in that the first end surface 1122a of each first terminal end portion 1122 has a connecting region 1122c. Unless otherwise specified, the connecting region 1122c described below is common to the first end surface 1122a of each first terminal end portion 1122.

[0094] As shown in Figures 23 and 25, the connecting region 1122c is connected to the two exposed regions 1122b. In the illustrated example, the connecting region 1122c is disposed on the upper side in the thickness direction z. Thus, the connecting region 1122c is connected to the upper surface (surface facing upward in the thickness direction z) of the first terminal tip portion 1122, and the concave surface 1122d is connected to the lower surface (surface facing downward in the thickness direction z) of the first terminal tip portion 1122. Unlike the illustrated example, the connecting region 1122c may be disposed on the lower side in the thickness direction z. Thus, the connecting region 1122c may be connected to the lower surface (surface facing downward in the thickness direction z) of the first terminal tip portion 1122, and the concave surface 1122d may be connected to the upper surface (surface facing upward in the thickness direction z) of the first terminal tip portion 1122.

[0095] The shape of each first terminal tip portion 1122 is formed, for example, as follows: In the state of lead frame 80 shown in Fig. 21 , a groove recessed from the lower side (bottom surface side) in the thickness direction z is formed in place of through hole 1120, and then, by cutting along cutting line CL later, connecting region 1122c is formed on first tip surface 1122a.

[0096] According to this embodiment, the semiconductor device A20 can be surface-mounted using the first terminal tip portion 1122. In the semiconductor device A20, similar to the semiconductor device A10, the first tip surface 1122a is exposed from the metal layer 110, and the concave surface 1122d is covered by the metal layer 110. Therefore, according to this embodiment, the area of ​​the first terminal tip portion 1122 covered by the metal layer 110 is expanded, thereby enhancing the mounting strength of the semiconductor device A20. However, when comparing the area of ​​the concave surface 1122d of the semiconductor device A10 with the area of ​​the concave surface 1122d of the semiconductor device A20, the area of ​​the concave surface 1122d of the semiconductor device A10 is larger. In other words, the semiconductor device A10 is preferable in terms of enhancing the mounting strength of the semiconductor device of the present disclosure. Furthermore, similar to the semiconductor device A10, the semiconductor device A20 has a recess 113 formed in the first terminal portion 112. Therefore, according to this embodiment, resin burrs can also be suppressed, and defects of the semiconductor device A20 caused by resin burrs (for example, the above-mentioned mounting defects and processing defects) can be suppressed. In addition, the semiconductor device A20 has a common configuration with the semiconductor device A10, and therefore exhibits the same effects as the semiconductor device A10.

[0097] 26 to 29 show a semiconductor device A30 according to a third embodiment. The semiconductor device A30 differs from the semiconductor device A10 in the shape of each first terminal tip portion 1122.

[0098] 26 to 29 , in the semiconductor device A30, each tip portion in the second direction y of the two first terminal tip portions 1122 is bifurcated. As shown in FIGS. 28 and 29 , in the two first terminal tip portions 1122, each bifurcated tip portion protrudes on both sides in the first direction x beyond the portion connected to the first terminal intermediate portion 1123. Therefore, the two exposed regions 1122b are located outward from the first terminal intermediate portion 1123 when viewed from the first tip surface 1122a in the direction connected to the corresponding first terminal intermediate portion 1123.

[0099] This embodiment also enables surface mounting of the semiconductor device A30 using the first terminal tip portion 1122. In the semiconductor device A30, similar to the semiconductor device A10, the first tip surface 1122a is exposed from the metal layer 110, and the concave surface 1122d is covered by the metal layer 110. Therefore, this embodiment also expands the area of ​​the first terminal tip portion 1122 covered by the metal layer 110, thereby improving the mounting strength of the semiconductor device A30. In particular, the area of ​​the concave surface 1122d of the semiconductor device A30 is larger than that of the semiconductor device A10, making the semiconductor device A30 preferable for improving the mounting strength of the semiconductor device disclosed herein. Furthermore, similar to the semiconductor device A10, the semiconductor device A30 has a recess 113 formed in the first terminal portion 112. Therefore, this embodiment also suppresses resin burrs, thereby reducing defects of the semiconductor device A30 (e.g., the above-mentioned mounting defects and processing defects) caused by resin burrs. In addition, the semiconductor device A30 has a configuration common to the semiconductor devices A10 and A20, and therefore exhibits the same effects as the semiconductor devices A10 and A20.

[0100] The area of ​​the concave surface 1122d of the semiconductor device A30 is larger than the area of ​​the concave surface 1122d of the semiconductor device A10. With this configuration, the area covered by the metal layer 110 in the first terminal tip portion 1122 is further expanded, thereby further increasing the mounting strength of the semiconductor device A30.

[0101] 30 to 33 show a semiconductor device A40 according to a fourth embodiment. The semiconductor device A40 differs from the semiconductor device A10 in the arrangement of the first tip surfaces 1122a of the first terminal tip portions 1122.

[0102] In the first terminal tip portion 1122 of the semiconductor device A40, the first tip surface 1122a is sandwiched between two concave surfaces 1122d in the first direction x. In other words, the two concave surfaces 1122d are arranged on both sides of the first tip surface 1122a in the first direction x.

[0103] This embodiment also enables surface mounting of the semiconductor device A40 using the first terminal tip portion 1122. In the semiconductor device A40, similar to the semiconductor device A10, the first tip surface 1122a is exposed from the metal layer 110, and the concave surface 1122d is covered by the metal layer 110. Therefore, this embodiment also expands the area of ​​the first terminal tip portion 1122 covered by the metal layer 110, thereby increasing the mounting strength of the semiconductor device A40. Furthermore, similar to the semiconductor device A10, the semiconductor device A40 has a recess 113 formed in the first terminal portion 112. Therefore, this embodiment also suppresses resin burrs, thereby suppressing defects of the semiconductor device A40 (e.g., the above-mentioned mounting defects and processing defects) caused by resin burrs. Furthermore, the semiconductor device A40 has a configuration common to the semiconductor devices A10, A20, and A30, and thus achieves the same effects as the semiconductor devices A10, A20, and A30.

[0104] In the semiconductor device A40, the first terminal tip portion 1122 has two concave surfaces 1122d. With this configuration, the area covered by the metal layer 110 in the first terminal tip portion 1122 is further expanded compared to the semiconductor device A10, thereby further increasing the mounting strength of the semiconductor device A40.

[0105] 34 shows a semiconductor device A50 according to a fifth embodiment. The semiconductor device A50 differs from the semiconductor device A10 in the configuration of the first terminal portion 112.

[0106] In the semiconductor device A50, the first terminal portion 112 includes a first terminal root portion 1121, one first terminal tip portion 1122, and one first terminal intermediate portion 1123. The first terminal intermediate portion 1123 extends downward in the thickness direction z from the first terminal root portion 1121 and is rectangular when viewed in the first direction x. The size of the first terminal intermediate portion 1123 in the second direction y is the same as the size of the first terminal root portion 1121 in the second direction y.

[0107] The first terminal tip portion 1122 extends from the first terminal intermediate portion 1123 to one side (outside) in the first direction x. When viewed in the thickness direction z, the first terminal tip portion 1122 has a rectangular shape with the second direction y as its longitudinal direction. Both ends of the first terminal tip portion 1122 in the second direction y protrude outward in the second direction y from the first terminal intermediate portion 1123. The positions of both ends of the first terminal tip portion 1122 in the second direction y are the same as (or approximately the same as) the fifth resin surface 45 and the sixth resin surface 46 of the sealing resin 40. These end positions may or may not protrude outward in the second direction y from the fifth resin surface 45 and the sixth resin surface 46. In this embodiment, a first tip surface 1122a and a concave surface 1122d are respectively disposed at both ends of the first terminal tip portion 1122 in the second direction y.

[0108] This embodiment also enables surface mounting of the semiconductor device A50 using the first terminal tip portion 1122. In the semiconductor device A50, similar to the semiconductor device A10, the first tip surface 1122a is exposed from the metal layer 110, and the concave surface 1122d is covered by the metal layer 110. Therefore, this embodiment also expands the area of ​​the first terminal tip portion 1122 covered by the metal layer 110, thereby increasing the mounting strength of the semiconductor device A50. Furthermore, similar to the semiconductor device A10, the semiconductor device A50 has a recess 113 formed in the first terminal portion 112. Therefore, this embodiment also suppresses resin burrs, thereby suppressing defects of the semiconductor device A50 (e.g., the above-mentioned mounting defects and processing defects) caused by resin burrs. Furthermore, the semiconductor device A50 has a configuration common to the semiconductor devices A10, A20, and A30, and thus achieves the same effects as the semiconductor devices A10, A20, and A30. As can be understood from this embodiment, in the semiconductor device of the present disclosure, the specific configurations of the first terminal tip portion 1122 and the first terminal intermediate portion 1123 are not limited in any way.

[0109] 35 shows a semiconductor device A51 according to a modification of the fifth embodiment. The semiconductor device A51 differs from the semiconductor device A50 in the arrangement of the first tip surface 1122a and the concave surface 1122d.

[0110] In the semiconductor device A51, a first tip surface 1122a and multiple concave surfaces 1122d are arranged at the outer end in the first direction x of the first terminal tip portion 1122. The first tip surface 1122a faces one side in the first direction x. In the first terminal tip portion 1122 of the semiconductor device A51, the number of concave surfaces 1122d is not limited in any way and may be, for example, one.

[0111] In the semiconductor device A50, both ends of the first terminal tip portion 1122 in the second direction y are connected to the frame body 81 of the lead frame 80, and therefore the end faces on both sides of the first terminal tip portion 1122 in the second direction y are first tip faces 1122a. On the other hand, in the semiconductor device A51, one end of the first terminal tip portion 1122 in the first direction x is connected to the frame body 81 of the lead frame 80, and therefore the end face on one side of the first terminal tip portion 1122 in the first direction x is the first tip face 1122a. In this way, the arrangement of the concave surface 1122d differs depending on the connection portion between the first terminal tip portion 1122 and the frame body 81 of the lead frame 80.

[0112] This embodiment also enables surface mounting of the semiconductor device A51 using the first terminal tip portion 1122. In the semiconductor device A51, similar to the semiconductor device A50, the first tip surface 1122a is exposed from the metal layer 110, and the concave surface 1122d is covered by the metal layer 110. Therefore, this embodiment also expands the area of ​​the first terminal tip portion 1122 covered by the metal layer 110, thereby increasing the mounting strength of the semiconductor device A51. Furthermore, similar to the semiconductor device A50, the semiconductor device A51 has a recess 113 formed in the first terminal portion 112. Therefore, this embodiment also suppresses resin burrs, thereby suppressing defects of the semiconductor device A51 (e.g., the above-mentioned mounting defects and processing defects) caused by resin burrs. Furthermore, the semiconductor device A51 achieves the same effects as the semiconductor device A50 due to the configuration common to the semiconductor device A50.

[0113] 36 to 42 illustrate semiconductor devices according to modified examples of the present disclosure. While FIGS. 36 to 42 illustrate an example in which the present disclosure is applied to the semiconductor device A10 according to the first embodiment, the present disclosure can also be applied to the semiconductor devices A20, A30, A40, and A50 according to the other embodiments (second to fifth embodiments). The semiconductor devices according to the modified examples described below share the same feature as the semiconductor device A10 in that the first terminal portion 112 includes a first terminal tip portion 1122. Therefore, similar to the semiconductor device A10, the semiconductor device can be surface-mounted using the first terminal tip portion 1122. The semiconductor devices according to the modified examples described below share the same feature in that the first tip surface 1122a is exposed from the metal layer 110 and the concave surface 1122d is covered by the metal layer 110. Therefore, similar to the semiconductor device A10, the area of ​​the first terminal tip portion 1122 covered by the metal layer 110 is expanded, thereby enhancing the mounting strength of the semiconductor device. Furthermore, the semiconductor devices according to the modifications described below have in common the formation of recesses 113 in the first terminal portions 112. Therefore, similar to the semiconductor device A10, resin burrs can be suppressed, and defects of the semiconductor device caused by resin burrs (for example, the above-mentioned mounting defects and processing defects) can be suppressed.

[0114] FIG. 36 illustrates a semiconductor device according to a first modification. The semiconductor device illustrated in FIG. 36 differs from the semiconductor device A10 in the arrangement of the recesses 113. In the semiconductor device illustrated in FIG. 36, the two first terminal intermediate portions 1123 of the first terminal portion 112 each have an extending surface 1123a. Each of the pair of extending surfaces 1123a faces the third resin surface 43 of the sealing resin 40. The pair of extending surfaces 1123a are individually connected to the pair of base side surfaces 1121a. In this embodiment, the two recesses 113 are individually formed on the pair of extending surfaces 1123a. In particular, in the example illustrated in FIG. 36, each recess 113 is arranged on the side of the corresponding extending surface 1123a that is connected to the base side surface 1121a. The arrangement of each recess 113 is not limited in any way as long as it is formed on the extending surface 1123a.

[0115] As can be understood from this modification, in the semiconductor device of the present disclosure, the arrangement of the recesses 113 is not limited to the configuration in which they are formed on each root side surface 1121 a, but they may be formed on each extending surface 1123 a. Alternatively, the recesses 113 may be arranged on the upper surface (surface facing upward in the thickness direction z) of the first terminal root portion 1121 of the first terminal portion 112 or on the lower surface (surface facing downward in the thickness direction z) of the first terminal root portion 1121.

[0116] Fig. 37 shows a semiconductor device according to a second modification. The semiconductor device shown in Fig. 37 differs from the semiconductor device A10 in that the first terminal portion 112 includes a recess 114. The recess 114 is formed in the first terminal root portion 1121. When viewed in the thickness direction z, the recess 114 is recessed from a surface of the first terminal root portion 1121 facing one side in the first direction x.

[0117] FIG. 38 shows a step in the manufacturing method of the semiconductor device shown in FIG. 37 . As shown in FIG. 38 , the first terminal root portion 1121 is connected to the frame body 81 of the lead frame 80. The lead frame 80 has a notch 82 on each side of this connected portion in the second direction y. The notch 82 is recessed when viewed in the thickness direction z. When manufacturing the semiconductor device shown in FIG. 37 , the first terminal root portion 1121 is cut from the frame body 81 using the notch 82. This forms the recess 114 shown in FIG. 37 . By cutting using the notch 82 in this manner, it is possible to prevent the surface of the first terminal root portion 1121 facing one side in the first direction x from protruding beyond the surfaces of each first terminal tip portion 1122 and each first terminal intermediate portion 1123 facing one side in the first direction x.

[0118] 39 and 40 show a semiconductor device according to a third modification. The semiconductor device shown in Fig. 39 and 40 differs from the semiconductor device A10 in the following respects. First, the sealing resin 40 of the semiconductor device according to this modification includes a pair of recesses 47. Second, the sealing resin 40 of the semiconductor device according to this modification includes a groove 49.

[0119] One of the recesses 47 is recessed from the first resin surface 41 and the fifth resin surface 45. The other recess 47 is recessed from the first resin surface 41 and the sixth resin surface 46. A portion of the first lead main surface 1111 is exposed from each recess 47. The pair of recesses 47 is formed by fixing the die pad portion 111 with a jig during the manufacturing of the semiconductor device according to this modification. In other words, the pair of recesses 47 are traces of the placement of the jig. In this way, since the die pad portion 111 is fixed with a jig during the manufacturing of the semiconductor device according to this modification, vibration and tilt of the die pad portion 111 can be suppressed. This can suppress poor bonding between the die pad portion 111 and the semiconductor element 20.

[0120] The groove 49 is recessed from the second resin surface 42 in the thickness direction z and extends along the second direction y. The groove 49 extends from the fifth resin surface 45 to the sixth resin surface 46. The groove 49 is located between the first lead back surface 1112 and the fourth resin surface 44. The inclusion of the groove 49 in the sealing resin 40 can extend the distance (creepage distance) along the surface of the sealing resin 40 between the first lead back surface 1112 (first lead 11) and each of the second terminal portions 122 (second lead 12), third terminal portions 132 (third lead 13), and fourth terminal portions 142 (fourth lead 14). This can improve the dielectric strength between the first lead 11 and the second lead 12, third lead 13, and fourth lead 14. In the illustrated example, one groove 49 is formed in the sealing resin 40, but multiple grooves 49 may be formed. For example, the multiple grooves 49 are arranged parallel to each other in the first direction x.

[0121] Fig. 41 shows a semiconductor device according to a fourth modification. The semiconductor device shown in Fig. 41 differs from the semiconductor devices shown in Fig. 39 and 40 in that the sealing resin 40 includes a protrusion 48 instead of a groove 49.

[0122] The protrusion 48 protrudes upward in the thickness direction z from the second resin surface 42. The protrusion 48 extends along the second direction y, from the fifth resin surface 45 to the sixth resin surface 46. In the illustrated example, the protrusion 48 is disposed at the other end of the sealing resin 40 in the first direction x and contacts the fourth resin surface 44. The sealing resin 40 has the protrusion 48, which can extend the creepage distance between the first lead back surface 1112 (first lead 11) and each of the second terminal portion 122 (second lead 12), the third terminal portion 132 (third lead 13), and the fourth terminal portion 142 (fourth lead 14). This can improve the dielectric strength between the first lead 11 and the second lead 12, the third lead 13, and the fourth lead 14.

[0123] Fig. 42 shows a semiconductor device according to the fifth modification. The semiconductor device shown in Fig. 42 differs from the semiconductor device A10 in the following respect: two first terminal tip portions 1122 are bent inward relative to two first terminal intermediate portions 1123, respectively.

[0124] 42 , the two first terminal tip portions 1122 extend individually inward in the second direction y from the two first terminal intermediate portions 1123. Therefore, the two first terminal tip portions 1122 extend toward each other. The first tip surfaces 1122a of the two first terminal tip portions 1122 face each other.

[0125] As can be understood from this modification, in the semiconductor device of the present disclosure, the extending direction of first terminal tip portion 1122 relative to first terminal intermediate portion 1123 is not limited in any way.

[0126] In the above-described first to fifth embodiments and each modified example, an example has been shown in which concave surface 1122d is formed on first terminal tip portion 1122. However, in addition to or instead of this, a concave surface may be formed on at least one of second terminal tip portion 1222, tip portion 1322, or tip portion 1422. In other words, the shape of at least one of second terminal tip portion 1222, tip portion 1322, or tip portion 1422 may be configured similarly to the shape of first terminal tip portion 1122.

[0127] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways. For example, the present disclosure includes the embodiments described in the following appendices. Appendix 1. a semiconductor element; a first lead including: a die pad portion having a first lead main surface facing one side in a thickness direction and on which the semiconductor element is mounted and a first lead back surface facing the other side in the thickness direction; and a first terminal portion; and a sealing resin having a first resin surface facing one side in the thickness direction, a second resin surface facing the other side in the thickness direction, and a third resin surface facing one side in a first direction orthogonal to the thickness direction, and covering the semiconductor element and a part of the die pad portion, wherein the first lead includes a metal layer covering a part of the first terminal portion, the first lead back surface is exposed from the second resin surface, the first terminal portion has a first terminal root portion and at least one first terminal tip portion, the first terminal root portion penetrates the third resin surface and is spaced from the first resin surface in the thickness direction, and the at least one first terminal tip portion is located on the one side in the thickness direction relative to the first terminal root portion and is used for mounting, A semiconductor device, wherein the at least one first terminal tip portion has a first tip surface and a concave surface connected to the first tip surface, the first tip surface being exposed from the metal layer, and the concave surface being covered by the metal layer. Appendix 2. The semiconductor device according to Appendix 1, wherein the first tip surface includes two exposed regions spaced apart from each other, and the concave surface is sandwiched between the two exposed regions. Appendix 3. The semiconductor device according to Appendix 2, wherein the two exposed regions are spaced apart in the first direction. Appendix 4. The semiconductor device according to Appendix 3, wherein the first tip surface has a connecting region connecting the two exposed regions and being flush with the two exposed regions, and the connecting region is exposed from the metal layer. Appendix 5. The semiconductor device according to Appendix 4, wherein the at least one first terminal tip portion has a first mounting surface facing one side in the thickness direction and connected to the first tip surface, and the concave surface being connected to the first mounting surface.Appendix 6. The semiconductor device according to any one of claims 3 to 5, wherein the first terminal portion has at least one first terminal intermediate portion individually interposed between the first terminal root portion and the at least one first terminal tip portion. Appendix 7. The semiconductor device according to Appendix 6, wherein the two exposed regions are located outward of the first terminal intermediate portion when viewed in a direction connecting from the first tip surface to the corresponding first terminal intermediate portion. Appendix 8. The semiconductor device according to Appendix 6 or Appendix 7, further comprising a second lead including a first pad portion covered with the sealing resin and at least one second terminal portion exposed from the sealing resin, wherein the sealing resin has a fourth resin surface facing the other side of the first direction, and the at least one second terminal portion penetrates the fourth resin surface. Appendix 9. The semiconductor device according to Appendix 8, wherein the at least one second terminal portion has a second terminal root portion, a second terminal tip portion, and a second terminal intermediate portion. Appendix 10. The semiconductor device according to Supplementary Note 9, wherein the first terminal intermediate portion has a first dimension, the second terminal intermediate portion has a second dimension, the first dimension is a dimension along a direction perpendicular to the thickness direction and the direction in which the first terminal intermediate portion extends as viewed in the thickness direction, the second dimension is a dimension along a direction perpendicular to the thickness direction and the direction in which the second terminal intermediate portion extends as viewed in the thickness direction, and the first dimension is 0.5 to 2 times the second dimension. Supplementary Note 11. The semiconductor device according to any of Supplementary Note 8 to Supplementary Note 10, wherein the at least one second terminal portion includes a plurality of second terminal portions, and each of the plurality of second terminal portions is connected to the first pad portion. Supplementary Note 12. The semiconductor device according to any of Supplementary Note 8 to Supplementary Note 11, further comprising a third lead including a second pad portion covered by the sealing resin and a third terminal portion exposed from the sealing resin, and the third terminal portion penetrating the fourth resin surface. Supplementary Note 13. 13. The semiconductor device according to claim 1, wherein the at least one first terminal tip portion includes two first terminal tip portions, and the two first terminal tip portions extend on opposite sides of the first terminal root portion in a second direction perpendicular to the thickness direction and the first direction.Appendix 14. The semiconductor device according to any one of Appendixes 1 to 13, wherein a recess is formed in the first terminal portion, and the first terminal root portion has a pair of root side surfaces facing opposite each other in the thickness direction and a second direction orthogonal to the first direction, and the recess is recessed from each of the pair of root side surfaces or a pair of extending surfaces of the first terminal portion that are individually connected to each of the pair of root side surfaces, as viewed in the thickness direction. Appendix 15. The semiconductor device according to Appendix 14, wherein the recess is disposed on the pair of root side surfaces. Appendix 16. The semiconductor device according to Appendix 15, wherein the recess is located on each of the pair of root side surfaces that are connected to the pair of extending surfaces in the first direction, as viewed in the thickness direction. Appendix 17. A vehicle comprising: a drive source; a storage battery that stores power to be supplied to the drive source; and an on-board charger that converts power input from an external source and supplies the power to the storage battery, wherein the on-board charger comprises the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 16.

[0128] A10, A20, A30, A40, A50, A51: semiconductor device 10: conductive member 11: first lead 12: second lead 13: third lead 14: fourth lead 20: semiconductor element 29: bonding layer 31, 32, 33: connecting member 40: sealing resin 41: first resin surface 42: second resin surface 43: third resin surface 44: fourth resin surface 45: fifth resin surface 46: sixth resin surface 47: recess 48: protrusion 49: groove 80: lead frame 81: frame 82: notch 91: heat sink 92: circuit board 95: on-board charger 96: storage battery 97: drive system 110: metal layer 111: die pad portion 112: first terminal portion 113: depression 114: recess 120: Metal layer 121: Pad portion 122: Second terminal portion 130: Metal layer 131: Pad portion 132: Third terminal portion 140: Metal layer 141: Pad portion 142: Fourth terminal portion 201: First electrode 202: Second electrode 203: Third electrode 205: Semiconductor layer 919: Sheet material 921: Solder 971: Inverter 972: Driving source 1111: First lead main surface 1112: First lead back surface 1113: First lead side surface 1114: First intermediate surface 1120: Through hole 1121: First terminal root portion 1121a: Root side surface 1122: First terminal tip portion 1122a: First tip surface 1122b: Exposed region 1122c: Connecting region 1122d: Concave surface 1123: First terminal intermediate portion 1123a: Extension surface 1211: Second lead main surface 1212: Second lead back surface 1221: Second terminal root portion 1222: Second terminal tip portion 1223: Second terminal intermediate portion 1311: Third lead main surface 1312: Third lead back surface 1321: Root portion 1322: Tip portion 1323: Intermediate portion 1411: Fourth lead main surface 1412: Fourth lead back surface 1421: Root portion 1422: Tip portion 1423: Intermediate portion CL: Cutting line V: Vehicle

Claims

1. A semiconductor element; a first lead including a die pad portion having a first lead main surface facing one side in a thickness direction and on which the semiconductor element is mounted and a first lead back surface facing the other side in the thickness direction, and a first terminal portion; a sealing resin having a first resin surface facing one side in the thickness direction, a second resin surface facing the other side in the thickness direction, and a third resin surface facing one side in a first direction perpendicular to the thickness direction, the sealing resin covering the semiconductor element and a part of the die pad portion; Equipped with the first lead includes a metal layer covering a portion of the first terminal portion, the rear surface of the first lead is exposed from the second resin surface, the first terminal portion has a first terminal root portion and at least one first terminal tip portion; the first terminal root portion penetrates the third resin surface and is spaced apart from the first resin surface in the thickness direction; the at least one first terminal tip portion is located on the one side in the thickness direction relative to the first terminal root portion and is used for mounting; the at least one first terminal tip portion has a first tip surface and a concave surface connected to the first tip surface; the first tip surface is exposed from the metal layer, The concave surface is covered with the metal layer.

2. the first tip surface includes two exposed regions spaced apart from each other; The semiconductor device according to claim 1 , wherein the concave surface is sandwiched between two exposed regions.

3. The semiconductor device according to claim 2 , wherein the two exposed regions are spaced apart in the first direction.

4. the first tip surface has a connecting region that connects the two exposed regions and is flush with the two exposed regions; The semiconductor device according to claim 3 , wherein the connecting region is exposed from the metal layer.

5. the at least one first terminal tip portion has a first mounting surface facing the one side in the thickness direction and connected to the first tip surface, The semiconductor device according to claim 4 , wherein the concave surface is connected to the first mounting surface.

6. 4. The semiconductor device according to claim 3, wherein the first terminal portion has at least one first terminal intermediate portion interposed between the first terminal root portion and the at least one first terminal tip portion.

7. 7. The semiconductor device according to claim 6, wherein the two exposed regions are located outward from the corresponding first terminal intermediate portions when viewed in a direction from the first end face to the corresponding first terminal intermediate portions.

8. a second lead including a first pad portion covered with the sealing resin and at least one second terminal portion exposed from the sealing resin; the sealing resin has a fourth resin surface facing the other side of the first direction, The semiconductor device according to claim 6 , wherein the at least one second terminal portion penetrates the fourth resin surface.

9. The semiconductor device according to claim 8 , wherein the at least one second terminal portion has a second terminal root portion, a second terminal tip portion, and a second terminal middle portion.

10. the first terminal intermediate portion has a first dimension; the second terminal intermediate portion has a second dimension; the first dimension is a dimension along a direction perpendicular to the thickness direction and a direction in which the first terminal intermediate portion extends as viewed in the thickness direction, the second dimension is a dimension along a direction perpendicular to the thickness direction and a direction in which the second terminal intermediate portion extends as viewed in the thickness direction, The semiconductor device according to claim 9 , wherein the first dimension is 0.5 to 2 times the second dimension.

11. the at least one second terminal portion includes a plurality of second terminal portions, The semiconductor device according to claim 8 , wherein each of said plurality of second terminal portions is connected to said first pad portion.

12. a third lead including a second pad portion covered with the sealing resin and a third terminal portion exposed from the sealing resin; The semiconductor device according to claim 8 , wherein the third terminal portion penetrates the fourth resin surface.

13. the at least one first terminal tip includes two first terminal tips; 13. The semiconductor device according to claim 1, wherein the two first terminal tip portions extend in opposite directions from the first terminal root portion in a second direction perpendicular to the thickness direction and the first direction.

14. The first terminal portion has a recess formed therein, the first terminal base portion has a pair of base side surfaces facing opposite to each other in the thickness direction and a second direction perpendicular to the first direction, 13. The semiconductor device according to claim 1, wherein the recess is recessed from each of the pair of root side surfaces of the first terminal portion or a pair of extension surfaces that are individually connected to each of the pair of root side surfaces, when viewed in the thickness direction.

15. The semiconductor device according to claim 14 , wherein the recesses are disposed on the pair of root side surfaces.

16. The semiconductor device according to claim 15 , wherein the recess is located on each of the pair of base side surfaces that are connected to the pair of extending surfaces in the first direction, as viewed in the thickness direction.

17. A driving source; a storage battery that stores power to be supplied to the driving source; an on-board charger that converts power input from an external source and supplies the converted power to the storage battery; Equipped with A vehicle, wherein the on-board charger comprises the semiconductor device according to claim 1 .