Semiconductor device

Abstract

This semiconductor device comprises: a chip which has a main surface; a semiconductor region which has a first conductivity type and is formed in a surface layer part of the main surface; a trench type gate structure which is formed in the main surface so as to be positioned within the semiconductor region; a body region which has a second conductivity type and is formed in a region that is on the main surface side with respect to the depth position of a bottom wall of the gate structure in the surface layer part of the main surface; and a high concentration region which has the first conductivity type and is formed within the thickness range between the bottom wall of the gate structure and the bottom of the body region within the chip, and which has an impurity concentration that is higher than the impurity concentration of the semiconductor region.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-093514 filed with the Japan Patent Office on June 6, 2023, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2010 / 0224932A1) discloses a semiconductor device including a semiconductor substrate, a drift region, a body region, a gate trench, a gate insulating film, a gate electrode, and a p-type diffusion region. The drift region is formed on the upper surface side of the semiconductor substrate. The body region is formed on the upper surface side of the semiconductor substrate relative to the drift region.

[0003] The gate trench is formed in the upper surface of the semiconductor substrate and penetrates the body region. The gate insulating film covers the wall surface of the gate trench. The gate electrode is buried in the gate trench via the gate insulating film. The p-type diffusion region is formed along the bottom wall of the gate trench in the drift region.

[0004] US Patent Application Publication No. 2010 / 0224932

[0005] [Summary] The present disclosure provides a semiconductor device that can improve electrical characteristics.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; a first conductivity type semiconductor region formed in a surface layer portion of the main surface; a trench-type gate structure formed on the main surface and positioned within the semiconductor region; a second conductivity type body region formed in a region in the surface layer portion of the main surface on the main surface side with respect to a depth position of a bottom wall of the gate structure; and a first conductivity type high concentration region formed in the chip in a thickness range between the bottom wall of the gate structure and a bottom of the body region, the high concentration region having an impurity concentration higher than the impurity concentration of the semiconductor region.

[0007] The above and further objects, features and advantages will become more apparent from the accompanying drawings and detailed description.

[0008] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing an example layout of a main portion of the first main surface. FIG. 5 is a cross-sectional view taken along line VV in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is an enlarged cross-sectional view of a region including a gate structure shown in FIG. 5. FIG. 8 is an enlarged cross-sectional view of a region including a gate structure shown in FIG. 6. FIG. 9 is a schematic diagram showing a wafer used in manufacturing a semiconductor device. FIG. 10A is a cross-sectional view showing an example method for manufacturing a semiconductor device. FIG. 10B is a cross-sectional view showing a step subsequent to FIG. 10A. FIG. 10C is a cross-sectional view showing a step subsequent to FIG. 10B. FIG. 10D is a cross-sectional view showing a step subsequent to FIG. 10C. FIG. 10E is a cross-sectional view showing a step subsequent to FIG. 10D. FIG. 10F is a cross-sectional view showing a step subsequent to FIG. 10E. FIG. 10G is a cross-sectional view showing a step subsequent to FIG. 10F. 10H is a cross-sectional view showing a step after FIG. 10G. FIG. 10I is a cross-sectional view showing a step after FIG. 10H. FIG. 10J is a cross-sectional view showing a step after FIG. 10I. FIG. 10K is a cross-sectional view showing a step after FIG. 10J. FIG. 10L is a cross-sectional view showing a step after FIG. 10K. FIG. 10M is a cross-sectional view showing a step after FIG. 10L. FIG. 10N is a cross-sectional view showing a step after FIG. 10M. FIG. 10O is a cross-sectional view showing a step after FIG. 10N. FIG. 10P is a cross-sectional view showing a step after FIG. 10O. FIG. 11 is a cross-sectional view showing a main part of a semiconductor device according to the second embodiment. FIG. 12 is a plan view showing a main part of a semiconductor device according to the third embodiment. FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 12. FIG. 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. 12. FIG. 15 is an enlarged cross-sectional view of a region including a source structure shown in FIG. 13. Fig. 16 is an enlarged cross-sectional view of a region including the source structure shown in Fig. 14. Fig. 17 is a plan view showing a main part of a semiconductor device according to a fourth embodiment. Fig. 18 is a cross-sectional view showing a semiconductor device according to a first modified example. Fig. 19 is a cross-sectional view showing a semiconductor device according to a second modified example. Fig. 20 is a cross-sectional view showing a semiconductor device according to a third modified example. Fig. 21 is a cross-sectional view showing a semiconductor device according to a fourth modified example. Fig. 22 is a cross-sectional view showing a semiconductor device according to a fifth modified example.23, 24, and 25 are cross-sectional views showing a semiconductor device according to a sixth, seventh, and eighth modifications, respectively.

[0009] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] FIG. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface 3. FIG. 4 is an enlarged plan view showing an example layout of a main portion of the first main surface 3. FIG. 5 is a cross-sectional view taken along line VV shown in FIG. 4. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4. FIG. 7 is an enlarged cross-sectional view of a region including a gate structure 15 shown in FIG. 5. FIG. 8 is an enlarged cross-sectional view of a region including a gate structure 15 shown in FIG. 6.

[0013] 1 to 8, semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1A is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip."

[0014] In this embodiment, the chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of another polytype.

[0015] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0016] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0017] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0018] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0019] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical line toward the off-axis direction by the off-axis angle. The c-plane of the SiC single crystal is also inclined with respect to the horizontal plane by the off-axis angle.

[0020] The off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0021] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0022] The semiconductor device 1A includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4 of the chip 2. A drain potential is applied to the first semiconductor region 6 as a first potential (high potential). The first semiconductor region 6 may also be referred to as a "semiconductor layer," a "first semiconductor layer," a "drain region," or the like. The first semiconductor region 6 has a capacitance of 1×10 １４ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may be as follows:

[0023] The first semiconductor region 6 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. In this embodiment, the first semiconductor region 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. The first semiconductor region 6 (substrate) has the off direction and off angle described above.

[0024] The first semiconductor region 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor region 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0025] The semiconductor device 1A includes an n-type second semiconductor region 7 formed in a surface layer portion of the first main surface 3 of the chip 2. The second semiconductor region 7 may be referred to as a "semiconductor layer," a "second semiconductor layer," a "drift region," or the like. The second semiconductor region 7 has an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor region 6. The n-type impurity concentration of the second semiconductor region 7 is 1×10 １４ cm －３ 1x10 or more １８ cm －３ It may be the following:

[0026] The second semiconductor region 7 is formed in a layer shape extending along the first main surface 3 and is electrically connected to the first semiconductor region 6. The second semiconductor region 7 is exposed from the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. In this embodiment, the second semiconductor region 7 is made of an n-type semiconductor layer.

[0027] Specifically, the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) containing SiC single crystal (semiconductor single crystal), and forms the first main surface 3 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. The second semiconductor region 7 (epitaxial layer) has the off direction and off angle described above. The second semiconductor region 7 preferably has a thickness less than that of the first semiconductor region 6. The thickness of the second semiconductor region 7 may be greater than that of the first semiconductor region 6.

[0028] The thickness of the second semiconductor region 7 may be 5 μm or more and 50 μm or less. The thickness of the second semiconductor region 7 may have a value belonging to at least one of the ranges of 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or more and 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or more, and 45 μm or more and 50 μm or less.

[0029] The semiconductor device 1A includes a first surface 8, a second surface 9, and first to fourth connection surface portions 10A to 10D formed on the first main surface 3. The first surface 8, the second surface 9, and the first to fourth connection surface portions 10A to 10D define a mesa 11 on the first main surface 3. The first surface 8, the second surface 9, and the first to fourth connection surface portions 10A to 10D (i.e., the mesa 11) may be considered to be components of the chip 2 (first main surface 3).

[0030] The first surface portion 8 may be referred to as the "active surface," the second surface portion 9 may be referred to as the "outer surface," the first to fourth connecting surface portions 10A to 10D may be referred to as "connecting surfaces," and the mesa 11 may be referred to as the "active mesa."

[0031] The first surface portion 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The first surface portion 8 has a flat surface extending horizontally and is formed by a c-plane (Si-plane). In this embodiment, the first surface portion 8 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. The planar area of ​​the first surface portion 8 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0032] The second surface 9 is located closer to the periphery of the first main surface 3 than the first surface 8, and is recessed in the thickness direction of the chip 2 (toward the second main surface 4) from the height position of the first surface 8. The second surface 9 extends in a strip shape along the first surface 8 in a plan view, and is formed in a ring shape (specifically, a quadrangular ring) surrounding the first surface 8. The second surface 9 is continuous with the first to fourth side surfaces 5A to 5D.

[0033] The second surface 9 is formed substantially parallel to the first surface 8 and has a flat surface extending horizontally. In this embodiment, the second surface 9 is formed by the c-plane (Si-plane). The second surface 9 is formed in the second semiconductor region 7 at a distance from the first semiconductor region 6. In other words, the second surface 9 is recessed to a depth less than the thickness of the second semiconductor region 7, exposing the second semiconductor region 7.

[0034] The second surface portion 9 has a depth of 0.1 μm or more and 3 μm or less. The depth of the second surface portion 9 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the second surface portion 9 is preferably 1.5 μm or more and 2.5 μm or less.

[0035] The first to fourth connection surface portions 10A to 10D extend in the vertical direction Z and are connected to the first surface portion 8 and the second surface portion 9. The first connection surface portion 10A is located on the first side surface 5A side, the second connection surface portion 10B is located on the second side surface 5B side, the third connection surface portion 10C is located on the third side surface 5C side, and the fourth connection surface portion 10D is located on the fourth side surface 5D side. The first connection surface portion 10A and the second connection surface portion 10B extend in the first direction X and face the second direction Y. The third connection surface portion 10C and the fourth connection surface portion 10D extend in the second direction Y and face the first direction X.

[0036] The first to fourth connection surface portions 10A to 10D may extend substantially perpendicularly between the first surface portion 8 and the second surface portion 9, and define a quadrangular prism-shaped mesa 11. The first to fourth connection surface portions 10A to 10D may slope obliquely downward from the first surface portion 8 toward the second surface portion 9, and define a quadrangular pyramid-shaped mesa 11. The first to fourth connection surface portions 10A to 10D may be inclined at an angle greater than 90° and equal to or less than 135° with respect to the first surface portion 8.

[0037] In this way, the mesa 11 is defined in a protruding shape in the second semiconductor region 7 on the first main surface 3. The mesa 11 is formed only in the second semiconductor region 7, and is not formed in the first semiconductor region 6.

[0038] The semiconductor device 1A includes an active region 12 set in a chip 2. The active region 12 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 12 is set in an inner portion of the chip 2. Specifically, the active region 12 is set in a first surface portion 8.

[0039] The semiconductor device 1A includes a peripheral region 13 set outside the active region 12 in the chip 2. The peripheral region 13 is a region that does not include a device structure (transistor structure Tr). The peripheral region 13 is set in the peripheral portion of the chip 2. Specifically, the peripheral region 13 is set in the second surface 9. In other words, the peripheral region 13 is set in the region between the peripheral edge of the first surface 8 and the peripheral edge of the second surface 9 in a plan view.

[0040] The configuration within the active region 12 is shown below. The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures 15 formed on the first main surface 3 (first surface portion 8). The gate structures 15 may also be referred to as "trench gate structures," "trench structures," or the like. A gate potential is applied to the plurality of gate structures 15 as a control potential.

[0041] The plurality of gate structures 15 are formed on the first surface portion 8 at intervals inward from the periphery (first to fourth connection surface portions 10A to 10D) of the first surface portion 8. The plurality of gate structures 15 are arranged at intervals in the first direction X in plan view, and are each formed in a strip shape extending in the second direction Y. In other words, the plurality of gate structures 15 are arranged in stripes extending in the second direction Y in plan view.

[0042] The multiple gate structures 15 may be arranged at intervals of 0.25 μm to 3 μm. The intervals between the gate structures 15 may have a value belonging to at least one of the ranges of 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, 2.25 μm to 2.5 μm, 2.5 μm to 2.75 μm, and 2.75 μm to 3 μm. The intervals between the gate structures 15 are preferably 0.5 μm to 1.5 μm.

[0043] The plurality of gate structures 15 are located in the second semiconductor region 7. The plurality of gate structures 15 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of gate structures 15 are formed substantially perpendicular to the first main surface 3 (first surface portion 8).

[0044] Each of the plurality of gate structures 15 has, in a cross-sectional view, a first side wall 15 a on one side in the first direction X (the third side surface 5C side), a second side wall 15 b on the other side in the first direction X (the fourth side surface 5D side), and a bottom wall 15 c connecting the first side wall 15 a and the second side wall 15 b.

[0045] The first sidewall 15a and the second sidewall 15b are each formed by the a-plane ((11-20) plane) of the SiC single crystal. Of course, the first sidewall 15a and the second sidewall 15b may each be formed by the m-plane ((1-100) plane) of the SiC single crystal depending on the extending direction of the gate structure 15. The first sidewall 15a and the second sidewall 15b are formed approximately perpendicular to the first main surface 3.

[0046] The inclination angle (absolute value) of the first side wall 15a (second side wall 15b) relative to the vertical line may be 85° or more and 95° or less. The inclination angle of the first side wall 15a (second side wall 15b) may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle of the first side wall 15a (second side wall 15b) is preferably 87° or more and 93° or less.

[0047] The bottom wall 15c is formed by the c-plane (Si-plane) of the SiC single crystal. The bottom wall 15c preferably extends substantially flat in the horizontal direction. Of course, the bottom wall 15c may be curved in an arc shape toward the second main surface 4.

[0048] The gate structure 15 may have a width of 0.1 μm to 1.5 μm. The width of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, and 1.25 μm to 1.5 μm. The width of the gate structure 15 is preferably 0.25 μm to 0.75 μm.

[0049] The gate structure 15 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less. The depth of the gate structure 15 is preferably approximately equal to the depth of the second surface portion 9.

[0050] Each of the plurality of gate structures 15 includes a trench 16, an insulating film 17, and a buried electrode 18. The trench 16 is formed in the first main surface 3 (first surface portion 8) and defines the wall surfaces of the gate structure 15 (first sidewall 15 a, second sidewall 15 b, and bottom wall 15 c).

[0051] The insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 17 includes a silicon oxide film made of an oxide of the chip 2.

[0052] The insulating film 17 coats the wall surfaces of the trench 16 in a film-like manner. The insulating film 17 includes a first film portion, a second film portion, and a third film portion. The first film portion coats the first sidewall 15a in a film-like manner. The second film portion coats the second sidewall 15b in a film-like manner. The third film portion coats the bottom wall 15c in a film-like manner and is continuous with the first film portion and the second film portion.

[0053] The second film has a thickness approximately equal to that of the first film, and the third film has a thickness greater than both the first and second films. Of course, the thickness of the third film may be approximately equal to that of the first and second films.

[0054] The insulating film 17 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0055] The buried electrode 18 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried electrode 18 is buried in the trench 16 with the insulating film 17 sandwiched therebetween.

[0056] The buried electrode 18 has an electrode surface exposed from the trench 16. The electrode surface is located closer to the bottom wall 15c than the height of the first main surface 3. The electrode surface has a recess in its inner portion that tapers toward the bottom wall 15c. The bottom of the recess is preferably located closer to the first main surface 3 than the depth of the intermediate portion of the trench 16.

[0057] The semiconductor device 1A includes a plurality of p-type body regions 20 formed in a surface layer portion of the first main surface 3 (first surface portion 8). A source potential is applied to the plurality of body regions 20 as a second potential (low potential) different from a first potential (high potential). The body regions 20 may also be referred to as a "channel region" or a "base region", etc. The plurality of body regions 20 has a size of 1×10 １７ cm －３ 1x10 or more １９ cm －３ The p-type impurity concentration may be as follows:

[0058] The body regions 20 are formed in regions along the gate structures 15. Specifically, the body regions 20 are formed in regions between the gate structures 15, and extend in strips along the gate structures 15.

[0059] The following describes the configuration of one body region 20. In this embodiment, the body region 20 is formed in a layer shape extending in the first direction X in a cross-sectional view and is connected to one or both (both in this embodiment) of the adjacent gate structures 15. The body region 20 faces the buried electrodes 18 of the gate structures 15 with the insulating films 17 of the gate structures 15 sandwiched therebetween.

[0060] The body region 20 is formed at a distance from the depth position of the second surface 9 to a region on the first surface 8 side. The body region 20 is formed at a distance from the depth position of the bottom wall 15c of the gate structure 15 to the first main surface 3 side. The body region 20 has a bottom located on the bottom wall 15c side of the gate structure 15 with respect to the depth position of the middle part of the gate structure 15.

[0061] That is, the bottom of the body region 20 is located in a region between the bottom wall 15c of the gate structure 15 and the intermediate portion of the gate structure 15. In other words, the distance between the bottom of the body region 20 and the bottom wall 15c of the gate structure 15 is less than the thickness (depth) of the body region 20. The bottom of the body region 20 is located on the bottom wall 15c side of the gate structure 15 with respect to the bottom of the recess of the buried electrode 18. Of course, the bottom of the body region 20 may be located on the first main surface 3 side with respect to the depth position of the intermediate portion of the gate structure 15.

[0062] The body region 20 may have a thickness of 0.1 μm or more and 1 μm or less. The thickness of the body region 20 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, and 0.8 μm or more and 1 μm or less. The thickness of the body region 20 is preferably 0.3 μm or more and 0.7 μm or less.

[0063] The semiconductor device 1A includes a plurality of n-type source regions 21 formed in regions on the first main surface 3 side of the plurality of body regions 20. The plurality of source regions 21 have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The n-type impurity concentration of the plurality of source regions 21 is 1×10 １８cm －３ 1x10 or more ２１ cm －３ It may be the following:

[0064] The source regions 21 are formed in regions along the gate structures 15 in the surface layer portions of the body regions 20. Specifically, the source regions 21 are formed in regions between the gate structures 15, and extend in strips along the gate structures 15.

[0065] The configuration of one source region 21 will be described below. The source region 21 is formed at a distance from the bottom of the body region 20 toward the first main surface 3. In this embodiment, the source region 21 is formed in a layer extending in the first direction X in a cross-sectional view, and is connected to one or both (both in this embodiment) of a plurality of adjacent gate structures 15. The source region 21 faces the buried electrodes 18 of the plurality of gate structures 15, with the insulating films 17 of the plurality of gate structures 15 sandwiched therebetween.

[0066] The source region 21 has a bottom portion located on the bottom wall 15c side of the trench 16 relative to the height position of the electrode surface of the buried electrode 18, and a surface portion located on the first main surface 3 side relative to the height position of the electrode surface of the buried electrode 18. In other words, the source region 21 has a portion (bottom portion) facing the buried electrode 18 across the insulating film 17, and a portion (surface portion) not facing the buried electrode 18 across the insulating film 17.

[0067] The bottom of the source region 21 may be located closer to the first main surface 3 than the depth position of the bottom of the recess of the buried electrode 18. Of course, the bottom of the source region 21 may be located closer to the bottom of the body region 20 than the depth position of the bottom of the recess.

[0068] The semiconductor device 1A includes a plurality of p-type well regions 22 formed in the chip 2 (second semiconductor region 7). The plurality of well regions 22 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the plurality of well regions 22 may be lower than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the plurality of well regions 22 is 1×10 １６ cm－３ 1x10 or more ２０ cm －３ It may be the following:

[0069] The multiple well regions 22 are formed in the chip 2 (second semiconductor region 7) in regions along the bottom walls 15 c of the multiple gate structures 15 at intervals in the first direction X. In this embodiment, the multiple well regions 22 are formed in a one-to-one correspondence with the multiple gate structures 15.

[0070] The multiple well regions 22 are each formed in a strip shape extending along the corresponding gate structure 15 in a plan view, and face the corresponding buried electrode 18 across the corresponding insulating film 17. Of course, the multiple well regions 22 may be formed in a one-to-many correspondence with one gate structure 15. In this case, the multiple well regions 22 are formed at intervals in the second direction Y.

[0071] The following describes the configuration of one well region 22. In plan view, the well region 22 is formed to be wider than the gate structure 15. In cross-sectional view, the well region 22 is formed in a columnar shape extending in the thickness direction (vertical direction Z) of the second semiconductor region 7.

[0072] The well region 22 may have a depth that crosses an intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall 15 c of the gate structure 15. The well region 22 may be formed at a distance from the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall 15 c of the gate structure 15 toward the first main surface 3.

[0073] The well region 22 is formed at a distance from the bottom of the second semiconductor region 7 toward the first surface portion 8, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. Of course, the well region 22 may cross the bottom of the second semiconductor region 7 and have a bottom located within the first semiconductor region 6. The well region 22 forms a pn junction with the second semiconductor region 7.

[0074] In this embodiment, the well region 22 has a thickness (depth) greater than the thickness (depth) of the body region 20. The thickness of the well region 22 is the thickness of the well region 22 in the vertical direction Z with respect to the bottom wall 15c of the gate structure 15. In this embodiment, the thickness of the well region 22 is greater than the depth of the gate structure 15. Of course, the thickness of the well region 22 may be less than the depth of the gate structure 15. In this case, the thickness of the well region 22 may be less than the thickness of the body region 20.

[0075] The well region 22 has an upper end portion that is aligned with a corner portion of the bottom wall 15c of the gate structure 15. The well region 22 has, at the upper end portion, a first extension portion 22a on the first sidewall 15a side and a second extension portion 22b on the second sidewall 15b side (see FIG. 7).

[0076] The first extension 22a extends from a region directly below the gate structure 15 to the lower end of the first sidewall 15a. The first extension 22a is formed at a distance from the bottom of the body region 20 toward the bottom wall 15c of the gate structure 15. In this embodiment, the first extension 22a faces the buried electrode 18 in the horizontal direction, with the insulating film 17 interposed therebetween.

[0077] Of course, the first extension 22 a may be formed on the bottom wall 15 c side of the trench 16 with respect to the depth position of the lower end of the buried electrode 18, and may face only the insulating film 17 (third film portion) in the horizontal direction. The first extension 22 a is formed in a tapered shape toward the first main surface 3 (the bottom side of the body region 20) in a cross-sectional view.

[0078] The second extension portion 22b is drawn out from the region directly below the gate structure 15 to the lower end of the second sidewall 15b, and faces the first extension portion 22a across the gate structure 15. The second extension portion 22b is formed at a distance from the bottom of the body region 20 toward the bottom wall 15c of the gate structure 15. In this embodiment, the second extension portion 22b faces the buried electrode 18 in the horizontal direction, with the insulating film 17 therebetween.

[0079] Of course, the second extension portion 22b may be formed on the bottom wall 15c side of the trench 16 with respect to the depth position of the lower end of the buried electrode 18, and may face only the insulating film 17 (third film portion) in the horizontal direction. The second extension portion 22b is formed in a tapered shape toward the first main surface 3 (the bottom side of the body region 20) in a cross-sectional view.

[0080] The well region 22 has one or more (multiple in this embodiment) first bulge portions 22c. The accompanying drawings illustrate a well region 22 having four first bulge portions 22c. The number of first bulge portions 22c is adjusted appropriately by adjusting the process conditions. The multiple first bulge portions 22c are each formed by a portion of the well region 22 whose width in the horizontal direction (first direction X) gradually increases and decreases in the thickness direction, and are formed in multiple steps from the bottom wall 15c of the gate structure 15 toward the bottom of the second semiconductor region 7.

[0081] The multiple first bulging portions 22c extend in an arc shape (circular arc shape) from a region directly below the gate structure 15 to both sides of the gate structure 15. When the well region 22 has a single first bulging portion 22c, the single first bulging portion 22c may be formed in an intermediate portion of the well region 22 so as to extend in an arc shape (circular arc shape) to both sides of the gate structure 15.

[0082] The semiconductor device 1A includes a plurality of p-type high-concentration well regions 23 formed in each of the plurality of well regions 22. The plurality of high-concentration well regions 23 are regions in which the p-type impurity concentration of the well region 22 is increased, and have a p-type impurity concentration higher than the p-type impurity concentration of the well region 22. The high-concentration well regions 23 may be regarded as high-concentration portions of the well region 22. The p-type impurity concentration of the plurality of high-concentration well regions 23 is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ It may be the following:

[0083] The plurality of high-concentration well regions 23 are formed in a one-to-one correspondence with the plurality of well regions 22. The plurality of high-concentration well regions 23 are formed in regions along the bottom walls 15c of the corresponding gate structures 15. The plurality of high-concentration well regions 23 are each formed in a strip shape extending along the corresponding gate structure 15 (well region 22) in a plan view, and face the corresponding buried electrode 18 with the corresponding insulating film 17 interposed therebetween.

[0084] Of course, a plurality of high-concentration well regions 23 may be formed in a one-to-many correspondence with one well region 22. In this case, the plurality of high-concentration well regions 23 are formed at intervals in the second direction Y within one well region 22.

[0085] The following describes the configuration of one high-concentration well region 23. The high-concentration well region 23 is formed at a distance from the bottom of the well region 22 toward the bottom wall 15c of the gate structure 15. It is preferable that the high-concentration well region 23 has a bottom located closer to the bottom wall 15c of the gate structure 15 than the depth position of the middle part of the well region 22.

[0086] The bottom of the high-concentration well region 23 is defined by a concentration transition portion where the p-type impurity concentration gradually decreases toward the bottom side of the well region 22. Of course, the bottom of the high-concentration well region 23 may be located closer to the bottom side of the well region 22 than the depth position of the intermediate portion of the well region 22.

[0087] The high-concentration well region 23 is formed to be narrower than the well region 22. In this embodiment, the high-concentration well region 23 is formed to be narrower than the gate structure 15. Of course, the high-concentration well region 23 may be formed to be wider than the gate structure 15 and extend to both sides of the gate structure 15.

[0088] The high-concentration well region 23 has a thickness (depth) that is less than the depth of the gate structure 15. The thickness of the high-concentration well region 23 is the thickness of the high-concentration well region 23 in the vertical direction Z with the bottom wall 15c of the gate structure 15 as the reference. The thickness of the high-concentration well region 23 is less than the thickness of the body region 20. Of course, the thickness of the high-concentration well region 23 may be greater than the thickness of the body region 20 or greater than the depth of the gate structure 15.

[0089] The semiconductor device 1A includes a plurality of n-type high-concentration regions 24 formed in regions below the plurality of body regions 20 in the chip 2 (second semiconductor region 7). The plurality of high-concentration regions 24 are regions (low-resistance regions) in which the n-type impurity concentration of the second semiconductor region 7 is increased, and have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The plurality of high-concentration regions 24 may be considered as high-concentration portions of the second semiconductor region 7.

[0090] The n-type impurity concentration of the plurality of high concentration regions 24 is 1×10 １６ cm －３ 1x10 or more １９ cm －３ For example, the n-type impurity concentration of the multiple high-concentration regions 24 can be appropriately compared by comparing it with the n-type impurity concentration on the bottom side of the second semiconductor region 7. The high-concentration regions 24 may be referred to as "high-concentration drift regions."

[0091] The multiple high concentration regions 24 are formed in regions below the multiple body regions 20 and along the multiple gate structures 15. Specifically, the multiple high concentration regions 24 are formed in regions between the multiple gate structures 15 in thickness ranges between the bottom walls 15c of the multiple gate structures 15 and the bottoms of the multiple body regions 20. The multiple high concentration regions 24 extend in strip shapes along the multiple gate structures 15 in a plan view.

[0092] The configuration of one high-concentration region 24 will be described below. In this embodiment, the high-concentration region 24 is formed in a layer shape extending in the first direction X in a cross-sectional view, and is connected to one or both (both in this embodiment) of the adjacent gate structures 15. The high-concentration region 24 faces the buried electrodes 18 of the gate structures 15, with the insulating films 17 of the gate structures 15 sandwiched therebetween.

[0093] The heavily doped regions 24 face the source regions 21 in the thickness direction, sandwiching a part of the body region 20. In this embodiment, the heavily doped regions 24 face the source regions 21 in a one-to-one correspondence in the thickness direction.

[0094] The high concentration region 24 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The high concentration region 24 is preferably formed at a distance from the middle of the second semiconductor region 7 toward the first main surface 3.

[0095] In this embodiment, the high concentration region 24 has a bottom located closer to the first main surface 3 than the depth position of the bottom wall 15c of the gate structure 15. The bottom of the high concentration region 24 is defined by a concentration transition portion where the n-type impurity concentration gradually decreases toward the bottom side of the second semiconductor region 7. In other words, the high concentration region 24 is formed at a distance from the depth position of the bottom wall 15c of the gate structure 15 toward the first main surface 3.

[0096] The high-concentration region 24 is formed in a thickness range between the body region 20 and the well region 22, and separates the well region 22 from the body region 20. In other words, the high-concentration region 24 suppresses an increase in the p-type impurity concentration in the portion along the sidewalls (first sidewall 15 a and second sidewall 15 b) of the gate structure 15. The high-concentration region 24 has a thickness (depth) in the vertical direction Z that is less than the thickness (depth) of the body region 20.

[0097] The thickness of the high-concentration region 24 may be 0.1 μm or more and 0.5 μm or less. The thickness of the high-concentration region 24 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.15 μm or less, 0.15 μm or more and 0.2 μm or less, 0.2 μm or more and 0.25 μm or less, 0.25 μm or more and 0.3 μm or less, 0.3 μm or more and 0.35 μm or less, 0.35 μm or more and 0.4 μm or more and 0.4 μm or more and 0.45 μm or less, and 0.45 μm or more and 0.5 μm or less. The thickness of the high-concentration region 24 is preferably 0.1 μm or more and 0.3 μm or less.

[0098] For example, the distance in the vertical direction Z between the bottom wall 15c of the gate structure 15 and the bottom of the high-concentration region 24 may be 0 μm or more and 0.4 μm or less. The distance may have a value belonging to at least one of the ranges of 0 μm or more and 0.05 μm or less, 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.15 μm or less, 0.15 μm or more and 0.2 μm or less, 0.2 μm or more and 0.25 μm or less, 0.25 μm or more and 0.3 μm or more and 0.35 μm or less, and 0.35 μm or more and 0.4 μm or less. The distance is preferably 0.05 μm or more and 0.2 μm or less.

[0099] Of course, the bottom of the high concentration region 24 may be located closer to the bottom of the second semiconductor region 7 than the bottom wall 15c of the gate structure 15. In this case, the current density in the vicinity of the bottom wall 15c of the gate structure 15 is increased, and attention must be paid to electric field concentration in the vicinity of the bottom wall 15c of the gate structure 15 (particularly in the vicinity of the corners of the bottom wall 15c).

[0100] The multiple high-concentration regions 24 may have approximately the same n-type impurity concentration as each other, or may have different n-type impurity concentrations as each other. For example, with respect to one and the other high-concentration regions 24 located on both sides of one gate structure 15, the n-type impurity concentration of the other high-concentration region 24 may be different from the n-type impurity concentration of the one high-concentration region 24. In other words, the n-type impurity concentration of the other high-concentration region 24 may be higher than the n-type impurity concentration of the one high-concentration region 24, or may be lower than the n-type impurity concentration of the one high-concentration region 24.

[0101] The semiconductor device 1A includes a plurality of n-type medium concentration regions 25 formed in the chip 2 (second semiconductor region 7) in regions below the plurality of high concentration regions 24. The plurality of medium concentration regions 25 are regions (low resistance regions) in which the n-type impurity concentration of the second semiconductor region 7 is increased, and have an n-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7 and lower than the n-type impurity concentration of the high concentration regions 24. The plurality of medium concentration regions 25 may be regarded as high concentration portions of the second semiconductor region 7.

[0102] The n-type impurity concentration of the plurality of intermediate concentration regions 25 is 1×10 １５ cm －３ 1x10 or more １７ cm －３ For example, the n-type impurity concentrations of the plurality of medium concentration regions 25 can be appropriately compared by comparing them with the n-type impurity concentration on the bottom side of the second semiconductor region 7. The medium concentration regions 25 may be referred to as "medium concentration drift regions."

[0103] The plurality of medium concentration regions 25 are each formed in a thickness range between the bottom of the second semiconductor region 7 and the bottom of the plurality of high concentration regions 24 in the region between the plurality of gate structures 15. The plurality of medium concentration regions 25 each have a portion interposed in the region between the plurality of well regions 22. In this embodiment, the plurality of medium concentration regions 25 each have a portion interposed in the region between the plurality of gate structures 15.

[0104] The plurality of medium concentration regions 25 extend in a strip shape along the plurality of gate structures 15 in a plan view. In this embodiment, the plurality of medium concentration regions 25 are connected to one or both (both in this embodiment) of two adjacent well regions 22.

[0105] The following describes the configuration of one medium-concentration region 25. The medium-concentration region 25 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 with a part of the second semiconductor region 7 interposed therebetween.

[0106] The medium concentration region 25 has an upper end located above the depth position of the bottom wall 15c of the gate structure 15. The upper end of the medium concentration region 25 is located in a region between the multiple gate structures 15 and faces the gate structure 15 across the upper end (first extension portion 22a and second extension portion 22b) of the well region 22. The upper end of the medium concentration region 25 may have a portion connected to the gate structure 15.

[0107] The medium-concentration region 25 has a bottom located below the depth position of the bottom wall 15c of the gate structure 15. Specifically, the bottom of the medium-concentration region 25 is formed at a distance from the bottom of the well region 22 toward the first main surface 3. The bottom of the medium-concentration region 25 is preferably located closer to the bottom of the well region 22 than the bottom of the high-concentration well region 23.

[0108] The bottom of the medium concentration region 25 may be located closer to the bottom of the second semiconductor region 7 than the intermediate portion of the well region 22. Of course, the bottom of the medium concentration region 25 may be located closer to the bottom wall 15c of the gate structure 15 than the intermediate portion of the well region 22.

[0109] The semiconductor device 1A includes a plurality of channel regions 26 formed between the plurality of source regions 21 and the plurality of heavily doped regions 24 in the plurality of body regions 20. The inversion and non-inversion of the plurality of channel regions 26 is controlled by the gate structure 15. The plurality of channel regions 26 form current paths connecting the plurality of source regions 21 and the plurality of heavily doped regions 24 along the sidewalls (first sidewall 15 a and second sidewall 15 b) of the plurality of gate structures 15 in the plurality of body regions 20.

[0110] 4, 6 and 8, the semiconductor device 1A includes a plurality of p-type first contact regions 27 formed in regions along the plurality of gate structures 15 in the surface layer portion of the first main surface 3 (first surface portion 8).

[0111] The plurality of first contact regions 27 have a p-type impurity concentration higher than the p-type impurity concentration of the plurality of body regions 20. The p-type impurity concentration of the plurality of first contact regions 27 is higher than the p-type impurity concentration of the plurality of well regions 22. The p-type impurity concentration of the plurality of first contact regions 27 is 1×10 １７ cm －３ 1x10 or more １９ cm －３ It may be the following:

[0112] The multiple first contact regions 27 are formed in regions between the multiple gate structures 15. That is, the multiple first contact regions 27 are formed on both sides of the multiple gate structures 15. The multiple first contact regions 27 are arranged at intervals in the second direction Y along the multiple gate structures 15, and are each formed in a strip shape extending in the second direction Y. The multiple first contact regions 27 overlap the multiple body regions 20, and increase the p-type impurity concentration of the multiple body regions 20.

[0113] With respect to one and the other first contact regions 27 located on both sides of one gate structure 15, the other first contact region 27 faces the one first contact region 27 across the gate structure 15. In other words, the multiple first contact regions 27 are arranged in a matrix as a whole in a plan view.

[0114] The length and spacing of the multiple first contact regions 27 in the second direction Y are adjusted appropriately depending on the channel area to be achieved. The channel area corresponds to the total area of ​​the multiple source regions 21. The length of the first contact regions 27 in the second direction Y may be greater than the width of the gate structure 15 in the first direction X. Of course, the length of the first contact regions 27 may be less than the width of the gate structure 15.

[0115] A first ratio of the length of the first contact region 27 to the width of the gate structure 15 may be 0.5 or greater and 10 or less. The first ratio may have a value belonging to at least one of the ranges of 0.5 to 1, 1 to 2.5, 2.5 to 5, 5 to 7.5, and 7.5 to 10. The first ratio is preferably 1 to 5.

[0116] A second ratio of the spacing of the first contact regions 27 to the length of the first contact regions 27 may be greater than or equal to 1 and less than or equal to 50. The second ratio may have a value belonging to at least one of the ranges of greater than or equal to 1 and less than or equal to 5, greater than or equal to 10, greater than or equal to 10 and less than or equal to 15, greater than or equal to 15 and less than or equal to 20, greater than or equal to 25 and less than or equal to 25, greater than or equal to 30 and less than or equal to 30 and less than or equal to 35, greater than or equal to 35 and less than or equal to 40, greater than or equal to 40 and less than or equal to 45, and greater than or equal to 45 and less than or equal to 50.

[0117] The following describes the configuration of one first contact region 27. The first contact region 27 is formed in a layer extending horizontally along the first main surface 3, and is connected to one or both (in this embodiment, both) of the adjacent gate structures 15. The first contact region 27 faces the buried electrodes 18 of the gate structures 15, with the insulating films 17 of the gate structures 15 sandwiched therebetween.

[0118] The first contact region 27 has a thickness greater than that of the source region 21, and has a bottom located closer to the bottom of the second semiconductor region 7 than the bottom of the source region 21. The bottom of the first contact region 27 is located closer to the bottom of the body region 20 with respect to the depth position of the bottom of the recess of the buried electrode 18.

[0119] In this embodiment, the first contact region 27 has a thickness greater than the thickness of the body region 20, and has a bottom located closer to the bottom of the second semiconductor region 7 than the bottom of the body region 20. The bottom of the first contact region 27 is defined by a concentration transition portion where the p-type impurity concentration gradually decreases toward the bottom of the second semiconductor region 7.

[0120] The bottom of first contact region 27 may be located closer to first main surface 3 than the depth position of bottom wall 15c of gate structure 15. In this case, first contact region 27 may have a thickness less than the thickness of body region 20, and may have a bottom located closer to first main surface 3 than the bottom of body region 20. In other words, first contact region 27 may face high-concentration region 24 with part of body region 20 sandwiched therebetween.

[0121] In this embodiment, the bottom of the first contact region 27 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall 15c of the gate structure 15. In this embodiment, the first contact region 27 overlaps part or all of the high-concentration region 24 in a cross-sectional view. That is, the first contact region 27 replaces the n-type impurity concentration of part or all of the high-concentration region 24 with a p-type impurity concentration. Therefore, the p-type impurity concentration at the bottom (lower end) of the first contact region 27 is reduced by the amount of the n-type impurity concentration of the high-concentration region 24.

[0122] In this embodiment, the first contact region 27 has a bottom that traverses the bottom of the high-concentration region 24 and is located within the medium-concentration region 25. Therefore, the first contact region 27 also replaces the n-type impurity concentration of a portion of the medium-concentration region 25 with a p-type impurity concentration. The bottom of the first contact region 27 is preferably located closer to the first main surface 3 than the depth position of the intermediate portion of the well region 22.

[0123] The bottom of the first contact region 27 overlaps with the upper end portion (first extension portion 22 a and second extension portion 22 b) of the well region 22 in a region closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall 15 c of the gate structure 15. In this way, the first contact region 27 electrically connects the well region 22 to the body region 20.

[0124] In this embodiment, the first contact region 27 has a high concentration portion 27a on the first main surface 3 side and a low concentration portion 27b on the bottom side of the second semiconductor region 7. The high concentration portion 27a is formed at least closer to the first main surface 3 than the depth position of the bottom wall 15c of the gate structure 15, and forms the main body of the first contact region 27. The high concentration portion 27a extends horizontally along the first main surface 3 in a layered manner.

[0125] The low concentration portion 27b is formed closer to the bottom of the second semiconductor region 7 than the high concentration portion 27a, and forms the bottom (concentration transition portion) of the first contact region 27. The low concentration portion 27b is also a portion where the p-type impurity concentration is reduced by the n-type impurity concentration of the high concentration region 24. The low concentration portion 27b has a thickness less than that of the high concentration portion 27a, and extends horizontally in a layer shape along the high concentration portion 27a.

[0126] The low concentration portion 27b crosses in the thickness direction the depth position of the bottom wall 15c of the gate structure 15. That is, the low concentration portion 27b has a portion located closer to the first main surface 3 than the depth position of the bottom wall 15c of the gate structure 15, and a portion located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall 15c of the gate structure 15. The low concentration portion 27b overlaps the upper ends of the multiple well regions 22 and is electrically connected to the multiple well regions 22.

[0127] Of course, depending on the thickness of the high concentration portion 27a, the low concentration portion 27b may be located only on the first main surface 3 side relative to the depth position of the bottom wall 15c of the gate structure 15. Depending on the thickness of the high concentration portion 27a, the low concentration portion 27b may be located only on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom wall 15c of the gate structure 15.

[0128] The semiconductor device 1A includes a plurality of p-type second contact regions 28 formed in regions along the bottom walls 15 c of the plurality of gate structures 15 within the chip 2. The plurality of second contact regions 28 have a p-type impurity concentration higher than the p-type impurity concentration of the plurality of body regions 20. The p-type impurity concentration of the plurality of second contact regions 28 is higher than the p-type impurity concentration of the plurality of well regions 22.

[0129] The p-type impurity concentration of the plurality of second contact regions 28 is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The p-type impurity concentration of the plurality of second contact regions 28 is preferably approximately equal to the p-type impurity concentration of the plurality of first contact regions 27 .

[0130] The second contact regions 28 are formed in a one-to-many correspondence with the bottom walls 15c of the gate structures 15. The second contact regions 28 are respectively interposed in regions between the first contact regions 27 adjacent to each other in the first direction X in a plan view. In other words, the second contact regions 28 are positioned on the same straight line as the first contact regions 27 in the first direction X.

[0131] The second contact regions 28 are each formed in a strip shape extending along the corresponding gate structure 15 in a plan view, and face the buried electrode 18 across the insulating film 17. In the second direction Y, the lengths of the second contact regions 28 are approximately equal to the lengths of the first contact regions 27. In the second direction Y, the spacing between the second contact regions 28 is approximately equal to the spacing between the first contact regions 27.

[0132] The configuration of one second contact region 28 will be described below. The second contact region 28 is formed in one corresponding well region 22. The second contact region 28 overlaps with the high-concentration well region 23 and is electrically connected to the high-concentration well region 23 within the well region 22. The second contact region 28 is formed at a distance inward from the periphery of the well region 22.

[0133] The second contact regions 28 are formed at intervals from the bottom of the well region 22 toward the bottom wall 15c of the gate structure 15, and face the bottom of the second semiconductor region 7 across a part of the well region 22. The second contact regions 28 are each formed in a columnar shape extending in the thickness direction (vertical direction Z) of the second semiconductor region 7 in a cross-sectional view.

[0134] In this embodiment, the second contact region 28 has a bottom that is located closer to the bottom of the well region 22 than the thickness position of the intermediate portion of the well region 22. Of course, the bottom of the second contact region 28 may be located closer to the bottom wall 15c of the gate structure 15 than the thickness position of the intermediate portion of the well region 22.

[0135] In this embodiment, the bottom of the second contact region 28 is located closer to the bottom wall 15c of the gate structure 15 than the bottom of the moderately doped region 25. Of course, the bottom of the second contact region 28 may be located closer to the bottom of the second semiconductor region 7 than the bottom of the moderately doped region 25. In this case, the second contact region 28 may be formed to cross the bottom of the well region 22 and have its bottom located within the second semiconductor region 7.

[0136] The second contact region 28 has an upper end portion that is located along a corner portion of the bottom wall 15c of the gate structure 15. The second contact region 28 is electrically connected at its upper end portion to the plurality of first contact regions 27. In other words, the second contact region 28 electrically connects the well region 22 and the high-concentration well region 23 to the body region 20 via the plurality of first contact regions 27.

[0137] The second contact region 28 has a first extension 28a on the first sidewall 15a side and a second extension 28b on the second sidewall 15b side. The first extension 28a extends from the region directly below the gate structure 15 to the lower end of the first sidewall 15a. The first extension 28a faces the buried electrode 18 in the horizontal direction, with the insulating film 17 sandwiched therebetween.

[0138] The first extension portion 28 a is connected to the first contact region 27 in a region along the first sidewall 15 a. Specifically, the first extension portion 28 a is connected to both the high concentration portion 27 a and the low concentration portion 27 b of the first contact region 27.

[0139] The second extension portion 28b is drawn out from the region directly below the gate structure 15 to the lower end of the second sidewall 15b and faces the first extension portion 28a across the gate structure 15. The second extension portion 28b faces the buried electrode 18 in the horizontal direction, with the insulating film 17 therebetween. The second extension portion 28b is connected to the first contact region 27 in a region along the second sidewall 15b. Specifically, the second extension portion 28b is connected to both the high-concentration portion 27a and the low-concentration portion 27b of the first contact region 27.

[0140] The second contact region 28 has one or more (in this embodiment, multiple) second bulge portions 28c. The accompanying drawings illustrate an example of the second contact region 28 having two second bulge portions 28c. The number of second bulge portions 28c can be adjusted appropriately by adjusting the process conditions.

[0141] The multiple second bulge portions 28c are each formed by a portion of the second contact region 28 whose width in the horizontal direction (first direction X) gradually increases or decreases in the thickness direction, and are formed in multiple steps from the bottom wall 15c of the gate structure 15 toward the bottom of the second semiconductor region 7.

[0142] The multiple second bulging portions 28c extend in an arc shape (circular arc shape) from a region directly below the gate structure 15 to both sides of the gate structure 15. When the second contact region 28 has a single second bulging portion 28c, the single second bulging portion 28c may be formed in an intermediate portion of the second contact region 28 so as to extend in an arc shape (circular arc shape) to both sides of the gate structure 15.

[0143] The semiconductor device 1A includes a main surface insulating film 30 that covers the first main surface 3. The main surface insulating film 30 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connecting surface portions 10A to 10D. The main surface insulating film 30 is connected to the insulating films 17 of the plurality of gate structures 15 on the first surface portion 8, and exposes the buried electrodes 18 of the plurality of gate structures 15.

[0144] The main surface insulating film 30 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 30 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 30 include a silicon oxide film made of an oxide of the chip 2.

[0145] The semiconductor device 1A includes an insulating interlayer film 31 that covers the main surface insulating film 30. The interlayer film 31 may also be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 31 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connecting surface portions 10A to 10D with the main surface insulating film 30 in between. The interlayer film 31 covers the multiple gate structures 15 (buried electrodes 18) on the first surface portion 8.

[0146] In this embodiment, the interlayer film 31 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral portion of the second surface portion 9. Of course, the interlayer film 31 may be formed at a distance inward from the peripheral portion of the second surface portion 9, exposing the second semiconductor region 7 from the peripheral portion of the second surface portion 9. The interlayer film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the interlayer film 31 include a silicon oxide film.

[0147] The interlayer film 31 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer film 31 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0148] The semiconductor device 1A includes a plurality of source openings 32 formed in an interlayer film 31. The plurality of source openings 32 are formed in regions between the plurality of gate structures 15, respectively, and expose the plurality of source regions 21 and the plurality of first contact regions 27. The plurality of source openings 32 extend in a strip shape in the second direction Y along the plurality of gate structures 15.

[0149] Preferably, each of the source openings 32 has an opening end curved in an arc shape. The source openings 32 may be formed at intervals in the second direction Y in a region between adjacent gate structures 15. In this case, the source openings 32 may be formed in a quadrangular shape, a rectangular shape (strip shape), a circular shape, or the like in a plan view.

[0150] The semiconductor device 1A includes a plurality of gate openings 33 formed in an interlayer film 31 (see FIG. 3). In this embodiment, each of the plurality of gate openings 33 selectively exposes both ends of a corresponding one of the gate structures 15.

[0151] Specifically, each of the gate openings 33 exposes both ends of the buried electrode 18 of a corresponding gate structure 15. It is preferable that each of the gate openings 33 has an opening end that is curved in an arc, similar to the source opening 32. The gate openings 33 may be formed in a quadrangular, rectangular (strip-like), circular, or other shape in plan view.

[0152] The semiconductor device 1A includes a source electrode 35 disposed on the first main surface 3. The source electrode 35 is a terminal electrode to which a source potential is applied from the outside. The source electrode 35 may also be referred to as a "source pad electrode," a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like. The source electrode 35 is disposed on a portion of the interlayer film 31 that covers the first surface portion 8.

[0153] In this embodiment, the source electrode 35 has a first pad portion 35a, a second pad portion 35b, and a third pad portion 35c. The first pad portion 35a has a relatively large planar area and forms the main body of the source electrode 35. In this embodiment, the first pad portion 35a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first surface portion 8.

[0154] The second pad portion 35b has a planar area smaller than that of the first pad portion 35a, and extends in a strip shape (rectangular shape) from one end of the first pad portion 35a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 35c has a planar area smaller than that of the first pad portion 35a, and extends in a strip shape (rectangular shape) from the other end of the first pad portion 35a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 35b in the second direction Y.

[0155] The planar area of ​​the third pad portion 35c may be approximately equal to the planar area of ​​the second pad portion 35b. Of course, the planar area of ​​the third pad portion 35c may be larger than the planar area of ​​the second pad portion 35b, or may be smaller than the planar area of ​​the second pad portion 35b. Either or both of the second pad portion 35b and the third pad portion 35c may be used as a terminal portion for monitoring current.

[0156] The source electrode 35 does not necessarily have to have both the second pad portion 35b and the third pad portion 35c at the same time. The source electrode 35 may have only one of the second pad portion 35b and the third pad portion 35c. Of course, the source electrode 35 may be composed of only the first pad portion 35a and may not have both the second pad portion 35b and the third pad portion 35c.

[0157] The source electrode 35 extends from above the interlayer film 31 into the plurality of source openings 32 and is connected to the first main surface 3 (first surface portion 8) within the plurality of source openings 32. The source electrode 35 is electrically connected to the plurality of source regions 21 and the plurality of first contact regions 27 within the plurality of source openings 32.

[0158] In this embodiment, the source electrode 35 has a layered structure including a lower electrode film 36 and a main electrode film 37, which are layered in this order from the chip 2 side. In this embodiment, the lower electrode film 36 has a layered structure including a first electrode film 38 and a second electrode film 39. In this embodiment, the first electrode film 38 includes a Ti film, and the second electrode film 39 includes a TiN film. The lower electrode film 36 does not necessarily have to have a layered structure, and may have a single-layer structure consisting of either the first electrode film 38 (Ti film) or the second electrode film 39 (TiN film).

[0159] The first electrode film 38 has a thickness less than the thickness of the interlayer film 31. The thickness of the first electrode film 38 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 38 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0160] The second electrode film 39 has a thickness less than that of the interlayer film 31. The thickness of the second electrode film 39 is preferably greater than that of the first electrode film 38. The thickness of the second electrode film 39 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 39 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0161] The first electrode film 38 collectively covers the region of the interlayer film 31 where the plurality of source openings 32 are formed, and extends into the plurality of source openings 32 from above the interlayer film 31. The first electrode film 38 has a portion that covers the insulating main surface of the interlayer film 31 in a film-like manner, a portion that covers the wall surfaces of the plurality of source openings 32 in a film-like manner, and a portion that covers the first main surface 3 inside the plurality of source openings 32 in a film-like manner.

[0162] Specifically, the first electrode film 38 directly covers the insulating principal surface of the interlayer film 31 and faces the gate structure 15 across the interlayer film 31. The first electrode film 38 extends in an arc shape from above the insulating principal surface of the interlayer film 31 following the opening edge of the source opening 32 and covers the wall surface of the source opening 32 in a film-like manner. The first electrode film 38 covers the first principal surface 3 (first surface portion 8) in the source opening 32 in a film-like manner and is mechanically and electrically connected to the plurality of source regions 21 and the plurality of first contact regions 27 on the first principal surface 3.

[0163] The second electrode film 39 directly covers the first electrode film 38. The second electrode film 39 collectively covers the region of the interlayer film 31 where the plurality of source openings 32 are formed, sandwiching the first electrode film 38 therebetween, and extends from above the interlayer film 31 into the plurality of source openings 32.

[0164] The second electrode film 39 has a portion that coats the insulating main surface of the interlayer film 31 in a film-like manner, sandwiching the first electrode film 38 therebetween, a portion that coats the wall surfaces of the multiple source openings 32 in a film-like manner, sandwiching the first electrode film 38 therebetween, and a portion that coats the first main surface 3 in a film-like manner within the multiple source openings 32, sandwiching the first electrode film 38 therebetween.

[0165] Specifically, the second electrode film 39 covers the insulating main surface of the interlayer film 31 with the first electrode film 38 sandwiched therebetween, and faces the gate structure 15 with the interlayer film 31 and the first electrode film 38 sandwiched therebetween. The second electrode film 39 covers the opening end of the source opening 32 in an arc shape with the first electrode film 38 sandwiched therebetween, and coats the wall surface of the source opening 32 in a film-like manner with the first electrode film 38 sandwiched therebetween. The second electrode film 39 coats the first main surface 3 (first surface portion 8) in a film-like manner within the source opening 32 with the first electrode film 38 sandwiched therebetween, and is electrically connected to the plurality of source regions 21 and the plurality of first contact regions 27 via the first electrode film 38.

[0166] The main electrode film 37 contains a different conductive material from the lower electrode film 36 (the first electrode film 38 and the second electrode film 39). The main electrode film 37 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 37 has a thickness greater than the thickness (total thickness) of the lower electrode film 36. The thickness of the main electrode film 37 is preferably greater than the thickness of the interlayer film 31.

[0167] The thickness of the main electrode film 37 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 37 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0168] The main electrode film 37 directly covers the lower electrode film 36 (second electrode film 39). The main electrode film 37 backfills the source openings 32 and collectively covers the regions of the interlayer film 31 where the source openings 32 are formed. The main electrode film 37 has a portion that covers the insulating principal surface of the interlayer film 31 with the lower electrode film 36 in between, a portion that covers the wall surfaces of the source openings 32 with the lower electrode film 36 in between, and a portion that covers the first principal surface 3 with the lower electrode film 36 in between.

[0169] Specifically, the main electrode film 37 covers the insulating main surface of the interlayer film 31 with the lower electrode film 36 sandwiched therebetween, and faces the gate structure 15 with the interlayer film 31 and the lower electrode film 36 sandwiched therebetween. The main electrode film 37 covers the opening edge of the source opening 32 with the lower electrode film 36 sandwiched therebetween. The main electrode film 37 covers the first main surface 3 (first surface portion 8) within the source opening 32 with the lower electrode film 36 sandwiched therebetween, and is electrically connected to the plurality of source regions 21 and the plurality of first contact regions 27 via the lower electrode film 36.

[0170] The semiconductor device 1A includes a gate electrode 40 disposed on the first main surface 3. The gate electrode 40 is a terminal electrode to which a gate potential is applied from the outside. The gate electrode 40 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. Although not shown, the gate electrode 40, like the source electrode 35, includes a lower electrode film 36 and a main electrode film 37 stacked in this order from the chip 2 side.

[0171] The gate electrode 40 is disposed on a portion of the interlayer film 31 that covers the first surface 8, with a gap between it and the source electrode 35. In this embodiment, the gate electrode 40 is disposed in a region on the third side surface 5C side of the first pad 35a, and faces the first pad 35a in the first direction X. The gate electrode 40 is also interposed in a region between the second pad 35b and the third pad 35c, and faces both the second pad 35b and the third pad 35c in the second direction Y.

[0172] The gate electrode 40 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 40 has a planar area less than the planar area of ​​the source electrode 35. The gate electrode 40 has a planar area less than the planar area of ​​the first pad portion 35a. The gate electrode 40 may also have a planar area less than the planar area of ​​the second pad portion 35b (third pad portion 35c).

[0173] The gate electrode 40 partially faces the plurality of gate structures 15 across the interlayer film 31. Specifically, the gate electrode 40 is disposed inwardly from both ends of the plurality of gate structures 15 at intervals, and faces inner portions (intermediate portions in this embodiment) of the plurality of gate structures 15 across the interlayer film 31.

[0174] In this embodiment, the gate electrode 40 does not have any direct electrical connection to the plurality of gate structures 15. Of course, the gate electrode 40 may be electrically connected to the plurality of gate structures 15 via the plurality of gate openings 33. The portions of the plurality of gate structures 15 that are located under the gate electrode 40 may be removed. In this case, the gate electrode 40 may face the body region 20 with the main surface insulating film 30 and the interlayer film 31 sandwiched therebetween.

[0175] The semiconductor device 1A includes a gate wiring 41 extending from the gate electrode 40 onto the first main surface 3. The gate wiring 41 may also be referred to as a "gate finger" or "gate finger electrode." The gate wiring 41 transmits the gate potential applied to the gate electrode 40 to other regions. Although not shown, the gate wiring 41 includes a lower electrode film 36 and a main electrode film 37 stacked in this order from the chip 2 side, similar to the source electrode 35 (gate electrode 40).

[0176] The gate wiring 41 is drawn out from the gate electrode 40 onto a portion of the interlayer film 31 that covers the first surface 8. The gate wiring 41 is routed in a strip shape in the region between the periphery of the first surface 8 and the source electrode 35. The gate wiring 41 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view. In this embodiment, the gate wiring 41 is formed in a strip shape with ends, having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 35.

[0177] The gate wiring 41 intersects (specifically, is perpendicular to) the ends (both ends in this embodiment) of the plurality of gate structures 15. The gate wiring 41 enters the plurality of gate openings 33 from above the interlayer film 31, and is mechanically and electrically connected to the ends (both ends) of the plurality of gate structures 15 (buried electrodes 18) within the plurality of gate openings 33. As a result, the gate potential applied to the gate electrode 40 is applied to the plurality of gate structures 15 via the gate wiring 41.

[0178] The semiconductor device 1A includes a drain electrode 42 covering the second main surface 4. The drain electrode 42 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 42 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like.

[0179] The drain electrode 42 is electrically connected to the first semiconductor region 6. The drain electrode 42 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 42 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0180] The breakdown voltage that can be applied between the source electrode 35 and the drain electrode 42 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0181] As described above, the semiconductor device 1A includes the chip 2, the n-type second semiconductor region 7 (semiconductor layer), the trench gate structure 15, the p-type body region 20, and the n-type high-concentration region 24. The chip 2 has a first main surface 3. The second semiconductor region 7 is formed in a surface layer portion of the first main surface 3. The gate structure 15 is formed on the first main surface 3 and is located within the second semiconductor region 7.

[0182] The body region 20 is formed in a surface layer portion of the first main surface 3 in a region closer to the first main surface 3 than the depth position of the bottom wall 15c of the gate structure 15. The high concentration region 24 is formed in the chip 2 in a thickness range between the bottom wall 15c of the gate structure 15 and the bottom of the body region 20. The high concentration region 24 has an impurity concentration higher than the impurity concentration of the second semiconductor region 7.

[0183] This configuration allows the application of a semiconductor device 1A capable of improving electrical characteristics. For example, the resistance value near the gate structure 15 is reduced by the high-concentration region 24 formed below the body region 20. This configuration is effective in reducing on-resistance and JFET resistance. The high-concentration region 24 offsets undesired p-type impurities introduced laterally of the gate structure 15 due to process errors or the like. This suppresses fluctuations in the gate threshold voltage caused by the undesired p-type impurities.

[0184] The chip 2 preferably contains SiC. This configuration provides the semiconductor device 1A as a SiC semiconductor device capable of improving electrical characteristics. The high-concentration region 24 may have a bottom located closer to the first main surface 3 than the depth position of the bottom wall 15c of the gate structure 15. This configuration suppresses an increase in current density near the bottom wall 15c of the gate structure 15. This reduces the electric field with respect to the bottom wall 15c of the gate structure 15, suppressing a decrease in breakdown voltage due to electric field concentration.

[0185] The high concentration region 24 may be connected to the gate structure 15. With this configuration, undesired p-type impurities introduced laterally into the gate structure 15 are appropriately offset by the high concentration region 24. This appropriately suppresses fluctuations in the gate threshold voltage.

[0186] The high-concentration region 24 may have a thickness less than that of the body region 20. This configuration suppresses a reduction in the cross-sectional area of ​​the body region 20 due to the high-concentration region 24. Therefore, the function of the body region 20 is properly ensured in a configuration in which the high-concentration region 24 is present.

[0187] The gate structure 15 may have sidewalls (first sidewall 15a and second sidewall 15b) with an inclination angle of 87° to 93°. For example, when the gate structure 15 has sidewalls (first sidewall 15a and second sidewall 15b) inclined at an inclination angle of less than 87°, p-type impurities may be easily introduced laterally into the gate structure 15 through the sidewalls (first sidewall 15a and second sidewall 15b) of the trench 16 of the gate structure 15, depending on the process conditions.

[0188] Therefore, the gate structure 15 having sidewalls (first sidewall 15 a and second sidewall 15 b) substantially perpendicular to the first main surface 3 suppresses undesired introduction of p-type impurities through the sidewalls (first sidewall 15 a and second sidewall 15 b). Even if p-type impurities are introduced, they are offset by the high concentration region 24. Therefore, fluctuations in the gate threshold voltage are appropriately suppressed.

[0189] A plurality of gate structures 15 may be formed at intervals on the first main surface 3. In this case, the body region 20 may be formed in a region between the plurality of gate structures 15. Furthermore, the high concentration region 24 may be formed in the region between the plurality of gate structures 15 in a thickness range between the bottom walls 15c of the plurality of gate structures 15 and the bottom of the body region 20.

[0190] According to this configuration, the high concentration region 24 has the effect of reducing the resistance value in the region between the plurality of gate structures 15. In addition, the high concentration region 24 has the effect of suppressing fluctuations in the gate threshold voltage for the plurality of gate structures 15. In this configuration, the high concentration region 24 may be connected to the plurality of gate structures 15.

[0191] The semiconductor device 1A may include an n-type source region 21 (impurity region) and a channel region 26. In this case, the source region 21 may be formed in a region on the first main surface 3 side with respect to the body region 20 so as to be aligned with the gate structure 15.

[0192] The high-concentration region 24 may face the source region 21 across a part of the body region 20. The channel region 26 may be formed in the body region 20 between the source region 21 and the high-concentration region 24. The high-concentration region 24 may have an n-type impurity concentration lower than the n-type impurity concentration of the source region 21.

[0193] The semiconductor device 1A may include a p-type well region 22 formed in a region along the bottom wall 15c of the gate structure 15 within the chip 2. With this configuration, a depletion layer expands from the pn junction between the well region 22 and the second semiconductor region 7 when a reverse bias voltage is applied.

[0194] Furthermore, with this configuration, undesired p-type impurities that may be introduced laterally of the gate structure 15 during the process of forming the well region 22 are offset by the high concentration region 24. As a result, the well region 22 improves the breakdown voltage and simultaneously appropriately suppresses fluctuations in the gate threshold voltage.

[0195] The well region 22 may have an upper end portion along a corner portion of the bottom wall 15c of the gate structure 15. In this case, the high concentration region 24 may be formed in a thickness range between the bottom of the body region 20 and the upper end portion of the well region 22. With this configuration, fluctuations in the gate threshold voltage caused by the p-type impurity constituting the upper end portion of the well region 22 are appropriately suppressed by the high concentration region 24. The well region 22 may have a thickness greater than that of the body region 20.

[0196] The semiconductor device 1A may include a p-type high-concentration well region 23 formed in the well region 22 at a distance from the bottom of the well region 22 toward the bottom wall 15c of the gate structure 15. The high-concentration well region 23 may have a p-type impurity concentration higher than the p-type impurity concentration of the well region 22.

[0197] According to this configuration, the electrical response of well region 22 is improved by high-concentration well region 23. Furthermore, according to this configuration, fluctuations in the gate threshold voltage caused by p-type impurities constituting high-concentration well region 23 are suppressed by high-concentration region 24. High-concentration well region 23 may have a bottom located closer to bottom wall 15c of gate structure 15 than the depth position of the middle part of well region 22.

[0198] The semiconductor device 1A may include a p-type first contact region 27 formed in a region along the sidewall of the gate structure 15 within the chip 2. The first contact region 27 may have an impurity concentration higher than the impurity concentration of the body region 20. With this configuration, the first contact region 27 improves the electrical response of the body region 20.

[0199] The semiconductor device 1A may include a p-type first contact region 27 formed in a region along the bottom wall 15 c of the gate structure 15 within the chip 2. The first contact region 27 may have an impurity concentration higher than the impurity concentration of the body region 20. With this configuration, the first contact region 27 improves the electrical response of the body region 20.

[0200] The semiconductor device 1A may include a p-type second contact region 28 formed in a region along the bottom wall 15 c of the gate structure 15 within the chip 2. The second contact region 28 may have an impurity concentration higher than the impurity concentration of the body region 20.

[0201] The second contact region 28 may be electrically connected to the first contact region 27. According to this configuration, the electrical response of the second contact region 28 is improved by the first contact region 27. The second contact region 28 may electrically connect the well region 22 to the first contact region 27. According to this configuration, the electrical response of the well region 22 is improved by the second contact region 28.

[0202] The semiconductor device 1A may include an n-type medium concentration region 25 formed in a region below the high concentration region 24 within the chip 2. The medium concentration region 25 may have an impurity concentration higher than the impurity concentration of the second semiconductor region 7 and lower than the impurity concentration of the high concentration region 24.

[0203] According to this configuration, the resistance value in the region below the high-concentration region 24 is reduced by the medium-concentration region 25. Such a configuration is effective in reducing the on-resistance and JFET resistance. Since the medium-concentration region 25 has a lower impurity concentration than the high-concentration region 24, an increase in current density near the bottom wall 15c of the gate structure 15 is suppressed. Therefore, a decrease in breakdown voltage due to electric field concentration is suppressed.

[0204] In the semiconductor device 1A, the medium concentration region 25 may have a region located above the depth position of the bottom wall 15c of the gate structure 15, and a region located below the depth position of the bottom wall 15c of the gate structure 15.

[0205] 9 is a schematic diagram showing a wafer 45 used in the manufacture of the semiconductor device 1A. The wafer 45 is a base material for the chip 2 and includes a SiC single crystal. The wafer 45 is formed in a flat disk shape. Of course, the wafer 45 may also be formed in a flat rectangular parallelepiped shape. The wafer 45 has a first wafer main surface 46 on one side, a second wafer main surface 47 on the other side, and a wafer side surface 48 connecting the first wafer main surface 46 and the second wafer main surface 47.

[0206] The first wafer main surface 46 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 47 corresponds to the second main surface 4 of the chip 2. The first wafer main surface 46 and the second wafer main surface 47 are formed by the c-plane of the SiC single crystal. The first wafer main surface 46 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 47 is formed by the carbon surface of the SiC single crystal. The wafer 45 (the first wafer main surface 46 and the second wafer main surface 47) has the off-direction and off-angle described above.

[0207] The wafer 45 has a mark 49 on the wafer side surface 48 that indicates the crystal orientation of the SiC single crystal. The mark 49 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 46 in a plan view.

[0208] The mark 49 may include either or both of a first orientation flat extending in the a-axis direction and a second orientation flat extending in the m-axis direction. The mark 49 may include either or both of an orientation notch recessed in the a-axis direction and an orientation notch recessed in the m-axis direction.

[0209] The wafer 45 includes an n-type first semiconductor region 6 formed in a surface layer portion of the second wafer main surface 47. The first semiconductor region 6 is formed in a layer shape extending along the second wafer main surface 47, and is exposed from the second wafer main surface 47 and a wafer side surface 48. In this embodiment, the first semiconductor region 6 is made of an n-type semiconductor wafer (SiC wafer) containing SiC single crystal (semiconductor single crystal), and has the above-mentioned off direction and off angle.

[0210] The wafer 45 includes an n-type second semiconductor region 7 formed in a surface layer portion of the first wafer main surface 46. The second semiconductor region 7 is formed in a layer shape extending along the first wafer main surface 46, and is exposed from the first wafer main surface 46 and a wafer side surface 48.

[0211] The second semiconductor region 7 is made of an n-type epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and is stacked on the first semiconductor region 6. The second semiconductor region 7 has the off direction and off angle described above. That is, in this embodiment, the wafer 45 is made of an epitaxial wafer (a so-called epiwafer) having a stacked structure including a semiconductor wafer and an epitaxial layer.

[0212] The wafer 45 includes a plurality of device regions 50 and a plurality of cutting lines 51. For example, the plurality of device regions 50 and the plurality of cutting lines 51 are defined by alignment marks or the like formed on the first wafer main surface 46. Each device region 50 corresponds to a semiconductor device 1A. The plurality of device regions 50 are each set to have a rectangular shape in a plan view.

[0213] In this embodiment, the device regions 50 are set in a matrix along the first direction X and the second direction Y in a plan view. The device regions 50 are set at intervals inward from the periphery of the first wafer main surface 46 in a plan view. The cutting lines 51 are set in a grid pattern extending along the first direction X and the second direction Y to partition the device regions 50.

[0214] 10A to 10P are cross-sectional views showing an example of a method for manufacturing semiconductor device 1A. 10A to 10P show cross sections of a region corresponding to FIG. 5. First, referring to FIG. 10A, the aforementioned wafer 45 (see FIG. 9) is prepared.

[0215] 10B , a base medium concentration region 52 is formed in the wafer 45 (second semiconductor region 7) in a surface layer portion of the first wafer main surface 46. The base medium concentration region 52 is the base of the plurality of medium concentration regions 25. In the process of forming the base medium concentration region 52, n-type impurities are introduced into the second semiconductor region 7 by ion implantation.

[0216] The ion implantation method may be either or both of a channeling ion implantation method and a random ion implantation method. In the channeling ion implantation process, n-type impurities are introduced into the second semiconductor region 7 along an axial channel of the second semiconductor region 7. The axial channel is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the second semiconductor region 7, and is surrounded by atomic rows that constitute a crystal axis that extends in the stacking direction (crystal growth direction).

[0217] In other words, the axial channel is a region in which the atomic rows are sparse extending in the stacking direction and the atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a planar view. The axial channel is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values ​​of "a1", "a2", "a3", and "c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c).

[0218] In this embodiment, the axial channel is composed of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal. That is, the axial channel extends along the c-axis and has the off-direction and off-angle described above. In other words, the axial channel is inclined by the off-angle from the vertical axis toward the off-direction.

[0219] In the channeling ion implantation process, the n-type impurity is implanted deep into the second semiconductor region 7 while repeatedly undergoing small-angle scattering due to the channeling effect. That is, in the case of the channeling implantation method, the probability of the n-type impurity colliding with the atomic columns of the SiC single crystal is reduced. Therefore, the channeling ion implantation process is effective in forming a relatively deep medium-concentration base region 52.

[0220] On the other hand, in the random ion implantation process, n-type impurities are introduced in random directions into the second semiconductor region 7. The random directions are directions other than the axial channel of the second semiconductor region 7 (i.e., directions intersecting the axial channel).

[0221] For example, the random direction is the vertical direction Z. In the case of the random ion implantation process, the probability of collision of n-type impurities with atomic rows of the SiC single crystal is high, so the medium-concentration base region 52 is formed in a relatively shallow region. Therefore, the random ion implantation process is effective in forming a relatively shallow medium-concentration base region 52.

[0222] In the step of forming the medium-concentration base region 52, the medium-concentration base region 52 is formed so as to extend horizontally in a layer shape along the first wafer main surface 46. The medium-concentration base region 52 may be formed in the second semiconductor region 7 at a distance from the first wafer main surface 46 toward the bottom of the second semiconductor region 7. Of course, the medium-concentration base region 52 may also be exposed from the first wafer main surface 46. In consideration of the cancellation of p-type impurities and n-type impurities in later steps, it is preferable that the high-concentration base region 53 be formed at a distance from the first wafer main surface 46.

[0223] 10C, a high concentration base region 53 is formed in the wafer 45 (second semiconductor region 7) in the surface layer portion of the first wafer main surface 46. The high concentration base region 53 is the base of the multiple high concentration regions 24.

[0224] In the process of forming the high-concentration base region 53, n-type impurities are introduced into the second semiconductor region 7 by ion implantation. The ion implantation may be either or both of channeling ion implantation and random ion implantation. Since the n-type impurities are introduced into a region shallower than the intermediate-concentration base region 52, the ion implantation is preferably random ion implantation.

[0225] The n-type impurity is introduced into the first wafer main surface 46 and into the thickness range of the medium-concentration base region 52. This forms a high-concentration base region 53 that extends horizontally in a layer shape along the first wafer main surface 46. The high-concentration base region 53 may be formed in the second semiconductor region 7 at a distance from the first wafer main surface 46 toward the bottom of the second semiconductor region 7.

[0226] Of course, the high-concentration base region 53 may be exposed from the first wafer main surface 46. Considering the offset of p-type impurities and n-type impurities in later processes, the high-concentration base region 53 is preferably formed at a distance from the first wafer main surface 46 to the bottom side of the second semiconductor region 7.

[0227] 10D , a base body region 54 is formed in the wafer 45 (second semiconductor region 7) in a surface layer portion of the first wafer main surface 46. The high-concentration base region 53 is the base of the plurality of body regions 20. In the process of forming the base body region 54, p-type impurities are introduced into the second semiconductor region 7 by ion implantation.

[0228] The ion implantation method may be either one or both of channeling ion implantation and random ion implantation. Since the p-type impurity is introduced into a region shallower than the heavily doped base region 53, the ion implantation method is preferably random ion implantation. In this embodiment, the p-type impurity is introduced into the first wafer main surface 46 and the thickness range of the heavily doped base region 53. This forms the base body region 54, which extends horizontally in a layer-like manner along the first wafer main surface 46.

[0229] 10E , a base source region 55 is formed in the wafer 45 (base body region 54) in a surface layer portion of the first wafer main surface 46. The base source region 55 is the base of the multiple source regions 21. In the process of forming the base source region 55, n-type impurities are introduced into the base body region 54 by ion implantation.

[0230] The ion implantation method may be either or both of channeling ion implantation and random ion implantation. Since the n-type impurity is introduced into a region shallower than the base body region 54, the ion implantation method is preferably random ion implantation. This forms the base source region 55 extending horizontally in layers along the first wafer main surface 46.

[0231] The order of the steps of forming the base medium concentration region 52, the base high concentration region 53, the body region 20, and the base source region 55 may be arbitrarily changed and may be suitably reversed.

[0232] 10F , a mesa 11 and a plurality of trenches 16 are formed on the first wafer main surface 46. In this process, a first mask 56 having a predetermined layout is first formed on the first wafer main surface 46. The first mask 56 may be an inorganic mask (e.g., a silicon oxide film) or an organic mask (resist mask). The first mask 56 exposes the regions where the second surface 9 and the plurality of trenches 16 are to be formed and covers the other regions.

[0233] Next, unnecessary portions of the wafer 45 are removed by etching through the first mask 56. The etching may be either or both of wet etching and dry etching.

[0234] This forms first surface portion 8, second surface portion 9, first to fourth connection surface portions 10A to 10D, and a plurality of trenches 16. Furthermore, base high concentration region 53, base body region 54, and base source region 55 are separated by a plurality of trenches 16, and a plurality of body regions 20, a plurality of source regions 21, and a plurality of high concentration regions 24 are formed.

[0235] In this process, the plurality of trenches 16 are formed substantially perpendicular to the first wafer main surface 46. That is, the first sidewalls 15a and second sidewalls 15b of the plurality of trenches 16 have an inclination angle of 87° or more and 93° or less. The bottom walls 15c of the plurality of trenches 16 are formed flat along the horizontal direction. The trenches 16 having flat bottom walls 15c improve the accuracy of introducing impurities through the bottom walls 15c. The first mask 56 is removed after this process.

[0236] 10G , a plurality of well regions 22 are formed in the wafer 45 (second semiconductor region 7) in regions along the bottom walls 15 c of the plurality of trenches 16. In this step, a second mask 57 having a predetermined layout is first formed on the first wafer main surface 46. The second mask 57 may be an inorganic mask (for example, a silicon oxide film) or an organic mask (a resist mask).

[0237] The second mask 57 exposes regions where the multiple well regions 22 are to be formed (i.e., the multiple trenches 16) and covers the remaining regions. Next, p-type impurities are introduced into the second semiconductor region 7 through the bottom walls 15c of the multiple trenches 16 by ion implantation using the second mask 57. The ion implantation may be either or both of channeling ion implantation and random ion implantation.

[0238] The ion implantation is preferably a random ion implantation, and the p-type impurity is introduced into the wafer 45 at an implantation angle that is approximately perpendicular to the first wafer main surface 46. The ion implantation is preferably a perpendicular ion implantation, not an oblique ion implantation. This process suppresses the introduction of the p-type impurity into the wafer 45 through the first sidewall 15 a and the second sidewall 15 b of the trench 16.

[0239] In the random ion implantation step, the p-type impurity may be implanted in a single step at a target depth position in the second semiconductor region 7 (medium base concentration region 52). The p-type impurity may be implanted in multiple steps at different target depth positions in the second semiconductor region 7 (medium base concentration region 52) with different implantation energies. In either the single-step implantation step or the multistep implantation step, the p-type impurity implantation step may include a step of implanting the p-type impurity multiple times at the same target depth position in the second semiconductor region 7 (medium base concentration region 52).

[0240] The number of injection stages (number of target depth positions) of p-type impurities in the multistage injection process is adjusted appropriately depending on the thickness of the well region 22. The number of injection stages may be two, three, four, five, six, seven, eight, nine, or ten. The number of injection stages is preferably two or more and five or less. In the case of the multistage injection process, p-type impurities are injected into different target depth positions so that the injection sites of the p-type impurities overlap.

[0241] In the multistage implantation process, the dose (impurity concentration) of the p-type impurity into the second semiconductor region 7 (medium base concentration region 52) may be adjusted to increase as the implantation location becomes deeper. Also, in the multistage implantation process, the implantation energy of the p-type impurity into the second semiconductor region 7 (medium base concentration region 52) may be adjusted to increase as the implantation location becomes deeper.

[0242] As a result, a plurality of well regions 22 having a plurality of first bulging portions 22c that gradually increase and decrease in multiple steps along the thickness direction are formed in regions along the bottom walls 15c of the plurality of trenches 16. In addition, the base medium concentration region 52 is separated by the plurality of well regions 22, and a plurality of medium concentration regions 25 are formed.

[0243] 10H , a plurality of high-concentration well regions 23 are formed in the well regions 22 in regions along the bottom walls 15 c of the trenches 16. In this step, p-type impurities are introduced into the wafer 45 through the bottom walls 15 c of the trenches 16 by ion implantation using the second mask 57 described above. The ion implantation may be either or both of channeling ion implantation and random ion implantation.

[0244] The ion implantation is preferably a random ion implantation, and the p-type impurity is introduced into the wafer 45 at an implantation angle that is approximately perpendicular to the first wafer main surface 46. The ion implantation is preferably a perpendicular ion implantation, not an oblique ion implantation. This process suppresses the introduction of the p-type impurity into the second semiconductor region 7 through the first sidewall 15 a and the second sidewall 15 b of the trench 16.

[0245] As a result, a plurality of high-concentration well regions 23 are formed in each of the plurality of well regions 22. In this step, the second mask 57 used in the step of forming the well regions 22 is used. Of course, the plurality of high-concentration well regions 23 may be formed using a mask different from the second mask 57. The second mask 57 is then removed.

[0246] 10I, a plurality of first contact regions 27 and a plurality of second contact regions 28 are formed in the wafer 45 (second semiconductor region 7) in regions along the plurality of trenches 16. In this step, first, a third mask 58 having a predetermined layout is formed on the first wafer main surface 46.

[0247] The third mask 58 may be an inorganic mask (e.g., a silicon oxide film) or an organic mask (a resist mask). The third mask 58 exposes regions where the plurality of first contact regions 27 and the plurality of second contact regions 28 are to be formed, and covers the other regions. In other words, the third mask 58 selectively exposes a portion of the first wafer main surface 46 and a portion of the plurality of trenches 16.

[0248] Next, p-type impurities are introduced into the wafer 45 through the first wafer main surface 46 and the plurality of trenches 16 by ion implantation using the third mask 58. The ion implantation may be either or both of channeling ion implantation and random ion implantation.

[0249] In this embodiment, the ion implantation is a random ion implantation, which may be a vertical ion implantation, in which p-type impurities are introduced into wafer 45 at an implantation angle that is approximately perpendicular to first wafer main surface 46.

[0250] The random ion implantation method may be an oblique ion implantation method. In this case, p-type impurities are introduced into the wafer 45 at an implantation angle oblique to the first wafer main surface 46. The implantation angle may be greater than 0° and less than or equal to 10°. As a result, a plurality of first contact regions 27 and a plurality of second contact regions 28 are formed in the second semiconductor region 7. The third mask 58 is then removed.

[0251] 10J, a base insulating film 59 is formed on the first wafer main surface 46. The base insulating film 59 serves as a base for the plurality of insulating films 17 and the main surface insulating film 30. The base insulating film 59 is formed in the form of a film along the first wafer main surface 46 and the wall surfaces of the plurality of trenches 16. The base insulating film 59 may be formed by either or both of a CVD method and an oxidation method (for example, a thermal oxidation method).

[0252] 10K, a first base electrode film 60 is formed on the base insulating film 59. The first base electrode film 60 serves as a base for the multiple buried electrodes 18. The first base electrode film 60 has a portion that covers the first wafer main surface 46 with the base insulating film 59 in between, and a portion that is buried in the multiple trenches 16 with the base insulating film 59 in between. The base insulating film 59 may be formed by a CVD method.

[0253] 10L, unnecessary portions of the first base electrode film 60 are removed by etching until the base insulating film 59 is exposed. The etching may be either wet etching or dry etching, or both. As a result, a plurality of buried electrodes 18 are formed. Also, a plurality of gate structures 15 are formed.

[0254] 10M, an interlayer film 31 is formed on the first wafer main surface 46. The interlayer film 31 collectively covers the first surface 8, the second surface 9, the first to fourth connection surface portions 10A to 10D, and the plurality of gate structures 15. The interlayer film 31 may be formed by a CVD method.

[0255] 10N, a fourth mask 61 having a predetermined layout is formed on the interlayer film 31. The fourth mask 61 may be an organic mask (resist mask). The fourth mask 61 exposes regions where the plurality of source openings 32 and the plurality of gate openings 33 are to be formed, and covers the other regions.

[0256] Next, unnecessary portions of the interlayer film 31 are removed by etching through the fourth mask 61. The etching method may be either or both of wet etching and dry etching.

[0257] Next, unnecessary portions of the base insulating film 59 are removed by etching through the fourth mask 61. The etching method may be either or both of wet etching and dry etching.

[0258] The unnecessary portions of the base insulating film 59 may be removed simultaneously with the interlayer film 31. As a result, a plurality of source openings 32 and a plurality of gate openings 33 are formed in the interlayer film 31. The base insulating film 59 is also divided into the insulating film 17 and the main surface insulating film 30. The fourth mask 61 is then removed.

[0259] 10O , a second base electrode film 62 is formed on the interlayer film 31. The second base electrode film 62 is a base for the source electrode 35, the gate electrode 40, and the gate wiring 41. The second base electrode film 62 has a layered structure including the lower electrode film 36 and the main electrode film 37. The lower electrode film 36 has a layered structure including the first electrode film 38 and the second electrode film 39.

[0260] The first electrode film 38 may be formed by either or both of a sputtering method and a vapor deposition method, and is formed in a film shape along the first wafer main surface 46, the interlayer film 31, the wall surfaces of the plurality of source openings 32, and the wall surfaces of the plurality of gate openings 33.

[0261] The second electrode film 39 may be formed by either or both of a sputtering method and a vapor deposition method. The second electrode film 39 is laminated on the first electrode film 38 and is formed in a film shape along the first wafer main surface 46, the interlayer film 31, the wall surfaces of the plurality of source openings 32, and the wall surfaces of the plurality of gate openings 33.

[0262] The main electrode film 37 is formed on the lower electrode film 36. The main electrode film 37 may be formed by either or both of a sputtering method and a vapor deposition method. The main electrode film 37 is laminated on the lower electrode film 36 and is formed in a film shape along the first wafer main surface 46, the interlayer film 31, the wall surfaces of the plurality of source openings 32, and the wall surfaces of the plurality of gate openings 33.

[0263] Next, the second base electrode film 62 is divided into the source electrode 35, the gate electrode 40, and the gate wiring 41. In this process, a mask (not shown) having a predetermined layout is formed on the main electrode film 37. The mask (not shown) covers the regions where the source electrode 35, the gate electrode 40, and the gate wiring 41 are to be formed, and leaves the other regions exposed.

[0264] Next, unnecessary portions of the main electrode film 37 are removed by etching using a mask (not shown). The unnecessary portions of the main electrode film 37 are removed until the lower electrode film 36 is exposed. The etching method may be either wet etching or dry etching, or both. The mask (not shown) is removed after the etching process of the main electrode film 37.

[0265] Next, unnecessary portions of the lower electrode film 36 are removed by etching using the main electrode film 37 as a mask. The unnecessary portions of the lower electrode film 36 are removed until the interlayer film 31 is exposed. The step of removing the lower electrode film 36 includes a step of removing the second electrode film 39 by etching and a step of removing the first electrode film 38 by etching. The etching method may be either or both of wet etching and dry etching.

[0266] This forms the source electrode 35, the gate electrode 40, and the gate wiring 41. Of course, unnecessary portions of the lower electrode film 36 may be removed by etching using a mask (not shown) in the etching step of the main electrode film 37.

[0267] Next, referring to FIG. 10P, a drain electrode 42 is formed on the second wafer main surface 47. The drain electrode 42 may be formed by either or both of a sputtering method and a vapor deposition method. Thereafter, the wafer 45 is cut along the cutting lines 51 (see FIG. 9) to cut out a plurality of semiconductor devices 1A. Through the steps including those described above, the semiconductor device 1A is manufactured.

[0268] 11 is a cross-sectional view showing a main portion of a semiconductor device 1B according to the second embodiment. Referring to FIG. 11, the semiconductor device 1B includes a plurality of well regions 22 each formed as a column region forming a superjunction structure. Similar to the semiconductor device 1A, the plurality of well regions 22 are formed in a columnar shape extending in the thickness direction in cross-section.

[0269] The semiconductor device 1B includes a plurality of n-type intermediate drift regions 64 formed in the chip 2 (second semiconductor region 7). Each of the plurality of intermediate drift regions 64 is made up of a region partitioned between a plurality of well regions 22 in the second semiconductor region 7. That is, in this embodiment, the plurality of intermediate drift regions 64 each include a part of the second semiconductor region 7, a high concentration region 24, and an intermediate concentration region 25.

[0270] The intermediate drift regions 64 are arranged alternately with the well regions 22 in the first direction X, and are each formed in a strip shape extending in the second direction Y. That is, the intermediate drift regions 64 are formed in stripes extending in the second direction Y along the well regions 22. The extending direction of the intermediate drift regions 64 also coincides with the off-direction of the SiC single crystal. The intermediate drift regions 64 are formed in a columnar shape extending in the thickness direction in a cross-sectional view, and face the body regions 20 in a one-to-one correspondence.

[0271] The intermediate drift regions 64 form charge-balanced pn junctions together with the well regions 22 in the thickness range below the gate structures 15. The charge-balanced state means that, for adjacent well regions 22, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the intermediate drift regions 64.

[0272] As described above, semiconductor device 1B includes n-type intermediate drift region 64 defined between multiple well regions 22 in chip 2 (second semiconductor region 7). Intermediate drift region 64 is defined in the second semiconductor region 7 as a region between multiple well regions 22.

[0273] The intermediate drift region 64 forms a superjunction structure together with the plurality of well regions 22. This configuration provides a superjunction type semiconductor device 1B. When the chip 2 includes SiC, a superjunction type SiC semiconductor device is provided.

[0274] Fig. 12 is a plan view showing a main part of a semiconductor device 1C according to a third embodiment. Fig. 13 is a cross-sectional view taken along line XIII-XIII shown in Fig. 12. Fig. 14 is a cross-sectional view taken along line XIV-XIV shown in Fig. 12. Fig. 15 is an enlarged cross-sectional view of a region including a source structure 65 shown in Fig. 13. Fig. 16 is an enlarged cross-sectional view of a region including a source structure 65 shown in Fig. 14.

[0275] The semiconductor device 1C differs from the semiconductor device 1A in that it includes a plurality of trench-type (trench electrode-type) source structures 65 formed on the first main surface 3 (first surface portion 8). The source structures 65 may also be referred to as "trench source structures," "second trench structures," or the like. A source potential is applied to the plurality of source structures 65.

[0276] In the semiconductor device 1C, the layout of other components relative to the gate structure 15 is the same as in the semiconductor device 1A, so the following mainly describes the form of other components relative to the source structure 65. Description of other components relative to the gate structure 15 will be omitted unless otherwise specified. For the omitted descriptions, the descriptions given in the semiconductor device 1A apply.

[0277] 12 to 16, the source structures 65 are formed adjacent to the gate structures 15 in the first direction X. Specifically, the source structures 65 are respectively disposed in regions between adjacent gate structures 15 and face the gate structures 15 in the first direction X. The source structures 65 and the gate structures 15 are arranged alternately in the first direction X.

[0278] The source structures 65 may be formed on the first surface 8 at intervals inward from the periphery (first to fourth connection surface portions 10A to 10D) of the first surface 8. The source structures 65 may penetrate the periphery of the first surface 8 and be exposed from the first to fourth connection surface portions 10A to 10D.

[0279] The plurality of source structures 65 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of source structures 65 are formed substantially perpendicular to the first main surface 3 (first surface portion 8).

[0280] Each of the source structures 65 has, in a cross-sectional view, a first side wall 65 a on one side in the first direction X (the third side surface 5C side), a second side wall 65 b on the other side in the first direction X (the fourth side surface 5D side), and a bottom wall 65 c connecting the first side wall 65 a and the second side wall 65 b.

[0281] The first sidewall 65a and the second sidewall 65b are each formed by the a-plane ((11-20) plane) of the SiC single crystal. Of course, the first sidewall 65a and the second sidewall 65b may each be formed by the m-plane ((1-100) plane) of the SiC single crystal depending on the extending direction of the source structure 65. The first sidewall 65a and the second sidewall 65b are formed approximately perpendicular to the first main surface 3.

[0282] The inclination angle (absolute value) of the first side wall 65a (second side wall 65b) relative to the vertical line may be 85° or greater and 95° or less. The inclination angle of the first side wall 65a (second side wall 65b) may have a value belonging to at least one of the ranges of 85° or greater and 87.5° or less, 87.5° or greater and 90° or less, 90° or greater and 92.5° or less, and 92.5° or greater and 95° or less. The inclination angle of the first side wall 65a (second side wall 65b) is preferably 87° or greater and 93° or less.

[0283] The bottom wall 65c is formed by the c-plane (Si-plane) of the SiC single crystal. The bottom wall 65c preferably extends substantially flat in the horizontal direction. Of course, the bottom wall 65c may be curved in an arc shape toward the second main surface 4.

[0284] The width of the source structure 65 may be approximately equal to the width of the gate structure 15. The width of the source structure 65 may be greater than or less than the width of the gate structure 15. The source structure 65 may have a width of 0.1 μm or more and 1.5 μm or less.

[0285] The width of the source structure 65 may be in at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, and 1.25 μm to 1.5 μm. The width of the source structure 65 is preferably 0.25 μm to 0.75 μm.

[0286] The depth of the source structure 65 may be approximately equal to the depth of the second surface portion 9. The depth of the source structure 65 may be greater than the depth of the second surface portion 9 or less than the depth of the second surface portion 9. The depth of the source structure 65 may be approximately equal to the depth of the gate structure 15. The depth of the source structure 65 may be greater than the depth of the gate structure 15 or less than the depth of the gate structure 15.

[0287] The depth of the source structure 65 may be 0.1 μm or more and 3 μm or less. The depth of the source structure 65 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the source structure 65 is preferably 0.5 μm or more and 1.5 μm or less.

[0288] Each of the multiple source structures 65 includes a second trench 66, a second insulating film 67, and a second buried electrode 68. The second trench 66 is formed in the first main surface 3, and defines the wall surfaces of the source structure 65 (a first sidewall 65 a, a second sidewall 65 b, and a bottom wall 65 c).

[0289] The second insulating film 67 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating film 67 preferably includes the same type of insulating material as the insulating film 17. In this embodiment, the second insulating film 67 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 67 includes a silicon oxide film made of an oxide of the chip 2.

[0290] The second insulating film 67 coats the wall surfaces of the second trench 66 in a film-like manner. The second insulating film 67 coats the first sidewall 65a and the second sidewall 65b at a distance from the first main surface 3 toward the bottom wall 65c. In other words, the second insulating film 67 exposes a part of the first sidewall 65a and a part of the second sidewall 65b from the opening end of the second trench 66.

[0291] The second insulating film 67 includes a first film portion, a second film portion, and a third film portion. The first film portion coats the first sidewall 65a of the second trench 66 in a film-like manner. The second film portion coats the second sidewall 65b of the second trench 66 in a film-like manner. The third film portion coats the bottom wall 65c of the second trench 66 in a film-like manner and is continuous with the first film portion and the second film portion.

[0292] The second membrane has a thickness approximately equal to the thickness of the first membrane. The third membrane has a thickness greater than the thickness of the first membrane and the thickness of the second membrane. The thickness of the third membrane may be approximately equal to the thickness of the first membrane and the thickness of the second membrane.

[0293] The first film portion of the second insulating film 67 may have a thickness approximately equal to that of the first film portion of the insulating film 17. The second film portion of the second insulating film 67 may have a thickness approximately equal to that of the second film portion of the insulating film 17. The third film portion of the second insulating film 67 may have a thickness approximately equal to that of the third film portion of the insulating film 17.

[0294] The second insulating film 67 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0295] The second buried electrode 68 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The second buried electrode 68 is buried in the second trench 66 with a second insulating film 67 sandwiched therebetween. The second buried electrode 68 has an electrode surface exposed from the second trench 66.

[0296] The electrode surface of the second buried electrode 68 is located closer to the bottom wall 65c of the second trench 66 than the height position of the first main surface 3. The electrode surface of the second buried electrode 68 may be located closer to the bottom wall 65c than the height position of the electrode surface of the buried electrode 18.

[0297] Of course, the height position of the electrode surface of the second buried electrode 68 may be substantially equal to the height position of the electrode surface of the buried electrode 18. The electrode surface of the second buried electrode 68 has a recess in its inner part that is tapered toward the bottom wall 15c. The bottom of the recess is preferably located closer to the first main surface 3 than the depth position of the intermediate part of the second trench 66.

[0298] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of body regions 20 formed in regions along the plurality of gate structures 15 in the surface layer portion of the first main surface 3 (first surface portion 8). In this embodiment, the plurality of body regions 20 are formed in regions between the plurality of gate structures 15 and the plurality of source structures 65, respectively, and extend in strip shapes along the plurality of gate structures 15 and the plurality of source structures 65, respectively.

[0299] The following describes the configuration of one body region 20. In this embodiment, the body region 20 is formed in a layer shape extending in the first direction X in a cross-sectional view, and is connected to the gate structure 15 and the source structure 65. The body region 20 faces the second buried electrode 68 on the source structure 65 side, with a second insulating film 67 sandwiched therebetween.

[0300] The body region 20 is formed in a region on the first main surface 3 side with respect to the depth position of the bottom wall 65c of the source structure 65. The body region 20 has a bottom portion located on the bottom wall 65c side of the source structure 65 with respect to the depth position of the middle part of the source structure 65.

[0301] That is, the bottom of the body region 20 is located in a region between the bottom wall 65c of the source structure 65 and the middle part of the source structure 65. In other words, the distance between the bottom of the body region 20 and the bottom wall 65c of the source structure 65 is less than the thickness (depth) of the body region 20. The bottom of the body region 20 is located on the bottom wall 65c side with respect to the bottom of the recess of the second buried electrode 68.

[0302] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of source regions 21 formed in regions on the first main surface 3 side of the plurality of body regions 20. In this embodiment, the plurality of source regions 21 are formed in regions between the plurality of gate structures 15 and the plurality of source structures 65, respectively, and extend in strip shapes along the plurality of gate structures 15 and the plurality of source structures 65, respectively.

[0303] The configuration of one source region 21 will be described below. The source region 21 is formed at an interval from the bottom of the body region 20 toward the first main surface 3. In this embodiment, the source region 21 is formed in a layer shape extending in the first direction X in a cross-sectional view, and is connected to the gate structure 15 and the source structure 65. The multiple source regions 21 face the second buried electrode 68 on the source structure 65 side, with the second insulating film 67 sandwiched therebetween.

[0304] The source region 21 has a bottom portion located closer to the bottom wall 65 c of the second trench 66 than the height position of the electrode surface of the second buried electrode 68, and a surface portion located closer to the first main surface 3 than the height position of the electrode surface of the second buried electrode 68. In other words, the source region 21 has a portion (bottom portion) facing the second buried electrode 68 across the second insulating film 67, and a portion (surface portion) not facing the second buried electrode 68 across the second insulating film 67.

[0305] The bottom of the source region 21 is preferably located closer to the bottom of the body region 20 than the depth of the bottom of the recess of the second buried electrode 68. Of course, the bottom of the source region 21 may be located closer to the first main surface 3 than the depth of the bottom of the recess. A surface portion of the source region 21 is exposed from the upper end of the first sidewall 65a or the upper end of the second sidewall 65b of the source structure 65.

[0306] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of well regions 22 formed in the chip 2 (second semiconductor region 7). The description of the plurality of well regions 22 is omitted here because it is similar to the case of the semiconductor device 1A.

[0307] The semiconductor device 1C includes a plurality of p-type second well regions 72 formed in the chip 2 (second semiconductor region 7) in regions along the bottom walls 65 c of the plurality of source structures 65. The plurality of second well regions 72 are formed in the same manner as the plurality of well regions 22, and have p-type impurity concentrations approximately equal to the p-type impurity concentrations of the plurality of well regions 22.

[0308] The second well regions 72 are formed in regions along the bottom walls 65 c of the source structures 65 at intervals in the first direction X from the well regions 22. The second well regions 72 are formed in one-to-one correspondence with the source structures 65, respectively.

[0309] The second well regions 72 are each formed in a strip shape extending along the source structures 65 in a plan view, and face the corresponding second buried electrodes 68 across the corresponding second insulating films 67. Of course, the second well regions 72 may be formed in a one-to-many correspondence with one source structure 65. In this case, the second well regions 72 are formed at intervals in the second direction Y.

[0310] The following describes the configuration of one second well region 72. In plan view, each second well region 72 is formed to be wider than the source structure 65. In cross-sectional view, each second well region 72 is formed in a columnar shape extending in the thickness direction (vertical direction Z) of the second semiconductor region 7.

[0311] The second well region 72 is formed at a distance from the bottom of the second semiconductor region 7 toward the first surface portion 8, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. Of course, the second well region 72 may be formed to cross the bottom of the second semiconductor region 7 and have its bottom located within the first semiconductor region 6. The second well region 72 forms a pn junction with the second semiconductor region 7.

[0312] In this embodiment, the second well region 72 has a thickness (depth) greater than the thickness (depth) of the body region 20. The thickness of the second well region 72 is the thickness of the second well region 72 in the vertical direction Z with respect to the bottom wall 65c of the source structure 65. In this embodiment, the thickness of the second well region 72 is greater than the depth of the source structure 65.

[0313] Of course, the thickness of the second well region 72 may be less than the depth of the source structure 65. In this case, the thickness of the second well region 72 may be less than the thickness of the body region 20. The thickness of the second well region 72 is preferably approximately equal to the thickness of the well region 22. Of course, the thickness of the second well region 72 may be greater than the thickness of the well region 22 or less than the thickness of the well region 22.

[0314] The second well region 72 has an upper end portion that fits along the corner of the bottom wall 65c of the source structure 65. The second well region 72 has, at its upper end portion, a first extension portion 72a on the first sidewall 65a side and a second extension portion 72b on the second sidewall 65b side (see FIG. 15 ).

[0315] The first extension 72a extends from a region directly below the source structure 65 to the lower end of the first sidewall 65a. The first extension 72a is formed at a distance from the bottom of the body region 20 toward the bottom wall 65c of the source structure 65. In this embodiment, the first extension 72a faces the second buried electrode 68 in the horizontal direction, with the second insulating film 67 interposed therebetween.

[0316] Of course, the first extension 72a may be formed on the bottom wall 65c side of the second trench 66 with respect to the depth position of the lower end of the second buried electrode 68, and may face only the second insulating film 67 (third film portion) in the horizontal direction. The first extension 72a is formed in a tapered shape toward the first main surface 3 (the bottom side of the body region 20) in a cross-sectional view.

[0317] The second extension portion 72b is drawn out from the region directly below the source structure 65 to the lower end of the second sidewall 65b, and faces the first extension portion 72a across the source structure 65. The second extension portion 72b is formed at a distance from the bottom of the body region 20 toward the bottom wall 65c of the source structure 65. In this embodiment, the second extension portion 72b faces the second buried electrode 68 in the horizontal direction, with the second insulating film 67 therebetween.

[0318] Of course, the second extension portion 72b may be formed on the bottom wall 65c side of the second trench 66 with respect to the depth position of the lower end portion of the second buried electrode 68, and may face only the second insulating film 67 (third film portion) in the horizontal direction. The second extension portion 72b is formed in a tapered shape toward the first main surface 3 (the bottom side of the body region 20) in a cross-sectional view.

[0319] The second well region 72 has one or more (multiple in this embodiment) third bulge portions 72c. The attached drawings illustrate an example of a second well region 72 having four third bulge portions 72c. The multiple third bulge portions 72c are each formed by a portion of the second well region 72 whose width in the horizontal direction (first direction X) gradually increases or decreases in the thickness direction, and are formed in multiple steps from the bottom wall 65c of the source structure 65 toward the bottom of the second semiconductor region 7.

[0320] The multiple third bulge portions 72c extend in an arc shape (circular arc shape) from a region directly below the source structure 65 to both sides of the source structure 65. When the second well region 72 has a single third bulge portion 72c, the single third bulge portion 72c may be formed in an intermediate portion of the second well region 72 so as to extend in an arc shape (circular arc shape) to both sides of the source structure 65.

[0321] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of high-concentration well regions 23 formed in each of the plurality of well regions 22. The description of the plurality of high-concentration well regions 23 is omitted here, as it is similar to that of the semiconductor device 1A.

[0322] The semiconductor device 1C includes a plurality of p-type second high-concentration well regions 73 formed in each of the second well regions 72. The second high-concentration well regions 73 are formed in the same manner as the high-concentration well regions 23, and have a p-type impurity concentration substantially equal to the p-type impurity concentration of the high-concentration well regions 23.

[0323] The plurality of second high-concentration well regions 73 are formed in a one-to-one correspondence with the corresponding second well regions 72. The plurality of second high-concentration well regions 73 are formed in regions along the bottom walls 65 c of the corresponding source structures 65. The plurality of second high-concentration well regions 73 are formed in strip shapes extending along the corresponding source structures 65 (second well regions 72) in plan view, and face the corresponding second buried electrodes 68 with the corresponding second insulating films 67 interposed therebetween.

[0324] Of course, a plurality of second high-concentration well regions 73 may be formed in a one-to-many correspondence with one second well region 72. In this case, the plurality of second high-concentration well regions 73 are formed at intervals in the second direction Y within one second well region 72.

[0325] The following describes the configuration of one second high-concentration well region 73. The second high-concentration well region 73 is formed at a distance from the bottom of the second well region 72 toward the bottom wall 65c of the source structure 65. The second high-concentration well region 73 preferably has a bottom that is located closer to the bottom wall 65c of the source structure 65 than the depth position of the middle part of the second well region 72.

[0326] The bottom of the second high-concentration well region 73 is defined by a concentration transition portion where the p-type impurity concentration gradually decreases toward the bottom of the second well region 72. Of course, the bottom of the second high-concentration well region 73 may be located closer to the bottom of the second well region 72 than the depth position of the middle portion of the second well region 72. In this embodiment, the bottom of the second high-concentration well region 73 is formed at a depth position substantially equal to the depth position of the bottom of the high-concentration well region 23.

[0327] The second high-concentration well region 73 is formed to be narrower than the second well region 72. In this embodiment, the second high-concentration well region 73 is formed to be narrower than the source structure 65. Of course, the second high-concentration well region 73 may be formed to be wider than the source structure 65 and extend to both sides of the source structure 65.

[0328] In this embodiment, the width of the second high-concentration well region 73 is approximately equal to the width of the high-concentration well region 23. Of course, the width of the second high-concentration well region 73 may be larger or smaller than the width of the high-concentration well region 23.

[0329] The second high-concentration well region 73 has a thickness (depth) that is less than the depth of the source structure 65. The thickness of the second high-concentration well region 73 is the thickness of the second high-concentration well region 73 in the vertical direction Z with the bottom wall 65c of the source structure 65 as the reference. The thickness of the second high-concentration well region 73 is less than the thickness of the body region 20. Of course, the thickness of the second high-concentration well region 73 may be greater than the thickness of the body region 20 or greater than the depth of the source structure 65.

[0330] It is preferable that the thickness of the second high-concentration well region 73 is approximately equal to the thickness of the high-concentration well region 23. Of course, the thickness of the second well region 72 may be greater than the thickness of the high-concentration well region 23 or may be less than the thickness of the high-concentration well region 23.

[0331] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of high-concentration regions 24 formed in the chip 2 (second semiconductor region 7) in regions below the plurality of body regions 20. In this embodiment, the plurality of high-concentration regions 24 are formed in regions between the plurality of gate structures 15 and the plurality of source structures 65.

[0332] The plurality of heavily doped regions 24 are formed in the thickness range between the bottom walls 65c of the plurality of source structures 65 and the bottoms of the plurality of body regions 20 for the plurality of source structures 65. The plurality of heavily doped regions 24 extend in a strip shape along the plurality of gate structures 15 and the plurality of source structures 65 in a plan view.

[0333] The following describes the configuration of one high-concentration region 24. In this embodiment, the high-concentration region 24 is formed in a layer shape extending in the first direction X in a cross-sectional view, and is connected to both the gate structure 15 and the source structure 65. The high-concentration region 24 faces the second buried electrode 68 on the source structure 65 side, with the second insulating film 67 sandwiched therebetween.

[0334] The heavily doped region 24 has a bottom located closer to the first main surface 3 than the depth position of the bottom wall 65c of the source structure 65. In other words, the heavily doped region 24 is formed at a distance from the depth position of the bottom wall 65c of the source structure 65 toward the first main surface 3.

[0335] The high-concentration region 24 is formed in a thickness range between the body region 20 and the second well region 72, and separates the second well region 72 from the body region 20. In other words, the high-concentration region 24 suppresses an increase in the p-type impurity concentration in the portion along the sidewall (first sidewall 65 a or second sidewall 65 b) of the source structure 65. Of course, the bottom of the high-concentration region 24 may be located closer to the bottom of the second semiconductor region 7 than the bottom wall 65 c of the source structure 65.

[0336] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of n-type medium concentration regions 25 formed in the chip 2 (second semiconductor region 7) in regions below the plurality of high concentration regions 24. In this embodiment, the plurality of medium concentration regions 25 are formed in regions between the plurality of gate structures 15 and the plurality of source structures 65.

[0337] The plurality of medium concentration regions 25 are each formed in a thickness range between the bottom of the second semiconductor region 7 and the bottom of the plurality of high concentration regions 24. Each of the plurality of medium concentration regions 25 has a portion interposed in a region between the plurality of well regions 22 and the plurality of second well regions 72. In this embodiment, each of the plurality of medium concentration regions 25 has a portion interposed in a region between the plurality of gate structures 15 and the plurality of source structures 65.

[0338] The plurality of medium concentration regions 25 extend in a strip shape along the plurality of gate structures 15 and the plurality of source structures 65 in a plan view. The plurality of medium concentration regions 25 are connected to either one or both (in this embodiment, both) of the adjacent well region 22 and second well region 72.

[0339] The following describes the configuration of one medium-concentration region 25. The medium-concentration region 25 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 with a part of the second semiconductor region 7 interposed therebetween.

[0340] The medium concentration region 25 has an upper end located above the depth position of the bottom wall 65c of the source structure 65. The upper end of the medium concentration region 25 is located in a region between the gate structure 15 and the source structure 65. The upper end of the medium concentration region 25 faces the source structure 65 across the upper end (first extension portion 72a or second extension portion 72b) of the second well region 72. The upper end of the medium concentration region 25 may have a portion connected to the source structure 65.

[0341] The medium-concentration region 25 has a bottom located below the depth position of the bottom wall 65c of the source structure 65. Specifically, the bottom of the medium-concentration region 25 is formed at a distance from the bottom of the second well region 72 toward the first main surface 3. The bottom of the medium-concentration region 25 is preferably located closer to the bottom of the second well region 72 than the bottom of the second high-concentration well region 73.

[0342] The bottom of the medium concentration region 25 may be located closer to the bottom of the second semiconductor region 7 than the intermediate portion of the second well region 72. Of course, the bottom of the medium concentration region 25 may be located closer to the bottom wall 65c of the source structure 65 than the intermediate portion of the second well region 72.

[0343] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of channel regions 26 formed between a plurality of source regions 21 and a plurality of high-concentration regions 24 in the body region 20. The description of the plurality of channel regions 26 is omitted here because it is similar to that of the semiconductor device 1A.

[0344] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of first contact regions 27 formed in regions along the plurality of gate structures 15 in the surface layer portion of the first main surface 3. In this embodiment, the plurality of first contact regions 27 are formed in the body region 20 in regions between the plurality of gate structures 15 and the plurality of source structures 65.

[0345] That is, the multiple first contact regions 27 are formed on both sides of the multiple gate structures 15 and on both sides of the multiple source structures 65. The multiple first contact regions 27 are arranged at intervals in the second direction Y along the multiple gate structures 15 and the multiple source structures 65, and are each formed in a strip shape extending in the second direction Y. The multiple first contact regions 27 are formed to overlap the body region 20, and increase the p-type impurity concentration of the body region 20.

[0346] Looking at the first contact regions 27 located on both sides of one source structure 65 (gate structure 15), the other first contact region 27 faces the first contact region 27 across the source structure 65 (gate structure 15). In other words, the multiple first contact regions 27 are arranged in a matrix as a whole in a plan view.

[0347] The following describes the configuration of one first contact region 27. The first contact region 27 is formed in a layer shape extending horizontally along the first main surface 3, and is connected to either or both of the gate structure 15 and the source structure 65 (both in this embodiment). The first contact region 27 faces the second buried electrode 68 of the source structure 65, with the second insulating film 67 of the source structure 65 sandwiched therebetween.

[0348] The bottom of the first contact region 27 is located closer to the bottom of the body region 20 than the depth position of the bottom of the recess of the second buried electrode 68. In this embodiment, the bottom of the first contact region 27 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall 65c of the source structure 65. Of course, the bottom of the first contact region 27 may also be located closer to the first main surface 3 than the depth position of the bottom wall 65c of the source structure 65.

[0349] Similar to the semiconductor device 1A, the first contact region 27 overlaps part or all (all in this embodiment) of the high-concentration region 24 in a cross-sectional view. The first contact region 27 has a bottom that traverses the bottom of the high-concentration region 24 and is positioned within the medium-concentration region 25. The bottom of the first contact region 27 overlaps the upper end of the well region 22 (the first extension 72a and the second extension 72b).

[0350] Similar to the semiconductor device 1A, the first contact region 27 has a high-concentration portion 27 a and a low-concentration portion 27 b. The high-concentration portion 27 a is formed at least closer to the first main surface 3 than the depth position of the bottom wall 65 c of the source structure 65, and extends horizontally in a layer shape along the first main surface 3. The high-concentration portion 27 a is connected to the gate structure 15 and the source structure 65.

[0351] The low concentration portion 27b crosses in the thickness direction the depth position of the bottom wall 65c of the source structure 65. That is, the low concentration portion 27b has a portion located closer to the first main surface 3 than the depth position of the bottom wall 65c of the source structure 65, and a portion located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall 65c of the source structure 65. The low concentration portion 27b overlaps the upper ends of the plurality of second well regions 72 and is electrically connected to the plurality of second well regions 72.

[0352] Of course, depending on the thickness of the high concentration portion 27a, the low concentration portion 27b may be located only on the first main surface 3 side relative to the depth position of the bottom wall 65c of the source structure 65. Depending on the thickness of the high concentration portion 27a, the low concentration portion 27b may be located only on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom wall 65c of the source structure 65.

[0353] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of second contact regions 28 formed in regions along the bottom walls 15c of the plurality of gate structures 15 within the chip 2. The description of the second contact regions 28 is omitted here, as it is similar to that of the semiconductor device 1A.

[0354] The semiconductor device 1C includes a plurality of third contact regions 78 formed in regions along the bottom walls 65c of the plurality of source structures 65 within the chip 2. The plurality of third contact regions 78 are formed in a manner similar to the plurality of second contact regions 28, and have a p-type impurity concentration approximately equal to the p-type impurity concentration of the plurality of second contact regions 28.

[0355] The third contact regions 78 are formed in a one-to-many correspondence with the bottom walls 65c of the source structures 65. The third contact regions 78 are respectively interposed in regions between the first contact regions 27 adjacent to each other in the first direction X in a plan view. In other words, the third contact regions 78 are positioned on the same straight line as the first contact regions 27 in the first direction X.

[0356] The plurality of third contact regions 78 are formed in regions between the plurality of well regions 22 (second contact regions 28) at intervals from the plurality of well regions 22 (second contact regions 28) in the first direction X. The plurality of third contact regions 78 are each formed in a strip shape extending along the bottom wall 65 c of the corresponding source structure 65 in plan view, and face the second buried electrode 68 with the second insulating film 67 interposed therebetween.

[0357] In the second direction Y, the lengths of the multiple third contact regions 78 are approximately equal to the lengths of the multiple first contact regions 27. The lengths of the multiple third contact regions 78 are approximately equal to the lengths of the multiple second contact regions 28. In the second direction Y, the spacing between the multiple third contact regions 78 is approximately equal to the spacing between the multiple first contact regions 27. The spacing between the multiple third contact regions 78 is approximately equal to the spacing between the multiple second contact regions 28.

[0358] The configuration of one third contact region 78 will be described below. The third contact region 78 is formed in a corresponding one of the second well regions 72. The third contact region 78 overlaps with the second high-concentration well region 73 and is electrically connected to the second high-concentration well region 73 within the second well region 72. The third contact region 78 is formed inward from the periphery of the second well region 72 with a gap therebetween.

[0359] The third contact regions 78 are formed at an interval from the bottom of the second well region 72 toward the bottom wall 65c of the source structure 65, and face the bottom of the second semiconductor region 7 across a part of the second well region 72. The third contact regions 78 are each formed in a columnar shape extending in the thickness direction (vertical direction Z) of the second semiconductor region 7 in a cross-sectional view.

[0360] In this embodiment, the third contact region 78 has a bottom that is located closer to the bottom of the second well region 72 than the thickness position of the intermediate portion of the second well region 72. Of course, the bottom of the third contact region 78 may be located closer to the bottom wall 65c of the source structure 65 than the thickness position of the intermediate portion of the second well region 72.

[0361] In this embodiment, the bottom of the third contact region 78 is located closer to the bottom wall 65c of the source structure 65 than the bottom of the moderately doped region 25. Of course, the bottom of the third contact region 78 may be located closer to the bottom of the second semiconductor region 7 than the bottom of the moderately doped region 25. In this case, the third contact region 78 may be formed to cross the bottom of the second well region 72 and have its bottom located within the second semiconductor region 7.

[0362] The thickness of the third contact region 78 is preferably approximately equal to the thickness of the second contact region 28. Of course, the thickness of the third contact region 78 may be greater than the thickness of the second contact region 28 or less than the thickness of the second contact region 28.

[0363] The third contact region 78 has an upper end portion that is located along a corner portion of the bottom wall 65c of the source structure 65. The third contact region 78 is electrically connected at its upper end portion to the plurality of first contact regions 27. In other words, the third contact region 78 electrically connects the second well region 72 and the second high-concentration well region 73 to the body region 20 via the plurality of first contact regions 27.

[0364] The third contact region 78 has a first extension 78a on the first sidewall 65a side and a second extension 78b on the second sidewall 65b side. The first extension 78a extends from the region directly below the source structure 65 to the lower end of the first sidewall 65a.

[0365] The first extension 78a faces the second buried electrode 68 in the horizontal direction, with the second insulating film 67 interposed therebetween. The first extension 78a is connected to the first contact region 27 in a region along the first sidewall 65a. Specifically, the first extension 78a is connected to both the high-concentration portion 27a and the low-concentration portion 27b of the first contact region 27.

[0366] The second extension portion 78b is drawn out from the region directly below the source structure 65 to the lower end of the second sidewall 65b and faces the second extension portion 78b across the source structure 65. The second extension portion 78b faces the second buried electrode 68 in the horizontal direction, with the second insulating film 67 therebetween. The second extension portion 78b is connected to the first contact region 27 in a region along the second sidewall 65b. Specifically, the second extension portion 78b is connected to both the high-concentration portion 27a and the low-concentration portion 27b of the first contact region 27.

[0367] The third contact region 78 has one or more (in this embodiment, multiple) fourth bulge portions 78c. The accompanying drawings illustrate an example of the third contact region 78 having two fourth bulge portions 78c. The number of fourth bulge portions 78c can be adjusted appropriately by adjusting the process conditions.

[0368] The multiple fourth bulge portions 78c are each formed by a portion of the third contact region 78 whose width in the horizontal direction (first direction X) gradually increases or decreases in the thickness direction, and are formed in multiple steps from the bottom wall 65c of the source structure 65 toward the bottom of the second semiconductor region 7.

[0369] The multiple fourth bulge portions 78c extend in an arc shape (circular arc shape) from a region directly below the source structure 65 to both sides of the source structure 65. When the third contact region 78 has a single third bulge portion 72c, the single third bulge portion 72c may be formed in an intermediate portion of the third contact region 78 so as to extend in an arc shape (circular arc shape) to both sides of the source structure 65.

[0370] Similar to the semiconductor device 1A, the semiconductor device 1C includes a main surface insulating film 30 that covers the first main surface 3. In this embodiment, the main surface insulating film 30 is connected to the insulating film 17 at the first surface portion 8, exposing the buried electrode 18. Although not specifically shown in the drawings, the main surface insulating film 30 is connected to the second insulating film 67 at the peripheral portion of the first surface portion 8, exposing the second buried electrode 68.

[0371] Similar to the semiconductor device 1A, the semiconductor device 1C includes an interlayer film 31 that covers the main surface insulating film 30. The interlayer film 31 covers the plurality of gate structures 15 (buried electrodes 18) on the first surface portion 8. The interlayer film 31 covers the plurality of source structures 65 (second buried electrodes 68) on the periphery of the first surface portion 8.

[0372] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of source openings 32 and a plurality of gate openings 33 (see FIG. 3) formed in the interlayer film 31. The plurality of source openings 32 are formed in a one-to-one correspondence with the plurality of source structures 65. Each of the plurality of source openings 32 exposes a corresponding one of the source structures 65, the plurality of source regions 21, and the plurality of first contact regions 27. Preferably, each of the plurality of source openings 32 has an opening end that is curved in an arc shape.

[0373] The multiple source openings 32 are formed in a strip shape extending in the second direction Y along the corresponding source structures 65. The multiple source openings 32 may be formed in a one-to-many correspondence with the corresponding source structures 65. In this case, the multiple source openings 32 may be formed at intervals along the corresponding source structure 65. Furthermore, in this case, the multiple source openings 32 may be formed in a quadrangular shape, a rectangular shape (strip shape), a circular shape, or the like in a plan view.

[0374] Similar to the semiconductor device 1A, the semiconductor device 1C includes a source electrode 35, a gate electrode 40, a gate wiring 41, and a drain electrode 42 arranged on the first main surface 3. The gate electrode 40, the gate wiring 41, and the drain electrode 42 will not be described here because they are similar to those in the semiconductor device 1A.

[0375] The source electrode 35 extends from above the interlayer film 31 into the plurality of source openings 32, and is electrically connected to the plurality of source structures 65, the plurality of source regions 21, and the plurality of first contact regions 27 within the plurality of source openings 32. Specifically, the source electrode 35 covers the first main surface 3 (first surface portion 8) within the plurality of source openings 32, and is mechanically and electrically connected to the plurality of source structures 65, the plurality of source regions 21, and the plurality of first contact regions 27 on the first main surface 3.

[0376] The source electrode 35 extends further into the multiple second trenches 66 from above the first major surface 3, and is mechanically and electrically connected to the second buried electrode 68, the multiple source regions 21, and the multiple first contact regions 27 within the multiple second trenches 66.

[0377] As in the case of the semiconductor device 1A, the source electrode 35 has a laminated structure including a lower electrode film 36 and a main electrode film 37, which are laminated in this order from the chip 2 side. The lower electrode film 36 has a laminated structure including a first electrode film 38 and a second electrode film 39.

[0378] The first electrode film 38 collectively covers the region of the interlayer film 31 where the plurality of source openings 32 are formed, and extends into the plurality of source openings 32 from above the interlayer film 31. The first electrode film 38 has a portion that covers the insulating main surface of the interlayer film 31 in a film-like manner, a portion that covers the wall surfaces of the plurality of source openings 32 in a film-like manner, a portion that covers the first main surface 3 inside the plurality of source openings 32 in a film-like manner, and a portion that covers the plurality of source structures 65 in a film-like manner.

[0379] Specifically, the first electrode film 38 directly covers the insulating main surface of the interlayer film 31 and faces the gate structure 15 across the interlayer film 31. The first electrode film 38 extends in an arc shape from above the insulating main surface of the interlayer film 31, following the opening edge of the source opening 32, and covers the wall surface of the source opening 32 in a film-like manner.

[0380] The first electrode film 38 covers the first main surface 3 in the form of a film within the source opening 32 and is mechanically and electrically connected to the plurality of source regions 21 and the plurality of first contact regions 27 on the first main surface 3 .

[0381] The first electrode film 38 extends from above the first main surface 3 into the second trench 66, and coats the first sidewall 65 a, the second sidewall 65 b, the second insulating film 67, and the second buried electrode 68 in the second trench 66. The first electrode film 38 is mechanically and electrically connected to the second buried electrode 68, the plurality of source regions 21, and the plurality of first contact regions 27.

[0382] The second electrode film 39 directly covers the first electrode film 38. The second electrode film 39 collectively covers the region of the interlayer film 31 where the plurality of source openings 32 are formed, sandwiching the first electrode film 38 therebetween, and extends from above the interlayer film 31 into the plurality of source openings 32.

[0383] The second electrode film 39 has a portion that coats the insulating main surface of the interlayer film 31 in a film-like manner, sandwiching the first electrode film 38 therebetween, a portion that coats the wall surfaces of the multiple source openings 32 in a film-like manner, sandwiching the first electrode film 38 therebetween, a portion that coats the first main surface 3 in a film-like manner within the multiple source openings 32 in a film-like manner, and a portion that coats the multiple source structures 65 in a film-like manner, sandwiching the first electrode film 38 therebetween.

[0384] Specifically, the second electrode film 39 covers the insulating main surface of the interlayer film 31 with the first electrode film 38 sandwiched therebetween, and faces the gate structure 15 with the interlayer film 31 and the first electrode film 38 sandwiched therebetween. The second electrode film 39 covers the opening edge of the source opening 32 in an arc shape with the first electrode film 38 sandwiched therebetween, and coats the wall surface of the source opening 32 in a film-like shape with the first electrode film 38 sandwiched therebetween.

[0385] The second electrode film 39 covers the first main surface 3 in a film-like manner within the source opening 32, sandwiching the first electrode film 38 therebetween, and is electrically connected to the multiple source regions 21 and the multiple first contact regions 27 via the first electrode film 38.

[0386] The second electrode film 39 extends from above the first main surface 3 into the second trench 66, and in a film-like manner covers the first sidewall 65 a, the second sidewall 65 b, the second insulating film 67, and the second buried electrode 68 with the first electrode film 38 sandwiched therebetween within the second trench 66. The second electrode film 39 is electrically connected to the second buried electrode 68, the plurality of source regions 21, and the plurality of first contact regions 27 via the first electrode film 38.

[0387] The main electrode film 37 directly covers the lower electrode film 36 (second electrode film 39). The main electrode film 37 backfills the second trenches 66 and the source openings 32 with the lower electrode film 36 in between, and collectively covers the regions of the interlayer film 31 where the source openings 32 are formed with the lower electrode film 36 in between.

[0388] The main electrode film 37 has a portion that covers the insulating main surface of the interlayer film 31 across the lower electrode film 36, a portion that covers the wall surfaces of the multiple source openings 32 across the lower electrode film 36, a portion that covers the first main surface 3 across the lower electrode film 36, and a portion that covers the second trench 66 across the lower electrode film 36.

[0389] Specifically, the main electrode film 37 covers the insulating main surface of the interlayer film 31 with the lower electrode film 36 sandwiched therebetween, and faces the gate structure 15 with the interlayer film 31 and the lower electrode film 36 sandwiched therebetween. The main electrode film 37 covers the opening edge of the source opening 32 with the lower electrode film 36 sandwiched therebetween. The main electrode film 37 covers the first main surface 3 within the source opening 32 with the lower electrode film 36 sandwiched therebetween, and is electrically connected to the plurality of source regions 21 and the plurality of first contact regions 27 via the lower electrode film 36.

[0390] The main electrode film 37 extends into the second trench 66 from above the first major surface 3, and covers the first sidewall 65 a, the second sidewall 65 b, the second insulating film 67, and the second buried electrode 68 with the lower electrode film 36 interposed therebetween within the second trench 66. The main electrode film 37 is electrically connected to the second buried electrode 68, the source region 21, and the first contact region 27 within the second trench 66 via the lower electrode film 36.

[0391] The semiconductor device 1C is manufactured by modifying the layout of various masks in the manufacturing method of the semiconductor device 1A. For example, the source structure 65 is formed simultaneously with the gate structure 15 by utilizing the formation process of the gate structure 15. For example, the second well region 72 is formed simultaneously with the well region 22 by utilizing the formation process of the well region 22.

[0392] For example, the second high-concentration well region 73 is formed simultaneously with the high-concentration well region 23 by utilizing the formation process of the high-concentration well region 23. For example, the third contact region 78 is formed simultaneously with the first contact region 27 (second contact region 28) by utilizing the formation process of the first contact region 27 (second contact region 28).

[0393] 17 is a cross-sectional view showing a main portion of a semiconductor device 1D according to the fourth embodiment. Referring to FIG. 17 , the semiconductor device 1D includes a plurality of well regions 22 formed as column regions that form a super junction structure, and a plurality of second well regions 72 also formed as column regions that form the super junction structure. Similar to the semiconductor device 1C, the plurality of well regions 22 and the plurality of second well regions 72 are each formed in a columnar shape extending in the thickness direction in cross-section.

[0394] The semiconductor device 1D includes a plurality of n-type intermediate drift regions 64 formed in the second semiconductor region 7. The plurality of intermediate drift regions 64 are each made of a region partitioned between the plurality of well regions 22 and the plurality of second well regions 72 in the second semiconductor region 7. That is, in this embodiment, the plurality of intermediate drift regions 64 each include a part of the second semiconductor region 7, a high concentration region 24, and an intermediate concentration region 25.

[0395] The multiple intermediate drift regions 64 are arranged alternately with the multiple well regions 22 and the multiple second well regions 72 in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the multiple intermediate drift regions 64 are formed in stripes extending in the second direction Y along the multiple well regions 22 and the multiple second well regions 72.

[0396] The extension direction of the intermediate drift regions 64 coincides with the off-direction of the SiC single crystal. The intermediate drift regions 64 are formed in a columnar shape extending in the thickness direction in cross-sectional view, and face the body regions 20 in a one-to-one correspondence.

[0397] The intermediate drift regions 64 form charge-balanced pn junctions together with the well regions 22 and the second well regions 72 in a thickness range below the gate structures 15. The charge-balanced state means that, for adjacent well regions 22 and second well regions 72, a depletion layer extending from one pn junction and a depletion layer extending from the other pn junction are connected within the intermediate drift region 64.

[0398] Hereinafter, first to eighth modified examples of semiconductor devices 1A to 1D will be shown with reference to Figures 18 to 25. Figures 18 to 25 show examples in which the first to eighth embodiment examples are applied to semiconductor device 1A, but the first to eighth embodiment examples can also be applied to semiconductor devices 1B to 1D.

[0399] 18, semiconductor devices 1A to 1D according to the first modification do not have well region 22, high-concentration well region 23, first contact region 27, and second contact region 28. In this embodiment, the plurality of medium-concentration regions 25 are integrated directly below the plurality of gate structures 15, and are formed as a single medium-concentration region 25 extending along the horizontal direction. The single medium-concentration region 25 corresponds to the above-mentioned base medium-concentration region 52.

[0400] When the first modification example is applied to the semiconductor devices 1C and 1D, the second well region 72, the second high-concentration well region 73, and the third contact region 78 are further removed. In this case, the multiple medium-concentration regions 25 are integrated directly below the multiple gate structures 15 and directly below the multiple source structures 65, and are formed as a single medium-concentration region 25 extending along the horizontal direction.

[0401] 19, semiconductor devices 1A to 1D according to the second modification do not have the medium concentration region 25. Referring to Fig. 20, semiconductor devices 1A to 1D according to the third modification have a configuration in which well region 22 (second well region 72), high concentration well region 23 (second high concentration well region 73), first contact region 27, and second contact region 28 (third contact region 78) are removed from the configuration of semiconductor devices 1A to 1D according to the second modification.

[0402] 21 , semiconductor devices 1A to 1D according to the fourth modification do not have high-concentration region 24. In this embodiment, intermediate-concentration region 25 is formed in a region below body region 20 as high-concentration region 24 having an n-type impurity concentration higher than the n-type impurity concentration of second semiconductor region 7.

[0403] That is, in this embodiment, the medium concentration region 25 has a portion formed in the second semiconductor region 7 in a thickness range between the bottom wall 15 c of the gate structure 15 (source structure 65) and the bottom of the body region 20. According to this configuration, the resistance value in the vicinity of the gate structure 15 is reduced by the medium concentration region 25 formed below the body region 20. In addition, the medium concentration region 25 offsets undesired p-type impurities introduced laterally of the gate structure 15 due to process errors or the like.

[0404] Referring to Figure 22, semiconductor devices 1A to 1D according to the fifth modified example have a configuration in which the well region 22 (second well region 72), high-concentration well region 23 (second high-concentration well region 73), first contact region 27 and second contact region 28 (third contact region 78) are removed from the configuration of semiconductor devices 1A to 1D according to the fourth modified example.

[0405] 23, semiconductor devices 1A to 1D according to the sixth modification include a plurality of high concentration regions 24 formed in second semiconductor region 7 at intervals from a plurality of gate structures 15. That is, in this embodiment, the plurality of high concentration regions 24 face sidewalls of the plurality of gate structures 15 with a portion of a medium concentration region 25 interposed therebetween.

[0406] When the medium concentration region 25 is not present, the multiple high concentration regions 24 face the sidewalls of the multiple gate structures 15 with a part of the second semiconductor region 7 interposed therebetween. The multiple high concentration regions 24 may have substantially the same n-type impurity concentration as one another, or may have different n-type impurity concentrations as one another.

[0407] When the sixth modification example is applied to the semiconductor devices 1C and 1D, the multiple high concentration regions 24 are formed at intervals from the multiple gate structures 15 toward the multiple source structures 65. In this case, the multiple high concentration regions 24 may be connected to the multiple source structures 65. Of course, the multiple high concentration regions 24 may also be formed at intervals from the multiple source structures 65 toward the multiple gate structures 15.

[0408] The high concentration region 24 in the sixth variant is obtained by introducing n-type impurities into the second semiconductor region 7 through a mask having multiple openings that expose the regions where multiple high concentration regions 24 are to be formed during the process of forming the high concentration region 24.

[0409] 24 , semiconductor devices 1A to 1D according to the seventh modification include a plurality of high concentration regions 24 formed in second semiconductor region 7 in regions along the lower ends of the sidewalls (first sidewall 15 a and second sidewall 15 b) of a plurality of gate structures 15. The plurality of high concentration regions 24 are formed at intervals from one another in regions between the plurality of gate structures 15, and face one another with part of second semiconductor region 7 sandwiched therebetween.

[0410] The plurality of heavily doped regions 24 may extend in the vertical direction Z along the side walls (first side wall 15 a and second side wall 15 b) of the plurality of gate structures 15. The plurality of heavily doped regions 24 may be formed so as to bulge outward from the side walls (first side wall 15 a and second side wall 15 b) of the plurality of gate structures 15.

[0411] In this embodiment, the plurality of medium concentration regions 25 have portions interposed between the plurality of high concentration regions 24 in the regions between the plurality of gate structures 15. The plurality of medium concentration regions 25 are electrically connected to the bottoms of the plurality of body regions 20.

[0412] When the seventh variant is applied to semiconductor devices 1C and 1D, the multiple high concentration regions 24 are formed in regions along the lower ends of the sidewalls (first sidewall 15a and second sidewall 15b) of the multiple gate structures 15, spaced apart from the multiple source structures 65.

[0413] The high concentration region 24 according to the seventh modification is obtained by introducing n-type impurities into the second semiconductor region 7 through the sidewalls (first sidewall 15 a and second sidewall 15 b) of the trench 16 of the gate structure 15. The n-type impurities may be introduced into the second semiconductor region 7 by oblique ion implantation.

[0414] 25 , semiconductor devices 1A to 1D according to the eighth modification include gate structures 15 each having a trench 16, an insulating film 17, a buried electrode 18, and a buried insulator 80. Buried insulator 80 is buried in trench 16 so as to expose first main surface 3, and covers insulating film 17 and buried electrode 18 within trench 16. Buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Buried insulator 80 preferably includes a silicon oxide film.

[0415] The source electrode 35 has a portion that directly covers the first main surface 3 and a portion that directly covers the buried insulator 80. The source electrode 35 is electrically connected to the plurality of source regions 21 and the plurality of first contact regions 27 on the first main surface 3, and is electrically insulated from the plurality of buried electrodes 18 by the buried insulator 80. With this configuration, the connection area of ​​the source electrode 35 with the plurality of source regions 21 and the plurality of first contact regions 27 is increased.

[0416] The above-described embodiments (including variations) can be implemented in other forms. For example, in each of the above-described embodiments, a structure may be adopted in which the conductivity type of an "n-type" semiconductor region is inverted to "p-type" and the conductivity type of a "p-type" semiconductor region is inverted to "n-type." A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and the accompanying drawings.

[0417] In the above-described embodiment, the chip 2 includes a SiC single crystal. However, the chip 2 may include a wide bandgap semiconductor single crystal other than a SiC single crystal. A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of silicon. For example, the chip 2 may include gallium nitride, gallium oxide, diamond, or the like. Of course, the chip 2 may also include a silicon single crystal.

[0418] Similarly, the first semiconductor region 6 may contain a wide bandgap semiconductor single crystal other than SiC single crystal. The first semiconductor region 6 may contain gallium nitride, gallium oxide, diamond, etc. Of course, the first semiconductor region 6 may also contain silicon single crystal.

[0419] Similarly, the second semiconductor region 7 may contain a wide bandgap semiconductor single crystal other than SiC single crystal. The second semiconductor region 7 may contain gallium nitride, gallium oxide, diamond, etc. Of course, the second semiconductor region 7 may also contain silicon single crystal.

[0420] In each of the above-described embodiments, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description.

[0421] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following descriptions may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0422] [A1] A semiconductor device (1A-1D) including: a chip (2) having a main surface (3); a semiconductor region (7) of a first conductivity type (n-type) formed on the main surface (3); a trench-type gate structure (15) formed on the main surface (3) and positioned within the semiconductor region (7); a body region (20) of a second conductivity type (p-type) formed in a region on the main surface (3) side relative to a depth position of a bottom wall (15c) of the gate structure (15) in a surface layer portion of the main surface (3); and a high-concentration region (24) of the first conductivity type (n-type) formed in the chip (2) in a thickness range between the bottom wall (15c) of the gate structure (15) and a bottom of the body region (20), the high-concentration region having an impurity concentration higher than the impurity concentration of the semiconductor region (7).

[0423] [A2] The semiconductor device (1A to 1D) according to A1, wherein the chip (2) includes SiC.

[0424] [A3] The semiconductor device (1A-1D) according to A1 or A2, wherein the high concentration region (24) has a bottom portion positioned on the main surface (3) side relative to a depth position of a bottom wall (15c) of the gate structure (15).

[0425] [A4] The semiconductor device (1A to 1D) according to any one of A1 to A3, wherein the high concentration region (24) is connected to the gate structure (15).

[0426] [A5] The semiconductor device (1A to 1D) according to any one of A1 to A4, wherein the high concentration region (24) has a thickness less than the thickness of the body region (20).

[0427] [A6] A semiconductor device (1A to 1D) according to any one of A1 to A5, wherein the body region (20) has a bottom portion positioned closer to the bottom wall (15c) of the gate structure (15) than the depth position of the middle portion of the gate structure (15).

[0428] [A7] The semiconductor device (1A to 1D) according to any one of A1 to A6, wherein the gate structure (15) includes a sidewall having an inclination angle of 87° or more and 93° or less.

[0429] [A8] A semiconductor device (1A-1D) according to any one of A1 to A7, wherein a plurality of the gate structures (15) are formed at intervals on the main surface (3), the body region (20) is formed in a region between the plurality of the gate structures (15), and the high concentration region (24) is formed in the region between the plurality of the gate structures (15) in a thickness range between bottom walls (15c) of the plurality of the gate structures (15) and a bottom of the body region (20).

[0430] [A9] The semiconductor device (1A to 1D) according to A8, wherein the high concentration region (24) is connected to a plurality of the gate structures (15).

[0431] [A10] A semiconductor device (1A-1D) according to any one of A1 to A9, further including: a first conductivity type (n-type) impurity region (21) formed in a region on the main surface (3) side of the body region (20) so as to align with the gate structure (15); the high concentration region (24) facing the impurity region (21) across a portion of the body region (20); and a channel (26) formed between the impurity region (21) and the high concentration region (24) within the body region (20).

[0432] [A11] The semiconductor device (1A to 1D) according to A10, wherein the high concentration region (24) has an impurity concentration lower than the impurity concentration of the impurity region (21).

[0433] [A12] A semiconductor device (1A to 1D) according to any one of A1 to A11, further including a second conductivity type (p-type) well region (22) formed in the chip (2) in a region along the bottom wall (15c) of the gate structure (15).

[0434] [A13] The semiconductor device (1A-1D) according to A12, wherein the well region (22) has an upper end portion along a corner portion of the bottom wall (15c) of the gate structure (15), and the high concentration region (24) is formed in a thickness range between the bottom of the body region (20) and the upper end portion of the well region (22).

[0435] [A14] The semiconductor device (1A to 1D) according to A12 or A13, wherein the well region (22) has a thickness greater than a thickness of the body region (20).

[0436] [A15] The semiconductor device (1A to 1D) according to any one of A12 to A14, further including a high-concentration well region (23) of a second conductivity type (p-type) formed in the well region (22) at a distance from the bottom of the well region (22) toward the bottom wall (15c) of the gate structure (15), and having an impurity concentration higher than the impurity concentration of the well region (22).

[0437] [A16] The semiconductor device (1A to 1D) described in A15, wherein the high concentration well region (23) has a bottom positioned on the bottom wall (15c) side of the gate structure (15) relative to the depth position of the middle part of the well region (22).

[0438] [A17] A semiconductor device (1A-1D) according to any one of A1 to A16, further including a second conductivity type (p-type) contact region (27) formed in a region along the sidewall of the gate structure (15) within the chip (2) and having an impurity concentration higher than the impurity concentration of the body region (20).

[0439] [A18] A semiconductor device (1A-1D) according to any one of A1 to A17, further including a second conductivity type (p-type) bottom contact region (28) formed in a region along the bottom wall (15c) of the gate structure (15) within the chip (2) and having an impurity concentration higher than the impurity concentration of the body region (20).

[0440] [A19] A semiconductor device (1A to 1D) according to any one of A1 to A18, further including a first conductivity type (n-type) medium concentration region (25) formed in a region below the high concentration region (24) within the chip (2) and having an impurity concentration higher than the impurity concentration of the semiconductor region (7) and lower than the impurity concentration of the high concentration region (24).

[0441] [A20] The semiconductor device (1A to 1D) described in A19, wherein the medium concentration region (25) has a region positioned above the depth position of the bottom wall (15c) of the gate structure (15) and a region positioned below the depth position of the bottom wall (15c) of the gate structure (15).

[0442] Although specific embodiments have been described in detail above, these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiment examples.

[0443] 1A Semiconductor device 1B Semiconductor device 1C Semiconductor device 1D Semiconductor device 3 First main surface 7 Second semiconductor region 15 Gate structure 15c Bottom wall of gate structure 20 Body region 21 Source region (impurity region) 22 Well region 23 Highly doped well region 24 Highly doped region 25 Medium doped region 26 Channel region 27 First contact region 28 Second contact region (bottom contact region)

Claims

1. a chip having a major surface; a first conductivity type semiconductor region formed in a surface layer portion of the main surface; a trench-type gate structure formed on the major surface and positioned within the semiconductor region; a body region of a second conductivity type formed in a surface layer portion of the main surface in a region on the main surface side with respect to a depth position of a bottom wall of the gate structure; a high concentration region of a first conductivity type formed in the chip in a thickness range between a bottom wall of the gate structure and a bottom of the body region, the high concentration region having an impurity concentration higher than an impurity concentration of the semiconductor region.

2. The semiconductor device according to claim 1 , wherein the chip comprises SiC.

3. 2. The semiconductor device according to claim 1, wherein said heavily doped region has a bottom located on said main surface side relative to a depth position of a bottom wall of said gate structure.

4. The semiconductor device according to claim 1 , wherein said heavily doped region is connected to said gate structure.

5. 2. The semiconductor device according to claim 1, wherein said heavily doped region has a thickness less than a thickness of said body region.

6. 2. The semiconductor device according to claim 1, wherein said body region has a bottom portion positioned closer to a bottom wall of said gate structure than a depth position of an intermediate portion of said gate structure.

7. The semiconductor device according to claim 1 , wherein the gate structure includes sidewalls having a slope angle of 87° or more and 93° or less.

8. a plurality of the gate structures are formed at intervals on the main surface; the body region is formed in a region between the plurality of gate structures; 2. The semiconductor device according to claim 1, wherein said high concentration region is formed in a thickness range between bottom walls of said gate structures and a bottom of said body region in a region between said gate structures.

9. The semiconductor device according to claim 8 , wherein said high concentration region is connected to a plurality of said gate structures.

10. an impurity region of a first conductivity type formed in a region on the main surface side of the body region so as to be aligned with the gate structure; the high concentration region facing the impurity region with a part of the body region interposed therebetween; 10. The semiconductor device according to claim 1, further comprising: a channel formed in said body region between said impurity region and said high concentration region.

11. 11. The semiconductor device according to claim 10, wherein the high concentration region has an impurity concentration lower than that of the impurity region.

12. 10. The semiconductor device according to claim 1, further comprising a well region of a second conductivity type formed in a region along a bottom wall of said gate structure within said chip.

13. the well region has an upper edge along a corner of a bottom wall of the gate structure; 13. The semiconductor device according to claim 12, wherein said heavily doped region is formed in a thickness range between a bottom of said body region and an upper end of said well region.

14. The semiconductor device according to claim 12 , wherein the well region has a thickness greater than a thickness of the body region.

15. 13. The semiconductor device according to claim 12, further comprising a high concentration well region of a second conductivity type formed in the well region at a distance from a bottom of the well region toward a bottom wall of the gate structure, the high concentration well region having an impurity concentration higher than an impurity concentration of the well region.

16. 16. The semiconductor device according to claim 15, wherein said high concentration well region has a bottom portion positioned on the bottom wall side of said gate structure with respect to a depth position of an intermediate portion of said well region.

17. 10. The semiconductor device according to claim 1, further comprising a second conductivity type contact region formed in a region along a sidewall of the gate structure within the chip, the second conductivity type contact region having an impurity concentration higher than an impurity concentration of the body region.

18. 10. The semiconductor device according to claim 1, further comprising a bottom contact region of a second conductivity type formed in a region along a bottom wall of the gate structure within the chip, the bottom contact region having an impurity concentration higher than an impurity concentration of the body region.

19. 10. The semiconductor device according to claim 1, further comprising a first conductivity type medium concentration region formed in a region below the high concentration region within the chip, the medium concentration region having an impurity concentration higher than that of the semiconductor region and lower than that of the high concentration region.

20. 20. The semiconductor device according to claim 19, wherein the medium concentration region has a region positioned above a depth position of a bottom wall of the gate structure and a region positioned below a depth position of the bottom wall of the gate structure.