Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device that includes a transistor having a large ON current. The semiconductor device includes: a semiconductor layer; first to third conductive layers; and first and second insulative layers. The first insulative layer includes a first opening that reaches the first conductive layer. The second conductive layer is located above the first insulative layer and includes a second opening in a region overlapping the first opening. The semiconductor layer includes: a first region adjoining the upper surface of the first conductive layer; and a second region adjoining a lateral surface of the first insulative layer. The second insulative layer is located above the semiconductor layer. The third conductive layer includes a region overlapping the semiconductor layer with the second insulative layer disposed therebetween. The first region and the second insulative layer each include a first element. The first element is boron or phosphorus. The concentration of the first element in the second region is no more than 0.001 times the concentration of the first element in the first region. The angle formed by the lateral surface of the first insulative layer and the upper surface of the first conductive layer is 66 degrees to 90 degrees.

Description

Semiconductor device and method for manufacturing the same

[0001] BACKGROUND OF THE INVENTION 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof. 2. Description of the Related Art One embodiment of the present invention relates to a transistor and a manufacturing method thereof.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] Semiconductor devices including transistors are widely used in electronic devices. For example, in display devices, pixel size can be reduced by reducing the area occupied by a transistor, and resolution can be increased. Therefore, miniaturized transistors are in demand.

[0005] As devices requiring high-definition display devices, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR) are being actively developed.

[0006] 2. Description of the Related Art As display devices, for example, light-emitting devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using organic EL elements.

[0008] International Publication No. 2016 / 038508

[0009] An object of one embodiment of the present invention is to provide a semiconductor device including a micro-sized transistor. Another object is to provide a semiconductor device including a transistor with a short channel length. Another object is to provide a semiconductor device including a transistor with high on-state current. Another object is to provide a semiconductor device including a transistor with high field-effect mobility. Another object is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device with a small occupation area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-resolution display device. Another object is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another object is to provide a novel transistor, semiconductor device, or display device, or a manufacturing method thereof.

[0010] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0011] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer is located on the first conductive layer. The first insulating layer has a first opening reaching the first conductive layer. The second conductive layer is located on the first insulating layer. The second conductive layer has a second opening in a region overlapping with the first opening. The semiconductor layer has, in the first opening, a first region in contact with a top surface of the first conductive layer and a second region in contact with a side surface of the first insulating layer. The second insulating layer is located on the semiconductor layer. The third conductive layer has a region overlapping with the semiconductor layer via the second insulating layer. The first region and the second insulating layer each contain a first element. The first element is boron or phosphorus. The concentration of the first element in the second region is 1×10 of the concentration of the first element in the first region. −３ The angle formed between the side surface of the first insulating layer and the top surface of the first conductive layer in the first opening is equal to or greater than 66 degrees and equal to or less than 90 degrees.

[0012] In the semiconductor device described above, the semiconductor layer preferably has a region in contact with a side surface of the second conductive layer in the second opening and a third region in contact with an upper surface of the second conductive layer. The third region preferably contains the first element. The concentration of the first element in the second region is preferably 1×10 of the concentration of the first element in the third region. −３ It is preferable that the ratio is 1:1 or less.

[0013] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer is located on the first conductive layer. The first insulating layer has a first opening reaching the first conductive layer. The second conductive layer is located on the first insulating layer. The second conductive layer has a second opening in a region overlapping with the first opening. The semiconductor layer has, in the first opening, a first region in contact with a top surface of the first conductive layer and a second region in contact with a side surface of the first insulating layer. The second insulating layer is located on the semiconductor layer. The third conductive layer has a region overlapping with the semiconductor layer via the second insulating layer. The first region and the second insulating layer each contain a first element. The first element is boron or phosphorus. The concentration of the first element in the second region is 1×10 of the concentration of the first element in the first region. −３ In a direction perpendicular to the top surface of the first conductive layer, the thickness of the portion of the second insulating layer that contacts the second region is 2.5 times or more the thickness of the portion of the second insulating layer that contacts the first region.

[0014] In the semiconductor device described above, the semiconductor layer preferably has a region in contact with a side surface of the second conductive layer in the second opening and a third region in contact with an upper surface of the second conductive layer. The third region preferably contains the first element. The thickness of the portion of the second insulating layer in contact with the second region in a direction perpendicular to the upper surface of the first conductive layer is preferably 2.5 times or more the thickness of the portion of the second insulating layer in contact with the third region.

[0015] In the semiconductor device described above, the first region preferably contains hydrogen, and the concentration of hydrogen in the first region is preferably higher than the concentration of hydrogen in the second region.

[0016] In the semiconductor device described above, the first region preferably contains a second element, which is preferably argon, krypton, or xenon, and the concentration of the second element in the first region preferably is higher than the concentration of the second element in the second region.

[0017] In the above-described semiconductor device, the semiconductor layer preferably contains a metal oxide.

[0018] In the semiconductor device described above, the first insulating layer preferably includes a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer. The third insulating layer and the fifth insulating layer preferably include silicon and nitrogen, respectively. The fourth insulating layer preferably includes silicon and oxygen.

[0019] In the semiconductor device described above, the first insulating layer preferably includes a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer. The third insulating layer preferably includes silicon and nitrogen. The fourth insulating layer preferably includes silicon and oxygen. The fifth insulating layer preferably includes one or both of aluminum and hafnium, and oxygen.

[0020] One embodiment of the present invention is a method for manufacturing a semiconductor device, comprising: forming a first conductive layer; forming a first insulating film on the first conductive layer; forming the first conductive film on the first insulating film; processing the first conductive film and the first insulating film; forming a first insulating layer having a first opening reaching the first conductive layer and a second conductive layer having a second opening overlapping the first opening; forming a semiconductor layer over the first conductive layer, the first insulating layer, and the second conductive layer; forming a second insulating layer on the semiconductor layer; supplying a first element to the semiconductor layer through the second insulating layer by plasma ion doping or ion implantation; and forming a third conductive layer on the second insulating layer. The first element is boron or phosphorus. The semiconductor layer has a first region in contact with a top surface of the first conductive layer and a second region in contact with a side surface of the first insulating layer. The first region and the second insulating layer each contain the first element. Pa expressed by the following formula (1) is 1×10 −３ The following is the result.

[0021]

[0022] In the above formula (1), θ is less than 90 degrees and represents the angle formed between the side surface of the first opening in the first insulating layer and the top surface of the first conductive layer, α is a real number greater than 0 and represents the ratio of the standard deviation to the projected range of ions in the supply of the first element, and β is a real number greater than 0 and represents the ratio, in a direction perpendicular to the top surface of the first conductive layer, of the thickness of the portion of the second insulating layer provided along the side surface of the first insulating layer to the thickness of the portion of the second insulating layer provided along the top surface of the first conductive layer.

[0023] In the above-described method for manufacturing a semiconductor device, a second element is preferably supplied to the semiconductor layer through the second insulating layer by plasma ion doping or ion implantation before the first element is supplied. The second element is preferably argon, krypton, or xenon.

[0024] According to one embodiment of the present invention, a semiconductor device including a micro-sized transistor can be provided. Alternatively, a semiconductor device including a transistor with a short channel length can be provided. Alternatively, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with high field-effect mobility can be provided. Alternatively, a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, a semiconductor device that operates at high speed can be provided. Alternatively, a semiconductor device with a small occupation area can be provided. Alternatively, a semiconductor device with low wiring resistance can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-resolution display device can be provided. Alternatively, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Alternatively, a novel transistor, semiconductor device, or display device, or a manufacturing method thereof can be provided.

[0025] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0026] FIG. 1A is a top view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIGS. 2A to 2D are perspective views showing an example of a semiconductor device. FIG. 3A is a top view showing an example of a semiconductor device. FIG. 3B is a cross-sectional view showing an example of a semiconductor device. FIG. 4 is a cross-sectional view showing an example of a semiconductor device. FIGS. 5A and 5B are diagrams showing examples of concentrations of impurity elements. FIG. 6 is a diagram showing an example of a concentration ratio of impurity elements. FIG. 7 is a cross-sectional view showing an example of a semiconductor device. FIGS. 8A and 8B are diagrams showing examples of concentration ratios of impurity elements. FIG. 9 is a diagram showing an example of a concentration ratio of impurity elements. FIG. 10 is a cross-sectional view showing an example of a semiconductor device. FIGS. 11A to 11D are cross-sectional views showing an example of a semiconductor device. FIG. 12 is a cross-sectional view showing an example of a semiconductor device. FIGS. 13A to 13C are cross-sectional views showing an example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing an example of a semiconductor device. FIGS. 15A and 15B are cross-sectional views showing an example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing an example of a semiconductor device. 17A and 17B are cross-sectional views showing an example of a semiconductor device. FIG. 18 is a cross-sectional view showing an example of a semiconductor device. FIGS. 19A and 19B are cross-sectional views showing an example of a semiconductor device. FIG. 20A is a top view showing an example of a semiconductor device. FIGS. 20B and 20C are cross-sectional views showing an example of a semiconductor device. FIGS. 21A to 21I are circuit diagrams showing an example of a semiconductor device. FIG. 22A is a top view showing an example of a semiconductor device. FIGS. 22B and 22C are cross-sectional views showing an example of a semiconductor device. FIG. 23A is a top view showing an example of a semiconductor device. FIGS. 23B and 23C are cross-sectional views showing an example of a semiconductor device. FIG. 24A is a top view showing an example of a semiconductor device. FIG. 24B is a cross-sectional view showing an example of a semiconductor device. FIG. 25A is a top view showing an example of a semiconductor device. FIG. 25B is a cross-sectional view showing an example of a semiconductor device. FIGS. 26A and 26B are equivalent circuit diagrams of semiconductor devices. FIG. 26C is a top view showing an example of a semiconductor device. FIG. 27 is a cross-sectional view showing an example of a semiconductor device. FIG. 28 is a perspective view showing an example of a semiconductor device.29A to 29D are perspective views showing an example of a semiconductor device. FIGS. 30A and 30B are equivalent circuit diagrams of the semiconductor device. FIG. 30C is a top view showing an example of a semiconductor device. FIG. 31 is a cross-sectional view showing an example of a semiconductor device. FIG. 32 is a perspective view showing an example of a semiconductor device. FIGS. 33A to 33D are perspective views showing an example of a semiconductor device. FIGS. 34A to 34E are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 35A to 35D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 36A to 36C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 37 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. FIGS. 38A and 38B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 39 is a perspective view showing an example of a display device. FIGS. 40A and 40B are cross-sectional views showing an example of a display device. FIG. 41 is a cross-sectional view showing an example of a display device. FIGS. 42A to 42C are cross-sectional views showing an example of a display device. FIGS. 43A and 43B are cross-sectional views showing an example of a display device. Fig. 44 is a cross-sectional view showing an example of a display device. Fig. 45 is a cross-sectional view showing an example of a display device. Fig. 46 is a cross-sectional view showing an example of a display device. Figs. 47A and 47B are cross-sectional views showing an example of a display device. Figs. 48A to 48D are diagrams showing an example of an electronic device. Figs. 49A to 49F are diagrams showing an example of an electronic device. Figs. 50A to 50G are diagrams showing an example of an electronic device.

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0028] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0029] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0030] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0031] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0032] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0033] The functions of "source" and "drain" may be interchanged when transistors of different polarities are used or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" may be used interchangeably in this specification. Note that the names of the source and drain of a transistor may be appropriately changed depending on the situation, such as the source terminal and drain terminal, or the source electrode and drain electrode.

[0034] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0035] Unless otherwise specified, in this specification, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0036] In this specification, the top surface shape of a component refers to the contour shape of the component as viewed from above (also referred to as a plan view). The top view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0037] In this specification, the phrase "top surface shapes are approximately the same" refers to at least a portion of the contours of stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the phrase "top surface shapes are approximately the same" may also be used. Furthermore, when the top surface shapes are the same or approximately the same, it can also be said that the edges are aligned or approximately aligned.

[0038] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface on which a substrate is to be formed. The angle between the inclined side surface and the substrate surface or the surface on which a substrate is to be formed is sometimes referred to as a taper angle. The side surface of a structure, the substrate surface, and the surface on which a substrate is to be formed do not necessarily have to be completely flat, but may be substantially planar with a slight curvature or a substantially planar with a slight unevenness.

[0039] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution due to the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment for manufacturing metal masks and a metal mask cleaning process. Furthermore, devices with an MML structure are suitable for mass production because they can keep manufacturing costs low.

[0040] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0041] In this specification and the like, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0042] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0043] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0044] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0045] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 33D. FIG.

[0046] One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first conductive layer functions as one of a source electrode and a drain electrode of a transistor, and the second conductive layer functions as the other. The third conductive layer functions as one of a gate electrode and a gate insulating layer. A region of the semiconductor layer in contact with the first conductive layer functions as one of a source region and a drain region, and a region in contact with the second conductive layer functions as the other.

[0047] The first insulating layer is located on the first conductive layer and has a first opening reaching the first conductive layer. An angle formed between a side surface of the first opening of the first insulating layer and an upper surface of the first conductive layer is 66 degrees or more and 90 degrees or less. The second conductive layer is located on the first insulating layer and has a second opening in a region overlapping with the first opening. The semiconductor layer has, in the first opening, a first region contacting the upper surface of the first conductive layer and a second region contacting the side surface of the first insulating layer. The semiconductor layer also has, in the second opening, a region contacting the side surface of the second conductive layer and a third region contacting the upper surface of the second conductive layer. The second insulating layer is located on the semiconductor layer. The third conductive layer has a region overlapping with the semiconductor layer via the second insulating layer.

[0048] The first region, the third region, and the second insulating layer each contain an impurity element. The impurity element is preferably a first element. The first element is preferably one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and a noble gas (helium, neon, argon, krypton, xenon, etc.).

[0049] By including the impurity element in the first region and the third region, the electric resistance of the source region and the drain region can be reduced, and a transistor with a large on-state current can be obtained.

[0050] The second region functions as a channel formation region of the transistor. The concentration of the first element in the second region is 1×10 1 / 2 times lower than the concentration of the first element in the first region. −３ The concentration of the first element in the second region is preferably 1×10 or less times the concentration of the first element in the third region. −３ By lowering the concentration of the first element in the second region, a shift in threshold voltage can be suppressed, and a transistor with favorable electrical characteristics can be obtained.

[0051] In a transistor according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0052] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0053] <Configuration Example 1> [Configuration Example 1-1] A semiconductor device according to one embodiment of the present invention will be described. FIG. 1A shows a top view (also referred to as a plan view) of a semiconductor device 10. FIG. 1B shows a cross-sectional view of a section taken along dashed-dotted line A1-A2 in FIG. 1A, and FIG. 1C shows a cross-sectional view of a section taken along dashed-dotted line B1-B2 in FIG. 1A. Note that some components of the semiconductor device 10 (such as a gate insulating layer) are omitted in FIG. 1A. As with FIG. 1A, some components are also omitted in the top views of the semiconductor device in subsequent drawings. FIGS. 2A to 2D show perspective views of the semiconductor device 10. FIG. 2B shows a cross-sectional view taken along dashed-dotted line C1-C2 in FIG. 2A. In FIG. 2C, the insulating layer shown in FIG. 2A is transparent, and its outline is indicated by a dashed line. Similarly, in FIG. 2D, the insulating layer shown in FIG. 2B is transparent, and its outline is indicated by a dashed line. FIGS. 3A and 3B show enlarged views of FIGS. 1A and 1B.

[0054] The semiconductor device 10 includes a transistor 100 and an insulating layer 110. The semiconductor device 10 is provided on a substrate 102.

[0055] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 functions as a gate electrode. A part of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other. A region of the semiconductor layer 108 that overlaps with the gate electrode between the source electrode and the drain electrode with the gate insulating layer interposed therebetween functions as a channel formation region. A region of the semiconductor layer 108 that is in contact with the source electrode functions as a source region, and a region that is in contact with the drain electrode functions as a drain region.

[0056] A conductive layer 112a is provided on a substrate 102, an insulating layer 110 is provided on the conductive layer 112a, and a conductive layer 112b is provided on the insulating layer 110. The insulating layer 110 is in contact with the conductive layer 112a and the conductive layer 112b and has a region sandwiched between them. The conductive layer 112a has a region overlapping with the conductive layer 112b via the insulating layer 110. The insulating layer 110 has an opening 141 that reaches the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141. The conductive layer 112b has an opening 143 in a region overlapping with the conductive layer 112a. The opening 143 is provided in a region overlapping with the opening 141.

[0057] The semiconductor layer 108 is provided to cover the openings 141 and 143. The semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a and a region in contact with the side surface of the insulating layer 110 in the opening 141, and a region in contact with the side surface of the conductive layer 112b in the opening 143. Furthermore, the semiconductor layer 108 preferably has a region in contact with the top surface of the conductive layer 112b. The semiconductor layer 108 has a shape that follows the shapes of the top surface and side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a.

[0058] The semiconductor material used for the semiconductor layer 108 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: Oxide Semiconductor). Note that these semiconductor materials may contain impurities as dopants.

[0059] The crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0060] The semiconductor layer 108 can be made of, for example, silicon. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon for its channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon for its channel formation region has high field-effect mobility and can operate at high speed. Furthermore, a transistor using microcrystalline silicon for its channel formation region has higher field-effect mobility and can operate at high speed than a transistor using amorphous silicon.

[0061] The semiconductor layer 108 preferably includes a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has extremely high field-effect mobility compared to a transistor using amorphous silicon. Furthermore, an OS transistor has an extremely low off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0062] The semiconductor layer 108 has a region 108Da in one part and a region 108Db in the other part. The region 108Da and the region 108Db each contain an impurity element. The region 108Da and the region 108Db each have a higher concentration of the impurity element and a lower electrical resistance (hereinafter also referred to as a low-resistance region) than other regions (e.g., channel formation regions) of the semiconductor layer 108. In the semiconductor layer 108, the channel formation region is located between the region 108Da and the region 108Db.

[0063] 1B, 1C, and 3B show an example in which the region 108Da is formed in a region of the semiconductor layer 108 that is in contact with the upper surface of the conductive layer 112a and is located between the upper surface of the conductive layer 112a and the lower surface of the conductive layer 104. The region in which the region 108Da is formed is not limited thereto, and for example, the region 108Da may be formed in the entire region that is in contact with the upper surface of the conductive layer 112a. For example, the impurity element may diffuse due to heat applied when the impurity element is supplied to the semiconductor layer 108 or in a process after the impurity element is supplied.

[0064] 1B, 1C, and 3B show an example in which the region 108Db is formed in a region of the semiconductor layer 108 that is in contact with the top surface of the conductive layer 112b. Note that the region 108Db may also be provided in a region of the semiconductor layer 108 that is in contact with the side surface of the conductive layer 112b. The region 108Db may also be provided in a part of a region of the semiconductor layer 108 that is in contact with the side surface of the insulating layer 110.

[0065] It is preferable to use the first element as the impurity element, or it is preferable to use both the first element and hydrogen as the impurity element.

[0066] As the first element, it is preferable to use one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0067] The first element is not limited to the above elements, and one or more of first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and elements included in rare earth elements can be used.

[0068] By supplying the first element to the source region and the drain region (this can also be referred to as adding the first element or injecting the first element), oxygen vacancies (V Ｏ : Oxygen Vacancy) occurs. Ｏ ) into which hydrogen has entered (hereinafter referred to as V Ｏ Carriers are generated by the ion implantation (also referred to as H). This can reduce the electrical resistance of the source region and the drain region. Furthermore, the electrical resistance of the semiconductor layer 108, the contact resistance between the semiconductor layer 108 and the conductive layer 112a, and the contact resistance between the semiconductor layer 108 and the conductive layer 112b can all be reduced. Therefore, the on-state current of the transistor 100 can be increased. By increasing the on-state current, the operating voltage of the transistor 100 can be reduced. This can reduce the power consumption of the semiconductor device.

[0069] When an element that easily bonds with oxygen is used as the first element, the first element removes oxygen from the semiconductor layer 108 and exists in a state of being bonded to oxygen. Ｏ ) occurs. When an element that becomes stable when bonded with oxygen is used as the first element, the first element in the semiconductor layer 108 exists stably in an oxidized state and is therefore unlikely to be desorbed by heat or the like applied during the manufacturing process of the transistor 100, and the electrical resistance can be maintained low. For this reason, it is preferable to use an element whose oxide can exist in a solid state at least at the temperature during the manufacturing process as the first element. Specifically, preferred first elements include typical nonmetal elements other than hydrogen, typical metal elements, and transition elements (transition metals), and particularly preferred first elements include boron, phosphorus, magnesium, aluminum, and silicon.

[0070] For these reasons, it is preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements, and it is particularly preferable to use boron or phosphorus as one of the first elements.

[0071] Hydrogen is suitable as an impurity element because it has the function of generating oxygen vacancies and also the function of bonding to oxygen vacancies.

[0072] The impurity element can be preferably supplied by plasma ion doping or ion implantation. These methods allow for highly accurate control of the concentration profile in the depth direction by adjusting the ion acceleration energy and dose. By using ion implantation, which ionizes a source gas and supplies the ions after mass separation, ions of a specific mass can be supplied, thereby increasing the purity of the supplied impurity element. Alternatively, by using plasma ion doping, which supplies ions without mass separation, productivity can be increased.

[0073] When boron is used as the first element, the source gas may be, for example, BF ３ When phosphorus is used as the first element, the source gas may be, for example, PH ３ Furthermore, by mass-separating ions generated from these gases and supplying them, ions of specific masses can be supplied to the region 108Da and the region 108Db, which is more preferable.

[0074] By using both the first element and hydrogen as the impurity elements, the electrical resistance of each of the regions 108Da and 108Db can be easily reduced and the electrical resistance can be kept low.

[0075] When both the first element and hydrogen are supplied, a gas containing the first element and hydrogen (for example, PH ３ Gas and B ２ H ６ Alternatively, a mixed gas of a gas containing the first element and a gas containing hydrogen can be used as the source gas. By using a source gas containing the first element and hydrogen, ions generated from the source gas can be supplied without mass separation, which is preferable because it can increase productivity. For example, a source gas containing B ２ H ６By using the gas, boron and hydrogen can be supplied as impurity elements. ３ By using gas, phosphorus and hydrogen can be supplied as impurity elements.

[0076] The region 108Da has an impurity element concentration Na of 1×10 １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ Less than or equal to 5 × 10, more preferably １９ atoms / cm ３ 5x10 or more ２１ atoms / cm ３ For example, when boron is used as the first element, the region 108Da preferably includes a portion where the concentration Na of boron is in the above-mentioned range.

[0077] The region 108Db has an impurity element concentration Nb of 1×10 １９ atoms / cm ３ 1x10 or more ２３ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ 5x10 or more ２２ atoms / cm ３ Less than or equal to 5 × 10, more preferably １９ atoms / cm ３ 5x10 or more ２１ atoms / cm ３ For example, when boron is used as the first element, the region 108Db preferably includes a portion where the concentration Nb of boron is in the above-mentioned range.

[0078] When the region 108Da contains two or more impurity elements, it is preferable that the concentration of at least one of the impurity elements is in the above range. It is more preferable that the concentration of each impurity element is in the above range. The same applies to the region 108Db.

[0079] When the impurity elements are supplied to the regions 108Da and 108Db, the impurity elements may also be supplied to the channel formation region of the semiconductor layer 108. Alternatively, due to heat or the like applied during the manufacturing process, some of the impurity elements contained in the regions 108Da and 108Db may diffuse into the channel formation region.

[0080] The concentration Nc of the impurity element in the channel formation region of the semiconductor layer 108 is preferably low. The concentration Nc is preferably lower than the concentration Na of the impurity element in the region 108Da. The concentration Nc is preferably lower than the concentration Nb of the impurity element in the region 108Db. This prevents the carrier concentration in the channel formation region from increasing. A high carrier concentration in the channel formation region may shift the threshold voltage of the transistor, increasing the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V. For example, in the case of an n-channel transistor, a negative shift in the threshold voltage may increase the cutoff current. By preventing the carrier concentration in the channel formation region from increasing, the threshold voltage shift is prevented, resulting in a transistor with a small cutoff current. Therefore, a semiconductor device with low power consumption can be obtained.

[0081] The concentration Nc is 1×10 of the concentration Na. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４ Similarly, the concentration Nc is preferably 1×10 times or less of the concentration Nb. −１ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −２ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −３ It is preferable that the ratio is 1×10 or less, and more preferably 1×10 −４This allows a transistor to have both a small cutoff current and a large on-state current, thereby providing a semiconductor device that has both low power consumption and high performance.

[0082] The ratio Pa of the concentration Nc to the concentration Na can be expressed by Equation (2). The ratio Pb of the concentration Nc to the concentration Nb can be expressed by Equation (3). The ratios Pa and Pb are both dimensionless quantities and real numbers greater than 0.

[0083]

[0084] The ratio Pa and the ratio Pb are each 1×10 −１ Preferably, it is equal to or less than 1×10 −２ Preferably, it is equal to or less than 1×10 −３ Preferably, it is equal to or less than 1×10 −４ The following is preferable: This allows a transistor to have both a small cutoff current and a large on-state current, thereby providing a semiconductor device that has both low power consumption and high performance.

[0085] The concentrations of impurity elements (here, concentrations Na, Nb, and Nc) in the channel formation region, region 108Da, and region 108Db of the semiconductor layer 108 can be analyzed using, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectrometry (XPS, or ESCA). When using XPS analysis, the concentration distribution in the depth direction can be determined by combining ion sputtering from the front or back side of the sample with XPS analysis. As mentioned above, it is preferable that the concentration Nc in the channel formation region is low. Therefore, the concentration Nc may be difficult to quantify or may be below the detection limit.

[0086] In manufacturing the semiconductor device of one embodiment of the present invention, it is preferable to use a method in which the impurity element is more easily supplied to the source and drain regions of the semiconductor layer 108 than to the channel formation region. The impurity element is preferably supplied from a direction perpendicular or substantially perpendicular to the top surface of the substrate 102. In this case, the amount of the impurity element supplied to a region of the semiconductor layer 108 that is inclined with respect to the top surface of the substrate 102 is smaller than that supplied to a region that is parallel or substantially parallel to the top surface of the substrate 102. That is, the amount of the impurity element supplied to the source and drain regions of the semiconductor layer 108 is larger than that supplied to the channel formation region. Therefore, the electrical resistance of the source and drain regions can be preferentially reduced.

[0087] The insulating layer 110 can be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The insulating layer 110 preferably includes one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

[0088] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0089] The insulating layer 110 has a region in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 preferably contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, the portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 preferably contains oxygen. One or more of an oxide and an oxynitride can be suitably used for the portion of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108.

[0090] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 releases oxygen by heating. As a result, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, and oxygen vacancies (V Ｏ ), and V Ｏ H can be reduced.

[0091] The insulating layer 106, which functions as a gate insulating layer of the transistor 100, is provided to cover the openings 141 and 143. The insulating layer 106 is provided over the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. The insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110. The insulating layer 106 has a shape that follows the shapes of the top surface of the insulating layer 110, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the semiconductor layer 108, and the top surface of the conductive layer 112a.

[0092] 3B shows the thickness Ta of the insulating layer 106 at a portion in contact with the region 108Da, the thickness Tb of the portion in contact with the region 108Db, and the thickness Tc of the portion in contact with the channel formation region. The thicknesses Ta, Tb, and Tc are thicknesses in a direction perpendicular or substantially perpendicular to the surface on which the insulating layer 106 is formed. More specifically, the thickness Ta is the shortest distance between the top surface of the semiconductor layer 108 provided along the top surface of the conductive layer 112a and the top surface of the insulating layer 106. The thickness Tb is the shortest distance between the top surface of the semiconductor layer 108 provided along the top surface of the conductive layer 112b and the top surface of the insulating layer 106. The thickness Tc is the shortest distance between the side surface of the semiconductor layer 108 on the insulating layer 106 side, which is provided along the side surface of the insulating layer 110, and the side surface of the insulating layer 106 on the conductive layer 104 side. 3B shows a configuration in which the thicknesses Ta, Tb, and Tc are the same, but one embodiment of the present invention is not limited to this. Some or all of the thicknesses Ta, Tb, and Tc may be different.

[0093] As described above, part of the insulating layer 106 functions as a gate insulating layer. The thickness Tc of the portion of the insulating layer 106 in contact with the channel formation region is preferably 1 nm to 200 nm, more preferably 1 nm to 150 nm, and even more preferably 1 nm to 100 nm. For example, when the channel length is 100 nm to 500 nm, the thickness Tc is preferably 30 nm to 100 nm. Furthermore, for example, when the channel length is 10 nm to 100 nm, the thickness Tc is preferably 1 nm to 50 nm. Furthermore, for example, when the channel length is 1 nm to 10 nm, the thickness Tc is preferably 1 nm to 10 nm.

[0094] The conductive layer 104, which functions as a gate electrode of the transistor 100, is provided over the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106. The conductive layer 104 has a region overlapping with the semiconductor layer 108 with the insulating layer 106 interposed therebetween. The conductive layer 104 has a shape that follows the shape of the top surface of the insulating layer 106.

[0095] The transistor 100 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 108. Furthermore, since the bottom surface of the semiconductor layer 108 is in contact with the source electrode and the drain electrode, the transistor 100 can be referred to as a top-gate bottom-contact (TGBC) transistor. Furthermore, the source electrode and the drain electrode of the transistor 100 are located at different heights with respect to the surface of the substrate 102, which is the surface where the transistor 100 is formed, and a drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain current flows vertically or approximately vertically in the transistor 100. Therefore, the transistor according to one embodiment of the present invention can be referred to as a VFET.

[0096] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length shorter than the minimum exposure dimension of an exposure apparatus used to manufacture the transistor can be manufactured with high precision. Furthermore, the characteristic variation among the plurality of transistors 100 is also reduced. Therefore, the operation of the semiconductor device 10 can be stabilized and the reliability can be improved. Furthermore, the reduced characteristic variation of the transistors increases the degree of freedom in circuit design, and the operating voltage of the semiconductor device can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0097] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which the semiconductor layer is arranged in a planar shape.

[0098] The conductive layers 112a, 112b, and 104 can each function as wirings, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit including the transistor 100 and the wirings, the area occupied by the transistor 100 and the wirings can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be provided.

[0099] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-resolution display device can be obtained.Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (for example, one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

[0100] The insulating layer 110 preferably has a stacked structure. In Fig. 1B and other figures, an example is shown in which the insulating layer 110 includes an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layers 110a, 110b, and 110c can each be made of the materials listed in the description of the insulating layer 110.

[0101] A region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region. The insulating layer 110b preferably contains oxygen and is preferably made of one or more of the above-described oxides and oxynitrides. Specifically, the insulating layer 110b can be made of silicon oxide, silicon oxynitride, or both.

[0102] It is more preferable to use a material that releases oxygen when heated for the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 10, the insulating layer 110b releases oxygen, which allows oxygen to be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region of the semiconductor layer 108, oxygen vacancies (V Ｏ ) is repaired, and oxygen vacancies (V Ｏ ) can be reduced. Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0103] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by forming a film on the top surface of the insulating layer 110b by sputtering in an oxygen-containing atmosphere. The film may then be removed. Note that a method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 2.

[0104] The insulating layer 110b is preferably formed by a deposition method such as a sputtering method or a plasma-enhanced chemical vapor deposition (PECVD) method. In particular, by forming the insulating layer 110b by a method that does not use a gas containing hydrogen (e.g., hydrogen gas or ammonia gas) as a deposition gas, a film with an extremely low hydrogen content can be obtained. A sputtering method can be particularly preferably used for the insulating layer 110b. This can suppress the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100.

[0105] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. The insulating layer 110a and the insulating layer 110c preferably release small amounts of impurities (e.g., hydrogen and water) from themselves. Furthermore, the insulating layer 110a and the insulating layer 110c preferably are impermeable to substances (e.g., atoms, molecules, and ions). The insulating layer 110a and the insulating layer 110c can also be said to function as barrier films. Specifically, the insulating layer 110a and the insulating layer 110c preferably are impermeable to impurities. This can prevent impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation region. Therefore, a highly reliable transistor can be obtained, exhibiting favorable electrical characteristics.

[0106] The insulating layer 110a and the insulating layer 110c are preferably made of a material that is difficult for oxygen to permeate. This can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a through the insulating layer 110a. Similarly, it can prevent oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112b through the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108, reducing oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained. Furthermore, the conductive layer 112a can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which would prevent the electrical resistance of the conductive layer 112a from increasing. Similarly, the conductive layer 112b can be prevented from being oxidized by oxygen contained in the insulating layer 110b, which would prevent the electrical resistance of the conductive layer 112b from increasing. Therefore, a transistor with large on-state current can be obtained.

[0107] In this specification and the like, a barrier film refers to a film having barrier properties. The barrier properties refer to one or both of a function of making it difficult for a target substance to diffuse and thereby suppressing the substance from permeating the film (also referred to as low permeability) and a function of capturing or fixing the substance (also referred to as gettering). For example, an insulating layer having barrier properties can be referred to as a barrier insulating layer.

[0108] The insulating layer 110a and the insulating layer 110c, which function as barrier films, can each be made of, for example, one or more of an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, a nitride containing silicon, and a nitride oxide containing silicon. Specifically, the insulating layer 110a and the insulating layer 110c can each be made of, for example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Note that the insulating layer 110a and the insulating layer 110c can be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can be made of different materials.

[0109] By using an oxide or an oxynitride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) when the insulating layer 110c (or the insulating film that will become the insulating layer 110c) is formed.

[0110] In this specification and the like, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0111] The impurity element is preferably supplied to the semiconductor layer 108 through the insulating layer 106. Supplying the impurity element to the semiconductor layer 108 through the insulating layer 106 can reduce damage to the semiconductor layer 108 during supply. The supply of the impurity element will be described with reference to FIG. 4. The lower side of FIG. 4 shows a cross-sectional view of the insulating layer 106, the semiconductor layer 108, and their vicinity when the impurity element is supplied to the semiconductor layer 108 through the insulating layer 106. Here, an example will be described in which the impurity element is supplied from a direction perpendicular to the top surface of the substrate 102. Note that the cross-sectional view shown in FIG. 4 illustrates a configuration in which the surface of the insulating layer 106 (specifically, the top surface and side surface of the insulating layer 106) is parallel to the top surface and side surface of the semiconductor layer 108, which are surfaces on which the insulating layer 106 is formed.

[0112] FIG. 4 shows the thickness Td of the region of the insulating layer 106 provided along the side surface of the insulating layer 110 in the direction in which the impurity element is supplied (here, the direction perpendicular to the top surface of the substrate 102). For example, the thickness Td can be the thickness of the insulating layer 106 on a line extending from the midpoint between the top and bottom ends of the insulating layer 110b in the direction in which the impurity element is supplied (here, the direction perpendicular to the top surface of the substrate 102). Compared to the thickness Td, the thickness Ta of the region provided along the top surface of the conductive layer 112a and the thickness Tb of the region provided along the top surface of the conductive layer 112b are thinner. As a result, the amount of impurity element supplied to the region of the semiconductor layer 108 provided along the top surface of the conductive layer 112a or the top surface of the conductive layer 112b is larger than that of the region provided along the side surface of the insulating layer 110. In this way, the supply of the impurity element to the channel formation region of the semiconductor layer 108 can be suppressed, and the electrical resistance of the source and drain regions can be preferentially reduced.

[0113] The greater the thickness of the insulating layer 106, the greater the difference between the thickness Ta and the thickness Td and the difference between the thickness Tb and the thickness Td can be. Therefore, it is possible to suppress the supply of impurity elements to the channel formation region of the semiconductor layer 108, and to preferentially reduce the electrical resistance of the source and drain regions. On the other hand, in order to miniaturize transistors or fabricate transistors with extremely short channel lengths, it is preferable that the thickness Tc be small from the viewpoints of improving the on-current and suppressing the short channel effect.

[0114] When the impurity element is supplied to the semiconductor layer 108 through the insulating layer 106, the insulating layer 106 may also contain the impurity element. It is preferable that the regions 108Da and 108Db each have a portion with a higher concentration of the impurity element than the insulating layer 106, because the electrical resistance of the regions 108Da and 108Db can be reduced. For an analysis of the concentration of the impurity element in the insulating layer 106, the description of the analysis of the concentration of the impurity element in the semiconductor layer 108 can be referred to.

[0115] The insulating layer 106 preferably includes an insulating layer containing oxygen. When an element that easily bonds with oxygen is used as the impurity element, the impurity element exists in a state bonded to oxygen in the insulating layer 106 as in the semiconductor layer 108. When oxygen and the impurity element are bonded and stabilized, oxygen is less likely to be released from the region containing the impurity element even when heat is applied, thereby suppressing oxygen diffusion to other layers. This suppresses oxygen supply from the insulating layer 106 to the regions 108Da and 108Db while efficiently supplying oxygen to the channel formation region. Therefore, oxygen vacancies in the channel formation region can be reduced while preventing the electrical resistance of the regions 108Da and 108Db from increasing. As a result, a transistor with excellent electrical characteristics and high reliability can be realized.

[0116] For example, when boron is used as an impurity element, the boron contained in the regions 108Da, 108Db, and the insulating layer 106 may exist in a state of being bonded to oxygen. ２ O ３ In XPS analysis, the spectral peak due to the existence of elemental boron is not observed or the peak intensity is extremely small, almost to the background level.

[0117] When an impurity element is supplied to the semiconductor layer 108 through the insulating layer 106, the impurity element penetrates from the surface of the insulating layer 106, passes through the insulating layer 106, and then reaches the semiconductor layer 108 via the interface between the insulating layer 106 and the semiconductor layer 108. In this case, the thickness of the insulating layer 106 in the direction in which the impurity element is supplied can also be referred to as the depth D of the impurity element from the surface of the insulating layer 106 to the semiconductor layer 108. The depth D in each region of the insulating layer 106 is shown in the upper part of FIG. 4. In this figure, the horizontal axis indicates the position of the insulating layer 106 in a cross-sectional view, and the vertical axis indicates the depth D. The depth D in the region of the insulating layer 106 provided along the top surface of the conductive layer 112a corresponds to the thickness Ta of the insulating layer 106. The depth D in the region of the insulating layer 106 provided along the top surface of the conductive layer 112b corresponds to the thickness Tb of the insulating layer 106. The depth D in the region of the insulating layer 106 provided along the side surface of the insulating layer 110 corresponds to the thickness Td. Note that when the impurity element is supplied to the semiconductor layer 108 through the insulating layer 106, the insulating layer 106 and the semiconductor layer 108 may each be referred to as an implanted layer.

[0118] 4, the depth "Td" of the insulating layer 106 in the region provided along the side surface of the insulating layer 110 is deeper than the depth "Ta" in the region provided along the top surface of the conductive layer 112a, and is deeper than the depth "Tb" in the region provided along the top surface of the conductive layer 112b. In region A shown in the figure, the depth D takes a value between "Ta" and "Td," and in region B, the depth D takes a value between "Tb" and "Td." In other words, in regions A and B, the depth D is smaller than "Td."

[0119] When plasma ion doping or ion implantation is used to supply the impurity element, the concentration of the impurity element can be expressed by a Gaussian distribution. Specifically, the concentration N(x) of the impurity element at a depth x can be expressed by Equation (4). The concentration N(x) is a real number greater than 0.

[0120]

[0121] In the above formula (4), Q is the dose, m is the projected range (also referred to as Rp), and s is the standard deviation in the depth direction (also referred to as ΔRp). The dose Q, projected range m, and standard deviation s are all real numbers greater than 0. Note that the projected range m is the average depth at which ions stop during implantation, and the concentration of the impurity element is highest at depth "m."

[0122] Projected range m, standard deviation s (dispersion s ２ 5A shows the Gaussian distribution of the concentration of impurity elements at the depth D in the ion implantation region. In FIG. 5A, the horizontal axis indicates the depth D in a linear scale, and the vertical axis indicates the concentration N(D) in a logarithmic scale. As shown in FIG. 5A, the concentration N(m) is highest at the projected range m. ｍａｘ " he wrote.

[0123] The projected range m and standard deviation s can be calculated using, for example, simulation software. Examples of such simulation software include TRIM (Transport of Ion in Matter) and SRIM (Stopping and Range of Ions in Matter). These are software that simulate the ion implantation process using the Monte Carlo method. Simulation parameters can include the type of impurity element supplied (specifically, the type of ion), the composition and film density of the implanted layer, and the acceleration energy. For example, when the mass number of the impurity element supplied is large, the projected range m becomes small. Furthermore, since the stopping power in ion implantation differs depending on the type of element, the projected range m differs depending on the composition of the implanted layer. Furthermore, when the film density of the implanted layer is high, the stopping power increases and the projected range m becomes small. Therefore, the projected range m can be varied depending on the material used for the implanted layer (e.g., the insulating layer 106). The film density refers to the mass per unit volume. When the acceleration energy is high, the projected range m increases and the standard deviation s increases.

[0124] The concentration Na of the impurity element in the region 108Da is the concentration of the impurity element at depth "Ta" and can be expressed by formula (5). The concentration Nb of the impurity element in the region 108Db is the concentration of the impurity element at depth "Tb" and can be expressed by formula (6). The concentration Nc of the impurity element in the channel formation region is the concentration of the impurity element at depth "Td" and can be expressed by formula (7). The concentrations Na, Nb, and Nc are each a real number greater than 0.

[0125]

[0126] The ratio Pa of the impurity element concentration Nc in the channel formation region to the impurity element concentration Na in the region 108Da can be expressed by the following formula (8). The ratio Pb of the impurity element concentration Nc in the channel formation region to the impurity element concentration Nb in the region 108Db can be expressed by the following formula (9).

[0127]

[0128] As shown in Equation (8), the ratio Pa can be expressed by the thickness Ta, the thickness Td, the projected range m, and the standard deviation s. As shown in Equation (9), the ratio Pb can be expressed by the thickness Tb, the thickness Td, the projected range m, and the standard deviation s. It is preferable to set the thicknesses Ta, Tb, Td, the projected range m, and the standard deviation s so that the ratio Pa and the ratio Pab are each within the aforementioned range. As shown in Equation (8), the ratio Pa can be made smaller as the difference between the thickness Td and the thickness Ta increases. As shown in Equation (9), the ratio Pb can be made smaller as the difference between the thickness Td and the thickness Tb increases.

[0129] Here, if the angle θ is the angle between the side surface of the insulating layer 110 and the surface on which the insulating layer 110 is to be formed (here, the top surface of the conductive layer 112a), the thickness Td can be expressed by equation (10). When the angle θ is greater than 0 degrees and less than 90 degrees, cos θ is greater than 0 and less than 1. Therefore, the thickness Td is thicker than the thickness Tc. Furthermore, the smaller the angle θ, the thinner the thickness Td, and the larger the angle θ, the thicker the thickness Td. In other words, the larger the angle θ, the greater the difference between the thickness Td and the thickness Ta, and the smaller the ratio Pa. Similarly, the larger the angle θ, the greater the difference between the thickness Td and the thickness Tb, and the smaller the ratio Pb.

[0130]

[0131] The angle θ is preferably equal to or less than 90 degrees, and more preferably less than 90 degrees. By reducing the angle θ, the coverage of the layers provided over the insulating layer 110 (for example, the semiconductor layer 108, the insulating layer 106, and the conductive layer 104) can be improved, and defects such as discontinuities or voids in the layers can be suppressed.

[0132] 4 illustrates a configuration in which the top surface of the conductive layer 112a is parallel to the top surface of the substrate 102. In this case, the angle θ is the same as the angle between the side surface of the insulating layer 110 and the top surface of the substrate 102. The impurity element is preferably supplied from a direction perpendicular or approximately perpendicular to the top surface of the conductive layer 112a. That is, the impurity element is preferably supplied from a direction perpendicular or approximately perpendicular to the top surface of the substrate 102. Note that when the top surface of the conductive layer 112a and the top surface of the substrate 102 are not parallel in cross-sectional view, the impurity element is preferably supplied from a direction perpendicular or approximately perpendicular to the top surface of the conductive layer 112a.

[0133] When the thickness Td is expressed by the formula (10), the ratio Pa can be expressed by the formula (11), and the ratio Pb can be expressed by the formula (12).

[0134]

[0135] The ratio Pa can be expressed by the angle θ, the thickness Ta, the thickness Tc, the projected range m, and the standard deviation s, as shown in Equation (11). The ratio Pb can be expressed by the angle θ, the thickness Tb, the thickness Tc, the projected range m, and the standard deviation s, as shown in Equation (12). It is preferable to set the angle θ, the thickness Ta, the thickness Tb, the thickness Tc, the projected range m, and the standard deviation s so that the ratio Pa and the ratio Pab are each within the above-mentioned range. When the angle θ is greater than 0 degrees and less than 90 degrees, as shown in Equations (11) and (12), the ratio Pa and the ratio Pb can be reduced as the angle θ increases.

[0136] Here, it is assumed that the impurity element concentration N(D) is highest at the interface between the insulating layer 106 and the semiconductor layer 108 in a region provided along the top surface of the conductive layer 112a, and at the interface between the insulating layer 106 and the semiconductor layer 108 in a region provided along the top surface of the conductive layer 112b. Furthermore, it is assumed that the thicknesses Ta, Tb, and Tc are all the same. That is, when the projected range m is "Ta," the concentration Na at the depth "Ta" and the concentration Nb at the depth "Tb" are highest, as shown in FIG. 5B . Furthermore, when the thickness Td is expressed as "Ta / cos θ," the ratio Pa can be expressed by Equation (13), and the ratio Pb can be expressed by Equation (14).

[0137]

[0138] As shown in Equation (13) and Equation (14), the ratio Pa and the ratio Pb can be expressed by the angle θ, the thickness Ta, and the standard deviation s, respectively. It is preferable to set the angle θ, the thickness Ta, and the standard deviation s so that the ratio Pa and the ratio Pab are each within the above-mentioned range. Note that when the thickness Ta and the thickness Tb are different from each other, the ratio Pb can be calculated by using Equation (12).

[0139] The projected range m and standard deviation s are determined by selecting the acceleration energy according to the type of impurity element supplied, the composition, film density, and thickness of the implanted layer, and the standard deviation s can be expressed by Equation (15). α is the ratio of the standard deviation s to the projected range m, and is a dimensionless quantity. α is a real number greater than 0. The ratio α is determined by selecting the acceleration energy according to the type of impurity element supplied, the composition, film density, and thickness of the implanted layer. Using the ratio α, the ratio Pa can be expressed by Equation (16), and the ratio Pb can be expressed by Equation (17).

[0140]

[0141] As shown in Equations (16) and (17), the ratios Pa and Pb can be expressed by the angle θ and the ratio α of the standard deviation s to the projected range m, respectively. It is preferable to set the angle θ according to the ratio α so that the ratios Pa and Pb are within the aforementioned ranges. As shown in Equations (16) and (17), the larger the ratio α, the larger the angle θ, which can be used to reduce the ratio Pa. This allows a transistor to have both a small cutoff current and a large on-current. Therefore, a semiconductor device can be obtained that achieves both low power consumption and high performance.

[0142] The relationship between the angle θ and the ratio Pa is shown in Fig. 6. In Fig. 6, the horizontal axis represents the angle θ, and the vertical axis represents the ratio Pa. Fig. 6 shows the ratio Pa when the ratio α is changed to 0.25, 0.30, 0.33, 0.35, 0.38, 0.40, 0.45, and 0.50.

[0143] As shown in FIG. 6 , when the ratio α is 0.25 or less, the angle θ is set to 59 degrees or more, when the ratio α is 0.30 or less, the angle θ is set to 62 degrees or more, when the ratio α is 0.33 or less, the angle θ is set to 64 degrees or more, when the ratio α is 0.35 or less, the angle θ is set to 65 degrees or more, when the ratio α is 0.38 or less, the angle θ is set to 66 degrees or more, when the ratio α is 0.40 or less, the angle θ is set to 67 degrees or more, when the ratio α is 0.45 or less, the angle θ is set to 69 degrees or more, and when the ratio α is 0.50 or less, the angle θ is set to 70 degrees or more, thereby making the ratio Pa 1×10 −３Furthermore, when the ratio α is 0.25 or less, the angle θ is set to 62 degrees or more, when the ratio α is 0.30 or less, the angle θ is set to 65 degrees or more, when the ratio α is 0.33 or less, the angle θ is set to 66 degrees or more, when the ratio α is 0.35 or less, the angle θ is set to 67 degrees or more, when the ratio α is 0.38 or less, the angle θ is set to 68 degrees or more, when the ratio α is 0.40 or less, the angle θ is set to 69 degrees or more, when the ratio α is 0.45 or less, the angle θ is set to 71 degrees or more, and when the ratio α is 0.50 or less, the angle θ is set to 72 degrees or more, whereby the ratio Pa can be reduced to 1×10 −４ It can be, and more preferably, the following:

[0144] As described above, the larger the ratio α, the smaller the ratio Pa and the ratio Pb can be made by increasing the angle θ.

[0145] When the thickness Ta and the thickness Tb are the same or approximately the same, the ratio Pa and the ratio Pb are the same or approximately the same, so the ratio Pa in FIG. 6 and the above description can be replaced with the ratio Pb.

[0146] Boron (specifically, １１ B ＋ ions), and the insulating layer 106 has a film density of 2.23 g / cm ３ Silicon oxide (SiO ２ A more specific explanation will be given below using an example of a configuration in which a 1000 nm layer is applied. In a simulation using TRIM with this configuration, when the acceleration energy is 20 keV, the projected range m is approximately 83.4 nm and the standard deviation s is approximately 32.0 nm (ratio α is approximately 0.38). When the ratio α is set to 0.38, from the above-mentioned formulas (16) and (17), when the angle θ is 65 degrees, the ratios Pa and Pb are each 1.6×10 −３ When the angle θ is 66 degrees, the ratios Pa and Pb are 6.3 × 10 −４ When the angle θ is 68 degrees, the ratios Pa and Pb are 6.4 × 10 −５ Therefore, by making the angle θ 66 degrees or more, the ratio Pa and the ratio Pb can be made 1×10 −３ By setting the angle θ to 68 degrees or more, the ratio Pa and the ratio Pb can be set to 1×10 −４ It can be as follows:

[0147] As described above, by increasing the angle θ, it is possible to reduce the ratios Pa and Pb. Furthermore, by increasing the angle θ depending on the impurity element used and the film density of the insulating layer 106, it is possible to reduce the ratios Pa and Pb.

[0148] Here, the example has been described in which the thicknesses Ta, Tb, and Tc of the insulating layer 106 are the same, but one embodiment of the present invention is not limited to this. The thicknesses Ta, Tb, and Tc may be partly or entirely different from each other. FIG. 7 shows a configuration in which the thickness Tc is thinner than the thicknesses Ta and Tb.

[0149] The thickness Tc can be expressed by equation (18) using the thickness Ta. β is the ratio of the thickness Tc to the thickness Ta and is a dimensionless quantity. The ratio β is a real number greater than 0. When the thickness Ta and the thickness Tc are the same, the ratio β is 1.

[0150]

[0151] A configuration in which the thickness Tc is different from the thickness Ta, i.e., the ratio β in Equation (18) is not 1, will be described. The thickness Tc of the insulating layer 106 in the region provided along the side surface of the insulating layer 110 may be thinner than the thickness Ta of the insulating layer 106 in the region provided along the top surface of the conductive layer 112a. In this case, the ratio β is a real number greater than 0 and less than 1. On the other hand, when the thickness Tc is thicker than the thickness Ta, the ratio β is a real number greater than 1. For example, when the insulating layer 106 is formed by PECVD or sputtering, the thickness Tc may be thinner than the thickness Ta, i.e., the ratio β may be less than 1. When the insulating layer 106 is formed by atomic layer deposition (ALD), the ratio β can be closer to 1.

[0152] When the thickness Tc is expressed by the formula (18), the thickness Td can be expressed by the formula (19). Furthermore, the ratio Pa shown in the formula (11) can be expressed by the formula (20). The ratio Pb shown in the formula (12) can be expressed by the formula (21).

[0153]

[0154] As shown in Equation (20), the ratio Pa can be expressed by the ratio β, the angle θ, the thickness Ta, the projected range m, and the standard deviation s. As shown in Equation (21), the ratio Pb can be expressed by the ratio β, the thickness Ta, the thickness Tb, the projected range m, and the standard deviation s. It is preferable to set the angle θ, the thickness Ta, the thickness Tb, the projected range m, and the standard deviation s according to the ratio β so that the ratio Pa and the ratio Pab are each within the aforementioned range. As shown in Equations (20) and (21), the smaller the ratio β, the larger the angle θ, which can reduce the ratio Pa. This allows for a transistor that achieves both a small cutoff current and a large on-current. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.

[0155] It is assumed that the concentration N of the impurity element is highest at the interface between the insulating layer 106 and the semiconductor layer 108. Also, it is assumed that the thickness Ta and the thickness Tb are the same. In other words, if the projected range m is "Ta", the ratio Pa can be expressed by formula (22), and the ratio Pb can be expressed by formula (23).

[0156]

[0157] As shown in Equation (22) and Equation (23), the ratios Pa and Pb can be expressed by the ratio β, the thickness Ta, the angle θ, and the standard deviation s, respectively. It is preferable to set the angle θ, the thickness Ta, and the standard deviation s according to the ratio β so that the ratios Pa and Pab are each within the aforementioned ranges.

[0158] As shown in Equation (15), when the standard deviation s is expressed using the projected range m and the ratio α, and the projected range m is “Ta”, the ratio Pa can be expressed by Equation (24), and the ratio Pb can be expressed by Equation (25).

[0159]

[0160] As shown in Equation (24) and Equation (25), the ratios Pa and Pb can be expressed by the ratio α of the standard deviation s to the projected range m, the ratio β of the thickness Tc to the thickness Ta, and the angle θ, respectively. It is preferable to set the angle θ according to the ratio α and the ratio β so that the ratios Pa and Pb are within the aforementioned ranges. Note that the ratio Pa when β is set to 1 in Equation (24) is the aforementioned Equation (16). The ratio Pb when β is set to 1 in Equation (25) is the aforementioned Equation (17).

[0161] The relationship between the angle θ and the ratio Pa is shown in Figures 8A and 8B. Figure 8A shows the relationship between the angle θ and the ratio Pa when the ratio β is 0.85, and Figure 8B shows the relationship between the angle θ and the ratio Pa when the ratio β is 0.75. In Figures 8A and 8B, the horizontal axis represents the angle θ, and the vertical axis represents the ratio Pa. Figures 8A and 8B show the ratio Pa when the ratio α is changed to 0.25, 0.30, 0.33, 0.35, 0.38, 0.40, 0.45, and 0.50, respectively. Note that Figure 6 shows the relationship between the angle θ and the ratio Pa when the ratio β is 1.

[0162] As shown in FIG. 8A , when the ratio β is 0.85, the angle θ is set to 64 degrees or more when the ratio α is 0.25 or less, the angle θ is set to 67 degrees or more when the ratio α is 0.30 or less, the angle θ is set to 68 degrees or more when the ratio α is 0.33 or less, the angle θ is set to 69 degrees or more when the ratio α is 0.35 or less, the angle θ is set to 70 degrees or more when the ratio α is 0.38 or less, the angle θ is set to 71 degrees or more when the ratio α is 0.40 or less, the angle θ is set to 72 degrees or more when the ratio α is 0.45 or less, and the angle θ is set to 73 degrees or more when the ratio α is 0.50 or less, thereby making the ratio Pa 1×10 −３ Furthermore, when the ratio α is 0.25 or less, the angle θ is set to 66 degrees or more, when the ratio α is 0.30 or less, the angle θ is set to 69 degrees or more, when the ratio α is 0.33 or less, the angle θ is set to 70 degrees or more, when the ratio α is 0.35 or less, the angle θ is set to 71 degrees or more, when the ratio α is 0.38 or less, the angle θ is set to 72 degrees or more, when the ratio α is 0.40 or less, the angle θ is set to 72 degrees or more, when the ratio α is 0.45 or less, the angle θ is set to 74 degrees or more, and when the ratio α is 0.50 or less, the angle θ is set to 75 degrees or more, whereby the ratio Pa can be reduced to 1×10 −４ It can be, and more preferably, the following:

[0163] As shown in FIG. 8B , when the ratio β is 0.75, if the ratio α is 0.25 or less, the angle θ is 68 degrees or more; if the ratio α is 0.30 or less, the angle θ is 70 degrees or more; if the ratio α is 0.33 or less, the angle θ is 71 degrees or more; if the ratio α is 0.35 or less, the angle θ is 71 degrees or more; if the ratio α is 0.38 or less, the angle θ is 72 degrees or more; if the ratio α is 0.40 or less, the angle θ is 73 degrees or more; if the ratio α is 0.45 or less, the angle θ is 74 degrees or more; and if the ratio α is 0.50 or less, the angle θ is 75 degrees or more, thereby making the ratio Pa 1×10 −３ Furthermore, when the ratio α is 0.25 or less, the angle θ is set to 69 degrees or more, when the ratio α is 0.30 or less, the angle θ is set to 71 degrees or more, when the ratio α is 0.33 or less, the angle θ is set to 72 degrees or more, when the ratio α is 0.35 or less, the angle θ is set to 73 degrees or more, when the ratio α is 0.38 or less, the angle θ is set to 74 degrees or more, when the ratio α is 0.40 or less, the angle θ is set to 74 degrees or more, when the ratio α is 0.45 or less, the angle θ is set to 76 degrees or more, and when the ratio α is 0.50 or less, the angle θ is set to 77 degrees or more, whereby the ratio Pa can be reduced to 1×10 −４ It can be, and more preferably, the following:

[0164] As described above, the larger the ratio α, the larger the angle θ, which allows the ratio Pa to be reduced. This allows a transistor that achieves both a small cutoff current and a large on-current. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.

[0165] When the thickness Ta and the thickness Tb are the same or approximately the same, the ratio Pa and the ratio Pb are the same or approximately the same, so the ratio Pa in Figures 8A and 8B and the above description can be replaced with the ratio Pb.

[0166] As described above, it is preferable that the difference between the thickness Td and the thickness Ta of the insulating layer 106 is large. It is preferable that the difference between the thickness Td and the thickness Tb of the insulating layer 106 is large. In other words, it is preferable that the ratio of the thickness Td to the thickness Ta is large. It is preferable that the ratio of the thickness Td to the thickness Tb is large.

[0167] The thickness Td can be expressed by equation (26) using the thickness Ta. γ is the ratio of the thickness Td to the thickness Ta and is a dimensionless quantity. The ratio γ is a real number greater than 0. The ratio γ corresponds to "β / cos θ" in equation (19). Using the ratio γ, the ratio Pa can be expressed by equation (27). If the thickness Tb and the thickness Ta of the insulating layer 106 are the same, the ratio Pb can be expressed by equation (28).

[0168]

[0169] As shown in Equations (27) and (28), the ratios Pa and Pb can be expressed by the ratio α of the standard deviation s to the projected range m and the ratio γ of the thickness Td to the thickness Ta of the insulating layer 106, respectively. It is preferable to set the ratio β according to the ratio α so that the ratios Pa and Pb are within the aforementioned ranges. As shown in Equations (27) and (28), the larger the ratio γ, the smaller the ratios Pa and Pb can be. In other words, the larger the ratio of the thickness Td to the thickness Ta, the smaller the ratios Pa and Pb can be.

[0170] The relationship between the ratio γ and the ratio Pa is shown in Fig. 9. In Fig. 9, the horizontal axis represents the angle θ, and the vertical axis represents the ratio Pa. Fig. 9 shows the ratio Pa when the ratio α is changed to 0.25, 0.30, 0.33, 0.35, 0.38, 0.40, 0.45, and 0.50.

[0171] As shown in FIG. 9 , when the ratio α is 0.25 or less, the ratio γ is set to 2.0 or more, when the ratio α is 0.30 or less, the ratio γ is set to 2.2 or more, when the ratio α is 0.33 or less, the ratio γ is set to 2.3 or more, when the ratio α is 0.35 or less, the ratio γ is set to 2.4 or more, when the ratio α is 0.38 or less, the ratio γ is set to 2.5 or more, when the ratio α is 0.40 or less, the ratio γ is set to 2.5 or more, when the ratio α is 0.45 or less, the ratio γ is set to 2.7 or more, and when the ratio α is 0.50 or less, the ratio γ is set to 2.9 or more, thereby making the ratio Pa 1×10 −３Furthermore, when the ratio α is 0.25 or less, the ratio γ can be set to 2.1 or more, when the ratio α is 0.30 or less, the ratio γ can be set to 2.3 or more, when the ratio α is 0.33 or less, the ratio γ can be set to 2.5 or more, when the ratio α is 0.35 or less, the ratio γ can be set to 2.6 or more, when the ratio α is 0.38 or less, the ratio γ can be set to 2.7 or more, when the ratio α is 0.40 or less, the ratio γ can be set to 2.8 or more, when the ratio α is 0.45 or less, the ratio γ can be set to 3.0 or more, and when the ratio α is 0.50 or less, the ratio γ can be set to 3.2 or more, thereby making the ratio Pa 1×10 −４ It can be, and more preferably, the following:

[0172] As described above, the larger the ratio α, the larger the ratio γ, thereby making it possible to reduce the ratio Pa. This allows a transistor that achieves both a small cutoff current and a large on-current. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.

[0173] When the thickness Ta and the thickness Tb are the same or approximately the same, the ratio Pa and the ratio Pb are the same or approximately the same, so the ratio Pa in FIG. 9 and the above description can be replaced with the ratio Pb.

[0174] Boron (specifically, １１ B ＋ ions), and the insulating layer 106 has a film density of 2.23 g / cm ３ Silicon oxide (SiO ２ A more specific explanation will be given below using an example of a configuration in which a γ layer is applied. In a simulation using TRIM with this configuration, when the acceleration energy is 20 keV, the projected range m is approximately 83.4 nm and the standard deviation s is approximately 32.0 nm (ratio α is approximately 0.38). When the ratio α is set to 0.38, from the above-mentioned formulas (27) and (28), the ratio γ is 2.4, and the ratios Pa and Pb are each 1.1 × 10 −３ The ratio γ is 2.5, and the ratios Pa and Pb are 4.1 × 10 −４ The ratio γ is 2.6, and the ratios Pa and Pb are 1.4 × 10 −４ The ratio γ is 2.7, and the ratios Pa and Pb are 4.5×10 −５Therefore, by setting the ratio γ to 2.5 or more, the ratios Pa and Pb can be increased to 1×10 −３ By making the ratio γ equal to or greater than 2.7 degrees, the ratio Pa and the ratio Pb can be made equal to or less than 1×10 −４ It can be as follows:

[0175] As described above, by increasing the ratio γ, it is possible to reduce the ratios Pa and Pb. Furthermore, by increasing the ratio γ depending on the impurity element used and the film density of the insulating layer 106, it is possible to reduce the ratios Pa and Pb.

[0176] As described above, it is preferable that the amount of impurity element supplied to the channel formation region is small. More specifically, it is preferable that the amount of impurity element supplied to the region of the semiconductor layer 108 that is in contact with the insulating layer 110b is small. Therefore, in a cross-sectional view, it is more preferable that the thickness Te of the insulating layer 106 on a straight line extending from the end of the top surface of the insulating layer 110b in the direction in which the impurity element is supplied (here, the direction perpendicular to the top surface of the substrate 102) is large. It is more preferable that the thickness Te is at least the same as or approximately the same as the thickness Td.

[0177] 4 and 7 show a thickness Ha of a region of the semiconductor layer 108 provided along the top surface of the conductive layer 112a, a thickness Hb of a region of the semiconductor layer 108 provided along the top surface of the conductive layer 112b, and a thickness Hc of a region of the semiconductor layer 108 provided along the side surface of the insulating layer 110. The thicknesses Ha, Hb, and Hc are thicknesses in a direction perpendicular or substantially perpendicular to the surface on which the semiconductor layer 108 is formed. More specifically, the thickness Ha is the shortest distance between the top surface of the conductive layer 112a and the top surface of the semiconductor layer 108. The thickness Hb is the shortest distance between the top surface of the conductive layer 112b and the top surface of the semiconductor layer 108. The thickness Hc is the shortest distance between the side surface of the insulating layer 110 and the side surface of the semiconductor layer 108 on the insulating layer 106 side. Although the thicknesses Ha, Hb, and Hc are the same in FIGS. 4 and 7, one embodiment of the present invention is not limited thereto. Some or all of the thicknesses Ha, Hb, and Hc may be different from each other.

[0178] As shown in Equation (29), K is the sum of the thickness Tb of the insulating layer 106 provided along the top surface of the insulating layer 110b, the thickness Hb of the semiconductor layer 108, the thickness T112b of the conductive layer 112b, and the thickness T110c of the insulating layer 110c. The sum K is the distance between the top surface of the insulating layer 106 provided along the top surface of the conductive layer 112b and the top surface of the insulating layer 110b in the direction in which the impurity element is supplied (here, the direction perpendicular to the top surface of the substrate 102). If the sum K is small, the thickness Te of the insulating layer 106 may be thinner than the thickness Td (see region B in FIG. 4 or FIG. 7 ). Therefore, it is preferable that the sum K is large. Furthermore, as shown in Equation (30), L is the sum of the thickness Hd of the semiconductor layer 108 and the thickness Td of the insulating layer 106. As shown in Equation (31), the sum K is preferably equal to or greater than the sum L. This allows the thickness Te of the insulating layer 106 to be large.

[0179]

[0180] It is preferable to set the thicknesses Tb and Td of the insulating layer 106, the thicknesses Hb and Hd of the semiconductor layer 108, the thickness T112b of the conductive layer 112b, and the thickness T110c of the insulating layer 110c so as to satisfy the formula (31). For example, it is preferable to increase one or both of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c so as to satisfy the formula (31).

[0181] Here, if the thicknesses Tb and Tc of the insulating layer 106 are the same, the thickness Td can be expressed by formula (32). If the thicknesses Hb and Hc of the semiconductor layer 108 are the same, the thickness Hd can be expressed by formula (33). Furthermore, the sum L can be expressed by formula (34).

[0182]

[0183] When the formula (31) is expanded using the formula (29) and the formula (34), the formula (35) is obtained.

[0184]

[0185] As shown in Equation (35), when the angle θ is greater than 0 degrees and less than 90 degrees, it is preferable to increase the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c as the angle θ increases. Specifically, it is preferable to increase one or both of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c as the angle θ increases.

[0186] For example, when the angle θ is 60 degrees or less, the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is more preferably equal to or greater than the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108. When the angle θ is 65 degrees or less, the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is more preferably equal to or greater than 1.4 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108. When the angle θ is 70 degrees or less, the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is more preferably equal to or greater than 2.0 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108. When the angle θ is 75 degrees or less, the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is more preferably at least 2.9 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108. When the angle θ is 80 degrees or less, the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is more preferably at least 4.8 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.

[0187] Note that although the example described here is a structure in which the thicknesses Tb and Tc of the insulating layer 106 are the same and the thicknesses Hb and Hc of the semiconductor layer 108 are the same, one embodiment of the present invention is not limited to this. A structure in which the thicknesses Tb and Tc are different from each other may also be used. A structure in which the thicknesses Hb and Hc are different from each other may also be used. Even in such cases, it is preferable to set the thickness of each layer so as to satisfy Equation (31).

[0188] An example will be described in which the thickness Tc of the insulating layer 106 is 0.85 times the thickness Tb and the thickness Hc of the semiconductor layer 108 is 0.85 times the thickness Hb. In this configuration, the sum L can be expressed as "0.85 × (Tb + Hb) / cos θ," which can be applied to equation (31). For example, when the angle θ is 60 degrees or less, the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is preferably at least 0.7 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108. When the angle θ is 65 degrees or less, the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is preferably at least 1.1 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108. When the angle θ is 70 degrees or less, the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is more preferably at least 1.5 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108. When the angle θ is 75 degrees or less, the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is more preferably at least 2.3 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108. When the angle θ is 80 degrees or less, the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is more preferably at least 3.9 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.

[0189] As described above, it is preferable that the ratios Pa and Pb of the impurity element concentrations are small. The angle θ can be determined so that the ratios Pa and Pb are within the aforementioned ranges. Furthermore, it is more preferable to determine the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c at the angle θ so as to satisfy formula (31). This allows the concentration of the impurity elements in the entire channel formation region to be low.

[0190] The regions 108Da and 108Db can each have a configuration including a first element and a second element as an impurity element. The second element is different from the first element. The second element can be one or more of the elements that can be used as the first element. The second element preferably has a larger mass number than the first element. The first element preferably easily bonds with oxygen. For example, boron or phosphorus can be used as the first element, and argon, krypton, or xenon can be used as the second element.

[0191] After the second element is supplied to the semiconductor layer 108, the first element can be supplied to the semiconductor layer 108. When the mass number of the supplied element is large, the number of metal-oxygen bonds broken in the metal oxide contained in the semiconductor layer 108 increases. Furthermore, due to the breaking of the metal-oxygen bonds, oxygen vacancies (V Ｏ ) occurs. By supplying the first element after supplying the second element having a larger mass number to break more bonds between the metal and oxygen, the first element can efficiently bond with oxygen. Therefore, the electrical resistance of the regions 108Da and 108Db can be efficiently reduced.

[0192] When the amount of the second element supplied to the channel forming region increases, oxygen vacancies (V Ｏ ) occurs, and V Ｏ There is a risk that H will increase, resulting in a high carrier concentration. The concentration of the second element in the channel formation region is preferably lower than the concentration of the second element in the region 108Da. Similarly, the concentration of the second element in the channel formation region is preferably lower than the concentration of the second element in the region 108Db.

[0193] The second element is preferably supplied to the semiconductor layer 108 through the insulating layer 106. It is preferable that the second element is supplied to the semiconductor layer 108 through the insulating layer 106, and then the first element is supplied to the semiconductor layer 108 through the insulating layer 106. When the second element is supplied to the semiconductor layer 108 through the insulating layer 106, the insulating layer 106 may also contain the second impurity element.

[0194] The second element is preferably supplied from a direction perpendicular or approximately perpendicular to the top surface of the substrate 102. The second element can be supplied by the same method as that used to supply the first element. For example, plasma ion doping or ion implantation can be suitably used to supply the second element. When plasma ion doping or ion implantation is used to supply the first and second elements, the amount of the second element supplied to the channel formation region can be reduced by setting the angle θ of the insulating layer 110 or the thickness Td of the insulating layer 106 within the aforementioned range, which is preferable. Because the second element has a larger mass number than the first element, it is more preferable that the acceleration energy used to supply the second element be higher than the acceleration energy used to supply the first element. This increases the amount of the second element supplied to the regions 108Da and 108Db, thereby efficiently reducing the electrical resistance of the regions 108Da and 108Db.

[0195] Alternatively, the first element and the second element can be supplied in the same process. For example, the first element and the second element can be supplied to the semiconductor layer 108 using a source gas containing the first element and the second element. A plasma ion doping method can be suitably used for supplying the elements. At this time, it is preferable to set the acceleration energy so that the ratios Pa and Pb of the concentrations of the first element fall within the above-mentioned ranges. Furthermore, a mixed gas of a gas containing the first element and a gas containing the second element can be used as the source gas. For example, when the first element is boron and the second element is argon, BF ３ The source gas is not limited to a mixed gas, and a gas containing the first element and the second element can also be used.

[0196] 1B and the like show an example in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 cover the openings 141 and 143; however, one embodiment of the present invention is not limited to this. A step may be formed between the insulating layer 110, the conductive layer 112b, and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 may be provided along the step.

[0197] [Semiconductor Layer 108] Metal oxides that can be used for the semiconductor layer 108 will be specifically described. Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium or zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have a high bond energy with oxygen and an ionic radius similar to that of indium or zinc. Furthermore, tin is more preferred because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may also include metalloid elements.

[0198] The semiconductor layer 108 may be formed of, for example, indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium tungsten oxide (In—W oxide, also referred to as IWO), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide), , AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO), etc. Alternatively, indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0199] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide. Therefore, the presence of a metal element having a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0200] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0201] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When a plurality of elements are contained as the element M, the sum of the ratios of the number of atoms of the element M to the sum of the numbers of atoms of all contained metal elements can be referred to as the content of the element M.

[0202] By increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0203] By increasing the content of element M in the metal oxide, it is possible to obtain a metal oxide with a large band gap. Ｏ ) is suppressed, the formation of oxygen vacancies (V Ｏ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, resulting in a normally-off transistor. Furthermore, the transistor can have a small off-state current. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, resulting in improved reliability.

[0204] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0205] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M Examples of suitable compositions include In:M:Zn = 5:1:9, In:M:Zn = 6:1:6, In:M:Zn = 10:1:1, In:M:Zn = 10:1:3, In:M:Zn = 10:1:4, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, and compositions in the vicinity thereof. Note that a composition in the vicinity includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-state current or field-effect mobility of the transistor.

[0206] The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of the element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, oxygen deficiency (V Ｏ ) can be suppressed.

[0207] When the element M contains a plurality of elements, the atomic ratio of the element M can be the sum of the atomic ratios of these elements.

[0208] By using a material with a high indium content for the semiconductor layer 108, the on-state current or the field-effect mobility of the transistor can be increased. Ｏ ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, even more preferably 0.1% to 10%, even more preferably 0.1% to 8%, even more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows for a transistor with excellent electrical characteristics. For example, it is preferable to use a metal oxide having a ratio of In:M:Zn=40:1:10 or a metal oxide having a similar ratio. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides having a ratio of In:Sn:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used. Alternatively, metal oxides having a ratio of In:Al:Zn=40:1:10 or a metal oxide having a similar ratio can be suitably used.

[0209] Here, when a polycrystalline metal oxide is used for the semiconductor layer 108, crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Furthermore, when a polycrystalline metal oxide is used for the semiconductor layer 108, the surface of the semiconductor layer 108 may become uneven. This increases the step on the surface where a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 is to be formed, which may cause defects such as discontinuities or voids in the layer. When a metal oxide having a composition that easily results in a polycrystalline structure is used for the semiconductor layer 108, it is preferable to include an element that inhibits crystallization. This prevents the semiconductor layer 108 from becoming polycrystalline, resulting in a transistor with a large on-state current. Furthermore, the coverage of a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 can be improved, which may prevent defects such as discontinuities or voids in the layer.

[0210] For example, compared with indium tin oxide (ITO), indium tin oxide (ITSO) containing silicon is less likely to form a polycrystalline structure and is therefore suitable for use in the semiconductor layer 108. When ITSO is used, the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1 atomic % to 20 atomic %, more preferably 3 atomic % to 20 atomic %, further preferably 3 atomic % to 15 atomic %, and further preferably 5 atomic % to 15 atomic %. Specifically, metal oxides having an atomic ratio of metal elements of In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, or similar ratios thereto can be suitably used. When indium tin oxide (ITSO) containing silicon is used for the semiconductor layer 108, it is preferable that ITSO have crystallinity. Note that the semiconductor layer 108 may have an amorphous region or may be amorphous.

[0211] A metal oxide not containing element M can be used for the semiconductor layer 108. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions in the vicinity thereof. Furthermore, it is more preferable that the atomic ratio of In is equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of the transistor can be increased.

[0212] The composition of the semiconductor layer 108 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.

[0213] The metal oxide can be preferably formed by sputtering or ALD. When the metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may be reduced to about 50% of that of the sputtering target.

[0214] It is preferable to use a crystalline metal oxide for the semiconductor layer 108. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide, the density of defect states in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0215] The semiconductor layer 108 is preferably formed using a CAAC-OS or an nc-OS.

[0216] The CAAC-OS has a plurality of layered crystals. The c-axes of the crystals are oriented in the normal direction to the surface where the semiconductor layer 108 is formed. The semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the surface where the semiconductor layer 108 is formed. For example, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the top surface of the conductive layer 112b in a region in contact with the top surface of the conductive layer 112b and layered crystals parallel or approximately parallel to the side surface of the conductive layer 112b in a region in contact with the side surface of the conductive layer 112b. In particular, the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface where the semiconductor layer 108 is formed, in the opening 141. With this structure, the layered crystals of the semiconductor layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, thereby enabling the transistor to have a large on-state current.

[0217] By using a metal oxide with high crystallinity for the channel formation region, the density of defect states in the channel formation region can be reduced, while by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

[0218] The higher the substrate temperature during metal oxide formation, the higher the crystallinity of the resulting metal oxide. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for formation or the oxygen partial pressure in the processing chamber, the higher the crystallinity of the resulting metal oxide.

[0219] The crystallinity of the semiconductor layer 108 can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

[0220] When a metal oxide is used for the semiconductor layer 108, V Ｏ It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic. Ｏ To obtain a metal oxide with a sufficiently reduced amount of H, impurities such as water and hydrogen in the metal oxide must be removed (sometimes referred to as dehydration or dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V Ｏ It is important to repair the Ｏ By using a metal oxide in which impurities such as H are sufficiently reduced in a channel formation region of a transistor, stable electrical characteristics can be obtained. Ｏ ) is sometimes referred to as oxygenation treatment.

[0221] When a metal oxide is used for the semiconductor layer 108, the carrier concentration in the channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm−３ It is more preferable that the carrier concentration in the channel formation region is less than 1×10. −９ cm −３ It can be said that:

[0222] A region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of a source region and a drain region of the transistor 100, and a region of the semiconductor layer 108 in contact with the conductive layer 112b functions as the other. The source region and the drain region have lower electrical resistance than the channel formation region. The source region and the drain region can also be said to have a higher carrier concentration or a higher oxygen defect density than the channel formation region.

[0223] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0224] The semiconductor layer 108 may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0225] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0226] The semiconductor layer 108 can have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 108 can have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the two or more metal oxide layers included in the semiconductor layer 108 have the same or substantially the same composition, the boundary (interface) between these metal oxide layers may not be clearly identified.

[0227] [Insulating Layer 110] As described above, the insulating layer 110 preferably has a stacked-layer structure. The insulating layer 110b has a function of supplying oxygen to a channel formation region. The insulating layers 110a and 110c function as barrier films.

[0228] The thickness T110a of the insulating layer 110a is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, even more preferably 10 nm to 300 nm, even more preferably 20 nm to 300 nm, even more preferably 50 nm to 300 nm, even more preferably 100 nm to 300 nm, even more preferably 100 nm to 250 nm, even more preferably 150 nm to 250 nm. As shown in FIG. 3B , the thickness T110a can be the shortest distance between the surface on which the insulating layer 110a is formed (here, the upper surface of the conductive layer 112a) and the upper surface of the insulating layer 110a in a cross-sectional view.

[0229] If the thickness T110a of the insulating layer 110a is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a side through the insulating layer 110a, and the amount of oxygen supplied to the channel formation region may decrease. On the other hand, if the thickness T110a is large, the amount of impurities released from the insulating layer 110a may increase, and the amount of impurities diffusing into the channel formation region may increase. By setting the thickness T110a within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ This can reduce the thickness T110a. In addition, it is possible to prevent the conductive layer 112a from being oxidized by oxygen contained in the insulating layer 110b, which would otherwise increase the electrical resistance of the conductive layer 112a. The thickness T110a is not limited to the above range.

[0230] The thickness T110a of the insulating layer 110a can be made thicker than the thickness T110c of the insulating layer 110c. When the region of the semiconductor layer 108 in contact with the insulating layer 110a functions as a source region or a drain region, increasing the thickness T110a can make the distance from the source region or the drain region to the gate electrode more uniform. This can make the electric field of the gate electrode applied to the channel formation region more uniform. As shown in FIG. 3B , the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is to be formed (here, the top surface of the insulating layer 110b) and the top surface of the insulating layer 110c in a cross-sectional view.

[0231] The thickness T110c of the insulating layer 110c is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, even more preferably 3 nm or more and 50 nm or less, even more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 3 nm or more and 10 nm or less, and even more preferably 5 nm or more and 10 nm or less.

[0232] The thickness T110c is preferably a value that at least functions as a barrier film against oxygen. The thickness T110c can be thinner than the thickness T110a. If the thickness T110c of the insulating layer 110c is thick, the amount of impurities released from the insulating layer 110c increases, which may result in a larger amount of impurities diffusing into the channel formation region. On the other hand, if the thickness T110c is thin, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112b via the insulating layer 110c, which may result in a reduced amount of oxygen supplied to the channel formation region. By setting the thickness T110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V Ｏ ) and V Ｏ This can reduce H. Furthermore, it is possible to prevent the conductive layer 112b from being oxidized by oxygen contained in the insulating layer 110b, which would otherwise increase the electrical resistance of the conductive layer 112b. Note that the thickness T110c is not limited to the above range.

[0233] At least one of the regions of the semiconductor layer 108 in contact with the insulating layer 110a and the insulating layer 110c can be a region having lower electrical resistance than the channel formation region (hereinafter also referred to as a low-resistance region). This region can also be referred to as a region having a higher carrier concentration or a higher oxygen defect density than the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) for the insulating layer 110a, the region of the semiconductor layer 108 in contact with the insulating layer 110a can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110c, the region of the semiconductor layer 108 in contact with the insulating layer 110c can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region. The low resistance region can function as a buffer region for alleviating the drain electric field. Note that the low resistance region can also function as a source region or a drain region.

[0234] Note that impurities released from the insulating layer 110a may diffuse into the channel formation region via the insulating layer 110b or via one of the source region and the drain region of the semiconductor layer 108. Similarly, impurities released from the insulating layer 110c may diffuse into the channel formation region via the insulating layer 110b or via the other of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0235] However, if the amount of impurities released from the insulating layer 110a and the insulating layer 110c becomes too large, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and V Ｏ The amount of H may be greater than the amount of H. Even when a material that releases impurities is used for the insulating layer 110a and the insulating layer 110c, it is more preferable that the amount of released impurities is small.

[0236] One or more of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can have a stacked structure.

[0237] When the insulating layer 110c has a stacked structure, the materials listed in the description of the insulating layer 110c can be used for each of the layers constituting the insulating layer 110c. An oxide or oxynitride can be preferably used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side. By using an oxide or oxynitride for the layer provided on the insulating layer 110b side, oxygen can be supplied to the insulating layer 110b (or the insulating film that will become the insulating layer 110b) during the formation of the layer (or the film that will become the layer), which is preferable. The insulating layer 110c can have, for example, a stacked structure of a first film containing an oxide or oxynitride and a second film containing a nitride or nitride oxide on the first film. More specifically, the insulating layer 110c can have, for example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0238] [Opening 141, Opening 143] The top surface shapes of openings 141 and 143 are not limited and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygonal shape, or shapes with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 1A and other figures, the top surface shapes of openings 141 and 143 are preferably circular. By making the top surface shapes of the openings circular, the processing accuracy when forming the openings can be improved, allowing for the formation of openings of finer sizes. Note that, in this specification and other documents, "circular" does not necessarily mean a perfect circle.

[0239] In this specification and the like, the top surface shape of the opening 141 refers to the shape of the top surface end portion of the insulating layer 110 on the opening 141 side. Also, the top surface shape of the opening 143 refers to the shape of the bottom surface end portion of the conductive layer 112b on the opening 143 side.

[0240] As shown in FIG. 1A and other figures, the top shapes of the openings 141 and 143 can be made to match or approximately match each other. In this case, as shown in FIGS. 1B and 1C and other figures, it is preferable that the bottom edge of the conductive layer 112b on the opening 143 side be made to match or approximately match the top edge of the insulating layer 110 on the opening 141 side. The bottom surface of the conductive layer 112b refers to the surface on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface on the conductive layer 112b side. Note that the top shapes of the openings 141 and 143 may not be made to match each other. Note that when the top shapes of the openings 141 and 143 are circular, the openings 141 and 143 may or may not be concentric.

[0241] The channel length and channel width of the transistor 100 will be described with reference to FIGS. 3A and 3B.

[0242] In FIG. 3B , the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow. The channel length L100 of the transistor 100 corresponds to the length of the side surface of the insulating layer 110b on the opening 141 side in a cross-sectional view. That is, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110b between the side surface of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure tool, thereby enabling the realization of a fine-sized transistor. Specifically, it is possible to realize a transistor with an extremely short channel length that could not be realized using conventional exposure tools used in the mass production of flat panel displays (e.g., minimum dimensions of approximately 2 μm or 1.5 μm). Furthermore, it is possible to realize a transistor with a channel length of less than 10 nm without using the extremely expensive exposure tools used in cutting-edge LSI technology.

[0243] 3 shows a configuration in which the top surface of the insulating layer 110a, the top surface of the conductive layer 112a, and the top surface of the substrate 102 are parallel to one another. In this case, the angle θ 110b is the same as the angle θ shown in Fig. 4. For the angle θ, see the above description.

[0244] The channel length L100 may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and may be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 may be 100 nm or more and 1 μm or less.

[0245] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced, and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

[0246] The channel length L100 can be controlled by adjusting the thickness T110b and angle θ110b of the insulating layer 110b.

[0247] The thickness T110b of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.

[0248] The smaller the angle θ110b, the longer the channel length L100 can be, and the larger the angle θ110b, the shorter the channel length L100 can be.

[0249] 1B and the like, the angle θ110b is shown as being less than 90 degrees; however, one embodiment of the present invention is not limited to this. As shown in FIG. 10, the angle θ110b can be set to 90 degrees or approximately 90 degrees. This can shorten the channel length L100 of the transistor 100.

[0250] In a configuration in which the angle θ110b is 90 degrees, when an impurity element is supplied through the insulating layer 106, the impurity element must pass through the insulating layer 106 and the region of the semiconductor layer 108 that contacts the conductive layer 112b and the region that contacts the insulating layer 110c before reaching the channel formation region. At this time, the impurity element passes through the insulating layer 106 having a thickness Tb and the semiconductor layer 108 having a thickness equal to the sum of the thickness Hb, the thickness T112b, and the thickness T110c (see FIG. 4 ). Therefore, the depth of the channel formation region is deeper than the depth of the region provided along the top surface of the conductive layer 112b. Therefore, the concentration Nc of the impurity element in the channel formation region is lower than the concentration Nb of the impurity element in the region 108Db. Furthermore, the concentration Nc is lower than the concentration Na of the impurity element in the region 108Da. Note that the higher the film density of the material used for the semiconductor layer 108, the higher the stopping power during ion implantation, and the smaller the amount of impurity element that reaches the channel formation region. For example, when the film density of the semiconductor layer 108 is higher than that of the insulating layer 106, the amount of the impurity element supplied to the semiconductor layer 108 is smaller even if the depth is the same.

[0251] 1B and the like show a configuration in which the shape of the side surface of the insulating layer 110 on the opening 141 side is linear in a cross-sectional view, but one embodiment of the present invention is not limited to this. In a cross-sectional view, the shape of the side surface of the insulating layer 110 on the opening 141 side may be curved, or the side surface may have both a linear region and a curved region.

[0252] Here, the conductive layer 112b is preferably not provided inside the opening 141. Specifically, the conductive layer 112b preferably does not have a region in contact with the side surface of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110b, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 coincides with the top shape of the opening 141 or that the opening 143 encompasses the opening 141 in a top view (also referred to as a plan view).

[0253] 3A and 3B, the width D141 of the opening 141 is indicated by a two-dot chain line with a double arrow. FIG. 3A shows an example in which the top surface shape of the opening 141 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the length of the circumference of the circle. In other words, the channel width W100 is π×D141. In this way, when the top surface shape of the opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.

[0254] The width D141 of the opening 141 may vary in the depth direction. For example, the width D141 of the opening 141 may be an average value of the diameter at the highest point, the diameter at the lowest point, and the diameter at the midpoint between these three points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view. Alternatively, the diameter of the opening 141 may be any of the diameter at the highest point, the diameter at the lowest point, or the diameter at the midpoint between these three points of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view.

[0255] When the opening 141 is formed using photolithography, the width D141 of the opening 141 is equal to or greater than the minimum exposure dimension of the exposure device. The width D141 can be, for example, 200 nm or greater, 300 nm or greater, 400 nm or greater, or 500 nm or greater, and can be less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0256] Note that although the example in which the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region has been described here, one embodiment of the present invention is not limited to this. The region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel formation region. Similarly, the region in contact with the insulating layer 110c may also function as a channel formation region.

[0257] [Conductive Layer 112a, Conductive Layer 112b, and Conductive Layer 104] The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each have a single-layer structure or a stacked structure of two or more layers. Materials that can be used for the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the above metals. The conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each be preferably made of a conductive material with low electrical resistivity, such as one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly preferred because of its excellent mass productivity.

[0258] A conductive metal oxide (also referred to as an oxide conductor) can be used for each of the conductive layer 112a, the conductive layer 112b, and the conductive layer 104. Examples of oxide conductors (OC) include indium oxide, zinc oxide, In—Sn oxide (ITO), In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide (also referred to as ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In—Ga—Zn oxide. In particular, an oxide conductor containing indium is preferable because of its high conductivity.

[0259] When oxygen vacancies are formed in a metal oxide having semiconductor properties and hydrogen is added to the oxygen vacancies, a donor level is formed near the conduction band. As a result, the metal oxide becomes electrically conductive, and the conductivity of the metal oxide increases. The metal oxide that has become electrically conductive can be called an oxide conductor.

[0260] The conductive layers 112a, 112b, and 104 can each have a stacked-layer structure of a conductive film containing the oxide conductor (metal oxide) and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced.

[0261] A Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be applied to each of the conductive layer 112a, the conductive layer 112b, and the conductive layer 104. By using a Cu-X alloy film, it can be processed by wet etching, thereby reducing manufacturing costs.

[0262] Note that the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can be formed using the same material, or at least one of them can be formed using a different material.

[0263] The conductive layer 112a and the conductive layer 112b each have a region in contact with the semiconductor layer 108. When an oxide semiconductor is used for the semiconductor layer 108, if a metal that is easily oxidized (e.g., aluminum) is used for the conductive layer 112a or the conductive layer 112b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, which may hinder conduction therebetween. Therefore, for the conductive layer 112a and the conductive layer 112b, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor.

[0264] For the conductive layer 112a and the conductive layer 112b, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are resistant to oxidation or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112a or the conductive layer 112b has a stacked structure, it is preferable to use a conductive material that is resistant to oxidation for at least the layer in contact with the semiconductor layer 108.

[0265] The conductive layer 112 a and the conductive layer 112 b can each be formed using any of the above-described oxide conductors, such as indium oxide, zinc oxide, ITO, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn oxide containing silicon, and zinc oxide doped with gallium.

[0266] The conductive layer 112a and the conductive layer 112b may each be formed using a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layer 104 may also be formed using any of the nitride conductors described above.

[0267] One or more of the conductive layers 112a, 112b, and 104 can have a stacked structure.

[0268] 11A to 11D are cross-sectional views of a semiconductor device 10A according to one embodiment of the present invention. For a top view of the semiconductor device 10A, refer to FIG. 1A. Each of FIGS. 11A to 11D is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 1A.

[0269] The semiconductor device 10A includes a transistor 100A and an insulating layer 110. The transistor 100A differs mainly from the transistor 100 illustrated in FIG. 1B and the like in that a conductive layer 112a has a stacked-layer structure.

[0270] 11A and 11B show a structure in which the conductive layer 112a has a two-layer structure including a conductive layer 112a_1 and a conductive layer 112a_2 over the conductive layer 112a_1.

[0271] The conductive layer 112a_2 having a region in contact with the semiconductor layer 108 is preferably formed using a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor. The conductive layer 112a_2 can be formed using any of the materials mentioned in the description of the conductive layer 112a.

[0272] The conductive layer 112a_1 does not have a region in contact with the semiconductor layer 108, and therefore the material used is not particularly limited. For example, the conductive layer 112a_1 is preferably made of a material having lower electrical resistivity than the conductive layer 112a_2. This can reduce the electrical resistance of the conductive layer 112a. For example, In—Sn—Si oxide (ITSO) can be preferably used for the conductive layer 112a_2, and copper or tungsten can be preferably used for the conductive layer 112a_1.

[0273] 11A, the edge of the conductive layer 112a_2 can be aligned or approximately aligned with the edge of the conductive layer 112a_1. For example, a first film to be the conductive layer 112a_1 and a second film to be the conductive layer 112a_2 are formed, and a mask layer (e.g., photoresist) is formed on the second film. Then, the first film and the second film are processed using the mask layer as a mask, thereby forming the conductive layer 112a. By processing the first film and the second film in the same process using the same mask layer, manufacturing costs can be reduced.

[0274] The end of the conductive layer 112a_2 may not be aligned with the end of the conductive layer 112a_1. As shown in FIG. 11B, the conductive layer 112a_2 may be provided so as to cover the conductive layer 112a_1. The conductive layer 112a_2 has a region in contact with the top surface and side surface of the conductive layer 112a_1. It can also be said that the conductive layer 112a_2 has a portion protruding beyond the end of the conductive layer 112a_1. For example, the conductive layer 112a_1 may be formed, a film to become the conductive layer 112a_2 may be formed on the conductive layer 112a_1, and the film may be processed to form the conductive layer 112a_2. By making the conductive layer 112a_2 protrude beyond the end of the conductive layer 112a_1, the step of the formation surface of a layer (e.g., the insulating layer 110) formed on the conductive layer 112a is reduced, thereby improving the coverage of the layer. This can prevent defects such as discontinuities or voids in the layer.

[0275] 11A and 11B, the layers constituting the conductive layer 112a are shown to have the same or approximately the same thickness, but this is not limited to this embodiment of the present invention. Some or all of the layers constituting the conductive layer 112a may have different thicknesses. For example, it is more preferable to make the layer using a material with low electrical resistivity thicker than the other layers, which can reduce the electrical resistance of the conductive layer 112a. Specifically, a material with lower electrical resistivity than the conductive layer 112a_2 can be used for the conductive layer 112a_1, and the thickness of the conductive layer 112a_1 can be made thicker than the thickness of the conductive layer 112a_2. This can reduce the electrical resistance of the conductive layer 112a.

[0276] 11C and 11D show a structure in which the conductive layer 112a has a three-layer structure including a conductive layer 112a_3, a conductive layer 112a_1 over the conductive layer 112a_3, and a conductive layer 112a_2 over the conductive layer 112a_1.

[0277] 11C , the end portion of the conductive layer 112a_1 can be in contact with the top surface of the conductive layer 112a_3. The conductive layer 112a_2 has regions in contact with the top surface and side surface of the conductive layer 112a_1 and the top surface of the conductive layer 112a_3. That is, it can be said that the conductive layers 112a_2 and 112a_3 each have portions that protrude beyond the end portion of the conductive layer 112a_1. It can also be said that the top surface, side surface, and bottom surface of the conductive layer 112a_1 are surrounded by the conductive layers 112a_2 and 112a_3. The conductive layer 112a_3 is preferably made of a material that has high adhesion to the surface on which the conductive layer 112a_3 is to be formed (here, the surface of the substrate 102).

[0278] As described above, the conductive layer 112a_1 is preferably made of a material with low electrical resistivity. However, depending on the material, adhesion between the conductive layer 112a_1 and a surface on which the conductive layer 112a_1 is to be formed (e.g., the surface of the substrate 102) may be low, which may result in a low manufacturing yield of the semiconductor device. By using a material for the conductive layer 112a_3 that has higher adhesion to the surface on which the conductive layer 112a_1 is to be formed than the conductive layer 112a_1, the manufacturing yield of the semiconductor device can be increased. Note that the thickness of the conductive layer 112a_3 can be set to a thickness that effectively increases the adhesion of the conductive layer 112a to the surface on which the conductive layer 112a is to be formed, and can be thinner than the thicknesses of the conductive layer 112a_1 and the conductive layer 112a_2. By reducing the thickness of the conductive layer 112a_3, manufacturing costs can be reduced.

[0279] For example, it is preferable to use In—Sn—Si oxide (ITSO) for the conductive layer 112a_3, copper for the conductive layer 112a_1, and In—Sn—Si oxide (ITSO) for the conductive layer 112a_2. When a glass substrate is used as the substrate 102, adhesion between the glass substrate and an ITSO film is higher than adhesion between a glass substrate and a copper film. Furthermore, using the same material for the conductive layers 112a_2 and 112a_3 facilitates processing when the conductive layers 112a_2 and 112a_3 are formed in the same process, thereby increasing the manufacturing yield of the semiconductor device.

[0280] As shown in FIG. 11C , the edge of the conductive layer 112a_2 can be aligned or substantially aligned with the edge of the conductive layer 112a_3. For example, a first film to become the conductive layer 112a_3 is formed, a conductive layer 112a_1 is formed on the first film, and a second film to become the conductive layer 112a_2 is formed on the first film and the conductive layer 112a_1. A mask layer (e.g., photoresist) is formed on the second film. Then, the first film and the second film are processed using the mask layer as a mask to form the conductive layer 112a, which includes the conductive layer 112a_3, the conductive layer 112a_1, and the conductive layer 112a_2. Processing the first film and the second film in the same process can reduce manufacturing costs. Alternatively, as shown in FIG. 11D , the edge of the conductive layer 112a_1 can be aligned or substantially aligned with the edge of the conductive layer 112a_3.

[0281] Although the conductive layer 112a has a stacked structure of two or three layers in this example, one embodiment of the present invention is not limited to this. The conductive layer 112a can also have a stacked structure of four or more layers.

[0282] The configuration of the conductive layer 112a shown in FIGS. 11A to 11D can also be applied to other configuration examples.

[0283] [Insulating Layer 106] The insulating layer 106 preferably has one or more inorganic insulating layers. The insulating layer 106 can be made of the same material as that used for the insulating layer 110.

[0284] The insulating layer 106 has a region in contact with the semiconductor layer 108, the conductive layer 112b, the conductive layer 104, and the insulating layer 110. When a metal oxide is used for the semiconductor layer 108, any of the above oxides and oxynitrides is preferably used for at least a film that is in contact with the semiconductor layer 108 among the films that constitute the insulating layer 106. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

[0285] Note that in a miniaturized transistor, a thinner gate insulating layer may result in a larger leakage current. By using a material with a high relative dielectric constant (also referred to as a high-k material) for the gate insulating layer, a lower voltage can be achieved during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0286] 1B and the like, the insulating layer 106 has a single-layer structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers. FIG. 12 shows a structure in which the insulating layer 106 has a two-layer structure of an insulating layer 106a and an insulating layer 106b over the insulating layer 106a.

[0287] 12 is a cross-sectional view of a semiconductor device 10B according to one embodiment of the present invention. For a top view of the semiconductor device 10B, see FIG. 1A. FIG. 12 is a cross-sectional view of the cut surface taken along dashed line A1-A2 in FIG. 1A.

[0288] The semiconductor device 10B includes a transistor 100B and an insulating layer 110. The transistor 100B differs mainly from the transistor 100 shown in FIG. 1B and the like in that the insulating layer 106 has a stacked-layer structure.

[0289] In the case where the insulating layer 106 has a stacked-layer structure, the insulating layer on the semiconductor layer 108 side (the insulating layer 106a here) preferably contains oxide or oxynitride. The insulating layer 106a can be preferably formed using, for example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0290] It is preferable to use a material that is difficult for substances to permeate for at least one of the layers constituting the insulating layer 106. The layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to prevent metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in layers formed on the transistor 100 from diffusing into the semiconductor layer 108 through the insulating layer 106. Furthermore, it is possible to prevent oxygen contained in the semiconductor layer 108 from diffusing into the conductive layer 104 through the insulating layer 106. This prevents oxygen deficiency (V Ｏ ) can be suppressed. In addition, the conductive layer 104 can be prevented from being oxidized by oxygen contained in the semiconductor layer 108, which can prevent the electrical resistance of the conductive layer 104 from increasing. As a result, a transistor with good electrical characteristics and high reliability can be obtained. The layer functioning as a barrier film preferably uses one or more of the above-described nitrides and nitride oxides. Alternatively, one or more of oxides and oxynitrides can also be used for the layer, and aluminum oxide can be preferably used, for example.

[0291] When the insulating layer 106 has a stacked-layer structure, for example, silicon oxynitride can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a and aluminum oxide can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon oxynitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a and silicon nitride can be used for the insulating layer 106b.

[0292] Although an example in which the insulating layer 106 has a stacked structure of two layers is shown here, one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a stacked structure of three or more layers.

[0293] The configuration of the insulating layer 106 shown in FIG. 12 can also be applied to other configuration examples.

[0294] [Substrate 102] There are no significant limitations on the material of the substrate 102, but it is necessary that the material has at least heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. Also, a substrate on which a semiconductor element is provided can be used as the substrate 102. The shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.

[0295] A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing the peeling layer, after a semiconductor device is partially or entirely completed thereon, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0296] The following describes a configuration example of a semiconductor device that is partially different from the configuration example described above. Note that, in the following, descriptions of parts that overlap with the configuration example described above may be omitted. Furthermore, in the drawings shown below, parts that have the same functions as the configuration example described above may be hatched with the same pattern and may not be assigned reference numerals.

[0297] 13A and 13B show cross-sectional views of a semiconductor device 10C according to one embodiment of the present invention. For a top view of the semiconductor device 10B, see FIG. 1A. FIG. 13A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A, and FIG. 13B is a cross-sectional view of a cut surface taken along dashed line B1-B2 in FIG. 1A.

[0298] The semiconductor device 10C includes a transistor 100 and an insulating layer 110. The semiconductor device 10C differs from the semiconductor device 10 shown in FIG. 1B etc. mainly in that the insulating layer 110 includes an insulating layer 110d and an insulating layer 110e.

[0299] An enlarged view of FIG. 13A is shown in FIG. 13C. The insulating layer 110 includes an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110e on the insulating layer 110c. The insulating layer 110d and the insulating layer 110e can each be made of the materials listed in the description of the insulating layer 110a. The insulating layer 110d and the insulating layer 110e can each preferably be made of, for example, silicon nitride or silicon nitride oxide. The insulating layer 110d and the insulating layer 110e can be made of the same material, or different materials.

[0300] The insulating layer 110d is provided between the insulating layer 110a and the substrate 102 and the conductive layer 112a. The insulating layer 110d is provided to cover the conductive layer 112a. The insulating layer 110d has regions in contact with the top surface and side surfaces of the conductive layer 112a, the top surface of the substrate 102, and the side surfaces of the semiconductor layer 108.

[0301] The insulating layer 110e is provided between the insulating layer 110c and the conductive layer 112b and the insulating layer 106. The insulating layer 110e has regions in contact with the top surface of the insulating layer 110c, the bottom surface of the conductive layer 112b, the bottom surface of the insulating layer 106, and the side surface of the semiconductor layer 108.

[0302] It is more preferable that the insulating layers 110d and 110e each be made of a material that releases impurities (e.g., water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108. This allows the region of the semiconductor layer 108 in contact with the insulating layer 110d to be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112a (one of the source and drain regions) and the channel formation region. Similarly, by using a material that releases impurities for the insulating layer 110e, the region of the semiconductor layer 108 in contact with the insulating layer 110e can be a low-resistance region. The semiconductor layer 108 can have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source and drain regions) and the channel formation region. The low-resistance region can function as a buffer region for reducing the drain electric field. Note that these low-resistance regions may function as source or drain regions.

[0303] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor. For example, when the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode, by forming a region of the semiconductor layer 108 in contact with the insulating layer 110d as a low-resistance region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor. When the conductive layer 112a functions as a source electrode and the conductive layer 112b functions as a drain electrode, by forming a region of the semiconductor layer 108 in contact with the insulating layer 110e as a low-resistance region, a high electric field is less likely to be generated near the drain region, which can suppress the generation of hot carriers and the deterioration of the transistor.

[0304] When the region of the semiconductor layer 108 in contact with the insulating layer 110d functions as a source region or a drain region, the distance from the source region to the gate electrode and the distance from the drain region to the gate electrode of the semiconductor layer 108 can be made more uniform, thereby making the electric field of the gate electrode applied to the channel formation region more uniform.

[0305] The insulating layer 110a preferably releases a small amount of impurities and is less likely to penetrate the insulating layer 110a. This can prevent impurities from diffusing into the channel formation region of the semiconductor layer 108 through the insulating layers 110a and 110b. Similarly, the insulating layer 110c preferably releases a small amount of impurities and is less likely to penetrate the insulating layer 110c. This can prevent impurities from diffusing into the channel formation region of the semiconductor layer 108 through the insulating layers 110c and 110b. This can provide a transistor with good electrical characteristics and high reliability.

[0306] When a metal oxide is used for the semiconductor layer 108, it is more preferable that the impurities released from the insulating layers 110d and 110e include hydrogen. The hydrogen reacts with oxygen that is bonded to the metal atoms of the metal oxide to form water, which causes oxygen deficiency (V Ｏ ) is formed. Furthermore, oxygen vacancies (V Ｏ ) with hydrogen atoms (V Ｏ H) functions as a donor, generating electrons as carriers. This increases the carrier concentration in the region of the semiconductor layer 108 that is in contact with the insulating layer 110d and the region that is in contact with the insulating layer 110e, thereby reducing the electrical resistance.

[0307] The insulating layer 110d preferably has a region with a higher hydrogen content than the insulating layer 110a. The hydrogen content of the insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS).

[0308] The amount of released hydrogen can be adjusted by differentiating the deposition conditions for the insulating layer 110d and the insulating layer 110a. Specifically, the deposition conditions for the insulating layer 110d and the insulating layer 110a can be varied by varying one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow rate ratio, deposition temperature, and distance between the substrate and the electrode. For example, by making the deposition power density for the insulating layer 110d lower than the deposition power density for the insulating layer 110a, the hydrogen content in the insulating layer 110d can be made higher than the hydrogen content in the insulating layer 110a. This increases the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d.

[0309] The hydrogen content in the deposition gas used to form the insulating layer 110d is preferably higher than the hydrogen content in the deposition gas used to form the insulating layer 110a. Specifically, when silicon nitride films or silicon nitride oxide films are formed by PECVD for each of the insulating layer 110d and the insulating layer 110a, the ratio of the flow rate of ammonia gas to the total flow rate of the deposition gas used to form the insulating layer 110d (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the deposition gas used to form the insulating layer 110a. By forming the insulating layer 110d under conditions with a high ammonia flow rate ratio, the hydrogen content in the insulating layer 110d can be increased. Furthermore, the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d can be increased.

[0310] It is more preferable that the film density of the insulating layer 110a be higher than that of the insulating layer 110d. This can prevent hydrogen contained in the insulating layer 110d from diffusing into the channel formation region of the semiconductor layer 108 via the insulating layers 110a and 110b. The film density can be evaluated using, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflection (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image. Therefore, in a transmission electron (TE) image, the insulating layer 110a may appear darker than the insulating layer 110d. Even if the same material is used for the insulating layers 110d and 110a, the film densities are different, and therefore the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

[0311] The insulating layer 110e preferably has a region containing more hydrogen than the insulating layer 110c. The film density of the insulating layer 110c is more preferably higher than that of the insulating layer 110e. For the insulating layers 110c and 110e, the descriptions of the insulating layers 110a and 110d can be referred to.

[0312] Although the insulating layer 110 has a five-layer structure here, one embodiment of the present invention is not limited to this. The insulating layer 110 can also have a two-layer, three-layer, four-layer, or six or more-layer structure. Alternatively, the insulating layer 110 can have a single-layer structure.

[0313] The configuration of the insulating layer 110 shown in Configuration Example 1-2 can also be applied to other configuration examples.

[0314] 14A and 14B show cross-sectional views of a semiconductor device 10D according to one embodiment of the present invention. For a top view of the semiconductor device 10D, see FIG. 1A. FIG. 14A is a cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 14B is a cross-sectional view of a cut surface taken along dashed dotted line B1-B2 in FIG. 1A.

[0315] The semiconductor device 10D includes a transistor 100, an insulating layer 110, and an insulating layer 109. The semiconductor device 10D differs from the semiconductor device 10 shown in FIG. 1B etc. mainly in that the semiconductor device 10D includes the insulating layer 109 between the substrate 102 and the conductive layer 112a.

[0316] An insulating layer 109 is provided over the substrate 102, a conductive layer 112a is provided over the insulating layer 109, and an insulating layer 110 is provided over the conductive layer 112a. The insulating layer 109 has regions in contact with a lower surface of the conductive layer 112a and a lower surface of the insulating layer 110. The conductive layer 112a has regions in contact with and sandwiched between the insulating layer 109 and the insulating layer 110. The insulating layer 110 has regions in contact with a top surface and side surfaces of the conductive layer 112a, the top surface of the insulating layer 109, the side surface of the semiconductor layer 108, a bottom surface of the conductive layer 112b, and a bottom surface of the insulating layer 106.

[0317] The insulating layer 109 is preferably made of a material that releases impurities (for example, water and hydrogen) that reduce the electrical resistance of the semiconductor layer 108. The insulating layer 109 can be made of the same material as can be used for the insulating layer 110d and the insulating layer 110e. For example, the insulating layer 109 can be made of silicon nitride or silicon nitride oxide.

[0318] The impurities released from the insulating layer 109 diffuse into a region of the conductive layer 112a that is in contact with the insulating layer 109. The impurities diffused into the conductive layer 112a also diffuse into a region of the semiconductor layer 108 that is in contact with the conductive layer 112a. This reduces the electrical resistance of the region of the semiconductor layer 108 that is in contact with the conductive layer 112a, that is, one of the source region and the drain region. Therefore, a transistor with a large on-state current can be obtained, and a semiconductor device that operates at high speed can be obtained.

[0319] When a metal oxide is used for the semiconductor layer 108, the impurities released from the insulating layer 109 preferably contain hydrogen. Hydrogen diffused from the insulating layer 109 to the semiconductor layer 108 through the conductive layer 112a increases the carrier concentration in the region of the semiconductor layer 108 in contact with the conductive layer 112a, thereby reducing the electrical resistance of one of the source and drain regions.

[0320] The insulating layer 109 is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112a. This can reduce the electrical resistance of the conductive layer 112a. For example, when a metal oxide is used for the conductive layer 112a, the impurities preferably contain hydrogen. This increases the carrier concentration of the conductive layer 112a, thereby reducing the electrical resistance. Furthermore, the conductive layer 112a can function as a wiring, thereby providing a semiconductor device with low wiring resistance. Note that the impurities that reduce the electrical resistance of the conductive layer 112a may be the same as or different from the impurities that reduce the electrical resistance of the semiconductor layer 108.

[0321] The materials that can be used for the conductive layer 112a are as described above. Note that the conductive layer 112a preferably easily transmits impurities and more preferably does not easily adsorb impurities.

[0322] The insulating layer 110a has a region in contact with the top surface of the insulating layer 109 and the top surface and side surfaces of the conductive layer 112a, which can suppress diffusion of impurities contained in the insulating layer 109 and the conductive layer 112a into the channel formation region of the semiconductor layer 108 through the insulating layer 110b.

[0323] The insulating layer 109 preferably has a region containing more hydrogen than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109. For the insulating layer 109, the descriptions of the insulating layers 110d and 110e can be referred to.

[0324] Note that impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 112a and one of the source region and the drain region of the semiconductor layer 108. However, oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, and therefore oxygen vacancies (V Ｏ ) and V Ｏ H can be reduced. This suppresses a shift in threshold voltage, enabling a transistor with both a small cutoff current and a large on-state current. Therefore, a semiconductor device with both low power consumption and high performance can be provided.

[0325] 14A and the like illustrate a three-layer structure of the insulating layer 110 including the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c, but one embodiment of the present invention is not limited to this. For example, as shown in FIGS. 15A and 15B , the insulating layer 110 can include the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, and the insulating layer 110e. The insulating layer 110e is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112b. This can reduce the electrical resistance of the conductive layer 112b. For example, when a metal oxide is used for the conductive layer 112b, the impurities preferably contain hydrogen. This can increase the carrier concentration of the conductive layer 112b and reduce the electrical resistance. The conductive layer 112b can function as a wiring, thereby achieving a semiconductor device with low wiring resistance. Alternatively, the insulating layer 110 can include the insulating layer 110d. For example, the insulating layer 110 may have an insulating layer 110a, an insulating layer 110b, an insulating layer 110c, an insulating layer 110d, and an insulating layer 110e.

[0326] 16A , the insulating layer 110 can be in contact with the side surface of the insulating layer 109. Furthermore, the insulating layer 109 can have an edge aligned with or substantially aligned with an edge of the conductive layer 112a. For example, an insulating film that will become the insulating layer 109 and a conductive film that will become the conductive layer 112a can be formed and then processed to form the insulating layer 109 and the conductive layer 112a. Processing the insulating film and the conductive film in the same process can reduce manufacturing costs.

[0327] The end of the insulating layer 109 may not be aligned with the end of the conductive layer 112a. As shown in FIG. 16B , the insulating layer 109 may have a portion that protrudes beyond the end of the conductive layer 112a. The end of the conductive layer 112a contacts the top surface of the insulating layer 109. This structure reduces the step between the surface of the conductive layer 112a and a layer (e.g., the insulating layer 110) formed on the insulating layer 109, thereby improving the coverage of the layer. This prevents defects such as discontinuities or voids in the layer.

[0328] The configuration of the insulating layer 109 shown in Configuration Example 1-3 can also be applied to other configuration examples.

[0329] 17A and 17B are cross-sectional views of a semiconductor device 10E according to one embodiment of the present invention. For a top view of the semiconductor device 10E, see FIG. 1A. FIG. 17A is a cross-sectional view of a section taken along dashed dotted line A1-A2 in FIG. 1A, and FIG. 17B is a cross-sectional view of a section taken along dashed dotted line B1-B2 in FIG. 1A.

[0330] The semiconductor device 10E includes a transistor 100C and an insulating layer 110. The transistor 100C differs mainly from the transistor 100 shown in FIG. 1B and the like in that the semiconductor layer 108 has a stacked-layer structure.

[0331] 17A and 17B show a configuration in which the semiconductor layer 108 has a three-layer structure including a semiconductor layer 108a, a semiconductor layer 108b on the semiconductor layer 108a, and a semiconductor layer 108c on the semiconductor layer 108b.

[0332] The semiconductor layer 108a, the semiconductor layer 108b, and the semiconductor layer 108c can each be made of the materials listed in the description of the semiconductor layer 108. The semiconductor layer 108a, the semiconductor layer 108b, and the semiconductor layer 108c each preferably contain a metal oxide that exhibits semiconductor properties.

[0333] The band gap of each of the first metal oxide in the semiconductor layer 108a, the second metal oxide in the semiconductor layer 108b, and the third metal oxide in the semiconductor layer 108c is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0334] The band gap of the first metal oxide is preferably larger than that of the second metal oxide. The band gap of the third metal oxide is preferably larger than that of the second metal oxide. The semiconductor layer 108b is sandwiched between the semiconductor layers 108a and 108c, which have larger band gaps than the semiconductor layer 108b, to form a buried channel. As a result, the main current path in the semiconductor layer 108 is the semiconductor layer 108b.

[0335] The difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more. The difference between the band gap of the third metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, even more preferably 0.3 eV or more, and even more preferably 0.5 eV or more.

[0336] The conduction band minimum of the first metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the second metal oxide. In other words, the electron affinity of the first metal oxide is preferably smaller than the electron affinity of the second metal oxide. The electron affinity of the third metal oxide is preferably smaller than the electron affinity of the second metal oxide.

[0337] The band gaps of the first metal oxide, the second metal oxide, and the third metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS or ESCA), or X-ray absorption fine structure (XAFS). Alternatively, analysis can be performed by combining a plurality of these techniques. The electron affinity or the conduction band minimum can be determined from the ionization potential, which is the energy difference between the vacuum level and the valence band maximum, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0338] Trap levels due to impurities or defects can be formed at and near the interface between the insulating layer 110 and the semiconductor layer 108. Examples of such impurities include residual components of an etchant or etching gas used to form the opening 141, and components of the conductive layers 112a and 112b that are attached to the side surfaces of the insulating layer 110 when the opening 141 is formed. By providing the semiconductor layer 108a between the semiconductor layer 108b and the insulating layer 110, the semiconductor layer 108b can be kept away from the trap levels.

[0339] Damage may occur to the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity when the insulating layer 106 is formed. As a result, trap states may be formed at the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity. By providing the semiconductor layer 108c between the semiconductor layer 108b and the insulating layer 106, the semiconductor layer 108b can be kept away from the trap states.

[0340] By sandwiching the semiconductor layer 108b, which is the main current path of the semiconductor layer 108, between the semiconductor layer 108a and the semiconductor layer 108c, it is possible to reduce trap levels at the interface of the semiconductor layer 108b and in the vicinity of the interface. This makes it possible to provide a transistor with high on-state current and high reliability. Therefore, it is possible to provide a semiconductor device that achieves both high-speed operation and high reliability.

[0341] The composition of the first metal oxide is preferably different from the composition of the second metal oxide. The composition of the third metal oxide is preferably different from the composition of the second metal oxide. By varying the compositions of the metal oxides, the band gap can be adjusted. Specifically, the content of element M in the first metal oxide and the content of element M in the third metal oxide are preferably higher than the content of element M in the second metal oxide. This allows the band gap of the first metal oxide and the band gap of the third metal oxide to be larger than the band gap of the second metal oxide.

[0342] The indium content of the second metal oxide is preferably higher than the indium content of the first metal oxide and the indium content of the third metal oxide, thereby enabling a transistor with a large on-state current to be obtained.

[0343] For example, when the first metal oxide and the second metal oxide are In-M-Zn oxides, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 40:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:10 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 (atomic ratio) or thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:40 (atomic ratio) or thereabout. It is particularly preferable to use one or more of gallium, aluminum, and tin as the element M. The element M in the first metal oxide, the element M in the second metal oxide, and the element M in the third metal oxide may be the same as or partially or entirely different from one another. When one or more of the first metal oxide, the second metal oxide, and the third metal oxide contain multiple elements M, each of the elements M may be the same as or partially or entirely different from the elements M contained in the other metal oxides.

[0344] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, the second metal oxide may preferably have a composition of In:Sn:Zn=10:1:40 [atomic ratio] or a composition thereabout, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout.

[0345] The second metal oxide may be free of element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar ratio; the second metal oxide may have an atomic ratio of In:Zn=4:1 or a similar ratio; and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar ratio. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Zn=1:1 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Zn=1:4 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition.

[0346] An enlarged view of the side surface of the insulating layer 110 and its vicinity is shown in Figure 18. In Figure 18, the thickness T108a of the semiconductor layer 108a, the thickness T108b of the semiconductor layer 108b, and the thickness T108c of the semiconductor layer 108c are each indicated by a solid double-headed arrow. Here, the shortest distance between the insulating layer 110 and the insulating layer 106 in a cross-sectional view is taken as the thickness of the semiconductor layer 108. Specifically, the thickness of each layer of the semiconductor layer 108 at the midpoint between the height of the top surface and the height of the bottom surface of the insulating layer 110 is shown.

[0347] By increasing the thickness T108b of the semiconductor layer 108b, which is the main current path, a transistor with a large on-state current can be obtained. However, if the thickness T108b is too thick, oxygen vacancies (V Ｏ ) and V Ｏ The amount of H is the oxygen vacancy (V Ｏ ) and VＯ The amount of H may be greater than the amount of H. The thickness T108b is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 15 nm or less.

[0348] The thickness T108c of the semiconductor layer 108c is preferably thicker than the thickness T108a of the semiconductor layer 108a. By increasing the thickness T108c, the semiconductor layer 108b can be separated from trap levels that may be formed at the interface between the insulating layer 106 and the semiconductor layer 108 and in the vicinity thereof. Furthermore, damage to the semiconductor layer 108b during the formation of the insulating layer 106 can be suppressed. If the thickness T108c is too thick, the distance between the conductive layer 104, which functions as a gate electrode, and the semiconductor layer 108b increases, which may result in a small on-state current. The thickness T108c is preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, even more preferably 1 nm or more and 10 nm or less, and even more preferably 2 nm or more and 10 nm or less.

[0349] Oxygen contained in the insulating layer 110 is supplied to the semiconductor layer 108b via the semiconductor layer 108a. Therefore, it is preferable that the semiconductor layer 108a is easily permeable to oxygen. By making the thickness T108a thinner than the thickness T108c, the oxygen contained in the insulating layer 110 can be efficiently supplied to the semiconductor layer 108b. This reduces the oxygen vacancy (V Ｏ ) and V Ｏ H can be reduced. If the thickness T108a is too thin, the distance between the interface between the insulating layer 110 and the semiconductor layer 108 and the trap level near the interface and the semiconductor layer 108b, which is the main current path, becomes short, which may result in a small on-current. Furthermore, reliability may be deteriorated. The thickness T108a is preferably 0.1 nm or more and 10 nm or less, more preferably 0.3 nm or more and 5 nm or less, even more preferably 0.5 nm or more and 5 nm or less, and even more preferably 0.5 nm or more and 3 nm or less.

[0350] It is more preferable that the semiconductor layers 108a, 108b, and 108c each have crystallinity. When the semiconductor layer 108a has crystallinity, the crystallinity of the semiconductor layer 108b formed thereon can be increased. Similarly, when the semiconductor layer 108b has crystallinity, the crystallinity of the semiconductor layer 108c formed thereon can be increased.

[0351] The band gap of the first metal oxide and the band gap of the third metal oxide may be different.

[0352] The band gap of the third metal oxide is preferably larger than the band gap of the first metal oxide. By using a material with a large band gap for the semiconductor layer 108c located on the conductive layer 104 side functioning as the gate electrode, generation and induction of carriers in the semiconductor layer 108c and at the interface between the semiconductor layer 108c and the gate insulating layer (the insulating layer 106 here) can be suppressed, thereby making the transistor highly reliable. For example, generation and induction of carriers in the semiconductor layer 108c and at the interface thereof due to light incident on the transistor can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor due to light.

[0353] The semiconductor layer 108a has regions in contact with the conductive layers 112a and 112b, which function as a source electrode and a drain electrode. By making the band gap of the first metal oxide in the semiconductor layer 108a smaller than the band gap of the third metal oxide, the contact resistance between the semiconductor layer 108a and the conductive layer 112a and the contact resistance between the semiconductor layer 108a and the conductive layer 112b can be reduced. Therefore, a transistor with a large on-state current can be obtained.

[0354] The difference between the band gap of the first metal oxide and the band gap of the third metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more. The conduction band minimum of the third metal oxide is preferably closer to the vacuum level than the conduction band minimum of the first metal oxide. In other words, the electron affinity of the third metal oxide is preferably smaller than the electron affinity of the first metal oxide.

[0355] The content of element M in the third metal oxide is preferably higher than the content of element M in the first metal oxide, thereby making it possible to make the band gap of the third metal oxide larger than the band gap of the first metal oxide.

[0356] When the first metal oxide, the second metal oxide, and the third metal oxide are In-M-Zn oxides, for example, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=40:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn=1:1:1 (atomic ratio) or thereabout, the second metal oxide can have a composition of In:M:Zn=10:1:10 (atomic ratio) or thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 (atomic ratio) or thereabout.

[0357] More specifically, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=40:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition. Alternatively, the first metal oxide may have an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, the second metal oxide may have an atomic ratio of In:Sn:Zn=10:1:10 or a similar composition, and the third metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition.

[0358] The second metal oxide may be configured to not contain the element M. For example, the second metal oxide may be an In—Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=4:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, the first metal oxide may have an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, the second metal oxide may have an In:Zn=1:1 atomic ratio or a composition thereabout, and the third metal oxide may have an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout.

[0359] 17A and the like illustrate an example in which the semiconductor layer 108 has a three-layer structure including semiconductor layers 108a, 108b, and 108c, but one embodiment of the present invention is not limited to this. For example, a structure without one or both of the semiconductor layers 108a and 108c is also possible. Specifically, as shown in FIG. 19A , the semiconductor layer 108 can have a two-layer structure including semiconductor layers 108a and 108b. Alternatively, as shown in FIG. 19B , the semiconductor layer 108 can have a two-layer structure including semiconductor layers 108b and 108c. Alternatively, the semiconductor layer 108 can have a stacked structure of four or more layers.

[0360] The configuration of the semiconductor layer 108 shown in Configuration Example 1-4 can also be applied to other configuration examples.

[0361] 20A shows a top view of a semiconductor device 10F according to one embodiment of the present invention, FIG. 20B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 20A , and FIG. 20C shows a cross-sectional view of the cut surface taken along dashed dotted line B1-B2 in FIG.

[0362] The semiconductor device 10F includes a transistor 100D and an insulating layer 110. The transistor 100D differs from the transistor 100 shown in FIG.

[0363] The transistor 100D includes the conductive layer 103 and the insulating layer 107 between the conductive layer 112a and the insulating layer 110.

[0364] The insulating layer 107 is located over the conductive layer 112a and is provided to cover the top and side surfaces of the conductive layer 112a.

[0365] The conductive layer 103 is located on the insulating layer 107. The conductive layer 112a and the conductive layer 103 are electrically insulated from each other by the insulating layer 107. The conductive layer 103 has an opening 148 that reaches the insulating layer 107 in a region overlapping with the conductive layer 112a.

[0366] The insulating layer 110 is provided over the insulating layer 107 and the conductive layer 103. The insulating layer 110 is provided to cover the top surface and side surfaces of the conductive layer 103 and the top surface of the insulating layer 107. An opening 141 reaching the conductive layer 112a is provided in the insulating layer 110 and the insulating layer 107.

[0367] The insulating layer 110a is located over the insulating layer 107 and the conductive layer 103. The insulating layer 110a is provided so as to cover the top surface and side surfaces of the conductive layer 103. The insulating layer 110a is also provided so as to cover part of the opening 148. The insulating layer 110a is in contact with the insulating layer 107 in the opening 148.

[0368] The top surface shape of opening 148 is not particularly limited. The top surface shape of opening 148 can be any shape that can be applied to openings 141 and 143. As shown in Fig. 20A, the top surface shapes of openings 141, 143, and 148 are preferably circular. By making the top surface shapes of the openings circular, processing accuracy can be improved when forming the openings, and openings of fine sizes can be formed.

[0369] In this specification and the like, the top surface shape of the opening 148 refers to the shape of the top surface end or the bottom surface end of the conductive layer 103 on the opening 148 side.

[0370] When the top shapes of the openings 141 and 148 are circular, the openings 141 and 148 are preferably concentric. This allows the shortest distance between the semiconductor layer 108 and the conductive layer 103 in a cross-sectional view to be equal on the left and right sides of the opening 141. In addition, the openings 141 and 148 may not be concentric.

[0371] In the transistor 100D, the semiconductor layer 108 has a region that overlaps with the conductive layer 104 via the insulating layer 106 and also overlaps with the conductive layer 103 via parts of the insulating layer 110 (particularly, the insulating layer 110a and the insulating layer 110b). In other words, the semiconductor layer 108 has a region that is sandwiched between the conductive layer 104 via the insulating layer 106 and the conductive layer 103 via parts of the insulating layer 110 (particularly, the insulating layer 110a and the insulating layer 110b).

[0372] The conductive layer 104 functions as a gate electrode (also referred to as a first gate electrode) of the transistor 100D. Part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 103 functions as a back gate electrode (also referred to as a second gate electrode). Part of the insulating layer 110 functions as a back gate insulating layer (also referred to as a second gate insulating layer). The conductive layer 103 can be formed using the same material as can be used for the conductive layers 112a, 112b, and 104.

[0373] By providing the back gate electrode in the transistor 100D, the potential of the back gate electrode side (also referred to as the back channel side) of the semiconductor layer 108 is fixed, and the saturation of the Id-Vd characteristics can be improved.

[0374] In this specification and the like, a small change in current in the saturation region in the Id-Vd characteristics of a transistor may be expressed as "high saturation."

[0375] Since the transistor 100D has a back gate electrode, the potential on the back channel side of the semiconductor layer 108 can be fixed, and a shift in the threshold voltage can be suppressed. Here, a shift in the threshold voltage of a transistor may increase the cutoff current. By suppressing the shift in the threshold voltage, a transistor with a small cutoff current can be obtained. This allows a semiconductor device with low power consumption.

[0376] The insulating layer 107 can be formed using a material that can be used for the insulating layer 110. The insulating layer 107 in contact with the conductive layer 112a and the conductive layer 103 is preferably formed using an insulating layer containing nitrogen. The insulating layer 107 can be formed using a material that can be used for the insulating layer 110a. For example, silicon nitride can be preferably used for the insulating layer 107. Note that although the insulating layer 107 has a single-layer structure in this embodiment, one embodiment of the present invention is not limited thereto. The insulating layer 107 can also have a stacked structure of two or more layers.

[0377] The conductive layer 103 can be electrically connected to the conductive layer 112a. For example, an opening can be formed in a region of the insulating layer 107 that overlaps with the conductive layer 112a, and the conductive layer 103 can be provided to cover the opening, thereby making the conductive layer 103 and the conductive layer 112a in contact with each other. The conductive layer 112a, which functions as a source or drain electrode, is electrically connected to the conductive layer 103, which functions as a back gate electrode, so that the source or drain electrode and the back gate electrode can have the same potential. For example, when the conductive layer 112a functions as a source electrode, a shift in the threshold voltage of the transistor 100D can be suppressed. Furthermore, the reliability of the transistor 100D can be improved. Note that the conductive layer 103 can also be formed in contact with the top surface of the conductive layer 112a without providing the insulating layer 107.

[0378] The conductive layer 103 can be electrically connected to the conductive layer 112b. For example, an opening is provided in a region of the insulating layer 110 that overlaps with the conductive layer 103, and the conductive layer 112b is provided to cover the opening, so that the conductive layer 103 and the conductive layer 112b can be in contact with each other.

[0379] The conductive layer 103 can be electrically connected to the conductive layer 104. For example, openings can be provided in regions of the insulating layer 106 and the insulating layer 110 that overlap with the conductive layer 103, and the conductive layer 104 can be provided to cover the openings, thereby making it possible to have a structure in which the conductive layer 103 and the conductive layer 104 are in contact with each other. When the conductive layer 104 that functions as a gate electrode is electrically connected to the conductive layer 103 that functions as a back gate electrode, the back gate electrode and the gate electrode can have the same potential, and the on-state current of the transistor 100D can be increased.

[0380] The thickness of the conductive layer 103 can be made thicker than the thickness of the insulating layer 110. This allows the potential on the back channel side of the semiconductor layer 108 to be fixed over a wide range between the source region and the drain region in the semiconductor layer 108.

[0381] The transistor 100D has a region in which the conductive layer 103, the insulating layer 110, the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 overlap in this order in one direction without any other layers therebetween. The direction may be perpendicular to the channel length direction. By widening the region, the potential on the back channel side of the semiconductor layer 108 can be more reliably controlled.

[0382] The thickness of the conductive layer 103 can be made larger than the sum of the thickness of the portion of the semiconductor layer 108 that is in contact with the conductive layer 112a inside the opening 141 and the thickness of the insulating layer 106 that is in contact with this portion.

[0383] The structures of the conductive layer 103 and the insulating layer 107 shown in Structural Example 1-5 can also be applied to other structural examples.

[0384] 21A to 21I show circuit diagrams of a semiconductor device of one embodiment of the present invention. FIGS. 21A to 25 show top views and cross-sectional views of the semiconductor device of one embodiment of the present invention. Hereinafter, the transistor 100 will be mainly used as an example of a vertical channel transistor included in the semiconductor device of one embodiment of the present invention. The semiconductor device of one embodiment of the present invention is not limited thereto, and can have a structure including one or more of the above-described transistors 100A to 100D.

[0385] A semiconductor device of one embodiment of the present invention includes at least two transistors, and one of the gate, source, or drain of one transistor is electrically connected to the gate, source, or drain of another transistor.

[0386] 21A includes a transistor 100 and a transistor 200. One of the source and the drain of the transistor 200 is electrically connected to the gate of the transistor 100.

[0387] 21A to 21C, the transistors 100 and 200 are illustrated as n-channel transistors; however, one embodiment of the present invention is not limited to this. One or both of the transistors 100 and 200 may be p-channel transistors.

[0388] 21B shows a circuit diagram of a semiconductor device 20 according to one embodiment of the present invention. FIG. 22A shows a top view of the semiconductor device 20. FIG. 22B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 22A , and FIG. 22C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0389] The semiconductor device 20 includes a transistor 100 and a transistor 200. The other of the source and the drain of the transistor 200 is electrically connected to the other of the source and the drain of the transistor 100.

[0390] The transistor 100 and the transistor 200 are each provided on a substrate 102 .

[0391] The transistor 100 can be described above, and therefore a detailed description thereof will be omitted.

[0392] The transistor 200 includes a conductive layer 112b, a conductive layer 112c, a semiconductor layer 208, an insulating layer 106, and a conductive layer 204. The transistor 200 can have a structure similar to that of the transistor 100.

[0393] The conductive layer 112c functions as one of the source electrode and the drain electrode of the transistor 200. The conductive layer 112b functions as the other of the source electrode and the drain electrode of the transistor 100 and also functions as the other of the source electrode and the drain electrode of the transistor 200. Sharing the conductive layer 112b between the transistors 100 and 200 can reduce the area occupied by the semiconductor device. Part of the insulating layer 106 functions as a gate insulating layer of the transistor 200. The conductive layer 204 functions as a gate electrode of the transistor 200.

[0394] The conductive layer 112c can be formed using the same material as the conductive layer 112a. The conductive layer 112c can be formed in the same process as the conductive layer 112a. The insulating layer 110 has an opening 241 that reaches the conductive layer 112c. The opening 241 can be formed in the same process as the opening 141. The conductive layer 112b has an opening 243 in a region overlapping with the opening 241. The opening 243 can be formed in the same process as the opening 143. The top shapes of the openings 241 and 243 are not limited, but are preferably circular. Although the top shapes of the openings 241 and 243 are identical in this example, one embodiment of the present invention is not limited thereto. The top shapes of the openings 241 and 243 may also be different from each other.

[0395] The width of the opening 141 can be made different from the width of the opening 241. By making the width of the opening different, two transistors having different channel widths can be manufactured.

[0396] A semiconductor layer 208 is provided so as to cover the openings 241 and 243. The semiconductor layer 208 can be formed in the same process as the semiconductor layer 108. The insulating layer 106 is provided over the semiconductor layer 208, and the conductive layer 204 is provided over the insulating layer 106. The conductive layer 204 can be formed in the same process as the conductive layer 104.

[0397] The semiconductor layer 208 includes a region 208Da and a region 208Db. Of the regions of the semiconductor layer 208 in contact with the top surface of the conductive layer 112c, the region 208Da is formed in a region located between the top surface of the conductive layer 112c and the bottom surface of the conductive layer 204, and the region 208Db is formed in a region in contact with the top surface of the conductive layer 112b. The regions 208Da and 208Db can be formed in the same process as the regions 108Da and 108Db. The regions 208Da and 208Db contain the same type of impurity element as the regions 108Da and 108Db. In the semiconductor layer 208, the channel formation region of the transistor 200 is located between the regions 208Da and 208Db. For the channel formation regions, the regions 208Da and 208Db, of the transistor 200, the description of the channel formation regions, the regions 108Da and 108Db, of the transistor 100 can be referred to.

[0398] 22A and the like show a structure in which the semiconductor layer is separated into the semiconductor layer 108 and the semiconductor layer 208 in the transistor 100 and the transistor 200; however, one embodiment of the present invention is not limited to this. The transistor 100 and the transistor 200 may share a semiconductor layer.

[0399] [Configuration Example 2-2] Fig. 21C shows a circuit diagram of a semiconductor device 20A according to one embodiment of the present invention. Fig. 23A shows a top view of the semiconductor device 20A. Fig. 23B shows a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in Fig. 23A, and Fig. 23C shows cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4.

[0400] The semiconductor device 20A includes a transistor 100 and a transistor 200. One of the source and the drain of the transistor 200 is electrically connected to one of the source and the drain of the transistor 100.

[0401] The transistor 100 and the transistor 200 are each provided on a substrate 102 .

[0402] The transistor 100 can be described above, and therefore a detailed description thereof will be omitted.

[0403] The transistor 200 includes a conductive layer 112 a , a conductive layer 112 c , a semiconductor layer 208 , an insulating layer 106 , and a conductive layer 204 .

[0404] The conductive layer 112c functions as one of a source electrode and a drain electrode of the transistor 200. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100 and also functions as the other of the source electrode and the drain electrode of the transistor 200. By sharing the conductive layer 112a between the transistors 100 and 200, the area occupied by the semiconductor device can be reduced.

[0405] The conductive layer 112c can be formed using the same material as the conductive layer 112b and in the same process as the conductive layer 112b.

[0406] 21D is a circuit diagram of a semiconductor device 20B according to one embodiment of the present invention. FIG. 24A is a top view of the semiconductor device 20B. FIG. 24B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 24A.

[0407] The semiconductor device 20B includes a transistor 100 and a transistor 250. One of a source and a drain of the transistor 250 is electrically connected to one of a source and a drain of the transistor 100.

[0408] The transistor 100 and the transistor 250 are each provided on a substrate 102 .

[0409] The semiconductor device 20B has a conductive layer 259 over the substrate 102, an insulating layer 252 over the substrate 102 and the conductive layer 259, and a semiconductor layer 253 over the insulating layer 252. The semiconductor device 20B also has an insulating layer 254 over the insulating layer 252 and the semiconductor layer 253, and a conductive layer 255 over the insulating layer 254. The semiconductor layer 253 and the conductive layer 255 overlap each other in a region. The conductive layer 259 functions as a back gate electrode of the transistor 250, and the insulating layer 252 functions as a back gate insulating layer. The insulating layer 254 functions as a gate insulating layer, and the conductive layer 255 functions as a gate electrode.

[0410] An insulating layer 256 is provided over the insulating layer 254 and the conductive layer 255. An opening 257a is provided in the insulating layer 254 and the insulating layer 256 in a region overlapping with part of the semiconductor layer 253. An opening 257b is provided in the insulating layer 254 and the insulating layer 256 in a region overlapping with another part of the semiconductor layer 253.

[0411] A conductive layer 258a is provided over the insulating layer 256 and the opening 257a, and a conductive layer 258b is provided over the insulating layer 256 and the opening 257b. The conductive layer 258a is electrically connected to the semiconductor layer 253 in the opening 257a. The conductive layer 258b is electrically connected to the semiconductor layer 253 in the opening 257b.

[0412] In the semiconductor layer 253, a region overlapping with the conductive layer 255 functions as a channel formation region. The semiconductor layer 253 has a pair of regions 253D sandwiching the channel formation region. One of the pair of regions 253D functions as one of the source region and the drain region and is electrically connected to the conductive layer 258a. The other of the pair of regions 253D functions as the other of the source region and the drain region and is electrically connected to the conductive layer 258b.

[0413] The insulating layer 110 is provided over the insulating layer 256, the conductive layer 258a, and the conductive layer 258b, and the conductive layer 112b is provided over the insulating layer 110.

[0414] The conductive layer 112b and the insulating layer 110 have an opening 146 in a region overlapping with part of the conductive layer 258a (FIG. 24A). The semiconductor layer 108 is provided to cover the opening 146.

[0415] The insulating layer 106 is provided over the insulating layer 110, the conductive layer 112b, and the semiconductor layer 108, and the conductive layer 104 is provided over the insulating layer 106. In addition, an insulating layer 195 is provided over the insulating layer 106 and the conductive layer 104.

[0416] The conductive layer 259 preferably overlaps with the channel formation region and extends beyond the edge of the channel formation region. That is, the conductive layer 259 is preferably larger than the channel formation region. The conductive layer 259 also preferably extends beyond the edge of the semiconductor layer 253. That is, the conductive layer 259 is preferably larger than the semiconductor layer 253.

[0417] The gate electrode and the back gate electrode are arranged to sandwich the channel formation region of the semiconductor layer. The threshold voltage of the transistor can be changed by changing the potential of the back gate electrode. The potential of the back gate electrode can be ground potential or any other potential.

[0418] The back gate electrode can be formed using the same materials and methods as the gate electrode, source electrode, drain electrode, etc. Furthermore, since the gate electrode and the back gate electrode are conductive layers, they have a function of preventing an electric field generated outside the transistor from acting on the semiconductor layer in which the channel is formed (particularly, an electric field shielding function against static electricity). That is, the electrical characteristics of the transistor can be prevented from fluctuating due to the influence of an external electric field such as static electricity. Furthermore, by providing the back gate electrode, the amount of change in the threshold voltage of the transistor before and after a BT (Bias Temperature) stress test can be reduced. By providing the back gate electrode, the variation in the characteristics of the transistor can be reduced, and the reliability of the semiconductor device can be improved.

[0419] As shown in Fig. 21E, the transistor 250 may have a structure in which the back gate and the gate are electrically connected. Alternatively, as shown in Fig. 21F, the transistor 250 may have a structure in which the back gate and the source or the drain are electrically connected. Alternatively, as shown in Fig. 21G, the transistor 250 may have no back gate.

[0420] 21D to 21H, the transistor 100 is illustrated as an n-channel transistor and the transistor 250 is illustrated as a p-channel transistor, but one embodiment of the present invention is not limited thereto. Both the transistor 100 and the transistor 250 can be n-channel or p-channel. Alternatively, the transistor 100 can be a p-channel transistor and the transistor 250 can be an n-channel transistor.

[0421] Like the transistor 100, the transistor 250 can be an OS transistor.

[0422] Here, the same material can be used for the semiconductor layer 108 and the semiconductor layer 253. Alternatively, different materials can be used for these layers. For the structures of the semiconductor layer 108 and the semiconductor layer 253, the description of the semiconductor layer 108 and the semiconductor layer 208 in the semiconductor device 20 can also be referred to.

[0423] A transistor using silicon in a channel formation region (hereinafter also referred to as a Si transistor) can also be used as the transistor 250. For example, a transistor having LTPS in a semiconductor layer (hereinafter also referred to as an LTPS transistor) has high field-effect mobility and favorable frequency characteristics.

[0424] The transistor 100 has the same structure as that described above (see FIG. 1) except that a conductive layer 258a is included instead of the conductive layer 112a.

[0425] The conductive layer 258a functions as one of a source electrode and a drain electrode of the transistor 100 and also functions as one of a source electrode and a drain electrode of the transistor 250. When the conductive layer 258a is shared between the transistors 100 and 250, the area occupied by the semiconductor device can be reduced.

[0426] As described above, the transistor 100 is a vertical channel transistor. On the other hand, in the transistor 250, the current flowing through the semiconductor layer flows in the horizontal direction, that is, in a direction parallel or substantially parallel to the surface of the substrate 102. Such a transistor can be called a horizontal channel transistor.

[0427] In this manner, the semiconductor device of one embodiment of the present invention can have a structure including not only vertical channel transistors but also lateral channel transistors.

[0428] Note that the transistor 100 can also be formed in a region overlapping with the opening 257a. Specifically, an opening 146 can be provided in a region overlapping with the opening 257a, and the conductive layer 258a and the semiconductor layer 108 can be in contact with each other at the opening 257a. Furthermore, the conductive layer 258a can be omitted, and the region 253D and the semiconductor layer 108 can be in contact with each other at the opening 257a. With such a structure, a semiconductor device with a smaller occupation area can be obtained.

[0429] 21H is a circuit diagram of a semiconductor device 20C according to one embodiment of the present invention. FIG. 25A is a top view of the semiconductor device 20C. FIG. 25B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 25A.

[0430] The semiconductor device 20C includes a transistor 100 and a transistor 250. A gate of the transistor 250 is electrically connected to one of the source and the drain of the transistor 100.

[0431] The semiconductor device 20C is different from the semiconductor device 20B mainly in that the opening 146 overlaps with the conductive layer 255 functioning as the gate electrode of the transistor 250. Thus, in the semiconductor device 20B, the transistor 100 overlaps with the gate electrode of the transistor 250.

[0432] 25A and 25B , the opening 146 overlaps with the channel formation region, but this is not limiting. The opening 146 may be provided so as not to overlap with the channel formation region and to overlap with the conductive layer 255. In the semiconductor device 20C, the conductive layer 255 functions as a gate electrode of the transistor 250 and also as one of the source and drain electrodes of the transistor 100.

[0433] By providing the transistor 100 and the transistor 250 so that they overlap, a semiconductor device with a smaller occupation area can be realized.

[0434] The semiconductor device 20C differs from the semiconductor device 20B in the configurations of the opening 257a, the opening 257b, the conductive layer 258a, and the conductive layer 258b.

[0435] The openings 257a and 257b are formed by selectively removing parts of the insulating layer 254 and the insulating layer 110 in regions overlapping with the region 253D of the semiconductor layer 253. The conductive layers 258a and 258b are provided over the insulating layer 110 and are electrically connected to the region 253D through the openings 257a and 257b.

[0436] In the semiconductor device 20C, the conductive layers 258a and 258b can be formed in the same process as the conductive layer 112b. Since it is not necessary to form the conductive layers 258a and 258b and the conductive layer 112b in separate processes, the manufacturing process of the semiconductor device can be shortened, and productivity of the semiconductor device can be improved.

[0437] A semiconductor device of one embodiment of the present invention includes at least one transistor and at least one capacitor, and has a structure in which a source or a drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor. FIG. 21I illustrates an example in which the source or drain of the transistor 100 is electrically connected to one of the electrodes of the capacitor 190.

[0438] The transistor of one embodiment of the present invention is a type of vertical transistor, and since a source electrode, a semiconductor layer, and a drain electrode can be provided in a stacked manner, the occupied area can be significantly reduced compared to a planar transistor. Furthermore, by using a p-channel Si transistor as the planar transistor and an n-channel OS transistor as the vertical transistor, a complementary metal oxide semiconductor (CMOS) circuit can be configured. Furthermore, by using this structure and providing the planar transistor and the vertical transistor in a stacked manner, the occupied area of ​​the CMOS circuit can be reduced.

[0439] 26A illustrates an equivalent circuit diagram of a semiconductor device 30 according to one embodiment of the present invention. The semiconductor device 30 includes transistors 100_1 to 100_p (p is an integer greater than or equal to 2). The transistors 100_1 to 100_p are connected in parallel, and the semiconductor device 30 can be regarded as a single transistor.

[0440] Gate electrodes of the transistors 100_1 to 100_p are electrically connected to each other, source electrodes of the transistors 100_1 to 100_p are electrically connected to each other, and drain electrodes of the transistors 100_1 to 100_p are electrically connected to each other.

[0441] 26A illustrates the transistors 100_1 to 100_p as n-channel transistors, one embodiment of the present invention is not limited to this. The transistors 100_1 to 100_p can also be p-channel transistors.

[0442] A specific description will be given taking the case where p is 4 as an example. FIG. 26B shows an equivalent circuit diagram of a semiconductor device 30 which is one embodiment of the present invention. FIG. 26C shows a top view of the semiconductor device 30. FIG. 27 shows a cross-sectional view of the cut surface taken along dashed dotted line A3-A4 in FIG. 26C. FIG. 28 shows a perspective view of the semiconductor device 30.

[0443] The semiconductor device 30 includes transistors 100_1 to 100_4. The structure of the transistor 100 described above can be applied to each of the transistors 100_1 to 100_4. Note that although the transistor 100 is used as an example in the description here, one embodiment of the present invention is not limited thereto. Any of the transistors 100A to 100D can be applied to the transistors 100_1 to 100_4.

[0444] 26C and other figures show a configuration in which the transistors 100_1 to 100_4 are arranged in two rows and two columns, the arrangement of the transistors is not particularly limited. For example, the transistors 100_1 to 100_4 may be arranged in one row and four columns.

[0445] The transistors 100_1 to 100_4 each include a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 functions as a gate electrode of the transistors 100_1 to 100_4. Part of the insulating layer 106 functions as a gate insulating layer of the transistors 100_1 to 100_4. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistors 100_1 to 100_4, and the conductive layer 112b functions as the other.

[0446] FIG. 29A is a perspective view showing an extracted conductive layer 112a.

[0447] 29B is a perspective view illustrating the conductive layer 112a, the conductive layer 112b, the openings 141_1 to 141_4, and the openings 143_1 to 143_4. Note that the openings 141_1 to 141_4 provided in the insulating layer 110 are indicated by dashed lines. The openings 141_1 to 141_4 and the openings 143_1 to 143_4 can be described with reference to the description of the openings 141 and 143, and therefore detailed description thereof will be omitted.

[0448] When the semiconductor device 30 is considered as one transistor, the channel width of the transistor is the sum of the channel widths of the transistors 100_1 to 100_4. For example, if the top shapes of the openings 141_1 to 141_4 are circular, and the widths of the openings 141_1 to 141_4 are each defined as D141, the semiconductor device 30 can be considered as a transistor having a channel width of "D141×π×4" (see FIGS. 3A and 3B). The semiconductor device 30 including p transistors can be considered as a transistor having a channel width of "D141×π×p". Note that the semiconductor device 30 can be considered as a transistor having a channel length of L100 (see FIG. 3B). Connecting multiple transistors in parallel increases the channel width, thereby increasing the on-state current. Furthermore, the channel width can be varied by adjusting the number (p) of transistors connected in parallel. The number (p) of transistors connected in parallel can be determined so as to achieve a desired on-state current.

[0449] 29C is a perspective view illustrating the conductive layer 112a and the semiconductor layer 108. The semiconductor layer 108 is provided to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4. Note that although FIG. 29C and other drawings illustrate a structure in which the transistors 100_1 to 100_4 share the semiconductor layer 108, one embodiment of the present invention is not limited to this. The semiconductor layer 108 may be separate for each of the transistors 100_1 to 100_4.

[0450] 29D is a perspective view illustrating the conductive layer 112a and the conductive layer 104. The conductive layer 104 is provided to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4.

[0451] The configuration of the semiconductor device 30 shown in Configuration Example 2-5 can also be applied to other configuration examples. For example, the semiconductor device 30 can be applied to one or more of the transistors included in the semiconductor devices shown in FIGS.

[0452] 30A illustrates an equivalent circuit diagram of a semiconductor device 40 according to one embodiment of the present invention. The semiconductor device 40 includes transistors 100_1 to 100_q (q is an integer greater than or equal to 2). The transistors 100_1 to 100_q are connected in series, and the semiconductor device 40 can be regarded as a single transistor.

[0453] 30A illustrates the transistors 100_1 to 100_q as n-channel transistors, one embodiment of the present invention is not limited to this. The transistors 100_1 to 100_q can also be p-channel transistors.

[0454] A specific description will be given taking the case where q is 4 as an example. FIG. 30B shows an equivalent circuit diagram of a semiconductor device 40 according to one embodiment of the present invention. FIG. 30C shows a top view of the semiconductor device 40. FIG. 31 shows a cross-sectional view of the cut surface taken along dashed dotted line A5-A6 in FIG. 30C. FIG. 32 shows a perspective view of the semiconductor device 40.

[0455] The semiconductor device 40 includes transistors 100_1 to 100_4. The structure of the transistor 100 described above can be applied to each of the transistors 100_1 to 100_4. Note that although the transistor 100 is used as an example in the description here, one embodiment of the present invention is not limited thereto. Any of the transistors 100A to 100D can be applied to the transistors 100_1 to 100_4.

[0456] 30C and other figures show a configuration in which the transistors 100_1 to 100_4 are arranged in two rows and two columns, the arrangement of the transistors is not particularly limited. For example, the transistors 100_1 to 100_4 may be arranged in one row and four columns.

[0457] The transistor 100_1 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b. The conductive layer 112a functions as one of a source electrode and a drain electrode of the transistor 100_1, and the conductive layer 112b functions as the other electrode.

[0458] The transistor 100_2 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_2, a conductive layer 112a, and a conductive layer 112c. The conductive layer 112a serves as one of a source electrode and a drain electrode of the transistor 100_2, and the conductive layer 112c serves as the other electrode. The conductive layer 112a is shared by the transistor 100_1 and the transistor 100_2.

[0459] The transistor 100_3 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_3, a conductive layer 112c, and a conductive layer 112d. The conductive layer 112c serves as one of a source electrode and a drain electrode of the transistor 100_3, and the conductive layer 112d serves as the other electrode. The conductive layer 112c is shared by the transistors 100_2 and 100_3.

[0460] The transistor 100_4 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_4, a conductive layer 112d, and a conductive layer 112e. The conductive layer 112d functions as one of a source electrode and a drain electrode of the transistor 100_4, and the conductive layer 112e functions as the other. The conductive layer 112d is shared by the transistors 100_3 and 100_4.

[0461] 33A is a perspective view showing the conductive layer 112a and the conductive layer 112d. The conductive layer 112a and the conductive layer 112d can be formed in the same process.

[0462] 33B is a perspective view illustrating the conductive layers 112a, 112b, 112c, 112d, and 112e, the openings 141 to 1414, and the openings 1431 to 1434. The conductive layers 112a to 112e can be formed in the same process. The conductive layer 112b has an opening 1431, the conductive layer 112c has openings 1432 and 1433, and the conductive layer 112e has an opening 1434.

[0463] 33C is a perspective view illustrating the conductive layer 112a, the conductive layer 112d, and the semiconductor layers 108_1 to 108_4. The semiconductor layers 108_1 to 108_4 can be formed in the same process.

[0464] 33D is a perspective view illustrating the conductive layer 112a, the conductive layer 112d, and the conductive layer 104. The conductive layer 104 functions as a gate electrode of the transistors 100_1 to 100_4.

[0465] One of the source electrode and the drain electrode of the transistor 100_1 is electrically connected to one of the source electrode and the drain electrode of the transistor 100_2. The other of the source electrode and the drain electrode of the transistor 100_2 is electrically connected to one of the source electrode and the drain electrode of the transistor 100_3. The other of the source electrode and the drain electrode of the transistor 100_3 is electrically connected to one of the source electrode and the drain electrode of the transistor 100_4.

[0466] When the semiconductor device 40 is regarded as a single transistor, the channel length of the transistor is the sum of the channel lengths of the transistors 100_1 to 100_4. For example, if the channel length of each of the transistors 100_1 to 100_4 is L100, the semiconductor device 40 can be regarded as a transistor having a channel length of "L100×4" (see FIG. 3B). The semiconductor device 40, which is composed of q transistors, can be regarded as a transistor having a channel length of "L100×q". Note that the semiconductor device 40 can be regarded as a transistor having a channel width W100 (see FIGS. 3A and 3B). By connecting multiple transistors in series, the channel length is increased, thereby improving saturation. Furthermore, the channel lengths can be varied by adjusting the number (q) of transistors connected in series. The number (q) of transistors connected in series can be determined so as to achieve the desired saturation.

[0467] The configuration of the semiconductor device 40 shown in Configuration Example 2-6 can also be applied to other configuration examples. For example, the semiconductor device 40 can be applied to one or more of the transistors included in the semiconductor devices shown in FIGS.

[0468] The semiconductor device 40 can be applied to each transistor included in the semiconductor device 30. That is, a configuration can be achieved in which a group of parallel-connected transistors are further connected in series (hereinafter also referred to as series-parallel connection).

[0469] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0470] 34A to 37. Note that with regard to materials and formation methods of elements, descriptions of parts similar to those described in Embodiment 1 may be omitted.

[0471] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, etc. CVD methods include a PECVD method and a thermal CVD method. One type of thermal CVD method is a metal organic chemical vapor deposition (MOCVD) method.

[0472] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0473] When processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film can be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film can be directly formed by a film formation method using a shielding mask such as a metal mask.

[0474] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0475] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other examples include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0476] The thin film can be etched by one or more of dry etching, wet etching, and sandblasting.

[0477] 15A and 15B will be described with reference to Fig. 34A to Fig. 37. Fig. 34A to Fig. 37 show a cross-sectional view taken along dashed dotted line A1-A2 and a cross-sectional view taken along dashed dotted line B1-B2 shown in Fig. 1A side by side.

[0478] First, the insulating layer 109 is formed over the substrate 102. The insulating layer 109 can be formed by a sputtering method or a PECVD method.

[0479] Next, a conductive film to be the conductive layer 112a is formed over the insulating layer 109 and processed to form the conductive layer 112a (FIG. 34A). The conductive film can be preferably formed by sputtering.

[0480] Subsequently, an insulating film 110af that will become the insulating layer 110a and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112a (FIG. 34B).

[0481] The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This can prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic substances. For example, after forming the insulating film 110af, it is preferable to form the insulating film 110bf continuously using the same device.

[0482] The substrate temperature during the formation of the insulating films 110af and 110bf is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, further preferably 350° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating films 110af and 110bf within the above-described range, the amount of impurities (e.g., water and hydrogen) released from the insulating films 110af and 110bf can be reduced, and the diffusion of the impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0483] Since the insulating films 110af and 110bf are formed before the semiconductor layer 108, there is no need to worry about oxygen being desorbed from the semiconductor layer 108 due to heat applied when the insulating films 110af and 110bf are formed.

[0484] After the insulating films 110af and 110bf are formed, heat treatment can be performed. By performing the heat treatment, impurities (for example, water and hydrogen) can be removed from the insulating films 110af and the insulating films 110bf and from their surfaces.

[0485] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. Examples of methods for supplying oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment. For the plasma treatment, an apparatus that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of apparatus that convert gas into plasma using high-frequency power include a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus. The plasma treatment is preferably performed in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N ２ O), nitrogen dioxide (NO ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of carbon monoxide, carbon dioxide, and / or arsenic.

[0486] After the insulating film 110bf is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can improve productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, N ２ O plasma treatment can be performed.

[0487] Next, a film 139 is preferably formed on the insulating film 110bf (FIG. 34D). The film 139 can be formed by a sputtering method. By forming the film 139 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf. FIG. 34C shows, with arrows, a schematic diagram of oxygen being supplied to the insulating film 110bf.

[0488] The conductivity of the film 139 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 139.

[0489] The film 139 is preferably formed using an oxide material containing one or more elements that are the same as those of the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be used for the semiconductor layer 108.

[0490] When forming the film 139, the amount of oxygen supplied to the insulating film 110bf can be increased by increasing the oxygen flow rate of the film formation gas introduced into the treatment chamber of the film formation apparatus or the oxygen partial pressure in the treatment chamber. The oxygen flow rate or oxygen partial pressure is, for example, preferably 50% to 100%, more preferably 60% to 100%, even more preferably 70% to 100%, still more preferably 80% to 100%, and even more preferably 90% to 100%. In particular, it is preferable to set the oxygen flow rate to 100% and the oxygen partial pressure as close to 100% as possible.

[0491] In this way, by forming the film 139 by a sputtering method in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the film 139, and oxygen desorption from the insulating film 110bf can be prevented. As a result, a large amount of oxygen can be confined in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0492] Heat treatment may be performed after the film 139 is formed. By performing heat treatment after the film 139 is formed, oxygen can be effectively supplied from the film 139 to the insulating film 110bf.

[0493] The temperature of the heat treatment is preferably 150° C. or higher and lower than the strain point of the substrate, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 400° C. or lower, and further preferably 350° C. or higher and 400° C. or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the nitrogen-containing atmosphere or the oxygen-containing atmosphere, dry air (CDA: Clean Dry Air) can be used. Note that the content of hydrogen, water, and the like in the atmosphere is preferably as low as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower. Using an atmosphere containing as little hydrogen, water, and the like as possible can prevent hydrogen, water, and the like from being taken into the insulating films 110af and 110bf as much as possible. The heat treatment can be performed using an oven, a rapid thermal annealing (RTA) device, etc. By using an RTA device, the heat treatment time can be shortened.

[0494] After the film 139 is formed or after the above-described heat treatment, oxygen can be further supplied to the insulating film 110bf through the film 139. Oxygen can be supplied by, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. The above description of the plasma treatment can be referred to, and therefore, detailed description thereof will be omitted.

[0495] Next, the film 139 is removed ( FIG. 34E ). Although there is no particular limitation on the method for removing the film 139, a wet etching method can be suitably used. By using the wet etching method, etching of the insulating film 110bf can be suppressed when removing the film 139. This can suppress the thickness of the insulating film 110bf from becoming thin, and can make the thickness of the insulating layer 110b uniform.

[0496] The process of supplying oxygen to the insulating film 110bf is not limited to the above-described method. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied to the insulating film 110bf by ion doping, ion implantation, or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through the film. The film is preferably removed after oxygen is supplied. The film that suppresses oxygen desorption can be a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten.

[0497] Next, an insulating film 110cf that will become the insulating layer 110c and an insulating film 110ef that will become the insulating layer 110e are formed on the insulating film 110bf ( FIG. 35A ). The insulating film 110cf can be preferably formed by sputtering. The description of the formation of the insulating films 110af and 110bf can be referenced for the formation of the insulating films 110cf and 110ef, and therefore detailed description thereof will be omitted.

[0498] Next, a conductive film 112bf to be the conductive layer 112b is formed over the insulating film 110ef (FIG. 35B). The conductive film 112bf can be preferably formed by sputtering.

[0499] Next, the conductive film 112bf is processed to form the conductive layer 112B (FIG. 35C). The conductive layer 112B will later become the conductive layer 112b. The conductive layer 112B can be preferably formed by, for example, wet etching.

[0500] Subsequently, a part of the conductive layer 112B is removed to form a conductive layer 112b having an opening 143. The conductive layer 112b can be preferably formed by wet etching.

[0501] Subsequently, portions of the insulating films 110af, 110bf, and 110cf are removed to form the insulating layer 110 having an opening 141 ( FIG. 35D ). The opening 141 is provided in a region overlapping with the opening 143. The formation of the opening 141 exposes the conductive layer 112a. The insulating layer 110 can be preferably formed by dry etching.

[0502] The opening 141 can be formed using, for example, the resist mask used to form the opening 143. Specifically, a resist mask is formed over the conductive layer 112B, part of the conductive layer 112B is removed using the resist mask to form the opening 143, and part of the insulating films 110af, 110bf, and 110cf is removed using the resist mask to form the opening 141. The opening 141 can also be formed using a resist mask different from the resist mask used to form the opening 143.

[0503] Next, a metal oxide film 108f to be the semiconductor layer 108 is formed so as to cover the openings 141 and 143 ( FIG. 36A ). The metal oxide film 108f is provided in contact with the upper and side surfaces of the conductive layer 112b, the upper and side surfaces of the insulating layer 110, and the upper surface of the conductive layer 112a.

[0504] The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed by an ALD method. Because the ALD method has high coverage, it can be suitably used to form the metal oxide film 108f that covers the openings 141 and 143. By using the ALD method, a metal oxide film can be formed with high coverage also on the side surfaces of the insulating layer 110. Furthermore, the ALD method makes it easy to control the film formation rate, so a thin film can be formed with a high yield. Therefore, the ALD method is particularly suitable when the metal oxide film 108f is thin. Instead of the sputtering method and the ALD method, a CVD method can also be used to form the metal oxide film 108f.

[0505] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film in which impurities including hydrogen are reduced as much as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0506] When the metal oxide film 108f is formed, oxygen gas is preferably used. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0507] By supplying oxygen to the insulating layer 110b, oxygen is supplied to the semiconductor layer 108 in a later step, and oxygen vacancies and V Ｏ H can be reduced.

[0508] The metal oxide film 108f can be formed by mixing oxygen gas with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas when forming the metal oxide film, the higher the crystallinity of the metal oxide film, and thus a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow rate ratio or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, and thus a transistor with a large on-state current can be realized.

[0509] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the crystal grain boundaries become recombination centers, and carriers are captured, which may reduce the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film 108f does not become polycrystalline. Since the ease with which the metal oxide film becomes polycrystalline differs depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure depending on the composition of the metal oxide film 108f.

[0510] The higher the substrate temperature during formation of the metal oxide film, the higher the crystallinity and density of the metal oxide film, which leads to a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film, which leads to a transistor with a large on-state current.

[0511] The substrate temperature during the formation of the metal oxide film 108f is preferably from room temperature to 250° C., more preferably from room temperature to 200° C., and even more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to 140° C. is preferable because productivity is increased. Furthermore, by forming the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

[0512] Note that if the substrate temperature is too high, the metal oxide film may have a polycrystalline structure. It is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film 108f.

[0513] When the ALD method is used, it is preferable to use a film formation method such as a thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it not only exhibits high coverage but also allows low-temperature film formation.

[0514] The metal oxide film can be formed by, for example, the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0515] For example, when forming an In—Ga—Zn oxide, three precursors, namely, a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, namely, a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0516] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amido]-indium.

[0517] Gallium-containing precursors include, for example, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0518] Precursors containing aluminum include, for example, aluminum chloride and trimethylaluminum.

[0519] Tin-containing precursors include, for example, tin(IV) chloride and tetrakis(dimethylamido)tin.

[0520] Precursors containing zinc include, for example, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0521] Oxidizing agents include, for example, ozone, oxygen, and water.

[0522] The composition of the resulting film can be controlled by adjusting one or more of the types of source gases, the flow rate ratio of the source gases, the time for which the source gases are flowed, and the order in which the source gases are flowed. By adjusting these, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these, it is also possible to form a metal oxide film 108f whose composition changes continuously.

[0523] Before forming the metal oxide film 108f, it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere. Alternatively, plasma treatment in an atmosphere containing oxygen may be performed. Alternatively, dinitrogen monoxide (N ２ Oxygen may be supplied to the insulating layer 110 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (NO). When plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such treatment, it is preferable to form the metal oxide film 108f continuously without exposing the surface of the insulating layer 110 to the air.

[0524] In addition, when the semiconductor layer 108 has a stacked structure, it is preferable to form a metal oxide film first, and then form a next metal oxide film in succession without exposing the surface of the first metal oxide film to the air.

[0525] When the semiconductor layer 108 has a stacked structure, all layers constituting the semiconductor layer 108 can be formed by the same deposition method (for example, sputtering or ALD). Alternatively, different deposition methods can be used for different layers. For example, the first metal oxide layer can be formed by sputtering, and the second metal oxide layer can be formed by ALD.

[0526] Subsequently, the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 (FIG. 36B).

[0527] The semiconductor layer 108 can be preferably formed by wet etching. At this time, a part of the conductive layer 112b in a region that does not overlap with the semiconductor layer 108 may be etched and thinned. Similarly, a part of the insulating layer 110 in a region that does not overlap with both the semiconductor layer 108 and the conductive layer 112b may be etched and thinned. For example, the insulating layer 110c of the insulating layer 110 may be removed by etching, and the surface of the insulating layer 110b may be exposed. Note that, in etching the metal oxide film 108f, using a material with a high etching selectivity for the insulating layer 110c can prevent the insulating layer 110c from becoming thin.

[0528] Heat treatment is preferably performed after the metal oxide film 108f is formed or after the metal oxide film 108f is processed into the semiconductor layer 108. The heat treatment can remove hydrogen and water contained in or adsorbed on the surface of the metal oxide film 108f or the semiconductor layer 108. Furthermore, the heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (for example, reduce defects or improve crystallinity).

[0529] By the heat treatment, oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108. In this case, it is preferable to perform the heat treatment before processing into the semiconductor layer 108. The above description can be referred to for the heat treatment, and therefore detailed description thereof will be omitted.

[0530] Note that this heat treatment does not have to be performed if it is not necessary. Alternatively, the heat treatment may be omitted here and may be combined with a heat treatment performed in a later step. Furthermore, a high-temperature treatment in a later step (e.g., a film formation step) may also serve as this heat treatment.

[0531] Subsequently, the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110 (FIG. 36C). The insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.

[0532] When an oxide semiconductor is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses oxygen diffusion. The insulating layer 106 has a function of suppressing oxygen diffusion, which suppresses oxygen from diffusing from above the insulating layer 106 to the conductive layer 104, thereby suppressing oxidation of the conductive layer 104. As a result, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0533] By increasing the temperature during the formation of the insulating layer 106 that functions as a gate insulating layer, the insulating layer can have fewer defects. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the semiconductor layer 108, causing oxygen vacancies and V in the semiconductor layer 108. Ｏ H may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. or higher and 450° C. or lower, more preferably 200° C. or higher and 450° C. or lower, further preferably 250° C. or higher and 450° C. or lower, further preferably 300° C. or higher and 450° C. or lower, and further preferably 300° C. or higher and 400° C. or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

[0534] Before forming the insulating layer 106, plasma treatment may be performed on the surface of the semiconductor layer 108. The plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. Furthermore, the plasma treatment and the formation of the insulating layer 106 are preferably performed successively without exposure to the air.

[0535] Next, an impurity element 189 is supplied to the semiconductor layer 108 (FIG. 37). By supplying the impurity element 189, a region 108Da and a region 108Db are formed.

[0536] The impurity element 189 is preferably supplied from a direction perpendicular or substantially perpendicular to the upper surface of the substrate 102. In this case, as described above, the amount of the impurity element supplied to a region of the semiconductor layer 108 that is inclined with respect to the upper surface of the substrate 102 is smaller than that to a region that is parallel or substantially parallel to the upper surface of the substrate 102. That is, the amount of the impurity element supplied to the source and drain regions of the semiconductor layer 108 is larger than that to the channel formation region. Therefore, the electrical resistance of the source and drain regions can be preferentially reduced. By supplying the impurity element 189 to the semiconductor layer 108, oxygen vacancies (V Ｏ Alternatively, when the impurity element 189 is supplied to the semiconductor layer 108, oxygen vacancies (V Ｏ ) may be combined.

[0537] Furthermore, the impurity element 189 is preferably supplied to the semiconductor layer 108 through the insulating layer 106. The thickness of the insulating layer 106 in the direction in which the impurity element 189 is supplied varies depending on the location. Therefore, the semiconductor layer 108 has regions where the amount of the impurity element 189 is large and regions where the amount of the impurity element 189 is small. Specifically, the amount of the impurity element supplied is larger in a region of the semiconductor layer 108 provided along the top surface of the conductive layer 112a or the top surface of the conductive layer 112b than in a region provided along the side surface of the insulating layer 110. In this way, the impurity element can be prevented from being supplied to the channel formation region of the semiconductor layer 108, and the electrical resistance of the source region and the drain region can be preferentially reduced. At this time, the impurity element 189 is also supplied to the insulating layer 106.

[0538] The elements that can be used as the impurity element 189 are as described above.

[0539] As described above, the impurity element 189 can be preferably supplied by plasma ion doping or ion implantation.

[0540] The purity of the supplied impurity element can be increased by using an ion implantation method in which a source gas is ionized and the ions are mass-separated and supplied. When using the ion implantation method, it is preferable to use the first element described above as the impurity element 189, and it is more preferable to use boron or phosphorus. By using an element that becomes stable when bonded with oxygen as the impurity element 189, it is possible to realize the regions 108Da and 108Db that are stable and have low electrical resistance.

[0541] The productivity can be improved by using a plasma ion doping method in which the impurity element 189 is supplied without mass separation. When the plasma ion doping method is used, it is preferable to use both the first element and hydrogen as the impurity element 189, and it is more preferable to use both boron or phosphorus and hydrogen. By using both an element that becomes stable when bonded with oxygen and hydrogen as the impurity element 189, the electrical resistance of the regions 108Da and 108Db can be easily reduced and the low electrical resistance can be stably maintained.

[0542] The ion implantation equipment or ion doping equipment used to supply the impurity element 189 is also used in the manufacture of Si transistors such as LTPS transistors, so that the equipment in the existing LTPS production line can be utilized, which is preferable because no new capital investment is required. This reduces the initial capital investment costs involved in the manufacture of semiconductor devices. Furthermore, boron and phosphorus are particularly preferable because they are used in the ion implantation equipment or ion doping equipment in the Si transistor production line and do not require any new capital investment.

[0543] In the supplying treatment of the impurity element 189, the treatment conditions are preferably controlled so that the concentration of the impurity element in a portion of the semiconductor layer 108 that overlaps with the conductive layer 112 a or the conductive layer 112 b is higher than the concentration of the impurity element in other regions. This allows the impurity element 189 at an optimum concentration to be supplied to the source and drain regions of the semiconductor layer 108.

[0544] As a source gas of the impurity element 189, a gas containing the above-mentioned impurity element can be used. ２ H ６ Gas, BF ３ In addition, when phosphorus is supplied, a typical example is a PH ３ A mixed gas obtained by diluting these source gases with hydrogen or a noble gas may also be used.

[0545] Other raw material gases include CH ４ , N ２ , N.H. ３ , AlH ３ , AlCl ３ , SiH ４ , Si ２ H ６ , F ２ , H.F., H. ２ , (C ５ H ５ ) ２ Mg, noble gases, etc. can be used. The raw material used to supply the impurity element is not limited to a gas, and a solid or liquid can also be heated and vaporized for use.

[0546] For example, it is preferable to use a gas containing boron and hydrogen to supply boron and hydrogen as the impurity element 189. In this case, the impurity element 189 can be supplied without mass separation, and the electrical resistance of the semiconductor layer 108 can be easily reduced, which is preferable because it is possible to improve both the productivity and characteristics of the semiconductor device.

[0547] The supply of the impurity element 189 can be controlled by setting conditions such as acceleration energy and dose amount in consideration of the type of the impurity element 189, the composition, film density, thickness, and the like of each of the insulating layer 106 and the semiconductor layer 108.

[0548] The method for supplying the impurity element 189 is not limited, and for example, plasma treatment or treatment using thermal diffusion due to heating can be used. In the case of plasma treatment, the impurity element can be supplied by generating plasma in a gas atmosphere containing the impurity element to be supplied and performing plasma treatment. As an apparatus for generating the plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, or the like can be used.

[0549] In one embodiment of the present invention, the impurity element 189 is supplied to the semiconductor layer 108 through the insulating layer 106. This can prevent the crystallinity of the semiconductor layer 108 from decreasing when the impurity element 189 is supplied. Therefore, an increase in electrical resistance due to a decrease in crystallinity can be prevented.

[0550] Furthermore, if the insulating layer 106 is formed after the impurity element 189 is supplied, the inside of a deposition chamber for the insulating layer 106 may be contaminated. For this reason, it is preferable to supply the impurity element 189 after the insulating layer 106 is formed.

[0551] On the other hand, the impurity element 189 can be directly supplied to the semiconductor layer 108, and then the insulating layer 106 can be formed over the semiconductor layer 108. This can prevent the insulating layer 106 from being damaged by the supply of the impurity element 189.

[0552] The supplying step of the impurity element 189 is preferably performed while heating the substrate 102. This allows damage to the semiconductor layer 108 that occurs when the impurity element 189 is supplied to be repaired. That is, the supplying of the impurity element 189 to the semiconductor layer 108 and the repairing of damage caused by the supplying can be performed in parallel. Furthermore, damage to the insulating layer 106 that occurs when the impurity element 189 is supplied can also be repaired. Note that one embodiment of the present invention is not limited thereto, and the supplying step of the impurity element 189 can be performed without heating the substrate 102.

[0553] The substrate temperature in the supplying step of the impurity element 189 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or even more preferably 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.

[0554] Heat treatment can be performed after supplying the impurity element 189. By performing the heat treatment, damage to the semiconductor layer 108 and the insulating layer 106 caused in the step of supplying the impurity element 189 can be repaired.

[0555] If the temperature of the heat treatment is too high, the electrical resistance of the region 108Da, the electrical resistance of the region 108Db, the contact resistance between the region 108Da and the conductive layer 112a, and the contact resistance between the region 108Db and the conductive layer 112b may increase. Therefore, the temperature of the heat treatment after supplying the impurity element 189 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, further preferably 200°C or higher and 450°C or lower, further preferably 250°C or higher and 400°C or lower, further preferably 250°C or higher and 350°C or lower, or 300°C or higher and 400°C or lower, and further preferably 300°C or higher and 350°C or lower.

[0556] By using an element that becomes stable by bonding with oxygen as the impurity element 189, it is possible to prevent the impurity element 189 from being desorbed in the heat application process. Therefore, after the impurity element 189 is supplied, the electrical resistance of the regions 108Da and 108Db can be kept low even after the heat application process.

[0557] Subsequently, the conductive layer 104 is formed over the insulating layer 106 (FIGS. 15A and 15B). The conductive film that becomes the conductive layer 104 can be preferably formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.

[0558] Through the above steps, the semiconductor device 10C of one embodiment of the present invention can be manufactured.

[0559] <Fabrication Method Example 2> Here, a fabrication method for a structure in which the regions 108Da and 108Db contain a second element in addition to a first element will be described. Note that descriptions of parts that overlap with the above-described <Fabrication Method Example 1> will be omitted, and differences will be described.

[0560] 38A and 38B show a cross-sectional view taken along dashed dotted line A1-A2 and a cross-sectional view taken along dashed dotted line B1-B2 shown in FIG. 1A side by side.

[0561] First, similarly to Manufacturing Method Example 1, steps are performed up to the formation of the insulating layer 106. Since the description of FIGS. 34A and 36C can be referred to for the steps up to the formation of the insulating layer 106, detailed description thereof will be omitted.

[0562] Next, an impurity element 187 is supplied to the semiconductor layer 108 ( FIG. 38A ). The impurity element 187 is preferably the second element described above, and argon is preferably used. By supplying the impurity element 187, regions 108Ea and 108Eb containing the second element are formed. Later, the region 108Ea becomes the region 108Da, and the region 108Eb becomes the region 108Db.

[0563] The impurity element 187 can be supplied by the same method as that used for supplying the impurity element 189. A plasma ion doping method or an ion implantation method can be suitably used for supplying the impurity element 187. The supply of the impurity element 187 can be controlled by setting conditions such as acceleration energy and dose amount in consideration of the type of the impurity element 187, the composition, film density, thickness, and the like of the insulating layer 106 and the semiconductor layer 108.

[0564] The impurity element 187 is preferably supplied from a direction perpendicular or approximately perpendicular to the top surface of the substrate 102. For the supply of the impurity element 187, the above description of the supply of the impurity element 189 can be referred to.

[0565] By supplying the impurity element 187, the bond between the metal and oxygen of the metal oxide is broken in the region 108Ea which becomes the region 108Da and the region 108Eb which becomes the region 108Db. In addition, the breaking of the bond between the metal and oxygen causes oxygen deficiency (V Ｏ ) occurs. Then, by supplying the first element to the regions 108Ea and 108Eb, the first element can efficiently bond with oxygen. Therefore, the electrical resistance of the regions 108Da and 108Db can be efficiently reduced.

[0566] Next, an impurity element 189 is supplied to the semiconductor layer 108 ( FIG. 38B ). By supplying the impurity element 189, regions 108Da and 108Db are formed. The regions 108Da and 108Db each contain a first element and a second element.

[0567] The supply conditions of the impurity element 189 can be made different from the supply conditions of the impurity element 187. It is preferable to set conditions such as acceleration energy and dose amount depending on the type of the first element and the type of the second element. Note that the supply conditions of the impurity element 187 and the impurity element 189 can also be made the same.

[0568] Although an example in which the first element and the second element are supplied in different steps has been described here, one embodiment of the present invention is not limited thereto and may be configured to supply the first element and the second element in the same step.

[0569] Subsequently, the conductive layer 104 is formed on the insulating layer 106 (FIGS. 15A and 15B). For the formation of the conductive layer 104, the above description can be referred to.

[0570] Through the above steps, the semiconductor device 10C of one embodiment of the present invention can be manufactured.

[0571] This embodiment mode can be combined with other embodiment modes as appropriate.

[0572] Embodiment 3 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0573] The display device of this embodiment can be a high-resolution display device or a large-sized display device. Therefore, the display device of this embodiment can be used as a display unit for electronic devices having relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0574] The display device of the present embodiment can be a high-definition display device, and can therefore be used, for example, as a display unit for a wristwatch-type or bracelet-type information terminal (wearable device), as well as a display unit for a wearable device that can be worn on the head, such as a head-mounted display (HMD) for VR, or a glasses-type AR device.

[0575] The semiconductor device of one embodiment of the present invention can be used for a display device or a module including the display device. Examples of the module including the display device include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0576] The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also referred to as sensor elements) that can detect the proximity or contact of a detection target such as a finger can be applied to the display device.

[0577] Examples of sensor types include a capacitance type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type.

[0578] The capacitance type includes, for example, a surface capacitance type and a projected capacitance type. The projected capacitance type includes, for example, a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferred because it enables simultaneous multi-point detection.

[0579] Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel is a type in which electrodes constituting a detection element are provided on one or both of a substrate supporting a display element and an opposing substrate.

[0580] <Display Device 50A> FIG. 39 shows a perspective view of the display device 50A.

[0581] The display device 50A has a configuration in which a substrate 152 and a substrate 151 are bonded together. In Fig. 39, the substrate 152 is indicated by a dashed line.

[0582] The display device 50A has a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, etc. Fig. 39 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Fig. 39 can also be said to be a display module having the display device 50A, an IC, and an FPC.

[0583] The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 39 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

[0584] The circuit portion 164 includes, for example, a scan line driver circuit (also referred to as a gate driver). Alternatively, the circuit portion 164 may include both a scan line driver circuit and a signal line driver circuit (also referred to as a source driver).

[0585] The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside through the FPC 172 or are input to the conductive layer 165 from the IC 173.

[0586] 39 shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like. The IC 173 may be, for example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit. The display device 50A and the display module may be configured without an IC. The IC may also be mounted on an FPC by a COF method, or the like.

[0587] The semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50A. An oxide semiconductor (OS) can be suitably used for a channel formation region of a transistor included in the display device. By using an OS transistor, the display device can have low power consumption. Furthermore, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all of the transistors included in the display device can be OS transistors. By using OS transistors for all of the transistors included in the display device in this manner, an effect of reducing manufacturing costs can be obtained.

[0588] For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, resulting in a high-resolution display device. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, resulting in a display device with a narrow frame. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0589] The display section 162 is an area in the display device 50A that displays an image, and has a plurality of periodically arranged pixels 201. Fig. 39 shows an enlarged view of one pixel 201.

[0590] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied, such as a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0591] 39 includes a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light,...

Claims

a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer; the first insulating layer overlies the first conductive layer; the first insulating layer has a first opening reaching the first conductive layer; the second conductive layer is located on the first insulating layer; the second conductive layer has a second opening in a region overlapping with the first opening; the semiconductor layer has, in the first opening, a first region in contact with an upper surface of the first conductive layer and a second region in contact with a side surface of the first insulating layer; the second insulating layer is located on the semiconductor layer; the third conductive layer has a region overlapping with the semiconductor layer via the second insulating layer, the first region and the second insulating layer each have a first element; the first element is boron or phosphorus; The concentration of the first element in the second region is 1×10 −３ It is less than double, a side surface of the first insulating layer in the first opening and a top surface of the first conductive layer form an angle of 66 degrees or more and 90 degrees or less. In claim 1, the semiconductor layer has a region in contact with a side surface of the second conductive layer in the second opening and a third region in contact with a top surface of the second conductive layer; the third region has the first element; The concentration of the first element in the second region is 1×10 4 of the concentration of the first element in the third region. −３ 4. A semiconductor device, comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer; the first insulating layer overlies the first conductive layer; the first insulating layer has a first opening reaching the first conductive layer; the second conductive layer is located on the first insulating layer; the second conductive layer has a second opening in a region overlapping with the first opening; the semiconductor layer has, in the first opening, a first region in contact with an upper surface of the first conductive layer and a second region in contact with a side surface of the first insulating layer; the second insulating layer is located on the semiconductor layer; the third conductive layer has a region overlapping with the semiconductor layer via the second insulating layer, the first region and the second insulating layer each have a first element; the first element is boron or phosphorus; The concentration of the first element in the second region is 1×10 −３ It is less than double, A semiconductor device, wherein in a direction perpendicular to an upper surface of the first conductive layer, a thickness of a portion of the second insulating layer that contacts the second region is 2.5 times or more a thickness of a portion of the second insulating layer that contacts the first region. In claim 3, the semiconductor layer has a region in contact with a side surface of the second conductive layer in the second opening and a third region in contact with a top surface of the second conductive layer; the third region has the first element; A semiconductor device, wherein a thickness of a portion of the second insulating layer that contacts the second region in a direction perpendicular to an upper surface of the first conductive layer is 2.5 times or more a thickness of a portion of the second insulating layer that contacts the third region. In any one of claims 1 to 4, the first region comprises hydrogen; A semiconductor device, wherein a concentration of hydrogen in the first region is higher than a concentration of hydrogen in the second region. In any one of claims 1 to 4, the first region has a second element; the second element is argon, krypton or xenon; A semiconductor device, wherein a concentration of the second element in the first region is higher than a concentration of the second element in the second region. In any one of claims 1 to 4, The semiconductor device, wherein the semiconductor layer comprises a metal oxide. In any one of claims 1 to 4, the first insulating layer includes a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer; the third insulating layer and the fifth insulating layer each include silicon and nitrogen; The fourth insulating layer comprises silicon and oxygen. In any one of claims 1 to 4, the first insulating layer includes a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer; the third insulating layer comprises silicon and nitrogen; the fourth insulating layer comprises silicon and oxygen; The fifth insulating layer comprises one or both of aluminum and hafnium, and oxygen. forming a first conductive layer; forming a first insulating film on the first conductive layer; forming a first conductive film on the first insulating film; processing the first conductive film and the first insulating film to form a first insulating layer having a first opening reaching the first conductive layer and to form a second conductive layer having a second opening overlapping the first opening; forming a semiconductor layer on the first conductive layer, the first insulating layer, and the second conductive layer; forming a second insulating layer on the semiconductor layer; supplying a first element to the semiconductor layer through the second insulating layer by using a plasma ion doping method or an ion implantation method; forming a third conductive layer on the second insulating layer; the first element is boron or phosphorus; the semiconductor layer has a first region in contact with an upper surface of the first conductive layer and a second region in contact with a side surface of the first insulating layer; the first region and the second insulating layer each have the first element; Pa expressed by the following formula (1) is 1×10 −３ The following is a method for manufacturing a semiconductor device. (In formula (1), θ is less than 90 degrees and represents the angle between a side surface of the first opening of the first insulating layer and the top surface of the first conductive layer. α is a real number greater than 0 and represents a ratio of a standard deviation to a projected range of ions in the supply of the first element. β is a real number greater than 0 and represents a ratio, in a direction perpendicular to the top surface of the first conductive layer, of a thickness of a portion of the second insulating layer provided along a side surface of the first insulating layer to a thickness of a portion of the second insulating layer provided along the top surface of the first conductive layer.) In claim 10, supplying a second element to the semiconductor layer through the second insulating layer by using a plasma ion doping method or an ion implantation method before supplying the first element; The second element is argon, krypton or xenon.