Semiconductor module

Abstract

This semiconductor module includes: a first logic chip including a first surface and a second surface which are parallel to a first direction and a second direction; a first semiconductor chip including a third surface and a fourth surface which are parallel to the second surface, the third surface being disposed on the second surface, and electrically connected to the first logic chip; and a first semiconductor cube disposed on the fourth surface and including a plurality of second semiconductor chips stacked in the first direction, wherein the second semiconductor chip includes a first inductor disposed in a third direction orthogonal to the first direction and the second direction, the first semiconductor chip includes a plurality of routers and a second inductor disposed parallel to the fourth surface, and a plurality of circuits in the first logic chip and a plurality of circuits in the first semiconductor chip are connected by using the plurality of routers and are capable of non-contact communication with the plurality of second semiconductor chips.

Description

Semiconductor Module

[0001] An embodiment of the present invention relates to a semiconductor module.

[0002] In recent years, the power consumption of electronic computers, such as those used in data centers, has been increasing rapidly. Furthermore, as data communication volume increases, the power consumption of electronic computers has also increased, and the memory capacity of electronic computers has also increased, leading to a growing demand for electronic computers with lower power consumption and larger capacity. For example, an electronic computer may include multiple logic chips and multiple memory chips electrically connected to the multiple logic chips. The logic chip is, for example, a semiconductor chip on which a logic circuit is implemented, and the memory chip is, for example, a semiconductor chip on which a memory circuit is implemented. Data communication in an electronic computer is performed, for example, between the logic chip and the memory chip. For example, stacking the logic chip and the memory chip for three-dimensional implementation to shorten the distance between the logic chip and the memory chip is one effective solution for reducing the power consumption of an electronic computer.

[0003] Patent Documents 1 to 6 disclose, as examples of three-dimensional packaging methods, semiconductor modules in which a structure (vertically stacked memory cube) in which multiple memory chips are stacked is arranged on a substrate or logic chip so that the multiple memory chips are parallel to the substrate or logic chip, or semiconductor modules in which a structure (horizontally stacked memory cube) in which multiple memory chips are stacked on a substrate or logic chip so that the multiple memory chips are perpendicular to the substrate or logic chip is vertically mounted on the substrate or logic chip. The vertically stacked memory cubes disclosed in Patent Documents 1 to 3 are electrically connected to the substrate or logic chip using, for example, TSVs or microbumps. Patent Documents 5 and 6 also disclose techniques for contactless communication between a chip and a substrate.

[0004] Japanese Patent Application Publication No. 2012-156478 Japanese Patent Application Publication No. 2019-057528 Japanese Patent Application Publication No. 2011-086767 Japanese Patent Application Publication No. 3-501428 International Publication No. 2021 / 095083 International Publication No. 2021 / 199447

[0005] However, the memory chips, substrates, and logic chips in the semiconductor modules described in Patent Documents 1 to 3 are stacked parallel to the stacking direction, which increases the thermal resistance of the semiconductor module due to, for example, the oxide films included in the stacked memory chips. When the thermal resistance of the semiconductor module increases, the thermal conductivity of the semiconductor module decreases, making it difficult to dissipate heat from, for example, the logic chip. When it becomes difficult to dissipate heat from the logic chip, the temperature of the semiconductor module increases, which may cause the semiconductor module to malfunction. Furthermore, to prevent malfunction of the semiconductor module, it is necessary to limit the temperature rise of the semiconductor module to a temperature range in which the semiconductor module operates normally. Therefore, the number of stacked chips in a semiconductor module is limited.

[0006] Furthermore, the logic chips of the semiconductor modules described in Patent Documents 1 to 3 are connected to external circuits using a rewiring layer, which results in an increase in wiring length and wiring load (capacity), which causes delays in signal transmission, degradation of calculation performance, and an increase in chip power consumption.

[0007] Furthermore, in the technologies described in Patent Documents 5 and 6, although a gap is generated between the chip and the substrate, the chip and the substrate are arranged in adjacent positions, which results in electromagnetic noise occurring due to non-contact communication between the chip and the substrate, and the chip and the substrate may malfunction due to the electromagnetic noise.

[0008] In view of these problems, one embodiment of the present invention aims to provide a semiconductor module using inductor communication that has good thermal conductivity and excellent heat dissipation characteristics, suppresses malfunctions caused by electromagnetic noise and heat, and enables suppression of signal delays and low power consumption.

[0009] a semiconductor module according to one embodiment of the present invention, comprising: a first logic chip including a first surface parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first surface; a first semiconductor chip including a third surface parallel to the second surface and a fourth surface parallel to the third surface, the third surface being disposed on the second surface and electrically connected to the first logic chip; and a first semiconductor cube disposed on the fourth surface, the first semiconductor chip including a plurality of second semiconductor chips stacked in the first direction, each of the plurality of second semiconductor chips including a first inductor disposed in a third direction perpendicular to the first direction and the second direction, the first semiconductor chip including a plurality of routers and a second inductor disposed parallel to the fourth surface, the plurality of circuits in the first logic chip and the plurality of circuits in the first semiconductor chip being connected using the plurality of routers, and the plurality of second semiconductor chips, the first logic chip, and the first semiconductor chip being configured to be capable of contactless communication using the first inductor and the second inductor.

[0010] The first logic chip may include a first electrode on the second surface side, and the first semiconductor chip may include a second electrode on the third surface side that can be joined to the first electrode by fusion bonding.

[0011] Each of the plurality of routers may include a switch.

[0012] The plurality of second semiconductor chips may include at least one type of memory chip, and the first semiconductor chip may include a memory controller capable of controlling the at least one type of memory chip.

[0013] The plurality of second semiconductor chips may include an FPGA chip configured to be controllable using the first logic chip.

[0014] The first logic chip may include a plurality of wiring layers provided on the first surface side, and may be electrically connected to a package substrate via a plurality of bumps electrically connected to the plurality of wiring layers, and may receive control signals and power supply voltages from the package substrate.

[0015] The first logic chip may be connected to the third surface of the first semiconductor chip in a face-up connection, and the first semiconductor chip may be electrically connected to the first semiconductor cube in a face-up connection.

[0016] The semiconductor device may further include a second logic chip different from the first semiconductor chip, the second semiconductor chip, and the first logic chip, and the second logic chip may include a sixth surface parallel to the first direction and the second direction and a seventh surface parallel to the sixth surface, and may be positioned apart from the first logic chip in the first direction and the second direction, with the sixth surface in contact with the third surface.

[0017] The semiconductor device may further include a second semiconductor cube on which a plurality of third semiconductor chips different from the first semiconductor chip, the second semiconductor chip, and the first logic chip are arranged in the first direction, and the second semiconductor cube may be arranged on the fourth surface and a fifth surface of the first semiconductor cube opposite along the third direction.

[0018] According to one embodiment of the present invention, it is possible to provide a semiconductor module using inductor communication that has good thermal conductivity and excellent heat dissipation characteristics, suppresses malfunctions caused by electromagnetic noise and heat, and enables large memory capacity and low power consumption.

[0019] 9 is a perspective view showing the configuration of a semiconductor module according to a first embodiment of the present invention; FIG. 10 is a cross-sectional view showing the configuration of a semiconductor module according to the first embodiment of the present invention; FIG. 11 is a perspective view showing inductor groups included in a plurality of memory chips according to the first embodiment of the present invention, and inductor groups included in a magnetically coupled through chip interface router chip (TCI router chip), and FIG. 12 is a perspective view showing the configuration of inductors on the memory chips and the inductors on the TCI router chip shown in FIG. 10; FIG. 12 is a schematic view showing the configuration of a memory cube and a TCI router chip according to a first embodiment of the present invention; FIG. 13 is a schematic view showing the configuration of a TCI router chip and a logic chip according to a first embodiment of the present invention; FIG. 14 is a schematic view showing the configuration of a memory chip according to a first embodiment of the present invention; FIG. 15 is a perspective view showing the configuration of a memory chip according to a first embodiment of the present invention; 13 is a schematic diagram showing the configuration of a logic chip according to a first embodiment of the present invention. FIG. 14 is a perspective view showing the configuration of a logic chip according to the first embodiment of the present invention. FIG. 15 is a cross-sectional view showing the cross-sectional structure of a logic chip taken along line C1-C2 shown in FIG. 12. FIG. 16 is a cross-sectional view showing the configuration of a semiconductor module according to a second embodiment of the present invention. FIG. 17 is a schematic diagram showing the configuration of a memory cube and a TCI router chip according to a second embodiment of the present invention. FIG. 18 is a cross-sectional view showing the configuration of a semiconductor module according to a third embodiment of the present invention. FIG. 19 is a schematic diagram showing the configuration of an FPGA cube and a TCI router chip according to a third embodiment of the present invention. FIG. 19 is a cross-sectional view showing the configuration of a semiconductor module according to a fourth embodiment of the present invention. FIG. 19 is a schematic diagram showing the configuration of a memory cube and a TCI router chip according to a fourth embodiment of the present invention. FIG. 19 is a cross-sectional view showing the configuration of a semiconductor module according to a fifth embodiment of the present invention. FIG. 19 is a cross-sectional view showing the configuration of a semiconductor module according to a sixth embodiment of the present invention.

[0020] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the following exemplary embodiments. For clarity of explanation, the drawings may show schematic representations of the width, thickness, shape, etc. of each part compared to the actual form. However, these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals (or reference numerals with a, b, etc. suffixed thereto), and detailed descriptions may be omitted as appropriate. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element and have no further meaning unless otherwise specified.

[0021] In one embodiment of the present invention, when a component or region is said to be "on (or under)" another component or region, unless otherwise specified, this includes not only the case where it is directly above (or directly under) the other component or region, but also the case where it is above (or under) the other component or region, i.e., the case where another component is included between the component or region and above (or under) the other component or region.

[0022] In one embodiment of the present invention, the D1 direction intersects with the D2 direction, and the D3 direction intersects with the D1 and D2 directions (D1D2 plane). The D1 direction is called the first direction, the D2 direction is called the second direction, and the D3 direction is called the third direction.

[0023] In one embodiment of the present invention, when the expressions "identical" and "matching" are used, the expressions "identical" and "matching" may include a tolerance within the design range. In addition, in one embodiment of the present invention, when a tolerance within the design range is included, the expressions "approximately identical" and "approximately matching" may be used.

[0024] First Embodiment A semiconductor module 10 according to a first embodiment will be described with reference to FIGS.

[0025] <1-1. Overview of Semiconductor Module 10> An overview of the semiconductor module 10 will be described with reference to FIGS. 1 to 5. FIG. 1 is a perspective view showing the configuration of the semiconductor module 10. FIG. 2 is a cross-sectional view showing the configuration of the semiconductor module 10. FIG. 3A is a perspective view showing an inductor group 171 included in a plurality of memory chips 110 included in the semiconductor module 10 and an inductor group 371 included in a magnetically coupled chip-to-chip interface router chip (Through Chip Interface Router Chip (TCI router chip)) 300. FIG. 3B is a perspective view showing the configuration of the inductor 172 on the memory chip 110 and the inductor 372 on the TCI router chip 300 shown in FIG. 3A. FIG. 4 is a schematic diagram showing the configuration of the memory cube 100 and the TCI router chip 300 included in the semiconductor module 10. FIG. 5 is a schematic diagram showing the configuration of the TCI router chip 300 and the logic chip 200 included in the semiconductor module 10.

[0026] <1-1-1. Overall Configuration of Semiconductor Module 10> The overall configuration of the semiconductor module 10 will be described with reference to FIGS. 1 and 2. FIG.

[0027] 1 or 2, the semiconductor module 10 includes a memory cube 100, a TCI router chip 300, a logic chip 200, and an adhesive layer 400. For example, a stack 20 is formed by the memory cube 100, the TCI router chip 300, the logic chip 200, and the adhesive layer 400. The semiconductor module 10 may also include a bump layer 500, a package substrate 600, and a bump layer 700. The memory cube 100 may be referred to as a first semiconductor cube, the TCI router chip 300 may be referred to as a first semiconductor chip, and the logic chip 200 may be referred to as a first logic chip.

[0028] The memory cube 100 includes a configuration in which multiple memory chips 110 are stacked in the D1 direction. Each of the multiple memory chips 110 has a similar configuration including multiple inductors 172 (first inductors). The memory cube 100 includes a first surface 142 parallel to the D2 and D3 directions, and a second surface 144 opposite the first surface 142 with respect to the D1 direction and parallel to the first surface 142. The memory cube 100 also includes a first side surface 145 perpendicular to the first surface 142 and the second surface 144, a second side surface 146 adjacent to the first side surface 145, a third side surface 147 adjacent to the second side surface 146, and a fourth side surface 148 adjacent to the third side surface 147 and the first side surface 145. The memory cube 100 is disposed on the second surface 304 of the TCI router chip 300, with the second side 146 in contact with the adhesive layer 400 and facing the second surface 304 of the TCI router chip 300. The memory chip 110 may be referred to as a second semiconductor chip. A plurality of inductors 172 are disposed parallel to and spaced apart from the second side 146 and aligned in the D2 direction.

[0029] When the multiple memory chips 110 are not distinguished from one another, the memory chips are referred to as memory chips 110. When the multiple memory chips 110 are distinguished from one another, the memory chips are referred to as memory chip 110n, memory chip 110n+1, etc. The multiple memory chips 110 included in the memory cube 100 include, for example, memory chip 110n (see FIG. 3) and memory chip 110n+1 (see FIG. 3) arranged adjacent to memory chip 110n. Note that the memory cube 100 includes a configuration in which eight memory chips 110 are stacked in the D1 direction. The number of stacked memory chips 110 shown in FIG. 1 is an example, and the number of stacked memory chips 110 is not limited to eight layers shown in FIG. 1. The number of stacked memory chips 110 may be selected appropriately based on the application, specifications, etc. of the semiconductor module 10.

[0030] The TCI router chip 300 includes, for example, a transistor layer 330 and an inductor layer 370 stacked on the transistor layer 330. The transistor layer 330 includes a first surface 302, which is the exposed surface of the TCI router chip 300, and a plurality of through-hole electrodes 360. The plurality of through-hole electrodes 360 are exposed on the first surface 302. The inductor layer 370 includes a second surface 304, which is the exposed surface of the TCI router chip 300 opposite the first surface 302, and a plurality of inductors 372. The first surface 302 and the second surface 304 are parallel to the D1 and D2 directions. The first surface 302 faces the second surface 204 of the logic chip 200 and is in contact with the second surface 204 of the logic chip 200. As described above, the second surface 304 is in contact with the adhesive layer 400 and faces the second side surface 146 of the memory cube 100. As will be described in detail later, the TCI router chip 300 includes a wiring layer 350 between the transistor layer 330 and the inductor layer 370. The transistor layer 330, the wiring layer 350, and the inductor layer 370 are stacked in this order in the D3 direction.

[0031] Furthermore, as will be described in detail later, the substrate 373 (see, for example, FIG. 11 ) included in the TCI router chip 300 is positioned downward (toward the first surface 302) in the D3 direction, and the N-type transistor 368 and the P-type transistor 369 (see, for example, FIG. 11 ) are stacked above the substrate 373 in the D3 direction. That is, the stacking direction of each layer constituting the TCI router chip 300 is upward in the D3 direction. For example, a mounting structure in which the stacking direction is upward in the D3 direction is called face-up mounting, and a mounting structure in which the stacking direction is downward in the D3 direction is called face-down mounting. In the semiconductor module 10, the first surface 302 of the TCI router chip 300 is placed on the logic chip 200, and the TCI router chip 300 is mounted face-up.

[0032] The logic chip 200 includes, for example, a lower wiring layer 210 and a transistor layer 230 stacked on the lower wiring layer 210. The lower wiring layer 210 includes a first surface 202, which is the exposed surface of the logic chip 200, multiple electrode pads 222, 221, and 220, and multiple wirings 228. The multiple electrode pads 222, 221, and 220 are exposed on the first surface 202. The transistor layer 230 includes a second surface 204, which is the exposed surface of the logic chip 200 opposite the first surface 202, multiple through electrodes 260 connected to each of the multiple wirings 228, and multiple wirings 280. The multiple wirings 280 are exposed on the second surface 204. The first surface 202 and the second surface 204 are surfaces parallel to the D1 direction and the D2 direction. The second surface 204 is the surface that contacts the first surface 302 of the TCI router chip 300. The logic chip 200 is disposed on the package substrate 600 via a bump layer 500 disposed on the first surface 202, for example.

[0033] Furthermore, second surface 204 of logic chip 200 is disposed opposite first surface 302 of TCI router chip 300, and logic chip 200 is stacked (bonded) with TCI router chip 300. At this time, each of the multiple wirings 280 is bonded to a corresponding multiple through electrodes 360, and logic chip 200 is electrically connected to TCI router chip 300. For stacking (bonding) chips together, techniques such as fusion bonding and silicon direct bonding (SDB) can be used. Since fusion bonding and silicon direct bonding are well known techniques in the technical field, detailed explanations thereof will be omitted here. The plurality of wirings 280 and the plurality of through electrodes 360 are formed using, for example, a conductor made of metal. The conductor made of metal is, for example, a conductor containing copper or the like. The wirings 280 and the through electrodes 360 may be called, for example, a first electrode and a second electrode, respectively.

[0034] Furthermore, as will be described in detail later, a substrate 273 (see, for example, FIG. 14 ) included in logic chip 200 is located below (on the first surface 202 side) in the direction D3, and an N-type transistor 268 and a P-type transistor 269 (see, for example, FIG. 14 ) are stacked above substrate 273 in the direction D3. In semiconductor module 10, first surface 202 of logic chip 200 is disposed on package substrate 600, and logic chip 200 is mounted on package substrate 600 face-up.

[0035] The adhesive layer 400 is disposed between the memory cube 100 and the TCI router chip 300, and bonds the memory cube 100 and the TCI router chip 300. The adhesive layer 400 may be, for example, an adhesive containing an epoxy resin or an acrylic polymer, a die bonding film (DBF) containing an epoxy resin or an acrylic polymer, or an adhesive film such as a die attached film (DAF).

[0036] The package substrate 600 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. The package substrate 600 includes, for example, a second surface 604 and a first surface 602, which are exposed surfaces of the package substrate 600, and multiple wiring layers 608, 610, and 612. The wiring layers 608, 610, and 612 are arranged parallel to the D1 and D2 directions and are stacked in this order from top to bottom in the D3 direction. The multiple wiring layers 608, 610, and 612 include multiple wirings 609, multiple wirings 611, and multiple wirings 613. The multiple wirings 609 are exposed on the first surface 602, and the multiple wirings 613 are exposed on the second surface 604. For example, the wiring 609 is electrically connected to the wiring 611, and the wiring 611 is electrically connected to the wiring 613. Note that FIG. 2 does not illustrate the insulating layers alternately stacked with the wirings. Furthermore, the number of layers in the multilayer wiring structure of the package substrate 600 is not limited to the number of layers (three layers) shown in Fig. 2. The number of layers in the multilayer wiring structure of the package substrate 600 can be changed as appropriate based on the application or specifications of the semiconductor module 10.

[0037] Furthermore, the package substrate 600 is electrically connected to the stack 20 via a plurality of bumps 502 included in a bump layer 500 disposed between the stack 20 and the package substrate 600. Furthermore, the package substrate 600 is connected to an external substrate, an external circuit, etc. via a plurality of bumps 702 included in a bump layer 700. Specifically, each of the plurality of wirings 609 exposed on the first surface 602 is electrically connected to each of the plurality of electrode pads 222, 221, and 220 included in the logic chip 200 using the bumps 502, and each of the plurality of wirings 613 exposed on the second surface 604 is connected to an external substrate, an external circuit, etc. using the bumps 702.

[0038] The semiconductor module 10 includes a memory cube 100 suspended above a TCI router chip 300 in the D3 direction, and has a lower thermal resistance than a configuration including multiple memory chips stacked in the D1 and D2 directions. Therefore, the semiconductor module 10 has high thermal conductivity and excellent heat dissipation characteristics, which can suppress malfunctions caused by temperature increases in the semiconductor module. Therefore, the limit on the number of stacked chips within the semiconductor module 10 is relaxed compared to a configuration including multiple memory chips stacked in the D1 and D2 directions.

[0039] 1-1-2. Overview of the inductor 172 and the inductor 372 The inductor 172 and the inductor 372 will be outlined with reference to Figures 3A and 3B. Configurations that are the same as or similar to those in Figures 1 and 2 will be explained as necessary.

[0040] As described above, the multiple memory chips 110 have similar configurations, so here, the configuration of memory chip 110n+1 will be described, and then, if necessary, the configuration of memory chip 110n will be described. Memory chip 110n+1 includes an inductor layer 170 (see, for example, FIGS. 7 and 8 ). Inductor layer 170 includes multiple inductor groups 171, and each of the multiple inductor groups 171 includes multiple inductors 172.

[0041] As shown in FIG. 3A or 3B, each of the multiple inductors 172 is arranged parallel to a direction D3 that is perpendicular to the directions D1 and D2 (i.e., the second surface 304).

[0042] As described above, the multiple inductors 172 are arranged side by side in the direction D2, parallel to and spaced apart from the second side surface 146. Each of the multiple inductors 172 includes a terminal A, a terminal B, a first portion 172a, a second portion 172b, a third portion 172c, a fourth portion 172d, and a fifth portion 172e. As will be described in detail later, the inductor 172 is electrically connected to the transmitting / receiving circuit 114 ( FIG. 4 ) using the terminal A and the terminal B.

[0043] The fourth portion 172d extends in the D2 direction, one end of which is electrically connected to terminal A, and the other end of which is electrically connected to one end of the fifth portion 172e. The fifth portion 172e extends in the D3 direction, and the other end of which is electrically connected to one end of the first portion 172a. The first portion 172a extends in the D2 direction, and the other end of which is electrically connected to one end of the second portion 172b. The second portion 172b extends in the D3 direction, and the other end of which is electrically connected to one end of the third portion 172c. The third portion 172c extends in the D2 direction, and the other end of which is electrically connected to terminal B.

[0044] The TCI router chip 300 includes an inductor group 371 including a plurality of inductors 372 arranged parallel to the location where the plurality of inductors 172 are arranged and parallel to and adjacent to the second surface 304. The TCI router chip 300 also includes an inductor layer 370 (see, for example, FIGS. 10 and 11 ), which includes a plurality of inductors 372. The plurality of inductors 372 are arranged in a matrix along the D1 and D2 directions. Each of the plurality of inductors 372 includes a terminal C, a terminal D, a first portion 372a, a second portion 372b, a third portion 372c, a fourth portion 372d, and a fifth portion 372e. As will be described in detail later, the inductor 372 is electrically connected to the transceiver circuit 314 using terminal C and terminal D.

[0045] The fourth portion 372d extends in the D2 direction, one end of which is electrically connected to terminal C, and the other end of which is electrically connected to one end of the fifth portion 372e. The fifth portion 372e extends in the D1 direction, and the other end of which is electrically connected to one end of the first portion 372a. The first portion 372a extends in the D2 direction, and the other end of which is electrically connected to one end of the second portion 372b. The second portion 372b extends in the D1 direction, and the other end of which is electrically connected to one end of the third portion 372c. The third portion 372c extends in the D2 direction, and the other end of which is electrically connected to terminal D.

[0046] As shown in FIGS. 3A and 3B , in the semiconductor module 10, the shape of the inductor 172 when viewed from the D1 direction along a plane parallel to the D2 and D3 directions, and the shape of the inductor 372 when viewed from the D3 direction along a plane parallel to the D1 and D2 directions, are, for example, rectangular. Because the memory chip 110 is perpendicular to the TCI router chip 300, the inductor 172 is positioned facing the inductor 372 at a 90-degree angle. Furthermore, when viewed from the D3 direction along a plane parallel to the D1 and D2 directions, the first portion 172a of the inductor 172 overlaps the first portion 372a of the inductor 372. Among the multiple inductors 172 and the multiple inductors 372, one inductor 172 and one inductor 372 that face each other are magnetically coupled, enabling one-to-one, non-contact communication between the inductors. Communication between the inductors due to magnetic field coupling is referred to, for example, as inductor communication, signal communication, or data communication. The shapes of the inductors 172 and 372 are not limited to a quadrangle. For example, the shapes of the inductors 172 and 372 may be trapezoidal or pentagonal. The shapes of the inductors 172 and 372 may be any shapes that allow inductor communication.

[0047] As shown in FIG. 3B , for example, inductors 172 and 372 face each other at 90 degrees and are capable of one-to-one communication through magnetic field coupling. More specifically, effective inductor communication is performed by first portion 172a of inductor 172 and first portion 372a of inductor 372. First portion 172a mainly functions to perform inductor communication with first portion 372a. In inductor 172, second portion 172b, third portion 172c, fourth portion 172d, and fifth portion 172e, excluding first portion 172a, mainly function to supply current to first portion 172a. Similar to inductor 172, in inductor 372, second portion 372b, third portion 372c, fourth portion 372d, and fifth portion 372e, excluding first portion 372a, mainly function to supply current to first portion 372a.

[0048] The inductor 372 has the same configuration and function as the inductor 172. Note that in the semiconductor module 10, viewing a surface parallel to the D2 and D3 directions from the D1 direction is sometimes referred to as a front view, and viewing a surface parallel to the D1 and D2 directions from the D3 direction is sometimes referred to as a plan view.

[0049] The semiconductor module 10 includes a memory cube 100 suspended above a TCI router chip 300, and the overlapping portion of the inductor 172 and the inductor 372 is a first portion 172a and a first portion 372a, with the overlapping portion of the inductor 172 and the inductor 372 being minimized. The logic chip 200 does not include an inductor, and the inductor 172 in the memory cube 100 and the inductor 372 in the TCI router chip 300 are located away from the logic chip 200. Therefore, the semiconductor module 10 can suppress the generation of electromagnetic noise due to inductor communication associated with the logic chip 200, and can suppress malfunctions of the memory cube 100, the TCI router chip 300, and the logic chip 200 due to electromagnetic noise.

[0050] <1-1-3. Circuit Configuration of Semiconductor Module 10> The circuit configuration of the semiconductor module 10 will be outlined with reference to FIGS. 4 and 5. As shown in FIG. 4, the memory cube 100 and the TCI router chip 300 are connected based on inductor communication. As shown in FIG. 4 or 5, the TCI router chip 300 and the logic chip 200 are electrically connected using a signal bus 340. Note that the circuits in the memory cube 100, the circuits in the TCI router chip 300, and the circuits in the logic chip 200 may be electrically connected using the signal bus 340.

[0051] 4, the memory cube 100 includes a plurality of through chip interface-IOs (TCI-IOs) 112 and a plurality of memory modules 111. The plurality of TCI-IOs 112 are electrically connected to the memory modules 111.

[0052] The TCI-IO 112 includes an inductor 172, a transmitting / receiving circuit 114, and a parallel-to-serial conversion circuit 113. The inductor 172 is electrically connected to the transmitting / receiving circuit 114 using terminals A and B. The transmitting / receiving circuit 114 is electrically connected to the parallel-to-serial conversion circuit 113. The parallel-to-serial conversion circuit 113 is electrically connected to the memory module 111.

[0053] As described above, the inductor 172 has the function of performing contactless inductor communication with the inductor 372 of the TCI router chip 300 .

[0054] The transmitter / receiver circuit 114 has, for example, a function of amplifying the signal (data) received by the inductor 172 and a function of removing noise from the received signal (data). The transmitter / receiver circuit 114 also has, for example, a function of transmitting the desired signal (data) converted using the parallel-to-serial converter circuit 113 onto radio waves. The signal received by the inductor 172 includes a large number of parallel signals from the TCI router chip 300. The desired signal includes a large number of parallel signals from the memory module 111.

[0055] For example, in step 1, the parallel-serial conversion circuit 113 performs parallel-to-serial conversion on a large number of parallel signals from the TCI router chip 300 to convert them into serial signals (serial signals). The serial signals are transferred at high speed using a single signal path (wiring). In step 2, the parallel-serial conversion circuit 113 performs serial-to-parallel conversion on the serial signals immediately before the memory module 111 to return them to a large number of parallel signals, and then transmits the large number of parallel signals to the memory module 111. When transmitting signals (data) from the memory module 111 to the TCI router chip 300, the parallel-serial conversion circuit 113 performs, for example, step 2 followed by step 1. The parallel-serial conversion circuit 113 is called, for example, a SerDes circuit (Serialize and Deserialize Circuit).

[0056] The memory module 111 includes, for example, a function for generating a large number of parallel signals to be transmitted, a function for controlling a large number of parallel signals received, and a function for storing the signals in the memory cell array 115 (FIG. 6).

[0057] As shown in FIG. 4 or 5, the TCI router chip 300 includes, for example, a plurality of TCI-IOs 312, a plurality of network routers (Router®) 318, a plurality of external IOs 316, and a plurality of memory controllers 319.

[0058] The TCI-IO 312, the external IO 316, and the memory controller 319 are functional blocks that make up an LSI (Large Scale Integration). The functional blocks that make up an LSI are called, for example, IP (Intellectual Property) cores, IPs, or macros. The IP cores include a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a memory, and the like.

[0059] IP cores such as multiple TCI-IOs 312 , multiple external IOs 316 , and multiple memory controllers 319 include a network interface (NI) 317 .

[0060] In addition, IP cores such as the multiple TCI-IOs 312, the multiple external IOs 316, and the multiple memory controllers 319 may not include the NI 317, and the NI 317 may be located outside the multiple TCI-IOs 312, the multiple external IOs 316, and the multiple memory controllers 319, and each of the multiple TCI-IOs 312, the multiple external IOs 316, and the multiple memory controllers 319 may be electrically connected to R318 corresponding to each circuit via the NI 317.

[0061] IP cores such as a plurality of TCI-IOs 312, a plurality of external IOs 316, and a plurality of memory controllers 319 are electrically connected to R318 corresponding to the NI 317 of each IP core. Thus, IP cores such as a plurality of TCI-IOs 312, a plurality of external IOs 316, and a plurality of memory controllers 319 are connected in a network using a plurality of R318. The plurality of R318 are electrically connected using, for example, a plurality of signal buses 340.

[0062] A network configuration of IP cores using multiple R318s may be a mesh configuration as shown in Fig. 5. The network configuration of IP cores shown in Fig. 5 is an example, and the network configuration of IP cores is not limited to the configuration shown in Fig. 5. The network configuration of IP cores is selected appropriately depending on the specifications and applications of the semiconductor module 10, the number of IP cores included in the semiconductor module 10, and the like.

[0063] The multiple TCI-IOs 312 include, for example, TCI-IOs 312a, 312b, ..., and 312e. When the multiple TCI-IOs 312 are not distinguished from one another, the TCI-IO is expressed as TCI-IO312. When the multiple TCI-IOs 312 are distinguished from one another, the multiple TCI-IOs are expressed as TCI-IOs 312a, 312b, ..., and 312e, etc. There is no limit to the number of multiple TCI-IOs 312 included in the semiconductor module 10, and the number is selected appropriately depending on the specifications and applications of the semiconductor module 10, the number of IP cores included in the semiconductor module 10, etc.

[0064] The TCI-IO 312 includes an inductor 372, a transmitting / receiving circuit 314, a parallel-serial conversion circuit 313, and an NI 317. The inductor 372 is electrically connected to the transmitting / receiving circuit 314 using terminals C and D. The transmitting / receiving circuit 314 is electrically connected to the parallel-serial conversion circuit 313. The parallel-serial conversion circuit 313 is electrically connected to the NI 317. The TCI-IO 312 (NI 317) is electrically connected to R318.

[0065] The configurations and functions of the inductor 372, the transmitting / receiving circuit 314, the parallel-serial conversion circuit 313, and the memory controller 319 are similar to the configurations and functions of the inductor 172, the transmitting / receiving circuit 114, the parallel-serial conversion circuit 113, and the memory module 111. Therefore, descriptions of the configurations and functions of the inductor 372, the transmitting / receiving circuit 314, the parallel-serial conversion circuit 313, and the memory controller 319 will be omitted here.

[0066] The NI 317 can convert, for example, data transmitted and received using the signal bus 340 into a data format compatible with the IP core electrically connected to the NI 317, and can convert the data format compatible with the IP core into a data format compatible with the signal bus 340. As a result, the semiconductor module 10 can transmit and receive both addresses and data using the signal bus 340, thereby enabling a smaller bus width than a module including signal buses arranged in a concentrated manner. Furthermore, because the semiconductor module 10 can transmit and receive data without relying on the data format compatible with each IP core, an increase in the number of signal buses 340 can be suppressed.

[0067] Here, data transmitted and received using the signal bus 340 includes, for example, an address that can identify an IP core electrically connected to the NI 317 .

[0068] The plurality of R318 includes, for example, R318a, 318b, ..., and 318i. As with the TCI-IO, when the plurality of R318 are not distinguished from one another, the plurality of Rs are expressed as R318. When the plurality of R318 are distinguished from one another, the plurality of Rs are expressed as R318a, 318b, ..., 318i, etc. Note that there is no limit to the number of the plurality of R318s included in the semiconductor module 10, and the number is selected appropriately depending on the specifications and applications of the semiconductor module 10, the number of IP cores included in the semiconductor module 10, and the like.

[0069] Each of the multiple R318s is electrically connected to the IP core and signal bus 340. Each of the multiple R318s includes multiple switches and can control the data transmission / reception path to each IP core connected in a network configuration based on the address. As a result, the semiconductor module 10 can transmit and receive data to a desired IP core among the IP cores connected in a network configuration by controlling the multiple switches of the multiple R318s. Furthermore, since the semiconductor module 10 controls the data transmission / reception path to the IP core using the R318, it can change the location and address of the R318 without depending on the location of the IP core, thereby flexibly configuring the data transmission / reception path.

[0070] Furthermore, R318 can aggregate multiple signal buses 340 and function as a repeater (also called a bus buffer) that appropriately divides the routed signal buses 340. Therefore, the semiconductor module 10 can suppress the concentration of multiple signal buses 340. As a result, for example, the degree of freedom in the position of R318 is improved, and restrictions on the placement of IP cores connected to R318 can be alleviated.

[0071] The external IO 316 includes, for example, an NI 317. The external IO 316 is electrically connected to an R318 via the NI 317. The external IO 316 is electrically connected to the logic chip 200, the memory cube 100, and an external circuit (not shown, for example, a power supply circuit) via the R318, and has the function of transmitting and receiving signals between the external circuit and the logic chip 200 and the memory cube 100.

[0072] The memory controller 319 includes, for example, an NI 317. For example, the memory controller 319 is electrically connected to an R318 via the NI 317. The memory controller 319 is also electrically connected to the logic chip 200 and the memory cube 100 via the R318, and has the function of transmitting and receiving signals between the memory cube 100 and the logic chip 200.

[0073] As shown in FIG. 5, the logic chip 200 includes, for example, a plurality of CPUs (Central Processing Units) 211, a memory interface 212, a PCIe interface (PCI Express Interface (PCIeIF)) 213, an Ethernet interface (Ethernet Interface (EIF)) 214, and a plurality of R218.

[0074] The CPUs 211, the memory interface 212, the PCIe IF 213, and the EIF 214 may be IP cores. Each of the CPUs 211, the memory interface 212, the PCIe IF 213, and the EIF 214 includes an NI 217.

[0075] Note that each of the multiple CPUs 211, memory interface 212, PCIe IF 213, and EIF 214 may not include NI 217, and NI 217 may be located outside the multiple CPUs 211, memory interface 212, PCIe IF 213, and EIF 214, and each of the multiple CPUs 211, memory interface 212, PCIe IF 213, and EIF 214 may be electrically connected to R318 corresponding to each circuit via NI 217. The configuration and function of NI 217 are similar to those of NI 317. Therefore, a description of the configuration and function of NI 217 will be omitted here.

[0076] The multiple IP cores, such as the CPU 211, memory interface 212, PCIe IF 213, and EIF 214, are electrically connected to R218s corresponding to the NIs 217 of each IP core. Therefore, the multiple IP cores, such as the CPU 211, memory interface 212, PCIe IF 213, and EIF 214, are connected in a network using multiple R218s. The multiple R218s are electrically connected using, for example, multiple signal buses 340. The configurations and functions of the multiple R218s are similar to those of the multiple R318s. Therefore, a description of the configurations and functions of the multiple R218s will be omitted here.

[0077] The multiple CPUs 211 include, for example, CPUs 211a, 211b, and 211c. When the multiple CPUs 211 are not distinguished from one another, the CPU is expressed as CPU 211. When the multiple CPUs 211 are distinguished from one another, the multiple CPUs are expressed as CPUs 211a, 211b, and 211c, etc. There is no limit to the number of multiple CPUs 211 included in the semiconductor module 10, and the number is selected appropriately depending on the specifications and use of the semiconductor module 10, etc.

[0078] The plurality of R218 includes, for example, R218a, 218b, ..., and 218f. As with the plurality of R318, when the plurality of R218 are not distinguished from one another, the plurality of Rs are expressed as R218. When the plurality of R218 are distinguished from one another, the plurality of Rs are expressed as R218a, 218b, ..., and 218f, etc. Note that there is no limit to the number of the plurality of R218s included in the semiconductor module 10, and the number is selected appropriately depending on the specifications and use of the semiconductor module 10, etc.

[0079] Here, data transmitted and received using the signal bus 340 includes, for example, an address that can identify an IP core electrically connected to the NI 217 .

[0080] Each of the multiple CPUs 211 is a logic module including a so-called arithmetic circuit. Each of the multiple CPUs 211 has a function for controlling the transmission of signals (data) to the memory cube 100, the TCI router chip 300, the memory interface 212, the PCIe IF 213, the EIF 214, and the multiple R218, or the reception of signals (data) from the memory cube 100, the TCI router chip 300, the memory interface 212, the PCIe IF 213, the EIF 214, and the multiple R218. For example, the CPU 211 transmits a signal for driving the memory module 111 via the TCI router chip 300.

[0081] The memory interface 212 is, for example, a DRAM interface (Dynamic Random Access Memory (DRAM) IO), and has the function of transmitting and receiving signals between a DRAM (not shown) and the logic chip 200 .

[0082] The PCIe IF 213 is an interface that complies with the serial bus standard used for connecting an expansion card in a computer, for example, and has a function that enables high-speed data transfer with a CPU, memory, storage, and the like that are connected to an expansion card installed in the computer.

[0083] The EIF 214 is an interface that has the function of connecting the semiconductor module 10 and all devices (computers, printers, etc.) that communicate via a network to a network medium (cable), for example.

[0084] As described above, the circuits in the TCI router chip 300 and the circuits in the logic chip 200 are connected in a network via a network router (Router®), and the circuits in the memory cube 100 are connected to the circuits in the TCI router chip 300 and the circuits in the logic chip 200 using inductor communication. The semiconductor module 10 is a so-called Network on Chip (NoC) in which multiple IP cores are connected in a network, and is a module capable of communication using the NoC and inductor communication.

[0085] 5, R318h connected to memory controller 319 is connected to R318g, R318e, and R318i in TCI router chip 300, and also connected to R218b in logic chip 200. That is, memory controller 319 connected to R318h is electrically connected to memory controller 319 connected to R318g, TCI-IO 312e connected to R318e, and external IO 316 connected to R318i, and is also electrically connected to PCIe IF 213 connected to R218b in logic chip 200 via signal bus 340. TCI-IO 312e communicates with inductor 172 in memory cube 100 using inductor 372, and is electrically connected to memory module 111.

[0086] Furthermore, R218b connected to the PCIeIF 213 is connected to R218a, R218c, and R218e within the logic chip 200. That is, the PCIeIF 213 connected to R218b is electrically connected to the memory interface 212 connected to R218a, the EIF 214 connected to R218c, and the CPU 211b connected to R218e.

[0087] Thus, CPU 211b sends a signal to drive memory module 111 to TCI-IO 312e via R218e, R218b, signal bus 340, R318h and R318e, and TCI-IO 312e communicates with inductor 172 in memory cube 100 using inductor 372, and can send a signal to drive memory module 111 to memory module 111.

[0088] The semiconductor module 10 electrically connects the TCI router chip 300 and the logic chip 200 using a router connected in a network configuration, enabling communication using a network-type bus, and also enabling contactless communication using inductor communication between the TCI router chip 300 and the memory cube 100 suspended from the TCI router chip 300. Thus, the semiconductor module 10 is three-dimensionally connected using electrical connections and connections based on contactless communication, suppressing signal delays associated with wiring in the horizontal direction parallel to the D1 and D2 directions, and in the vertical direction (D3 direction), making it a module capable of reducing power consumption.

[0089] <1-2. Overview of Memory Cube 100> Next, an overview of the memory cube 100 will be described with reference to FIGS. 1, 3A, and 6 to 8. FIG. 6 is a schematic diagram showing the configuration of the memory chip 110. FIG. 7 is a perspective view showing the configuration of the memory chip 110. FIG. 8 is a cross-sectional view showing the schematic cross-sectional structure of the memory chip 110 taken along line A1-A2 shown in FIG. 7. Configurations that are the same as or similar to those in FIGS. 1 to 5 will be described as necessary.

[0090] 1, as described in "1-1. Overview of Semiconductor Module 10," the memory cube 100 includes a configuration in which multiple memory chips 110 are stacked in the D1 direction. The second side 146 is positioned in contact with the adhesive layer 400 and faces the second surface 304 of the TCI router chip 300, and the memory cube 100 is disposed on the second surface 304 of the TCI router chip 300.

[0091] 6, the memory chip 110 includes a plurality of memory modules 111, a plurality of TCI-IOs 112, power supply wiring 164, and ground wiring 165. Each of the plurality of memory modules 111 includes a memory cell array 115. Each of the plurality of TCI-IOs 112 includes a plurality of inductor groups 171, and the inductor groups 171 include a plurality of inductors 172. The memory chip 110 shown in FIG. 6 is, for example, an SRAM (Static Random Access Memory) chip.

[0092] The memory module 111 has functions for controlling the storage of signals (data) in the memory cell array 115, the reading of signals (data) from the memory cell array 115, the transmission of signals (data) to the TCI-IO 112, or the reception of signals (data) from the TCI-IO 112.

[0093] The memory cell array 115 includes a plurality of memory cells (not shown). Each of the plurality of memory cell arrays 115 is, for example, an SRAM, and each of the plurality of memory cells is an SRAM cell. The SRAM, SRAM cells, and SRAM memory module 111 may employ technology used in the SRAM technical field. Therefore, detailed description thereof will be omitted here. Note that the plurality of memory cell arrays 115 and the plurality of memory cells may be memory cell arrays and memory cells other than SRAM, such as a dynamic random access memory (DRAM) and DRAM cells, or a magnetoresistive random access memory (MRAM) and MRAM cells.

[0094] The multiple memory modules 111 and the multiple TCI-IOs 112 are electrically connected to power supply wiring 164 and ground wiring 165. The power supply wiring 164 and ground wiring 165 are electrically connected to, for example, an external circuit (not shown), and are supplied with a power supply voltage VDD and a voltage VSS, etc. The power supply voltage VDD is, for example, 1 V, 3 V, etc. The voltage VSS is, for example, a ground voltage, 0 V, etc.

[0095] 1 and 7, each of the multiple memory chips 110 includes, for example, a transistor layer 130, a wiring layer 150, and an inductor layer 170. The multiple memory chips 110 include, for example, a memory chip 110n (FIG. 3A) and a memory chip 110n+1 (FIG. 3A) adjacent to the memory chip 110n.

[0096] 7 , the memory chip 110 includes a first surface 102 parallel to the D2 and D3 directions and a second surface 104 opposite the first surface 102 in the D1 direction. The first surface 102 is the exposed surface of the transistor layer 130. The second surface 104 is the exposed surface of the inductor layer 170. The first surface 102 and the second surface 104 are parallel to the first surface 142 and the second surface 144.

[0097] The memory chip 110 also includes a first side surface 105 perpendicular to the first surface 102 and the second surface 104, a second side surface 106 adjacent to the first side surface 105, a third side surface 107 adjacent to the second side surface 106, and a fourth side surface 108 adjacent to the third side surface 107 and the first side surface 105. The first side surface 105 is part of the first side surface 145, the second side surface 106 is part of the second side surface 146, the third side surface 107 is part of the third side surface 147, and the fourth side surface 108 is part of the fourth side surface 148.

[0098] A portion of the power supply wiring 164 and a portion of the ground wiring 165 are exposed, for example, on the first side surface 105, the fourth side surface 108, or the third side surface 107, and are electrically connected to side wiring electrically connected to an external circuit. Power supply voltages VDD and VSS are supplied to a portion of the power supply wiring 164 and a portion of the ground wiring 165 via the external circuit and the power supply side wiring. The side wiring can be formed by employing technology used in the technical field of semiconductor modules.

[0099] The inductor layer 170 includes a plurality of inductor groups 171. Each of the plurality of inductor groups 171 includes a plurality of inductors 172. The plurality of inductor groups 171 are arranged parallel to the D2 and D3 directions (i.e., the first surface 102 and the second surface 104) and perpendicular to the D1 and D2 directions. Each of the plurality of inductor groups 171 is arranged away from the fourth side surface 108 and close to the second side surface 146, and is arranged extending in the D2 direction. Note that although the number of inductors 172 shown in FIG. 7 is three, the number of inductors 172 shown in FIG. 7 is merely an example. The number of inductors 172 can be changed as appropriate depending on the specifications and applications of the semiconductor module 10.

[0100] As shown in FIG. 3A or 7 , the multiple inductor groups 171 are adjacent to the second side surface 106 of the memory chip 110 and are arranged parallel to the D2 direction. Each of the multiple inductor groups 171 includes multiple inductors 172. The multiple inductors 172 include, for example, inductors having a data communication (data transmission) function and inductors having a clock communication (clock transmission) function. Each inductor 172 may perform inductor communication with its corresponding inductor 372 in response to (synchronized with) a clock received by clock communication. Alternatively, each inductor 172 may perform inductor communication with its corresponding inductor 372 asynchronously to (asynchronous with) the clock received by clock communication. Furthermore, for example, each inductor 172 may perform inductor communication with its corresponding inductor 372 asynchronously to the clock communication.

[0101] As shown in FIG. 8 , the transistor layer 130 includes, for example, a substrate 173, wiring 163, an insulating layer 174, fins 167, wiring 166, an active region 184, a gate insulating film 175, a gate electrode 176, an N-type transistor 168, a P-type transistor 169, and an insulating layer 177. The substrate 173 is, for example, an N-type Si substrate or an N-type Si-wafer. As an example, the memory chip 110 is formed using a 2 nm CMOS process and is configured using fin-type transistors as shown in FIG. 8 . However, the memory chip 110 may be formed using a CMOS process other than 2 nm and may be configured using transistors other than fin-type transistors. The structure of the transistors in the memory chip 110 may be selected appropriately depending on the specifications and applications of the semiconductor module 10.

[0102] The wiring layer 150 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. The wiring layer 150 includes, for example, wiring 178, insulating layer 179, wiring 180, and insulating layer 181. The number of layers of the multilayer wiring in the wiring layer 150 is not limited to two layers as shown in FIG. 8 . The number of layers of the multilayer wiring in the wiring layer 150 may be three or more. The number of layers of the multilayer wiring in the wiring layer 150 can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10.

[0103] The inductor layer 170 includes, for example, an insulating layer 182 and a plurality of inductors 172. The inductor layer 170 also includes a plurality of inductor groups 171.

[0104] The wiring 163 is a so-called buried electrode. The wiring 178 and the wiring 166 are connected to an external circuit, for example, via the side wiring described above, and signals (data), power supply voltage VDD, voltage VSS, etc. are supplied to the wiring 163 via the side wiring, the wiring 178, and the wiring 166. The wiring 178 and the wiring 180 have, for example, a damascene structure, and the wiring 166 has, for example, a structure equivalent to a through electrode.

[0105] Inductor 172 is connected to wiring 180, and wiring 180 is connected to wiring 178. Although not shown in the figure, wiring 178 is electrically connected to the source electrode or drain electrode of N-type transistor 168, the source electrode or drain electrode of P-type transistor 169, gate electrode 176, and the like. A signal (data) received by inductor 172 is transmitted to N-type transistor 168, P-type transistor 169, and the like via wiring 180 and wiring 178. Furthermore, a signal (data) including a result calculated by a logical operation is transmitted to inductor 172 via N-type transistor 168, P-type transistor 169, wiring 180, and wiring 178.

[0106] <1-3. Overview of the TCI router chip 300> Next, an overview of the TCI router chip 300 will be described with reference to Figs. 1, 3A, and 9 to 11. Fig. 9 is a block diagram showing the configuration of the TCI router chip 300. Fig. 10 is a perspective view showing the configuration of the TCI router chip 300. Fig. 11 is a cross-sectional view showing an outline of the cross-sectional structure of the TCI router chip 300 taken along line B1-B2 shown in Fig. 10. Configurations that are the same as or similar to those in Figs. 1 to 8 will be described as necessary.

[0107] 1, as explained in "1-1. Overview of Semiconductor Module 10," the TCI router chip 300 includes a configuration in which a transistor layer 330, a wiring layer 350, and an inductor layer 370 are stacked in this order in the D3 direction, and includes a first surface 302 parallel to the D1 and D2 directions, and a second surface 304 opposite to the first surface 302. The first surface 302 is the surface on which the transistor layer 330 is exposed. The second surface 304 is the surface on which the inductor layer 370 is exposed.

[0108] 1 and 10 , the inductor layer 370 includes a plurality of inductor groups 371. The plurality of inductor groups 371 (see, for example, FIG. 3A ) includes a plurality of inductors 372. The plurality of inductors 372 are arranged in a matrix pattern parallel to the D1 direction and the D2 direction (i.e., the first surface 302 and the second surface 304).

[0109] 11 , the transistor layer 330 includes, for example, a substrate 373, a wiring 363, a through electrode 360, a through electrode 394, a through electrode 395, an insulating layer 374, a fin 367, a wiring 366, an active region 384, a gate insulating film 375, a gate electrode 376, an N-type transistor 368, a P-type transistor 369, and an insulating layer 377. The wiring layer 350 includes a multilayer wiring structure in which wirings and insulating layers are alternately stacked. The wiring layer 350 includes, for example, a wiring 378, an insulating layer 379, a wiring 380, and an insulating layer 381. The inductor layer 370 includes, for example, an insulating layer 382 and a plurality of inductors 372.

[0110] The respective configurations and functions of the substrate 373, wiring 363, insulating layer 374, fin 367, wiring 366, activation region 384, gate insulating film 375, gate electrode 376, N-type transistor 368, P-type transistor 369, insulating layer 377, wiring 378, insulating layer 379, wiring 380, insulating layer 381, insulating layer 382, ​​and inductor 372 are similar to the respective configurations and functions of the substrate 173, wiring 163, insulating layer 174, fin 167, wiring 166, activation region 184, gate insulating film 175, gate electrode 176, N-type transistor 168, P-type transistor 169, insulating layer 177, wiring 178, insulating layer 179, wiring 180, insulating layer 181, insulating layer 182, and inductor 172 described in "1-2. Overview of memory cube 100". Therefore, the layers and wirings constituting the transistor layer 330, the wiring layer 350 and the inductor layer 370 will be explained as needed.

[0111] The through electrodes 360, 394, and 395 are electrically connected to wiring 363, which is a so-called embedded wiring, and a portion of the through electrodes 360, 394, and 395 are exposed on the first surface 302. A portion of the through electrodes 360, 394, and 395 are electrically connected to wiring 280 exposed on the second surface 204 of the logic chip 200. Signals (data), power supply voltages VDD and VSS, etc. are supplied from an external circuit to the through electrodes 360, 394, and 395 via the logic chip 200 (e.g., wiring 280).

[0112] As described in "1-1-3. Circuit Configuration of Semiconductor Module 10" with reference to FIGS. 4 and 5, as shown in FIG. 9, the TCI router chip 300 includes, for example, multiple TCI-IOs 312, multiple R318s, multiple external IOs 316, and multiple memory controllers 319. The multiple TCI-IOs 312 include TCI-IOs 312a to 312e and TCI-IO 312j, and the multiple R318s include R318a to R318j. Each of the multiple TCI-IOs 312 includes multiple inductor groups 271, and the inductor group 271 includes multiple inductors 372. The configuration of the TCI router chip 300 shown in FIG. 9 is merely an example, and the configuration of the TCI router chip 300 is not limited to the example shown in FIG. 9. For example, the TCI router chip 300 may include IP cores other than those shown in FIG. 9.

[0113] The power supply wiring 364 is electrically connected to the through electrode 394, the ground wiring 365 is electrically connected to the through electrode 395, and the signal bus 340 (see FIG. 4 ) is electrically connected to the through electrode 360 ​​(see FIG. 11 ). As shown in FIG. 9 , the TCI router chip 300 includes, for example, one through electrode 394 and one through electrode 395, and includes one system of power supply wiring 364 and one system of ground wiring 365. As shown in FIG. 11 or FIG. 5 , the TCI router chip 300 includes, for example, two through electrodes 360 and three systems of signal buses 340. The numbers of through electrodes 394, through electrodes 395, and through electrodes 360 included in the TCI router chip 300, as well as the number of systems of power supply wiring 364, ground wiring 365, and signal buses 340, are not limited to the examples shown in FIG. 11 or FIG. 5 . The TCI router chip 300 may include two or more through electrodes 394, two or more through electrodes 395, and two or more systems of power supply wiring 364, two or more systems of ground wiring 365, and two or more systems of signal bus 340. The number of through electrodes 394, two or more through electrodes 395, and two or more systems of power supply wiring 364, two or more systems of ground wiring 365, and two or more systems of signal bus 340 included in the TCI router chip 300 can be changed as appropriate depending on the specifications and applications of the semiconductor module 10.

[0114] As explained in "1-1. Overview of Semiconductor Module 10," the second surface 304 of the TCI router chip 300 is mounted on the adhesive layer 400, and the first surface 302 is mounted on the second surface 204 of the logic chip 200. In other words, the TCI router chip 300 is mounted face-up on the adhesive layer 400. As a result, the multiple inductors 372 arranged on the second surface 304 side are positioned away from the logic chip 200. This makes it possible to suppress the generation of electromagnetic noise and the like due to inductor communication associated with the logic chip 200.

[0115] 3A or 10 , the multiple inductors 372 are arranged in a matrix in the D1 and D2 directions on the second surface 304 side. Similar to the multiple inductors 172, the multiple inductors 372 include, for example, inductors having a data communication (data transmission) function and inductors having a clock communication (clock transmission) function. Similar to each inductor 172, each inductor 372 may perform inductor communication with its corresponding inductor 172 in accordance with (in synchronization with) a clock received by clock communication, or may perform inductor communication with its corresponding inductor 172 in asynchronous communication with (in synchronization with) the clock received by clock communication.

[0116] <1-4. Overview of Logic Chip 200> Next, an overview of the logic chip 200 will be described with reference to FIG. 1 and FIGS. 12 to 14. FIG. 12 is a block diagram showing the configuration of the logic chip 200. FIG. 13 is a perspective view showing the configuration of the logic chip 200. FIG. 14 is a cross-sectional view showing the outline of the cross-sectional structure of the logic chip 200 taken along line C1-C2 shown in FIG. 13. Configurations that are the same as or similar to those in FIGS. 1 to 11 will be described as necessary.

[0117] 1, as explained in "1-1. Overview of Semiconductor Module 10," logic chip 200 includes a configuration in which lower wiring layer 210 and transistor layer 230 are stacked in this order in the D3 direction as shown in FIG. 13, and includes first surface 202 parallel to the D1 and D2 directions, and second surface 204 opposite to first surface 202. First surface 202 is the surface on which lower wiring layer 210 is exposed. Second surface 204 is the surface on which transistor layer 230 is exposed.

[0118] 14 , the transistor layer 230 includes, for example, a substrate 273, wiring 263, through electrodes 260, through electrodes 294, through electrodes 295, an insulating layer 274, a fin 267, wiring 266, an active region 284, a gate insulating film 275, a gate electrode 276, an N-type transistor 268, a P-type transistor 269, and an insulating layer 277. The transistor layer 230 also includes a multilayer wiring structure in which wirings and insulating layers are alternately stacked. The multilayer wiring structure includes, for example, wiring 278, an insulating layer 279, wiring 280, and an insulating layer 281.

[0119] The respective configurations and functions of the substrate 273, wiring 263, through electrode 260, through electrode 294, through electrode 295, insulating layer 274, fin 267, wiring 266, activation region 284, gate insulating film 275, gate electrode 276, N-type transistor 268, P-type transistor 269, insulating layer 277, wiring 278, insulating layer 279, wiring 280, and insulating layer 281 are similar to the respective configurations and functions of the substrate 373, wiring 363, through electrode 360, through electrode 394, through electrode 395, insulating layer 374, fin 367, wiring 366, activation region 384, gate insulating film 375, gate electrode 376, N-type transistor 368, P-type transistor 369, insulating layer 377, wiring 378, insulating layer 379, wiring 380, insulating layer 381, and insulating layer 382 described in "1-3. Overview of TCI router chip 300". Therefore, each layer and wiring that constitutes the transistor layer 230 will be explained as needed.

[0120] The lower wiring layer 210 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked. The lower wiring layer 210 includes, for example, electrode pads 220, electrode pads 221, electrode pads 222, insulating layers 223, through electrodes 224, through electrodes 225, through electrodes 226, insulating layers 227, wiring 228, and insulating layers 229. The number of layers of the multilayer wiring in the lower wiring layer 210 is not limited to two as shown in FIG. 14 . The number of layers of the multilayer wiring in the lower wiring layer 210 may be three or more. The number of layers of the multilayer wiring in the lower wiring layer 210 can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10.

[0121] The lower wiring layer 210 is a wiring layer for so-called backside power delivery (BPD). BPD is a technology used in the technical field of semiconductor modules, and a detailed description thereof will be omitted here. Briefly, BPD is a technology for separating the supply of signals (data), power supply voltages, voltages, etc., between the second surface 204 and the first surface 202 of the substrate 273. For example, the use of BPD enables scaling of metal wiring connections within the semiconductor module 10, simplifies complex metal wiring patterning, and reduces the manufacturing costs of the semiconductor module 10.

[0122] The through electrodes 260, 294, and 295 are electrically connected to wiring 263, which is a so-called embedded wiring. The through electrodes 260, 294, and 295 are electrically connected to, for example, a second-layer wiring 228 counting from the first surface 202 side. The second-layer wiring 228 is electrically connected to the electrode pad 222, for example, using a plurality of through electrodes 226. The second-layer wiring 228 is electrically connected to the electrode pad 221, for example, using a plurality of through electrodes 225, and is electrically connected to the electrode pad 220, for example, using a plurality of through electrodes 224. For example, a power supply voltage VDD is supplied from an external circuit to the electrode pad 221, a voltage VSS is supplied from the external circuit to the electrode pad 222, and a signal (data) is supplied from the external circuit to the electrode pad 220. In this way, signals (data), power supply voltage VDD, voltage VSS, etc. are supplied from an external circuit to through electrodes 226, 225, and 224 via the electrode pads, and are then supplied to the inside of logic chip 200. Electrode pad 220, electrode pad 221, and electrode pad 222 are the first layer of wiring counting from the first surface 202 side.

[0123] As described in "1-1-3. Circuit Configuration of Semiconductor Module 10" with reference to FIGS. 4 and 5, as shown in FIG. 12, the logic chip 200 includes, for example, multiple CPUs 211, a memory interface 212, a PCIe IF 213, an EIF 214, and multiple R218s. The multiple CPUs 211 include CPUs 211a to 211c, and the multiple R218s include R218a to R218f. Note that the configuration of the logic chip 200 shown in FIG. 12 is just an example, and the configuration of the logic chip 200 is not limited to the example shown in FIG. 12. For example, the logic chip 200 may include IP cores other than those shown in FIG. 12.

[0124] The CPU 211 has a function for controlling the transmission of signals (data) to the TCI-IO 312, or the reception of signals (data) from the TCI-IO 312. The CPU 211 also has a function for driving the memory module 111 in the memory chip 110. For example, the CPU 211 transmits a signal for driving the memory module 111 via the TCI-IO 312. The CPU 211 is a logic module, and may include an arithmetic circuit such as a CPU (Central Processing Unit), for example.

[0125] For example, the power supply wiring 264 is electrically connected to the electrode pad 221 via the through electrode 294, the wiring 228, and the plurality of through electrodes 225, and the ground wiring 265 is electrically connected to the electrode pad 222 via the through electrode 295, the wiring 228, and the plurality of through electrodes 226. Furthermore, although not shown, for example, the through electrode 360 ​​(see FIG. 11) connected to the signal bus 340 (see FIG. 5) is electrically connected to the electrode pad 220 via the wiring 280, the wiring 278, the wiring 266, the wiring 263, the through electrode 260, the wiring 228, and the plurality of through electrodes 224.

[0126] 12 or 14, the logic chip 200 includes, for example, one electrode pad 221, one electrode pad 222, and one electrode pad 220, and one system each of power supply wiring 264 and ground wiring 265. Also, as shown in FIG. 14 or 5, the logic chip 200 includes, for example, one wiring 280 and three systems of signal buses 340. The numbers of electrode pads 221, 222, and electrode pads 220 included in the logic chip 200, as well as the number of systems of power supply wiring 264, ground wiring 265, and signal buses 340, are not limited to the examples shown in FIG. 12, 14, or 5. The logic chip 200 may include two or more electrode pads 221, 222, and electrode pads 220, and may include two or more systems of power supply wiring 264, ground wiring 265, and signal buses 340. The number of electrode pads 221, electrode pads 222, and electrode pads 220 included in the logic chip 200, as well as the number of power supply wiring 264, ground wiring 265, and signal bus 340 systems, can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10.

[0127] Second Embodiment A semiconductor module 10A according to a second embodiment will be described with reference to FIGS. 15 and 16. FIG. 15 is a cross-sectional view showing the configuration of the semiconductor module 10A. FIG. 16 is a schematic diagram showing the configuration of a memory cube 100A and a TCI router chip 300A included in the semiconductor module 10A. Configurations that are the same as or similar to those in FIGS. 1 to 14 will be described as necessary.

[0128] As shown in FIG. 15 , the semiconductor module 10A includes a memory cube 100A, a TCI router chip 300A, a logic chip 200, and an adhesive layer 400. For example, a stacked body 20A is configured with the memory cube 100A, the TCI router chip 300A, the logic chip 200, and the adhesive layer 400. The semiconductor module 10A may also include a bump layer 500, a package substrate 600, and a bump layer 700. The semiconductor module 10A includes a configuration in which the memory cube 100 and the TCI router chip 300 of the semiconductor module 10 are replaced with the memory cube 100A and the TCI router chip 300A. Other than the memory cube 100A and the TCI router chip 300A, the configuration of the semiconductor module 10A is the same as that of the semiconductor module 10. In the description of the semiconductor module 10A, configurations similar to those of the semiconductor module 10 will be described as necessary.

[0129] The memory cube 100A includes a configuration in which the multiple memory chips 110 of the memory cube 100 are replaced with multiple DRAM chips 110A. The configuration of the DRAM chip 110A is the same as the configuration of the memory chip 110 described in the first embodiment, except that it is a DRAM. As shown in FIG. 16, the DRAM chip 110A includes multiple DRAMs 111A, multiple TCI-IOs 112, and the like.

[0130] 16, the memory cube 100A has a configuration in which the memory module 111 of the memory cube 100 is replaced with a DRAM 111A. The configuration of the memory cube 100A other than that related to the DRAM 111A is the same as that of the semiconductor module 10. The DRAM 111A is electrically connected to the TCI-IO 112 (parallel-to-serial conversion circuit 113).

[0131] Like the memory module 111, the DRAM 111A includes, for example, a function to generate a large number of parallel signals to be transmitted, and a function to control a large number of received parallel signals and store them in a memory cell array included in the DRAM 111A.

[0132] The TCI router chip 300A includes a configuration in which the memory controller 319 of the TCI router chip 300 is replaced with a DRAM controller 319A. The configuration of the TCI router chip 300A other than the configuration related to the DRAM controller 319A is the same as that of the semiconductor module 10. The DRAM controller 319A is electrically connected to R318. The DRAM controller 319A is, for example, an IP core.

[0133] The DRAM controller 319A includes an NI317, similar to the memory controller 319. Note that the DRAM controller 319A may not include the NI317, and the NI317 may be located outside the DRAM controller 319A, with each of the multiple DRAM controllers 319A being electrically connected to R318 corresponding to the respective circuit via the NI317.

[0134] IP cores such as the multiple TCI-IOs 312, the multiple external IOs 316, and the multiple DRAM controllers 319A are electrically connected to R318 corresponding to the NI 317 of each IP core. Thus, the multiple TCI-IOs 312, the multiple external IOs 316, and the multiple DRAM controllers 319A are connected in a network using multiple R318. The multiple R318s are electrically connected using, for example, multiple signal buses 340.

[0135] The DRAM controller 319A is electrically connected to the logic chip 200 and the memory cube 100A via R318, and has the function of transmitting and receiving signals between the memory cube 100A and the logic chip 200.

[0136] The semiconductor module 10A can achieve the same effects as the semiconductor module 10. Furthermore, the semiconductor module 10A includes a DRAM 111A and a DRAM controller 319A, and has good thermal conductivity and excellent heat dissipation characteristics, which suppresses malfunctions caused by electromagnetic noise and heat, allowing it to transmit signals including large-capacity programs at high speed and with lower power consumption than conventional semiconductor modules.

[0137] Third Embodiment A semiconductor module 10B according to a third embodiment will be described with reference to FIGS. 17 and 18. FIG. 17 is a cross-sectional view showing the configuration of the semiconductor module 10B. FIG. 18 is a schematic diagram showing the configurations of a memory cube 100B and a TCI router chip 300B included in the semiconductor module 10B. Configurations that are the same as or similar to those in FIGS. 1 to 16 will be described as necessary.

[0138] As shown in FIG. 17 , the semiconductor module 10B includes a memory cube 100B, a TCI router chip 300B, a logic chip 200, and an adhesive layer 400. For example, a stacked body 20B is configured with the memory cube 100B, the TCI router chip 300B, the logic chip 200, and the adhesive layer 400. The semiconductor module 10B may include a bump layer 500, a package substrate 600, and a bump layer 700. The semiconductor module 10B includes a configuration in which the memory cube 100 and the TCI router chip 300 of the semiconductor module 10 are replaced with the memory cube 100B and the TCI router chip 300B. Other than the memory cube 100B and the TCI router chip 300B, the configuration of the semiconductor module 10B is the same as that of the semiconductor module 10. In describing the semiconductor module 10B, configurations similar to those of the semiconductor module 10 will be described as necessary.

[0139] The memory cube 100B includes a configuration in which the multiple memory chips 110 of the memory cube 100 are replaced with multiple FPGA (Field Programmable Gate Array) chips 110B. The configuration of the FPGA chip 110B is the same as the configuration of the memory chip 110 described in the first embodiment, except that it is an FPGA. The FPGA chip 110B includes multiple FPGAs 111B, multiple TCI-IOs 112, and the like.

[0140] 18, the memory cube 100B includes a configuration in which the memory module 111 of the memory cube 100 is replaced with an FPGA 111B. The configuration of the memory cube 100B other than that related to the FPGA 111B is the same as that of the semiconductor module 10. The FPGA 111B is electrically connected to the TCI-IO 112 (parallel-serial conversion circuit 113).

[0141] Like the memory module 111, the FPGA 111B includes, for example, a function for generating a large number of parallel signals to be transmitted and a function for controlling a large number of parallel signals received.

[0142] The TCI router chip 300B does not include the memory controller 319 of the TCI router chip 300. If the semiconductor module 10B includes a storage circuit having a function of storing data, such as a memory, it may include the memory controller 319. If the FPGA 111B includes a storage circuit, it may include the memory controller 319, or the FPGA 111B may include a configuration similar to that of the memory controller 319. The FPGA chip 110B is, for example, an IP core.

[0143] IP cores such as multiple TCI-IOs 312 and multiple external IOs 316 are electrically connected to R318 corresponding to the NI 317 of each IP core. Thus, IP cores such as multiple TCI-IOs 312 and multiple external IOs 316 are connected in a network using multiple R318. The multiple R318s are electrically connected using, for example, multiple signal buses 340.

[0144] The semiconductor module 10B can achieve the same effects as the semiconductor module 10. Furthermore, the semiconductor module 10B has good thermal conductivity and excellent heat dissipation characteristics, suppresses malfunctions caused by electromagnetic noise and heat, and includes an FPGA 111B that can be rewritten faster than conventional semiconductor modules.

[0145] Fourth Embodiment A semiconductor module 10C according to a fourth embodiment will be described with reference to FIGS. 19 and 20. FIG. 19 is a cross-sectional view showing the configuration of the semiconductor module 10C. FIG. 20 is a schematic diagram showing the configurations of a memory cube 100C and a TCI router chip 300C included in the semiconductor module 10C. Configurations that are the same as or similar to those in FIGS. 1 to 18 will be described as necessary.

[0146] As shown in FIG. 19 , the semiconductor module 10C includes a memory cube 100C, a TCI router chip 300C, a logic chip 200, and an adhesive layer 400. For example, a stack 20C is configured with the memory cube 100C, the TCI router chip 300C, the logic chip 200, and the adhesive layer 400. The semiconductor module 10C may also include a bump layer 500, a package substrate 600, and a bump layer 700. The semiconductor module 10C includes a configuration in which the memory cube 100 and the TCI router chip 300 of the semiconductor module 10 are replaced with the memory cube 100C and the TCI router chip 300C. Other than the memory cube 100C and the TCI router chip 300C, the configuration of the semiconductor module 10C is the same as that of the semiconductor module 10. In describing the semiconductor module 10C, configurations similar to those of the semiconductor module 10 will be described as necessary.

[0147] As shown in FIG. 19 or 20 , the memory cube 100C includes a configuration in which the multiple memory chips 110 stacked in the D1 direction of the memory cube 100 are replaced with DRAM chips 110A and NVM (Non Volatile Memory) chips 110C stacked alternately in the D1 direction. The memory cube 100C includes DRAM chips 110A and NVM chips 110C stacked alternately. The configuration of the memory chip 110 described in the first embodiment is the same as that of the memory chip 110 described in the first embodiment, except that the memory chip is the DRAM chip 110A. The configuration of the NVM chip 110C is the same as that of the memory chip 110 described in the first embodiment, except that the NVM chip 110C is an NVM. The DRAM chip 110A includes multiple DRAMs 111A, multiple TCI-IOs 112, etc., and the NVM chip 110C includes multiple NVMs 111C, multiple TCI-IOs 112, etc.

[0148] 20, the memory cube 100C has a configuration in which the memory module 111 of the memory cube 100 is replaced with a DRAM 111A and an NVM 111C. The configuration of the memory cube 100C other than that related to the DRAM 111A and NVM 111C is the same as that of the semiconductor module 10. The DRAM 111A is electrically connected to a TCI-IO 112 (parallel-serial conversion circuit 113), and the NVM 111C is electrically connected to a TCI-IO 112 (parallel-serial conversion circuit 113) different from the TCI-IO 112 (parallel-serial conversion circuit 113) connected to the DRAM 111A.

[0149] The DRAM 111A, like the memory module 111, includes, for example, a function to generate a large number of parallel signals to be transmitted and a function to control a large number of parallel signals received and store them in a memory cell array included in the DRAM 111A. Also, the NVM 111C, like the memory module 111, includes, for example, a function to generate a large number of parallel signals to be transmitted and a function to control a large number of parallel signals received and store them in a memory cell array included in the NVM 111C.

[0150] The TCI router chip 300C includes a configuration in which the memory controller 319 of the TCI router chip 300 is replaced with a DRAM controller 319A and an NVM controller 319C. The configuration of the TCI router chip 300C is the same as that of the semiconductor module 10 except for the configuration related to the DRAM controller 319A and the NVM controller 319C. The DRAM controller 319A is electrically connected to, for example, R318g, and the NVM controller 319C is electrically connected to, for example, R318h. The DRAM controller 319A and the NVM controller 319C are, for example, IP cores.

[0151] The DRAM controller 319A and the NVM controller 319C include the NI317, similar to the memory controller 319. Note that the DRAM controller 319A and the NVM controller 319C may not include the NI317, and the NI317 may be located outside the DRAM controller 319A and the NVM controller 319C, with each of the DRAM controller 319A and the NVM controller 319C being electrically connected to R318 corresponding to the respective circuits via the NI317.

[0152] IP cores such as the multiple TCI-IOs 312, multiple external IOs 316, DRAM controller 319A, and NVM controller 319C are electrically connected to R318 corresponding to the NI 317 of each IP core. Therefore, IP cores such as the multiple TCI-IOs 312, multiple external IOs 316, multiple DRAM controllers 319A, and NVM controller 319C are connected in a network using multiple R318. The multiple R318s are electrically connected using, for example, multiple signal buses 340.

[0153] The DRAM controller 319A and NVM controller 319C are electrically connected to the logic chip 200 and memory cube 100C via R318, and have the function of transmitting and receiving signals between the memory cube 100C and the logic chip 200.

[0154] The semiconductor module 10C can achieve the same effects as the semiconductor module 10. The semiconductor module 10C includes a DRAM 111A and a DRAM controller 319A that have excellent thermal conductivity and heat dissipation characteristics and are less susceptible to malfunctions caused by electromagnetic noise and heat, enabling it to transmit signals containing large amounts of programs at higher speeds and with lower power consumption than conventional semiconductor modules. The semiconductor module 10C also includes an NVM 111C and an NVM controller 319C that have excellent thermal conductivity and heat dissipation characteristics and are less susceptible to malfunctions caused by electromagnetic noise and heat, enabling it to transmit signals containing large amounts of data at higher speeds and with lower power consumption than conventional semiconductor modules, and to store large amounts of data in a nonvolatile manner.

[0155] Fifth Embodiment A semiconductor module 10D according to a fifth embodiment will be described with reference to Fig. 21. Fig. 21 is a cross-sectional view showing the configuration of the semiconductor module 10D. Configurations that are the same as or similar to those in Figs. 1 to 20 will be described as necessary.

[0156] 21 , the semiconductor module 10D includes a memory cube 100D, a TCI router chip 300, a logic chip 200, a graphics processing unit (GPU) 200A, and an adhesive layer 400. For example, a stack 20D is configured with the memory cube 100D, the TCI router chip 300, the logic chip 200, and the adhesive layer 400. The semiconductor module 10D may include a bump layer 500, a package substrate 600, and a bump layer 700. The semiconductor module 10D includes a configuration in which the memory cube 100 of the semiconductor module 10 is replaced with the memory cube 100D, and the TCI router chip 300 on which the logic chip 200 of the semiconductor module 10 is stacked (bonded) is replaced with the TCI router chip 300 on which the logic chip 200 and the GPU 200A are stacked (bonded). Other configurations of the semiconductor module 10D are the same as those of the semiconductor module 10 or the semiconductor module 10A. In the description of the semiconductor module 10D, configurations that are the same as those of the semiconductor module 10 or the semiconductor module 10A will be described as necessary.

[0157] In the semiconductor module 10, the multiple memory chips 110 stacked in the D1 direction of the memory cube 100 are one type of memory chip (SRAM). On the other hand, as shown in FIG. 21 , in the memory cube 100D, the multiple memory chips stacked in the D1 direction are two types: memory chips 110 and DRAM chips 110A. The memory chips 110 are SRAM. The memory cube 100D includes a configuration in which two memory chips 110, four DRAM chips 110A, and two memory chips 110 are stacked in this order in the D1 direction. The stacking order of the memory chips 110 and DRAM chips 110A in the memory cube 100D is not limited to the example shown in FIG. 21 . The stacking order of the memory chips 110 and DRAM chips 110A in the memory cube 100D can be changed as appropriate depending on the specifications and applications of the semiconductor module 10D. The configuration of the DRAM chip 110A is the same as the configuration of the memory chip 110 described in the second embodiment, except that it is a DRAM.

[0158] As described above, the logic chip 200 and GPU 200A are stacked (bonded) on the TCI router chip 300. The stacking (bonding) of the logic chip 200 and the TCI router chip 300 is as described in "1-1-1. Overall configuration of semiconductor module 10."

[0159] The GPU 200A includes a configuration in which a lower wiring layer 210A and a transistor layer 230A are stacked in this order in the D3 direction, and includes a first surface 202A parallel to the D1 and D2 directions, and a second surface 204A opposite the first surface 202A. The first surface 202A is the exposed surface of the lower wiring layer 210A. The second surface 204A is the exposed surface of the transistor layer 230A. The lower wiring layer 210A and the transistor layer 230A have the same configuration and function as the lower wiring layer 210 and the transistor layer 230 described in the first embodiment. Therefore, the configurations of the lower wiring layer 210A and the transistor layer 230A will be described as necessary. The transistor layer 230A includes a plurality of wirings 280, which are exposed on the second surface 204A, and the lower wiring layer 210A includes a plurality of electrode pads 220, which are exposed on the first surface 202A. The GPU 200A includes the same configuration and functions as a GPU used in the technical field of semiconductor modules. For example, the GPU 200A is a logic chip specialized for image processing that has the same configuration and functions as the logic chip 200. The GPU 200A may be referred to as a second logic chip.

[0160] Similarly to the logic chip 200, the first surface 202A of the GPU 200A is disposed on the package substrate 600, and the GPU 200A is mounted on the package substrate 600 face-up.

[0161] Similar to the logic chip 200 of the semiconductor module 10, the first surface 302 of the TCI router chip 300 of the semiconductor module 10D is positioned to face the second surface 204A of the GPU 200A and is the surface that contacts the second surface 204A of the GPU 200A. Also, similar to the logic chip 200 of the semiconductor module 10, each of the plurality of through electrodes 360 exposed on the first surface 302 of the TCI router chip 300 is bonded to a corresponding plurality of wirings 280 among the plurality of wirings 280 exposed on the second surface 204, and the GPU 200A is electrically connected to the TCI router chip 300.

[0162] Furthermore, similar to the logic chip 200 of the semiconductor module 10, each of the multiple wirings 609 exposed on the first surface 602 of the package substrate 600 is electrically connected to each of the multiple electrode pads 220 exposed on the first surface 202A of the GPU 200A using bumps 502, and each of the multiple wirings 613 exposed on the second surface 604 of the package substrate 600 is connected to an external board, external circuit, etc. using bumps 702.

[0163] The TCI router chip 300 may include a plurality of through electrodes 360 that are not connected to the logic chip 200 and the GPU 200A.

[0164] The DRAM controller 319A and NVM controller 319C are electrically connected to the logic chip 200 and memory cube 100D via R318, and have the function of transmitting and receiving signals between the memory cube 100D and the logic chip 200.

[0165] The semiconductor module 10D can achieve the same effects as the semiconductor module 10. The semiconductor module 10D also includes a SARM chip and a DRAM chip 110A that have good thermal conductivity and excellent heat dissipation characteristics, and are less susceptible to malfunctions caused by electromagnetic noise and heat, and can transmit signals including large amounts of programs and signals (data) at high speed and with low power consumption compared to conventional semiconductor modules. Furthermore, the semiconductor module 10D also includes a configuration that has good thermal conductivity and excellent heat dissipation characteristics, and is less susceptible to malfunctions caused by electromagnetic noise and heat, and can transmit signals including signals (data) associated with image processing at high speed and with low power consumption.

[0166] Sixth Embodiment A semiconductor module 10E according to a sixth embodiment will be described with reference to Fig. 22. Fig. 22 is a cross-sectional view showing the configuration of the semiconductor module 10E. Configurations that are the same as or similar to those in Figs. 1 to 21 will be described as necessary.

[0167] As shown in FIG. 22 , the semiconductor module 10E includes a memory cube 100A, a memory cube 100E, a TCI router chip 300, a logic chip 200, a GPU 200A, and adhesive layers 400A and 400. For example, a stack 20E is configured with the memory cube 100A, the memory cube 100E, the TCI router chip 300, the logic chip 200, the GPU 200A, and adhesive layers 400A and 400. The semiconductor module 10E may include a bump layer 500, a package substrate 600, and a bump layer 700. The semiconductor module 10E includes a configuration in which the memory cube 100D of the semiconductor module 10D is replaced with a configuration in which the memory cube 100A and the memory cube 100E are connected by the adhesive layer 400A. The other configurations of the semiconductor module 10E are similar to those of the semiconductor module 10D. In the description of the semiconductor module 10E, configurations similar to those of the semiconductor module 10D will be described as necessary.

[0168] The memory cube arranged in the D3 direction of the semiconductor module 10D is a single-tiered memory cube 100D. Meanwhile, the memory cube arranged in the D3 direction of the semiconductor module 10E is a two-tiered memory cube, consisting of the memory cube 100A and the memory cube 100E. While the memory cube arranged in the D3 direction of the semiconductor module 10E is, for example, two-tiered, the memory cube arranged in the D3 direction of the semiconductor module 10E may be three or more tiered. The number of tiers of memory cubes arranged in the D3 direction of the semiconductor module 10E is appropriately selected depending on the specifications and applications of the semiconductor module 10E, the number of IP cores included in the semiconductor module 10E, and other factors.

[0169] The memory cube 100A has a configuration similar to that of the memory cube 100A according to the second embodiment. The reference numerals of the multiple inductors of the DRAM chip 110A included in the memory cube 100A are denoted as inductors 172f to avoid duplication with the multiple inductors 172 included in the memory chip 110. The inductors 172f have the same configuration and function as the inductors 172. The multiple inductors 172f are arranged close to the second side surface 146 and extend in the D2 direction.

[0170] The memory cube 100E includes a configuration in which the multiple memory chips 110 included in the memory cube 100A according to the second embodiment are replaced with multiple memory chips 110E. The memory chip 110E differs from the memory chip 110 in that the multiple inductors 172 included in the memory chip 110 are arranged close to both the second side surface 146 side and the fourth side surface 148 side and are arranged extending in the D2 direction. The configuration and function of the inductors 172 included in the memory chip 110E are similar to the configuration and function of the inductors 172 included in the memory chip 110.

[0171] The adhesive layer 400A is disposed between the fourth side surface 148 of the memory cube 100E and the second side surface 146D of the memory cube 100A, and bonds the memory cube 100E to the memory cube 100A. The adhesive layer 400A is made of the same material as the adhesive layer 400.

[0172] Each of the multiple inductors 172f is magnetically coupled to a corresponding inductor 172 among the multiple inductors 172 arranged adjacent to the fourth side surface 148, thereby enabling one-to-one, non-contact communication between the inductors. Also, each of the multiple inductors 172 arranged adjacent to the second side surface 146 is magnetically coupled to a corresponding inductor 372 among the multiple inductors 372 arranged adjacent to the second surface 304 of the TCI router chip 300, thereby enabling one-to-one, non-contact communication between the inductors.

[0173] The semiconductor module 10E can achieve the same effects as the semiconductor module 10. Furthermore, the semiconductor module 10E includes a configuration in which memory cubes, each having memory chips stacked in the D1 direction, are arranged in multiple stages in the D3 direction, thereby enabling further increase in memory capacity.

[0174] The various configurations of the semiconductor modules 10, 10A, 10B, 10C, 10D, and 10E illustrated as embodiments of the present invention may be interchanged as appropriate, provided they are consistent with the spirit of the present invention. Furthermore, the various configurations of the semiconductor modules 10, 10A, 10B, 10C, 10D, and 10E illustrated as embodiments of the present invention may be combined as appropriate, provided they are consistent with the spirit of the present invention. Technical matters common to each embodiment are included in each embodiment even if not explicitly stated. Furthermore, semiconductor modules disclosed in this specification and drawings, in which a person skilled in the art appropriately adds, deletes, or modifies components, or adds, omits, or modifies processes, are also included within the scope of the present invention, as long as they incorporate the gist of the present invention.

[0175] Even if there are other effects and advantages different from those brought about by the aspects of the embodiments disclosed in this specification, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention.

[0176] 10: semiconductor module, 10A: semiconductor module, 10B: semiconductor module, 10C: semiconductor module, 10D: semiconductor module, 10E: semiconductor module, 20: stack, 20A: stack, 20B: stack, 20C: stack, 20D: stack, 20E: stack, 100: memory cube, 100A: memory cube, 100B: memory cube, 100C: memory cube, 100D: memory cube, 100E: memory cube, 102: first surface, 104: second surface, 105: first side surface, 106: second side surface, 107: third side surface, 108: 4 sides, 110: memory chip, 110n: memory chip, 110n+1: memory chip, 110A: DRAM chip, 110B: FPGA chip, 110C: NVM chip, 111: memory module, 111A: DRAM, 111B: FPGA, 111C: NVM, 112: TCI-IO, 113: parallel-serial conversion circuit, 114: transmitter / receiver circuit, 115: memory cell array, 130: transistor layer, 142: first surface, 144: second surface, 145: first side surface, 146: second side surface, 146D: second side surface, 147: third side surface, 148: fourth side surface, 150: wiring layer , 163: wiring, 164: power supply wiring, 165: ground wiring, 166: wiring, 167: fin, 168: N-type transistor, 169: P-type transistor, 170: inductor layer, 171: inductor group, 172: inductor, 172a: first portion, 172b: second portion, 172c: third portion, 172d: fourth portion, 172e: fifth portion, 172f: inductor, 173: substrate, 174: insulating layer, 175: gate insulating film, 176: gate electrode, 177: insulating layer, 178: wiring, 179: insulating layer, 180: wiring, 181: insulating layer, 182: insulating layer, 184: activation Area, 200: logic chip, 200A: GPU, 202: first surface, 202A: first surface, 204: second surface, 204A: second surface, 210: lower wiring layer, 210A: lower wiring layer, 211: CPU, 211a: CPU, 211b: CPU, 211c: CPU, 212: memory interface, 213: PCIe interface, 214: Ethernet interface, 217: network interface, 218a: network router, 218b: network router, 218c: network router, 218d: network router,218e: network router, 218f: network router, 220: electrode pad, 221: electrode pad, 222: electrode pad, 223: insulating layer, 224: through electrode (e.g., signal), 225: through electrode, 226: through electrode, 227: insulating layer, 228: wiring, 229: insulating layer, 230: transistor layer, 230A: transistor layer, 260: through electrode, 263: wiring, 264: power supply wiring, 265: ground wiring, 266: wiring, 267: fin, 268: N-type transistor, 269: P-type transistor, 273: substrate, 274: insulating layer, 275: gate insulator Insulating film, 276: gate electrode, 277: insulating layer, 278: wiring, 279: insulating layer, 280: wiring, 281: insulating layer, 284: active region, 294: through electrode, 295: through electrode, 300: TCI router chip, 300A: TCI router chip, 300B: TCI router chip, 300C: TCI router chip, 300D: TCI router chip, 302: first surface, 304: second surface, 312: TCI-IO, 312a: TCI-IO, 312b: TCI-IO, 312c: TCI-IO, 312d: TCI-IO, 312e: TCI-IO, 312j: TCI-IO, 313: parallel-serial conversion circuit, 314: transmission / reception circuit, 316: external IO, 317: network interface, 318: network router, 318a: network router, 318b: network router, 318c: network router, 318d: network router, 318e: network router, 318f: network router, 318g: network router, 318h: network router, 318i: network router, 318j: network router, 319: memory controller, 319 A: DRAM controller, 319C: NVM controller, 330: transistor layer, 340: signal bus, 350: wiring layer, 360: through electrode, 363: wiring, 364: power supply wiring, 365: ground wiring, 366: wiring, 367: fin, 368: N-type transistor, 369: P-type transistor, 370: inductor layer, 371: inductor group, 372: inductor, 372a: first portion, 372b: second portion, 372c: third portion, 372d: fourth portion, 372e: fifth portion, 373: substrate, 374: insulating layer, 375: gate insulating film, 376: gate electrode,377: insulating layer, 378: wiring, 379: insulating layer, 380: wiring, 381: insulating layer, 382: insulating layer, 384: active region, 394: through electrode, 395: through electrode, 400: adhesive layer, 400A: adhesive layer, 500: bump layer, 502: bump, 600: package substrate, 602: first surface, 604: second surface, 608: wiring layer, 609: wiring, 610: wiring layer, 611: wiring, 612: wiring layer, 613: wiring, 700: bump layer, 702: bump,

Claims

1. A semiconductor module comprising: a first logic chip including a first surface parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first surface; a first semiconductor chip including a third surface parallel to the second surface and a fourth surface parallel to the third surface, the third surface being disposed on the second surface and electrically connected to the first logic chip; and a first semiconductor cube including a plurality of second semiconductor chips stacked in the first direction and disposed on the fourth surface, wherein each of the plurality of second semiconductor chips includes a first inductor disposed in a third direction perpendicular to the first direction and the second direction, the first semiconductor chip includes a plurality of routers and a second inductor disposed parallel to the fourth surface, a plurality of circuits in the first logic chip and a plurality of circuits in the first semiconductor chip are connected using the plurality of routers, and the plurality of second semiconductor chips, the first logic chip, and the first semiconductor chip are configured to enable contactless communication using the first inductor and the second inductor.

2. The semiconductor module according to claim 1, wherein the first logic chip includes a first electrode on the second surface side, and the first semiconductor chip includes a second electrode on the third surface side that can be joined to the first electrode by fusion bonding.

3. The semiconductor module according to claim 1, wherein each of the plurality of routers includes a switch.

4. The semiconductor module according to claim 1, wherein the plurality of second semiconductor chips include at least one type of memory chip, and the first semiconductor chip includes a memory controller capable of controlling the at least one type of memory chip.

5. The semiconductor module according to claim 1, wherein the plurality of second semiconductor chips include an FPGA chip configured to be controllable by the first logic chip.

6. The semiconductor module according to claim 1, wherein the first logic chip includes a plurality of wiring layers provided on the first surface side, is electrically connected to a package substrate via a plurality of bumps electrically connected to the plurality of wiring layers, and receives a control signal and a power supply voltage from the package substrate.

7. The semiconductor module of claim 1, wherein the first logic chip is connected to the third surface of the first semiconductor chip in a face-up connection, and the first semiconductor chip is electrically connected to the first semiconductor cube in a face-up connection.

8. The semiconductor module described in claim 4, further comprising a second logic chip different from the first semiconductor chip, the second semiconductor chip, and the first logic chip, wherein the second logic chip includes a sixth surface parallel to the first direction and the second direction and a seventh surface parallel to the sixth surface, and is disposed apart from the first logic chip in the first direction and the second direction, and wherein the sixth surface is disposed in contact with the third surface.

9. The semiconductor module of claim 1, further comprising a second semiconductor cube having a plurality of third semiconductor chips different from the first semiconductor chip, the second semiconductor chip, and the first logic chip arranged in the first direction, the second semiconductor cube being arranged on a fifth face of the first semiconductor cube opposite the fourth face along the third direction.