Semiconductor device

Abstract

This semiconductor device comprises: a chip which has a first main surface and a second main surface that is on the reverse side to the first main surface; a first impurity region that has a first conductivity type and is formed in a surface layer part of the first main surface; a second impurity region that has a second conductivity type and is formed in a surface layer part of the first impurity region; a third impurity region that has the first conductivity type and is formed in a surface layer part of the second impurity region; a plurality of trenches which extend from the first main surface to the first impurity region through the third impurity region and the second impurity region; and an electric field attenuating structure that has the second conductivity type and is formed integrally with the second impurity region so as to extend over bottom walls of the plurality of trenches.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2023-104405 filed with the Japan Patent Office on June 26, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] US Pat. No. 6,299,499 discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.

[0004] US Patent Application Publication No. 2015 / 0028351

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device that can easily manufacture a structure that can reduce electric field concentration on the bottom wall of a trench.

[0006] A semiconductor device according to one embodiment of the present disclosure includes a chip having a first main surface and a second main surface opposite to the first main surface, a first impurity region of a first conductivity type formed in a surface layer portion of the first main surface, a second impurity region of a second conductivity type formed in a surface layer portion of the first impurity region, a third impurity region of the first conductivity type formed in a surface layer portion of the second impurity region, a plurality of trenches extending from the first main surface through the third impurity region and the second impurity region to reach the first impurity region, and a second conductivity type electric field relaxation structure formed integrally with the second impurity region and spanning the bottom walls of the plurality of trenches.

[0007] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example of a chip layout. FIG. 4 is a perspective view showing an example of a chip layout. FIG. 5 is a plan view showing an active region and a trench structure. FIG. 6 is a cross-sectional perspective view showing the active region and the trench structure. FIG. 7 is an enlarged cross-sectional view showing the trench structure. FIG. 8 is an enlarged cross-sectional view showing the trench structure. FIG. 9 is an enlarged cross-sectional view showing the trench structure. FIG. 10 is a perspective view showing a configuration of a peripheral region. FIG. 11 is a cross-sectional view showing a main portion of the peripheral region. FIG. 12 is a schematic diagram showing a wafer used in manufacturing a semiconductor device. FIG. 13 is a flowchart showing an example of a method for manufacturing a semiconductor device. FIG. 14A is a view showing an example of a method for manufacturing a semiconductor device. FIG. 14B is a view showing a process subsequent to FIG. 14A . FIG. 14C is a view showing a process subsequent to FIG. 14B . FIG. 14D is a view showing a process subsequent to FIG. 14C . FIG. 14E is a view showing a process subsequent to FIG. 14D . FIG. 14F is a view showing a process subsequent to FIG. 14E . Fig. 14G is a diagram showing a process subsequent to Fig. 14F. Fig. 14H is a diagram showing a process subsequent to Fig. 14G. Fig. 15 is a diagram showing a first modified example of the semiconductor device. Fig. 16 is a diagram showing a second modified example of the semiconductor device. Fig. 17 is a diagram showing a third modified example of the semiconductor device. Fig. 18 is a diagram showing a fourth modified example of the semiconductor device. Fig. 19 is a diagram showing a fifth modified example of the semiconductor device. Fig. 20 is a diagram showing a sixth modified example of the semiconductor device.

[0008] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0009] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing an example layout of a chip 2. FIG. 4 is a perspective view showing an example layout of a chip 2. FIG. 5 is a plan view showing a trench structure 16 together with an active region 9. FIG. 6 is a cross-sectional perspective view showing the trench structure 16 and an electric field relaxation structure 21 together with the active region 9. FIGS. 7 to 9 are enlarged cross-sectional views showing the trench structure 16 and the electric field relaxation structure 21. FIGS. 7 to 9 are the same cross-sectional views, differing only in the indicated reference numerals. The shape of the electric field relaxation structure 21 will be described from various aspects with reference to FIGS. 7 to 9.

[0013] 1 to 9 , a semiconductor device 1 includes a chip 2 including a SiC single crystal. The chip 2 may be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, the chip 2 is made of a hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, a 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the chip 2 is made of a 4H-SiC single crystal, but the chip 2 may be made of another polytype.

[0014] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0015] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0016] In the circumferential direction of the chip 2 (counterclockwise in FIG. 1 ) starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0017] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0018] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0019] 4, the chip 2 (first main surface 3 and second main surface 4) has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Do by the off angle θo. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θo.

[0020] The off-direction Do is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle θo may be greater than 0° and less than or equal to 10°. The off-angle θo may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0021] The off angle θo is preferably 5° or less. The off angle θo is particularly preferably 2° or more and 4.5° or less. The off angle θo is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θo is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0022] The chip 2 includes an n-type base layer 6 made of SiC single crystal. The base layer 6 may also be referred to as a "drain region," a "base SiC layer," a "base region," or the like. The base layer 6 extends horizontally in a layered manner and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base layer 6 is made of a substrate made of SiC single crystal (i.e., a SiC substrate). The base layer 6 has the off direction Do and off angle θo described above.

[0023] The base layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration of the base layer 6 may have the following peak value. The base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted with a single pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted with a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted with nitrogen.

[0024] The base layer 6 has a first thickness T1. The first thickness T1 may be 5 μm or more and 300 μm or less. The first thickness T1 may have a value belonging to any one of the following ranges: 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or more, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or more and 300 μm or less. The first thickness T1 is preferably 50 μm or more and 250 μm or less.

[0025] The chip 2 includes a semiconductor layer 7 made of single crystal SiC stacked on a base layer 6. The semiconductor layer 7, which is an example of a first impurity region, may also be referred to as a "drift region," an "SiC layer," a "semiconductor region," or the like. The semiconductor layer 7 extends horizontally in a layered manner and forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the base layer 6.

[0026] The semiconductor layer 7 has a lower end and an upper end. The lower end of the semiconductor layer 7 is the starting point of crystal growth, and the upper end of the semiconductor layer 7 is the ending point of crystal growth. The lower end of the semiconductor layer 7 is also the bottom of the semiconductor layer 7. Since the semiconductor layer 7 is grown continuously from the base layer 6, the lower end of the semiconductor layer 7 coincides with the upper end of the base layer 6.

[0027] The semiconductor layer 7 includes an n-type drift region 8. In this embodiment, the drift region 8 is formed by a portion (n-type portion) of the semiconductor layer 7. More specifically, the drift region 8 is formed by a portion of the semiconductor layer 7 on the second main surface 4 side with respect to a body region 15 (described later) and an electric field relaxation structure 21 (described later) in the vertical direction Z.

[0028] The boundary between the base layer 6 and the semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The semiconductor layer 7 has an off-direction Do and an off-angle θo that are approximately identical to the off-direction Do and the off-angle θo of the base layer 6.

[0029] The n-type impurity concentration of the semiconductor layer 7 (drift region 8) is preferably lower than the n-type impurity concentration of the base layer 6. The semiconductor layer 7 has an n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the semiconductor layer 7 may have a peak value of the following: The n-type impurity concentration of the semiconductor layer 7 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the semiconductor layer 7 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0030] In this embodiment, the n-type impurity concentration of the semiconductor layer 7 is adjusted by nitrogen. The semiconductor layer 7 may have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the semiconductor layer 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the semiconductor layer 7 contains a pentavalent element other than phosphorus.

[0031] The semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 1 μm or more and 10 μm or less. The second thickness T2 may have a value that belongs to any one of the following ranges: 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The second thickness T2 is preferably 2 μm or more and 8 μm or less.

[0032] The semiconductor device 1 includes an active region 9 set in the chip 2. The active region 9 is set in an inner portion of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 9 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 9 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0033] The semiconductor device 1 includes a peripheral region 10 that is set outside the active region 9 in the chip 2. The peripheral region 10 is provided in a region between the periphery of the chip 2 and the active region 9 in a plan view. The peripheral region 10 extends in a band shape along the active region 9 in a plan view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 9.

[0034] The semiconductor device 1 includes an active surface 11, an outer surface 12, and first to fourth connecting surfaces 13A to 13D formed on a first main surface 3. The active surface 11, the outer surface 12, and the first to fourth connecting surfaces 13A to 13D define an active plateau 14 on the first main surface 3.

[0035] The active surface 11 may be referred to as the “first surface portion,” the outer peripheral surface 12 may be referred to as the “second surface portion,” the first to fourth connecting surfaces 13A to 13D may be referred to as “connecting surface portions,” and the active plateau 14 may be referred to as the “active mesa portion.” The active surface 11, the outer peripheral surface 12, and the first to fourth connecting surfaces 13A to 13D (i.e., the active plateaus 14) may be considered to be components of the chip 2 (first main surface 3).

[0036] The active surface 11 is formed in the active region 9. That is, the active surface 11 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 11 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 11 is formed by the c-plane (Si-plane). In this embodiment, the active surface 11 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0037] The outer peripheral surface 12 is formed in the outer peripheral region 10. In other words, the outer peripheral surface 12 is formed outside the active surface 11. The outer peripheral surface 12 is recessed in the thickness direction of the chip 2 (toward the second main surface 4) with respect to the active surface 11. Specifically, in this embodiment, the outer peripheral surface 12 is recessed to a depth less than the thickness of the semiconductor layer 7 so as to expose the semiconductor layer 7. In other words, the outer peripheral surface 12 faces the base layer 6 with a part of the semiconductor layer 7 sandwiched therebetween, exposing the semiconductor layer 7.

[0038] The outer peripheral surface 12 extends in a band shape along the active surface 11 in a plan view and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 11. The outer peripheral surface 12 has a flat surface extending in the first direction X and the second direction Y and is formed substantially parallel to the active surface 11. In this embodiment, the outer peripheral surface 12 is formed by a c-plane (Si-plane). The outer peripheral surface 12 is continuous with the first to fourth side surfaces 5A to 5D.

[0039] The outer peripheral surface 12 has a circumferential depth DO. The circumferential depth DO may be 0.1 μm or more and 2 μm or less. The circumferential depth DO may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The circumferential depth DO is preferably 0.1 μm or more and 1.5 μm or less.

[0040] The first to fourth connection surfaces 13A to 13D extend in the vertical direction Z and connect the active surface 11 and the outer peripheral surface 12. The first connection surface 13A is located on the first side surface 5A side, the second connection surface 13B is located on the second side surface 5B side, the third connection surface 13C is located on the third side surface 5C side, and the fourth connection surface 13D is located on the fourth side surface 5D side. The first connection surface 13A and the third connection surface 13C extend in the first direction X and face the second direction Y. The second connection surface 13B and the fourth connection surface 13D extend in the second direction Y and face the first direction X.

[0041] The first to fourth connection surfaces 13A to 13D may extend substantially perpendicularly between the active surface 11 and the outer peripheral surface 12 so as to define the square-prism-shaped active plateaus 14. The first to fourth connection surfaces 13A to 13D may be inclined obliquely downward from the active surface 11 toward the outer peripheral surface 12 so as to define the square-pyramid-shaped active plateaus 14. In this way, the active plateaus 14 are defined in a protruding shape on the semiconductor layer 7 at the first main surface 3. The active plateaus 14 are formed only on the semiconductor layer 7, and not on the base layer 6.

[0042] 6 to 9, the semiconductor device 1 includes a p-type body region 15 formed in a surface layer portion of the first main surface 3 (active surface 11). In this embodiment, the body region 15, which is an example of a second impurity region, is formed in a layer extending along the active surface 11. The body region 15 may be formed over the entire active surface 11 and exposed from the first to fourth connecting surfaces 13A to 13D. The body region 15 is formed at a distance from the lower end of the semiconductor layer 7 toward the active surface 11. Preferably, the body region 15 is formed at a distance from a depth position of the outer peripheral surface 12 toward the active surface 11 and exposed from the active surface 11.

[0043] The body region 15 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the body region 15 may have the following peak value: The p-type impurity concentration of the body region 15 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 15 may be at least one of boron, aluminum, gallium, and indium.

[0044] The semiconductor device 1 includes a plurality of trench electrode-type trench structures 16 formed in the first main surface 3 (active surface 11) in the active region 9. The trench structures 16 may also be referred to as "gate structures," "trench gate structures," or the like. A gate potential is applied to the plurality of trench structures 16 as a control potential. The plurality of trench structures 16 controls the inversion and non-inversion of a channel (current path) in the body region 15 in response to the gate potential.

[0045] The plurality of trench structures 16 are arranged at intervals inward from the periphery (first to fourth connection surfaces 13A to 13D) of the active surface 11 in the active region 9. In this embodiment, the plurality of trench structures 16 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y.

[0046] That is, the trench structures 16 are arranged at intervals in the m-axis direction and extend in the a-axis direction. In this embodiment, the trench structures 16 are arranged in stripes extending in the a-axis direction (second direction Y). The extension direction of the trench structures 16 coincides with the off-direction Do of the semiconductor layer 7.

[0047] The plurality of trench structures 16 are formed at intervals from the lower end (base layer 6) of the semiconductor layer 7 toward the first main surface 3 (active surface 11), and face the base layer 6 across a part of the semiconductor layer 7. The plurality of trench structures 16 define a lower region 7 a in a region between the bottom walls of the plurality of trench structures 16 and the lower end (base layer 6) of the semiconductor layer 7.

[0048] Each trench structure 16 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z. The trench width WT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench width WT may be 0.1 μm or more and 5 μm or less.

[0049] The trench width WT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0050] The trench depth DT is preferably less than the second thickness T2 of the semiconductor layer 7. It is particularly preferable that the trench depth DT is approximately equal to the aforementioned peripheral depth DO. Of course, the trench depth DT may be equal to or greater than the peripheral depth DO, or may be less than the peripheral depth DO.

[0051] The trench depth DT is preferably greater than the trench width WT. That is, the trench structures 16 preferably each have an aspect ratio DT / WT such that they extend in a vertically elongated columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The trench depth DT may be 0.1 μm or more and 5 μm or less.

[0052] The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, and 4 μm to 5 μm. The trench depth DT is preferably 0.1 μm to 1.5 μm, and more preferably 0.5 μm to 1.5 μm.

[0053] The trench structures 16 are arranged at intervals of a trench pitch PT in the first direction X. The trench pitch PT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench pitch PT is preferably less than the trench depth DT. The trench pitch PT may be 0.1 μm or more and 5 μm or less.

[0054] The trench pitch PT may have a value belonging to any one of the following ranges: 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The trench pitch PT is preferably 0.5 μm to 3 μm, and more preferably 0.5 μm to 1.5 μm.

[0055] Each trench structure 16 includes a trench 17, an insulating film 18, and a buried electrode 19. The trench 17 is formed in the active surface 11 and defines the wall surfaces (sidewalls and bottom wall) of the trench structure 16. The bottom wall of the trench 17 preferably has a flat portion. A mesa portion 20 formed by a part of the semiconductor layer 7 is formed between adjacent trenches 17. The mesa portion 20 may also be referred to as an "element mesa portion." In this embodiment, the plurality of trenches 17 and the plurality of mesa portions 20 are strip-shaped extending along the second direction Y and are alternately arranged in the first direction X. The plurality of trenches 17 and the plurality of mesa portions 20 are arranged in a stripe pattern as a whole.

[0056] It is particularly preferable that the flat portion of the bottom wall of trench 17 extends substantially parallel to first main surface 3. In other words, it is preferable that the bottom wall of trench 17 has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane. In other words, it is preferable that the bottom wall of trench 17 has a flat portion extending in the off direction Do. Of course, the bottom wall of trench 17 may be curved in an arc shape toward the lower end side of semiconductor layer 7.

[0057] The insulating film 18 covers the wall surface of the trench 17. The insulating film 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 18 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 18 include a silicon oxide film made of an oxide of the chip 2.

[0058] The buried electrode 19 is buried in the trench 17 and faces the channel across the insulating film 18. In this embodiment, the buried electrode 19 faces the body region 15 across the insulating film 18. The buried electrode 19 may include p-type or n-type conductive polysilicon.

[0059] The semiconductor device 1 includes a plurality of p-type electric field relaxation structures 21 formed at intervals in the horizontal direction in the semiconductor layer 7. Specifically, the plurality of electric field relaxation structures 21 are formed in the mesa portion 20 and the lower region 7a in the semiconductor layer 7. The plurality of electric field relaxation structures 21 are formed in a thickness range between the lower end of the semiconductor layer 7 and the bottom walls of the plurality of trench structures 16.

[0060] The multiple electric field relaxation structures 21 are arranged at intervals in the first direction X in the lower region 7a, and are each formed in a strip shape extending in the second direction Y. That is, the multiple electric field relaxation structures 21 are arranged at intervals in the m-axis direction and extend in the a-axis direction of the SiC single crystal. The multiple electric field relaxation structures 21 are formed in stripes extending in the a-axis direction (second direction Y), and the extending direction of the multiple electric field relaxation structures 21 coincides with the off-direction Do of the semiconductor layer 7.

[0061] The electric field relaxation structures 21 are arranged at intervals of a relaxation pitch PR in the first direction X. The relaxation pitch PR is preferably at least twice the trench pitch PT.

[0062] The relaxed pitch PR may have a value belonging to any one of the following ranges: 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The relaxed pitch PR is preferably 2.5 μm to 3 μm. In this case, the trench pitch PT is preferably 0.5 μm to 1.5 μm.

[0063] Each electric field relaxation structure 21 is formed integrally with the body region 15 and spans the bottom walls of multiple trenches 17. In this embodiment, each electric field relaxation structure 21 extends downward in the vertical direction Z from the body region 15 sandwiched between two adjacent trenches 17 below the bottom walls of the trenches 17, and spreads in the horizontal direction along the first main surface 3, overlapping the bottom walls of the trenches 17 on both sides.

[0064] Each electric field relaxation structure 21 covers the bottom wall of trench 17. In other words, each electric field relaxation structure 21 forms at least a part of the side wall and bottom wall of trench 17, and is in contact with insulating film 18. Each electric field relaxation structure 21 has a substantially L-shaped exposed surface in each trench 17 that is exposed as the lower part of the side wall of trench 17 and the bottom wall of trench 17 that is continuous with the lower part of the side wall.

[0065] The body region 15 includes a channel portion 22 and a non-channel portion 23. The channel portion 22 is physically and electrically isolated from the electric field relaxation structure 21. A channel is formed along the wall surface of the trench 17 adjacent to the channel portion 22. The non-channel portion 23 is physically and electrically integrated with the electric field relaxation structure 21. The non-channel portion 23 has a bottom wall covered from below by the electric field relaxation structure 21.

[0066] 7 to 9 , the channel portions 22 and the non-channel portions 23 may be arranged alternately in the first direction X, or a plurality of channel portions 22 may be interposed between adjacent non-channel portions 23. In other words, a plurality of electric field relaxation structures 21 may be alternately connected to a plurality of mesa portions 20 arranged in the first direction X with trenches 17 between them, or a plurality of mesa portions 20 to which no electric field relaxation structure 21 is connected may be interposed between mesa portions 20 to which an electric field relaxation structure 21 is connected.

[0067] In this embodiment, the channel portion 22 and the non-channel portion 23 have the same width in the first direction X. The first width W1 of the mesa portion 20 forming the channel portion 22 may be the same as the second width W2 of the mesa portion 20 forming the non-channel portion 23. The first width W1 = the second width W2 is obtained by arranging a plurality of trenches 17 at equal intervals (trench pitch PT) in the first direction X.

[0068] The electric field relaxation structure 21 forms a boundary 24 with the bottom of the non-channel portion 23 between adjacent trenches 17. The boundary 24 is formed linearly in cross section, dividing the mesa portion 20 along the horizontal direction from the sidewall of the trench 17 on one side to the sidewall of the trench 17 on the other side. The boundary 24 divides the mesa portion 20 into the body region 15 (non-channel portion 23) on the first main surface 3 side and the electric field relaxation structure 21 on the second main surface 4 side.

[0069] The boundary portion 24 does not need to be clearly defined by image analysis (for example, SEM image analysis, etc.) because both the body region 15 (non-channel portion 23) and the electric field relaxation structure 21 are p-type. The fact that the body region 15 and the electric field relaxation structure 21 are continuous in the vertical direction Z may be confirmed, for example, by obtaining a profile of the p-type impurity concentration in the vertical direction Z from the first main surface 3 to the second main surface 4.

[0070] 8 , taking into consideration that both the body region 15 and the electric field relaxation structure 21 are p-type, the body region 15 corresponding to the channel portion 22 may be referred to as a “first body region 25 of the second conductivity type,” and the body region 15 corresponding to the non-channel portion 23 and the electric field relaxation structure 21 may be integrally referred to as a “second body region 26 of the second conductivity type.” In this case, the first body regions 25 and the second body regions 26 may be arranged alternately in the first direction X as shown in FIG. 8 , or a plurality of first body regions 25 may be interposed between adjacent second body regions 26.

[0071] The first body region 25 is formed only in the mesa portion 20 between adjacent trenches 17, and has a bottom closer to the first main surface 3 than the bottom wall of the trench 17. On the other hand, the second body region 26 has the mesa portion 20 between adjacent trenches 17 and a protruding portion 27 that protrudes from the mesa portion 20 closer to the second main surface 4 than the bottom wall of the trench 17. The protruding portion 27 of the second body region 26 extends in the horizontal direction along the first main surface 3 and overlaps the bottom walls of the trenches 17 on both sides, covering the bottom walls of the trenches 17 from below.

[0072] Referring to Figure 9, in another aspect, each electric field relaxation structure 21 may integrally have a base portion 28 on the second main surface 4 side of the bottom walls of two adjacent trenches 17, and a protrusion portion 29 sandwiched between the two adjacent trenches 17.

[0073] The base portion 28 overlaps two adjacent trenches 17 and crosses the region between the two trenches 17 in the first direction X. The base portion 28 has a width greater than the trench pitch PT. The base portion 28 has an end portion that protrudes outward in the horizontal direction beyond the region directly below the mesa portion 20.

[0074] The protrusions 29 extend from the base 28 along the sidewalls of each trench 17 to the inside of the mesa 20 and are connected to the bottom of the body region 15. The protrusions 29 are formed over the entire mesa 20, from the bottom wall of the trench 17 to the body region 15 in the vertical direction Z.

[0075] 7 to 9 , each electric field relaxation structure 21 (second body region 26) may have an end portion 30 at a central position of the bottom wall on the non-channel portion 23 side relative to the wall surface (sidewall) of the trench 17 on the channel portion 22 side in the width direction of the trench 17. As a result, the bottom wall of the trench 17 may have a first portion 31 formed on the non-channel portion 23 side in the width direction of the trench 17 and covered by the electric field relaxation structure 21. The bottom wall of the trench 17 may also have a second portion 32 formed on the channel portion 22 side relative to the first portion 31 and covered by the semiconductor layer 7 (drift region 8). Because the portion of the bottom wall of the trench 17 on the channel portion 22 side is covered by the drift region 8, a current path can be sufficiently secured along the wall surface (sidewall and bottom wall) of the trench 17 on the channel portion 22 side. This reduces the on-resistance.

[0076] The bottom of each electric field relaxation structure 21 may be planar and parallel or substantially parallel to the first main surface 3 in the first direction X and the second direction Y. Therefore, in this embodiment, the portion of each electric field relaxation structure 21 closer to the second main surface 4 than the bottom wall of the trench 17 (the protruding portion 27 of the second body region 26) is formed in a substantially rectangular shape in cross section.

[0077] The p-type impurity concentration of the electric field relaxation structure 21 is preferably higher than the p-type impurity concentration of the body region 15. １６ cm －３ 1x10 or more １９ cm －３ The p-type impurity concentration of the electric field relaxation structure 21 may have the following peak value: The p-type impurity concentration of the electric field relaxation structure 21 may be approximately constant in the thickness direction. Of course, the p-type impurity concentration of the electric field relaxation structure 21 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0078] The electric field relaxation structure 21 has a relaxation depth DR in the vertical direction Z that is greater than that of the trench 17. More preferably, the relaxation depth DR of the electric field relaxation structure 21 is at least twice the trench depth DT. Of course, the relaxation depth DR may be less than twice the trench depth DT.

[0079] The relaxation depth DR may have a value in any one of the ranges of more than 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, and 4 μm to 5 μm. The relaxation depth DR is preferably 2 μm to 3 μm, in which case the trench depth DT is preferably 0.5 μm to 1.5 μm.

[0080] Each of the electric field relaxation structures 21 has a relaxation width WR in the arrangement direction. The relaxation width WR is preferably at least wider than the second width W2 (the width of the mesa portion 20 in the non-channel portion 23). Of course, the relaxation width WR may be the same as the second width W2.

[0081] The relaxed width WR may be 0.25 μm or more and 5 μm or less. The relaxed width WR may have a value belonging to any one of the ranges of 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0082] The semiconductor device 1 includes a plurality of source regions 33 formed on one side of a plurality of trench structures 16 in a surface layer portion of the first main surface 3 (active surface 11). The plurality of source regions 33, which are an example of third impurity regions, are formed in a surface layer portion of the body region 15. In this embodiment, the plurality of source regions 33 are selectively formed in the channel portion 22 of the plurality of body regions 15, which include a channel portion 22 and a non-channel portion 23.

[0083] The plurality of source regions 33 have a higher n-type impurity concentration (peak value) than the semiconductor layer 7. The plurality of source regions 33 have a peak value of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0084] 5 , the multiple source regions 33 extend in a strip shape in the extension direction of the corresponding trench structures 16 in a plan view. The multiple source regions 33 are formed at intervals from the bottom of the body region 15 toward the active surface 11, and face the drift region 8 directly below, with part of the body region 15 sandwiched between them in the vertical direction Z. The multiple source regions 33, together with the multiple drift regions 8 directly below, define channels (current paths) that extend along the wall surfaces of the corresponding trench structures 16.

[0085] The semiconductor device 1 includes a plurality of contact regions 34 formed in regions between the plurality of trench structures 16 in the surface layer portion of the first main surface 3 (active surface 11). The plurality of contact regions 34 are formed in the surface layer portion of the body region 15.

[0086] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 15. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of electric field relaxation structures 21. The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of electric field relaxation structures 21. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0087] The plurality of contact regions 34 include a first contact region 35 and a second contact region 36. The first contact region 35 is formed in the non-channel portion 23, and the second contact region 36 is formed in the channel portion 22.

[0088] The first contact region 35 is formed over the entire first main surface 3 between the trench structure 16 on one side of the non-channel portion 23 and the trench structure 16 on the other side. The first contact region 35 extends in a strip shape in the extension direction of the plurality of trench structures 16. The first contact region 35 crosses the mesa portion 20 of the non-channel portion 23 from the trench structure 16 on one side of the non-channel portion 23 to the trench structure 16 on the other side.

[0089] The first contact region 35 is exposed on the wall surfaces (sidewalls) of the trench 17 on both sides of the non-channel portion 23 in the first direction X, and is in contact with the insulating film 18. The first contact region 35 is formed at an interval from the bottom of the body region 15 toward the active surface 11, and faces the drift region 8 directly below in the vertical direction Z, with the body region 15 and part of the electric field relaxation structure 21 sandwiched therebetween.

[0090] The second contact region 36 is interposed in a region between adjacent source regions 33 in the channel portion 22, and extends in a strip shape in the extension direction of the trench structures 16. The second contact region 36 is formed at an interval from the bottom of the body region 15 toward the active surface 11, and faces the drift region 8 directly below, with a part of the body region 15 sandwiched between them in the vertical direction Z.

[0091] In this manner, the source region 33 is selectively formed in the channel portion 22 out of the channel portion 22 and the non-channel portion 23. On the other hand, in this embodiment, the source region 33 is not formed in the non-channel portion 23, and the first contact region 35 is formed in the entire surface portion of the body region 15. This makes it possible to separate the function of the channel portion 22, which forms a current path, from the function of the non-channel portion 23, which ensures electrical contact with the body region 15. As a result, an efficient on-state operation can be achieved.

[0092] In the non-channel portion 23, the lower portion of the body region 15 is completely covered with the electric field relaxation structure 21, and therefore the non-channel portion 23 does not function well as a channel. Therefore, by forming the first contact region 35 over the entire surface portion of the body region 15 in the non-channel portion 23, the potential of the body region 15 can be stabilized.

[0093] The configuration of the outer peripheral region 10 will be described below. Fig. 10 is a perspective view showing the configuration of the outer peripheral region 10. Fig. 11 is a cross-sectional view showing a main part of the outer peripheral region 10.

[0094] The semiconductor device 1 includes a p-type well region 37 formed in a surface layer portion of the outer peripheral surface 12. The well region 37 is formed at an interval from the periphery of the outer peripheral surface 12 (first to fourth side surfaces 5A to 5D) toward the active surface 11 in a plan view, and extends in a band shape along the active surface 11. In this embodiment, the well region 37 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 11 in a plan view.

[0095] The well region 37 is drawn out from the surface layer portion of the outer peripheral surface 12 toward the first to fourth connection surfaces 13A to 13D and extends along the surface layer portions of the first to fourth connection surfaces 13A to 13D. The well region 37 is electrically connected to the body region 15 in the surface layer portion of the active surface 11.

[0096] The well region 37 is formed at a distance from the lower end of the semiconductor layer 7 toward the outer peripheral surface 12, and faces the base layer 6 across a part of the semiconductor layer 7. The well region 37 forms a pn junction with the semiconductor layer 7. The well region 37 has a density of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The well region 37 may have the following p-type impurity concentration as a peak value: The well region 37 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 34 .

[0097] The p-type impurity concentration of the well region 37 may be higher than the p-type impurity concentration of the body region 15. Of course, the p-type impurity concentration of the well region 37 may be lower than the body region 15. The p-type impurity concentration of the well region 37 is preferably adjusted by at least one kind of trivalent element. The trivalent element of the well region 37 may be the same as the trivalent element of the electric field relaxation structure 21, or may be a different kind from the trivalent element of the electric field relaxation structure 21. The trivalent element of the well region 37 may be at least one kind of boron, aluminum, gallium, and indium.

[0098] The semiconductor device 1 includes at least one (preferably two to 20) p-type field region 38 formed in the surface layer of the outer peripheral surface 12 (first main surface 3) in the outer peripheral region 10. The number of the multiple field regions 38 is typically four to eight. The multiple field regions 38 are formed in an electrically floating state and relieve the electric field within the chip 2 at the periphery of the first main surface 3. The number, width, depth, p-type impurity concentration, etc. of the field region 38 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0099] In this embodiment, the field regions 38 are arranged at intervals from the periphery (first to fourth connection surfaces 13A to 13D) of the active surface 11 and the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Specifically, the field regions 38 are arranged at intervals from the well region 37 toward the periphery of the outer circumferential surface 12.

[0100] The plurality of field regions 38 are formed in strip shapes extending along the active region 9 in plan view. Each of the plurality of field regions 38 has a portion extending in strip shape in the first direction X and a portion extending in strip shape in the second direction Y. In this embodiment, the plurality of field regions 38 are formed in an annular shape (specifically, a quadrangular annular shape) surrounding the active region 9 (i.e., the plurality of electric field relaxation structures 21) in plan view.

[0101] The plurality of field regions 38 are formed in the semiconductor layer 7 at intervals from the lower end of the semiconductor layer 7 toward the outer peripheral surface 12, and form pn junctions with the semiconductor layer 7. The plurality of field regions 38 preferably have bottoms located closer to the outer peripheral surface 12 than the intermediate portion of the thickness range of the semiconductor layer 7.

[0102] In this embodiment, the multiple field regions 38 are formed at intervals from the multiple electric field relaxation structures 21 toward the periphery of the chip 2. Therefore, the multiple field regions 38 do not face the multiple electric field relaxation structures 21 in the vertical direction Z. The multiple field regions 38 are located closer to the second main surface 4 of the semiconductor layer 7 than the bottom wall of the trench structure 16.

[0103] The bottoms of the plurality of field regions 38 may be located closer to the first main surface 3 of the semiconductor layer 7 than the depth positions of the bottoms of the plurality of electric field relaxation structures 21. Of course, the bottoms of the plurality of field regions 38 may be located closer to the second main surface 4 of the semiconductor layer 7 than the depth positions of the bottoms of the plurality of electric field relaxation structures 21.

[0104] The plurality of field regions 38 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the field region 38 may be approximately equal to the p-type impurity concentration of the body region 15. The p-type impurity concentrations of the plurality of field regions 38 may be higher than the p-type impurity concentration of the body region 15. The p-type impurity concentrations of the plurality of field regions 38 may be lower than the p-type impurity concentration of the body region 15.

[0105] The p-type impurity concentrations of the plurality of field regions 38 are preferably adjusted by at least one trivalent element. The trivalent element in the field regions 38 may be the same as or different from the trivalent element in the electric field relaxation structure 21. The trivalent element in the field regions 38 may be at least one of boron, aluminum, gallium, and indium.

[0106] The field regions 38 preferably have a width different from the relaxed width WR of the electric field relaxation structure 21. In other words, the electric field relaxation effect of the field regions 38 is preferably adjusted separately from the electric field relaxation structures 21. It is particularly preferable that the width of the field regions 38 be smaller than the relaxed width WR. Of course, the width of the field regions 38 may be larger than the relaxed width WR. Alternatively, the width of the field regions 38 may be approximately equal to the relaxed width WR.

[0107] The field regions 38 are preferably formed at a pitch different from the relaxed pitch PR of the electric field relaxation structure 21. It is particularly preferable that the pitch of the field regions 38 be smaller than the relaxed pitch PR. The pitch of the field regions 38 may be larger than the relaxed pitch PR. The pitch of the field regions 38 may also be approximately equal to the relaxed pitch PR.

[0108] The semiconductor device 1 includes an interlayer insulating film 39 covering the first main surface 3. The interlayer insulating film 39 may also be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this embodiment, the interlayer insulating film 39 has a stacked structure including a first insulating film 40 and a second insulating film 41. The first insulating film 40 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 40 include a silicon oxide film made of an oxide of the chip 2 (semiconductor layer 7).

[0109] The first insulating film 40 selectively covers the first main surface 3 in the active region 9 and the peripheral region 10. Specifically, the first insulating film 40 selectively covers the active surface 11, the peripheral surface 12, and the first to fourth connecting surfaces 13A to 13D. The first insulating film 40 is connected to the insulating film 18 in the active surface 11, exposing the buried electrode 19.

[0110] The first insulating film 40 covers the well region 37 and the multiple field regions 38 on the outer peripheral surface 12. In this embodiment, the first insulating film 40 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the first insulating film 40 may be formed at an interval inward from the periphery of the outer peripheral surface 12, exposing the semiconductor layer 7 from the periphery of the outer peripheral surface 12. The first insulating film 40 covers the body region 15 and the well region 37 on the first to fourth connecting surfaces 13A to 13D.

[0111] The second insulating film 41 is stacked on the first insulating film 40. The second insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 39 preferably includes a silicon oxide film. The second insulating film 41 covers the first main surface 3 in the active region 9 and the peripheral region 10, sandwiching the first insulating film 40 therebetween. Specifically, the second insulating film 41 selectively covers the active surface 11, the peripheral surface 12, and the first to fourth connecting surfaces 13A to 13D, sandwiching the first insulating film 40 therebetween.

[0112] The second insulating film 41 covers the multiple trench structures 16 (buried electrodes 19) in the active region 9. The second insulating film 41 covers the well region 37 and the multiple field regions 38 in the peripheral region 10, sandwiching the first insulating film 40 therebetween. In this embodiment, the second insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the second insulating film 41 may be formed at a distance inward from the periphery of the peripheral surface 12, and may expose the periphery of the first main surface 3 together with the first insulating film 40.

[0113] The semiconductor device 1 includes a plurality of contact openings 42 formed in the interlayer insulating film 39. The plurality of contact openings 42 include a plurality of contact openings 42 (not shown) that expose the plurality of trench structures 16 (buried electrodes 19) and a plurality of contact openings 42 that expose the plurality of source regions 33. The plurality of contact openings 42 for the source regions 33 are formed in regions between the plurality of adjacent trench structures 16, and expose the plurality of source regions 33 and the plurality of contact regions 34.

[0114] The semiconductor device 1 includes a sidewall structure 43 disposed in the interlayer insulating film 39 so as to cover at least one of the first to fourth connecting surfaces 13A to 13D. The sidewall structure 43 is disposed on the first insulating film 40 and is covered by the second insulating film 41. The sidewall structure 43 reduces a step formed between the active surface 11 and the outer peripheral surface 12.

[0115] The sidewall structure 43 is formed in a strip shape extending along at least one of the first to fourth connecting surfaces 13A to 13D. In this embodiment, the sidewall structure 43 is formed in a ring shape (specifically, a rectangular ring shape) extending along the first to fourth connecting surfaces 13A to 13D so as to surround the active surface 11 in a plan view.

[0116] The sidewall structure 43 may have a portion extending in a film-like manner along the outer peripheral surface 12 and a portion extending in a film-like manner along the first to fourth connecting surfaces 13A to 13D. In this embodiment, the sidewall structure 43 is formed at a distance from the innermost field region 38 toward the active surface 11, and faces the well region 37 in the horizontal and vertical directions Z, with the first insulating film 40 sandwiched therebetween. The sidewall structure 43 may face the body region 15, with the first insulating film 40 sandwiched therebetween.

[0117] 1 , semiconductor device 1 includes a gate pad 44 disposed on interlayer insulating film 39. Gate pad 44 is an electrode to which a gate potential is applied from the outside. Gate pad 44 may also be referred to as a "gate pad electrode," a "first pad electrode," or the like. Gate pad 44 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 39 side.

[0118] In this embodiment, the gate pad 44 is disposed on a portion of the interlayer insulating film 39 that covers the active region 9. Specifically, the gate pad 44 is disposed on the active surface 11 at a distance from the outer peripheral surface 12 in a plan view. The gate pad 44 is disposed in a region close to the center of one side of the active surface 11 (the second connection surface 13B in this embodiment) in a plan view.

[0119] Of course, the gate pad 44 may be disposed in a region along any of the central portions of the first to fourth connection surfaces 13A to 13D. Of course, the gate pad 44 may be disposed at any corner of the active surface 11 in a plan view. The gate pad 44 may also be disposed at the central portion of the active surface 11 in a plan view. In this embodiment, the gate pad 44 is formed in a quadrangular shape in a plan view.

[0120] The semiconductor device 1 includes at least one gate wiring 45 (a plurality of gate wirings in this embodiment) extending from the gate pad 44 onto the interlayer insulating film 39. The gate wiring 45 may also be referred to as a "wiring" or "wiring electrode." In this embodiment, the plurality of gate wirings 45 are arranged on the active surface 11 at intervals from the outer peripheral surface 12 in a plan view.

[0121] The plurality of gate wirings 45 may have a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the side of the interlayer insulating film 39. In this embodiment, the plurality of gate wirings 45 include a first gate wiring 45A and a second gate wiring 45B.

[0122] The first gate wiring 45A is drawn out from the gate pad 44 toward the first connection surface 13A and extends in a line along the periphery of the active surface 11 so as to intersect (specifically, perpendicular to) part of (specifically, one end portion) of the multiple trench structures 16. The first gate wiring 45A penetrates the interlayer insulating film 39 via the multiple contact openings 42 and is electrically connected to one end portion of the multiple trench structures 16.

[0123] The second gate wiring 45B is drawn out from the gate pad 44 toward the third connection surface 13C and extends in a line along the periphery of the active surface 11 so as to intersect (specifically, perpendicular to) part of (specifically, the other end portions of) the multiple trench structures 16. The second gate wiring 45B penetrates the interlayer insulating film 39 via the multiple contact openings 42 and is electrically connected to the other end portions of the multiple trench structures 16.

[0124] The semiconductor device 1 includes a source pad 46 disposed on the interlayer insulating film 39 at a distance from the gate pad 44 and the gate wiring 45. The source pad 46 is an electrode to which a source potential is applied from the outside. The source pad 46 may also be referred to as a "source pad electrode," a "second pad electrode," or the like. The source pad 46 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 39 side.

[0125] In this embodiment, the source pad 46 is disposed on the active surface 11 at a distance from the outer peripheral surface 12 in a plan view. In this embodiment, the source pad 46 is formed in a polygonal shape having a recess that is recessed along the gate pad 44 in a plan view. Of course, the source pad 46 may also be formed in a quadrangular shape in a plan view.

[0126] The source pad 46 penetrates the interlayer insulating film 39 via the plurality of contact openings 42, and is electrically connected to the body region 15, the plurality of source regions 33, and the plurality of contact regions 34. In other words, the source pad 46 is electrically connected to the plurality of electric field relaxation structures 21 via the body region 15.

[0127] The semiconductor device 1 includes a drain pad 47 covering the second main surface 4. The drain pad 47 is an electrode to which a drain potential is applied from the outside. The drain pad 47 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 47 forms ohmic contact with the base layer 6 exposed from the second main surface 4.

[0128] That is, the drain pad 47 is electrically connected to the plurality of drift regions 8 via the base layer 6. The drain pad 47 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 47 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0129] The breakdown voltage that can be applied between source pad 46 and drain pad 47 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0130] 12 is a schematic diagram showing a wafer 50 used in manufacturing the semiconductor device 1. The wafer 50 is a substrate of the base layer 6 and contains a SiC single crystal. The wafer 50 is formed in a flat disk shape. Of course, the wafer 50 may also be formed in a flat rectangular parallelepiped shape. The wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.

[0131] The first wafer main surface 51 corresponds to the upper end of the base layer 6, and the second wafer main surface 52 corresponds to the lower end of the base layer 6. The first wafer main surface 51 and the second wafer main surface 52 are formed by the c-plane of the SiC single crystal. The first wafer main surface 51 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 52 is formed by the carbon surface of the SiC single crystal. The wafer 50 (the first wafer main surface 51 and the second wafer main surface 52) has the off-direction Do and the off-angle θo described above.

[0132] The wafer 50 has a mark 54 on the wafer side surface 53 that indicates the crystal orientation of the SiC single crystal. The mark 54 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 51 in a plan view.

[0133] The mark 54 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 54 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction. Figure 12 shows an orientation flat extending in the m-axis direction (first direction X) in a plan view.

[0134] For example, a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like. Each device region 55 corresponds to a semiconductor device 1. Each of the plurality of device regions 55 is set to have a quadrangular shape in a plan view.

[0135] In this embodiment, the device regions 55 are set in a matrix along the first direction X and the second direction Y in a plan view. The device regions 55 are set at intervals inward from the periphery of the first wafer main surface 51 in a plan view. The cutting lines 56 are set in a grid pattern extending along the first direction X and the second direction Y to partition the device regions 55.

[0136] Fig. 13 is a flowchart showing an example of a method for manufacturing the semiconductor device 1. Fig. 14A to Fig. 14H are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1. Fig. 14A to Fig. 14H are cross-sectional views corresponding to Fig. 7.

[0137] 14A, the aforementioned wafer 50 preparation step is performed (step S1 in FIG. 13). Next, the semiconductor layer 7 formation step is performed (step S2 in FIG. 13). The semiconductor layer 7 is formed by epitaxial growth starting from the first wafer main surface 51 (wafer 50).

[0138] 14B , the step of forming body region 15 is performed (step S3 in FIG. 13 ). In the step of forming body region 15, p-type impurities are introduced into the entire semiconductor layer 7. As a result, body region 15 is formed over the entire surface portion of semiconductor layer 7.

[0139] Next, referring to FIG. 14C , a step of forming a first mask 60 having a predetermined pattern is performed (step S4 in FIG. 13 ). The first mask 60 is preferably an inorganic mask (hard mask). The first mask 60 is disposed on the upper end of the semiconductor layer 7 and has a plurality of first openings 61 that expose regions where a plurality of electric field relaxation structures 21 are to be formed. Next, a step of forming a plurality of electric field relaxation structures 21 is performed (step S5 in FIG. 13 ). In the step of forming the electric field relaxation structures 21, p-type impurities are selectively introduced into the semiconductor layer 7 through the first mask 60. This forms the electric field relaxation structures 21 connected to the lower portion of the body region 15.

[0140] Various ion implantation methods can be applied as a method for forming the electric field relaxation structure 21. For example, the electric field relaxation structure 21 may be formed by a channeling ion implantation method. The channeling implantation process is performed based on data (information) of the off-angle θo. The channeling implantation process allows the electric field relaxation structure 21 to be selectively and easily formed at a deep position in the semiconductor layer 7. When the electric field relaxation structure 21 is formed by a channeling ion implantation method, the electric field relaxation structure 21 may be formed before the body region 15.

[0141] Next, referring to FIG. 14D, the first mask 60 is removed (step S6 in FIG. 13).

[0142] 14E, a step of forming a plurality of source regions 33 is performed (step S7 in FIG. 13). The plurality of source regions 33 are formed by introducing n-type impurities into the surface layer portion of the semiconductor layer 7 by ion implantation using a mask (not shown) having a predetermined layout.

[0143] 14F, a step of forming a plurality of contact regions 34 is performed (step S8 in FIG. 13). The plurality of contact regions 34 are formed by introducing p-type impurities into the surface layer of the semiconductor layer 7 by ion implantation using a mask (not shown) having a predetermined layout. At this time, the first contact region 35 and the second contact region 36 are formed physically independent of each other. The step of forming the contact regions 34 may be performed prior to the step of forming the source region 33.

[0144] Next, referring to FIG. 14G, a process for forming multiple trenches 17 is performed. First, a second mask (not shown) having a predetermined pattern is formed (step S9 in FIG. 13). The second mask is preferably an inorganic mask (hard mask). Next, unnecessary portions of the semiconductor layer 7 are removed by etching through the second mask. The etching method may be either wet etching or dry etching, or both. The etching method is preferably RIE (reactive ion etching). This forms multiple trenches 17 at the upper end of the semiconductor layer 7 (step S10 in FIG. 13). In addition, the active surface 11, the outer peripheral surface 12, and the first to fourth connection surfaces 12A to 12D are formed at the upper end of the semiconductor layer 7. After the process for forming the multiple trenches 17, the second mask is removed.

[0145] Next, referring to FIG. 14H , a step of forming insulating film 18 is performed (step S11 in FIG. 13 ). The step of forming insulating film 18 also serves as a step of forming first insulating film 40. Insulating film 18 may be formed by either or both of a CVD (Chemical Vapor Deposition) method and an oxidation treatment method. Insulating film 18 and first insulating film 40 are typically formed by a thermal oxidation treatment method. Insulating film 18 is formed in the form of a film on the wall surfaces of the plurality of trenches 17, and first insulating film 40 is formed in the form of a film in the region of the upper end of semiconductor layer 7 outside the plurality of trenches 17.

[0146] Next, a buried electrode 19 formation step is performed (step S12 in FIG. 13 ). This step includes a step of forming a base electrode film on the insulating film 18. In this embodiment, the base electrode film includes conductive polysilicon. The base electrode film backfills the multiple trenches 17 and covers the upper end of the semiconductor layer 7. The base electrode film may be formed by a CVD method. Next, unnecessary portions of the buried electrode 19 are removed by an etching method. The unnecessary portions of the buried electrode 19 are removed until the insulating film 18 is exposed. The etching method may be either a wet etching method or a dry etching method, or both. As a result, multiple buried electrodes 19 are respectively embedded in the multiple trenches 17, and multiple trench structures 16 are formed.

[0147] Next, a step of forming an interlayer insulating film 39 (second insulating film 41) is performed (step S13 in FIG. 13). The interlayer insulating film 39 may be formed by a CVD method. A plurality of contact openings 42 having a predetermined layout are formed in the interlayer insulating film 39 by an etching method using a mask (not shown) having a predetermined layout.

[0148] Next, a process for forming the gate pad 44, the gate wiring 45, and the source pad 46 is performed (step S14 in FIG. 13). The gate pad 44, the gate wiring 45, and the source pad 46 are formed by depositing a metal film on the interlayer insulating film 39 by sputtering, and then shaping the metal film into a predetermined layout by etching using a mask (not shown) having a predetermined layout.

[0149] Next, a step of forming drain pads 47 is carried out (step S15 in FIG. 13). The drain pads 47 are formed by depositing a metal film on the second wafer main surface 52 by sputtering. Thereafter, the wafer 50 is cut along a plurality of cutting lines 56 (step S16 in FIG. 13). Through the steps including those described above, a plurality of semiconductor devices 1 are manufactured from a single wafer 50.

[0150] As described above, the electric field relaxation structure 21 is formed on the bottom wall of the trench 17, so that electric field concentration on the bottom wall of the trench 17 in the trench gate structure related to the MISFET (Metal Insulator Semiconductor Field Effect Transistor) can be relaxed.

[0151] The electric field relaxation structure 21 is not formed one-to-one with each trench 17, but straddles the bottom walls of multiple trenches 17. In this configuration, one electric field relaxation structure 21 straddles the bottom walls of two adjacent trenches 17. This allows the dimensions of the electric field relaxation structure 21 (e.g., relaxation width WR, relaxation pitch PR, etc.) to be set by an independent design that does not depend on the width WT of each trench 17 or the pitch PT of the multiple trenches 17. As a result, the electric field relaxation structure 21 can be easily fabricated by appropriate design.

[0152] Therefore, even under design conditions where the pitch PT of the pattern of the multiple trench structures 16 is narrow due to miniaturization, a sufficient processing dimension margin can be obtained by using a pattern of electric field relaxation structure 21 having a width WR wider than the trench pitch PT. For example, if trench pitch PT = relaxation pitch PR, even if the mask pattern is misaligned even slightly during formation of electric field relaxation structure 21, electric field relaxation structure 21 will be formed horizontally away from trench 17, and the bottom wall of trench 17 will not be covered with electric field relaxation structure 21, which could result in a decrease in breakdown voltage. However, with semiconductor device 1 of this embodiment, even if the mask pattern is misaligned during formation of electric field relaxation structure 21, electric field relaxation structure 21 is formed wide in the horizontal direction, so the bottom wall of trench 17 can be reliably covered with electric field relaxation structure 21.

[0153] 14C and 14D , the electric field relaxation structure 21 must be formed deeper than the body region 15, so the first mask 60 must be formed relatively thick. This is because implanting ions deep into the trench 17 requires ion acceleration at high energy, preventing the accelerated ions from penetrating the first mask 60. Therefore, as the width of the first mask 60 narrows due to miniaturization, the aspect ratio of the first mask 60 tends to increase. A high aspect ratio reduces the durability of the first mask 60 against external forces, making it more likely to collapse or tilt due to its own weight or external forces. In contrast, if the dimensions of the electric field relaxation structure 21 (e.g., relaxation width WR, relaxation pitch PR, etc.) can be designed independently of the dimensions of the trench 17, the aspect ratio of the first mask 60 can be kept low. As a result, the electric field relaxation structure 21 can be formed with high precision even when the trench 17 is miniaturized.

[0154] Furthermore, the portion of the body region 15 that is physically and electrically integrated with the electric field relaxation structure 21 is covered with the second conductivity type portion (the body region 15 and the electric field relaxation structure 21) from the sidewall to the bottom wall of the trench 17. Because the range in which an inversion layer should be formed along the inner wall of the trench 17 is longer, the voltage (threshold voltage) required to form a channel tends to be selectively higher than that in the channel portion 22. Therefore, by making the portion of the body region 15 that is physically and electrically integrated with the electric field relaxation structure 21 into a non-channel portion 23, it is possible to suppress variations in the threshold voltage of the semiconductor device 1.

[0155] 15 to 20 are diagrams showing first to sixth modified examples of the semiconductor device 1. Next, the modified examples of the semiconductor device 1 will be described with reference to FIGS.

[0156] 15 , each electric field relaxation structure 21 may have an end 30 at a position on the wall surface (sidewall) of trench 17 on the channel portion 22 side in the width direction of trench 17. For example, in a cross-sectional view, the wall surface (sidewall) of trench 17 and end 30 of electric field relaxation structure 21 may be linearly continuous in the vertical direction Z.

[0157] With this configuration, the bottom wall of trench 17 is completely covered with electric field relaxation structure 21, further reducing the electric field concentration on the bottom wall of trench 17. However, compared to the structures shown in FIGS. 7 to 9 , electric field relaxation structure 21 acts as an obstacle, making it more difficult for a current path to form on the portion of the bottom wall of trench 17 on the channel portion 22 side. Therefore, compared to the structures shown in FIGS. 7 to 9 , there is a possibility that the on-resistance may increase. In other words, the structures shown in FIGS. 7 to 9 can achieve a good balance between reducing the electric field concentration on the bottom wall of trench 17 and reducing the on-resistance.

[0158] Referring to Figure 16, the end 30 of each electric field relaxation structure 21 may not be a flat surface parallel or approximately parallel to the vertical direction Z from the bottom wall of the trench 17, but may be a curved surface bulging toward the channel portion 22 in the horizontal direction (at least one of the first direction X and the second direction Y).

[0159] In this case, the curved apex 70 of the end 30 of each electric field relaxation structure 21 is preferably located more inward (closer to the non-channel portion 23) than the wall surface (sidewall) of the trench 17 on the channel portion 22 side. In other words, the curved end 30 is preferably formed to be set back horizontally toward the non-channel portion 23 side from the wall surface (sidewall) of the trench 17 on the channel portion 22 side. This allows the drift region 8 to cover the channel portion 22 side portion of the bottom wall of the trench 17, thereby ensuring a sufficient current path along the wall surface (sidewall and bottom wall) of the trench 17 on the channel portion 22 side. As a result, the on-resistance can be reduced.

[0160] 17 , a source region 33 may be formed in a part of non-channel portion 23. For example, a plurality of source regions 33 may be formed at intervals in the extension direction of corresponding trench structures 16 in a plan view.

[0161] In the non-channel portion 23, the electric field relaxation structure 21 having a higher p-type impurity concentration than the body region 15 is formed, and therefore a channel (inversion layer) is less likely to be formed in the non-channel portion 23 than in the channel portion 22. Under these conditions, by forming a source region 33 in the non-channel portion 23, the non-channel portion 23 can also be endowed with the function of channel formation.

[0162] Referring to FIG. 18, the first width W1 of the mesa portion 20 forming the channel portion 22 may be wider than the second width W2 of the mesa portion 20 forming the non-channel portion 23.

[0163] According to this configuration, by making the first width W1 wider than the second width W2, the ratio of the channel section 22 to the entire chip 2 can be increased, thereby improving the channel density.

[0164] 19 , the plurality of electric field relief structures 21 may straddle the bottom walls of three or more trenches 17 that are continuous in the first direction X. In this case, each electric field relief structure 21 straddles the bottom walls of trenches 17 on both ends of the three or more trenches 17 that are continuous in the first direction X. In FIG. 19 , each electric field relief structure 21 straddles the bottom walls of three trenches 17 that are continuous in the first direction X.

[0165] Of the three trenches 17, the bottom wall of the central trench 17 is completely covered by the electric field relaxation structure 21. The body regions 15 on both sides of the central trench 17 in the first direction X are non-channel portions 23 connected to the electric field relaxation structure 21. Of the three trenches 17, the bottom walls of the two trenches 17 on both ends are partially covered by the electric field relaxation structure 21. As a result, the bottom walls of the two trenches 17 on both ends have a first portion 31 covered by the electric field relaxation structure 21 and a second portion 32 covered by the semiconductor layer 7 (drift region 8).

[0166] 20, the element structure of semiconductor device 1 may be an IGBT (Insulated Gate Bipolar Transistor) structure, different from the MISFET structure of FIGS. 7 to 9. In this case, a p-type collector region 71 may be formed instead of base layer 6. Furthermore, a p-type base region 72 may be formed by body region 15, and an n-type emitter region 73 may be formed by source region 33.

[0167] In this configuration as well, the electric field relaxation structure 21 straddles the bottom walls of a plurality of trenches 17. This makes it possible to relax the electric field concentration on the bottom walls of the trenches 17 in the trench gate structure of the IGBT.

[0168] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0169] For example, in each of the above-described embodiments, the base layer 6 and the semiconductor layer 7 each include a SiC single crystal. However, at least one of the base layer 6 and the semiconductor layer 7 or all of the base layer 6 and the semiconductor layer 7 may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0170] Wide bandgap semiconductors are semiconductors that have a bandgap larger than that of silicon. Wide bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga ２ O ３ ) are examples. The base layer 6 and the semiconductor layer 7 may be made of the same type of single crystal, or may be made of different types of single crystal. Furthermore, at least one of the base layer 6 and the semiconductor layer 7 or all of them may be made of silicon (Si).

[0171] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0172] [Supplementary Note 1-1] A semiconductor device (1) comprising: a chip (2) having a first main surface (3) and a second main surface (4) opposite thereto; first impurity regions (7, 8) of a first conductivity type formed in a surface layer portion of the first main surface (3); second impurity regions (15, 72) of a second conductivity type formed in a surface layer portion of the first impurity regions (7, 8); third impurity regions (33, 73) of a first conductivity type formed in a surface layer portion of the second impurity regions (15, 72); a plurality of trenches (17) extending from the first main surface (3) through the third impurity regions (33, 73) and the second impurity regions (15, 72) to reach the first impurity regions (7, 8); and a second conductivity type electric field relaxation structure (21) formed integrally with the second impurity regions (15, 72) and spanning the bottom walls of the plurality of trenches (17).

[0173] According to this configuration, an electric field relaxation structure (21) is formed on the bottom wall of the trench (17), thereby reducing electric field concentration on the bottom wall of the trench (17). The electric field relaxation structure (21) is not formed one-to-one with each trench (17), but spans the bottom walls of multiple trenches (17). This allows the dimensions of the electric field relaxation structure (21) to be set independently, independent of the width of each trench (17) or the pitch of the multiple trenches (17). As a result, by appropriately designing, the electric field relaxation structure (21) can be easily fabricated. For example, even under design conditions where the pitch of the multiple trench (17) patterns is narrow due to miniaturization, a sufficient processing dimensional margin can be obtained by utilizing a pattern of the electric field relaxation structure (21) having a width wider than the pitch of the trenches (17).

[0174] [Supplementary Note 1-2] The semiconductor device (1) according to Supplementary Note 1-1, wherein the second impurity region (15, 72) includes a channel portion (22) that is physically and electrically separated from the electric field relaxation structure (21), and in which a channel is formed along the trench (17) adjacent to the channel portion (22), and a non-channel portion (23) that is physically and electrically integrated with the electric field relaxation structure (21) and has a bottom wall covered by the electric field relaxation structure (21).

[0175] The portion of the second impurity region (15, 72) that is physically and electrically integrated with the electric field relaxation structure (21) is covered with the second conductivity type portion (the second impurity region (15, 72) and the electric field relaxation structure (21)) from the sidewall to the bottom wall of the trench (17). Since the range in which an inversion layer should be formed along the inner wall of the trench (17) becomes longer, the voltage required for channel formation (threshold voltage) tends to be selectively high in that portion. Therefore, by making the portion of the second impurity region (15, 72) that is physically and electrically integrated with the electric field relaxation structure (21) a non-channel portion (23), it is possible to suppress variations in the threshold voltage.

[0176] [Supplementary Note 1-3] The semiconductor device (1) according to Supplementary Note 1-2, wherein the channel portion (22) has a width (W1) wider than the non-channel portion (23).

[0177] According to this configuration, by making the width (W1) of the channel portion (22) wider than the non-channel portion (23), the ratio of the channel portion (22) to the entire chip (2) can be increased, thereby improving the channel density.

[0178] [Appendix 1-4] The semiconductor device (1) according to Appendix 1-2 or Appendix 1-3, wherein the electric field relaxation structure (21) has an end (30) at a central position of the bottom wall on the non-channel portion (23) side relative to a wall surface of the trench (17) on the channel portion (22) side in the width direction of the trench (17).

[0179] According to this configuration, a gap is provided between the electric field relaxation structure (21) and the wall surface of the trench (17) on the channel portion (22) side, so that a sufficient current path can be secured along the wall surface of the trench (17) on the channel portion (22) side, thereby reducing the on-resistance.

[0180] [Appendix 1-5] The semiconductor device (1) according to any one of Appendices 1-2 to 1-4, wherein the bottom wall of the trench (17) includes a first portion (31) formed on the non-channel portion (23) side in the width direction of the trench (17) and covered by the electric field relaxation structure (21), and a second portion (32) formed on the channel portion (22) side of the first portion (31) and covered by the first impurity regions (7, 8).

[0181] With this configuration, the portion of the bottom wall of the trench (17) on the channel portion (22) side is covered with the first impurity regions (7, 8) (first conductivity type), so that a sufficient current path can be secured along the wall surface of the trench (17) on the channel portion (22) side, thereby reducing the on-resistance.

[0182] [Supplementary Note 1-6] The semiconductor device (1) according to any one of Supplementary Note 1-2 to Supplementary Note 1-5, wherein the third impurity region (33, 73) is selectively formed in the channel portion (22) of the channel portion (22) and the non-channel portion (23), and further includes a fourth impurity region (34, 35, 36) of a second conductivity type that is formed in a surface layer portion of the second impurity region (15, 72) and has a higher impurity concentration than the second impurity region (15, 72), and the fourth impurity region (34, 35, 36) includes a first contact region (35) formed in the non-channel portion (23).

[0183] According to this configuration, the third impurity region (33, 73) is selectively formed in the channel portion (22) of the channel portion (22) and the non-channel portion (23). On the other hand, the third impurity region (33, 73) is not formed in the non-channel portion (23), and the first contact region (35) is formed instead. By separating the function of the channel portion (22) that forms a current path from the function of the non-channel portion (23) that ensures electrical contact with the second impurity region (15, 72), an efficient on-state operation can be achieved.

[0184] [Appendix 1-7] The semiconductor device (1) according to appendix 1-6, wherein the fourth impurity region (34, 35, 36) includes a second contact region (36) that penetrates the third impurity region (33, 73) in the channel portion (22) and is connected to the second impurity region (15, 72).

[0185] According to this configuration, electrical contact with the second impurity region (15, 72) can be ensured even in the channel portion (22).

[0186] [Supplementary Note 1-8] The semiconductor device (1) according to Supplementary Note 1-7, wherein the channel portion (22) and the non-channel portion (23) are each partitioned into regions sandwiched between a plurality of the trenches (17), the first contact region (35) is formed over the entire first main surface (3) between the trench (17) on one side of the non-channel portion (23) and the trench (17) on the other side, and the second contact region (36) is formed sandwiched between a plurality of the third impurity regions (33, 73) arranged adjacent to each of the trenches (17) on one side of the channel portion (22) and the trenches (17) on the other side.

[0187] According to this configuration, in the channel portion 22, channels can be formed on the wall surfaces of both the one-side trench 17 and the other-side trench 17. Since multiple current paths can be formed in one channel portion 22, the on-resistance can be reduced.

[0188] [Appendix 1-9] The semiconductor device (1) according to any one of Appendices 1-1 to 1-8, wherein a plurality of the electric field relaxation structures (21) are arranged at intervals, and the pitch (PR) between adjacent electric field relaxation structures (21) is at least twice the pitch (PT) between adjacent trenches (17).

[0189] According to this configuration, even when a fine trench (17) pattern is formed, a relatively large margin can be provided for the processing dimensions of the electric field relaxation structure (21), thereby facilitating the fabrication of the electric field relaxation structure (21).

[0190] [Appendix 1-10] The semiconductor device (1) according to appendix 1-9, wherein the pitch (PT) of the trenches (17) is 4 μm or less.

[0191] [Appendix 1-11] The semiconductor device (1) according to appendix 1-9 or appendix 1-10, wherein the pitch (PT) of the trenches (17) is 0.5 μm or more and 3 μm or less.

[0192] [Appendix 1-12] The semiconductor device (1) according to any one of appendices 1-1 to 1-11, wherein the depth (DR) of the electric field relaxation structure (21) is at least twice the depth (DT) of the trench (17).

[0193] [Appendix 1-13] The semiconductor device (1) according to any one of Appendices 1-1 to 1-12, wherein the depth (DT) of the trench (17) is 0.5 μm or more and 1.5 μm or less, and the depth (DR) of the electric field relaxation structure (21) is 2 μm or more and 3 μm or less.

[0194] [Appendix 1-14] The semiconductor device (1) according to any one of Appendices 1-9 to 1-11, wherein the plurality of electric field relaxation structures (21) include at least one electric field relaxation structure (21) spanning the bottom walls of two adjacent trenches (17).

[0195] [Appendix 1-15] The semiconductor device (1) according to any one of Appendices 1-9 to 1-11, wherein the plurality of electric field relaxation structures (21) include at least one electric field relaxation structure (21) spanning the bottom walls of the trenches (17) at both ends of three consecutive trenches (17).

[0196] [Appendix 1-16] The semiconductor device (1) according to any one of Appendices 1-1 to 1-15, including: a drain region (6) of a first conductivity type formed on the second main surface (4) side of the first impurity region (7, 8); a body region (15) formed by the second impurity region (15, 72); a source region (33) formed by the third impurity region (33, 73); and a trench gate structure (16) formed by the trench (17), an insulating film (18) covering a wall surface of the trench (17), and a buried electrode (19) buried in the trench (17).

[0197] According to this configuration, it is possible to easily manufacture a structure capable of alleviating electric field concentration on the bottom wall of a trench gate structure (16) related to a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

[0198] [Appendix 1-17] The semiconductor device (1) according to any one of Appendices 1-1 to 1-15, including: a collector region (71) of a second conductivity type formed on the second main surface (4) side of the first impurity region (7, 8); a base region (72) formed by the second impurity region (15, 72); an emitter region (73) formed by the third impurity region (33, 73); and a trench gate structure (16) formed by the trench (17), an insulating film (18) covering a wall surface of the trench (17), and a buried electrode (19) buried in the trench (17).

[0199] According to this configuration, it is possible to easily manufacture a structure that can alleviate the electric field concentration on the bottom wall of the trench gate structure (16) related to an IGBT (Insulated Gate Bipolar Transistor).

[0200] [Appendix 1-18] The semiconductor device (1) according to any one of Appendices 1-1 to 1-17, wherein the chip (2) includes a SiC chip (2).

[0201] [Supplementary Note 1-19] The semiconductor device (1) according to any one of Supplementary Note 1-1 to Supplementary Note 1-18, wherein the electric field relaxation structure (21) has a higher impurity concentration than the second impurity region (15, 72).

[0202] [Supplementary Note 1-20] The impurity concentration of the second impurity region (15, 72) is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The impurity concentration of the electric field relaxation structure (21) is 1×10 １６ cm －３ 1x10 or more １９ cm －３The semiconductor device (1) described in Appendix 1-19 below.

[0203] 1: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: Base layer 7: Semiconductor layer 7a: Lower region 8: Drift region 9: Active region 10: Peripheral region 11: Active surface 12: Peripheral surface 12A: First connection surface 12B: Second connection surface 12C: Third connection surface 12D: Fourth connection surface 13A: First connection surface 13B: Second connection surface 13C: Third connection surface 13D: Fourth connection surface 14: Active plateau 15: Body region 16: Trench structure 17: Trench 18: Insulating film 19: Buried electrode 20: Mesa portion 21: electric field relaxation structure 22: channel portion 23: non-channel portion 24: boundary portion 25: first body region 26: second body region 27: protrusion portion 28: base portion 29: protrusion portion 30: end portion 31: first portion 32: second portion 33: source region 34: contact region 35: first contact region 36: second contact region 37: well region 38: field region 39: interlayer insulating film 40: first insulating film 41: second insulating film 42: contact opening 43: sidewall structure 44: gate pad 45: gate wiring 45A: first gate wiring 45B: second gate wiring 46: source pad 47: drain pad 50: wafer 51: first wafer main surface 52 : Second wafer main surface 53 : Wafer side surface 54 : Mark 55 : Device region 56 : Cutting line 60 : First mask 61 : First opening 71 : Collector region 72 : Base region 73 : Emitter region DO : Periphery depth DR : Relaxation depth DT : Trench depth Do : Off direction PR : Relaxation pitch PT : Trench pitch T1 : First thickness T2 : Second thickness W1 : First width W2 : Second width WR : Relaxation width WT : Trench width X : First direction Y : Second direction Z : Vertical direction θo : Off angle

Claims

1. A chip having a first main surface and a second main surface on the opposite side, A first impurity region of a first conductivity type formed on the surface layer of the first main surface, A second impurity region of a second conductivity type formed on the surface of the first impurity region, A third impurity region of the first conductivity type formed on the surface of the second impurity region, A plurality of trenches extending from the first main surface through the third impurity region and the second impurity region to the first impurity region, A semiconductor device comprising a second conductivity type field relaxation structure formed integrally with the second impurity region and spanning the bottom walls of the plurality of trenches.

2. The semiconductor device according to claim 1, wherein the second impurity region is a channel portion physically and electrically separated from the field relaxation structure, the channel portion comprising a channel formed along the trench adjacent to the channel portion, and a non-channel portion that is physically and electrically integrated with the field relaxation structure and has a bottom wall covered by the field relaxation structure.

3. The semiconductor device according to claim 2, wherein the channel portion has a wider width than the non-channel portion.

4. The semiconductor device according to claim 2, wherein the electric field relaxation structure has an end in the width direction of the trench that is located at the center of the bottom wall on the non-channel side rather than the wall surface of the trench on the channel side.

5. The semiconductor device according to any one of claims 2 to 4, wherein the bottom wall of the trench includes a first portion formed on the non-channel side in the width direction of the trench and covered by the electric field relaxation structure, and a second portion formed on the channel side relative to the first portion and covered by the first impurity region.

6. The third impurity region is selectively formed in the channel portion of the channel portion and the non-channel portion. The material further includes a fourth impurity region of a second conductivity type, which is formed on the surface of the second impurity region and has a higher impurity concentration than the second impurity region. The semiconductor device according to any one of claims 2 to 4, wherein the fourth impurity region includes a first contact region formed in the non-channel portion.

7. The semiconductor device according to claim 6, wherein the fourth impurity region includes a second contact region in the channel portion that penetrates the third impurity region and is connected to the second impurity region.

8. The channel portion and the non-channel portion are each partitioned into regions sandwiched between the multiple trenches. The first contact region is formed over the entire first main surface between the trench on one side of the non-channel portion and the trench on the other side. The semiconductor device according to claim 7, wherein the second contact region is formed by being sandwiched between a plurality of third impurity regions arranged adjacent to each of the trenches on one side and the other side of the channel portion.

9. Multiple of the aforementioned electric field relaxation structures are arranged at intervals, The semiconductor device according to any one of claims 1 to 4, wherein the pitch of adjacent electric field relaxation structures is at least twice the pitch of adjacent trenches.

10. The semiconductor device according to claim 9, wherein the pitch of the trench is 4 μm or less.

11. The semiconductor device according to claim 10, wherein the pitch of the trench is 0.5 μm or more and 3 μm or less.

12. The semiconductor device according to claim 9, wherein the depth of the electric field relaxation structure is twice or more the depth of the trench.

13. The depth of the trench is 0.5 μm or more and 1.5 μm or less. The semiconductor device according to claim 12, wherein the depth of the electric field relaxation structure is 2 μm or more and 3 μm or less.

14. The semiconductor device according to claim 9, wherein the plurality of electric field relaxation structures include at least one electric field relaxation structure that spans the bottom walls of two adjacent trenches.

15. The semiconductor device according to claim 9, wherein the plurality of electric field relaxation structures include at least one electric field relaxation structure that spans the bottom walls of the trenches at both ends of three consecutive trenches.

16. A drain region of the first conductivity type formed on the second main surface side with respect to the first impurity region, The body region formed by the second impurity region, The source region formed by the third impurity region, A semiconductor device according to any one of claims 1 to 4, comprising the trench, an insulating film covering the wall surface of the trench, and a trench gate structure formed by embedded electrodes embedded in the trench.

17. A second conductivity type collector region formed on the second main surface side with respect to the first impurity region, The base region formed by the second impurity region, The emitter region formed by the third impurity region, A semiconductor device according to any one of claims 1 to 4, comprising the trench, an insulating film covering the wall surface of the trench, and a trench gate structure formed by embedded electrodes embedded in the trench.

18. The semiconductor device according to any one of claims 1 to 4, wherein the chip includes a SiC chip.

19. The semiconductor device according to any one of claims 1 to 4, wherein the electric field relaxation structure has an impurity concentration higher than that of the second impurity region.

20. The impurity concentration in the second impurity region is 1 × 10⁻⁶ １５ cm －３ The above 1 x 10 １８ cm －３ The following: The impurity concentration of the aforementioned electric field relaxation structure is 1 × 10 １６ cm －３ The above 1 x 10 １９ cm －３ The semiconductor device according to claim 19, which is as follows: