Semiconductor device and control method for semiconductor device

Abstract

The present disclosure relates to a semiconductor device comprising: an n-type first semiconductor layer which is provided between a first main surface and a second main surface of a semiconductor substrate; a p-type second semiconductor layer which is provided between the first semiconductor layer and the first main surface; an n-type third semiconductor layer which is provided on the side of the second semiconductor layer that is toward the first main surface; a p-type fourth semiconductor layer which is provided between the first semiconductor layer and the second main surface; a first and a second trench which penetrate through the second semiconductor layer from the first main surface and which reach the inside of the first semiconductor layer; a first and a second control electrode which are embedded inside of the first and the second trench, respectively, with a first and a second gate insulating film therebetween; and an n-type fifth semiconductor layer which is the upper layer part of the first semiconductor layer below the second semiconductor layer and which is provided so as to be in contact with the second gate insulating film of the second trench, wherein the fifth semiconductor layer has a second impurity concentration higher than a first impurity concentration of the first semiconductor layer and is provided so as to not be in contact with the first gate insulating film of the first trench.

Description

Semiconductor device and method for controlling the semiconductor device

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a double gate structure.

[0002] In order to improve the switching performance of an insulated gate bipolar transistor (IGBT), a double-gate IGBT has been developed in which a double-gate structure as disclosed in Patent Document 1 is applied to the IGBT.

[0003] The double-gate IGBT disclosed in FIG. 1 of Patent Document 1 has a configuration in which normal gate electrodes and control gate electrodes are alternately formed on the main surface on the emitter electrode side.

[0004] The normal gate electrode is electrically connected to a normal gate pad, and the control gate electrode is electrically connected to a control gate pad, and a gate signal is inputted so that they can be individually controlled.

[0005] Generally, the gate electrode and the control gate electrode have a trench structure in which they are buried in a trench extending from the surface of the semiconductor substrate in the thickness direction, with a gate insulating film provided so as to cover the inner wall of the trench.

[0006] The IGBT has a configuration in which a p-type base layer is provided on an n-type drift layer, an n-type emitter layer is provided on the p-type base layer, and a trench is provided so as to penetrate the emitter layer, which also penetrates the base layer and has its bottom reaching into the drift layer.

[0007] In a double gate IGBT having such a structure, the control gate electrode is cut off before the normal gate electrode during the turn-off operation, thereby reducing the turn-off loss.

[0008] International Publication No. 2013 / 065247

[0009] In the double-gate IGBT disclosed in Patent Document 1, the normal gate electrode and the control gate electrode reach into the drift layer via the gate insulating film, so that the normal gate electrode and the control gate electrode are adjacent to the drift layer.

[0010] Increasing the donor concentration is effective in reducing the on-voltage of an IGBT. However, increasing the donor concentration generates noise when the IGBT is turned on, which means that there is a lower limit to how much the on-voltage of the IGBT can be reduced.

[0011] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that improves the trade-off between noise and on-voltage at turn-on.

[0012] A semiconductor device according to the present disclosure is a semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface opposing each other, and includes: a first semiconductor layer of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first main surface; a third semiconductor layer of the first conductivity type selectively provided on the first main surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second main surface; a first main electrode provided on the first main surface and electrically connected to the second semiconductor layer and the third semiconductor layer; a second main electrode provided on the second main surface and electrically connected to the fourth semiconductor layer; a first trench penetrating a first main surface through the second semiconductor layer to reach the inside of the first semiconductor layer; a second trench penetrating from the first main surface through the second semiconductor layer to reach the inside of the first semiconductor layer; a first control electrode embedded in the first trench with a first gate insulating film interposed therebetween; a second control electrode embedded in the second trench with a second gate insulating film interposed therebetween; and a fifth semiconductor layer of a first conductivity type selectively provided in an upper layer of the first semiconductor layer below the second semiconductor layer so as to be in contact with the second gate insulating film of the second trench, wherein a second impurity concentration of the fifth semiconductor layer is higher than a first impurity concentration of the first semiconductor layer, and the fifth semiconductor layer is provided so as not to be in contact with the first gate insulating film of the first trench.

[0013] According to the semiconductor device of the present disclosure, a fifth semiconductor layer is provided so as not to contact the first gate insulating film of the first trench, and the second impurity concentration of the fifth semiconductor layer is made higher than the first impurity concentration of the first semiconductor layer, thereby making it possible to obtain a semiconductor device with an improved trade-off between noise and on-voltage at turn-on.

[0014] FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a timing chart showing an example of turn-on control. FIG. 3 is a timing chart showing another example of turn-on control. FIG. 4 is a cross-sectional view showing a configuration of a first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 5 is a cross-sectional view showing a configuration of a second modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment of the present disclosure. FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment of the present disclosure. FIG. 8 is a diagram showing a donor concentration profile. FIG. 9 is a diagram showing a donor concentration profile. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present disclosure. FIG. 11 is a cross-sectional view showing a configuration of a modified example of the semiconductor device according to the fourth embodiment of the present disclosure. FIG. 12 is a cross-sectional view showing a configuration of a modified example of the semiconductor device according to the fifth embodiment of the present disclosure. FIG. 13 is a cross-sectional view showing a configuration of a first modified example of the semiconductor device according to the fifth embodiment of the present disclosure. FIG. 14 is a cross-sectional view showing a configuration of a second modified example of the semiconductor device according to the fifth embodiment of the present disclosure.

[0015] <Introduction> In the following description, n-type and p-type indicate the conductivity types of semiconductors, and in this disclosure, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be the p-type and the second conductivity type may be the n-type. － The n-type impurity concentration is lower than that of the n-type impurity concentration. ＋ The p type indicates that the impurity concentration is higher than that of the n type. － The impurity concentration is lower than that of the p-type. ＋ The "type" indicates that the impurity concentration is higher than that of the p-type.

[0016] Furthermore, the drawings are schematic, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0017] In addition, in the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used. However, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and are not related to the directions in which the embodiments are actually implemented.

[0018] 1 is a cross-sectional view showing the configuration of a double-gate IGBT 100 according to a first embodiment of the present disclosure. Although a planar configuration is not shown, the double-gate IGBT can have a configuration in which multiple striped trench gates extend in one direction, similar to a typical trench-gate IGBT.

[0019] As shown in FIG. 1, the double-gate IGBT 100 has an active gate electrode AG (first control electrode), a dummy electrode DE, and a control gate electrode CG (second control electrode) arranged at intervals on a first main surface side, which is the upper surface of a semiconductor substrate.

[0020] The active gate electrode AG is embedded in a trench 7 (first trench) formed in a semiconductor substrate via a gate insulating film 8 (first gate insulating film). The active gate electrode AG is electrically connected to a gate pad (not shown), and a gate signal is supplied to the active gate electrode AG. The gate insulating film 8 is made of, for example, a silicon oxide film (SiO ２ ) can be formed.

[0021] The control gate electrode CG is embedded in a trench 7 (second trench) formed in the semiconductor substrate via a gate insulating film 8 (second gate insulating film). The control gate electrode CG is electrically connected to a control gate pad (not shown), and a control gate signal is supplied to the control gate electrode CG.

[0022] The dummy electrode DE is embedded in a trench 7 (third trench) formed in the semiconductor substrate via a gate insulating film 8 (third gate insulating film). The dummy electrode DE is electrically connected to an emitter electrode 1 (first main electrode) provided on the first major surface, and an emitter voltage is supplied to stabilize the potential of the dummy electrode DE.

[0023] As shown in FIG. 1, the double-gate IGBT 100 is made up of n-type semiconductor substrates. － The n-type drift layer 9 (first semiconductor layer) is included. － The drift layer 9 is a semiconductor layer containing n-type impurities such as arsenic (As) or phosphorus (P), and the concentration of the n-type impurities is 1.0×10 １２ / cm ３ ~1.0 x 10 １６ / cm ３ is.

[0024] n － A p-type base layer 5 (second semiconductor layer) is provided in an upper layer portion on the first main surface side of the drift layer 9. The p-type base layer 5 is a semiconductor layer containing p-type impurities such as boron (B) or aluminum (Al), and the concentration of the p-type impurities is 1.0×10 １２ / cm ３ ~1.0 x 10 １９ / cm ３ The p-type base layer 5 is in contact with the gate insulating film 8 of the active gate electrode AG, the control gate electrode CG, and the dummy electrode DE.

[0025] In the upper layer of the p-type base layer 5, there are provided n-type gate electrodes 10a and 10b in contact with the gate insulating film 8 of the active gate electrode AG and the control gate electrode CG. ＋ A source layer 3 (third semiconductor layer) is provided. ＋ The source layer 3 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 １７ / cm ３ ~1.0 x 10 ２１ / cm ３ is.

[0026] In addition, the upper layer of the p-type base layer 5 is ＋ In contact with the p-type source layer 3 ＋ A contact layer 4 is provided. ＋ The contact layer 4 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 １５ / cm ３ ~1.0 x 10 ２１ / cm３ is.

[0027] The n-type base layer 5 － In the n-type drift layer 9, an n-type gate insulating film 8 of the control gate electrode CG is formed. － An n-type carrier accumulation layer 6c (fifth semiconductor layer) having a higher n-type impurity concentration than the n-type drift layer 9 is provided. The n-type carrier accumulation layer 6c is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the n-type impurity concentration is 1.0×10 １３ / cm ３ ~1.0 x 10 １８ / cm ３ Note that dummy electrodes DE are provided on both sides of the control gate electrode CG, and the n-type carrier accumulation layer 6 c is provided between the control gate electrode CG and the dummy electrodes DE on both sides, so that it is also in contact with the gate insulating film 8 of the dummy electrode DE, but it can also be provided so as not to be in contact with the gate insulating film 8 of the dummy electrode DE.

[0028] Furthermore, on the second main surface side, which is the underside of the semiconductor substrate, a p-type collector layer 11 (fourth semiconductor layer) and an n-type buffer layer 10 are provided in this order from the second main surface, and a collector electrode 12 (second main electrode) is provided on the second main surface opposite the emitter electrode 1.

[0029] The p-type collector layer 11 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 １６ / cm ３ ~1.0 x 10 ２０ / cm ３ The p-type collector layer 11 constitutes the second main surface of the semiconductor substrate.

[0030] The n-type buffer layer 10 contains, as an n-type impurity, for example, phosphorus or protons (H ＋ The n-type buffer layer 10 can be formed by implanting ions of phosphorus and protons, or by implanting both phosphorus and protons. The concentration of the n-type impurity in the n-type buffer layer 10 is 1.0×10 １２ / cm ３ ~1.0 x 10 １８ / cm ３ is.

[0031] The active gate electrode AG, the dummy electrode DE and the control gate electrode CG can be made of polysilicon doped with n-type or p-type impurities.

[0032] The emitter electrode 1 can be made of an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or can be made of a multi-layer metal film formed by electroless or electrolytic plating on an aluminum alloy electrode. The electroless or electrolytic plating can be, for example, a nickel (Ni) plating film.

[0033] The collector electrode 12 can be formed by depositing an aluminum silicon alloy (Al-Si alloy) or titanium (Ti) by PVD (physical vapor deposition) such as sputtering or evaporation, or by laminating multiple metals such as an aluminum silicon alloy, titanium, nickel, and gold. Furthermore, the collector electrode 12 can be configured by forming an additional metal film by electroless plating or electrolytic plating on a metal film formed by PVD.

[0034] An interlayer insulating film 2 is provided on the active gate electrode AG, the dummy electrode DE, and the control gate electrode CG. The interlayer insulating film 2 is, for example, a silicon oxide film (SiO ２ ) can be formed.

[0035] A barrier metal 21 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 2 is not provided, and on the interlayer insulating film 2. The barrier metal 21 may be, for example, a conductor containing titanium (Ti), and may be, for example, titanium nitride or TiSi, which is an alloy of titanium and silicon (Si). ＋ type source layer 3, p ＋ ohmic contact with the contact layer 4 and the dummy electrode DE, ＋ type source layer 3, p ＋ The contact layer 4 and the dummy electrode DE are electrically connected to each other.

[0036] The emitter electrode 1 is provided on the barrier metal 21, but the barrier metal 21 is not provided, and the n ＋ An emitter electrode 1 can also be provided on the type source layer 3. The barrier metal 21 and the emitter electrode 1 can be collectively called the emitter electrode.

[0037] As explained earlier, n － The concentration of n-type impurities in the n-type drift layer 9 is 1.0×10 １２ / cm ３ ~1.0 x 10 １６ / cm ３ The concentration of n-type impurities in the n-type carrier accumulation layer 6c is 1.0×10 １３ / cm ３ ~1.0 x 10 １８ / cm ３ and n － When the donor concentration of the n-type drift layer 9 is Nd (first impurity concentration) and the donor concentration of the n-type carrier accumulation layer 6c is N2 (second impurity concentration), the n-type impurity concentration is set so that Nd<N2.

[0038] The n-type carrier accumulation layer 6c is provided adjacent to the control gate electrode CG but not adjacent to the active gate electrode AG.

[0039] The following describes the operation of the double-gate IGBT 100 having such a configuration. When turning on the double-gate IGBT 100, the gate signal and the control gate signal are controlled so that after the active gate electrode AG starts to turn on, the control gate electrode CG starts to turn on later than the active gate electrode AG.

[0040] <Operation Example 1> Fig. 2 is a timing chart showing an example of turn-on control. In Fig. 2, the horizontal axis represents the passage of time, and the vertical axis represents the gate voltage. Both are in arbitrary units.

[0041] 2, the solid line indicates the change over time in the gate voltage of the active gate electrode AG, and the dashed line indicates the change over time in the gate voltage of the control gate electrode CG. As shown in Fig. 2, when an on signal (first on signal) is input to the active gate electrode AG and the gate voltage starts to increase, an on signal (second on signal) is input to the control gate electrode CG with a delay of time t1 from the active gate electrode AG.

[0042] After the gate voltage of the active gate electrode AG increases and enters the Miller effect period, the gate voltage of the control gate electrode CG also enters the Miller effect period. The Miller effect period is a period in which the voltage remains approximately constant, and corresponds to the period in which the gate-collector capacitance of the double-gate IGBT 100 is charged and discharged. To turn on the double-gate IGBT 100, the gate-collector capacitance must be discharged, and the period for this discharge is the Miller effect period. After the Miller effect period, the gate voltage of the active gate electrode AG increases again, and finally becomes constant at the collector voltage.

[0043] The gate voltage of the control gate electrode CG also increases again after the Miller effect period and becomes constant at the collector voltage. The timing at which the gate voltage of the control gate electrode CG reaches the mirror voltage is slower than the gate voltage of the active gate electrode AG, but the timing at which the Miller effect period ends is almost the same.

[0044] In this way, when an on signal is input to the control gate electrode CG later than the active gate electrode AG, n － The carrier concentration of the type drift layer 9 increases because the number of channels increases as the channels formed by the control gate electrodes CG are added to the channels formed by the active gate electrodes AG.

[0045] By inputting an ON signal to the control gate electrode CG later than the active gate electrode AG, a further effect described below can be obtained. －When the donor concentrations of the n-type drift layer 9 and the n-type carrier accumulation layer 6c are high, negative capacitance of the gate is likely to occur, and noise is likely to occur. Since noise mainly occurs up to the Miller effect period, rather than simultaneously turning on all cells including cells with a high donor concentration in the n-type carrier layer, noise can be suppressed by first turning on cells having active gate electrodes AG with a low donor concentration in the n-type carrier layer and then later turning on cells having control gate electrodes CG with a high donor concentration in the n-type carrier layer.

[0046] Here, the cell having the active gate electrode AG does not have the n-type carrier accumulation layer 6c formed therein. － Since a channel is formed in the n-type drift layer 9, the carrier concentration is low and the noise generated when the cell is turned on is small. － Since the concentration of n-type impurities (donors) in the n-type drift layer 9 is low, it does not contribute to reducing the on-state voltage, that is, the collector-emitter voltage (VCE(sat)).

[0047] On the other hand, in a cell having a control gate electrode CG, an n-type carrier accumulation layer 6c is formed, and a channel is formed in the n-type carrier accumulation layer 6c, so the carrier concentration is high and the noise generated when the cell is turned on is large. However, the donor concentration in the n-type carrier accumulation layer 6c is high, so the on-voltage can be reduced.

[0048] <Operation Example 2> Fig. 3 is a timing chart showing another example of turn-on control, in which the horizontal and vertical axes are the same as those in Fig. 2 .

[0049] As shown in FIG. 3, when an ON signal is input to the active gate electrode AG, the gate voltage starts to increase, and after the Miller effect period has begun, an ON signal is input to the control gate electrode CG with a delay of time t2.

[0050] The gate voltage of the active gate electrode AG increases again after a Miller effect period and finally becomes constant at the collector voltage. The gate voltage of the control gate electrode CG also increases again after a Miller effect period and becomes constant at the collector voltage. The timing at which the gate voltage of the control gate electrode CG reaches the mirror voltage is slower than the gate voltage of the active gate electrode AG, but the timing at which the Miller effect period ends is approximately the same.

[0051] An on signal is input to the control gate electrode CG after the gate voltage of the active gate electrode AG has reached the mirror voltage. Since noise mainly occurs up until the mirror effect period, the generation of noise can be suppressed by turning on only cells having the active gate electrode AG, i.e., cells that generate little noise when turned on, until the mirror effect period, and the on voltage can be reduced by turning on cells having the control gate electrode CG, i.e., cells with a low on-voltage, after the gate voltage of the active gate electrode AG has entered the mirror effect period.

[0052] <Operation Example 3> Fig. 4 is a timing chart showing another example of turn-on control, in which the horizontal and vertical axes are the same as those in Fig. 2 .

[0053] As shown in FIG. 4, when an ON signal is input to the active gate electrode AG, the gate voltage starts to increase, and after the Miller effect period has begun, an ON signal is input to the control gate electrode CG with a delay of time t3.

[0054] The gate voltage of the active gate electrode AG increases again after a Miller effect period and finally becomes constant at the gate-on voltage. When an on signal is input to the control gate electrode CG, the gate voltage of the control gate electrode CG increases without going through the Miller effect period and becomes constant at the gate-on voltage.

[0055] Since noise mainly occurs up until the Miller effect period, noise generation can be suppressed by turning on only cells having an active gate electrode AG, i.e., cells that generate little noise when turned on, until the Miller effect period ends, and the on-voltage can be reduced by turning on cells having a control gate electrode CG, i.e., cells with a low on-voltage, after the gate voltage of the active gate electrode AG has passed the Miller effect period.

[0056] As described above, in the double-gate IGBT 100, by providing a time difference between the drive timings of the active gate electrode AG and the control gate electrode CG, it is possible to take advantage of the respective characteristics, reduce noise while also reducing the on-voltage, and improve the trade-off between noise and on-voltage when the IGBT is turned on. While the above description has shown an example in which a time difference is provided between the drive timings of the active gate electrode AG and the control gate electrode CG in the turn-on control of the IGBT, a time difference can also be provided in the turn-off control, or a time difference can be provided in both the turn-on control and the turn-off control. Here, the order in which the active gate electrode AG and the control gate electrode CG are turned off in the turn-off control is not particularly limited; that is, either can be turned off first. When a time difference is provided in both the turn-on control and the turn-off control, the time difference in the turn-on control (the delay time of the control gate electrode CG) is set shorter than the time difference in the turn-off control (the delay time of the active gate electrode AG or the control gate electrode CG). This allows the off timing of the electrode that is turned off later in the turn-off to be relatively delayed, allowing for a high degree of freedom in the design of the off timing.

[0057] In addition, n － When the donor concentration of the n-type drift layer 9 is Nd and the donor concentration of the n-type carrier accumulation layer 6c is N2, the above-mentioned effect can be obtained by setting the relationship between the donor concentration N0 at which noise occurs as Nd<N0≦N2. １３ / cm ３ <1 x 10 １７ / cm ３≦3×10 １７ / cm ３ Examples include:

[0058] The time difference between the drive timing of the active gate electrode AG and the control gate electrode CG is set to about 0.1 μsec to 10 μsec in a device with a breakdown voltage of, for example, 1200 V.

[0059] <Modification 1> The double-gate IGBT 100 described above has a configuration in which a dummy electrode DE is provided between the active gate electrode AG and the control gate electrode CG, and this arrangement makes it possible to adjust the gate capacitance of the IGBT and improve the degree of freedom in designing the IGBT, but the number of dummy electrodes DE is not limited to 1. Furthermore, even if a configuration does not have a dummy electrode DE, the effect of improving the trade-off between noise when the IGBT is turned on and the on-voltage remains the same.

[0060] Fig. 5 is a cross-sectional view showing the configuration of a double-gate IGBT 101 which is a first modification of the first embodiment. In Fig. 5, the same components as those in the double-gate IGBT 100 shown in Fig. 1 are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0061] As shown in FIG. 5, in the double-gate IGBT 101, an active gate electrode AG and a control gate electrode CG are provided at intervals on the first main surface side, which is the upper surface of a semiconductor substrate, and the n-type gate electrodes AG and CG adjacent to each other are ＋ The upper layer of the p-type base layer 5 between the p-type source layers 3 is p ＋ A contact layer 4 is provided, and an n ＋ The source layers 3 are electrically connected to each other.

[0062] The n-type carrier accumulation layer 6c is provided adjacent to the control gate electrode CG, but is not provided adjacent to the active gate electrode AG.

[0063] The dummy electrodes DE are provided to adjust the capacitance of the gate electrodes, and the number of dummy electrodes DE is reduced when the capacitance is to be reduced, and the number of dummy electrodes DE is increased when the capacitance is to be increased. Therefore, between the double-gate IGBT 100 shown in Figure 1 and the double-gate IGBT 101 shown in Figure 5, the double-gate IGBT 101 has a smaller capacitance of the active gate electrode AG and the control gate electrode CG. Reducing the capacitance can improve the switching response of the IGBT and reduce switching loss when the cell pitch is constant, for example.

[0064] <Modification 2> In the double-gate IGBT 100 shown in FIG. 1, the control gate electrode CG is arranged so as to be sandwiched between the dummy electrodes DE, but the present invention is not limited to this arrangement.

[0065] Fig. 6 is a cross-sectional view showing the configuration of a double-gate IGBT 102 which is a second modification of the first embodiment. In Fig. 6, the same components as those in the double-gate IGBT 100 shown in Fig. 1 are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0066] 6, in the double-gate IGBT 102, a control gate electrode CG is arranged next to an active gate electrode AG, and two dummy electrodes DE are arranged on the opposite side of the active gate electrode AG. Here, the dummy electrode DE is adjacent to the control gate electrode CG, but FIG. 6 shows a unit cell, and the active gate electrode AG is adjacent to the dummy electrode DE (not shown).

[0067] The n-type carrier accumulation layer 6c is provided so as to be in contact with the gate insulating film 8 of the control gate electrode CG, but the n-type carrier accumulation layer 6c is provided so as not to be in contact with the gate insulating film 8 of the active gate electrode AG.

[0068] Even with this configuration, the effect of improving the trade-off between noise when the IGBT is turned on and the on-voltage is the same as that of the double-gate IGBT 100. Furthermore, by arranging the dummy electrodes DE adjacent to each other in this manner and not adjacent to both sides of the active gate electrode AG, the gate capacitance can be reduced, the response in switching of the IGBT can be improved, and switching loss can be reduced.

[0069] It goes without saying that the active gate electrodes AG and the control gate electrodes CG can be arranged alternately and repeatedly without providing the dummy electrodes DE.

[0070] 7 is a cross-sectional view showing the configuration of a double-gate IGBT 200 according to a second embodiment of the present disclosure. In Fig. 7, the same components as those in the double-gate IGBT 100 shown in Fig. 1 are denoted by the same reference numerals, and redundant description will be omitted.

[0071] As shown in FIG. 7, the double-gate IGBT 200 has an n-type base layer 5 below the p-type base layer 5. － In the n-type drift layer 9, an n-type － An n-type carrier accumulation layer 6c having a higher concentration of n-type impurities than the n-type drift layer 9 is provided, and an n-type carrier accumulation layer 6c is provided so as to contact the gate insulating film 8 of the active gate electrode AG. － An n-type carrier accumulation layer 6 a (sixth semiconductor layer) having a higher concentration of n-type impurities than the n-type drift layer 9 is provided.

[0072] The n-type carrier accumulation layer 6a is a semi-solid layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 １３ / cm ３ ~1.0 x 10 １８ / cm ３ and is set lower than the concentration of n-type impurities in the n-type carrier accumulation layer 6a.

[0073] That is, as explained above, n － The concentration of n-type impurities in the n-type drift layer 9 is 1.0×10 １２ / cm ３ ~1.0 x 10 １６ / cm３ The concentration of n-type impurities in the n-type carrier accumulation layer 6c is 1.0×10 １３ / cm ３ ~1.0 x 10 １９ / cm ３ and n － Assuming that the donor concentration of n-type drift layer 9 is Nd, the donor concentration of n-type carrier accumulation layer 6a is N1 (third impurity concentration), and the donor concentration of n-type carrier accumulation layer 6c is N2, the n-type impurity concentrations are set so that Nd<N1<N2. １３ / cm ３ <1 x 10 １７ / cm ３ <3 x 10 １７ / cm ３ Examples include:

[0074] The operation of the double-gate IGBT 200 having such a configuration is similar to the operation of the double-gate IGBT 100 described using Figures 2 to 4, and when turning on the double-gate IGBT 200, the gate signal and the control gate signal are controlled so that after the active gate electrode AG starts its turn-on operation, the control gate electrode CG starts its turn-on operation later than the active gate electrode AG.

[0075] Therefore, in the double-gate IGBT 200, by providing a time difference between the drive timings of the active gate electrode AG and the control gate electrode CG, it is possible to take advantage of the respective features of the active gate electrode AG and the control gate electrode CG, reduce the on-voltage while reducing noise, and improve the trade-off between the noise and on-voltage when the IGBT is turned on.

[0076] In addition, by providing the n-type carrier accumulation layer 6a, a channel is formed in the n-type carrier accumulation layer 6a in a cell having an active gate electrode AG, and the carrier concentration increases, and the noise generated when the cell is turned on increases. However, if the concentration of n-type impurities (donors) in the n-type carrier accumulation layer 6a is n －Since the gate electrode 100 is higher than the gate electrode 100 of the first embodiment, the on-state voltage, i.e., the collector-emitter voltage (VCE(sat)), can be reduced. Therefore, the on-state voltage can be reduced by about 15% compared to the double-gate IGBT 100 of the first embodiment.

[0077] Here, when the donor concentration of the n-type carrier accumulation layer 6a is N1 and the donor concentration of the n-type carrier accumulation layer 6c is N2, the above-mentioned effect can be obtained by setting the relationship between the donor concentration N0 at which noise occurs as N1<N0≦N2. １６ / cm ３ <1 x 10 １７ / cm ３ ≦3×10 １７ / cm ３ Examples include:

[0078] The time difference between the drive timing of the active gate electrode AG and the control gate electrode CG is set to about 0.1 μsec to 10 μsec in a device with a breakdown voltage of, for example, 1200 V.

[0079] The double-gate IGBT 200 described above has a configuration including a dummy electrode DE in addition to the active gate electrode AG and the control gate electrode CG. However, even if the dummy electrode DE is not included, the effect of improving the trade-off between noise and on-voltage when the IGBT is turned on remains the same. For example, a configuration without a dummy electrode DE, like the double-gate IGBT 101 shown in FIG. 5, may be adopted. Note that, as long as the n-type carrier accumulation layer 6c is not adjacent to the active gate electrode AG, the n-type carrier accumulation layer 6a and the n-type carrier accumulation layer 6c may or may not be in contact with each other.

[0080] In addition, in the double-gate IGBT 200 shown in FIG. 7, the control gate electrode CG is arranged so as to be sandwiched between the dummy electrodes DE, but this arrangement is not limited to this, and it is also possible to use an arrangement such as that of the double-gate IGBT 102 shown in FIG. 6, for example.

[0081] 8 is a cross-sectional view showing the configuration of a double-gate IGBT 300 according to a third embodiment of the present disclosure. In Fig. 8, the same components as those in the double-gate IGBT 100 shown in Fig. 1 are denoted by the same reference numerals, and redundant description will be omitted.

[0082] As shown in FIG. 8, the double-gate IGBT 300 is provided with an n-type carrier accumulation layer 6a and an n-type carrier accumulation layer 6c, similar to the double-gate IGBT 200 shown in FIG. － Assuming that the donor concentration of n-type drift layer 9 is Nd, the donor concentration of n-type carrier accumulation layer 6a is N1, and the donor concentration of n-type carrier accumulation layer 6c is N2, the n-type impurity concentrations are set so that Nd<N1<N2.

[0083] The difference from the double-gate IGBT 200 is that, when the depth at which the donor concentration in the n-type carrier accumulation layer 6 a reaches its maximum value (peak) is defined as p1 and the depth at which the donor concentration in the n-type carrier accumulation layer 6 c reaches its maximum value (peak) is defined as p2, the donor injection depth is different so that p2<p1.

[0084] Therefore, as shown in FIG. 8, the thickness of the n-type carrier accumulation layer 6c is thinner than the thickness of the n-type carrier accumulation layer 6a.

[0085] 9 shows donor concentration profiles of the n-type carrier accumulation layer 6a and the n-type carrier accumulation layer 6c, with the horizontal axis representing depth and the vertical axis representing donor concentration. Both are in arbitrary units. As shown in FIG. 9, the peak depth p1 of the profile PF1 of the n-type carrier accumulation layer 6a is deeper than the peak depth p2 of the profile PF2 of the n-type carrier accumulation layer 6c. Meanwhile, the peak of the profile PF2 of the n-type carrier accumulation layer 6c is higher than the peak of the profile PF1 of the n-type carrier accumulation layer 6a, and the profile width is narrower than the profile width of the n-type carrier accumulation layer 6a. By using such a profile, the thickness of the n-type carrier accumulation layer 6c becomes thinner than that of the n-type carrier accumulation layer 6a.

[0086] In this way, by changing the donor injection depths of the n-type carrier accumulation layers 6 a and 6 c, the degree of freedom in designing the n-type carrier accumulation layers 6 a and 6 c can be increased. In addition, the donor injection depths of the n-type carrier accumulation layers 6 a and 6 c can be reversed.

[0087] The operation of the double-gate IGBT 300 having such a configuration is similar to the operation of the double-gate IGBT 100 described using Figures 2 to 4, and when turning on the double-gate IGBT 300, the gate signal and the control gate signal are controlled so that after the active gate electrode AG starts its turn-on operation, the control gate electrode CG starts its turn-on operation later than the active gate electrode AG.

[0088] Therefore, in the double-gate IGBT 300, by providing a time difference between the drive timings of the active gate electrode AG and the control gate electrode CG, it is possible to take advantage of the respective features of the active gate electrode AG and the control gate electrode CG, reduce the on-voltage while reducing noise, and improve the trade-off between the noise and on-voltage when the IGBT is turned on.

[0089] Incidentally, by providing the n-type carrier accumulation layer 6a, the effect of being able to reduce the on-voltage by about 15% compared to the double-gate IGBT 100 of the first embodiment is the same as in the double-gate IGBT 200 of the second embodiment.

[0090] Here, when the n-type carrier accumulation layer 6a and the n-type carrier accumulation layer 6c have the same thickness as in the double-gate IGBT 200 of the second embodiment, the donor injection depths of the n-type carrier accumulation layer 6a and the n-type carrier accumulation layer 6c are made the same. Figure 10 shows the donor concentration profiles of the n-type carrier accumulation layer 6a and the n-type carrier accumulation layer 6c of the double-gate IGBT 200. The peak depth p1 of the profile PF1 of the n-type carrier accumulation layer 6a is the same as the peak depth of the profile PF2 of the n-type carrier accumulation layer 6c, and the profile widths are also the same. By using such profiles, the thickness of the n-type carrier accumulation layer 6c can be made the same as the thickness of the n-type carrier accumulation layer 6a.

[0091] The double-gate IGBT 300 described above has a configuration including a dummy electrode DE in addition to the active gate electrode AG and the control gate electrode CG. However, even if the dummy electrode DE is not included, the effect of improving the trade-off between noise and on-voltage when the IGBT is turned on remains the same. For example, a configuration without a dummy electrode DE, like the double-gate IGBT 101 shown in FIG. 5, may be adopted. Note that, as long as the n-type carrier accumulation layer 6c is not adjacent to the active gate electrode AG, the n-type carrier accumulation layer 6a and the n-type carrier accumulation layer 6c may or may not be in contact with each other.

[0092] Furthermore, in the double-gate IGBT 300 shown in FIG. 8, the control gate electrode CG is arranged so as to be sandwiched between the dummy electrodes DE, but this arrangement is not limited to this, and it is also possible to use an arrangement such as that of the double-gate IGBT 102 shown in FIG. 6, for example.

[0093] 11 is a cross-sectional view showing the configuration of a double-gate IGBT 400 according to a fourth embodiment of the present disclosure. In Fig. 11, the same components as those in the double-gate IGBT 100 shown in Fig. 1 are denoted by the same reference numerals, and redundant description will be omitted.

[0094] As shown in FIG. 11, the double-gate IGBT 400 is provided with an n-type carrier accumulation layer 6a and an n-type carrier accumulation layer 6c, similar to the double-gate IGBT 200 shown in FIG. － Assuming that the donor concentration of n-type drift layer 9 is Nd, the donor concentration of n-type carrier accumulation layer 6a is N1, and the donor concentration of n-type carrier accumulation layer 6c is N2, the n-type impurity concentrations are set so that Nd<N1<N2.

[0095] The difference from the double-gate IGBT 200 is that the thickness from the bottom to the top of the n-type carrier accumulation layer 6c is greater than the thickness from the bottom to the top of the n-type carrier accumulation layer 6a. As a result, the distance d2 (first distance) from the outermost surface of the p-type base layer 5c above the n-type carrier accumulation layer 6c to the upper end of the n-type carrier accumulation layer 6c is shorter than the distance d1 (second distance) from the outermost surface of the p-type base layer 5a above the n-type carrier accumulation layer 6a to the upper end of the n-type carrier accumulation layer 6a. In other words, the relationship d1 > d2 holds. This means that the n-type carrier accumulation layer 6c is formed wider, closer to the first main surface, which is the upper surface of the semiconductor substrate. The distances d1 and d2 can be set to 1 μm and 0.8 μm, respectively.

[0096] In this way, by forming the n-type carrier accumulation layer 6c wider and closer to the top surface of the semiconductor substrate, the manufacturing process of the double-gate IGBT 400 can be simplified. That is, after forming the p-type base layers 5a and 5c under the same ion implantation conditions, the n-type carrier accumulation layers 6a and 6c are formed with the same ion implantation energy, but the dose of n-type impurities in the n-type carrier accumulation layer 6c must be higher than the dose of n-type impurities in the n-type carrier accumulation layer 6a. This is to make the donor concentrations of both layers N1 < N2. As a result, the n-type carrier accumulation layer 6c is formed wider and closer to the top surface of the semiconductor substrate, resulting in the relationship d1 > d2. In this way, the p-type base layers 5a and 5c can be formed under the same ion implantation conditions, simplifying the manufacturing process of the double-gate IGBT 400.

[0097] 11 shows a configuration having an n-type carrier accumulation layer 6a, but as shown in a modified example in FIG. 12, the n-type carrier accumulation layer 6a is not provided, and this portion is n － In this case, the distance d1 is n － The n-type base layer 5a is formed on the n-type drift layer 9. － This is the distance to the top end of the mold drift layer 9.

[0098] The operation of the double-gate IGBT 400 having such a configuration is similar to the operation of the double-gate IGBT 100 described using Figures 2 to 4, and when turning on the double-gate IGBT 400, the gate signal and the control gate signal are controlled so that after the active gate electrode AG starts its turn-on operation, the control gate electrode CG starts its turn-on operation later than the active gate electrode AG.

[0099] Therefore, in the double-gate IGBT 400, by providing a time difference between the drive timings of the active gate electrode AG and the control gate electrode CG, it is possible to take advantage of the respective features of the active gate electrode AG and the control gate electrode CG, reduce the on-voltage while reducing noise, and improve the trade-off between the noise and on-voltage when the IGBT is turned on.

[0100] Incidentally, by providing the n-type carrier accumulation layer 6a, the effect of being able to reduce the on-voltage by about 15% compared to the double-gate IGBT 100 of the first embodiment is the same as in the double-gate IGBT 200 of the second embodiment.

[0101] The double-gate IGBT 400 described above has a configuration including a dummy electrode DE in addition to the active gate electrode AG and the control gate electrode CG. However, even if the dummy electrode DE is not included, the effect of improving the trade-off between noise and on-voltage when the IGBT is turned on remains the same. For example, a configuration without a dummy electrode DE, like the double-gate IGBT 101 shown in FIG. 5, may be adopted. Note that, as long as the n-type carrier accumulation layer 6c is not adjacent to the active gate electrode AG, it does not matter whether the n-type carrier accumulation layer 6a and the n-type carrier accumulation layer 6c are in contact with each other.

[0102] In addition, in the double-gate IGBT 400 shown in FIG. 11, the control gate electrode CG is arranged so as to be sandwiched between the dummy electrodes DE, but this arrangement is not limited to this, and it is also possible to use an arrangement such as that of the double-gate IGBT 102 shown in FIG. 6, for example.

[0103] 13 is a cross-sectional view showing the configuration of a double-gate IGBT 500 according to a fifth embodiment of the present disclosure. In FIG. 13, the same components as those in the double-gate IGBT 100 shown in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

[0104] As shown in FIG. 13, the double-gate IGBT 500 is provided with an n-type carrier accumulation layer 6a and an n-type carrier accumulation layer 6c, similar to the double-gate IGBT 200 shown in FIG. － Assuming that the donor concentration of n-type drift layer 9 is Nd, the donor concentration of n-type carrier accumulation layer 6a is N1, and the donor concentration of n-type carrier accumulation layer 6c is N2, the n-type impurity concentrations are set so that Nd<N1<N2.

[0105] The difference from the double-gate IGBT 200 is that the n-type carrier accumulation layer 6c － The seventh semiconductor layer 13c (p-type impurity layer) is provided in the upper portion of the drift layer 9. The p-type impurity layer 13c contains, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 １２ / cm ３ ~1.0 x 10 １８ / cm ３ is.

[0106] Providing the p-type impurity layer 13c can suppress a decrease in the breakdown voltage of the double-gate IGBT 500. That is, the breakdown voltage of the double-gate IGBT 500 is determined by the electric field at the bottom of the trench, but by providing the p-type impurity layer 13c in the vicinity of the bottom of the trench 7 having the control gate electrode CG, the electric field at the bottom of the trench 7 is alleviated, and a decrease in the breakdown voltage can be suppressed.

[0107] As shown in Modification 1 in FIG. 14, the p-type impurity layer 13c can be provided under the n-type carrier accumulation layer 6a. In this case, it is not necessary to pattern the p-type impurity layer 13c, which makes manufacturing easier.

[0108] 13 shows a configuration having an n-type carrier accumulation layer 6a, but as shown in Modification 2 in FIG. 15, the n-type carrier accumulation layer 6a is not provided, and this portion is n －Alternatively, the p-type impurity layer 13c may be a p-type drift layer 9. In this case, too, it is not necessary to pattern the p-type impurity layer 13c, which facilitates manufacturing.

[0109] The operation of the double-gate IGBT 500 having such a configuration is similar to the operation of the double-gate IGBT 100 described using Figures 2 to 4, and when turning on the double-gate IGBT 500, the gate signal and the control gate signal are controlled so that after the active gate electrode AG starts its turn-on operation, the control gate electrode CG starts its turn-on operation later than the active gate electrode AG.

[0110] Therefore, in the double-gate IGBT 500, by providing a time difference between the drive timings of the active gate electrode AG and the control gate electrode CG, it is possible to take advantage of the respective features of the active gate electrode AG and the control gate electrode CG, reduce the on-voltage while reducing noise, and improve the trade-off between the noise and on-voltage when the IGBT is turned on.

[0111] Incidentally, by providing the n-type carrier accumulation layer 6a, the effect of being able to reduce the on-voltage by about 15% compared to the double-gate IGBT 100 of the first embodiment is the same as in the double-gate IGBT 200 of the second embodiment.

[0112] The double-gate IGBT 500 described above has a configuration including a dummy electrode DE in addition to the active gate electrode AG and the control gate electrode CG. However, even if the dummy electrode DE is not included, the effect of improving the trade-off between noise and on-voltage when the IGBT is turned on remains the same. For example, a configuration without a dummy electrode DE, like the double-gate IGBT 101 shown in FIG. 5, may be used. Note that, as long as the n-type carrier accumulation layer 6c is not adjacent to the active gate electrode AG, the n-type carrier accumulation layer 6a and the n-type carrier accumulation layer 6c may or may not be in contact with each other.

[0113] In addition, in the double-gate IGBT 500 shown in FIG. 13, the control gate electrode CG is arranged so as to be sandwiched between the dummy electrodes DE, but this arrangement is not limited to this, and it may also be arranged, for example, as in the double-gate IGBT 102 shown in FIG. 6.

[0114] Although the present disclosure has been described in detail, the above description is illustrative in all respects and does not limit the present disclosure to the above. It is understood that countless variations not illustrated can be envisioned without departing from the scope of the present disclosure.

[0115] It should be noted that, within the scope of the present disclosure, the embodiments can be freely combined, and the embodiments can be modified or omitted as appropriate.

Claims

1. A semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface opposed to each other, a first semiconductor layer of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first major surface; a third semiconductor layer of a first conductivity type selectively provided on the first principal surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second major surface; a first main electrode provided on the first main surface and electrically connected to the second semiconductor layer and the third semiconductor layer; a second main electrode provided on the second main surface and electrically connected to the fourth semiconductor layer; a first trench extending from the first main surface through the second semiconductor layer to reach the inside of the first semiconductor layer; a second trench extending from the first principal surface through the second semiconductor layer to reach the interior of the first semiconductor layer; a first control electrode embedded in the first trench via a first gate insulating film; a second control electrode embedded in the second trench with a second gate insulating film interposed therebetween; a fifth semiconductor layer of a first conductivity type selectively provided in an upper layer portion of the first semiconductor layer below the second semiconductor layer so as to be in contact with the second gate insulating film of the second trench, a second impurity concentration of the fifth semiconductor layer is higher than a first impurity concentration of the first semiconductor layer; the fifth semiconductor layer is provided so as not to be in contact with the first gate insulating film of the first trench; The semiconductor device, wherein the third semiconductor layer is provided so as to be in contact with the first gate insulating film in the first trench.

2. A semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface facing each other, a first semiconductor layer of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first major surface; a third semiconductor layer of a first conductivity type selectively provided on the first principal surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second major surface; a first main electrode provided on the first main surface and electrically connected to the second semiconductor layer and the third semiconductor layer; a second main electrode provided on the second main surface and electrically connected to the fourth semiconductor layer; a first trench extending from the first main surface through the second semiconductor layer to reach the inside of the first semiconductor layer; a second trench extending from the first principal surface through the second semiconductor layer to reach the interior of the first semiconductor layer; a first control electrode embedded in the first trench via a first gate insulating film; a second control electrode embedded in the second trench with a second gate insulating film interposed therebetween; a fifth semiconductor layer of a first conductivity type selectively provided in an upper layer portion of the first semiconductor layer below the second semiconductor layer so as to be in contact with the second gate insulating film of the second trench, a second impurity concentration of the fifth semiconductor layer is higher than a first impurity concentration of the first semiconductor layer; the fifth semiconductor layer is provided so as not to be in contact with the first gate insulating film of the first trench; a sixth semiconductor layer of a first conductivity type selectively provided in the upper layer portion of the first semiconductor layer below the second semiconductor layer so as to be in contact with the first gate insulating film of the first trench; A semiconductor device, wherein a third impurity concentration of the sixth semiconductor layer is higher than the first impurity concentration and lower than the second impurity concentration.

3. a first depth at which the second impurity concentration of the fifth semiconductor layer is at a maximum value; 3. The semiconductor device according to claim 2, wherein the depth at which the third impurity concentration of the sixth semiconductor layer reaches a maximum value is different from the second depth at which the third impurity concentration of the sixth semiconductor layer reaches a maximum value.

4. a first distance from an outermost surface of the second semiconductor layer to an upper end of the fifth semiconductor layer, 3. The semiconductor device according to claim 2, wherein the distance of said sixth semiconductor layer is shorter than a second distance from said outermost surface of said second semiconductor layer to an upper end of said sixth semiconductor layer.

5. A semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface facing each other, a first semiconductor layer of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first major surface; a third semiconductor layer of a first conductivity type selectively provided on the first principal surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second major surface; a first main electrode provided on the first main surface and electrically connected to the second semiconductor layer and the third semiconductor layer; a second main electrode provided on the second main surface and electrically connected to the fourth semiconductor layer; a first trench extending from the first main surface through the second semiconductor layer to reach the inside of the first semiconductor layer; a second trench extending from the first principal surface through the second semiconductor layer to reach the interior of the first semiconductor layer; a first control electrode embedded in the first trench via a first gate insulating film; a second control electrode embedded in the second trench with a second gate insulating film interposed therebetween; a fifth semiconductor layer of a first conductivity type selectively provided in an upper layer portion of the first semiconductor layer below the second semiconductor layer so as to be in contact with the second gate insulating film of the second trench, a second impurity concentration of the fifth semiconductor layer is higher than a first impurity concentration of the first semiconductor layer; the fifth semiconductor layer is provided so as not to be in contact with the first gate insulating film of the first trench; a first distance from an outermost surface of the second semiconductor layer to an upper end of the fifth semiconductor layer, a second distance from the outermost surface of the second semiconductor layer to the upper end of the first semiconductor layer in the region where the first trench is provided;

6. 3. The semiconductor device according to claim 2, further comprising a seventh semiconductor layer of the second conductivity type provided in said first semiconductor layer below said fifth semiconductor layer.

7. The seventh semiconductor layer is 7. The semiconductor device according to claim 6, wherein the sixth semiconductor layer is also provided inside the first semiconductor layer below the sixth semiconductor layer.

8. A semiconductor device formed on a semiconductor substrate having a first main surface and a second main surface facing each other, a first semiconductor layer of a first conductivity type provided between the first main surface and the second main surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first major surface; a third semiconductor layer of a first conductivity type selectively provided on the first principal surface side of the second semiconductor layer; a fourth semiconductor layer of a second conductivity type provided between the first semiconductor layer and the second major surface; a first main electrode provided on the first main surface and electrically connected to the second semiconductor layer and the third semiconductor layer; a second main electrode provided on the second main surface and electrically connected to the fourth semiconductor layer; a first trench extending from the first main surface through the second semiconductor layer to reach the inside of the first semiconductor layer; a second trench extending from the first principal surface through the second semiconductor layer to reach the interior of the first semiconductor layer; a first control electrode embedded in the first trench via a first gate insulating film; a second control electrode embedded in the second trench with a second gate insulating film interposed therebetween; a fifth semiconductor layer of a first conductivity type selectively provided in an upper layer portion of the first semiconductor layer below the second semiconductor layer so as to be in contact with the second gate insulating film of the second trench, a second impurity concentration of the fifth semiconductor layer is higher than a first impurity concentration of the first semiconductor layer; the fifth semiconductor layer is provided so as not to be in contact with the first gate insulating film of the first trench; The semiconductor device further includes a seventh semiconductor layer of a second conductivity type provided in the interior of the first semiconductor layer below the fifth semiconductor layer and in the interior of the first semiconductor layer in a region where the first trench is provided.

9. a third trench extending from the first principal surface through the second semiconductor layer to reach the interior of the first semiconductor layer; 9. The semiconductor device according to claim 1, further comprising: a dummy electrode that is not connected to the first control electrode and the second control electrode and is embedded in the third trench with a third gate insulating film interposed therebetween.

10. The dummy electrode is 10. The semiconductor device according to claim 9, electrically connected to said first main electrode.

11. The third trench comprises: The semiconductor device according to claim 9 , wherein the second trench is provided between the first trench and the second trench.

12. The third trench is The semiconductor device according to claim 10 , wherein the second trench is formed between the first trench and the second trench.

13. A method for controlling the semiconductor device according to any one of claims 1, 2, 5 and 8, comprising: At least one of turning on and turning off the semiconductor device, A method for controlling a semiconductor device, comprising: inputting a first ON signal to the first control electrode, and then controlling so that a second ON signal is input to the second control electrode.

14. 14. The method for controlling a semiconductor device according to claim 13, wherein the method for controlling the semiconductor device is performed at the time of turning on the semiconductor device.

15. 15. The method for controlling a semiconductor device according to claim 14, wherein the control method is also performed at the turn-off of the semiconductor device, and the delay time of the second control electrode at the turn-on is set shorter than the delay time at the turn-off.