Semiconductor integrated circuit device

Abstract

A power tap array (CRT) including a power tap (TAP) is provided adjacent to a plurality of cell rows (CR). A cell (C1) comprises: transistors overlapping in a plan view; VDD power supply wiring (21) formed in a BM0 layer; and VSS power supply wiring (11) formed in an M0 layer. The power tap (TAP) comprises: VSS power supply wiring (22) formed in the BM0 layer; VSS power supply wiring (12) formed in the M0 layer; and a connection structure for connecting between the VSS power supply wiring (12, 22). The size of the cell (C1) in an X-direction is larger than the arrangement pitch of VSS power supply wiring (24) formed in a BM1 layer.