Method for manufacturing wiring board, method for manufacturing semiconductor device, wiring board, and semiconductor device

Abstract

This method for manufacturing a wiring board comprises: a step for forming a first insulating layer on a support substrate; a step for forming a resist layer on the first insulating layer; a step for forming a plurality of openings including a first opening and a second opening for a wiring electrode and a third opening for a dummy electrode in the resist layer; a step for forming a first wiring electrode and a second wiring electrode in the first opening and the second opening, respectively; a step for forming a first dummy electrode in the third opening; a step for removing the resist layer after forming the first wiring electrode, the second wiring electrode, and the first dummy electrode; and a step for forming a second insulating layer on the first insulating layer so as to cover at least the first dummy electrode. In this manufacturing method, the surfaces of the first wiring electrode and the second wiring electrode are exposed from the second insulating layer, and at least a part of the first dummy electrode is positioned between the first wiring electrode and the second wiring electrode.

Description

Method for manufacturing wiring board, method for manufacturing semiconductor device, wiring board, and semiconductor device

[0001] The present disclosure relates to a method for manufacturing a wiring board, a method for manufacturing a semiconductor device, a wiring board, and a semiconductor device.

[0002] To increase the density and performance of semiconductor packages, a packaging configuration has been proposed in which semiconductor elements (hereinafter sometimes referred to as "chips") with different performance characteristics are mixed in a single package. From a cost perspective, high-density interconnect technology between chips is becoming increasingly important (see, for example, Patent Document 1). Furthermore, a connection method known as package-on-package is widely adopted in smartphones and tablet devices. Package-on-package is a method of connecting different packages on one package by flip-chip mounting (see, for example, Non-Patent Documents 1 and 2). To achieve even higher density packaging, packaging technologies have been proposed, including packaging technology using organic substrates with high-density wiring (organic interposers), fan-out packaging technology with through-mold vias (TMVs) (FO-WLP), packaging technology using silicon or glass interposers, packaging technology using through-silicon vias (TSVs), and packaging technology using chips embedded in a substrate for inter-chip transmission. In particular, when semiconductor chips are mounted in parallel with each other in organic interposers and FO-WLP, a fine wiring layer is required to ensure high-density electrical continuity (see Patent Document 2).

[0003] In addition to the trend toward finer pitches, semiconductor devices have recently been used in harsh environments such as in automobiles. Therefore, there is a growing demand for high reliability, such as improved heat resistance and crack resistance, for permanent coatings such as solder resist used in semiconductor devices. When a semiconductor device mounted on a printed wiring board is subjected to temperature changes, differences in the thermal expansion coefficients of the various materials can cause cracks to form at the joints with the board's external connection terminals, resulting in disconnections (see Patent Document 3).

[0004] JP 2011-029287 A U.S. Patent Application Publication No. 2011 / 0221071 JP 2017-157666 A

[0005] Application of Through Mold Via (TMV) as PoP Base Package, Electronic Components and Technology Conference (ECTC), 2008Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology, ECTC, 2012

[0006] In various conventional semiconductor devices, sudden or continuous temperature changes can cause cracks in the resin composition that constitutes the semiconductor device. When such cracks occur, the cracks can cause the wiring in the semiconductor device to break. Therefore, it is desirable to prevent the wiring from breaking due to cracks.

[0007] An object of the present disclosure is to provide a method for manufacturing a wiring board, a method for manufacturing a semiconductor device, a wiring board, and a semiconductor device that can prevent breakage of wiring due to cracks.

[0008] [1] As one aspect, the present disclosure provides a method for manufacturing a wiring substrate. The method for manufacturing a wiring substrate includes the steps of forming a first insulating layer on a support substrate, forming a resist layer on the first insulating layer, forming a plurality of openings in the resist layer, including first and second openings for wiring electrodes and a third opening for a dummy electrode, forming first wiring electrodes and second wiring electrodes in the first and second openings, respectively, and forming first dummy electrodes in the third openings, removing the resist layer after forming the first wiring electrodes, the second wiring electrodes, and the first dummy electrodes, and forming a second insulating layer on the first insulating layer to cover at least the first dummy electrodes. In this manufacturing method, surfaces of the first wiring electrodes and the second wiring electrodes are exposed from the second insulating layer, and at least a portion of the first dummy electrodes is located between the first wiring electrodes and the second wiring electrodes.

[0009] According to the inventor's research, cracks that occur in the second insulating layer, etc., often occur near wiring electrodes connected to semiconductor devices, etc., via exposed surfaces. However, it has been found that providing dummy electrodes in proximity to these wiring electrodes can suppress the occurrence of cracks or the extension of existing cracks. Therefore, in this wiring board manufacturing method, at least a portion of the first dummy electrode that is not connected to a semiconductor chip, etc., is positioned between the first wiring electrode and the second wiring electrode that are connected to the semiconductor chip, etc. As a result, the wiring board manufactured by this manufacturing method can suppress the occurrence of cracks in the second insulating layer, etc., or the extension of existing cracks. As a result, when a semiconductor device is fabricated using this wiring board, wiring such as the first wiring electrode or the second wiring electrode is prevented from breaking due to temperature changes. As a result, this wiring board manufacturing method makes it possible to provide a wiring board that prevents wiring breakage due to cracks.

[0010] [2] In the method for manufacturing a wiring substrate according to [1] above, the width of the first dummy electrode may be 10 μm or more in a direction from the center of the first wiring electrode to the outside. In this case, the first dummy electrode can reliably suppress the extension of cracks that occur in the insulating layer near the first wiring electrode or the second wiring electrode. This makes it possible to provide a wiring substrate that more reliably prevents wiring breakage due to cracks.

[0011] [3] In the method for manufacturing a wiring substrate according to [1] or [2] above, the first dummy electrode may have a portion whose maximum width in a direction from the center of the first wiring electrode to the outside is 100 μm or more. In this case, it is possible to reliably prevent cracks from occurring in the insulating layer near the first wiring electrode or the second wiring electrode, or to more reliably prevent the extension of any cracks that do occur. This makes it possible to provide a wiring substrate that more reliably prevents wiring breakage due to cracks.

[0012] [4] In the method for manufacturing a wiring substrate according to any one of [1] to [3] above, the distance between the first wiring electrode and the first dummy electrode may be 50 μm or more. In this case, insulation between the first wiring electrode and the first dummy electrode can be ensured. This makes it possible to provide a wiring substrate in which the first dummy electrode does not impair the electrical conductivity of the first wiring electrode.

[0013] [5] In the method for manufacturing a wiring board according to any one of [1] to [4] above, the step of forming a plurality of openings in the resist layer may further include forming a fourth opening for a dummy electrode, and this manufacturing method may further include forming a second dummy electrode in the fourth opening. The first dummy electrode and the second dummy electrode may be formed such that at least a portion of each electrode is between the first wiring electrode and the second wiring electrode, with the first dummy electrode located on the first wiring electrode side and the second dummy electrode located on the second wiring electrode side. In this case, providing the second dummy electrode in addition to the first dummy electrode can suppress cracks from occurring near the second wiring electrode or suppress the extension of cracks that occur near the second wiring electrode. This makes it possible to provide a wiring board that further suppresses wiring breakage due to cracks.

[0014] [6] The method for manufacturing a wiring substrate according to [5] above may further include a step of forming a wiring portion between the first dummy electrode and the second dummy electrode, and the wiring portion may have a plurality of wirings of 10 μm or less. In this case, it is possible to provide a wiring substrate in which desired wiring is formed between the first wiring electrode and the second wiring electrode.

[0015] [7] In the method for manufacturing a wiring board according to [5] or [6] above, the first dummy electrode and the second dummy electrode may be connected by a conductive material. In this case, it is possible to provide a wiring board that improves the strength of the first dummy electrode and the second dummy electrode and more reliably suppresses the occurrence of cracks near the first wiring electrode and the second wiring electrode.

[0016] [8] In any of the wiring board manufacturing methods [1] to [7] above, the first dummy electrode may be formed to surround the first wiring electrode in a planar view. In this case, a wiring board can be provided that suppresses cracks from occurring or extending in any direction near the first wiring electrode. Furthermore, by providing dummy electrodes that surround the wiring electrode, a wiring board can be provided that is arranged so as not to hinder improvement in the packaging density of the wiring electrodes. Note that the second dummy electrode may be formed to surround the second wiring electrode in a planar view. In this case, the same effects as those of the first dummy electrode can be achieved.

[0017] [9] In the method for manufacturing a wiring substrate according to any one of [1] to [8] above, the first wiring electrode may have a portion that is curved in plan view, and the first dummy electrode may have a portion that is curved in plan view. By having the first wiring electrode have a portion that is curved, it is possible to provide a wiring substrate that suppresses cracks from occurring near the first wiring electrode. Furthermore, by having the first dummy electrode have a portion that is curved, it is possible to provide a wiring substrate that disperses the force of a generated crack and suppresses the crack from extending further.

[0018]

[10] In any of the wiring board manufacturing methods [1] to [9] above, the first dummy electrode may have a thickness equal to or greater than half the thickness of the second insulating layer. In this case, it is possible to provide a wiring board in which the first dummy electrode reliably prevents cracks originating near the first wiring electrode or the second wiring electrode from extending. The second dummy electrode may also have a thickness equal to or greater than half the thickness of the second insulating layer. In this case, the same effects as those of the first dummy electrode can be achieved.

[0019]

[11] In another aspect, the present disclosure provides a method for manufacturing a semiconductor device, the method comprising the steps of: preparing a wiring board manufactured by the wiring board manufacturing method according to any one of [1] to

[10] above; and mounting a semiconductor chip on the wiring board using a conductive member.

[0020] According to this method for manufacturing a semiconductor device, it is possible to provide a semiconductor device in which, as described above, the occurrence of cracks originating near the first wiring electrodes and the second wiring electrodes on a wiring substrate on which a semiconductor chip is mounted is suppressed, or the extension of cracks that have occurred is suppressed, thereby making it possible to provide a semiconductor device in which breakage of wiring due to cracks is prevented.

[0021]

[12] In the manufacturing method of a semiconductor device according to

[11] above, in the step of mounting the semiconductor chip, a first conductive member and a second conductive member, which are conductive members, may be arranged on the first wiring electrode and the second wiring electrode of the wiring substrate, respectively, and the semiconductor chip may be mounted on the first conductive member and the second conductive member, and the connection terminals of the semiconductor chip may be connected to the first wiring electrode and the second wiring electrode via the first conductive member and the second conductive member, and the semiconductor chip may be mounted on the surface of the wiring substrate on which the first dummy electrode is formed.

[0022]

[13] In yet another aspect, the present disclosure provides a wiring substrate including a support substrate, a first insulating layer provided on the support substrate, a second insulating layer provided on the first insulating layer, a first wiring electrode and a second wiring electrode provided in the second insulating layer, and a first dummy electrode provided in the second insulating layer, wherein surfaces of the first wiring electrode and the second wiring electrode are exposed from the second insulating layer, and at least a portion of the first dummy electrode is located between the first wiring electrode and the second wiring electrode.

[0023] In this wiring substrate, at least a portion of the first dummy electrode that is not connected to a semiconductor chip or the like is positioned between the first wiring electrode and the second wiring electrode that are connected to the semiconductor chip or the like. In this case, even if a temperature change or the like occurs in a semiconductor device using this wiring substrate, it is possible to suppress the occurrence of cracks in the second insulating layer or the like, or to suppress the extension of any cracks that do occur. As a result, in a semiconductor device using this wiring substrate, wiring such as the first wiring electrode or the second wiring electrode is prevented from being broken due to a temperature change.

[0024]

[14] In the wiring substrate of

[13] above, the width of the first dummy electrode may be 10 μm or more in a direction from the center of the first wiring electrode to the outside. In this case, the first dummy electrode can reliably suppress the extension of cracks that occur in the insulating layer near the first wiring electrode or the second wiring electrode. This more reliably prevents the wiring from being broken by cracks.

[0025]

[15] The wiring board of

[13] or

[14] above may further include a second dummy electrode provided in the second insulating layer, and at least a portion of the first dummy electrode and the second dummy electrode may be located between the first wiring electrode and the second wiring electrode, with the first dummy electrode located on the first wiring electrode side and the second dummy electrode located on the second wiring electrode side. In this case, the second dummy electrode can prevent cracks from occurring near the second wiring electrode or prevent cracks that occur near the second wiring electrode from extending. As a result, this wiring board can more reliably prevent wiring breakage due to cracks.

[0026]

[16] In the wiring board of any of

[13] to

[15] above, the first dummy electrode may be formed to surround the first wiring electrode in plan view. In this case, it is possible to suppress the occurrence or extension of cracks in any direction near the first wiring electrode. Furthermore, by providing dummy electrodes to surround the wiring electrode, it is possible to achieve a wiring board with a layout that does not hinder the improvement of the packaging density of the wiring electrodes. Note that the second dummy electrode may be formed to surround the second wiring electrode in plan view.

[0027]

[17] In yet another aspect, the present disclosure provides a semiconductor device. The semiconductor device includes a wiring substrate according to any one of the above-described embodiments

[13] to

[16] , a first conductive portion and a second conductive portion provided on the wiring substrate and on the first wiring electrode and the second wiring electrode, respectively, and a semiconductor chip mounted on the second insulating layer so as to be electrically connected to the first conductive portion and the second conductive portion. In this case, similar to the above, it is possible to prevent breakage of the wiring due to cracks.

[0028] According to the present disclosure, it is possible to prevent breakage of wiring due to cracks.

[0029] FIG. 1 is a cross-sectional view showing an example of a semiconductor device in which a semiconductor chip is mounted on a wiring substrate. FIG. 2 is a plan view showing the upper surface side of the wiring substrate of the semiconductor device shown in FIG. 1. FIG. 3 is a diagram showing a method of manufacturing a wiring substrate constituting the semiconductor device shown in FIG. 1. FIG. 4 is a diagram showing a method of manufacturing a wiring substrate, showing a step following FIG. 3. FIG. 5 is a diagram showing a method of manufacturing a wiring substrate, showing a step following FIG. 4. FIG. 6 is a diagram showing a method of manufacturing the semiconductor device shown in FIG. 1. FIG. 7 is a diagram showing how a crack occurring in the wiring substrate (semiconductor device) is stopped from extending by a dummy electrode. FIG. 8 is an enlarged view of a portion VIII of FIG. 7.

[0030] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, identical or equivalent parts will be designated by the same reference numerals, and duplicate explanations will be omitted. Furthermore, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings unless otherwise specified. When terms such as "left," "right," "front," "back," "top," "bottom," "upper," and "lower" are used in the description and claims of this specification, these terms are intended for explanatory purposes only and do not necessarily mean that these relative positions will always be the same. Furthermore, the dimensional proportions of the drawings are not limited to those shown.

[0031] In this specification, the term "layer" encompasses not only a structure with a shape formed over the entire surface when observed in a plan view, but also a structure with a shape formed on a portion of the surface. In this specification, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes as long as the intended effect of the process is achieved. In this specification, a numerical range indicated using "A to B" indicates a range that includes the numerical values ​​A and B written before and after "to" as the minimum and maximum values, respectively.

[0032] (Example of a semiconductor device including a wiring substrate) An example of a semiconductor device including a wiring substrate will be described with reference to Figures 1 and 2. As shown in Figure 1, the semiconductor device 1 includes a semiconductor chip 10, solder bumps 21, 22, and 23 (first conductive portion and second conductive portion), an insulating resin layer 25, and a wiring substrate 30.

[0033] The semiconductor chip 10 is, for example, a logic IC or a memory IC, and is mounted on the wiring substrate 30 via solder bumps 21 to 23. The connection terminals 11, 12, and 13 of the semiconductor chip 10 are connected to the wiring electrodes 70 of the wiring substrate 30 via the solder bumps 21 to 23. An insulating resin layer 25 formed from a sealing resin such as an underfill agent is provided between the semiconductor chip 10 and the wiring substrate 30.

[0034] 1 and 2, the wiring substrate 30 includes a support substrate 40, a first insulating layer 50, a second insulating layer 60, wiring electrodes 71, 72, and 73 (first wiring electrodes and second wiring electrodes), and dummy electrodes 81, 82, and 83 (first dummy electrodes and second dummy electrodes). The wiring substrate 30 may further include a wiring section 90. The wiring section 90 is a section in which various types of wiring are provided.

[0035] The support substrate 40 is not particularly limited, but may be, for example, a silicon substrate, a glass substrate, a SUS substrate, a substrate containing glass cloth, or a sealing resin containing a semiconductor element. The thickness of the support substrate 40 is, for example, 0.2 mm to 2.0 mm. When the thickness of the support substrate 40 is 0.2 mm or more, handling can be improved when manufacturing the wiring substrate 30 or when manufacturing the semiconductor device 1 using the wiring substrate 30. When the thickness of the support substrate 40 is 2.0 mm or less, material costs can be suppressed, thereby achieving cost reduction.

[0036] The first insulating layer 50 is an insulating layer formed on the support substrate 40 and is formed, for example, from a photosensitive insulating material. In this case, the first insulating layer 50 is composed of a cured product of the photosensitive insulating material. The photosensitive insulating material used may be a liquid or film-like material. From the viewpoints of film thickness flatness and cost, it is preferable to use a film-like photosensitive insulating material. Furthermore, from the viewpoint of forming fine wiring within the first insulating layer 50, the photosensitive insulating material used preferably contains a filler (filling material) having an average particle size of 500 nm or less in a photosensitive resin composition. The average particle size of the filler is more preferably 50 nm to 200 nm. The filler content in the photosensitive insulating material is preferably 0 to 70 parts by mass, and more preferably 10 to 50 parts by mass, based on 100 parts by mass of the photosensitive resin composition excluding the filler. The average particle size of the filler can be measured, for example, by measuring the particle sizes of approximately 20 fillers using a scanning electron microscope (SEM). An example of a measurement method using an SEM is a method in which a sample is prepared by curing a resin composition containing a filler, the central portion of the sample is cut, and the cross section is observed with an SEM.

[0037] The thermal expansion coefficient of the first insulating layer 50 after curing is set to 80×10 －６ / K or less, and from the viewpoint of obtaining high reliability, it is 70×10 －６ / K or less. The thermal expansion coefficient of the material of the first insulating layer 50 after hardening is preferably 20×10 / K or less from the viewpoint of the stress relaxation property of the insulating material and the ability to obtain a highly precise pattern. －６ It is more preferable that the value is 1 / K or more.

[0038] The thickness of the first insulating layer 50 is not particularly limited, but is preferably 10 μm or less, more preferably 5 μm or less, and even more preferably 3 μm or less. When the thickness of the first insulating layer 50 is within the above range, it becomes easier to form fine wiring within the first insulating layer 50. From the viewpoint of insulation reliability, the thickness of the first insulating layer 50 is preferably 1 μm or more.

[0039] The second insulating layer 60 is an insulating layer formed on the first insulating layer 50. Like the first insulating layer 50, the second insulating layer 60 is formed from, for example, a photosensitive insulating material and is composed of a cured product of the photosensitive insulating material. Other configurations of the second insulating layer 60 (such as thickness and filler content) may be the same as those of the first insulating layer 50.

[0040] The wiring electrodes 71-73 are exposed on the surface side of the wiring substrate 30 and are electrodes for connection to the semiconductor chip 10, etc. The wiring electrodes 71-73 are formed on the first insulating layer 50 and within the second insulating layer 60. Each of the wiring electrodes 71-73 has, for example, a circular or rectangular shape when viewed in plan. If the wiring electrodes 71-73 are circular, their diameter is, for example, 50 μm to 300 μm. The wiring electrodes 71-73 are formed from a conductive material such as copper. As the wiring substrate 30, each of the wiring electrodes 71-73 is configured so that its surface is exposed from the second insulating layer 60 and is connected to the semiconductor chip 10 via solder bumps 21-23 arranged on the wiring electrodes 71-73. Note that, in the example shown in the figure, three wiring electrodes 71-73 are shown for ease of explanation, but the number of wiring electrodes on the wiring substrate 30 is not limited to this, and a larger number of wiring electrodes may be provided on a single wiring substrate 30. The same applies to dummy electrodes 81 to 83, which will be described later.

[0041] The dummy electrodes 81-83, together with the wiring electrodes 71-73, are formed on the first insulating layer 50 and within the second insulating layer 60. At least a portion of each of the dummy electrodes 81-83 is located between two adjacent wiring electrodes 71-73 (wiring electrodes 71 and 72 or wiring electrodes 72 and 73). Each of the dummy electrodes 81-83 is formed to surround the corresponding wiring electrode 71-73 in a planar view. In the example shown in FIG. 2 , each of the dummy electrodes 81-83 has a circular void space 81a, 82a, 83a on the inside, and has a rectangular frame-like (circumferential) outer shape. The corresponding wiring electrodes 71-73 are disposed in the void spaces 81a-83a of the dummy electrodes 81-83. The shape of the dummy electrodes 81-83 allows for efficient electrode arrangement in the planar direction on the wiring substrate 30, thereby improving packaging density while providing the dummy electrodes 81-83. The dummy electrodes 81 to 83 are made of, for example, copper, similar to the wiring electrodes 71 to 73. Each of the dummy electrodes 81 to 83 is configured to be sealed within the second insulating layer 60, and unlike the wiring electrodes 71 to 73, is an electrode that is not connected to the semiconductor chip 10 via a solder bump or the like.

[0042] The dummy electrodes 81 to 83 have a width of, for example, 10 μm or more at their narrowest portions 81b in the direction from the center of the corresponding wiring electrodes 71 to 73 outward. The width of the narrowest portions 81b is preferably 20 μm or more. Furthermore, the dummy electrodes 81 to 83 have a width (maximum width) of, for example, 100 μm or more at their widest portions 81c in the direction from the center of the corresponding wiring electrodes 71 to 73 outward. The width of the widest portions 81c is preferably 150 μm or more. The distance between the outer periphery of each wiring electrode 71 to 73 and the inner periphery of the dummy electrodes 81 to 83 is, for example, 50 μm or more, and preferably 100 μm or more.

[0043] A connecting electrode 84 and a connecting electrode 85 may be further provided between the dummy electrodes 81 and 82, and between the dummy electrodes 82 and 83. The connecting electrode 84 is an electrode that extends to connect the dummy electrodes 81 and 82, and the connecting electrode 85 is an electrode that extends to connect the dummy electrodes 82 and 83. The connecting electrodes 84 and 85 can be formed from copper wiring, similar to the wiring electrodes 71 to 73 and the dummy electrodes 81 to 83.

[0044] Wiring sections 90 may be further provided between the connecting electrodes 84 and between the connecting electrodes 85. The wiring section 90 is a wiring section including fine wiring (for example, wiring of 10 μm or less). Furthermore, another wiring section 91 may be provided outside the dummy electrodes 81 to 83 (between another dummy electrode adjacent in the vertical direction in the figure). The wiring section 91 is a wiring section including a plurality of fine wirings, similar to the wiring section 90. The wiring sections 90 and 91 may not be provided, and in that case, the wiring electrodes 71 to 73 and the dummy electrodes 81 to 83 may be further provided at the locations where the wiring sections 90 and 91 are arranged.

[0045] (Method for Manufacturing Wiring Board) Next, a method for manufacturing the wiring board 30 will be described with reference to FIGS. 3 to 5. FIGS. 3 to 5 are diagrams sequentially showing a method for manufacturing one or more wiring boards 30. The method for manufacturing the wiring board 30 includes the following steps (a) to (h): (a) forming a first insulating layer on a support substrate; (b) forming a seed layer on the first insulating layer; (c) forming a resist layer on the first insulating layer (seed layer); (d) forming openings for wiring electrodes and openings for dummy electrodes in the resist layer; (e) forming wiring electrodes in the openings for the wiring electrodes; (f) forming dummy electrodes in the openings for the dummy electrodes; (g) removing the resist layer after forming the wiring electrodes and dummy electrodes; and (h) forming a second insulating layer on the first insulating layer so as to cover the dummy electrodes.

[0046] The method for manufacturing a wiring board according to this embodiment is particularly suitable for applications requiring miniaturization and an increased number of pins, and is particularly suitable for package configurations requiring an interposer for mounting different types of chips. More specifically, the manufacturing method according to this embodiment is suitable for package configurations in which the pin spacing is 200 μm or less (for example, 30 to 100 μm in even finer cases) and the number of pins is 500 or more (for example, 1,000 to 10,000 in even finer cases). Note that the term "pin" here refers to a wiring electrode.

[0047] [Step (a)] In step (a), first, as shown in FIG. 3A, a support substrate 110 is prepared, and a first insulating layer 120 is formed on the support substrate 110. The support substrate 110 is a substrate corresponding to the support substrate 40 and is not particularly limited, but may be, for example, a silicon substrate, a glass substrate, a SUS substrate, a substrate containing glass cloth, or a semiconductor element containing sealing resin. The thickness of the support substrate 110 is, for example, 0.2 mm to 2.0 mm. A thickness of 0.2 mm or more of the support substrate 110 improves handleability. Furthermore, a thickness of 2.0 mm or less of the support substrate 110 reduces material costs and achieves cost reduction. The planar shape of the support substrate 140 may be a wafer shape or a panel shape. The size of the support substrate 110 is not particularly limited, but is preferably, for example, a wafer with a diameter of 200 mm, 300 mm, or 450 mm, or a rectangular panel with a side length of 300 mm to 700 mm.

[0048] The first insulating layer 120 is formed, for example, from an insulating material containing at least one of a photosensitive insulating material and a thermosetting insulating resin composition. This insulating material can be a liquid or film-like material, and from the viewpoints of film thickness flatness and cost, a film-like insulating material is preferably used. In the process of forming the first insulating layer 120, the first insulating layer 120 is formed by laminating such a film-like insulating material on the support substrate 110. Furthermore, when fine wiring is formed in the first insulating layer 120, the insulating material preferably contains a filler (filling material) with an average particle size of 500 nm or less in the resin composition. The average particle size of the filler is more preferably 50 nm to 200 nm. The filler content in the insulating material is preferably 0 to 70 parts by mass, and more preferably 10 to 60 parts by mass, based on 100 parts by mass of the photosensitive resin composition excluding the filler.

[0049] When a film-like insulating material is used for the first insulating layer 120, it is preferable to carry out the lamination process at a low temperature, and therefore it is preferable to use an insulating film that can be laminated at 40°C to 120°C. If the lamination temperature of the film-like insulating material used for the first insulating layer 120 is 40°C or higher, tackiness at room temperature (approximately 25°C) can be weakened, improving handleability. On the other hand, if the lamination temperature of the film-like insulating material used for the first insulating layer 120 is 120°C or lower, warping after lamination can be reduced when the insulating film is attached by lamination.

[0050] The first insulating layer 120 may be formed by laminating the above-described film-like photosensitive material on the support substrate 110 and then curing the same. The thermal expansion coefficient of the cured first insulating layer 120 is set to 80×10 from the viewpoint of suppressing warpage. －６ / K or less, and from the viewpoint of obtaining high reliability, it is 70×10 －６ The thermal expansion coefficient of the first insulating layer 120 after curing is preferably 20×10 / K or less from the viewpoint of the stress relaxation property of the insulating material and the ability to obtain a highly precise pattern. －６ It is more preferable that the value is 1 / K or more.

[0051] The thickness of the first insulating layer 120 is not particularly limited, but is preferably 10 μm or less, more preferably 5 μm or less, and even more preferably 3 μm or less. When the thickness of the first insulating layer 120 is within the above range, it becomes easier to form fine wiring within the first insulating layer 120. From the viewpoint of insulation reliability, the thickness of the first insulating layer 120 is preferably 1 μm or more.

[0052] [Step (b)] Subsequently, once the first insulating layer 120 is formed, the surface of the first insulating layer 120 is modified, and a seed layer (not shown) is formed thereon. Methods for modifying the surface of the first insulating layer 120 include desmearing, ultraviolet irradiation, electron beam irradiation, ozone water treatment, corona discharge treatment, and plasma treatment. Among these methods, ultraviolet irradiation or desmearing is preferred, as they do not require vacuum equipment and do not generate waste liquid. Examples of ultraviolet irradiation lamps used for modification include high-pressure mercury lamps, low-pressure mercury lamps, and vacuum ultraviolet excimer lamps. However, it is preferred to use low-pressure mercury lamps or excimer lamps, which have a greater activation effect. Modification by ultraviolet irradiation is preferably performed in the atmosphere, and more preferably in an oxygen atmosphere. The modification is preferably performed at 25°C to 100°C. To further accelerate reactivity, it is more preferred to perform the modification at 40°C to 100°C, and even more preferred at 60°C to 100°C.

[0053] A seed layer is formed on the modified first insulating layer 120 by, for example, electroless copper plating. In this embodiment, the first insulating layer 120 is first washed with a pretreatment solution to adsorb palladium, which serves as a catalyst for electroless copper plating, onto the surface 121 of the first insulating layer 120. The pretreatment solution may be a commercially available alkaline pretreatment solution containing sodium hydroxide or potassium hydroxide. The concentration of sodium hydroxide or potassium hydroxide is between 1% and 30%. The immersion time in the pretreatment solution is between 1 minute and 60 minutes. The immersion temperature in the pretreatment solution is between 25°C and 80°C. After the pretreatment, excess pretreatment solution may be removed by washing with tap water, pure water, ultrapure water, or an organic solvent. Alternatively, the seed layer may be formed by sputtering. The seed layer formed by sputtering is preferably a metal species such as copper or titanium.

[0054] Palladium is deposited on the surface 121 of the first insulating layer 120 after immersion cleaning in the acidic aqueous solution. When depositing palladium, it is preferable to use a commercially available palladium-tin colloidal solution, an aqueous solution containing palladium ions, a palladium ion suspension, or the like, but it is more preferable to use an aqueous solution containing palladium ions that are effectively adsorbed to the modified layer.

[0055] When immersed in an aqueous solution containing palladium ions, the temperature of the aqueous solution containing palladium ions is 25°C to 80°C, and the immersion time for adsorption is between 1 minute and 60 minutes. After adsorption of palladium ions, the substrate may be washed with city water, pure water, ultrapure water, or an organic solvent to remove excess palladium ions. After adsorption of palladium ions, activation is performed to allow the palladium ions to act as a catalyst. A commercially available activator (activation treatment solution) may be used as the reagent for activating the palladium ions. The temperature of the activator used for immersion to activate the palladium ions is 25°C to 80°C, and the immersion time for activation is between 1 minute and 60 minutes. After activation of the palladium ions, the substrate may be washed with city water, pure water, ultrapure water, or an organic solvent to remove excess activator.

[0056] Thereafter, electroless copper plating is performed on the surface 121 of the first insulating layer 120 to form a seed layer. This seed layer serves as a power supply layer for the electrolytic plating performed in steps (e) and (f) described below. Examples of electroless copper plating include electroless pure copper plating (purity of 99% by mass or more) and electroless copper-nickel-phosphorus plating (nickel content: 1% by mass to 10% by mass, phosphorus content: 1% by mass to 13% by mass). However, from the viewpoint of adhesion, electroless copper-nickel-phosphorus plating is preferred. The electroless copper-nickel-phosphorus plating solution may be a commercially available plating solution, such as an electroless copper-nickel-phosphorus plating solution (manufactured by JCU Corporation, product name "AISL-570"). The electroless copper-nickel-phosphorus plating is performed in an electroless copper-nickel-phosphorus plating solution at 60°C to 90°C. The thickness of the seed layer formed by electroless copper plating is preferably 80 nm to 700 nm, more preferably 100 nm to 500 nm, and even more preferably 150 nm to 300 nm.

[0057] [Step (c)] Subsequently, after the seed layer is formed on the first insulating layer 120, as shown in (b) of Fig. 3, a resist layer 130 is formed on the first insulating layer 120 on which the seed layer has been formed. The resist used here is a photosensitive resist, and the photosensitive resist is applied to the seed layer on the first insulating layer 120 to form the resist layer 130. The thickness of the resist layer 130 is, for example, 12 µm to 40 µm.

[0058] [Step (d)] Next, after the resist layer 130 is formed, as shown in FIG. 4A, openings 131, 132, and 133 (first and second openings) for the wiring electrodes and openings 136, 137, and 138 (third and fourth openings) for the dummy electrodes are formed in the resist layer 130. This results in a resist layer 130a having openings. The openings 131 to 133 correspond to the wiring electrodes 71 to 73 described above (see FIG. 2) and have, for example, a circular or rectangular shape in plan view. The openings 136 to 138 correspond to the dummy electrodes 81 to 83 described above and have, for example, a frame shape surrounding the openings 131 to 133 in plan view, with a circular void on the inside and a rectangular shape on the outside.

[0059] Methods for forming the wiring electrode openings 131-133 and the dummy electrode openings 136-138 include laser ablation, photolithography, imprinting, and the like. Among these methods, from the standpoints of miniaturization and cost, it is preferable to form a resist layer 130 made of a photosensitive resin material in step (c) and then form the openings 131-133 by a photolithography process (exposure and development). Typical exposure methods for the photosensitive resin material include projection exposure, contact exposure, and direct writing exposure. Development methods preferably use an alkaline aqueous solution of sodium carbonate or TMAH (tetramethylammonium hydroxide). After forming the openings 131-133 and 136-138 in the resist layer 130, the insulating material may be further heated and cured. The heating temperature is 200°C to 280°C, and the heating time is between 5 minutes and 1 hour. Furthermore, if any residue of the resist layer 130 remains on the opened surface, it can be removed by oxygen plasma treatment, argon plasma treatment, or nitrogen plasma treatment.

[0060] The opening shapes of the openings 131 to 133 for the wiring electrodes formed in step (d) may be, for example, circular, elliptical, or rectangular. In this case, the opening size of the openings 131 to 133 may be 5 μm to 400 μm in diameter, or may be smaller, such as a circle with a diameter of 5 μm to 10 μm.

[0061] As described above, the opening shapes of the dummy electrode openings 136 to 138 formed in step (d) are frame shapes that surround the wiring electrode openings 131 to 133 (see FIG. 2). Therefore, at least a portion of the dummy electrode openings 136 to 138 is formed so as to be located between two adjacent wiring electrode openings 131 to 133. The dummy electrode openings 136 to 138 may be formed simultaneously with the wiring electrode openings 131 to 133, or may be formed separately.

[0062] [Step (e)] Next, as shown in FIG. 4B, wiring electrodes 141, 142, and 143 are formed in the wiring electrode openings 131 to 133. In this step, copper plating is performed using the seed layer formed in step (b) as a power supply layer. As a result, the openings 131 to 133 in the resist layer 130a are filled with a conductive material (e.g., copper), forming the wiring electrodes 141 to 143. The thickness of the wiring electrodes 141 to 143 is preferably 1 to 20 μm, more preferably 3 to 15 μm, and even more preferably 5 to 15 μm. The wiring electrodes 141 to 143 have a planar shape corresponding to the openings 131 to 133, and may be, for example, circular, elliptical, or rectangular.

[0063] [Step (f)] In addition to step (e), dummy electrodes 146, 147, and 148 are formed in the dummy electrode openings 136 to 138. In this step, similar to step (e), copper plating is performed using the seed layer formed in step (b) as a power supply layer. This fills the openings 136 to 138 with a conductive material (e.g., copper), forming the dummy electrodes 146 to 148. The thickness of the dummy electrodes 146 to 148 is preferably 1 to 20 μm, more preferably 3 to 15 μm, and even more preferably 5 to 15 μm. The dummy electrodes 146 to 148 have a planar shape corresponding to the openings 136 to 138, for example, a frame shape with a circular, elliptical, or rectangular inner surface and a rectangular outer surface (see FIG. 2). However, the dummy electrodes 146 to 148 may have other shapes as long as a part of them is located between two adjacent wiring electrodes 141 to 143, and may have a shape that corresponds to or follows the shape of the wiring electrodes 141 to 143. The dummy electrodes 146 to 148 may be formed simultaneously with the wiring electrodes 141 to 143, or may be formed separately. That is, step (e) and step (f) may be performed simultaneously or separately.

[0064] [Step (g)] Next, after the wiring electrodes 141-143 and the dummy electrodes 146-148 have been formed, the resist layer 130a is removed as shown in FIG. 5A. The resist layer 130a can be removed using various commercially available stripping solutions. The seed layer exposed by the stripping of the resist layer 130a is then removed. Palladium remaining below the seed layer may also be removed in conjunction with the removal of the seed layer. This removal can be performed using a commercially available stripping solution (etching solution). Specific examples include acidic etching solutions (BB-20, PJ-10, and SAC-700W3C, manufactured by JCU Corporation). After the resist layer 130a is stripped, a treatment may be performed to modify the surfaces of the wiring electrodes 141-143 and the dummy electrodes 146-148, which are made of a conductive material. This treatment is, for example, a roughening treatment using an acid, which can create irregularities on the electrode surfaces. Commercially available treatment solutions can be used as the treatment chemicals.

[0065] [Step (h)] Next, after the resist layer 130a is peeled off, a second insulating layer 150 is formed on the first insulating layer 120 to cover the wiring electrodes 141-143 and the dummy electrodes 146-148. The second insulating layer 150 is made of a photosensitive resin material, solder resist, or the like, and may have a thickness of, for example, 15 μm to 30 μm. When forming the second insulating layer 150, as shown in FIG. 5B, the surfaces 141a, 142a, and 143a of the wiring electrodes 141-143 are formed so as to be exposed from the second insulating layer 150. This exposure method can be a lithography process or laser processing. The lithography process can be a semi-additive process or a subtractive process. Note that the thickness of the dummy electrodes 146-148 embedded in the second insulating layer 150 is preferably at least half the thickness of the second insulating layer 150.

[0066] The material used for the second insulating layer 150 may be, for example, a material containing a carboxyl group-containing photosensitive resin composition. This carboxyl group-containing photosensitive resin composition may be a carboxyl group-containing photosensitive resin obtained by reacting a resin obtained by converting some or all of the phenolic hydroxyl groups of a phenol compound (a) having two or more phenolic hydroxyl groups in a molecule having a structure of the following general formula (1), obtained by a condensation reaction of a polymethylol of bisphenol A or bisphenol F with a phenol, with acrylic acid and / or methacrylic acid (c), and then reacting the resulting reaction product with a polybasic acid anhydride (d). (In the formula, R1 is —C(CH3)2— or —CH2—, R2 is a hydrocarbon group having 1 to 11 carbon atoms, a is an integer of 0 to 3, n is an integer of 1 or 2, and m is an integer of 1 to 10.)

[0067] In this manner, the wiring substrate 30 constituting the semiconductor device 1 shown in FIG. 1 can be fabricated.

[0068] (Method for Manufacturing Semiconductor Device) Next, a method for manufacturing the semiconductor device 1 using the wiring substrate 30 manufactured by the above-described manufacturing method will be described with reference to Fig. 6. Fig. 6 is a diagram showing a method for fabricating the semiconductor device 1. The method for manufacturing the semiconductor device 1 includes the following steps (j) to (k): (j) a step of preparing the above-described wiring substrate 30; and (k) a step of mounting a semiconductor chip on the wiring substrate using a conductive member.

[0069] 6A, in the step (j), a wiring substrate 30 is first prepared, and one or more semiconductor chips 10 are also prepared.

[0070] [Step (k)] Next, once preparation of the wiring substrate 30 is complete, the semiconductor chip 10 is mounted on the wiring substrate 30. In this mounting step, first, the wiring electrodes 141-143 of the wiring substrate 30 are surface-treated to remove organic components from the exposed surfaces. Then, solder bumps 161, 162, and 163 (first and second conductive members) are placed (mounted) on the wiring electrodes 141-143 of the wiring substrate 30, respectively, and a reflow process is performed. Then, the semiconductor chip 10 is mounted on the solder bumps 161-163, and a reflow process is performed again. As a result, the connection terminals 11-13 of the semiconductor chip 10 are connected to the wiring electrodes 141-143 via the solder bumps 161-163, and the semiconductor chip 10 is mounted on the surface of the wiring substrate 30 on which the dummy electrodes 146-148 are formed.

[0071] Subsequently, after the reflow process is completed, the substrate is diced into individual pieces, and then, as shown in Fig. 6(b), an underfilm agent, which is the insulating resin layer 25, is filled between the second insulating layer 60 (corresponding to the second insulating layer 150 before dicing) of the wiring substrate 30 and the semiconductor chip 10 to seal the space between them, thereby forming the insulating resin layer 25. In this way, the semiconductor device 1 shown in Fig. 1 is fabricated.

[0072] As described above, according to the method for manufacturing a wiring board of this embodiment, some of the dummy electrodes 146-148 (dummy electrodes 81-83) that are not connected to the semiconductor chip 10 or the like are positioned between the wiring electrodes 141-143 (wiring electrodes 71-73) that are connected to the semiconductor chip 10 or the like. As a result, the wiring board 30 manufactured by this manufacturing method can suppress the occurrence of cracks in the second insulating layer 60 or the like, or suppress the extension of cracks that do occur. As a result, when a semiconductor device 1 is fabricated using the wiring board 30, the wiring of the wiring electrodes 141-143 (wiring electrodes 71-73) is prevented from breaking due to temperature changes. As described above, according to this method for manufacturing a wiring board, it is possible to provide a wiring board that prevents wiring breakage due to cracks.

[0073] In the method for manufacturing a wiring board according to this embodiment, the width of the dummy electrodes 146 to 148 (dummy electrodes 81 to 83) is 10 μm or more in the direction from the center of the wiring electrodes 141 to 143 (wiring electrodes 71 to 73) outward. This makes it possible for the dummy electrodes 146 to 148 (dummy electrodes 81 to 83) to reliably suppress the extension of cracks that occur in the insulating layer near the wiring electrodes 141 to 143 (wiring electrodes 71 to 73).

[0074] In the method for manufacturing a wiring substrate according to this embodiment, the dummy electrodes 146 to 148 (dummy electrodes 81 to 83) have portions 81c, 82c, and 83c whose maximum width in the direction from the center of the wiring electrodes 141 to 143 (wiring electrodes 71 to 73) is 100 μm or more. This makes it possible to reliably prevent cracks from occurring in the insulating layer near the wiring electrodes 141 to 143 (wiring electrodes 71 to 73) or more reliably prevent cracks from extending once they have occurred.

[0075] In the method for manufacturing a wiring board according to this embodiment, the distance between the wiring electrodes 141 to 143 (wiring electrodes 71 to 73) and the dummy electrodes 146 to 148 (dummy electrodes 81 to 83) is 50 μm or more. This ensures insulation between the wiring electrodes 141 to 143 (wiring electrodes 71 to 73) and the dummy electrodes 146 to 148 (dummy electrodes 81 to 83), resulting in a wiring board in which the dummy electrodes 146 to 148 (dummy electrodes 81 to 83) do not impede the electrical conductivity of the wiring electrodes 141 to 143 (wiring electrodes 71 to 73).

[0076] The method for manufacturing a wiring substrate according to this embodiment may further include a step of forming a wiring portion 90 between adjacent dummy electrodes 146 to 148 (dummy electrodes 81 to 83). The wiring portion 90 may have a plurality of wirings of 10 μm or less. In this case, it is possible to provide a wiring substrate in which desired wirings are formed between adjacent wiring electrodes 141 to 143 (wiring electrodes 71 to 73).

[0077] In the method for manufacturing a wiring board according to this embodiment, adjacent dummy electrodes 146 to 148 (dummy electrodes 81 to 83) may be connected to each other by a conductive material, thereby improving the strength of the dummy electrodes 146 to 148 (dummy electrodes 81 to 83) and providing a wiring board that more reliably prevents cracks from occurring near the wiring electrodes 141 to 143 (wiring electrodes 71 to 73).

[0078] In the method for manufacturing a wiring board according to this embodiment, the dummy electrodes 146-148 (dummy electrodes 81-83) are formed so as to surround the wiring electrodes 141-143 (wiring electrodes 71-73) in a plan view. This makes it possible to provide a wiring board 30 that suppresses the occurrence or extension of cracks in any direction near the wiring electrodes 141-143 (wiring electrodes 71-73). Furthermore, by providing the dummy electrodes 146-148 (dummy electrodes 81-83) so as to surround the wiring electrodes 141-143 (wiring electrodes 71-73), it is possible to provide a wiring board 30 that is arranged in a way that does not hinder the improvement of the packaging density of the wiring electrodes 141-143 (wiring electrodes 71-73).

[0079] In the wiring substrate manufacturing method according to this embodiment, the wiring electrodes 141 to 143 (wiring electrodes 71 to 73) may have portions that are curved in plan view, for example, the outer periphery is circular. Furthermore, the dummy electrodes 146 to 148 (dummy electrodes 81 to 83) may have portions that are curved in plan view, for example, the inner periphery is circular. By having the wiring electrodes 141 to 143 (wiring electrodes 71 to 73) have portions that are curved, it is possible to prevent cracks from occurring starting near the wiring electrodes 141 to 143 (wiring electrodes 71 to 73). Furthermore, by having the dummy electrodes 146 to 148 (dummy electrodes 81 to 83) have portions that are curved, it is possible to disperse the force of any cracks that occur and prevent the cracks from extending further.

[0080] In the method for manufacturing a wiring board according to this embodiment, the dummy electrodes 146 to 148 (dummy electrodes 81 to 83) have a thickness that is at least half the thickness of the second insulating layer 60. This makes it possible for the dummy electrodes 146 to 148 (dummy electrodes 81 to 83) to reliably prevent cracks that originate near the wiring electrodes 141 to 143 (wiring electrodes 71 to 73) from extending.

[0081] The method for manufacturing a semiconductor device according to this embodiment makes it possible to provide a semiconductor device that suppresses the occurrence of cracks originating near the wiring electrodes 71 to 73 or the extension of cracks that have occurred in the wiring substrate 30 on which the semiconductor chip 10 is mounted, thereby making it possible to provide a semiconductor device in which breakage of wiring due to cracks is prevented.

[0082] In the wiring board according to this embodiment, at least some of the dummy electrodes 81-83 that are not connected to the semiconductor chip 10 or the like are positioned between the wiring electrodes 71-73 that are connected to the semiconductor chip 10 or the like. In this case, even if a temperature change or the like occurs in the semiconductor device 1 that uses this wiring board 30, it is possible to suppress the occurrence of cracks in the second insulating layer 60 or the like, or to suppress the extension of any cracks that do occur. As a result, in the semiconductor device 1 that uses the wiring board 30, the wiring of the wiring electrodes 71-73 and the like is prevented from being broken due to a temperature change.

[0083] In the wiring board according to this embodiment, the width of the dummy electrodes 81 to 83 is 10 μm or more in the direction from the center of the wiring electrodes 71 to 73 outward. This makes it possible for the dummy electrodes 81 to 83 to reliably suppress the extension of cracks that occur in the insulating layer near the wiring electrodes 71 to 73. This makes it possible to more reliably prevent the wiring from breaking due to cracks.

[0084] In the wiring board according to this embodiment, the dummy electrodes 81 to 83 are formed so as to surround the wiring electrodes 71 to 73 in a plan view. This makes it possible to prevent cracks from occurring or extending in any direction near the wiring electrodes 71 to 73. Furthermore, by providing the dummy electrodes 81 to 83 so as to surround the wiring electrodes 71 to 73, the wiring board 30 can be arranged in a manner that does not hinder an improvement in the packaging density of the wiring electrodes 71 to 73.

[0085] The present invention will be explained in more detail below by way of examples, although the present invention is not limited to these examples.

[0086] First, large-sized samples corresponding to multiple wiring substrates 30 were fabricated, as shown in FIG. 7 . These samples were fabricated using the method shown in FIGS. 3 to 5 , and the wiring electrodes 141 to 143 (wiring electrodes 71 to 73) and dummy electrodes 146 to 148 (dummy electrodes 81 to 83) were fabricated using copper plating. The diameters of the wiring electrodes 71 to 73 were 240 μm to 280 μm. The widths of the dummy electrodes 81 to 83 (minimum widths, corresponding to portion 81b in FIG. 2 ) measured from the center of the corresponding wiring electrode to the outside were 150 μm. The widths of the dummy electrodes 81 to 83 (maximum widths, corresponding to portions 81c, 82c, and 83c in FIG. 2 ) measured from the center of the corresponding wiring electrode to the outside were 170 μm. The second insulating layer 150 (second insulating layer 60) was made of a photosensitive insulating material and had a thickness of 18 μm. As shown in FIG. 5B, the wiring electrodes 141 to 143 (wiring electrodes 71 to 73) were exposed from the surface of the second insulating layer 150, but the dummy electrodes 146 to 148 (dummy electrodes 146 to 148) were not exposed from the surface of the second insulating layer 150. Other materials and manufacturing methods were conventional. A sample of the semiconductor package manufactured in this manner was subjected to a temperature cycle test. The test temperature was from -65°C to 150°C, and the holding times at the maximum temperature and the minimum temperature were each 15 minutes.

[0087] 7 and 8 show the state of cracks that occurred when the above-mentioned test was performed on an actual wiring substrate 30. FIG. 8 is an enlarged view of portion VIII in FIG. 7. The test results show that even when cracks occur near wiring electrodes 71-73, the dummy electrodes 81-83 located between the wiring electrodes 71-73 prevent the cracks from extending further. From the above, it was confirmed that providing dummy electrodes prevents cracks from extending further and prevents wiring breakage due to cracks.

[0088] 1...semiconductor device, 10...semiconductor chip, 11-13...connection terminals, 21-23...solder bumps (first conductive portion, second conductive portion), 25...insulating resin layer, 30...wiring substrate, 40, 110...support substrate, 50, 120...first insulating layer, 60, 150...second insulating layer, 71-73, 141-143...wiring electrodes (first wiring electrode, second wiring electrode), 81-83, 146-148...dummy electrodes (first dummy electrode, second dummy electrode), 90...wiring portion, 130...resist layer, 131-133...openings (first opening, second opening), 136-138 (third opening, fourth opening), 141a-143a...surface.

Claims

1. A step of forming a first insulating layer on a support substrate, A step of forming a resist layer on the first insulating layer, The process of forming a plurality of openings in the resist layer, including a first opening and a second opening for wiring electrodes and a third opening for dummy electrodes, A step of forming a first wiring electrode and a second wiring electrode in the first opening and the second opening, respectively. The steps include forming a first dummy electrode in the third opening, A step of removing the resist layer after forming the first wiring electrode, the second wiring electrode, and the first dummy electrode, The process includes the step of forming a second insulating layer on the first insulating layer so as to cover at least the first dummy electrode, A method for manufacturing a wiring substrate, wherein the surfaces of the first wiring electrode and the second wiring electrode are exposed from the second insulating layer, and at least a portion of the first dummy electrode is located between the first wiring electrode and the second wiring electrode.

2. The width of the first dummy electrode is 10 μm or more in the direction outward from the center of the first wiring electrode. A method for manufacturing a wiring board according to claim 1.

3. The first dummy electrode has a portion having a maximum width of 100 μm or more in the direction extending outward from the center of the first wiring electrode. A method for manufacturing a wiring board according to claim 1.

4. The distance between the first wiring electrode and the first dummy electrode is 50 μm or more. A method for manufacturing a wiring board according to claim 1.

5. In the step of forming a plurality of openings in the resist layer, a fourth opening for a dummy electrode is further formed. The process further comprises the step of forming a second dummy electrode in the fourth opening, The first dummy electrode and the second dummy electrode are such that at least a portion of each electrode is formed between the first wiring electrode and the second wiring electrode, with the first dummy electrode located on the side of the first wiring electrode and the second dummy electrode located on the side of the second wiring electrode. A method for manufacturing a wiring board according to claim 1.

6. The process further includes the step of forming a wiring portion between the first dummy electrode and the second dummy electrode, The aforementioned wiring section has multiple wires of 10 μm or less. The method for manufacturing a wiring board according to claim 5.

7. The first dummy electrode and the second dummy electrode are connected by a conductive material. The method for manufacturing a wiring board according to claim 5.

8. The first dummy electrode is formed to surround the first wiring electrode when viewed from above. A method for manufacturing a wiring board according to claim 1.

9. The first wiring electrode has a portion that is curved when viewed from above, The first dummy electrode has a portion that is curved when viewed from above. A method for manufacturing a wiring board according to claim 1.

10. The first dummy electrode has a thickness of at least half the thickness of the second insulating layer. A method for manufacturing a wiring board according to claim 1.

11. A step of preparing the wiring board manufactured by the wiring board manufacturing method described in any one of claims 1 to 10, A step of mounting a semiconductor chip onto the wiring board using a conductive material, A method for manufacturing a semiconductor device, comprising:

12. In the process of mounting the semiconductor chip, the first conductive member and the second conductive member, which are conductive members, are placed on the first wiring electrode and the second wiring electrode of the wiring board, respectively, and the semiconductor chip is mounted on the first conductive member and the second conductive member, and the connection terminals of the semiconductor chip are connected to the first wiring electrode and the second wiring electrode via the first conductive member and the second conductive member, and the semiconductor chip is mounted on the surface of the wiring board on which the first dummy electrode is formed. A method for manufacturing a semiconductor device according to claim 11.

13. Support substrate and A first insulating layer provided on the support substrate, A second insulating layer provided on the first insulating layer, The first wiring electrode and the second wiring electrode are provided within the second insulating layer, The invention comprises a first dummy electrode provided in the second insulating layer, A wiring substrate in which the surfaces of the first wiring electrode and the second wiring electrode are exposed from the second insulating layer, and at least a portion of the first dummy electrode is located between the first wiring electrode and the second wiring electrode.

14. The width of the first dummy electrode is 10 μm or more in the direction outward from the center of the first wiring electrode. The wiring board according to claim 13.

15. The present invention further comprises a second dummy electrode provided within the second insulating layer, The first dummy electrode and the second dummy electrode are such that at least a portion of each electrode is located between the first wiring electrode and the second wiring electrode, with the first dummy electrode located on the side of the first wiring electrode and the second dummy electrode located on the side of the second wiring electrode. The wiring board according to claim 13.

16. The first dummy electrode is formed to surround the first wiring electrode when viewed from above. The wiring board according to claim 13.

17. A wiring board according to any one of claims 13 to 16, A first conductive portion and a second conductive portion are provided on the wiring board and on the first wiring electrode and the second wiring electrode, respectively. A semiconductor chip mounted on the second insulating layer via the first conductive portion and the second conductive portion, A semiconductor device equipped with the following features.