Logical operation element, logic device, not logic device, switchable not logic device, xor logic device, and logic device, or logic device, and half adder

Abstract

A logical operation element 1A includes: a one-dimensional thin line structure 10 in which an electron spin wave propagates; and a gate electrode 20A along a part of the one-dimensional thin line structure 10. A logic input to the logical operation element 1A is a phase state of the electron spin wave before propagating through the one-dimensional thin line structure 10. A logic output of the logical operation element 1A is a phase state of the electron spin wave after propagating through the one-dimensional thin line structure 10.

Description

Logic operation element, logic device, NOT logic device, switchable NOT logic device, XOR logic device, AND logic device, OR logic device and half adder

[0001] The present invention relates to logic operation elements, logic devices, NOT logic devices, switchable NOT logic devices, XOR logic devices, AND logic devices, OR logic devices and half adders.

[0002] Majority logic operation elements using electron spin waves generated by the sustained spin precession of free electrons due to an effective magnetic field are known, and a majority logic device using spin polarization information of persistent spin helix (PSH) generated in a two-dimensional electron gas has been disclosed (e.g., Patent Document 1). Also, a technology has been disclosed in which, in a quantum well wire structure, the persistent spin helix and the inverse persistent spin helix (iPSH) of electron spin waves are switched by a gate voltage (e.g., Non-Patent Document 1).

[0003] Special Publication 2015-518267

[0004] “Gate-controlled switching between persistent and inverse persistent spin helix states”, K. Yoshizumi, A. Sasaki, M. Kohda and J. Nitta”, APPLIED PHYSICS LETTERS 108, 132402 (2016)

[0005] Conventionally, optical input signals are converted into electrical signals by photoelectric conversion, and then digitized based on the voltage level for logical operations. However, after photoelectric conversion, it is not possible to perform processing based on the coherence of waves.

[0006] The present invention has been made in view of these problems, and its purpose is to realize a logic device that can perform logical operations based on the voltage level of an optical input signal while maintaining the wave coherence, and can freely perform processes such as majority logic operations based on the logical operations and wave coherence.

[0007] In order to solve the above problem, a logical operation element of one embodiment of the present invention has a one-dimensional thin-wire structure through which electron spin waves propagate and a gate electrode along a part of the one-dimensional thin-wire structure, and the phase state of the electron spin waves before propagating through the one-dimensional thin-wire structure is used as a logical input, and the phase state of the electron spin waves after propagating through the one-dimensional thin-wire structure is used as a logical output.

[0008] In one aspect, in the above-described logical operation element, the one-dimensional thin wire structure may be made of a material that generates electron spin waves having a phase corresponding to the polarization state when irradiated with light having a predetermined polarization state. In this case, the one-dimensional thin wire structure includes a spin wave generator that generates electron spin waves when an optical signal is irradiated to electrons in the one-dimensional thin wire structure, or that receives electron spin waves output from an adjacent one-dimensional thin wire structure, and an output unit that outputs electron spin waves that have propagated through the one-dimensional thin wire structure. In the one-dimensional thin wire structure, a gate electrode unit along the gate electrode is disposed between the spin wave generator and the output unit. The distance between the spin wave generator and the output unit is approximately an integer multiple of the wavelength of the electron spin wave. The length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional thin wire structure is smaller than half the wavelength of the electron spin wave. When the electron spin wave before entering the gate electrode section from the spin wave generating section is in the iPSH state or the PSH state, and when the electron spin wave before entering the gate electrode section from the spin wave generating section is in the iPSH state, a gate voltage can be applied to bring the electron spin wave in the gate electrode section into the PSH state, and when the electron spin wave before entering the gate electrode section from the spin wave generating section is in the PSH state, a gate voltage can be applied to bring the electron spin wave in the gate electrode section into the iPSH state. In other words, this aspect is a NOT logic device consisting of the aforementioned logical operation elements, in which the phase state of the electron spin wave in the spin wave generating section is used as a logical input and the phase state of the electron spin wave in the output section is used as a logical output.

[0009] This NOT logic device has a one-dimensional wire structure and a gate electrode. The one-dimensional wire structure includes a spin wave generator that generates electron spin waves by irradiating electrons with an optical signal or that receives electron spin waves output from an adjacent one-dimensional wire structure, and an output unit that outputs electron spin waves that have propagated through the one-dimensional wire structure. In the latter case, the output unit of the adjacent one-dimensional wire structure also serves as the spin wave generator for the one-dimensional wire structure. The gate electrode is disposed between the spin wave generator and the output unit along the one-dimensional wire structure. The one-dimensional wire structure is made of a material that generates electron spin waves having a phase corresponding to a predetermined polarization state when irradiated with light having this polarization state. The spin wave generator generates electron spin waves by irradiating electrons with an optical signal. The output unit outputs the electron spin waves that have propagated through the one-dimensional wire structure.

[0010] In one aspect, in the above-described logical operation element, the one-dimensional thin wire structure may be made of a material that generates electron spin waves having a phase corresponding to the polarization state when irradiated with light having a predetermined polarization state. The one-dimensional thin wire structure includes a spin wave generator that generates electron spin waves when an optical signal is irradiated to electrons in the one-dimensional thin wire structure, or that receives electron spin waves output from an adjacent one-dimensional thin wire structure, and an output unit that outputs electron spin waves that have propagated through the one-dimensional thin wire structure. In the one-dimensional thin wire structure, a gate electrode unit along the gate electrode is disposed between the spin wave generator and the output unit. The distance between the spin wave generator and the output unit is approximately an integer multiple of the wavelength of the electron spin wave. The length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional thin wire structure is smaller than half the wavelength of the electron spin wave. The electron spin wave before entering the gate electrode section from the spin wave generating section is in an iPSH state or a PSH state, and a switch is provided for switching the voltage applied to the gate electrode between a first gate voltage that puts the electron spin wave into the PSH state and a second gate voltage that puts the electron spin wave into the iPSH state. In other words, this aspect is a switchable NOT logic device that is composed of the aforementioned logical operation element that uses the phase state of the electron spin wave in the spin wave generating section as a logical input and the phase state of the electron spin wave in the output section as a logical output, and that can switch between NOT logic and identity logic by the switch.

[0011] This switchable NOT logic device has a one-dimensional wire structure and a gate electrode. The one-dimensional wire structure includes a spin wave generator and an output section. The gate electrode has a switch that switches the applied gate voltage between a first gate voltage that puts electron spin waves into a PSH state and a second gate voltage that puts them into an iPSH state. When the switch is at the first gate voltage, the switchable NOT logic device is substantially the same as the above-mentioned NOT logic device. On the other hand, when the switch is at the second gate voltage, the switchable NOT logic device outputs from the output section a logical value that is the same as the logical value in the spin wave generator.

[0012] In one aspect, the device may be configured as an XOR logic device having two of the above switchable NOT logic devices. In this case, the two switchable NOT logic devices are connected in series in an upstream and downstream stage. The spin wave generation section of the switchable NOT logic device in the upstream stage serves as the overall spin wave generation section. The output section of the switchable NOT logic device in the upstream stage is shared with the spin wave generation section of the switchable NOT logic device in the downstream stage. The output section of the switchable NOT logic device in the downstream stage serves as the overall output section. Whether the voltage applied to the gate electrodes of the two switchable NOT logic devices is a first gate voltage that puts electron spin waves into a PSH state or a second gate voltage that puts electron spin waves into an iPSH state serves as a logic input, and the phase state of the electron spin waves in the overall output section serves as a logic output.

[0013] This XOR logic device includes a one-dimensional wire structure made of a material that generates electron spin waves having a phase corresponding to the polarization state when irradiated with light having a predetermined polarization state, and first and second gate electrodes capable of applying a first gate voltage that causes the electron spin waves to enter a PSH state or a second gate voltage that causes the electron spin waves to enter an iPSH state to a portion of the one-dimensional wire structure. The one-dimensional wire structure includes a spin wave generator that generates electron spin waves when an optical signal is irradiated to electrons in the one-dimensional wire structure, or that receives electron spin waves output from an adjacent one-dimensional wire structure, and an output unit that outputs electron spin waves that have propagated through the one-dimensional wire structure. The distance between the spin wave generator and the output unit is approximately an integer multiple of the wavelength of the electron spin wave. The lengths of the first gate electrode and the second gate electrode are each approximately an odd-number multiple of half the wavelength of the electron spin wave. The width of the one-dimensional wire structure is smaller than half the wavelength of the electron spin wave. The first gate electrode and the second gate electrode each have a switch for switching an applied gate voltage between the first gate voltage and the second gate voltage, and the first gate electrode and the second gate electrode are arranged in series along the one-dimensional thin wire structure.

[0014] In one aspect, the AND logic device may be configured with two of the above-described switchable NOT logic devices and one one-dimensional wire structure. This AND logic device is configured by connecting three devices in parallel: two switchable NOT logic devices and one one-dimensional wire structure. The two switchable NOT logic devices and the one-dimensional wire structure share a spin wave generating section. The two switchable NOT logic devices and the one-dimensional wire structure share an output section. Whether the voltage applied to the gate electrodes of the two switchable NOT logic devices is a first gate voltage that puts electron spin waves into a PSH state or a second gate voltage that puts electron spin waves into an iPSH state is used as a logic input, and the phase state of the electron spin waves at the output section is used as a logic output.

[0015] This AND logic device is configured by connecting a first switchable NOT logic device, a second switchable NOT logic device, and a one-dimensional thin wire structure in parallel. The first and second switchable NOT logic devices are the switchable NOT logic devices described above. The first switchable NOT logic device, the second switchable NOT logic device, and the one-dimensional thin wire structure have a common spin wave generating section. The first switchable NOT logic device, the second switchable NOT logic device, and the one-dimensional thin wire structure have a common output section.

[0016] In one aspect, the OR logic device may be configured with two of the above switchable NOT logic devices and one of the above NOT logic devices. This OR logic device is configured by connecting three devices in parallel: two switchable NOT logic devices and one NOT logic device. The two switchable NOT logic devices and the one NOT logic device share a spin wave generating section. The two switchable NOT logic devices and the one NOT logic device share an output section. The logic input is determined by whether the voltage applied to the gate electrodes of the two switchable NOT logic devices is a first gate voltage that puts electron spin waves into a PSH state or a second gate voltage that puts electron spin waves into an iPSH state, and the logic output is determined by the phase state of the electron spin waves at the output section.

[0017] The OR logic device is configured by connecting a first switchable NOT logic device, a second switchable NOT logic device, and a NOT logic device in parallel. The first switchable NOT logic device and the second switchable NOT logic device are the switchable NOT logic device described above. The NOT logic device is the NOT logic device described above. The first switchable NOT logic device, the second switchable NOT logic device, and the NOT logic device share a spin wave generating section in common. The first switchable NOT logic device, the second switchable NOT logic device, and the NOT logic device share an output section in common.

[0018] In one aspect, the logic operation element may be configured as a half adder including the above-mentioned AND logic device and the above-mentioned XOR logic device. This half adder is configured by connecting the AND logic device and the XOR logic device in parallel. The spin wave generating section of the AND logic device and the XOR logic device are common. The output sections of the AND logic device and the XOR logic device are separate. The phase state of the electron spin wave at the output section of the AND logic device is the most significant bit output of a 2-bit binary number, with the voltage applied to the gate electrodes of the two switchable NOT logic devices of the AND logic device being a first gate voltage that puts the electron spin wave in the PSH state or a second gate voltage that puts the electron spin wave in the iPSH state being used as a 1-bit binary input to be added. The phase state of the electron spin wave at the output of the XOR logic device is the lower bit output of the 2-bit binary number, with the 1-bit binary input being added depending on whether the voltage applied to the gate electrodes of the two switchable NOT logic devices of the XOR logic device is the first gate voltage or the second gate voltage.

[0019] That is, the logic operation element of this aspect is a half adder. This half adder is configured by connecting a first AND logic device and a second XOR logic device in parallel. The first AND logic device is the aforementioned AND logic device. The second XOR logic device is the aforementioned XOR logic device. The phase state of the electron spin wave output from the output part of the first AND logic device represents the upper bit of a 2-bit binary number. The phase state of the electron spin wave output from the output part of the second XOR logic device represents the lower bit of the 2-bit binary number.

[0020] Yet another aspect of the present invention is a logical operation element that has a one-dimensional wire structure through which electron spin waves propagate and a gate electrode that extends along a part of the one-dimensional wire structure, with the level of a gate voltage applied to the gate electrode serving as a logical input and the phase state of the electron spin waves serving as a logical output.

[0021] In one embodiment of the logical operation element, the one-dimensional wire structure is made of a material that generates electron spin waves having a phase corresponding to the polarization state when irradiated with light having a predetermined polarization state. The one-dimensional wire structure includes a spin wave generator that generates electron spin waves when an optical signal is irradiated to electrons in the one-dimensional wire structure, or that receives electron spin waves output from an adjacent one-dimensional wire structure, and an output unit that outputs electron spin waves that have propagated through the one-dimensional wire structure. In the one-dimensional wire structure, a gate electrode unit along the gate electrode is disposed between the spin wave generator and the output unit. The distance between the spin wave generator and the output unit is approximately an integer multiple of half the wavelength of the electron spin wave. The length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional wire structure is smaller than half the wavelength of the electron spin wave. The electron spin wave before entering the gate electrode section from the spin wave generating section is in the iPSH state or the PSH state, and the gate electrode can apply a first gate voltage that puts the electron spin wave into the PSH state and a second gate voltage that puts the electron spin wave into the iPSH state.

[0022] In one embodiment of the logic operation element, the one-dimensional wire structure is made of a material that generates electron spin waves having a phase corresponding to the polarization state when irradiated with light having a predetermined polarization state. The gate electrodes are composed of a first gate electrode and a second gate electrode. The one-dimensional wire structure includes a spin wave generator that generates electron spin waves when an optical signal is irradiated to electrons in the one-dimensional wire structure or that receives electron spin waves output from an adjacent one-dimensional wire structure, and an output unit that outputs electron spin waves that have propagated through the one-dimensional wire structure. In the one-dimensional wire structure, a first gate electrode section along the first gate electrode and a second gate electrode section along the second gate electrode are arranged in series between the spin wave generator and the output unit. The distance between the spin wave generator and the output unit is approximately an integer multiple of half the wavelength of the electron spin wave. The lengths of the first gate electrode and the second gate electrode are each approximately an odd-number multiple of half the wavelength of the electron spin wave. The distance between the first gate electrode and the second gate electrode is approximately an integer multiple of the wavelength of the electron spin wave. The width of the one-dimensional wire structure is smaller than half the wavelength of the electron spin wave. The electron spin wave before entering the first gate electrode section from the spin wave generating section is in the iPSH state or the PSH state, and the first gate electrode and the second gate electrode can respectively apply a first gate voltage that puts the electron spin wave into the PSH state and a second gate voltage that puts the electron spin wave into the iPSH state.

[0023] Yet another aspect of the present invention is a logic device. This logic device includes the aforementioned logical operation element and a majority logic element that receives the phase states of multiple electron spin waves as a logic input and receives the phase state of an electron spin wave obtained by superposing multiple electron spin waves as a logic output. The majority logic element has a one-dimensional wire structure through which electron spin waves propagate, a two-dimensional wire structure including a branch point where the one-dimensional wire structure branches into two or more branched wires, and a junction point where the two or more branched wires join together to form a single one-dimensional wire structure.

[0024] In one embodiment of the logic device, the one-dimensional wire structure may be made of a material that generates electron spin waves having a phase corresponding to the polarization state when irradiated with light having a predetermined polarization state. At the branch point, the one-dimensional wire structure branches into three branch wires, a first branch wire, a second branch wire, and a third branch wire, and at the junction point, the three branch wires merge to form a single one-dimensional wire structure. The one-dimensional wire structure has a first logic operation element consisting of a portion of the first branch wire and a first gate electrode along that portion, and a second logic operation element consisting of a portion of the second branch wire and a second gate electrode along that portion. The two-dimensional wire structure includes a spin wave generation unit that generates electron spin waves by irradiating electrons in the two-dimensional wire structure with an optical signal at or before the branch point, or that receives as input an electron spin wave output from an adjacent one-dimensional wire structure, and an output unit that outputs an electron spin wave obtained by superimposing electron spin waves propagated through the first to third branch wires at or after the junction point. The distance between the spin wave generating unit and the output unit is approximately an integer multiple of half the wavelength of the electron spin wave. A first gate electrode unit is arranged along the first gate electrode in the first branch thin wire. A second gate electrode unit is arranged along the second gate electrode in the second branch thin wire. The lengths of the first and second gate electrodes are approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional thin wire structure is smaller than half the wavelength of the electron spin wave. The electron spin wave before entering the first gate electrode unit and the second gate electrode unit from the spin wave generating unit is in an iPSH state or a PSH state, and a first gate voltage that puts the electron spin wave into a PSH state and a second gate voltage that puts the electron spin wave into an iPSH state can be applied to the first gate electrode and the second gate electrode, respectively.

[0025] In one embodiment of the logic device, the one-dimensional wire structure may be made of a material that generates electron spin waves having a phase corresponding to a predetermined polarization state when irradiated with light having a predetermined polarization state. At the branch point, the one-dimensional wire structure branches into three branch wires, namely, a first branch wire, a second branch wire, and a third branch wire, and at the junction point, the three branch wires join to form a single one-dimensional wire structure. The one-dimensional wire structure has a first logic operation element consisting of a portion of the first branch wire and a first gate electrode along the portion, a second logic operation element consisting of a portion of the second branch wire and a second gate electrode along the portion, and a third gate electrode along the portion of the third branch wire. The two-dimensional wire structure includes a spin wave generator that generates electron spin waves by irradiating an optical signal on electrons in the two-dimensional wire structure at or before the branch point, or that receives an electron spin wave output from an adjacent one-dimensional wire structure, and an output unit that outputs an electron spin wave obtained by superimposing electron spin waves propagating through the first to third branch wires at or before the junction. The distance between the spin wave generator and the output unit is approximately an integer multiple of half the wavelength of the electron spin wave. In the first branch wire, a first gate electrode unit is arranged along the first gate electrode. In the second branch wire, a second gate electrode unit is arranged along the second gate electrode. In the third branch wire, a third gate electrode unit is arranged along the third gate electrode. The lengths of the first, second, and third gate electrodes are approximately odd multiples of half the wavelength of the electron spin wave. The width of the one-dimensional wire structure is smaller than half the wavelength of the electron spin wave. The electron spin waves before entering the first gate electrode section, the second gate electrode section, and the third gate electrode section from the spin wave generating section are in an iPSH state or a PSH state, and the first gate electrode, the second gate electrode, and the third gate electrode can be applied with a first gate voltage that puts the electron spin waves into a PSH state and a second gate voltage that puts the electron spin waves into an iPSH state, respectively.

[0026] In one embodiment of the logic device, the one-dimensional thin wire structure may be made of a material that generates electron spin waves having a phase corresponding to the polarization state when irradiated with light having a predetermined polarization state. At the branch point, the one-dimensional thin wire structure branches to form four branch thin wires, namely, a first branch thin wire, a second branch thin wire, a third branch thin wire, and a fourth branch thin wire, and at the junction point, the three branch thin wires, namely, the first branch thin wire, the second branch thin wire, and the third branch thin wire, merge to form a single one-dimensional thin wire structure, and the fourth branch thin wire forms a one-dimensional thin wire structure that does not merge with the other branch thin wires. The logic device may have a first logic operation element including a part of the first branch thin wire and a first gate electrode along the part, a second logic operation element including a part of the second branch thin wire and a second gate electrode along the part, a third logic operation element including a part of the fourth branch thin wire and a third gate electrode along the part, and a fourth logic operation element including another part of the fourth branch thin wire and a fourth gate electrode along the another part. The two-dimensional wire structure includes a spin wave generator that generates electron spin waves by irradiating an optical signal on electrons in the two-dimensional wire structure at or before the branch point, or that receives as input an electron spin wave output from an adjacent one-dimensional wire structure. The two-dimensional wire structure also includes a first output unit that outputs an electron spin wave obtained by superimposing electron spin waves propagated through the first to third branch wires at or after the junction point, and a second output unit that outputs an electron spin wave propagated through the fourth branch wire. The distance between the spin wave generator and the first output unit, and the distance between the spin wave generator and the second output unit, are approximately integer multiples of the wavelength of the electron spin wave. In the first branch wire, a first gate electrode unit is arranged along the first gate electrode. In the second branch wire, a second gate electrode unit is arranged along the second gate electrode. In the fourth branch wire, a third gate electrode unit is arranged along the third gate electrode and a fourth gate electrode unit is arranged along the fourth gate electrode, in series. The length of the gate electrodes is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional wire structure is smaller than half the wavelength of the electron spin wave.The electron spin waves before entering the first gate electrode section, the second gate electrode section, and the third gate electrode section from the spin wave generating section are in an iPSH state or a PSH state, and the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode can be applied with a first gate voltage that puts the electron spin waves into a PSH state and a second gate voltage that puts the electron spin waves into an iPSH state, respectively.

[0027] In one embodiment, the one-dimensional wire structure may be made of a material that generates electron spin waves having a phase corresponding to the polarization state when irradiated with light having a predetermined polarization state. The gate electrode is capable of applying a first gate voltage that causes only the Rashba interaction to act as the spin-orbit interaction on electrons in the one-dimensional wire structure, and a second gate voltage that causes no interaction. The one-dimensional wire structure includes a spin wave generator that generates electron spin waves when an optical signal is irradiated to electrons in the one-dimensional wire structure, or that receives electron spin waves output from an adjacent one-dimensional wire structure, and an output unit that outputs electron spin waves that have propagated through the one-dimensional wire structure. The gate electrode is disposed between the spin wave generator and the output unit along the one-dimensional wire structure. The distance between the spin wave generator and the output unit is approximately an integer multiple of the wavelength of the electron spin wave, and the length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional wire structure is smaller than half the wavelength of the electron spin wave. In other words, this aspect is a switchable NOT logic device that is composed of the aforementioned logical operation element, which uses the phase state of the electron spin wave of the spin wave generating section as a logical input and the phase state of the electron spin wave of the output section as a logical output, and is capable of switching between NOT logic and identity logic.

[0028] In one embodiment of the logical operation element, the one-dimensional wire structure may be made of a material that generates electron spin waves having a phase corresponding to the polarization state when irradiated with light having a predetermined polarization state. The one-dimensional wire structure includes a spin wave generator that generates electron spin waves when an optical signal is irradiated to electrons in the one-dimensional wire structure, or that receives electron spin waves output from an adjacent one-dimensional wire structure, and an output unit that outputs electron spin waves that have propagated through the one-dimensional wire structure. In the one-dimensional wire structure, a gate electrode unit along the gate electrode is disposed between the spin wave generator and the output unit. The distance between the spin wave generator and the output unit is approximately an integer multiple of half the wavelength of the electron spin wave. The length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional wire structure is smaller than half the wavelength of the electron spin wave. The electron spin wave before entering the gate electrode section from the spin wave generating section is in a state in which only the Rashba interaction acts as a spin-orbit interaction, and the gate electrode can apply a first gate voltage that puts the electron spin wave in a state in which only the Rashba interaction acts as a spin-orbit interaction, and a second gate voltage that puts the electron spin wave in a state in which no spin-orbit interaction acts.

[0029] Any combination of the above components, and conversion of the present disclosure into a method, device, system, recording medium, computer program, etc., are also valid aspects of the present disclosure.

[0030] According to the present invention, by making it possible to perform logical operations based on the voltage level of an optical input signal while maintaining the wave coherence, it is possible to freely perform processing such as majority logic operations based on the logical operations and the wave coherence.

[0031] 1 is a schematic diagram of a logic operation element according to a first embodiment; FIG. 2 is a schematic diagram of a NOT logic device according to a second embodiment; FIG. 3 is a schematic diagram showing electrons propagating through the NOT logic device of FIG. 2; FIG. 4 is a schematic diagram of a switchable NOT logic device according to a third embodiment, which is a graph showing the relationship between the width of a one-dimensional thin wire structure and the relaxation time of electron spin; FIG. 5 is a schematic diagram of an XOR logic device according to a fourth embodiment; FIG. 6 is a schematic diagram of an AND logic device according to a fifth embodiment; FIG. 7 is a schematic diagram of an OR logic device according to a sixth embodiment; FIG. 8 is a schematic diagram of a half adder according to a seventh embodiment; FIG. 9 is a schematic diagram of a logic operation element according to an eighth embodiment; FIG. 10 is a schematic diagram of a logic operation element according to a tenth embodiment; FIG. 11 is a schematic diagram of a logic device according to a twelfth embodiment; FIG. 12 is a schematic diagram of a logic device according to a thirteenth embodiment; and FIG. 13 is a schematic diagram of a logic device according to a fourteenth embodiment.

[0032] The present invention will be described below based on preferred embodiments with reference to the drawings. The embodiments are illustrative and do not limit the invention. Not all features or combinations thereof described in the embodiments are necessarily essential to the invention. Identical or equivalent components, parts, and processes shown in each drawing are designated by the same reference numerals, and redundant description will be omitted where appropriate. Furthermore, the scale and shape of each part shown in each drawing are set for convenience to facilitate explanation and should not be interpreted as limiting unless otherwise specified. When terms such as "first" and "second" are used in this specification or claims, unless otherwise specified, these terms do not indicate any order or importance, but are intended only to distinguish one configuration from another. Furthermore, in each drawing, some components that are not important for explaining the embodiments are omitted.

[0033] Before describing specific embodiments, the basic knowledge will be explained.

[0034] In a one-dimensional wire structure formed from semiconductor quantum wells, electron spin waves with a defined phase state can be generated by irradiating polarized light onto electrons in the one-dimensional wire structure. Furthermore, electron spin waves with a defined phase state can be input from an adjacent one-dimensional wire structure. The generated or input electron spin waves propagate within the one-dimensional wire structure. The electron spin waves can take the following states depending on the type and magnitude of the spin-orbit interaction acting on them:

[0035] The PSH (persistent spin gyration) state is realized when the strength α of the Rashba spin-orbit interaction and the strength β of the Dresselhaus spin-orbit interaction are equal (α = β). At this time, the direction of the effective magnetic field created by the spin-orbit interaction is constant regardless of the direction of electron movement. Therefore, the spin precession is not affected by electron scattering, resulting in a state in which spin relaxation is suppressed. Specifically, when the crystal orientation in the quantization axis direction is the [0 0 1] axis, coherent spin rotation continues in the [1 -1 0] direction of the crystal, and in the [1 1 0] direction perpendicular to this, a state in which spin relaxation is suppressed, in which the spin direction propagates without rotating, is reached. Furthermore, when the crystal orientation in the quantization axis direction is the [1 0 -1 0] axis, coherent rotation of spins persists in the [0 0 0 1] direction of the crystal, and in the [1 1 2 0] direction perpendicular to this, spin relaxation is suppressed, in which the spin direction propagates without rotating.

[0036] The iPSH (inverse persistent spin gyration) state is realized when the sign of the strength of the Rashba spin-orbit interaction is reversed and becomes equal to the strength of the Dresselhaus spin-orbit interaction (α = -β). In this iPSH state, the direction of the effective magnetic field changes by 90 degrees relative to the PSH state, and the spin precession state changes to a state in which spin precession does not occur. Specifically, when the crystal orientation in the quantization axis direction is the [0 0 1] axis, the spin direction propagates without rotation in the [1 -1 0] direction of the crystal, and coherent spin rotation is sustained in the [1 1 0] direction perpendicular to this. Furthermore, when the crystal orientation in the quantization axis direction is the [1 0 -1 0] axis, the spin direction propagates without rotation in the [0 0 0 1] direction of the crystal, and coherent spin rotation is sustained in the [1 1 2 0] direction perpendicular to this.

[0037] Other characteristic states include a state in which only the Rashba spin-orbit interaction acts as the spin-orbit interaction (α≠0, β=0), and a state in which there is no spin-orbit interaction (α=0, β=0).

[0038] Here, the strength β of the Dresselhaus spin-orbit interaction is an intrinsic value determined by the material, while the strength α of the Rashba spin-orbit interaction is a value that varies depending on the carrier concentration. The carrier concentration can be controlled by the amount of impurity doped into the one-dimensional wire structure, or it can be continuously changed by providing a gate electrode in part of the one-dimensional wire structure and applying a voltage to the gate electrode. Therefore, by providing a gate electrode in part of the one-dimensional wire structure, the α of the area other than the area along the gate electrode can be set to a different value from the α of the gate electrode area.

[0039] By using the modulation of α by applying the gate voltage, the phase of the electron spin wave can be rotated in a one-dimensional thin-wire structure in a region other than the gate electrode, and the phase rotation of the electron spin wave can be stopped in the gate electrode. Three examples of this are shown below.

[0040] The first aspect is a one-dimensional wire structure in which the portions other than the gate electrode portion are in the iPSH state and the gate electrode portion is in the PSH state. In this case, a quantum well having a one-dimensional wire structure through which electrons propagate is configured such that the [1 1 0] or [0 0 0 1] direction of the crystal is the long axis (x-axis) direction, and the [1 -1 0] or [1 1 2 0] direction is the y-axis direction perpendicular to the x-axis. When the one-dimensional wire structure is in the PSH state, electrons propagate without rotating their spin direction. On the other hand, when the one-dimensional wire structure is in the iPSH state, electrons propagate while maintaining coherent spin rotation. By applying a gate voltage such that α = β to the gate electrode portion, the iPSH state other than the gate electrode portion can be converted to the PSH state. This allows the rotation of the spin direction of electrons propagating through the one-dimensional wire structure to be controlled.

[0041] The second aspect is a one-dimensional wire structure in which the portions other than the gate electrode portion are in the PSH state and the gate electrode portion is in the iPSH state. In this case, the [1 -1 0] direction or [1 1 2 0] direction of the crystal is taken as the long axis (x-axis) direction, and the [1 1 0] direction or [0 0 0 1] direction is taken as the y-axis direction perpendicular to the x-axis. When the one-dimensional wire structure is in the iPSH state, electrons propagate without rotating their spin direction. On the other hand, when the one-dimensional wire structure is in the PSH state, electrons propagate while maintaining coherent spin rotation. By applying a gate voltage such that α = -β to the gate electrode portion, the PSH state other than the gate electrode portion can be converted to the iPSH state. In the above two aspects, the distance refers to the distance projected in the x-direction.

[0042] The third aspect is a one-dimensional wire structure in which β = 0, where only the Rashba spin-orbit interaction is active in areas other than the gate electrode portion, and the gate electrode portion is in a state where no spin-orbit interaction is active. In this case, the long axis (x-axis) can be determined regardless of the crystal orientation, and the y-axis can be set perpendicular to the x-axis. When the one-dimensional wire structure is in a state where no spin-orbit interaction is active, electrons propagate without rotating their spin direction. On the other hand, when the one-dimensional wire structure is in a state where only the Rashba spin-orbit interaction is active, electrons propagate while maintaining coherent spin rotation. By applying a gate voltage such that α = 0 to the gate electrode portion, the state where only the Rashba spin-orbit interaction is active in areas other than the gate electrode portion can be converted to a state where no spin-orbit interaction is active. In this aspect, the distance refers to the distance on the xy plane.

[0043] These aspects make it possible to control the rotation of the spin direction of electrons propagating through the one-dimensional nanowire structure. In particular, when the length of the gate electrode is set to half the wavelength of the electron spin wave, the phase can be shifted by 180° by stopping the rotation for half the wavelength, and the device can be used as a NOT logic element. In the following embodiments, the first aspect will be mainly described, but the second aspect can also be applied by switching the PSH state and the iPSH state.

[0044] Such a one-dimensional wire structure can be fabricated as follows (see, for example, Non-Patent Document 1). Specifically, in the example of Non-Patent Document 1, an InAlAs / InGaAs / InAlAs quantum well structure is epitaxially grown on an InP substrate using metalorganic chemical vapor deposition (MOCVD), and then a one-dimensional wire structure in the [1 1 0] direction is fabricated by photolithography and etching. The films are stacked in the following order starting from the InP substrate: 200 nm In ０．５２ Al ０．４８ As 6nm In ０．５２ Al ０．４８ As (1.2 × 10 １８ cm －３ Si doping) 6 nm In ０．５２ Al ０．４８ As 7nm In ０．５３ Ga ０．４７As quantum well 6nm In ０．５２ Al ０．４８ As 6nm In ０．５２ Al ０．４８ As (3.2 × 10 １８ cm －３ Si doping) 10 nm In ０．５２ Al ０．４８ As where the gate insulating layer (5 nm Al ２ O ３ / 95nm HfO ２ ), and a gate electrode (10 nm Cr / 100 nm Au) is used.

[0045] For example, Non-Patent Document 1 discloses the results of simulating the states from α = -2β to α = 2β in the one-dimensional thin wire structure. The carrier concentrations in the iPSH state (α = -β), the state where the Rashba spin-orbit interaction is 0 (α = 0), and the PSH state (α = β) are 1.23, 1.38, and 1.54 (× 10 １６ m －２ The gate voltage that realizes these carrier concentrations is, for example, in the range of −0.5 to −1.0 V.

[0046] The first to third embodiments described below are all logic operation elements whose logic inputs and logic outputs are the phase states of electron spin waves, and further, logic switching is performed depending on the embodiment by switching the gate voltage applied to the gate electrode.Furthermore, the fourth to seventh embodiments are logic devices formed by combining the logic operation elements described in the second and / or third embodiments.

[0047] 1 is a schematic diagram of a logic operation element 1A according to a first embodiment. The [1 1 0] direction of the crystal is taken as the long axis (x-axis) direction, and the [1 -1 0] direction is taken as the y-axis direction perpendicular to the x-axis (the same applies below). The logic operation element 1A has a one-dimensional thin-wire structure 10 and a gate electrode 20A.

[0048] The one-dimensional wire structure 10 is set so that α = -β when no voltage is applied. The voltage applied to the gate electrode 20A is a gate voltage value such that α = β. When the applied voltage is near this gate voltage, the electron spin waves in the one-dimensional wire structure 10 are converted from the iPSH state to the PSH state. Conversely, when the applied voltage is a gate voltage value such that α = -β (or when no voltage is applied), the iPSH state of the electrons in the one-dimensional wire structure 10 is maintained as is.

[0049] First, electrons with a specific phase state are input to the left end of the one-dimensional wire structure 10. The phase state at this time corresponds to the logic input. The electron spin waves of the input electrons propagate through the one-dimensional wire structure 10 from left to right in the x direction, and are then extracted at the right end. The phase state at this time corresponds to the logic output.

[0050] Hereinafter, for simplicity, "electron spin waves propagating through region R are in the iPSH state" will be expressed as "region R is in the iPSH state," etc. Assume that a gate voltage that causes the region to enter the PSH state is applied to gate electrode 20A. In this case, regions R1 and R3 of one-dimensional wire structure 10 are not directly below gate electrode 20A, so the gate voltage is not applied. On the other hand, region R2 is directly below gate electrode 20A, so the gate voltage is applied. In this case, for example, if region R1 is in the iPSH state, region R2 is converted to the PSH state, and region R3 returns to the iPSH state. Electron spin waves propagating from left to right in the x-direction through one-dimensional wire structure 10 are extracted at the right end, and their phase state is used as a logic output.

[0051] Next, assume that a voltage that induces the iPSH state is applied to gate electrode 20A (or that no voltage is applied). In this case, no gate voltage that induces the PSH state is applied to any of regions R1, R2, and R3 of one-dimensional wire structure 10. At this time, the iPSH state remains unchanged in all regions (R1, R2, and R3). Electron spin waves propagating from left to right in the x-direction through one-dimensional wire structure 10 are extracted at the right end. The phase state at this time (which is generally different from the state when a gate voltage that induces the PSH state is applied to gate electrode 20A) is used as the logic output.

[0052] Thus, according to this embodiment, by appropriately setting the lengths of the one-dimensional wire structure 10 and the gate electrode 20A and using the phase state of the electron spin wave before propagating through the one-dimensional wire structure 10 as the logical input, it is possible to construct a logical operation element that can output various logical outputs.

[0053] 2 is a schematic diagram of a NOT logic device 1 according to a second embodiment. The NOT logic device 1 includes a one-dimensional wire structure 10 and a gate electrode 20. The one-dimensional wire structure 10 includes a spin wave generator 30 that generates electron spin waves by irradiating electrons with an optical signal or that receives electron spin waves output from an adjacent one-dimensional wire structure, and an output unit 40 that outputs electron spin waves that have propagated through the one-dimensional wire structure 10. In the latter case, the output unit of the adjacent one-dimensional wire structure doubles as the spin wave generator 30 of the one-dimensional wire structure 10. The gate electrode 20 is disposed between the spin wave generator 30 and the output unit 40 along the one-dimensional wire structure 10.

[0054] The one-dimensional wire structure 10 is made of a material that generates electron spin waves having a phase corresponding to a predetermined polarization state when irradiated with light. The spin wave generator 30 irradiates electrons with an optical signal to generate electron spin waves. The output unit 40 outputs the electron spin waves that have propagated through the one-dimensional wire structure 10. The phase state of the output electron spin waves can be detected, for example, by a magnetoresistive element (MR element) installed near the output unit 40.

[0055] For example, the polarization state of the irradiated light may be either right-handed circularly polarized light or left-handed circularly polarized light. When such light is irradiated onto the spin wave generation unit 30, the spin wave generation unit 30 generates an electron spin wave with a phase of 0 for right-handed circularly polarized light and an electron spin wave with a phase of π for left-handed circularly polarized light. Hereinafter, an electron spin wave with a phase of 0 will be associated with a logical value of "0," and an electron spin wave with a phase of π will be associated with a logical value of "1." Therefore, in this case, right-handed circularly polarized light of the irradiated light corresponds to a logical value of 0, and left-handed circularly polarized light corresponds to a logical value of 1.

[0056] The gate electrode 20 converts electrons in the one-dimensional wire structure 10 from the iPSH state to the PSH state by applying a gate voltage to a portion of the one-dimensional wire structure 10 that converts electron spin waves into the PSH state. In the example of FIG. 2 , the distance L1 between the spin wave generator 30 and the output section 40 is approximately an integer multiple of the wavelength of the electron spin waves propagating through the one-dimensional wire structure 10. Regions R1 and R3 of the one-dimensional wire structure 10 are not directly below the gate electrode 20, so no gate voltage is applied. On the other hand, region R2 is directly below the gate electrode 20, so a gate voltage is applied. At this time, for example, if the electron spin waves in region R1 are in the iPSH state, they are converted to the PSH state in region R2 and then return to the iPSH state in region R3.

[0057] The distance L1 between the spin wave generating section 30 and the output section 40 is approximately an integer multiple of the wavelength of the electron spin wave propagating in the one-dimensional wire structure 10. The length L2 of the gate electrode 20 is approximately an odd multiple of half the wavelength of the electron spin wave. The width W1 of the one-dimensional wire structure is smaller than half the wavelength of the electron spin wave.

[0058] 3 is a schematic diagram showing the state of electrons propagating through the NOT logic device 1 of FIG. 2. First, right-handed circularly polarized light is irradiated onto the spin-wave generating unit 30. The spin-wave generating unit 30 generates electron spin waves (upward) with a phase of 0. In region R1, the electron spin waves in the one-dimensional wire structure 10 are in the iPSH state (α = -β). Therefore, in region R1, electrons propagate while maintaining coherent spin rotation.

[0059] In region R2, the one-dimensional wire structure 10 is located directly below the gate electrode 20 to which a gate voltage is applied, and is therefore in a PSH state (α = β). Therefore, in region R2, electrons propagate without rotating in the direction of their spin. At this time, since the length of region R2 (the length of gate electrode 20) is approximately an odd multiple of half the wavelength of the electron spin wave, the phase of the electron spin wave is shifted by approximately π (approximately half the wavelength) compared to when no gate voltage is applied.

[0060] In region R3, the one-dimensional wire structure 10 is in an iPSH state because it is not directly under the gate electrode 20 to which a gate voltage is applied. Therefore, in region R3, electrons propagate while maintaining coherent spin rotation.

[0061] Since the distance between the spin wave generating unit 30 and the output unit 40 is approximately an integer multiple of the wavelength of the electron spin wave and the phase of the electron spin wave is shifted by π in region R2, it can be seen that the phase state of the electron spin wave output by the output unit 40 is the opposite of the state in the spin wave generating unit 30 (in other words, the phase is shifted by π). In other words, electrons that were in a state corresponding to a logical value of 0 in the spin wave generating unit 30 are in a state corresponding to a logical value of 1 in the output unit 40. In this way, when a logical value of 0 is input to the NOT logic device 1, the opposite logical value of 1 is output.

[0062] Conversely, consider the case where left-handed circularly polarized light is irradiated onto the spin wave generating unit 30 to generate electron spin waves (downward) with a phase of π. In this case, electrons that were in a state corresponding to a logical value of 1 in the spin wave generating unit 30 become in a state corresponding to a logical value of 0 in the output unit 40. Therefore, when a logical value of 1 is input to the NOT logic device 1, the opposite logical value of 0 is output.

[0063] As described above, the NOT logic device 1 realizes a NOT circuit (also called a NOT gate or an inverter) that realizes NOT logic without losing wave properties.

[0064] Figure 4 is a graph showing the relationship between the width of the one-dimensional wire structure and the relaxation time of the electron spin wave. The square dots in Figure 4 represent the case where the crystal orientation is [1 1 0], and the round dots represent the case where the crystal orientation is [1 -1 0]. In the above example, the wavelength of the electron spin wave is approximately 8 μm. As can be seen from Figure 4, by making the width of the one-dimensional wire structure less than half the wavelength, the time until the spin polarization state relaxes can be maintained at 1 ns or more.

[0065] As described above, according to this embodiment, it is possible to realize a logic device that can perform NOT operation processing on an optical input signal while maintaining the coherence of the wave.

[0066] 5 is a schematic diagram of a switchable NOT logic device 2 according to a third embodiment. The switchable NOT logic device 2 has a one-dimensional wire structure 10 and a gate electrode 20. The one-dimensional wire structure 10 includes a spin wave generator 30 and an output section 40. The gate electrode 20 of the switchable NOT logic device 2 has a switch 20S that switches the applied gate voltage between a first gate voltage that puts electron spin waves into a PSH state and a second gate voltage that puts them into an iPSH state. The other configuration of the switchable NOT logic device 2 is the same as the configuration of the NOT logic device 1 in FIG. 2.

[0067] When switch 20S is at the first gate voltage (hereinafter also referred to as "switch 20S is ON"; the same applies to other symbols for "20S"), switchable NOT logic device 2 is substantially the same as NOT logic device 1. Therefore, it functions as a logic device that can perform NOT operation processing on an optical input signal while maintaining wave coherence.

[0068] On the other hand, when the switch 20S is at the second gate voltage (hereinafter also referred to as "switch 20S is OFF"; the same applies to other symbols for "20S"), the switchable NOT logic device 2 outputs from the output section 40 a logical value that is the same as the logical value in the spin wave generating section 30. Therefore, in this case, the switchable NOT logic device 2 functions as a buffer. In this specification, such a logic device that can be switched between a buffer logic device and a NOT logic device will be called a "switchable NOT logic device".

[0069] As described above, according to this embodiment, it is possible to realize a logic device that can selectively perform NOT operation processing or identity operation processing on an optical input signal depending on the voltage level while maintaining the wave coherence.

[0070] 6 is a schematic diagram of an XOR logic device 3 according to a fourth embodiment. The XOR logic device 3 includes a one-dimensional wire structure 10 made of a material that generates electron spin waves having a phase corresponding to a predetermined polarization state when irradiated with light having a predetermined polarization state, and a first gate electrode 21 and a second gate electrode 22 that can apply, to a portion of the one-dimensional wire structure 10, a first gate voltage that puts the electron spin waves into a PSH state or a second gate voltage that puts the electron spin waves into an iPSH state. The one-dimensional wire structure 10 includes a spin wave generator 30 that generates electron spin waves when an optical signal is irradiated to electrons in the one-dimensional wire structure, or that receives electron spin waves output from an adjacent one-dimensional wire structure as input, and an output unit 40 that outputs the electron spin waves that have propagated through the one-dimensional wire structure 10. The distance L3 between the spin wave generator 30 and the output unit 40 is approximately an integer multiple of the wavelength of the electron spin wave. The length L4 of the first gate electrode 21 and the length L5 of the second gate electrode 22 are each approximately an odd multiple of a half wavelength of the electron spin wave. The width W1 of the one-dimensional wire structure 10 is smaller than the half wavelength of the electron spin wave. The first gate electrode 21 and the second gate electrode 22 have switches 21S and 22S, respectively, that switch the applied gate voltage between a first gate voltage and a second gate voltage. The first gate electrode 21 and the second gate electrode 22 are arranged in series along the one-dimensional wire structure 10.

[0071] Regions R4, R6, and R8 are in the iPSH state. Region R5 is in the PSH state when switch 21S is ON and in the iPSH state when switch 21S is OFF. Region R7 is in the PSH state when switch 22S is ON and in the iPSH state when switch 22S is OFF.

[0072] Hereinafter, a case will be considered in which right-handed circularly polarized light is irradiated onto the spin wave generating unit 30 to generate an electron spin wave (upward) with a phase of 0. The phase state of the electron spin wave output from the output unit 40 according to the ON / OFF states of the switches 21S and 22S will be described.

[0073] (When switch 21S = OFF, switch 22S = OFF) In region R4, electrons propagate while maintaining coherent spin rotation. In region R5, electrons propagate while maintaining coherent spin rotation. In region R6, electrons propagate while maintaining coherent spin rotation. In region R7, electrons propagate while maintaining coherent spin rotation. In region R8, electrons propagate while maintaining coherent spin rotation. Since distance L3 is approximately an integer multiple of the wavelength of the electron spin wave, the phase state of the electron spin wave output from the output unit 40 is approximately the same as the state in the spin wave generation unit 30 (i.e., the phase difference between the spin wave generation unit 30 and the output unit 40 is approximately an integer multiple of 2π). Therefore, an electron spin wave with a phase of 0 (upward) is output from the output unit 40.

[0074] (When switch 21S = OFF, switch 22S = ON) In region R4, electrons propagate while maintaining coherent spin rotation. In region R5, electrons propagate while maintaining coherent spin rotation. In region R6, electrons propagate while maintaining coherent spin rotation. In region R7, electrons propagate without rotating their spin direction. At this time, since the length of region R7 (the length of second gate electrode 22) is approximately an odd multiple of half the wavelength of the electron spin wave, the phase of the electron spin wave is shifted by approximately an odd multiple of π (approximately half the wavelength). In region R8, electrons propagate while maintaining coherent spin rotation. Since the distance L3 is approximately an integer multiple of the wavelength of the electron spin wave and the phase of the electron spin wave is shifted by approximately π in the region R7, the phase state of the electron spin wave output from the output unit 40 is approximately the opposite to that in the spin wave generation unit 30 (i.e., the phase difference between the spin wave generation unit 30 and the output unit 40 is approximately an odd multiple of π). Therefore, an electron spin wave (downward) with a phase of π is output from the output unit 40.

[0075] (When switch 21S = ON, switch 22S = OFF) In region R4, electrons propagate while maintaining coherent spin rotation. In region R5, electrons propagate without rotating their spin direction. At this time, since the length of region R5 (the length of the first gate electrode 21) is approximately an odd multiple of half the wavelength of the electron spin wave, the phase of the electron spin wave is shifted by approximately an odd multiple of π (approximately half the wavelength). In region R6, electrons propagate while maintaining coherent spin rotation. In region R7, electrons propagate while maintaining coherent spin rotation. In region R8, electrons propagate while maintaining coherent spin rotation. Since the distance L3 is approximately an integer multiple of the wavelength of the electron spin wave and the phase of the electron spin wave is shifted by approximately π in the region R5, the phase state of the electron spin wave output from the output unit 40 is approximately the opposite to that in the spin wave generation unit 30 (i.e., the phase difference between the spin wave generation unit 30 and the output unit 40 is approximately an odd multiple of π). Therefore, an electron spin wave (downward) with a phase of π is output from the output unit 40.

[0076] (When switch 21S = ON, switch 22S = ON) In region R4, electrons propagate while maintaining coherent spin rotation. In region R5, electrons propagate without rotating their spin direction. At this time, since the length of region R5 (the length of the first gate electrode 21) is approximately an odd multiple of half the wavelength of the electron spin wave, the phase of the electron spin wave is shifted by approximately an odd multiple of π (approximately a half wavelength). In region R6, electrons propagate while maintaining coherent spin rotation. In region R7, electrons propagate without rotating their spin direction. At this time, since the length of region R7 (the length of the second gate electrode 22) is approximately an odd multiple of half the wavelength of the electron spin wave, the phase of the electron spin wave is shifted by approximately an odd multiple of π (approximately a half wavelength). In region R8, electrons propagate while maintaining coherent spin rotation. Since the distance L3 is approximately an integer multiple of the wavelength of the electron spin wave and the phase of the electron spin wave is shifted by approximately π in regions R5 and R7 (regions R5 and R7 combined are shifted by approximately 2π), the phase state of the electron spin wave output from the output unit 40 is approximately the same as the state in the spin wave generation unit 30 (i.e., the phase difference between the spin wave generation unit 30 and the output unit 40 is approximately an integer multiple of 2π). Therefore, an electron spin wave with a phase of 0 (upward) is output from the output unit 40.

[0077] Here, the ON state of switch 21S corresponds to the logical value of the first input variable = 1, the OFF state of switch 21S corresponds to the logical value of the first input variable = 0, the ON state of switch 22S corresponds to the logical value of the second input variable = 1, and the OFF state of switch 22S corresponds to the logical value of the second input variable = 0. If the state in the spin wave generating unit 30 and the phase state of the electron spin wave output from the output unit 40 are opposite, then this is "true" (logical value = 1), and if the state in the spin wave generating unit 30 and the phase state of the electron spin wave output from the output unit 40 are the same, then this is "false" (logical value = 0), and the truth table is as shown in Table 1.

[0078] Table 1

[0079] In this way, by making the ON / OFF states of the switches 21S and 22S correspond to 1 / 0 of the first variable and the second variable, respectively, an XOR circuit (also called an XOR gate) that realizes XOR logic can be realized. That is, according to this embodiment, a logic device can be realized that can perform an XOR logic operation on an optical input signal based on the voltage level while maintaining wave coherence.

[0080] Fifth Embodiment Fig. 7 is a schematic diagram of an AND logic device 4 according to a fifth embodiment. The AND logic device 4 is configured by connecting a first switchable NOT logic device 201, a second switchable NOT logic device 202, and a third one-dimensional thin-wire structure 703 in parallel. The first switchable NOT logic device 201 and the second switchable NOT logic device 202 are the switchable NOT logic devices described in the third embodiment. The first switchable NOT logic device 201, the second switchable NOT logic device 202, and the third one-dimensional thin-wire structure 703 share a common spin wave generator 31. The first switchable NOT logic device 201, the second switchable NOT logic device 202, and the third one-dimensional thin-wire structure 703 share a common output section 41.

[0081] The electron spin waves generated by the spin wave generator 31 are split into equal amounts in three directions and propagate in the x direction through the first switchable NOT logic device 201, the second switchable NOT logic device 202, and the third one-dimensional wire structure 703. Here, the distances from the spin wave generator 31 to the output unit 41 in the three directions are equal when projected onto the X direction. The electron spin waves propagating through the first switchable NOT logic device 201, the second switchable NOT logic device 202, and the third one-dimensional wire structure 703 are combined at the output unit 41, and majority logic is executed.

[0082] As in the fourth embodiment, right-handed circularly polarized light is irradiated onto the spin wave generation unit 31 to generate an electron spin wave (upward) with a phase of 0. Table 2 shows the output results according to the ON / OFF of the switches 201S and 202S. However, in the output unit 41, the electron spin waves propagated through the first switchable NOT logic device 201, the second switchable NOT logic device 202, and the third one-dimensional thin wire structure 703 are combined, and majority logic is used. As in the fourth embodiment, when the state in the spin wave generation unit 31 and the phase state of the electron spin wave output from the output unit 41 are opposite, the result is considered to be "true" (logical value = 1), and when the state in the spin wave generation unit 31 and the phase state of the electron spin wave output from the output unit 41 are the same, the result is considered to be "false" (logical value = 0).

[0083] Table 2

[0084] In this way, by making the ON / OFF states of the switches 201S and 202S correspond to 1 / 0 of the first and second variables, an AND circuit (also called an AND gate) that realizes AND logic can be realized. That is, according to this embodiment, a logic device can be realized that can perform AND operation processing on an optical input signal based on the voltage level while maintaining wave coherence.

[0085] [Sixth Embodiment] Fig. 8 is a schematic diagram of an OR logic device 5 according to a sixth embodiment. The OR logic device 5 is configured by connecting a first switchable NOT logic device 201, a second switchable NOT logic device 202, and a third NOT logic device 103 in parallel. The first switchable NOT logic device 201 and the second switchable NOT logic device 202 are the switchable NOT logic devices described in the third embodiment. The third NOT logic device 103 is the NOT logic device described in the second embodiment. The first switchable NOT logic device 201, the second switchable NOT logic device 202, and the third NOT logic device 103 share a common spin wave generator 31. The first switchable NOT logic device 201, the second switchable NOT logic device 202, and the third NOT logic device 103 share a common output section 42.

[0086] The electron spin waves generated by the spin wave generation unit 32 are divided into equal amounts in three directions and propagate in the x direction through the first switchable NOT logic device 201, the second switchable NOT logic device 202, and the third NOT logic device 103. Here, in the three directions, the distances from the spin wave generation unit 32 to the output unit 42 are equal when projected onto the X direction. The electron spin waves that have propagated through the first switchable NOT logic device 201, the second switchable NOT logic device 202, and the third NOT logic device 103 are combined at the output unit 42, and majority logic is executed.

[0087] As in the fifth embodiment, right-handed circularly polarized light is irradiated onto the spin wave generation unit 32 to generate an electron spin wave (upward) with a phase of 0. Table 3 shows the output results according to the ON / OFF of the switches 201S and 202S. However, in the output unit 42, the electron spin waves propagating through the first switchable NOT logic device 201, the second switchable NOT logic device 202, and the third NOT logic device 103 are combined, and majority logic is used. As in the fifth embodiment, when the state in the spin wave generation unit 32 and the phase state of the electron spin wave output from the output unit 42 are opposite, the result is considered to be "true" (logical value = 1), and when the state in the spin wave generation unit 32 and the phase state of the electron spin wave output from the output unit 42 are the same, the result is considered to be "false" (logical value = 0).

[0088] Table 3

[0089] In this way, by making the ON / OFF states of switch 201S and switch 202S correspond to 1 / 0 of the first variable and the second variable, an OR circuit (also called an OR gate) that realizes OR logic can be realized. That is, according to this embodiment, a logic device can be realized that can perform OR operation processing on an optical input signal based on the voltage level while maintaining wave coherence.

[0090] 9 is a schematic diagram of a half adder 6 according to a seventh embodiment. The half adder 6 according to the seventh embodiment is configured by connecting a first AND logic device 401 and a second XOR logic device 302 in parallel. The first AND logic device 401 is the AND logic device described in the fifth embodiment. The second XOR logic device 302 is the XOR logic device described in the fourth embodiment. The phase state of the electron spin wave output from the output section 43 of the first AND logic device 401 represents the upper bit of a 2-bit binary number, and the phase state of the electron spin wave output from the output section 44 of the second XOR logic device represents the lower bit of the 2-bit binary number.

[0091] As in the fifth embodiment, right-handed circularly polarized light is irradiated onto the spin wave generation unit 33 to generate an electron spin wave of phase 0 (upward). Table 4 shows the output results according to the ON / OFF of switches 401S and 301S and switches 402S and 302S (the same logical value as 301S is input to switch 401S, and the same logical value as 302S is input to switch 402S). As in the fifth embodiment, when the state in the spin wave generation unit 33 and the phase state of the electron spin waves output from output units 43 and 44 are opposite, the result is "true" (logical value = 1), and when the state in the spin wave generation unit 33 and the phase state of the electron spin waves output from output units 43 and 44 are the same, the result is "false" (logical value = 0).

[0092] Table 4

[0093] The output section 43 of the first AND logic device 401 outputs the most significant bit of the binary sum of a first variable corresponding to the ON / OFF state of the switches 401S and 301S and a second variable corresponding to the ON / OFF state of the switches 402S and 302S. The output section 44 of the second XOR logic device 302 outputs the least significant bit of the binary sum of the first variable corresponding to the ON / OFF state of the switches 401S and 301S and the second variable corresponding to the ON / OFF state of the switches 402S and 302S. In other words, according to this embodiment, a half adder can be realized for an optical input signal while maintaining wave coherence.

[0094] In all of the eighth to thirteenth embodiments described below, the logic input is the level of the gate voltage, and the logic output is the phase of the electron spin wave.

[0095] 10 is a schematic diagram of a logic operation element 7 according to an eighth embodiment. The logic operation element 7 has a one-dimensional wire structure 10 through which electron spin waves propagate, and a gate electrode 23 arranged along the one-dimensional wire structure 10. The [1 1 0] direction of the crystal is taken as the long axis (x-axis) direction, and the [1 -1 0] direction is taken as the y-axis direction perpendicular to the x-axis (the same applies below). The electron spin waves propagating through the one-dimensional wire structure are in an iPSH state.

[0096] The voltage applied to the gate electrode 23 is either a first gate voltage that puts the electron spin wave in the PSH state or a second gate voltage that puts the electron spin wave in the iPSH state. In the latter case, the iPSH state of the electron spin wave in the one-dimensional wire structure 10 is maintained as it is.

[0097] The electron spin wave propagates from left to right in the x-direction through the one-dimensional wire structure 10 and is extracted at the right end. The phase state at this time corresponds to the logic output.

[0098] Assume that a first gate voltage is applied to gate electrode 23. In this case, regions R1 and R3 of one-dimensional wire structure 10 are not directly below gate electrode 23, and therefore no gate voltage is applied to them. On the other hand, region R2 is directly below gate electrode 23, and therefore the first gate voltage is applied to region R2. At this time, for example, if region R1 is in the iPSH state, region R2 is converted to the PSH state, and region R3 returns to the iPSH state again. The electron spin wave propagating from left to right in the x direction through one-dimensional wire structure 10 is extracted at the right end, and its phase state is used as the logic output.

[0099] Next, assume that a second gate voltage is applied to gate electrode 23. In this case, the first gate voltage is not applied to any of regions R1, R2, and R3 of one-dimensional wire structure 10. In this case, the iPSH state remains unchanged in all regions R1, R2, and R3. The electron spin wave propagating from left to right in the x-direction through one-dimensional wire structure 10 is extracted at the right end. The phase state at this time (which is generally different from that when the first gate voltage is applied to gate electrode 23) is used as the logic output.

[0100] Thus, according to this embodiment, by appropriately setting the lengths of the one-dimensional wire structure 10 and the gate electrode 23 and using the level of the voltage applied to the gate electrode 23 (whether it is the first gate voltage or the second gate voltage) as the logical input, it is possible to configure a logical operation element that can output various logical outputs while maintaining the coherence of the waves.

[0101] 11 is a schematic diagram of a logic operation element 8 with one logic input according to a ninth embodiment. The logic operation element 8 has a one-dimensional wire structure 10 and a gate electrode 24. The one-dimensional wire structure 10 includes a spin wave generating section 33 and an output section 45.

[0102] One-dimensional wire structure 10 is made of a material that generates electron spin waves having a phase corresponding to a predetermined polarization state when irradiated with light. Spin wave generator 33 generates electron spin waves by irradiating an optical signal to electrons in one-dimensional wire structure 10, or receives electron spin waves output from an adjacent one-dimensional wire structure as input. Output unit 45 outputs the electron spin waves that have propagated through one-dimensional wire structure 10.

[0103] The gate electrode 24 applies a first gate voltage to a portion of the one-dimensional wire structure 10 such that the electron spin waves are in the PSH state, or a second gate voltage to a portion of the one-dimensional wire structure 10 such that the electron spin waves are in the iPSH state, thereby converting or maintaining the state of the electron spin waves in the one-dimensional wire structure between the PSH state and the iPSH state. In the example of FIG. 11 , the distance L1 between the spin wave generator 33 and the output section 45 is approximately an integer multiple of a half wavelength of the electron spin wave propagating in the one-dimensional wire structure 10. Regions R1 and R3 of the one-dimensional wire structure 10 are not directly under the gate electrode 24, so no gate voltage is applied. On the other hand, region R2 is directly under the gate electrode 24, so a gate voltage is applied. When the second gate voltage is applied, if region R1 is in the iPSH state, region R2 is converted to the PSH state, and region R3 returns to the iPSH state.

[0104] The logic input is the level of the voltage applied to the gate electrode 24. That is, when the voltage applied to the gate electrode 24 is the first gate voltage, it corresponds to an input logic value of "1," and when the voltage applied to the gate electrode 24 is the second gate voltage, it corresponds to an input logic value of "0" (and so on).

[0105] Regarding the phase state of the electron spin wave extracted by the output section 45, an electron spin wave with a phase of 0 corresponds to an output logical value of "0," and an electron spin wave with a phase of π corresponds to an output logical value of "1." Therefore, in this case, right-handed circularly polarized light of the irradiated light corresponds to a logical value of 0, and left-handed circularly polarized light corresponds to a logical value of 1.

[0106] The distance L1 between the spin wave generating unit 33 and the output unit 45 is approximately an integer multiple of the half wavelength of the electron spin wave propagating in the one-dimensional wire structure 10. The length L2 of the gate electrode 24 is approximately an odd multiple of the half wavelength of the electron spin wave. The width W1 of the one-dimensional wire structure is smaller than the half wavelength of the electron spin wave.

[0107] When the input logic value of the gate voltage is 0 with respect to the phase of the input electron spin wave being 0, the electron spin wave continues to progress in the iPSH state. The logic operation element 8 operates differently depending on whether the distance L1 between the spin wave generator 33 and the output unit 45 is an even multiple of a half wavelength (in other words, an integer multiple of the wavelength) or an odd multiple of a half wavelength (in other words, a half-integer multiple of the wavelength). When L1 is an even multiple of a half wavelength (L1 = nλ, n is a natural number, λ is the wavelength (same below)), the phase state of the electron spin wave at the output unit 45 is 0, and the logic operation element 8 becomes an element that performs an identity logic operation. On the other hand, when L1 is an odd multiple of a half wavelength (L1 = (n + 1 / 2)λ), the phase state of the electron spin wave at the output unit 45 is π, and the logic operation element 8 becomes an element that performs a NOT logic operation.

[0108] Next, when the input logic value of the gate voltage is 1 with respect to the phase 0 of the input electron spin wave, the phase does not change during (1 / 2)λ, which is the time it takes for the electron spin wave to convert from the iPSH state to the PSH state. Therefore, when L1 is an even multiple of half the wavelength (L1 = nλ), the phase state of the electron spin wave at the output section 45 becomes π, and the logical operation element 8 becomes an element that performs a NOT logical operation. On the other hand, when L1 is an odd multiple of half the wavelength (L1 = (n + 1 / 2)λ), the phase state of the electron spin wave at the output section 45 becomes 0, and the logical operation element 8 becomes an element that performs an identity logical operation.

[0109] As described above, according to this embodiment, it is possible to configure an identity logic element or a NOT logic element with one logic input while maintaining the coherence of the waves.

[0110] 12 is a schematic diagram of a two-logic-input logic operation element 9 according to a tenth embodiment. The logic operation element 9 includes a one-dimensional wire structure 10 made of a material that generates electron spin waves having a phase corresponding to a predetermined polarization state when irradiated with light, and a first gate electrode 21 and a second gate electrode 22 that convert or maintain the state of the electron spin waves in the one-dimensional wire structure 10 between the PSH state and the iPSH state by applying a first gate voltage that causes the electron spin waves to enter the PSH state or a second gate voltage that causes the electron spin waves to enter the iPSH state to a part of the one-dimensional wire structure 10. The one-dimensional wire structure 10 includes a spin wave generator 30 that generates electron spin waves by irradiating electrons with an optical signal or that receives electron spin waves output from an adjacent one-dimensional wire structure as input, and an output unit 40 that outputs the electron spin waves propagated through the one-dimensional wire structure 10. The distance L3 between the spin wave generating unit 30 and the output unit 40 is approximately an integer multiple of the half wavelength of the electron spin wave. The length L4 of the first gate electrode 21 and the length L5 of the second gate electrode 22 are each approximately an odd multiple of the half wavelength of the electron spin wave. The width W1 of the one-dimensional wire structure 10 is smaller than the half wavelength of the electron spin wave. The first gate electrode 21 and the second gate electrode 22 can switch the applied first gate voltage and second gate voltage between HIGH and LOW, respectively. The first gate electrode 21 and the second gate electrode 22 are arranged in series along the one-dimensional wire structure 10. The distance L6 between the first gate electrode 21 and the second gate electrode 22 is approximately an integer multiple of the wavelength of the electron spin wave.

[0111] The logic operation element 9 is a two-logic input XOR logic element or XNOR logic element. Specifically, the high or low of the first gate voltage corresponds to the first logic input, and the high or low of the second gate voltage corresponds to the second logic input.

[0112] First, it is assumed that the distance L3 between the spin wave generating unit 30 and the output unit 40 is approximately an even multiple of half the wavelength of the electron spin wave (that is, approximately an integer multiple of the wavelength).

[0113] Regions R4, R6, and R8 are in the iPSH state. Region R5 is in the PSH state when the first gate voltage is HIGH and in the iPSH state when the first gate voltage is LOW. Region R7 is in the PSH state when the second gate voltage is HIGH and in the iPSH state when the second gate voltage is LOW.

[0114] Consider the case where right-handed circularly polarized light is irradiated onto the spin wave generating unit 30 to generate an electron spin wave (upward) with a phase of 0. The phase state of the electron spin wave output from the output unit 40 according to the HIGH / LOW of the first gate voltage and the second gate voltage will be described below.

[0115] (When the first gate voltage = LOW and the second gate voltage = LOW) In region R4, electrons propagate while maintaining coherent spin rotation. In region R5, electrons propagate while maintaining coherent spin rotation. In region R6, electrons propagate while maintaining coherent spin rotation. In region R7, electrons propagate while maintaining coherent spin rotation. In region R8, electrons propagate while maintaining coherent spin rotation. Since the distance L3 is approximately an integer multiple of the wavelength of the electron spin wave, the phase state of the electron spin wave output from the output unit 40 is approximately the same as the state in the spin wave generation unit 30 (i.e., the phase difference between the spin wave generation unit 30 and the output unit 40 is approximately an integer multiple of 2π). Therefore, an electron spin wave with a phase of 0 (upward) is output from the output unit 40.

[0116] (When the first gate voltage is LOW and the second gate voltage is HIGH) In region R4, electrons propagate while maintaining coherent spin rotation. In region R5, electrons propagate while maintaining coherent spin rotation. In region R6, electrons propagate while maintaining coherent spin rotation. In region R7, electrons propagate without rotating their spin direction. At this time, since the length of region R7 (the length of the second gate electrode 22) is approximately an odd multiple of half the wavelength of the electron spin wave, the phase of the electron spin wave is shifted by approximately an odd multiple of π (approximately half the wavelength). In region R8, electrons propagate while maintaining coherent spin rotation. Since the distance L3 is approximately an integer multiple of the wavelength of the electron spin wave and the phase of the electron spin wave is shifted by approximately π in the region R7, the phase state of the electron spin wave output from the output unit 40 is approximately the opposite to that in the spin wave generation unit 30 (i.e., the phase difference between the spin wave generation unit 30 and the output unit 40 is approximately an odd multiple of π). Therefore, an electron spin wave (downward) with a phase of π is output from the output unit 40.

[0117] (When the first gate voltage is HIGH and the second gate voltage is LOW) In region R4, electrons propagate while maintaining coherent spin rotation. In region R5, electrons propagate without rotating their spin direction. At this time, since the length of region R5 (the length of the first gate electrode 21) is approximately an odd multiple of half the wavelength of the electron spin wave, the phase of the electron spin wave is shifted by approximately an odd multiple of π (approximately half the wavelength). In region R6, electrons propagate while maintaining coherent spin rotation. In region R7, electrons propagate while maintaining coherent spin rotation. In region R8, electrons propagate while maintaining coherent spin rotation. Since the distance L3 is approximately an integer multiple of the wavelength of the electron spin wave and the phase of the electron spin wave is shifted by approximately π in the region R5, the phase state of the electron spin wave output from the output unit 40 is approximately the opposite to that in the spin wave generation unit 30 (i.e., the phase difference between the spin wave generation unit 30 and the output unit 40 is approximately an odd multiple of π). Therefore, an electron spin wave (downward) with a phase of π is output from the output unit 40.

[0118] (When the first gate voltage is HIGH and the second gate voltage is HIGH) In region R4, electrons propagate while maintaining coherent spin rotation. In region R5, electrons propagate without rotating their spin direction. At this time, since the length of region R5 (the length of the first gate electrode 21) is approximately an odd multiple of half the wavelength of the electron spin wave, the phase of the electron spin wave is shifted by approximately an odd multiple of π (approximately a half wavelength). In region R6, electrons propagate while maintaining coherent spin rotation. In region R7, electrons propagate without rotating their spin direction. At this time, since the length of region R7 (the length of the second gate electrode 22) is approximately an odd multiple of half the wavelength of the electron spin wave, the phase of the electron spin wave is shifted by approximately an odd multiple of π (approximately a half wavelength). In region R8, electrons propagate while maintaining coherent spin rotation. Since the distance L3 is approximately an integer multiple of the wavelength of the electron spin wave and the phase of the electron spin wave is shifted by approximately π in regions R5 and R7 (regions R5 and R7 combined are shifted by approximately 2π), the phase state of the electron spin wave output from the output unit 40 is approximately the same as the state in the spin wave generation unit 30 (i.e., the phase difference between the spin wave generation unit 30 and the output unit 40 is approximately an integer multiple of 2π). Therefore, an electron spin wave with a phase of 0 (upward) is output from the output unit 40.

[0119] Here, the HIGH state of the first gate voltage corresponds to the logical value of the first input variable = 1, the LOW state of the first gate voltage corresponds to the logical value of the first input variable = 0, the HIGH state of the second gate voltage corresponds to the logical value of the second input variable = 1, and the LOW state of the second gate voltage corresponds to the logical value of the second input variable = 0, the result is "true" (logical value = 1) when the state in the spin wave generating unit 30 and the phase state of the electron spin wave output from the output unit 40 are opposite, and the result is "false" (logical value = 0) when the state in the spin wave generating unit 30 and the phase state of the electron spin wave output from the output unit 40 are the same, so the truth table is as shown in Table 1.

[0120] Table 1

[0121] In this way, by making the HIGH / LOW state of the first gate voltage correspond to the first logic input and the HIGH / LOW state of the second gate voltage correspond to the second logic input, an XOR logic element with two logic inputs in series can be realized.

[0122] Next, assume that the distance L3 between the spin wave generating unit 30 and the output unit 40 is approximately an odd multiple of half the wavelength of the electron spin wave (i.e., approximately a half-integer multiple of the wavelength). In this case, it is clear that the logic is the opposite of when the distance L3 is approximately an even multiple of half the wavelength of the electron spin wave.

[0123] Therefore, by making the distance L3 between the spin wave generating unit 30 and the output unit 40 approximately an odd multiple of half the wavelength of the electron spin wave, and by making the HIGH / LOW state of the first gate voltage correspond to the first logic input and the HIGH / LOW state of the second gate voltage correspond to the second logic input, an XNOR logic element with two logic inputs in series can be realized.

[0124] 10 and a majority logic element that receives the phases of a plurality of electron spin waves as a logic input and the phase of an electron spin wave obtained by superposing these plurality of electron spin waves as a logic output. This majority logic element has a two-dimensional thin wire structure that includes a one-dimensional thin wire structure through which electron spin waves propagate, a branch point where the one-dimensional thin wire structure branches into two or more branched thin wires, and a junction point where the two or more branched thin wires join to form one one-dimensional thin wire structure.

[0125] According to this embodiment, any logical operation can be realized.

[0126] As will be described later, in an embodiment in which the distance is determined by projection in the X direction, no phase shift occurs even if the lengths on the XY plane from the branching points to the merging points of multiple one-dimensional thin-wire structures are different, so a two-dimensional thin-wire structure can be easily constructed.

[0127] 12th Embodiment Figure 13 is a schematic diagram of an AND logic device 11 according to a twelfth embodiment. This embodiment is a logic device that combines three parallel logic inputs and majority logic. This logic device includes a one-dimensional thin-wire structure made of a material that generates electron spin waves having a phase corresponding to a predetermined polarization state when irradiated with light having a predetermined polarization state. The one-dimensional thin-wire structure is branched into three branches, a first branch thin-wire 501, a second branch thin-wire 502, and a third branch thin-wire 503, at a branch point 34, and the three branch thin-wires merge into one at a junction 35. This two-dimensional thin-wire structure 36 also includes a first gate electrode 51 extending along a portion of the first branch thin-wire 501 and a second gate electrode 52 extending along a portion of the second branch thin-wire 502. The two-dimensional wire structure 36 includes a spin wave generator 31 at or before the branch point 34 that generates an electron spin wave by irradiating an optical signal on electrons in the two-dimensional wire structure 36, or that receives an electron spin wave output from an adjacent one-dimensional wire structure as input. The two-dimensional wire structure 36 also includes an output unit 41 at or before the junction 35 that outputs an electron spin wave obtained by superimposing electron spin waves propagating through the first to third branch wires. The distance between the spin wave generator 31 and the output unit 41 is approximately an integer multiple of a half wavelength of the electron spin wave. In the first branch wire 501, a first gate electrode portion is disposed along the first gate electrode 51, and in the second branch wire 502, a second gate electrode portion is disposed along the second gate electrode 52. The lengths of the first and second gate electrodes are approximately an odd multiple of a half wavelength of the electron spin wave. The width of the one-dimensional wire structure is smaller than the half wavelength of the electron spin wave. The electron spin waves from the spin wave generator 31 before entering the first gate electrode unit and the second gate electrode unit are in the iPSH state or the PSH state, and a first gate voltage that puts the electron spin waves into the PSH state and a second gate voltage that puts the electron spin waves into the iPSH state can be applied to the first gate electrode 51 and the second gate electrode 52, respectively. Here, the branch point 34 coincides with the spin wave generator 31, the confluence point 35 coincides with the output unit 41, and the two-dimensional thin-wire structure 36 coincides with the AND logic device 11 itself.

[0128] According to this embodiment, in a parallel three-logic-input majority logic element, a two-logic-input AND logic device 11 can be realized by fixing one logic input to a logic value of 0. Furthermore, a NAND logic device can be realized by shifting the distance between the spin wave generating unit and the output unit by half a wavelength.

[0129] 14 is a schematic diagram of an OR logic device 12 according to a thirteenth embodiment. This embodiment is a logic device that combines three parallel logic inputs and majority logic. This logic device includes a one-dimensional thin-wire structure made of a material that generates electron spin waves having a phase corresponding to a predetermined polarization state when irradiated with light having a predetermined polarization state. The one-dimensional thin-wire structure is branched into three branches, a first branch thin-wire 501, a second branch thin-wire 502, and a third branch thin-wire 503, at a branch point 34, and the three branch thin-wires merge into one at a junction 35. The two-dimensional thin-wire structure 37 also includes a first gate electrode 51 extending along a portion of the first branch thin-wire 501, a second gate electrode 52 extending along a portion of the second branch thin-wire 502, and a third gate electrode 53 extending along a portion of the third branch thin-wire 503. The two-dimensional wire structure 37 includes a spin wave generator 31 that generates electron spin waves by irradiating an optical signal on electrons in the two-dimensional wire structure 37 at or before the branch point 34, or that receives an electron spin wave output from an adjacent one-dimensional wire structure as input. The two-dimensional wire structure 37 also includes an output unit 41 that outputs an electron spin wave obtained by superimposing electron spin waves propagating through the first to third branch wires at or before the junction 35. The distance between the spin wave generator 31 and the output unit 41 is approximately an integer multiple of a half wavelength of the electron spin wave. In the first branch wire 501, a first gate electrode portion is arranged along the first gate electrode 51. In the second branch wire 502, a second gate electrode portion is arranged along the second gate electrode 52. In the third branch wire 503, a third gate electrode portion is arranged along the third gate electrode 53. The lengths of the first, second, and third gate electrodes are approximately an odd multiple of a half wavelength of the electron spin wave. The width of the one-dimensional wire structure is smaller than the half wavelength of the electron spin wave. The electron spin waves before entering the first gate electrode section, the second gate electrode section, and the third gate electrode section from the spin wave generator 31 are in the iPSH state or the PSH state, and the first gate electrode 51 and the second gate electrode 52 can apply a first gate voltage that puts the electron spin waves into the PSH state and a second gate voltage that puts the electron spin waves into the iPSH state, respectively. The third gate electrode 53 applies the first gate voltage that puts the electron spin waves into the PSH state.Here, the branch point 34 coincides with the spin wave generating section 31, the confluence point 35 coincides with the output section 41, and the two-dimensional thin wire structure 37 coincides with the OR logic device 12 itself.

[0130] According to this embodiment, in a majority device with three parallel logic inputs, a two-logic input OR logic device can be realized by fixing one logic input to a logic value of 1. Furthermore, a NOR logic device can be realized by shifting the distance between the spin wave generating unit and the output unit by half a wavelength.

[0131] [Fourteenth Embodiment] FIG. 15 is a schematic diagram of a half adder 13 according to a fourteenth embodiment. That is, this embodiment is a logic device constituting a half adder. In this logic device, a one-dimensional thin-wire structure made of a material that generates electron spin waves having a phase corresponding to a predetermined polarization state when irradiated with light is branched into two one-dimensional thin-wire structures at a first branch point 341, further branched into a first branch thin-wire 601 and a second branch thin-wire 602 at a second branch point 342, and branched into a third branch thin-wire 603 and a fourth branch thin-wire 604 at a third branch point 343. As a result, a total of four branch thin-wires are formed. Furthermore, the first branch thin-wire 601 and the second branch thin-wire 602 merge at a first junction point 351 to form a one-dimensional thin-wire structure. Furthermore, the one-dimensional thin-wire structure and the third branch thin-wire 603 merge into one at a second junction point 352. The half adder 13 has a two-dimensional thin wire structure 38 formed by the first branch thin wire 601, the second branch thin wire 602, and the third branch thin wire 603 merging into one and a fourth branch thin wire 604 that does not merge with the other branch thin wires, a first gate electrode 51 along a part of the first branch thin wire 601, a second gate electrode 52 along a part of the second branch thin wire 602, and a third gate electrode 53 and a fourth gate electrode 54 along a part of the fourth branch thin wire 604. The two-dimensional thin wire structure 38 is provided with a spin wave generator 33 at or before a first branch point 341 that generates an electron spin wave by irradiating electrons in the two-dimensional thin wire structure 38 with an optical signal, or that receives as input an electron spin wave output from an adjacent one-dimensional thin wire structure, and a first output unit 43 at or after a second junction 352 that outputs an electron spin wave obtained by superimposing electron spin waves propagated through the first to third branch thin wires. The fourth branch thin wire 604 also includes a second output section 44 that outputs the electron spin wave propagated through the fourth branch thin wire 604. The distance between the spin wave generator 33 and the first output section 43 and the distance between the spin wave generator 33 and the second output section 44 are approximately an integer multiple of the wavelength of the electron spin wave. In the first branch thin wire 601, a first gate electrode section is arranged along the first gate electrode 51. In the second branch thin wire 602, a second gate electrode section is arranged along the second gate electrode 52. In the fourth branch thin wire 604, a third gate electrode section is arranged along the third gate electrode 53 and a fourth gate electrode section is arranged along the fourth gate electrode 54 in series.The length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional wire structure is smaller than half the wavelength of the electron spin wave. The electron spin wave before entering the first gate electrode section, second gate electrode section, and third gate electrode section from the spin wave generator 33 is in the iPSH state or the PSH state, and the first gate electrode 51, the second gate electrode 52, the third gate electrode 53, and the fourth gate electrode 54 can be applied with a first gate voltage that puts the electron spin wave in the PSH state and a second gate voltage that puts the electron spin wave in the iPSH state, respectively. Here, the first branch point 341 coincides with the spin wave generator 33, and the two-dimensional wire structure 38 coincides with the half adder 13 itself.

[0132] In the above embodiment, the one-dimensional thin wire structure branches into two branch thin wires at the first branch point 341, and then further branches into two each at the second branch point 342 and the third branch point 343, but this is not limited to this, and for example, it may branch into four at the branch points.

[0133] For example, the phase state of the electron spin wave output from the first output section 43 may be the upper bit of a 2-bit binary number, and the phase state of the electron spin wave output from the second output section 44 may be the lower bit of the 2-bit binary number. Alternatively, one of the binary numbers to be added may be input to the first gate electrode 51 and the third gate electrode 53, and the other of the binary numbers to be added may be input to the second gate electrode 52 and the fourth gate electrode 54.

[0134] According to this embodiment, by making it possible to perform a logical operation on an optical input signal based on the voltage level while maintaining the wave coherence, a half adder based on the logical operation and the wave coherence can be realized.

[0135] Fifteenth Embodiment A logical operation element 1 according to a fifteenth embodiment will be described with reference to FIG. 2 . This logical operation element 1 operates as a NOT logic device. The logical operation element 1 has a one-dimensional wire structure 10 and a gate electrode 20. The one-dimensional wire structure 10 includes a spin wave generator 30 that generates electron spin waves when an optical signal is irradiated onto electrons in the one-dimensional wire structure, and an output section 40 that outputs the electron spin waves that have propagated through the one-dimensional wire structure 10. The gate electrode 20 is disposed between the spin wave generator 30 and the output section 40 along the one-dimensional wire structure 10.

[0136] For example, the polarization state of the irradiated light may be either right-handed circularly polarized light or left-handed circularly polarized light. When such light is irradiated onto the spin wave generation unit 30, the spin wave generation unit 30 generates an electron spin wave with a phase of 0 for right-handed circularly polarized light and an electron spin wave with a phase of π for left-handed circularly polarized light. Hereinafter, an electron spin wave with a phase of 0 will be associated with a logical value of "0," and an electron spin wave with a phase of π will be associated with a logical value of "1." Therefore, in this case, right-handed circularly polarized light of the irradiated light corresponds to a logical value of 0, and left-handed circularly polarized light corresponds to a logical value of 1.

[0137] By applying a gate voltage such that α = 0 to a portion of the one-dimensional wire structure 10 where β = 0, the gate electrode 20 converts between a state in which only the Rashba interaction acts as a spin-orbit interaction on electrons in the one-dimensional wire structure 10 and a state in which no interaction acts. In the example of FIG. 2 , the distance L1 between the spin-wave generator 30 and the output section 40 is approximately an integer multiple of the wavelength of the electron spin wave propagating through the one-dimensional wire structure 10. Regions R1 and R3 of the one-dimensional wire structure 10 are not directly under the gate electrode 20, so no gate voltage is applied. On the other hand, region R2 is directly under the gate electrode 20, so a gate voltage is applied. At this time, for example, if region R1 was in a state in which only the Rashba interaction acts as a spin-orbit interaction on electrons in the one-dimensional wire structure 10, region R2 is converted to a state in which no interaction acts, and region R3 returns to a state in which only the Rashba interaction acts.

[0138] The distance L1 between the spin wave generating section 30 and the output section 40 is approximately an integer multiple of the wavelength of the electron spin wave propagating in the one-dimensional wire structure 10. The length L2 of the gate electrode 20 is approximately an odd multiple of half the wavelength of the electron spin wave. The width W1 of the one-dimensional wire structure is smaller than half the wavelength of the electron spin wave.

[0139] Other configurations and operations of the logical operation element 1 are the same as those of the NOT logic device of the second embodiment.

[0140] In an InGaAs / GaAs heterostructure, a two-dimensional electron system is formed near the interface. The spin-orbit interaction that occurs when an electric field is applied perpendicularly to this system is the Rashba interaction. As described above, by applying a gate voltage exceeding a threshold value to the gate electrode 20 to convert between a state in which only the Rashba interaction acts as the spin-orbit interaction for electrons in the one-dimensional wire structure 10 and a state in which no Rashba interaction acts, the phase of the electron spin wave can be controlled, similar to the conversion between the PSH state and the iPSH state (second embodiment).

[0141] 11 , a logical operation element 8 according to a sixteenth embodiment will be described. This logical operation element 8 operates as a NOT logic device. The logical operation element 8 has a one-dimensional wire structure 10 and a gate electrode 24. The one-dimensional wire structure 10 includes a spin wave generating section 33 and an output section 45.

[0142] One-dimensional wire structure 10 is made of a material that generates electron spin waves having a phase corresponding to a predetermined polarization state when irradiated with light. Spin wave generator 33 generates electron spin waves when electrons in the one-dimensional wire structure are irradiated with an optical signal. Output unit 45 outputs the electron spin waves that have propagated through one-dimensional wire structure 10.

[0143] By applying a gate voltage such that α = β = 0 to a portion of one-dimensional wire structure 10 where β = 0, gate electrode 24 converts between a state in which only the Rashba interaction acts as a spin-orbit interaction on electrons in one-dimensional wire structure 10 and a state in which no interaction acts. In the example of FIG. 11 , distance L1 between spin wave generator 33 and output section 45 is approximately an integer multiple of half the wavelength of the electron spin wave propagating through one-dimensional wire structure 10. Regions R1 and R3 of one-dimensional wire structure 10 are not directly under gate electrode 24, so no gate voltage is applied. On the other hand, region R2 is directly under gate electrode 24, so a gate voltage is applied. At this time, for example, if region R1 was in a state in which only the Rashba interaction acts as a spin-orbit interaction on electrons in one-dimensional wire structure 10, region R2 is converted to a state in which no interaction acts, and region R3 returns to a state in which only the Rashba interaction acts.

[0144] Other configurations and operations of the logical operation element 8 are the same as those of the NOT logical device of the ninth embodiment.

[0145] In this way, by applying a gate voltage to gate electrode 20 such that α = β = 0, a state in which only the Rashba interaction acts as the spin-orbit interaction on electrons in one-dimensional wire structure 10 is converted to a state in which no interaction acts, and vice versa. This makes it possible to control the phase of the electron spin wave, similar to the conversion between the PSH state and the iPSH state (ninth embodiment).

[0146] The present invention has been described above based on the embodiments. These embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of the respective components and treatment processes, and that such modifications are also within the scope of the present invention.

[0147] The NOT logic device, AND logic device, and OR logic device described in the embodiments realize the basic functions of digital circuits. By combining these basic functions with majority logic while maintaining the wave nature of electron spin waves, various functions can be realized.

[0148] When understanding the abstract technical ideas of the embodiments and modifications, the technical ideas should not be interpreted as being limited to the contents of the embodiments and modifications. The above-described embodiments and modifications are merely illustrative examples, and many design modifications, such as changes, additions, and deletions of components, are possible. In the embodiments, the contents in which such design modifications are possible are emphasized by adding the notation "embodiment." However, design modifications are also permitted even in contents not so notated.

[0149] The technology of the present disclosure is applicable to fields such as optical communications, photoelectric conversion systems, and network computers.

[0150] DESCRIPTION OF THE SYMBOLS 1A... Logic operation element, 1... NOT logic device, 2... Switchable NOT logic device, 3... XOR logic device, 4... AND logic device, 5... OR logic device, 6... Half adder, 7... Logic operation element, 8... Logic operation element, 9... Logic operation element, 10... One-dimensional thin wire structure, 11... AND logic device, 12... OR logic device, 13... Half adder, 103... Third NOT logic device, 20A... Gate electrode, 20... Gate electrode, 21... Gate electrode, 22... Gate electrode, 23... Gate electrode, 24... Gate electrode, 201... First switchable NOT logic device, 202... Second switchable NOT logic device, 20S... Switch, 21S... Switch, 22S... Switch, 302: Second XOR logic device, 30: Spin wave generating unit, 31: Spin wave generating unit, 32: Spin wave generating unit, 33: Spin wave generating unit, 34: Branch point, 341: First branch point, 342: Second branch point, 343: Third branch point, 35: Junction point, 351: First junction point, 352: Second junction point, 36: Two-dimensional thin wire structure, 37: Two-dimensional thin wire structure, 38: Two-dimensional thin wire structure, 401: First AND logic device, 40: Output unit, 41: Output unit, 42: Output unit, 43: Output unit of first AND logic device, 44: Output unit of second XOR logic device, 45: Output unit, 51: First gate electrode, 52: Second gate electrode, 53: Third gate electrode, 54: Fourth gate electrode, 501: First branch thin wire, 502: Second branch thin wire, 503: Third branch thin wire, 601: First branch thin wire, 602: Second branch thin wire, 603: Third branch thin wire, 604: Fourth branch thin wire, 703: Third one-dimensional thin wire structure, L1: Distance between spin wave generating section and output section, L2: Length of gate electrode, L3: Distance between spin wave generating section and output section, L4: Length of first gate electrode, L5: Length of second gate electrode, L6: Distance between first gate electrode and second gate electrode, W1: Width of one-dimensional thin wire structure, R1: Region, R2: Region, R3: Region, R4... area, R5... area, R6... area, R7... area, R8... area.

Claims

1. A logic element comprising: a one-dimensional nanowire structure on which an electron spin wave having a phase corresponding to a predetermined polarization state is propagated, made of a material that generates an electron spin wave having a phase corresponding to the polarization state when irradiated with light having a predetermined polarization state; and a gate electrode along a part of the one-dimensional nanowire structure, wherein the phase state of the electron spin wave before it propagates through the one-dimensional nanowire structure is used as a logic input, and the phase state of the electron spin wave after it propagates through the one-dimensional nanowire structure is used as a logic output.

2. The one-dimensional nanowire structure comprises a spin wave generation unit that generates electron spin waves by irradiating electrons in the one-dimensional nanowire structure with an optical signal, or receives electron spin waves output from an adjacent one-dimensional nanowire structure, and an output unit that outputs the electron spin waves propagating through the one-dimensional nanowire structure. In the one-dimensional nanowire structure, the gate electrode portion along the gate electrode is arranged between the spin wave generation unit and the output unit. The distance between the spin wave generation unit and the output unit is approximately an integer multiple of the wavelength of the electron spin wave. The length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional nanowire structure is smaller than half the wavelength of the electron spin wave. The electron spin wave before it enters the gate electrode from the spin wave generation unit is in the iPSH state or the PSH state, and when the electron spin wave before it enters the gate electrode from the spin wave generation unit is in the iPSH state, a gate voltage can be applied to bring the electron spin wave in the gate electrode to the PSH state, and when the electron spin wave before it enters the gate electrode from the spin wave generation unit is in the PSH state, a gate voltage can be applied to bring the electron spin wave in the gate electrode to the iPSH state. The logic element according to claim 1, characterized in that it operates as a NOT logic device that takes the phase state of the electron spin wave of the spin wave generation unit as a logic input and the phase state of the electron spin wave of the output unit as a logic output.

3. The one-dimensional nanowire structure comprises a spin wave generation unit that generates electron spin waves by irradiating electrons in the one-dimensional nanowire structure with an optical signal, or receives electron spin waves output from an adjacent one-dimensional nanowire structure, and an output unit that outputs the electron spin waves propagating through the one-dimensional nanowire structure. In the one-dimensional nanowire structure, the gate electrode portion along the gate electrode is arranged between the spin wave generation unit and the output unit. The distance between the spin wave generation unit and the output unit is approximately an integer multiple of the wavelength of the electron spin wave. The length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional nanowire structure is smaller than half the wavelength of the electron spin wave. The electron spin wave before entering the gate electrode from the spin wave generation unit is in an iPSH state or a PSH state, and the gate electrode has a switch that switches the voltage applied to it between a first gate voltage that puts the electron spin wave into a PSH state and a second gate voltage that puts it into an iPSH state. The logic element according to claim 1, characterized in that it operates as a NOT logic device that can be switched to an identity logic device by the switch, with the phase state of the electron spin wave of the spin wave generation unit as the logic input and the phase state of the electron spin wave of the output unit as the logic output.

4. When the logic operation element described in Claim 3 is referred to as the first logic operation element, An XOR logic device having two of the first logic elements, The two aforementioned first logic elements are connected in series, one in the front stage and the other in the back stage. The spin wave generation unit of the preceding first logic operation element becomes the overall spin wave generation unit. The output section of the preceding first logic operation element is shared with the spin wave generation section of the subsequent first logic operation element. The output section of the subsequent first logic operation element becomes the overall output section. An XOR logic device characterized in that the voltage applied to the gate electrodes of two of the first logic elements is either a first gate voltage that puts the electron spin wave into a PSH state, or a second gate voltage that puts the electron spin wave into an iPSH state, is taken as a logic input, and the phase state of the electron spin wave in the overall output section is taken as a logic output.

5. When the logic operation element described in Claim 3 is referred to as the first logic operation element, An AND logic device having two of the first logic operation elements and one of the one-dimensional nanowire structures, The three components—two of the first logic operation elements and one of the one-dimensional nanowire structures—are connected in parallel, and the spin wave generation sections of the two first logic operation elements and the one of the one-dimensional nanowire structures are common to each other. The two first logic operation elements and the output section of one of the one-dimensional nanowire structures are common to each other. An AND logic device characterized in that the voltage applied to the gate electrodes of two of the first logic elements is either a first gate voltage that puts the electron spin wave into a PSH state, or a second gate voltage that puts the electron spin wave into an iPSH state, is taken as a logic input, and the phase state of the electron spin wave in the output section is taken as a logic output.

6. When the logic element described in Claim 3 is referred to as the first logic element, and the logic element described in Claim 2 is referred to as the second logic element, An OR logic device having two of the first logic elements and one of the second logic elements, The two first logic elements and the one second logic element are connected in parallel. The spin wave generation sections of the two first logic elements and the one second logic element are common to all of them. The output sections of the two first logic elements and the one second logic element are common. An OR logic device characterized in that the voltage applied to the gate electrodes of two of the first logic elements is either a first gate voltage that puts the electron spin wave into a PSH state, or a second gate voltage that puts the electron spin wave into an iPSH state, is taken as a logic input, and the phase state of the electron spin wave in the output section is taken as a logic output.

7. A half adder comprising the AND logic device described in claim 5 and the XOR logic device described in claim 4, The AND logic device and the XOR logic device are connected in parallel. The spin wave generation section of the AND logic device and the XOR logic device are common, while the output sections of the AND logic device and the XOR logic device are separate. The voltage applied to the gate electrodes of the two first logic elements of the AND logic device is either a first gate voltage that puts the electron spin wave into a PSH state, or a second gate voltage that puts the electron spin wave into an iPSH state. This is added together as a 1-bit binary input, and the phase state of the electron spin wave at the output of the AND logic device is output as the upper bit of a 2-bit binary number. A half-adder characterized in that the voltage applied to the gate electrodes of the two first logic elements of the XOR logic device is either the first gate voltage or the second gate voltage, which is used as the 1-bit binary input for addition, and the phase state of the electron spin wave at the output section of the XOR logic device is used as the lower bit output of a 2-bit binary number.

8. A logic device comprising a material that generates an electron spin wave having a phase corresponding to the polarization state when irradiated with light having a predetermined polarization state, a one-dimensional nanowire structure on which the electron spin wave propagates, and a gate electrode along a part of the one-dimensional nanowire structure, wherein the high or low gate voltage applied to the gate electrode is used as a logic input and the phase state of the electron spin wave is used as a logic output.

9. The one-dimensional nanowire structure comprises a spin wave generation unit that generates electron spin waves by irradiating electrons in the one-dimensional nanowire structure with an optical signal, or receives electron spin waves output from an adjacent one-dimensional nanowire structure, and an output unit that outputs the electron spin waves propagating through the one-dimensional nanowire structure. In the one-dimensional nanowire structure, the gate electrode portion along the gate electrode is arranged between the spin wave generation unit and the output unit. The distance between the spin wave generation unit and the output unit is approximately an integer multiple of half the wavelength of the electron spin wave. The length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional nanowire structure is smaller than half the wavelength of the electron spin wave. The logic device according to claim 8, characterized in that the electron spin wave before entering the gate electrode from the spin wave generation unit is in an iPSH state or a PSH state, and the gate electrode can be to which a first gate voltage that puts the electron spin wave into a PSH state and a second gate voltage that puts the electron spin wave into an iPSH state are applied.

10. The gate electrode is composed of a first gate electrode and a second gate electrode, The one-dimensional nanowire structure comprises a spin wave generation unit that generates electron spin waves by irradiating electrons within the one-dimensional nanowire structure with an optical signal, or receives electron spin waves output from an adjacent one-dimensional nanowire structure, and an output unit that outputs the electron spin waves propagating through the one-dimensional nanowire structure. In the one-dimensional nanowire structure, a first gate electrode portion along the first gate electrode and a second gate electrode portion along the second gate electrode are arranged in series between the spin wave generation unit and the output unit. The distance between the spin wave generation unit and the output unit is approximately an integer multiple of half the wavelength of the electron spin wave. The lengths of the first gate electrode and the second gate electrode are each approximately an odd multiple of half the wavelength of the electron spin wave. The distance between the first gate electrode and the second gate electrode is approximately an integer multiple of the wavelength of the electron spin wave. The width of the one-dimensional nanowire structure is smaller than half the wavelength of the electron spin wave. The logic element according to claim 8, characterized in that the electron spin wave before entering the first gate electrode from the spin wave generation unit is in an iPSH state or a PSH state, and the first gate electrode and the second gate electrode can each be to which a first gate voltage that puts the electron spin wave into a PSH state and a second gate voltage that puts the electron spin wave into an iPSH state are applied.

11. A logic device comprising a logic operation element as described in claim 8, and a majority voting logic element that takes the phase states of a plurality of electron spin waves as logic inputs and the phase state of an electron spin wave obtained by superimposing the plurality of electron spin waves as a logic output, The majority voting logic element is a logic device characterized by having a material that generates electron spin waves having a phase corresponding to a predetermined polarization state when irradiated with light having a predetermined polarization state, and having a one-dimensional nanowire structure on which the electron spin waves propagate, a branching point where the one-dimensional nanowire structure branches to form two or more branched nanowires, and a confluence point where the two or more branched nanowires merge to form one one-dimensional nanowire structure.

12. At the branching point, the one-dimensional nanowire structure branches into three branches: a first branched nanowire, a second branched nanowire, and a third branched nanowire; and at the confluence point, the three branched nanowires confluence to form a two-dimensional nanowire structure, where the three branched nanowires merge to form a single one-dimensional nanowire structure. The first logic operation element comprises a portion of the first branched nanowire and a first gate electrode along the portion thereof, and the second logic operation element comprises a portion of the second branched nanowire and a second gate electrode along the portion thereof, The two-dimensional nanowire structure includes a spin wave generation unit that generates electron spin waves by irradiating electrons within the two-dimensional nanowire structure with an optical signal at or before the branching point, or by receiving electron spin waves output from an adjacent one-dimensional nanowire structure, and an output unit that outputs electron spin waves obtained by superimposing the electron spin waves that have propagated through the first to third branched nanowires at or after the confluence point. The distance between the spin wave generation unit and the output unit is approximately an integer multiple of half the wavelength of the electron spin wave. In the first branched nanowire, a first gate electrode portion is arranged along the first gate electrode, and in the second branched nanowire, a second gate electrode portion is arranged along the second gate electrode. The lengths of the first and second gate electrodes are approximately odd multiples of half the wavelength of the electron spin wave. The width of the one-dimensional nanowire structure is smaller than half the wavelength of the electron spin wave. The logic device according to claim 11, characterized in that the electron spin wave before entering the first gate electrode and second gate electrode from the spin wave generation unit is in an iPSH state or a PSH state, and the first gate electrode and the second gate electrode can each be to which a first gate voltage that puts the electron spin wave into a PSH state and a second gate voltage that puts the electron spin wave into an iPSH state are applied.

13. At the branching point, the one-dimensional nanowire structure branches into three branches: a first branched nanowire, a second branched nanowire, and a third branched nanowire; and at the confluence point, the three branched nanowires confluence to form a two-dimensional nanowire structure, where the three branched nanowires merge to form a single one-dimensional nanowire structure. A first logic operation element comprising a portion of the first branched nanowire and a first gate electrode along the portion thereof, a second logic operation element comprising a portion of the second branched nanowire and a second gate electrode along the portion thereof, a portion of the third branched nanowire and a third gate electrode along the portion thereof, It has, The two-dimensional nanowire structure includes a spin wave generation unit that generates electron spin waves by irradiating electrons within the two-dimensional nanowire structure with an optical signal at or before the branching point, or by receiving electron spin waves output from an adjacent one-dimensional nanowire structure, and an output unit that outputs electron spin waves obtained by superimposing the electron spin waves that have propagated through the first to third branched nanowires at or after the confluence point. The distance between the spin wave generation unit and the output unit is approximately an integer multiple of half the wavelength of the electron spin wave. In the first branched nanowire, a first gate electrode portion is arranged along the first gate electrode; in the second branched nanowire, a second gate electrode portion is arranged along the second gate electrode; and in the third branched nanowire, a third gate electrode portion is arranged along the third gate electrode. The lengths of the first, second, and third gate electrodes are approximately odd multiples of half the wavelength of the electron spin wave. The width of the one-dimensional nanowire structure is smaller than half the wavelength of the electron spin wave. The logic device according to claim 11, characterized in that the electron spin wave before entering the first gate electrode, second gate electrode, and third gate electrode from the spin wave generation unit is in an iPSH state or a PSH state, the first gate electrode and the second gate electrode can each be to which a first gate voltage that puts the electron spin wave into a PSH state and a second gate voltage that puts the electron spin wave into an iPSH state are applied, and the third gate electrode can be to which a first gate voltage that puts the electron spin wave into a PSH state is applied.

14. At the branching point, the one-dimensional nanowire structure branches into four branches: a first branched nanowire, a second branched nanowire, a third branched nanowire, and a fourth branched nanowire; at the confluence point, the three branched nanowires, the first branched nanowire, the second branched nanowire, and the third branched nanowire, merge to form a single one-dimensional nanowire structure; and the fourth branched nanowire is a two-dimensional nanowire structure which is a one-dimensional nanowire structure that does not merge with the other branched nanowires. A first logic operation element comprising a portion of the first branch nanowire and a first gate electrode along the portion thereof; a second logic operation element comprising a portion of the second branch nanowire and a second gate electrode along the portion thereof; a third logic operation element comprising a portion of the fourth branch nanowire and a third gate electrode along the portion thereof; and a fourth logic operation element comprising another portion of the fourth branch nanowire and a fourth gate electrode along the other portion thereof. It has, The two-dimensional nanowire structure includes a spin wave generation unit that generates electron spin waves by irradiating electrons within the two-dimensional nanowire structure with an optical signal at or before the branching point, or by receiving electron spin waves output from an adjacent one-dimensional nanowire structure; a first output unit that outputs an electron spin wave obtained by superimposing the electron spin waves propagating through the first to third branch nanowires at or after the confluence point; and a second output unit that outputs the electron spin wave propagating through the fourth branch nanowire. The distance between the spin wave generation unit and the first output unit, and the distance between the spin wave generation unit and the second output unit are approximately integer multiples of the wavelength of the electron spin wave. In the first branched thin wire, a first gate electrode portion is arranged along the first gate electrode, In the second branched thin wire, a second gate electrode portion is arranged along the second gate electrode, In the fourth branched thin wire, a third gate electrode portion along the third gate electrode and a fourth gate electrode portion along the fourth gate electrode are arranged in series. The length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional nanowire structure is smaller than half the wavelength of the electron spin wave. The logic device according to claim 11, characterized in that the electron spin wave before entering the first gate electrode section, the second gate electrode section, and the third gate electrode section from the spin wave generation section is in an iPSH state or a PSH state, and the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode are each capable of having a first gate voltage applied to bring the electron spin wave into a PSH state and a second gate voltage applied to bring the electron spin wave into an iPSH state.

15. The gate electrode is capable of receiving a first gate voltage that causes only the Rashba interaction to act as the spin-orbit interaction with the electrons in the one-dimensional nanowire structure, and a second gate voltage that causes no interaction to act. The one-dimensional nanowire structure comprises a spin wave generation unit that generates electron spin waves by irradiating electrons within the one-dimensional nanowire structure with an optical signal, or receives electron spin waves output from an adjacent one-dimensional nanowire structure, and an output unit that outputs the electron spin waves propagating through the one-dimensional nanowire structure. The gate electrode is arranged between the spin wave generation unit and the output unit along the one-dimensional nanowire structure. The distance between the spin wave generation unit and the output unit is approximately an integer multiple of the wavelength of the electron spin wave. The length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional nanowire structure is smaller than half the wavelength of the electron spin wave. The logic element according to claim 1, characterized in that it operates as a NOT logic device that takes the phase state of the electron spin wave of the spin wave generation unit as a logic input and the phase state of the electron spin wave of the output unit as a logic output.

16. The one-dimensional nanowire structure comprises a spin wave generation unit that generates electron spin waves by irradiating electrons in the one-dimensional nanowire structure with an optical signal, or receives electron spin waves output from an adjacent one-dimensional nanowire structure, and an output unit that outputs the electron spin waves propagating through the one-dimensional nanowire structure. In the one-dimensional nanowire structure, the gate electrode portion along the gate electrode is arranged between the spin wave generation unit and the output unit. The distance between the spin wave generation unit and the output unit is approximately an integer multiple of half the wavelength of the electron spin wave. The length of the gate electrode is approximately an odd multiple of half the wavelength of the electron spin wave. The width of the one-dimensional nanowire structure is smaller than half the wavelength of the electron spin wave. The logic element according to claim 8, characterized in that the electron spin wave before it enters the gate electrode from the spin wave generation unit is in a state where only the Rashba interaction acts as the spin-orbit interaction, and the gate electrode can be to which a first gate voltage is applied that causes the electron spin wave to be in a state where only the Rashba interaction acts as the spin-orbit interaction, and a second gate voltage is applied that causes the electron spin wave to be in a state where no interaction acts as the spin-orbit interaction.