Semiconductor device

Abstract

This semiconductor device includes: a chip that has a main face; a first conductivity-type semiconductor region that is formed in a surface layer portion of the main face; a trench-type source structure that is formed on the main face and is located in the semiconductor region; and a second conductivity-type impurity region that is formed in a region directly below the source structure in the chip and that forms a pn junction portion with the semiconductor region.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-113895 filed with the Japan Patent Office on July 11, 2023, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2019 / 0280119A1) discloses a semiconductor device including a p-type doped region formed in an n-type epitaxial layer directly below a trench gate structure.

[0003] US Patent Application Publication No. 2019 / 0280119

[0004] [Summary] The present disclosure provides a semiconductor device that can improve electrical characteristics.

[0005] The present disclosure provides a semiconductor device including a chip having a main surface, a first conductivity type semiconductor region formed in a surface layer portion of the main surface, a trench-type source structure formed in the main surface and positioned within the semiconductor region, and a second conductivity type impurity region formed in a region directly below the source structure within the chip and forming a pn junction with the semiconductor region.

[0006] The present disclosure provides a semiconductor device including a chip having a main surface, a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface, a trench-type gate structure formed on the main surface and positioned within the semiconductor region, a trench-type source structure formed on the main surface and spaced apart from the gate structure and positioned within the semiconductor region, a first impurity region of a second conductivity type formed in a region immediately below the gate structure within the chip, and a second impurity region of the second conductivity type formed in a region immediately below the source structure and spaced apart from the first impurity region within the chip.

[0007] The present disclosure provides a method for manufacturing a semiconductor device, including the steps of: preparing a wafer having a semiconductor region of a first conductivity type in a surface layer portion of a main surface; forming a source trench in the main surface so as to be positioned within the semiconductor region; and introducing an impurity of a second conductivity type into the semiconductor region through a bottom wall of the source trench to form an impurity region of the second conductivity type that forms a pn junction with the semiconductor region in a region directly below the source trench.

[0008] The above and further objects, features and advantages will become more apparent from the accompanying drawings and detailed description.

[0009] FIG. 1 is a plan view showing a semiconductor device. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a perspective view showing the shape of a chip. FIG. 4 is a plan view showing a layout example of a first main surface. FIG. 5 is an enlarged plan view showing a main portion of the first main surface together with a contact region according to the first layout example. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 6 . FIG. 9 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 7 . FIG. 10 is a graph showing an example of a concentration gradient in a column region. FIG. 11 is a graph showing another example of a concentration gradient in a column region. FIG. 12A is an enlarged plan view showing a main portion of the first main surface together with a contact region according to a second layout example. FIG. 12B is an enlarged plan view showing a main portion of the first main surface together with a contact region according to a third layout example. 12C is an enlarged plan view showing a main portion of the first main surface together with a contact region according to a fourth layout example. FIG. 12D is an enlarged plan view showing a main portion of the first main surface together with a contact region according to a fifth layout example. FIG. 12E is an enlarged plan view showing a main portion of the first main surface together with a contact region according to a sixth layout example. FIG. 12F is an enlarged plan view showing a main portion of the first main surface together with a contact region according to a seventh layout example. FIG. 13 is a schematic diagram showing a wafer used in manufacturing a semiconductor device. FIG. 14A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. FIG. 14B is a cross-sectional view showing a step after FIG. 14A. FIG. 14C is a cross-sectional view showing a step after FIG. 14B. FIG. 14D is a cross-sectional view showing a step after FIG. 14C. FIG. 14E is a cross-sectional view showing a step after FIG. 14D. FIG. 14F is a cross-sectional view showing a step after FIG. 14E. FIG. 14G is a cross-sectional view showing a step after FIG. 14F. FIG. 14H is a cross-sectional view showing a step after FIG. 14G. Fig. 14I is a cross-sectional view showing a step after Fig. 14H. Fig. 14J is a cross-sectional view showing a step after Fig. 14I. Fig. 14K is a cross-sectional view showing a step after Fig. 14J. Fig. 14L is a cross-sectional view showing a step after Fig. 14K. Fig. 14M is a cross-sectional view showing a step after Fig. 14L. Fig. 14N is a cross-sectional view showing a step after Fig. 14M. Fig. 15 is a cross-sectional view showing a semiconductor device according to a first modification.16 is a cross-sectional view showing a semiconductor device according to a second modified example, FIG. 17 is a cross-sectional view showing a semiconductor device according to a third modified example, and FIG. 18 is a cross-sectional view showing a semiconductor device according to a fourth modified example.

[0010] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0011] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0012] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0013] Fig. 1 is a plan view showing a semiconductor device 1. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a perspective view showing the shape of a chip 2. Fig. 4 is a plan view showing an example layout of a first main surface 3.

[0014] Fig. 5 is an enlarged plan view showing a main portion of the first main surface 3 together with a contact region 35 according to a first layout example. Fig. 6 is a cross-sectional view taken along line VI-VI shown in Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 5. Fig. 8 is an enlarged cross-sectional view showing a main portion of the region shown in Fig. 6. Fig. 9 is an enlarged cross-sectional view showing a main portion of the region shown in Fig. 7.

[0015] The semiconductor device 1 is a semiconductor switching device including an insulated gate transistor structure Tr. The transistor structure Tr may be referred to as a MISFET structure (Metal Insulator Semiconductor Field Effect Transistor structure). The transistor structure Tr has a vertical structure.

[0016] 1 to 9, semiconductor device 1 includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1 is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0017] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device."

[0018] The semiconductor device 1 may be referred to as a "SiC-MISFET." Hexagonal SiC single crystal has a variety of polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0019] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0020] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0021] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0022] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0023] The chip 2 (first main surface 3 and second main surface 4) has an off-axis angle inclined at a predetermined angle in a predetermined off-axis direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical line toward the off-axis direction by the off-axis angle. The c-plane of the SiC single crystal is also inclined with respect to the horizontal plane by the off-axis angle.

[0024] The off-direction is preferably the a-axis direction of the SiC single crystal (second direction Y in this embodiment). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0025] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0026] The semiconductor device 1 includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4 of the chip 2. A drain potential as a first potential (high potential) is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as a "semiconductor layer," a "first semiconductor layer," a "drain region," or the like.

[0027] The first semiconductor region 6 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has the off direction and off angle described above.

[0028] The first semiconductor region 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor region 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0029] The semiconductor device 1 includes an n-type second semiconductor region 7 formed in a surface layer portion of the first main surface 3 of the chip 2. The second semiconductor region 7 may also be referred to as a "semiconductor layer," a "second semiconductor layer," a "drift region," or the like. The second semiconductor region 7 has an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor region 6.

[0030] The second semiconductor region 7 is formed in a layer shape extending along the first main surface 3 and is electrically connected to the first semiconductor region 6. The second semiconductor region 7 is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0031] The second semiconductor region 7 (epitaxial layer) has the off direction and off angle described above. The second semiconductor region 7 preferably has a thickness less than that of the first semiconductor region 6. Of course, the thickness of the second semiconductor region 7 may be greater than that of the first semiconductor region 6.

[0032] The thickness of the second semiconductor region 7 may be 5 μm or more and 50 μm or less. The thickness of the second semiconductor region 7 may have a value belonging to at least one of the ranges of 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or more and 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or more, and 45 μm or more and 50 μm or less.

[0033] In this embodiment, the second semiconductor region 7 has a concentration gradient in which the n-type impurity concentration changes in the thickness direction. Specifically, the second semiconductor region 7 includes a low-concentration region 7a on the bottom side and a high-concentration region 7b on the surface side, and has a concentration gradient in which the n-type impurity concentration increases from the bottom side to the surface side. The boundary between the high-concentration region 7b and the low-concentration region 7a is defined by the bottom of the high-concentration region 7b. The bottom of the high-concentration region 7b is the portion where the n-type impurity concentration gradually decreases toward the low-concentration region 7a (from the first main surface 3 side to the second main surface 4 side).

[0034] The low-concentration region 7a is formed in a layer shape extending along the first major surface 3 and is electrically connected to the first semiconductor region 6. The low-concentration region 7a is exposed from the first to fourth side surfaces 5A to 5D. The thickness of the low-concentration region 7a may be 0.1 μm or more and 5 μm or less. The thickness of the low-concentration region 7a may have a value belonging to any one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less.

[0035] The high-concentration region 7b is formed in a thickness range between the first main surface 3 and the low-concentration region 7a, and is electrically connected to the first semiconductor region 6 via the low-concentration region 7a. The high-concentration region 7b is formed in a layer shape extending along the first main surface 3, and faces the first semiconductor region 6 with the low-concentration region 7a sandwiched between them. The high-concentration region 7b is exposed from the first to fourth side surfaces 5A to 5D. The high-concentration region 7b may be exposed from the first main surface 3, or may be formed at an interval from the first main surface 3 toward the second main surface 4.

[0036] The high-concentration region 7b may have a portion located in a region closer to the first main surface 3 than the intermediate portion of the thickness range of the second semiconductor region 7, and a portion located in a region closer to the bottom of the second semiconductor region 7 than the intermediate portion of the thickness range of the second semiconductor region 7. Of course, the high-concentration region 7b may be located only in the region closer to the first main surface 3 than the intermediate portion of the thickness range of the second semiconductor region 7.

[0037] The high-concentration region 7 b may be formed by introducing a pentavalent element (n-type impurity) into the n-type semiconductor layer. The high-concentration region 7 b may be an n-type channeling region extending along an axial channel of the chip 2 (second semiconductor region 7) in a cross-sectional view. The axial channel is a region (channel) with a relatively wide interatomic distance (atomic spacing) with respect to the SiC single crystal constituting the chip 2 (second semiconductor region 7), and is surrounded by atomic rows constituting a crystal axis extending in the thickness direction (crystal growth direction).

[0038] That is, the axial channel is a region in which the atomic rows are sparse extending in the thickness direction and the atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a plan view. The axial channel is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values ​​of "a1", "a2", "a3", and "c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c).

[0039] In this embodiment, the axial channel is composed of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal. That is, the axial channel extends along the c-axis and has the off-direction and off-angle described above. In other words, the axial channel is inclined by the off-angle from the vertical axis toward the off-direction.

[0040] When the high-concentration region 7b is a channeling region, the high-concentration region 7b may be an impurity region introduced parallel or nearly parallel to a region (axial channel) surrounded by atomic rows along a low-index crystal axis in the chip 2, and may be obliquely inclined with respect to the first main surface 3. The high-concentration region 7b may have a thickness greater than that of the low-concentration region 7a. Of course, the thickness of the high-concentration region 7b may be less than that of the low-concentration region 7a.

[0041] The semiconductor device 1 includes a first surface 8, a second surface 9, and first to fourth connection surface portions 10A to 10D formed on the first main surface 3. The first surface 8, the second surface 9, and the first to fourth connection surface portions 10A to 10D define mesas on the first main surface 3. The first surface 8, the second surface 9, and the first to fourth connection surface portions 10A to 10D (i.e., mesas) may be considered to be components of the chip 2 (first main surface 3).

[0042] The first surface portion 8 may be referred to as the "active surface," the second surface portion 9 may be referred to as the "outer surface," the first to fourth connecting surface portions 10A to 10D may be referred to as "connecting surfaces," and the mesa may be referred to as the "active mesa."

[0043] The first surface portion 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The first surface portion 8 has a flat surface extending horizontally and is formed by a c-plane (Si-plane). In this embodiment, the first surface portion 8 is formed in a polygonal shape (specifically, a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. The planar area of ​​the first surface portion 8 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0044] The second surface 9 is located closer to the periphery of the first main surface 3 than the first surface 8, and is recessed in the thickness direction of the chip 2 (toward the second main surface 4) from the height position of the first surface 8. The second surface 9 extends in a strip shape along the first surface 8 in a plan view, and is formed in a ring shape (specifically, a quadrangular ring) surrounding the first surface 8. The second surface 9 is continuous with the first to fourth side surfaces 5A to 5D.

[0045] The second surface 9 is formed substantially parallel to the first surface 8 and has a flat surface extending horizontally. In this embodiment, the second surface 9 is formed by the c-plane (Si-plane). The second surface 9 is formed in the second semiconductor region 7 at a distance from the first semiconductor region 6. In other words, the second surface 9 is recessed to a depth less than the thickness of the second semiconductor region 7, exposing the second semiconductor region 7.

[0046] In this embodiment, the second surface 9 is formed in the high-concentration region 7b at a distance from the low-concentration region 7a, exposing the high-concentration region 7b. That is, the first surface 8, the second surface 9, and the first to fourth connection surface portions 10A to 10D are formed by the high-concentration region 7b.

[0047] The second surface portion 9 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the second surface portion 9 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the second surface portion 9 is preferably 0.5 μm or more and 1.5 μm or less.

[0048] The first to fourth connection surface portions 10A to 10D extend in the vertical direction Z and are connected to the first surface portion 8 and the second surface portion 9. The first connection surface portion 10A is located on the first side surface 5A side, the second connection surface portion 10B is located on the second side surface 5B side, the third connection surface portion 10C is located on the third side surface 5C side, and the fourth connection surface portion 10D is located on the fourth side surface 5D side. The first connection surface portion 10A and the second connection surface portion 10B extend in the first direction X and face the second direction Y. The third connection surface portion 10C and the fourth connection surface portion 10D extend in the second direction Y and face the first direction X.

[0049] In this way, the mesa is defined in a protruding (convex) shape on the first main surface 3. The mesa is formed only in the second semiconductor region 7, and not in the first semiconductor region 6. The first to fourth connecting surface portions 10A to 10D may extend approximately perpendicularly between the first surface portion 8 and the second surface portion 9, defining a mesa shaped like a quadrangular pillar. The first to fourth connecting surface portions 10A to 10D may be inclined obliquely downward from the first surface portion 8 toward the second surface portion 9, defining a mesa shaped like a quadrangular pyramid. The first to fourth connecting surface portions 10A to 10D may be inclined at an angle greater than 90° and equal to or less than 135° with respect to the first surface portion 8.

[0050] The semiconductor device 1 includes an active region 11 set in a chip 2. The active region 11 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 11 is set in an inner portion of the chip 2. Specifically, the active region 11 is set in a first surface portion 8.

[0051] The semiconductor device 1 includes a peripheral region 12 set outside the active region 11 in the chip 2. The peripheral region 12 is a region that does not include a device structure (transistor structure Tr). The peripheral region 12 is set in the peripheral portion of the chip 2. Specifically, the peripheral region 12 is set in the second surface portion 9. In other words, the peripheral region 12 is set in the region between the peripheral edge of the first surface portion 8 and the peripheral edge of the second surface portion 9 in a plan view.

[0052] 5 to 7, the semiconductor device 1 includes a p-type body region 13 formed in a surface layer portion of the first surface portion 8 (first main surface 3) in the active region 11. The body region 13 may also be referred to as a "channel region," a "base region," or the like. A source potential is applied to the body region 13 as a second potential (low potential) different from a first potential (high potential). The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be ground potential or a potential other than ground potential.

[0053] The body region 13 is formed at a distance from the bottom of the second semiconductor region 7 toward the first surface portion 8, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The body region 13 is formed in a thickness range between the first main surface 3 and the high-concentration region 7b in a cross-sectional view.

[0054] That is, the body region 13 is formed in a region closer to the first main surface 3 than the depth position of the high-concentration region 7 b, and faces the low-concentration region 7 a across the high-concentration region 7 b. The body region 13 preferably has a thickness less than that of the high-concentration region 7 b. Of course, the thickness of the body region 13 may be greater than that of the high-concentration region 7 b.

[0055] The body region 13 is formed at a distance from the depth position of the second surface portion 9 toward the first surface portion 8. The body region 13 is formed in a layer extending along the first surface portion 8. In this embodiment, the body region 13 is formed over the entire first surface portion 8 and is exposed from the first to fourth connecting surfaces 10A to 10D. Of course, the body region 13 may also be formed at a distance inward from the periphery of the first surface portion 8.

[0056] The semiconductor device 1 includes an n-type source region 14 formed in a surface layer portion of the first surface portion 8 (first main surface 3) in the active region 11. A source potential is applied to the source region 14. The source region 14 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7 (low-concentration region 7a). The n-type impurity concentration of the source region 14 is preferably higher than the n-type impurity concentration of the high-concentration region 7b.

[0057] The source region 14 is formed in a surface layer portion of the body region 13. Specifically, the source region 14 is formed at a distance from the bottom of the body region 13 toward the first surface portion 8. That is, the source region 14 is formed in a region on the first surface portion 8 side with respect to the depth position of the body region 13 in a cross-sectional view. The source region 14 forms a channel of the transistor together with the second semiconductor region 7 in the body region 13.

[0058] The source region 14 extends in a layered manner along the first surface 8. In this embodiment, the source region 14 is formed at a distance inward from the periphery of the first surface 8. Therefore, the source region 14 is not exposed from the first to fourth connection surface portions 10A to 10D. Of course, the source region 14 may be formed over the entire surface of the first surface 8 and exposed from the first to fourth connection surface portions 10A to 10D.

[0059] The semiconductor device 1 includes a plurality of trench-type (trench electrode-type) gate structures 15 formed in the first surface portion 8 (first main surface 3) in the active region 11. The gate structures 15 may also be referred to as "first trench structures," "trench gate structures," or the like. A gate potential is applied to the plurality of gate structures 15 as a control potential. The plurality of gate structures 15 control inversion and non-inversion of a channel in the body region 13 in response to the gate potential.

[0060] The multiple gate structures 15 are arranged on the first surface portion 8 at intervals inward from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D). The multiple gate structures 15 are arranged at intervals in the first direction X (= m-axis direction) in plan view, and each extends in a strip-like manner in the second direction Y (= a-axis direction). In other words, the multiple gate structures 15 are arranged in a strip-like manner extending in the second direction Y (= a-axis direction) in plan view. The extension direction of the multiple gate structures 15 coincides with the off-direction of the SiC single crystal.

[0061] When the distance between the centers of the plurality of gate structures 15 in the horizontal direction (first direction X) is defined as the gate pitch, the gate pitch may be 1 μm or more and 3 μm or less. The gate pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less. The gate pitch is preferably 1.5 μm or more and 2.5 μm or less.

[0062] The plurality of gate structures 15 penetrate the body region 13 and the source region 14 to reach the second semiconductor region 7. That is, the body region 13 and the source region 14 are located on both sides of the plurality of gate structures 15. The plurality of gate structures 15 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0063] In this embodiment, the plurality of gate structures 15 are formed at intervals from the bottom of the high concentration region 7 b toward the first surface 8, and face a part of the low concentration region 7 a across a part of the high concentration region 7 b. In other words, the bottom walls of the plurality of gate structures 15 are located within the high concentration region 7 b (second semiconductor region 7).

[0064] In this embodiment, the plurality of gate structures 15 are formed substantially perpendicular to the first surface portion 8. Of course, the plurality of gate structures 15 may also be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0065] The side walls (long sides) of the plurality of gate structures 15 are each formed by the m-plane ((1-100) plane) of the SiC single crystal. Of course, the side walls (long sides) of the plurality of gate structures 15 may each be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 15. The side walls of the plurality of gate structures 15 are formed approximately perpendicular to the first main surface 3.

[0066] The bottom walls of the gate structures 15 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the gate structures 15 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the gate structures 15 may be curved in an arc shape toward the second main surface 4.

[0067] The inclination angle (absolute value) of the sidewall of the gate structure 15 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0068] The gate structure 15 may have a width of 0.1 μm to 1.5 μm. The width of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, and 1.25 μm to 1.5 μm. The width of the gate structure 15 is preferably 0.25 μm to 1.25 μm.

[0069] The gate structure 15 has a depth that is approximately equal to the depth of the second surface portion 9. Of course, the depth of the gate structure 15 may be greater than the depth of the second surface portion 9 or may be less than the depth of the second surface portion 9.

[0070] The depth of the gate structure 15 may be 0.1 μm or more and 3 μm or less. The depth of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less.

[0071] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0072] The following describes the configuration of one gate structure 15. The gate structure 15 includes a first trench 16, a first insulating film 17, and a first buried electrode 18. The first trench 16 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 15.

[0073] The first insulating film 17 covers the wall surface of the first trench 16. The first insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 17 includes a silicon oxide film made of an oxide of the chip 2.

[0074] The first insulating film 17 includes a first film portion and a second film portion. The first film portion coats the sidewall of the first trench 16 in a film-like manner. The second film portion coats the bottom wall of the first trench 16 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to that of the first film portion.

[0075] The first insulating film 17 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0076] The first buried electrode 18 is buried in the first trench 16 with the first insulating film 17 sandwiched therebetween. The first buried electrode 18 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The first buried electrode 18 faces the channel with the first insulating film 17 sandwiched therebetween. In other words, the first buried electrode 18 faces the second semiconductor region 7 (high concentration region 7 b), the body region 13, and the source region 14 with the first insulating film 17 sandwiched therebetween.

[0077] The first buried electrode 18 has an electrode surface exposed from the first trench 16. The electrode surface of the first buried electrode 18 is located closer to the bottom wall of the first trench 16 with respect to the height position of the first surface portion 8. The electrode surface of the first buried electrode 18 is located closer to the first main surface 3 with respect to the depth position of the bottom of the body region 13. The electrode surface of the first buried electrode 18 has a recess in an inner portion that tapers toward the bottom wall of the first trench 16.

[0078] The semiconductor device 1 includes a plurality of trench-type (trench electrode-type) source structures 20 formed in the first surface portion 8 (first main surface 3) in the active region 11. The source structures 20 may also be referred to as "second trench structures," "trench source structures," etc. A source potential is applied to the plurality of source structures 20.

[0079] The source structures 20 are respectively arranged in regions between the gate structures 15 at intervals in the first direction X from the gate structures 15, and face the gate structures 15 in the first direction X. That is, the source structures 20 and the gate structures 15 are alternately arranged in the first direction X in a plan view, and are arranged in stripes extending in the second direction Y (= the a-axis direction). The extending direction of the source structures 20 coincides with the off-direction of the SiC single crystal.

[0080] The source structures 20 each extend in a strip shape in the second direction Y in a plan view. The source structures 20 may penetrate either or both of the first connection surface portion 10A and the second connection surface portion 10B. Of course, the source structures 20 may be formed at intervals in the second direction Y from both the first connection surface portion 10A and the second connection surface portion 10B.

[0081] When the distance between the centers of the plurality of source structures 20 in the horizontal direction (first direction X) is defined as the source pitch, the source pitch is preferably approximately equal to the gate pitch of the plurality of gate structures 15. Of course, the source pitch may be larger than the gate pitch or smaller than the gate pitch.

[0082] The source pitch may be 1 μm or more and 3 μm or less. The source pitch may have a value belonging to at least one range of 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less. The source pitch is preferably 1.5 μm or more and 2.5 μm or less.

[0083] When the trench pitch is defined as the horizontal distance between the center of source structure 20 and the center of gate structure 15, the trench pitch may be 0.25 μm or more and 2 μm or less. The trench pitch may have a value belonging to at least one of the ranges of 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The trench pitch is preferably 0.5 μm or more and 1.5 μm or less.

[0084] The plurality of source structures 20 penetrate the body region 13 and the source region 14 to reach the second semiconductor region 7. That is, the body region 13 and the source region 14 are located on both sides of the plurality of source structures 20. The plurality of source structures 20 face the plurality of gate structures 15 with the body region 13 and the source region 14 interposed therebetween.

[0085] The plurality of source structures 20 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7. In this embodiment, the plurality of source structures 20 are formed at intervals from the bottom of the high concentration region 7 b toward the first surface portion 8, and face a portion of the low concentration region 7 a across a portion of the high concentration region 7 b. In other words, the bottom walls of the plurality of source structures 20 are located within the high concentration region 7 b (second semiconductor region 7).

[0086] In this embodiment, the plurality of source structures 20 are formed substantially perpendicular to the first surface portion 8. Of course, the plurality of source structures 20 may be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0087] The sidewalls (long sides) of the plurality of source structures 20 are each formed by the m-plane ((1-100) plane) of the SiC single crystal. Of course, the sidewalls (long sides) of the plurality of source structures 20 may each be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the source structures 20. The sidewalls of the plurality of source structures 20 are formed approximately perpendicular to the first main surface 3.

[0088] The bottom walls of the source structures 20 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the source structures 20 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the source structures 20 may be curved in an arc shape toward the second main surface 4.

[0089] The inclination angle (absolute value) of the sidewall of the source structure 20 relative to the vertical line may be 85° to 95°. The inclination angle may have a value belonging to at least one of the ranges of 85° to 87.5°, 87.5° to 90°, 90° to 92.5°, and 92.5° to 95°. The inclination angle is preferably 87° to 93°.

[0090] The source structure 20 has a width that is approximately equal to the width of the gate structure 15. Of course, the width of the source structure 20 may be greater than the width of the gate structure 15 or may be less than the width of the gate structure 15.

[0091] The width of the source structure 20 may be 0.1 μm or more and 1.5 μm or less. The width of the source structure 20 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, and 1.25 μm or more and 1.5 μm or less. The width of the source structure 20 is preferably 0.25 μm or more and 1.25 μm or less.

[0092] The source structure 20 has a depth approximately equal to the depth of the second surface portion 9. Of course, the depth of the source structure 20 may be greater than the depth of the second surface portion 9 or less than the depth of the second surface portion 9. It is preferable that the depth of the source structure 20 is approximately equal to the depth of the gate structure 15. Of course, the depth of the source structure 20 may be greater than the depth of the gate structure 15 or less than the depth of the gate structure 15.

[0093] The ratio (depth ratio) of the depth of source structure 20 to the depth of gate structure 15 is preferably 0.8 to 1.2. The depth ratio may have a value belonging to at least one of the ranges of 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, 0.95 to 1, 1 to 1.05, 1.05 to 1.1, 1.1 to 1.15, and 1.15 to 1.2. The depth ratio is preferably 0.95 to 1.05.

[0094] The depth of the source structure 20 may be 0.1 μm or more and 3 μm or less. The depth of the source structure 20 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the source structure 20 is preferably 0.5 μm or more and 1.5 μm or less.

[0095] The source structure 20 may have an aspect ratio of 1 to 3, inclusive. The aspect ratio of the source structure 20 is the ratio of the depth of the source structure 20 to the width of the source structure 20. The aspect ratio may have a value belonging to at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3, inclusive. Preferably, the aspect ratio is 1.5 to 2.5, inclusive.

[0096] The configuration of one source structure 20 will be described below. The source structure 20 includes a second trench 21, a second insulating film 22, and a second buried electrode 23. The second trench 21 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the source structure 20. When the second trench 21 is connected to either or both of the first connection surface portion 10A and the second connection surface portion 10B, the sidewall of the second trench 21 is connected to either or both of the first connection surface portion 10A and the second connection surface portion 10B, and the bottom wall of the second trench 21 is connected to the second surface portion 9.

[0097] The second insulating film 22 covers the wall surface of the second trench 21. The second insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating film 22 preferably includes the same type of insulating material as the insulating material of the first insulating film 17. In this embodiment, the second insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 22 includes a silicon oxide film made of an oxide of the chip 2.

[0098] The second insulating film 22 includes a first film portion and a second film portion. The first film portion coats the sidewall of the second trench 21 in a film-like manner. The second film portion coats the bottom wall of the second trench 21 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the second insulating film 22 may be approximately equal to the thickness of the first film portion of the first insulating film 17. The thickness of the second film portion of the second insulating film 22 may be approximately equal to the thickness of the second film portion of the first insulating film 17.

[0099] The second insulating film 22 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0100] The second buried electrode 23 is buried in the second trench 21 with the second insulating film 22 sandwiched therebetween. The second buried electrode 23 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The second buried electrode 23 preferably contains the same type of conductive material as the conductive material of the first buried electrode 18. The second buried electrode 23 faces the second semiconductor region 7 (high concentration region 7b), the body region 13, and the source region 14 with the second insulating film 22 sandwiched therebetween.

[0101] The second buried electrode 23 has an electrode surface exposed from the second trench 21. The electrode surface of the second buried electrode 23 is located closer to the bottom wall of the second trench 21 with respect to the height position of the first surface portion 8. The electrode surface of the second buried electrode 23 is located closer to the second main surface 4 with respect to the depth position of the bottom of the body region 13. The electrode surface of the second buried electrode 23 has a recess in an inner portion that tapers toward the bottom wall of the second trench 21.

[0102] The semiconductor device 1 includes a plurality of p-type column regions 25 (impurity regions) formed at intervals in the horizontal direction within the second semiconductor region 7. The plurality of column regions 25 include a plurality of gate column regions 25g (first impurity regions) and a plurality of source column regions 25s (second impurity regions). The gate column regions 25g may be referred to as "first impurity regions," "first column regions," etc. The source column regions 25s may be referred to as "second impurity regions," "second column regions," etc.

[0103] The multiple gate column regions 25g are formed by introducing a trivalent element (p-type impurity) into the second semiconductor region 7, thereby converting the conductivity type of the second semiconductor region 7 from n-type to p-type. In other words, the gate column regions 25g have a higher p-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the gate column regions 25g may be higher than the p-type impurity concentration of the body region 13. Of course, the p-type impurity concentration of the gate column regions 25g may be lower than the p-type impurity concentration of the body region 13.

[0104] The multiple gate column regions 25g are formed in the chip 2 (second semiconductor region 7) in regions directly below the multiple gate structures 15, spaced apart from one another in the first direction X. Specifically, the multiple gate column regions 25g are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple gate structures 15, and overlap the multiple gate structures 15 in a one-to-one correspondence in the thickness direction.

[0105] The gate column regions 25g are arranged in stripes extending in the second direction Y (= the a-axis direction) in a plan view. The extending direction of the gate column regions 25g coincides with the off-direction of the SiC single crystal. Of course, if the gate structures 15 extend in the first direction X, the gate column regions 25g may also extend in the first direction X. In this case, the gate column regions 25g intersect (specifically, are perpendicular to) the off-direction.

[0106] The plurality of gate column regions 25g are formed at intervals from the periphery of the first surface portion 8 (first to fourth connecting surface portions 10A to 10D) toward the inside of the first surface portion 8. Both end portions of the plurality of gate column regions 25g may be located on the inside side of the plurality of gate structures 15 relative to both end portions of the plurality of gate structures 15. Both end portions of the plurality of gate column regions 25g may be located on the periphery side of the first surface portion 8 relative to both end portions of the plurality of gate structures 15.

[0107] The plurality of gate column regions 25g are each formed in a columnar shape extending in the thickness direction of the chip 2 in a cross-sectional view. The plurality of gate column regions 25g may be made of a p-type channeling region extending along the axial channel of the chip 2 (second semiconductor region 7) in a cross-sectional view.

[0108] In this case, the plurality of gate column regions 25g are formed by introducing a trivalent element (p-type impurity) into the second semiconductor region 7 through the bottom walls of the plurality of gate structures 15 (first trenches 16). The plurality of gate column regions 25g are made of impurity regions introduced parallel or nearly parallel to a region (axial channel) surrounded by an atomic row along a low-index crystal axis (c-axis in this embodiment) in the chip 2 (second semiconductor region 7), and may be inclined obliquely with respect to the first main surface 3.

[0109] When the distance between the centers of the plurality of gate column regions 25g in the horizontal direction (first direction X) is defined as the gate column pitch, the gate column pitch is preferably approximately equal to the gate pitch of the plurality of gate structures 15. Of course, the gate column pitch may be larger than the gate pitch or smaller than the gate pitch.

[0110] The gate column pitch may be 1 μm or more and 3 μm or less. The gate column pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less. The gate column pitch is preferably 1.5 μm or more and 2.5 μm or less.

[0111] The ratio of the gate column pitch to the gate pitch (gate pitch ratio) may be 0.8 or more and 1.2 or less. The gate pitch ratio may have a value belonging to any one of the ranges of 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.1 or less, 1.1 or more and 1.15 or less, and 1.15 or more and 1.2 or less. The gate pitch ratio is preferably 0.9 or more and 1.1 or less.

[0112] The configuration of one gate column region 25g will be described below. The gate column region 25g has an upper end located on the bottom wall side of the gate structure 15 and a lower end (bottom) located on the bottom side of the second semiconductor region 7. The upper end of the gate column region 25g is located in a region on the bottom wall side of the gate structure 15 relative to the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall of the gate structure 15.

[0113] The upper end of the gate column region 25g is formed at a distance from the bottom side of the second semiconductor region 7 relative to the depth position of the second surface portion 9. The upper end of the gate column region 25g is formed at a distance from the bottom wall of the gate structure 15 to the bottom side of the second semiconductor region 7, and faces the plurality of gate structures 15 with part of the second semiconductor region 7 in between.

[0114] Specifically, the upper end of the gate column region 25g faces the gate structure 15 across a part of the heavily doped region 7b and is electrically connected to the heavily doped region 7b. Of course, the upper end of the gate column region 25g may also be connected to the bottom wall of the gate structure 15.

[0115] The upper end of the gate column region 25g may be formed with an upper end distance of 0 μm or more and 1 μm or less from the bottom wall of the gate structure 15. The upper end distance of the gate column region 25g may have a value belonging to at least one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0116] The lower end of the gate column region 25g is located in a region on the bottom side of the second semiconductor region 7 with respect to the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall of the gate structure 15. The lower end of the gate column region 25g is located within the low concentration region 7a across the bottom of the high concentration region 7b and is electrically connected to the low concentration region 7a.

[0117] That is, in this embodiment, the gate column region 25g has a portion (upper end) located within the high-concentration region 7b and a portion (lower end) located within the low-concentration region 7a. The cross-sectional area of ​​the portion of the gate column region 25g located within the high-concentration region 7b is preferably larger than the cross-sectional area of ​​the portion of the gate column region 25g located within the low-concentration region 7a. Of course, the cross-sectional area of ​​the portion of the gate column region 25g located within the high-concentration region 7b may be smaller than the cross-sectional area of ​​the portion of the gate column region 25g located within the low-concentration region 7a.

[0118] In this embodiment, the lower end of the gate column region 25g is formed at a distance from the bottom of the low concentration region 7a (first semiconductor region 6) toward the bottom of the high concentration region 7b, and faces the first semiconductor region 6 across a portion of the low concentration region 7a.

[0119] The lower end of the gate column region 25g may be formed at a distance of 0 μm to 2 μm from the bottom of the second semiconductor region 7. The lower end distance of the gate column region 25g may have a value belonging to at least one of the ranges of 0 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The lower end distance of the gate column region 25g may be greater than or less than the upper end distance of the gate column region 25g.

[0120] The gate column region 25g has a width approximately equal to that of the gate structure 15. Of course, the width of the gate column region 25g may be greater than or less than that of the gate structure 15. The width of the gate column region 25g may have a width approximately equal to that of the source structure 20. Of course, the width of the gate column region 25g may be greater than or less than that of the source structure 20.

[0121] The width of the gate column region 25g may be 0.1 μm or more and 1.5 μm or less. The width of the gate column region 25g may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, and 1.25 μm or more and 1.5 μm or less. The width of the gate column region 25g is preferably 0.25 μm or more and 1.25 μm or less.

[0122] The ratio of the width of the gate column region 25g to the width of the gate structure 15 (gate width ratio) may be 0.8 to 1.2. The gate width ratio may have a value belonging to any one of the following ranges: 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, 0.95 to 1, 1 to 1.05, 1.05 to 1.1, 1.1 to 1.15, and 1.15 to 1.2. The gate width ratio is preferably 0.9 to 1.1.

[0123] The gate column region 25g preferably has a depth greater than the depth of the second surface portion 9. Of course, the depth of the gate column region 25g may be less than the depth of the second surface portion 9. The depth of the gate column region 25g is preferably greater than the depth of the gate structure 15. Of course, the depth of the gate column region 25g may be less than the depth of the gate structure 15.

[0124] The depth of the gate column region 25g is preferably greater than the depth of the source structure 20. Of course, the depth of the gate column region 25g may be less than the depth of the source structure 20. The depth of the gate column region 25g is preferably greater than the depth of the high concentration region 7b. Of course, the depth of the gate column region 25g may be less than the depth of the high concentration region 7b.

[0125] The ratio of the depth of the gate column region 25g to the depth of the gate structure 15 (the depth of the source structure 20) (gate depth ratio) may be equal to or greater than 1 and equal to or less than 5. The gate depth ratio may have a value belonging to at least one of the ranges of 1 to 1.5, 1.5 to 2, 2 to 2.5, 2.5 to 3, 3 to 3.5, 3.5 to 4, 4 to 4.5, and 4.5 to 5.

[0126] The depth of the gate column region 25g is preferably 1 μm to 5 μm, and may be in at least one of the following ranges: 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0127] The gate column region 25g may have an aspect ratio of 1 to 10. The aspect ratio of the gate column region 25g is the ratio of the depth of the gate column region 25g to the width of the gate column region 25g. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0128] The source column region 25s is formed by introducing a trivalent element (p-type impurity) into the second semiconductor region 7, thereby converting the conductivity type of the second semiconductor region 7 from n-type to p-type. In other words, the source column region 25s has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the source column region 25s may be higher than the p-type impurity concentration of the body region 13. Of course, the p-type impurity concentration of the source column region 25s may be lower than the p-type impurity concentration of the body region 13.

[0129] The p-type impurity concentration of the source column region 25s is preferably approximately equal to that of the gate column region 25g. Of course, the p-type impurity concentration of the source column region 25s may be higher than that of the gate column region 25g, or may be lower than that of the gate column region 25g.

[0130] The source column regions 25s are formed in the chip 2 (second semiconductor region 7) in regions immediately below the source structures 20 at intervals from one another in the first direction X. Specifically, the source column regions 25s are formed in regions immediately below the source structures 20 at intervals from the gate column regions 25g in the first direction X.

[0131] Specifically, the source column regions 25s are each formed in a thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the source structures 20, and overlap the source structures 20 in a one-to-one correspondence in the thickness direction. The source column regions 25s are arranged alternately with the gate column regions 25g in the first direction X in plan view, and are arranged in stripes extending in the second direction Y (= the a-axis direction).

[0132] The extending direction of the multiple source column regions 25s coincides with the off-direction of the SiC single crystal. Of course, when the multiple source structures 20 extend in the first direction X, the multiple source column regions 25s may also extend in the first direction X. In this case, the multiple source column regions 25s intersect (specifically, are perpendicular to) the off-direction.

[0133] Both end portions of the plurality of source column regions 25s may be located inward of the plurality of source structures 20 with respect to both end portions of the plurality of source structures 20. Both end portions of the plurality of source column regions 25s may be located on the peripheral edge side of the first surface portion 8 with respect to both end portions of the plurality of source structures 20.

[0134] The source column regions 25s may be exposed from either or both of the first connecting surface portion 10A and the second connecting surface portion 10B. Of course, the source column regions 25s may be formed at intervals in the second direction Y from both the first connecting surface portion 10A and the second connecting surface portion 10B.

[0135] The plurality of source column regions 25s face the plurality of gate column regions 25g across parts of the second semiconductor region 7 in the first direction X. In this embodiment, the plurality of source column regions 25s face the plurality of gate column regions 25g across parts of the low concentration region 7a and the high concentration region 7b of the second semiconductor region 7.

[0136] The multiple source column regions 25s are each formed in a columnar shape extending in the thickness direction of the chip 2 in a cross-sectional view. The multiple source column regions 25s may be made of p-type channeling regions extending along the axial channel of the chip 2 (second semiconductor region 7) in a cross-sectional view.

[0137] In this case, the multiple source column regions 25s are formed by introducing a trivalent element (p-type impurity) into the second semiconductor region 7 through the bottom walls of the multiple source structures 20 (second trenches 21). The multiple source column regions 25s are made of impurity regions introduced parallel or nearly parallel to a region (axial channel) surrounded by atomic rows along a low-index crystal axis (c-axis in this embodiment) in the chip 2 (second semiconductor region 7), and may be inclined obliquely with respect to the first main surface 3.

[0138] When the distance between the centers of the plurality of source column regions 25s in the horizontal direction (first direction X) is defined as the source column pitch, the source column pitch is preferably approximately equal to the source pitch of the plurality of source structures 20. Of course, the source column pitch may be larger than the source pitch or smaller than the source pitch.

[0139] The source column pitch may be 1 μm or more and 3 μm or less. The source column pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less. The source column pitch is preferably 1.5 μm or more and 2.5 μm or less.

[0140] The ratio of the source column pitch to the source pitch (source pitch ratio) may be 0.8 or more and 1.2 or less. The source pitch ratio may have a value belonging to any one of the ranges of 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.1 or less, 1.1 or more and 1.15 or less, and 1.15 or more and 1.2 or less. The source pitch ratio is preferably 0.9 or more and 1.1 or less.

[0141] When the horizontal distance between the center of the gate column region 25g and the center of the source column region 25s is defined as the column pitch, the column pitch is preferably approximately equal to the trench pitch between the gate structure 15 and the source structure 20. Of course, the column pitch may be larger than the trench pitch or smaller than the trench pitch.

[0142] The column pitch may be 0.25 μm or more and 2 μm or less. The column pitch may have a value belonging to at least one of the ranges of 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. The column pitch is preferably 0.5 μm or more and 1.5 μm or less.

[0143] The ratio of the column pitch to the trench pitch (pitch ratio) may be 0.8 or more and 1.2 or less. The pitch ratio may have a value belonging to any one of the ranges of 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.1 or less, 1.1 or more and 1.15 or less, and 1.15 or more and 1.2 or less. The pitch ratio is preferably 0.9 or more and 1.1 or less.

[0144] The configuration of one source column region 25s will be described below. The source column region 25s has an upper end located on the bottom wall side of the source structure 20 and a lower end (bottom) located on the bottom side of the second semiconductor region 7. The upper end of the source column region 25s is located in a region on the bottom wall side of the source structure 20 relative to an intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall of the source structure 20.

[0145] The upper end of the source column region 25s is formed at a distance from the bottom side of the second semiconductor region 7 relative to the depth position of the second surface portion 9. The upper end of the source column region 25s is formed at a distance from the bottom wall of the source structure 20 to the bottom side of the second semiconductor region 7, and faces the multiple source structures 20 with part of the second semiconductor region 7 in between.

[0146] Specifically, the upper end of the source column region 25 s faces the source structure 20 across a part of the high-concentration region 7 b and is electrically connected to the high-concentration region 7 b. Of course, the upper end of the source column region 25 s may also be connected to the bottom wall of the source structure 20.

[0147] The upper end of the source column region 25 s is preferably located at a depth substantially equal to the depth of the upper end of the gate column region 25 g. Of course, the depth of the upper end of the source column region 25 s may be located closer to the bottom wall of the source structure 20 than the depth of the upper end of the gate column region 25 g, or may be located closer to the bottom of the second semiconductor region 7 than the depth of the upper end of the gate column region 25 g.

[0148] The upper end of the source column region 25s may be formed at an upper end distance of 0 μm or more and 1 μm or less from the bottom wall of the source structure 20. The upper end distance of the source column region 25s may have a value belonging to at least one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0149] The lower end of the source column region 25s is located in a region on the bottom side of the second semiconductor region 7 with respect to the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall of the source structure 20. The lower end of the source column region 25s is located within the low concentration region 7a across the bottom of the high concentration region 7b and is electrically connected to the low concentration region 7a.

[0150] That is, in this embodiment, the source column region 25s has a portion (upper end) located within the high-concentration region 7b and a portion (lower end) located within the low-concentration region 7a. The cross-sectional area of ​​the portion of the source column region 25s located within the high-concentration region 7b is preferably larger than the cross-sectional area of ​​the portion of the source column region 25s located within the low-concentration region 7a. Of course, the cross-sectional area of ​​the portion of the source column region 25s located within the high-concentration region 7b may be smaller than the cross-sectional area of ​​the portion of the source column region 25s located within the low-concentration region 7a.

[0151] In this embodiment, the lower end of the source column region 25 s is formed at a distance from the bottom of the low-concentration region 7 a (first semiconductor region 6) toward the bottom of the high-concentration region 7 b, and faces the first semiconductor region 6 with a part of the low-concentration region 7 a in between.

[0152] The lower end of the source column region 25 s is preferably located at a depth substantially equal to the depth of the lower end of the gate column region 25 g. Of course, the depth of the lower end of the source column region 25 s may be located closer to the bottom wall of the source structure 20 than the depth of the lower end of the gate column region 25 g, or may be located closer to the bottom of the second semiconductor region 7 than the depth of the lower end of the gate column region 25 g.

[0153] The lower end of the source column region 25s may be formed at a distance of 0 μm or more and 5 μm or less from the bottom of the second semiconductor region 7. The lower end distance of the source column region 25s may have a value belonging to at least one of the ranges of 0 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The lower end distance of the source column region 25s may be greater than or less than the upper end distance of the source column region 25s.

[0154] The source column region 25s has a width approximately equal to the width of the source structure 20. Of course, the width of the source column region 25s may be greater than the width of the source structure 20 or less than the width of the source structure 20. The source column region 25s may have a width approximately equal to the width of the gate structure 15. Of course, the width of the source column region 25s may be greater than the width of the gate structure 15 or less than the width of the gate structure 15.

[0155] The width of the source column region 25s is preferably approximately equal to the width of the gate column region 25g, but may of course be greater than or less than the width of the gate column region 25g.

[0156] The width of the source column region 25s may be 0.1 μm or more and 1.5 μm or less. The width of the source column region 25s may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, and 1.25 μm or more and 1.5 μm or less. The width of the source column region 25s is preferably 0.25 μm or more and 1.25 μm or less.

[0157] The ratio of the width of the source column region 25s to the width of the source structure 20 (source width ratio) may be 0.8 to 1.2. The source width ratio may have a value belonging to any one of the ranges of 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, 0.95 to 1, 1 to 1.05, 1.05 to 1.1, 1.1 to 1.15, and 1.15 to 1.2. The source width ratio is preferably 0.9 to 1.1.

[0158] The source column region 25s preferably has a depth greater than the depth of the second surface portion 9. Of course, the depth of the source column region 25s may be less than the depth of the second surface portion 9. The source column region 25s preferably has a depth greater than the depth of the source structure 20. Of course, the depth of the source column region 25s may be less than the depth of the source structure 20.

[0159] The depth of the source column region 25s is preferably greater than the depth of the gate structure 15. Of course, the depth of the source column region 25s may be less than the depth of the gate structure 15. The depth of the source column region 25s is preferably greater than the depth of the heavily doped region 7b. Of course, the depth of the source column region 25s may be less than the depth of the heavily doped region 7b.

[0160] The depth of the source column region 25s is preferably approximately equal to the depth of the gate column region 25g, but may of course be greater than or less than the depth of the gate column region 25g.

[0161] The ratio of the depth of the source column region 25s to the depth of the source structure 20 (the depth of the gate structure 15) (source depth ratio) may be from 1 to 5. The source depth ratio may have a value belonging to at least one of the ranges of from 1 to 1.5, from 1.5 to 2, from 2 to 2.5, from 2.5 to 3, from 3 to 3.5, from 3.5 to 4, from 4 to 4.5, and from 4.5 to 5.

[0162] The depth of the source column region 25s is preferably 1 μm or more and 5 μm or less. The depth of the source column region 25s may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0163] The source column regions 25s may have an aspect ratio of 1 to 10. The aspect ratio of the source column regions 25s is the ratio of the depth of the source column regions 25s to the width of the source column regions 25s. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0164] The p-type concentration gradient of the multiple column regions 25 (gate column regions 25g and source column regions 25s) will be described below. FIG. 10 is a graph showing an example of the concentration gradient of the column regions 25. FIG. 10 shows the concentration gradient when the column regions 25 are formed by channeling implantation. In FIG. 10, the vertical axis represents the p-type impurity concentration of the column regions 25, and the horizontal axis represents the depth of the column regions 25, with the bottom wall of the gate structure 15 (the bottom wall of the source structure 20) serving as the reference (zero point).

[0165] The values ​​of the impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of the column region 25 based on the concentration gradient, and are not intended to uniquely limit the configuration of the column region 25. The impurity concentration, thickness, etc. are adjusted to various values ​​depending on the implantation conditions of the trivalent element (dose amount, implantation temperature, implantation energy, etc.).

[0166] 10 shows a first concentration gradient G1 and a second concentration gradient G2. The first concentration gradient G1 represents the concentration gradient in the column region 25 when a trivalent element is introduced into the chip 2 (second semiconductor region 7) with an energy of 500 KeV or more and 800 KeV or less. The second concentration gradient G2 represents the concentration gradient in the column region 25 when a trivalent element is introduced into the chip 2 (second semiconductor region 7) with an energy of 900 KeV or more and 1200 KeV or less.

[0167] In the first concentration gradient G1 and the second concentration gradient G2, １５ cm －３ The region having a p-type impurity concentration of 1×10 or more is defined as the column region 25. The trivalent element is aluminum, and the dose of the trivalent element is 1×10 １３ cm －２ The thickness of the second semiconductor region 7 is about 5 μm, and the depth of the gate structure 15 (the depth of the source structure 20) is about 1 μm.

[0168] With reference to the first concentration gradient G1, the column region 25 has a thickness of 2.5 μm or more and 2.8 μm or less, and has an upper end spaced from the bottom wall of the gate structure 15 (the bottom wall of the source structure 20) toward the bottom of the second semiconductor region 7, and a lower end spaced from the bottom of the second semiconductor region 7 toward the upper end. The upper end of the column region 25 is formed at a distance of 0.2 μm or more and 0.3 μm or less from the bottom wall of the gate structure 15 (the bottom wall of the source structure 20). The lower end of the column region 25 is formed at a distance of 1 μm or more and 1.2 μm or less from the bottom of the second semiconductor region 7.

[0169] The column region 25 has a concentration gradient from the upper end side to the lower end side, which includes a gradually increasing portion 26, a peak portion 27, a gradual portion 28, and a gradually decreasing portion 29. The gradually increasing portion 26 is a portion that forms the upper end of the column region 25, and the p-type impurity concentration gradually increases at a relatively steep rate from the upper end to the lower end side up to the peak portion 27. In this embodiment, the gradually increasing portion 26 is located within the high concentration region 7b and is electrically connected to the high concentration region 7b.

[0170] The peak portion 27 is a portion having a peak value P (maximum value) of the p-type impurity concentration. The peak portion 27 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend). The peak portion 27 is electrically connected to the high-concentration region 7 b.

[0171] The gradual portion 28 is formed in a region closer to the lower end than the peak portion 27, and is a portion where the impurity concentration gradually decreases at a relatively gradual rate. In other words, the gradual portion 28 is a portion where a constant p-type impurity concentration is maintained within a certain depth range, and forms the main body of the gate column region 25g. The p-type impurity concentration of the gradual portion 28 gradually decreases within a concentration range that is less than the p-type impurity concentration of the peak portion 27.

[0172] The gradual portion 28 is defined by a portion having a density decrease rate of 50% or less in a thickness range of at least 0.5 μm. In the example of FIG. 10 , the gradual portion 28 has a thickness of 1 μm or more and 1.3 μm or less, and has a density decrease rate of 50% or less in that thickness range. The gradual portion 28 is located within the high-concentration region 7 b and is electrically connected to the high-concentration region 7 b. The gradual portion 28 may have a portion located within the low-concentration region 7 a and be electrically connected to the low-concentration region 7 a.

[0173] The gradual portions 28 occupy a thickness range of at least one-quarter of the column region 25. Specifically, the proportion of the gradual portions 28 in the column region 25 is at least one-third. The proportion of the gradual portions 28 in the column region 25 is typically at most one-half (less than one-half). Of course, the proportion of the gradual portions 28 in the column region 25 may be at least one-half.

[0174] The gradually tapering portion 29 is a portion that forms the lower end of the column region 25. The gradually tapering portion 29 has a concentration decrease rate that is greater than that of the gradual portion 28, and is a portion where the p-type impurity concentration gradually decreases from the gradual portion 28 toward the lower end. The concentration decrease rate per unit thickness of the gradually tapering portion 29 is greater than that of the gradual portion 28. The gradually tapering portion 29 is located within the low-concentration region 7a and is electrically connected to the low-concentration region 7a.

[0175] With reference to the second concentration gradient G2, the column region 25 has a thickness of 3.1 μm or more and 3.2 μm or less, and has an upper end spaced from the bottom wall of the gate structure 15 (the bottom wall of the source structure 20) toward the bottom of the second semiconductor region 7, and a lower end spaced from the bottom of the second semiconductor region 7 toward the upper end. The upper end of the column region 25 is formed at a distance of 0.4 μm or more and 0.5 μm or less from the bottom wall of the gate structure 15 (the bottom wall of the source structure 20). The lower end of the column region 25 is formed at a distance of 0.4 μm or more and 0.6 μm or less from the bottom of the second semiconductor region 7.

[0176] Similar to the first concentration gradient G1, the column region 25 has a concentration gradient that includes a gradually increasing portion 26, a peak portion 27, a gradual portion 28, and a gradually decreasing portion 29 from the upper end side to the lower end side. The gradually increasing portion 26, the peak portion 27, the gradual portion 28, and the gradual decreasing portion 29 are all shifted closer to the bottom of the second semiconductor region 7 than in the case of the first concentration gradient G1. The peak value P of the peak portion 27 is lower than in the case of the first concentration gradient G1. The thickness of the gradual portion 28 is 1.4 μm or more and 1.5 μm or less, which is greater than in the case of the first concentration gradient G1.

[0177] In the case of channeling implantation, the thickness (depth) of the column region 25 increases with increasing implantation energy. The depth position of the upper end of the gate column region 25g relative to the bottom wall of the gate structure 15 increases with increasing implantation energy. The thicknesses of the gradually increasing portion 26, the peak portion 27, the gradual portion 28, and the gradually decreasing portion 29 increase with increasing implantation energy. On the other hand, the peak value P of the peak portion 27 decreases with increasing implantation energy. This is because the trivalent element is introduced into a relatively deep region with increasing implantation energy, increasing the p-type impurity concentration in that deep region.

[0178] 11 is a graph showing another example of the concentration gradient in the column region 25. This graph shows the concentration gradient when the column region 25 is formed by random implantation. The random implantation is a method of introducing a trivalent element into the chip 2 (second semiconductor region 7) in a random direction. The random direction is a direction (for example, the vertical direction Z) that intersects with the axial channel of the chip 2 (second semiconductor region 7).

[0179] In FIG. 11, the vertical axis indicates the p-type impurity concentration of the column region 25, and the horizontal axis indicates the depth of the column region 25 with the bottom wall of the gate structure 15 (bottom wall of the source structure 20) as the reference (zero point).

[0180] 11 shows a third concentration gradient G3 and a fourth concentration gradient G4. The third concentration gradient G3 represents the concentration gradient in the column region 25 when a trivalent element is introduced into the chip 2 (second semiconductor region 7) with an energy of 500 KeV or more and 800 KeV or less. The fourth concentration gradient G4 represents the concentration gradient in the column region 25 when a trivalent element is introduced into the chip 2 (second semiconductor region 7) with an energy of 900 KeV or more and 1200 KeV or less.

[0181] In the third concentration gradient G3 and the fourth concentration gradient G4, １５ cm －３ The region having a p-type impurity concentration of 100 or more is defined as a column region 25 and is shown in the figure. The trivalent element is aluminum, and the dose of the trivalent element is 1×10 １３ cm －２The thickness of the second semiconductor region 7 is about 5 μm, and the depth of the gate structure 15 (the depth of the source structure 20) is about 1 μm.

[0182] With reference to the third concentration gradient G3 and the fourth concentration gradient G4, in the case of the random implantation method, the column region 25 had a gradually increasing portion 26, a peak portion 27 (peak value P), and a gradually decreasing portion 29 within a range of 0.5 μm, but did not have a gradual portion 28 having a thickness of 0.5 μm or more. Furthermore, in the case of the random implantation method, the formation location of the column region 25 shifted toward the bottom of the second semiconductor region 7 as the implantation energy increased, but the thickness of the column region 25 was always less than 2 μm. In other words, the thickness of the column region 25 did not fluctuate significantly even when the implantation energy was increased.

[0183] From this, it can be understood that in the case of the random implantation method, it is difficult to achieve charge balance in the column region 25 consisting of a single impurity region. Unlike Si single crystal, SiC single crystal has physical properties that make it difficult for impurities to diffuse. Therefore, the above problem is generally solved by the multi-epitaxial growth method or the multi-stage random implantation method.

[0184] In the multi-epitaxial growth method, a step of introducing a trivalent element into an epitaxial layer having a relatively small thickness (for example, a thickness of less than 1 μm) by random implantation is repeated multiple times, which increases the number of epitaxial growth steps and random implantation steps, making the manufacturing process more complicated.

[0185] In the multi-stage random implantation method, a step of introducing a trivalent element into different depth positions in multiple stages using multiple implantation energies is carried out. In this process, the trivalent element can be introduced into the target depth position, but the depth position to which the trivalent element can be introduced is shallow. Therefore, the number of introduction stages (number of steps) using the random implantation method must be increased, which makes the manufacturing process more complicated.

[0186] In contrast, in the case of the channeling implantation method, a column region 25 having a relatively thick relaxed portion 28 is formed. Therefore, in the case of the channeling implantation method, the column region 25 having charge balance is formed with fewer steps than in the case of employing the random implantation method.

[0187] That is, the semiconductor device 1 preferably includes column regions 25 (gate column regions 25g and source column regions 25s) made of channeling regions. In this case, the semiconductor device 1 may include column regions 25 (gate column regions 25g and source column regions 25s) made of a plurality of channeling regions (impurity regions) introduced in multiple stages in the thickness direction of the second semiconductor region 7.

[0188] Of course, the semiconductor device 1 may have a column region 25 (gate column region 25 g and source column region 25 s) including a plurality of random regions (impurity regions) introduced in multiple stages in the thickness direction of the second semiconductor region 7 by a random injection method.

[0189] The semiconductor device 1 includes a plurality of n-type intermediate drift regions 30 formed in the second semiconductor region 7. Each of the plurality of intermediate drift regions 30 is composed of a region defined by a plurality of column regions 25 of the second semiconductor region 7. In other words, the plurality of intermediate drift regions 30 is defined into regions between a plurality of gate column regions 25g and a plurality of source column regions 25s.

[0190] The multiple intermediate drift regions 30 are partitioned at intervals in the first direction X (m-axis direction) within the second semiconductor region 7 and extend in strip-like shapes in the second direction Y (a-axis direction). Each of the multiple intermediate drift regions 30 is formed by a part of the second semiconductor layer. In this embodiment, the multiple intermediate drift regions 30 are formed by a part of the low-concentration region 7 a and a part of the high-concentration region 7 b.

[0191] The intermediate drift regions 30 form a plurality of first pn junctions with the gate column regions 25g and a plurality of second pn junctions with the source column regions 25s. The intermediate drift regions 30 form a charge balance together with the gate column regions 25g and the source column regions 25s.

[0192] Charge balance refers to a state in which, with respect to a gate column region 25 g and a source column region 25 s adjacent to each other across one intermediate drift region 30, the depletion layer extending from the first pn junction and the depletion layer extending from the second pn junction are connected within the intermediate drift region 30 when a reverse bias voltage is applied.

[0193] The semiconductor device 1 includes a plurality of contact regions 35 formed in the chip 2 (second semiconductor region 7). The plurality of contact regions 35 include a plurality of gate contact regions 35g and a plurality of source contact regions 35s.

[0194] The multiple gate contact regions 35g are formed in regions along the multiple gate structures 15 in the chip 2 (second semiconductor region 7). The gate contact regions 35g have a p-type impurity concentration higher than the p-type impurity concentration of the body region 13. The p-type impurity concentration of the gate contact regions 35g is preferably higher than the p-type impurity concentration of the column region 25 (gate column region 25g).

[0195] The plurality of gate contact regions 35g are formed in regions along the plurality of gate structures 15, spaced apart from the plurality of source structures 20. The plurality of gate contact regions 35g are formed in a one-to-many correspondence with the plurality of gate structures 15. The plurality of gate contact regions 35g are interposed in regions between the bottom walls of the plurality of gate structures 15 and the upper ends of the plurality of gate column regions 25g, and are formed at intervals in the second direction Y.

[0196] With respect to one gate structure 15 and the other gate structure 15, the multiple gate contact regions 35g along one gate structure 15 face the multiple gate contact regions 35g along the other gate structure 15 in the first direction X in a plan view. In other words, the multiple gate contact regions 35g are generally arranged in a matrix at intervals in the first direction X and the second direction Y in a plan view.

[0197] In this embodiment, the gate contact regions 35g extend in a strip shape along the gate structures 15 in a plan view. The lengths of the gate contact regions 35g in the second direction Y may be equal to or different from one another. The lengths of the gate contact regions 35g in the second direction Y are adjusted depending on the channel area to be formed.

[0198] The channel area is the total area of ​​the portions of the source region 14 exposed from the regions between the gate structures 15 and the source structures 20. That is, the channel area increases or decreases depending on the ratio of the total planar area of ​​the gate contact regions 35g. The total planar area of ​​the gate contact regions 35g is preferably less than the channel area.

[0199] That is, in the region between one adjacent gate structure 15 and one adjacent source structure 20, the total planar area of ​​the plurality of gate contact regions 35g is preferably less than the planar area of ​​the source region 14. With this configuration, an increase in the resistance value (on-resistance) due to a short channel is suppressed.

[0200] The length of the plurality of gate contact regions 35g may be greater than or less than the width of the gate structure 15. The length of the plurality of gate contact regions 35g may be greater than or less than the gate pitch of the plurality of gate structures 15.

[0201] The spacing between the multiple gate contact regions 35g in the second direction Y is preferably larger than the width of the gate structure 15. Of course, the spacing between the multiple gate contact regions 35g in the second direction Y may be smaller than the width of the gate structure 15. The spacing between the multiple gate contact regions 35g may be larger or smaller than the gate pitch.

[0202] The configuration of one gate contact region 35g will be described below. The gate contact region 35g is connected to the bottom wall of the corresponding gate structure 15 and the upper end of the corresponding gate column region 25g. The gate contact region 35g extends from the region directly below the gate structure 15 to both sides of the gate structure 15 and has extending portions that extend in the vertical direction Z along the sidewalls of the gate structure 15.

[0203] It is preferable that the thickness in the horizontal direction (first direction X) of the portion (extension) of the gate contact region 35g that runs along the side wall of the gate structure 15 is less than the thickness in the vertical direction Z of the portion of the gate contact region 35g that runs along the bottom wall of the gate structure 15.

[0204] The extension of the gate contact region 35g is electrically connected to the body region 13 in the surface layer portion of the first surface portion 8, and electrically connects the corresponding gate column region 25g to the body region 13. This prevents the gate column region 25g from being electrically floating, and improves the electrical response characteristics of the gate column region 25g.

[0205] The gate contact region 35g has an upper end exposed from the first surface portion 8. In this embodiment, the upper end of the gate contact region 35g is exposed from the sidewall of the first trench 16 at the opening end of the first trench 16. The upper end of the gate contact region 35g may extend horizontally in the surface layer portion of the body region 13.

[0206] The multiple source contact regions 35s are formed in regions along the multiple source structures 20 in the chip 2 (second semiconductor region 7). The source contact regions 35s have a p-type impurity concentration higher than the p-type impurity concentration of the body region 13. The p-type impurity concentration of the source contact regions 35s is preferably higher than the p-type impurity concentration of the column region 25 (source column region 25s).

[0207] The p-type impurity concentration of the source contact region 35s is preferably approximately equal to the p-type impurity concentration of the gate contact region 35g. Of course, the p-type impurity concentration of the source contact region 35s may be higher than the p-type impurity concentration of the gate contact region 35g, or may be lower than the p-type impurity concentration of the gate contact region 35g.

[0208] The source contact regions 35s are formed in regions along the source structures 20, spaced apart from the gate structures 15. The source contact regions 35s have a planar layout that is different from the planar layout of the gate contact regions 35g. In this embodiment, the source contact regions 35s are formed in a one-to-one correspondence with the source structures 20.

[0209] The multiple source contact regions 35s are respectively interposed in regions between the bottom walls of the corresponding source structures 20 and the upper ends of the corresponding source column regions 25s, and extend in a strip-like shape in the second direction Y. In other words, the multiple source contact regions 35s are formed in stripes extending along the multiple source structures 20 in a plan view.

[0210] That is, the source contact regions 35s have lengths in the second direction Y that are greater than the lengths of the gate contact regions 35g, and cross the gate structures 15 in the second direction Y. The source contact regions 35s may have lengths in the second direction Y that are greater than the lengths of the source structures 20, or may have lengths that are smaller than the lengths of the source structures 20.

[0211] The source contact regions 35s preferably have a total planar area greater than the total planar area of ​​the gate contact regions 35g. The total planar area of ​​the source contact regions 35s may be greater than or less than the channel area.

[0212] The configuration of one source contact region 35s will be described below. Each source contact region 35s is connected to the bottom wall of the corresponding source structure 20 and the upper end of the corresponding source column region 25s. The multiple source contact regions 35s extend from the region directly below the source structure 20 to both sides of the source structure 20 and have extending portions that extend along the sidewalls of the source structure 20.

[0213] It is preferable that the thickness in the horizontal direction (first direction X) of the portion (extension) of the source contact region 35s along the side wall of the source structure 20 is less than the thickness in the vertical direction Z of the portion of the source contact region 35s along the bottom wall of the source structure 20.

[0214] The extending portion of the source contact region 35s is electrically connected to the body region 13 in the surface layer portion of the first surface portion 8 (first main surface 3), and electrically connects the corresponding source column region 25s to the body region 13. This prevents the source column region 25s from being electrically floating, and improves the electrical response characteristics of the source column region 25s.

[0215] The source contact region 35s has an upper end exposed from the first surface portion 8. In this embodiment, the upper end of the source contact region 35s is exposed from the sidewall of the second trench 21 at the opening end of the second trench 21. The upper end of the source contact region 35s may extend horizontally in a surface layer portion of the body region 13. The upper end of the source contact region 35s is electrically connected to the upper end of the gate contact region 35g in the body region 13. In this embodiment, the upper end of the source contact region 35s is formed integrally with the upper end of the gate contact region 35g.

[0216] The semiconductor device 1 includes a main surface insulating film 40 covering the first main surface 3. The main surface insulating film 40 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 40 preferably includes the same type of insulating material as either or both of the insulating material of the first insulating film 17 and the insulating material of the second insulating film 22. In this embodiment, the main surface insulating film 40 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 40 include a silicon oxide film made of an oxide of the chip 2.

[0217] The main surface insulating film 40 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D. The main surface insulating film 40 is selectively connected to the first insulating films 17 of the plurality of gate structures 15 and the second insulating films 22 of the plurality of source structures 20 on the first surface portion 8, and exposes the first buried electrodes 18 of the plurality of gate structures 15 and the second buried electrodes 23 of the plurality of source structures 20.

[0218] In this embodiment, the main surface insulating film 40 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral portion of the second surface portion 9. Of course, the main surface insulating film 40 may be formed at a distance inward from the peripheral portion of the second surface portion 9, exposing the second semiconductor region 7 from the peripheral portion of the second surface portion 9.

[0219] The semiconductor device 1 includes an insulating interlayer film 41 that covers the main surface insulating film 40. The interlayer film 41 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 41 preferably includes a silicon oxide film.

[0220] The interlayer film 41 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connecting surface portions 10A to 10D with the main surface insulating film 40 sandwiched therebetween. The interlayer film 41 covers the plurality of gate structures 15 (first buried electrodes 18) on the first surface portion 8 and selectively exposes the plurality of source structures 20 (second buried electrodes 23). In this embodiment, the interlayer film 41 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the second surface portion 9. Of course, the interlayer film 41 may be formed at a distance inward from the periphery of the second surface portion 9, exposing the second semiconductor region 7 from the periphery of the second surface portion 9.

[0221] The interlayer film 41 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer film 41 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0222] The semiconductor device 1 includes a plurality of source openings 42 formed in an interlayer film 41. The plurality of source openings 42 are formed in regions between the plurality of gate structures 15, and each exposes a corresponding one of the source structures 20 in a one-to-one correspondence. Each of the plurality of source openings 42 exposes a corresponding one of the source structures 20, the source region 14, and the plurality of source contact regions 35s. Each of the plurality of source openings 42 extends in a strip shape in the second direction Y along the corresponding source structure 20. Preferably, each of the plurality of source openings 42 has an opening end that is curved in an arc shape.

[0223] Of course, a plurality of source openings 42 may be formed in a one-to-many correspondence with one corresponding source structure 20. In this case, the plurality of source openings 42 may be formed at intervals in the second direction Y along the corresponding source structure 20. Furthermore, in this case, the plurality of source openings 42 may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, or the like in a plan view.

[0224] The semiconductor device 1 includes a plurality of gate openings 43 formed in an interlayer film 41 (see FIG. 4). The plurality of gate openings 43 are formed in regions between the plurality of source structures 20, and each of the plurality of gate openings 43 exposes one corresponding gate structure 15 in a one-to-many correspondence. In this embodiment, the plurality of gate openings 43 expose one end and the other end of the corresponding gate structure 15 (first buried electrode 18).

[0225] The gate openings 43 preferably each have an opening end that is curved in an arc shape, similar to the source openings 42. The gate openings 43 may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, or the like, in a plan view.

[0226] The semiconductor device 1 includes a source electrode 45 disposed on the first main surface 3. The source electrode 45 is a terminal electrode to which a source potential is applied from the outside. The source electrode 45 may also be referred to as a "source pad electrode," a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like. The source electrode 45 is disposed on a portion of the interlayer film 41 that covers the first surface portion 8.

[0227] In this embodiment, the source electrode 45 has a first pad portion 45 a, a second pad portion 45 b, and a third pad portion 45 c. The first pad portion 45 a has a relatively large planar area and forms the main body of the source electrode 45. In this embodiment, the first pad portion 45 a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first surface portion 8.

[0228] The second pad portion 45b has a planar area smaller than that of the first pad portion 45a, and is drawn out in a strip shape (rectangular shape) from one end of the first pad portion 45a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 45c has a planar area smaller than that of the first pad portion 45a, and is drawn out in a strip shape (rectangular shape) from the other end of the first pad portion 45a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 45b in the second direction Y.

[0229] The plane area of ​​the third pad portion 45c may be approximately equal to the plane area of ​​the second pad portion 45b. Of course, the plane area of ​​the third pad portion 45c may be larger than the plane area of ​​the second pad portion 45b, or may be smaller than the plane area of ​​the second pad portion 45b. Either or both of the second pad portion 45b and the third pad portion 45c may be used as a terminal portion for monitoring current.

[0230] The source electrode 45 does not necessarily have to have both the second pad portion 45 b and the third pad portion 45 c at the same time. The source electrode 45 may have only one of the second pad portion 45 b and the third pad portion 45 c. Of course, the source electrode 45 may be composed of only the first pad portion 45 a, and may not have both the second pad portion 45 b and the third pad portion 45 c.

[0231] The source electrode 45 extends from above the interlayer film 41 into the plurality of source openings 42 and is electrically connected to the body region 13, the source region 14, the plurality of source structures 20, and the plurality of source contact regions 35s within the plurality of source openings 42.

[0232] In this embodiment, the source electrode 45 has a layered structure including a lower electrode film 46 and a main electrode film 47, which are layered in this order from the chip 2 side. In this embodiment, the lower electrode film 46 has a layered structure including a first electrode film 48 and a second electrode film 49. In this embodiment, the first electrode film 48 includes a Ti film, and the second electrode film 49 includes a TiN film. The lower electrode film 46 does not necessarily have to have a layered structure, and may have a single-layer structure consisting of either the first electrode film 48 (Ti film) or the second electrode film 49 (TiN film).

[0233] The first electrode film 48 has a thickness less than the thickness of the interlayer film 41. The thickness of the first electrode film 48 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 48 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0234] The second electrode film 49 has a thickness less than that of the interlayer film 41. The thickness of the second electrode film 49 is preferably greater than the thickness of the first electrode film 48. The thickness of the second electrode film 49 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 49 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0235] The first electrode film 48 collectively covers the region of the interlayer film 41 where the plurality of source openings 42 are formed, and extends into the plurality of source openings 42 from above the interlayer film 41. The first electrode film 48 has a portion that covers the insulating main surface of the interlayer film 41 in a film-like manner, a portion that covers the wall surfaces of the plurality of source openings 42 in a film-like manner, and a portion that covers the first main surface 3 within the plurality of source openings 42 in a film-like manner.

[0236] Specifically, the first electrode film 48 directly covers the insulating principal surface of the interlayer film 41 and faces the gate structure 15 across the interlayer film 41. The first electrode film 48 extends in an arc shape from above the insulating principal surface of the interlayer film 41 following the opening edge of the source opening 42 and covers the wall surface of the source opening 42 in a film-like manner. The first electrode film 48 covers the first principal surface 3 (first surface portion 8) in the source opening 42 in a film-like manner and is mechanically and electrically connected to the source region 14 and the plurality of source contact regions 35s on the first principal surface 3.

[0237] The first electrode film 48 extends from above the first main surface 3 into the second trench 21 and coats the sidewall of the second trench 21, the second insulating film 22, and the second buried electrode 23 in a film-like manner. The first electrode film 48 is mechanically and electrically connected to the source region 14, the second buried electrode 23, and the plurality of source contact regions 35s within the second trench 21.

[0238] The second electrode film 49 directly covers the first electrode film 48. The second electrode film 49 collectively covers the region of the interlayer film 41 where the multiple source openings 42 are formed, sandwiching the first electrode film 48 between them, and extends into the multiple source openings 42 from above the interlayer film 41. The second electrode film 49 has a portion that sandwiches the first electrode film 48 between them and covers the insulating main surface of the interlayer film 41 in a film-like manner, a portion that sandwiches the first electrode film 48 between them and covers the wall surfaces of the multiple source openings 42 in a film-like manner, and a portion that sandwiches the first electrode film 48 between them within the multiple source openings 42 and covers the first main surface 3 in a film-like manner.

[0239] Specifically, the second electrode film 49 covers the insulating main surface of the interlayer film 41 with the first electrode film 48 sandwiched therebetween, and faces the gate structure 15 with the interlayer film 41 and the first electrode film 48 sandwiched therebetween. The second electrode film 49 covers the opening edge of the source opening 42 in an arc shape with the first electrode film 48 sandwiched therebetween, and coats the wall surface of the source opening 42 in a film-like manner with the first electrode film 48 sandwiched therebetween. The second electrode film 49 coats the first main surface 3 (first surface portion 8) in a film-like manner within the source opening 42 with the first electrode film 48 sandwiched therebetween, and is electrically connected to the source region 14, the source structure 20, and the plurality of source contact regions 35s via the first electrode film 48.

[0240] The second electrode film 49 extends into the second trench 21 from above the first main surface 3, and coats the sidewall of the second trench 21, the second insulating film 22, and the second buried electrode 23 in a film-like manner, sandwiching the first electrode film 48. The second electrode film 49 is electrically connected to the source region 14, the second buried electrode 23, and the plurality of source contact regions 35s within the second trench 21 via the first electrode film 48.

[0241] The main electrode film 47 contains a different conductive material from the lower electrode film 46 (the first electrode film 48 and the second electrode film 49). The main electrode film 47 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 47 has a thickness greater than the thickness (total thickness) of the lower electrode film 46. The thickness of the main electrode film 47 is preferably greater than the thickness of the interlayer film 41.

[0242] The thickness of the main electrode film 47 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 47 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0243] The main electrode film 47 directly covers the lower electrode film 46 (second electrode film 49). The main electrode film 47 backfills the second trenches 21 and the source openings 42, and collectively covers the region of the interlayer film 41 where the source openings 42 are formed. The main electrode film 47 has a portion that covers the insulating main surface of the interlayer film 41 with the lower electrode film 46 in between, a portion that covers the wall surfaces of the source openings 42 with the lower electrode film 46 in between, and a portion that covers the first main surface 3 with the lower electrode film 46 in between.

[0244] Specifically, the main electrode film 47 covers the insulating main surface of the interlayer film 41 with the lower electrode film 46 sandwiched therebetween, and faces the gate structure 15 with the interlayer film 41 and the lower electrode film 46 sandwiched therebetween. The main electrode film 47 covers the opening edge of the source opening 42 with the lower electrode film 46 sandwiched therebetween. The main electrode film 47 covers the first main surface 3 (first surface portion 8) within the source opening 42 with the lower electrode film 46 sandwiched therebetween, and is electrically connected to the source region 14 and the plurality of source contact regions 35s via the lower electrode film 46.

[0245] The main electrode film 47 extends into the second trench 21 from above the first major surface 3, and covers the sidewall of the second trench 21, the second insulating film 22, and the second buried electrode 23 with the lower electrode film 46 in between. The main electrode film 47 is electrically connected to the source region 14, the second buried electrode 23, and the plurality of source contact regions 35s within the second trench 21 via the lower electrode film 46.

[0246] The semiconductor device 1 includes a gate electrode 50 disposed on the first main surface 3. The gate electrode 50 is a terminal electrode to which a gate potential is applied from the outside. The gate electrode 50 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. Although not shown, the gate electrode 50, like the source electrode 45, includes a lower electrode film 46 and a main electrode film 47 stacked in this order from the chip 2 side.

[0247] The gate electrode 50 is disposed on a portion of the interlayer film 41 that covers the first surface 8, with a gap between it and the source electrode 45. In this embodiment, the gate electrode 50 is disposed in a region on the third side surface 5C side of the first pad 45a, and faces the first pad 45a in the first direction X. The gate electrode 50 is also interposed in a region between the second pad 45b and the third pad 45c, and faces both the second pad 45b and the third pad 45c in the second direction Y.

[0248] The gate electrode 50 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 50 has a planar area less than the planar area of ​​the source electrode 45. The gate electrode 50 has a planar area less than the planar area of ​​the first pad portion 45a. The gate electrode 50 may also have a planar area less than the planar area of ​​the second pad portion 45b (third pad portion 45c).

[0249] The gate electrode 50 partially faces the plurality of gate structures 15 and the plurality of source structures 20 across the interlayer film 41. Specifically, the gate electrode 50 is disposed inwardly and spaced apart from both ends of the plurality of gate structures 15 and both ends of the plurality of source structures 20, and faces inner parts of the plurality of gate structures 15 and inner parts of the plurality of source structures 20 across the interlayer film 41.

[0250] In this embodiment, the gate electrode 50 does not have any direct electrical connection to the plurality of gate structures 15. Of course, the gate electrode 50 may be electrically connected to the plurality of gate structures 15 via the plurality of gate openings 43. The portions of the plurality of gate structures 15 that are located under the gate electrode 50 may be removed. In this case, the gate electrode 50 may face the body region 13 with the main surface insulating film 40 and the interlayer film 41 sandwiched therebetween.

[0251] The semiconductor device 1 includes a gate wiring 51 extending from the gate electrode 50 onto the first main surface 3. The gate wiring 51 may also be referred to as a "gate finger" or "gate finger electrode." The gate wiring 51 transmits the gate potential applied to the gate electrode 50 to other regions. Although not shown, the gate wiring 51 includes a lower electrode film 46 and a main electrode film 47 stacked in this order from the chip 2 side, similar to the source electrode 45 (gate electrode 50).

[0252] The gate wiring 51 is drawn out from the gate electrode 50 onto a portion of the interlayer film 41 that covers the first surface 8. The gate wiring 51 is routed in a strip shape in the region between the periphery of the first surface 8 and the source electrode 45. The gate wiring 51 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view. In this embodiment, the gate wiring 51 is formed in a strip shape with ends having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 45.

[0253] The gate wiring 51 intersects (specifically, is perpendicular to) the ends (both ends in this embodiment) of the plurality of gate structures 15. The gate wiring 51 enters the plurality of gate openings 43 from above the interlayer film 41 and is mechanically and electrically connected to the ends (both ends) of the plurality of gate structures 15 (first buried electrodes 18) within the plurality of gate openings 43. As a result, the gate potential applied to the gate electrode 50 is applied to the plurality of gate structures 15 via the gate wiring 51.

[0254] The semiconductor device 1 includes a drain electrode 52 covering the second main surface 4. The drain electrode 52 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 52 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like. The drain electrode 52 is electrically connected to the first semiconductor region 6. The drain electrode 52 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain electrode 52 may also partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0255] The breakdown voltage that can be applied between the source electrode 45 and the drain electrode 52 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0256] 12A to 12F, second to seventh layout examples of the contact region 35 are shown below. Figures 12A to 12F are enlarged plan views showing a main portion of the first main surface 3 together with the contact region 35 according to the second to seventh layout examples.

[0257] The semiconductor device 1 may include the features of any one of the contact regions 35 according to the first to seventh layout examples. Of course, the features of the contact regions 35 according to the first to seventh layout examples may be combined as appropriate. Therefore, the semiconductor device 1 may include at least two of the features of the contact regions 35 according to the first to seventh layout examples simultaneously in the same or different regions.

[0258] 12A (second layout example), the plurality of contact regions 35 may include a plurality of gate contact regions 35g arranged in a staggered pattern at intervals in the first direction X and the second direction Y in a plan view. That is, with respect to one gate structure 15 and the other gate structure 15, the plurality of gate contact regions 35g along one gate structure 15 may face in the first direction X a region between the plurality of gate contact regions 35g along the other gate structure 15 in a plan view.

[0259] 12B (third layout example), the contact regions 35 may include a plurality of source contact regions 35s formed in a one-to-many correspondence with the plurality of source structures 20. The source contact regions 35s are respectively interposed in regions between the bottom walls of the plurality of source structures 20 and the upper ends of the plurality of source column regions 25s, and are formed at intervals in the second direction Y.

[0260] With respect to one source structure 20 and the other source structure 20, the plurality of source contact regions 35s along one source structure 20 may be opposed in the first direction X to the plurality of source contact regions 35s along the other source structure 20 in a plan view. In other words, the plurality of source contact regions 35s may be arranged in a matrix with intervals in the first direction X and the second direction Y overall in a plan view.

[0261] In this embodiment, the source contact regions 35s extend in a strip shape along the source structures 20 in a plan view. The lengths of the source contact regions 35s in the second direction Y may be equal to or different from each other.

[0262] The length of the source contact regions 35s may be greater than or less than the width of the source structures 20. The length of the source contact regions 35s may be greater than or less than the source pitch of the source structures 20. In this embodiment, the length of the source contact regions 35s is approximately equal to the length of the gate contact regions 35g.

[0263] Of course, the length of the plurality of source contact regions 35s may be greater than or less than the length of the plurality of gate contact regions 35g. The spacing between the plurality of source contact regions 35s in the second direction Y may be greater than or less than the width of the source structure 20. The spacing between the plurality of source contact regions 35s may be greater than or less than the source pitch.

[0264] In this embodiment, the source contact regions 35s are arranged in regions adjacent to the gate contact regions 35g on both sides in the first direction X. In this embodiment, the upper ends of the source contact regions 35s are integrally formed with the upper ends of the gate contact regions 35g. In other words, the source contact regions 35s, together with the gate contacts, form contact regions 35 extending in stripes in the first direction X.

[0265] 12C (fourth layout example), the contact regions 35 have a layout obtained by modifying the layout of the source contact regions 35s in the third layout example (see FIG. 12B). The source contact regions 35s may have a length greater than the length of the gate contact regions 35g in the second direction Y in plan view.

[0266] 12D (fifth layout example), the contact regions 35 have a layout obtained by modifying the layout of the source contact regions 35s according to the third layout example (see FIG. 12B). The source contact regions 35s may be formed offset in the second direction Y from the gate structures 15. The source contact regions 35s may have portions facing the first direction X in regions between the gate structures 15.

[0267] In other words, the source contact regions 35s may face the gate structures 15 in the first direction X across the source region 14 in a cross-sectional view. In this case, the source contact regions 35s may be formed spaced apart from the gate contact regions 35g in the second direction Y, or may have portions connected to the gate contact regions 35g.

[0268] 12E (sixth layout example), the contact regions 35 have a layout obtained by modifying the layout of the source contact regions 35s in the fifth layout example (see FIG. 12D). The source contact regions 35s may have a length in the second direction Y that is greater than the length of the gate contact regions 35g in a plan view. In this case, the source contact regions 35s may be formed spaced apart from the gate contact regions 35g in the second direction Y, or may have portions connected to the gate contact regions 35g.

[0269] 12F (seventh layout example), the plurality of column regions 25 may include a plurality of (at least two) source contact regions 35s arranged in a range between two gate contact regions 35g adjacent to each other in the second direction Y. Fig. 12F shows an example in which three source contact regions 35s are formed in a range between two gate contact regions 35g adjacent to each other in the second direction Y.

[0270] The source contact region 35s adjacent to the gate contact region 35g may be formed at a distance from the gate contact region 35g in the second direction Y, or may have a portion connected to the gate contact region 35g. The length of the multiple source contact regions 35s may be greater than the length of the multiple gate contact regions 35g, or may be smaller than the length of the multiple gate contact regions 35g.

[0271] As described above, the semiconductor device 1 includes the chip 2, the n-type (first conductivity type) second semiconductor region 7 (semiconductor region), the trench-type source structure 20, and the p-type (second conductivity type) source column region 25s (impurity region). The chip 2 has a first main surface 3. The second semiconductor region 7 is formed in a surface layer portion of the first main surface 3. The source structure 20 is formed on the first main surface 3 and is located within the second semiconductor region 7. The source column region 25s is formed in a region directly below the source structure 20 within the chip 2, and forms a p-n junction with the second semiconductor region 7.

[0272] This configuration provides a semiconductor device 1 capable of improving electrical characteristics. Specifically, in this semiconductor device 1, a depletion layer expands from the source column region 25s located directly below the source structure 20. This improves the breakdown voltage (e.g., breakdown voltage) by utilizing the region directly below the source structure 20. The chip 2 preferably includes SiC. This configuration provides a SiC semiconductor device as the semiconductor device 1 capable of improving electrical characteristics.

[0273] The source column region 25s may be formed at a distance from the bottom wall of the source structure 20. The bottom wall of the source structure 20 is preferably formed flat. With this configuration, for example, when a p-type impurity (trivalent element) is introduced into the chip 2 through the bottom wall of the source structure 20, the p-type impurity can be introduced into the chip 2 through the flat bottom wall. This allows the source column region 25s to be appropriately formed in the chip 2.

[0274] The source column region 25s is preferably formed in a columnar shape extending in the thickness direction of the chip 2 in a cross-sectional view. With this configuration, a pn junction is formed along the thickness direction of the chip 2 in a cross-sectional view. This expands the extension range of the depletion layer in the chip 2, thereby appropriately improving the breakdown voltage. In this case, the source column region 25s preferably crosses the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall of the source structure 20.

[0275] The semiconductor device 1 may include a p-type body region 13 formed in a surface layer portion of the first main surface 3. In this case, the source structure 20 may penetrate the body region 13. The semiconductor device 1 may include a p-type source contact region 35s formed in a region along the source structure 20 within the chip 2. The source contact region 35s may have a p-type impurity concentration higher than the p-type impurity concentration of the body region 13.

[0276] The source contact region 35s may have a portion interposed between the source structure 20 and the source column region 25s. The source contact region 35s may electrically connect the source column region 25s to the body region 13. In this configuration, the source contact region 35s improves the electrical response characteristics of the source column region 25s.

[0277] The semiconductor device 1 may include a trench-type gate structure 15. The gate structure 15 may be formed on the first main surface 3 and located within the second semiconductor region 7. In this case, the source structure 20 may be formed spaced apart from the gate structure 15. The source structure 20 may have a depth approximately equal to that of the gate structure 15. The source structure 20 may have a width approximately equal to that of the gate structure 15.

[0278] The semiconductor device 1 may include a p-type gate column region 25g formed in a region immediately below the gate structure 15 in the chip 2 and forming a p-n junction with the second semiconductor region 7. In this case, the source column region 25s may be formed spaced apart from the gate column region 25g. With this configuration, a depletion layer expands from the gate column region 25g located immediately below the gate structure 15. This improves the breakdown voltage (e.g., breakdown voltage) by utilizing the region immediately below the gate structure 15.

[0279] Furthermore, with this configuration, the formation location of the gate column region 25g is limited to the region immediately below the gate structure 15, and the formation location of the source column region 25s is limited to the region immediately below the source structure 20. Therefore, the distance between the gate column region 25g and the source column region 25s can be limited to the distance between the gate structure 15 and the source structure 20.

[0280] This allows the distance between the gate column region 25g and the source column region 25s to be narrowed to the distance between the gate structure 15 and the source structure 20. This allows the accuracy of charge balance of the gate column region 25g relative to the second semiconductor region 7 to be improved, and at the same time, the accuracy of charge balance of the source column region 25s relative to the second semiconductor region 7 to be improved.

[0281] In this case, the pitch between the center of the gate column region 25 g and the center of the source column region 25 s is preferably approximately equal to the pitch between the center of the gate structure 15 and the center of the source structure 20 .

[0282] The semiconductor device 1 may include an n-type intermediate drift region 30 that is formed in a region between the source column region 25 s and the gate column region 25 g within the chip 2 and that forms a super junction structure together with the source column region 25 s and the gate column region 25 g.

[0283] This configuration provides a superjunction type semiconductor device 1 having an appropriate charge balance. This configuration is preferably applied to a configuration in which the chip 2 includes SiC. In this case, a superjunction type SiC semiconductor device having an appropriate charge balance is provided.

[0284] A plurality of gate structures 15 may be formed at intervals on the first main surface 3. A plurality of source structures 20 may be formed in regions between the plurality of gate structures 15 on the first main surface 3. A plurality of gate column regions 25g may be formed in regions directly below the plurality of gate structures 15. A plurality of source column regions 25s may be formed in regions directly below the plurality of source structures 20 at intervals from the plurality of gate column regions 25g.

[0285] The plurality of gate structures 15 may be arranged in a stripe pattern in a plan view. The plurality of source structures 20 may be arranged in a stripe pattern extending along the plurality of gate structures 15 in a plan view. The source column region 25s may have a depth approximately equal to that of the gate column region 25g. The source column region 25s may have a width approximately equal to that of the gate column region 25g.

[0286] The chip 2 may have an off angle tilted toward the off direction. In this case, the gate column region 25g may extend in a strip shape along the off direction in a plan view. The source column region 25s may also extend in a strip shape along the off direction in a plan view.

[0287] 13 is a schematic diagram showing a wafer 60 used in the manufacture of the semiconductor device 1. The wafer 60 is a base material for the chip 2 and includes a SiC single crystal. The wafer 60 is formed in a flat disk shape. Of course, the wafer 60 may also be formed in a flat rectangular parallelepiped shape. The wafer 60 has a first wafer main surface 61 on one side, a second wafer main surface 62 on the other side, and a wafer side surface 63 connecting the first wafer main surface 61 and the second wafer main surface 62.

[0288] The first wafer main surface 61 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 62 corresponds to the second main surface 4 of the chip 2. The first wafer main surface 61 and the second wafer main surface 62 are formed by the c-plane of the SiC single crystal. The first wafer main surface 61 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 62 is formed by the carbon surface of the SiC single crystal. The wafer 60 (the first wafer main surface 61 and the second wafer main surface 62) has the off-direction and off-angle described above.

[0289] The wafer 60 has a mark 64 on the wafer side surface 63 that indicates the crystal orientation of the SiC single crystal. The mark 64 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 61 in a plan view.

[0290] The mark 64 may include either or both of a first orientation flat extending in the a-axis direction and a second orientation flat extending in the m-axis direction. The mark 64 may include either or both of an orientation notch recessed in the a-axis direction and an orientation notch recessed in the m-axis direction.

[0291] The wafer 60 includes an n-type first semiconductor region 6 formed in a surface layer portion of the second wafer main surface 62. The first semiconductor region 6 is formed in a layer shape extending along the second wafer main surface 62, and is exposed from the second wafer main surface 62 and a wafer side surface 63. In this embodiment, the first semiconductor region 6 is made of an n-type semiconductor wafer (SiC wafer) containing SiC single crystal (semiconductor single crystal), and has the above-mentioned off direction and off angle.

[0292] The wafer 60 includes an n-type second semiconductor region 7 formed in a surface layer portion of the first wafer main surface 61. The second semiconductor region 7 is formed in a layer shape extending along the first wafer main surface 61, and is exposed from the first wafer main surface 61 and a wafer side surface 63.

[0293] The second semiconductor region 7 is made of an n-type epitaxial layer (SiC epitaxial layer) containing SiC single crystal (semiconductor single crystal) and is stacked on the first semiconductor region 6. That is, in this embodiment, the wafer 60 is made of an epitaxial wafer (so-called epi-wafer) having a stacked structure including a semiconductor wafer and an epitaxial layer. The second semiconductor region 7 has the aforementioned off direction and off angle.

[0294] The wafer 60 includes a plurality of device regions 65 and a plurality of cutting lines 66. For example, the plurality of device regions 65 and the plurality of cutting lines 66 are defined by alignment marks or the like formed on the first wafer main surface 61 side. Each device region 65 is a region corresponding to a semiconductor device 1. The plurality of device regions 65 are each set to have a quadrangular shape in a plan view.

[0295] In this embodiment, the multiple device regions 65 are set in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 65 are set at intervals inward from the periphery of the first wafer main surface 61 in a plan view. The multiple cutting lines 66 are set in a grid pattern extending along the first direction X and the second direction Y to partition the multiple device regions 65.

[0296] 14A to 14N are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1. Each of the cross-sections of a region corresponding to FIG. 6 is shown in FIG. 14A. First, referring to FIG. 14A, the aforementioned wafer 60 (see FIG. 13) is prepared. Next, referring to FIG. 14B, the low concentration region 7a and the high concentration region 7b of the second semiconductor region 7 are formed.

[0297] In this step, n-type impurities are introduced into the second semiconductor region 7 by ion implantation. The ion implantation may be either or both of channeling ion implantation and random ion implantation. In the channeling ion implantation step, n-type impurities are introduced into the second semiconductor region 7 along the axial channel of the second semiconductor region 7 (wafer 60).

[0298] In the channeling ion implantation process, the n-type impurity is implanted deep into the second semiconductor region 7 while repeatedly undergoing small-angle scattering due to the channeling effect. That is, in the case of the channeling implantation method, the probability of the n-type impurity colliding with the atomic columns of the SiC single crystal is reduced. Therefore, the channeling ion implantation process is effective in forming a relatively deep high-concentration region 7b.

[0299] On the other hand, in the random ion implantation process, n-type impurities are introduced into the second semiconductor region 7 in random directions. The random direction is a direction other than the axial channel of the second semiconductor region 7 (i.e., a direction intersecting the axial channel). For example, the random direction is the vertical direction Z. In the random ion implantation process, the probability of collision of n-type impurities with atomic rows of the SiC single crystal is high, so the high-concentration region 7b is formed in a relatively shallow region. Therefore, the random ion implantation process is effective in forming a relatively shallow high-concentration region 7b.

[0300] In this step, the n-type impurity is introduced into the surface region of the second semiconductor region 7 so as to leave the bottom region of the second semiconductor region 7 as the low concentration region 7 a. As a result, the second semiconductor region 7 including the low concentration region 7 a and the high concentration region 7 b is formed in the surface region of the first wafer main surface 61.

[0301] 14C , the body region 13 is formed in the surface layer portion of the first wafer main surface 61 (specifically, the surface layer portion of the second semiconductor region 7). In this embodiment, the p-type impurity is introduced into the surface layer portion of the high-concentration region 7 b. As a result, the body region 13 is formed in the surface layer portion of the first wafer main surface 61.

[0302] 14D , the source region 14 is formed in the surface layer portion of the first wafer main surface 61 (specifically, the surface layer portion of the body region 13). In this step, a mask (not shown) having a predetermined layout is first formed on the first wafer main surface 61. The mask (not shown) may be an inorganic mask or an organic mask (resist mask). The mask (not shown) exposes the region where the source region 14 is to be formed and covers the other regions.

[0303] Next, n-type impurities are introduced into the surface layer portion of the body region 13 by ion implantation using a mask (not shown). As a result, the source region 14 is formed in the surface layer portion of the body region 13. The mask (not shown) is then removed. Of course, the n-type impurities may be introduced into the entire first wafer main surface 61 without using a mask (not shown).

[0304] 14E , a first mask 70 having a predetermined layout is formed on the first wafer main surface 61. The first mask 70 may be an inorganic mask or an organic mask (resist mask). The first mask 70 exposes regions where the second surface portion 9, the plurality of first trenches 16, and the plurality of second trenches 21 are to be formed, and covers the other regions.

[0305] Next, unnecessary portions of the wafer 60 are removed by etching through the first mask 70. The etching may be either wet etching or dry etching, or both. As a result, the first surface 8, the second surface 9, the plurality of first trenches 16, and the plurality of second trenches 21 are formed.

[0306] In this step, the plurality of first trenches 16 and the plurality of second trenches 21 are formed substantially perpendicular to the first wafer main surface 61. Furthermore, the bottom walls of the plurality of first trenches 16 and the bottom walls of the plurality of second trenches 21 are each formed flat.

[0307] 14F , a plurality of column regions 25 are formed inside the wafer 60 (specifically, the second semiconductor region 7). Specifically, this process includes forming a plurality of gate column regions 25 g in regions along the plurality of first trenches 16 in the second semiconductor region 7, and forming a plurality of source column regions 25 s in regions along the plurality of second trenches 21 in the second semiconductor region 7.

[0308] In this step, p-type impurities are introduced into the second semiconductor region 7 by ion implantation through the above-described first mask 70. The p-type impurities are introduced into the second semiconductor region 7 through the bottom walls of the plurality of first trenches 16 and the bottom walls of the plurality of second trenches 21. The ion implantation may be either or both of channeling ion implantation and random ion implantation. The ion implantation is preferably channeling ion implantation.

[0309] According to the channeling ion implantation process, a plurality of relatively deep gate column regions 25g are formed with relatively high directivity in the regions directly below the plurality of first trenches 16, and a plurality of relatively deep source column regions 25s are formed with relatively high directivity in the regions directly below the plurality of second trenches 21. In other words, a plurality of gate column regions 25g are formed with a pitch approximately equal to the pitch of the plurality of first trenches 16, and a plurality of source column regions 25s are formed with a pitch approximately equal to the pitch of the plurality of second trenches 21.

[0310] Because the plurality of first trenches 16 have flat bottom walls, variations in the introduction depth of the p-type impurities caused by variations in the depth of the bottom walls of the first trenches 16 are suppressed. This improves the accuracy of introducing the p-type impurities into the second semiconductor region 7. Similarly, because the plurality of second trenches 21 have flat bottom walls, variations in the introduction depth of the p-type impurities caused by variations in the depth of the bottom walls of the second trenches 21 are suppressed. This improves the accuracy of introducing the p-type impurities into the second semiconductor region 7.

[0311] After this step, the first mask 70 is removed. In this step, the p-type impurity is introduced into the second semiconductor region 7 through the first mask 70. Of course, the p-type impurity may be introduced into the second semiconductor region 7 by ion implantation through a mask different from the first mask 70.

[0312] 14G , a plurality of contact regions 35 are formed inside the wafer 60 (specifically, the second semiconductor region 7). This process includes forming a plurality of gate contact regions 35g in the second semiconductor region 7 in regions aligned with the plurality of first trenches 16, and forming a plurality of source contact regions 35s in the second semiconductor region 7 in regions aligned with the plurality of second trenches 21.

[0313] In this process, a second mask 71 having a predetermined layout is first formed on the first wafer main surface 61. The second mask 71 may be an inorganic mask (e.g., a silicon oxide film) or an organic mask (resist mask). The second mask 71 exposes regions where the gate contact regions 35g and the source contact regions 35s are to be formed and covers the remaining regions. In other words, the second mask 71 covers a portion of the first wafer main surface 61 and selectively exposes the wall surfaces of the first trenches 16 and the wall surfaces of the second trenches 21.

[0314] Next, p-type impurities are introduced into the second semiconductor region 7 through a portion of the first wafer main surface 61, the wall surfaces of the plurality of first trenches 16, and the wall surfaces of the plurality of second trenches 21 by ion implantation using a second mask 71. The ion implantation may be either or both of channeling ion implantation and random ion implantation. In this embodiment, the ion implantation is random ion implantation.

[0315] The random ion implantation method may be a vertical ion implantation method. In this case, the p-type impurity is introduced into the second semiconductor region 7 at an implantation angle that is approximately perpendicular to the first wafer main surface 61. The random ion implantation method may be an oblique ion implantation method. In this case, the p-type impurity is introduced into the second semiconductor region 7 at an implantation angle that is oblique to the first wafer main surface 61. The implantation angle may be greater than 0° and equal to or less than 10°. As a result, a plurality of gate contact regions 35g and a plurality of source contact regions 35s are respectively formed in the second semiconductor region 7. The second mask 71 is then removed.

[0316] 14H, a base insulating film 72 is formed on the first wafer main surface 61. The base insulating film 72 serves as a base for the plurality of first insulating films 17, the plurality of second insulating films 22, and the main surface insulating film 40. The base insulating film 72 collectively covers the first surface portion 8, the second surface portion 9, the first to fourth connecting surface portions 10A to 10D, the wall surfaces of the plurality of first trenches 16, and the wall surfaces of the plurality of second trenches 21. The base insulating film 72 may be formed by either or both of a CVD method and an oxidation method (for example, a thermal oxidation method).

[0317] 14I, a first base electrode film 73 is formed on the base insulating film 72. The first base electrode film 73 serves as a base for the plurality of first buried electrodes 18 and the plurality of second buried electrodes 23. The first base electrode film 73 has a portion covering the first wafer main surface 61 with the base insulating film 72 sandwiched therebetween, a portion buried in the plurality of first trenches 16 with the base insulating film 72 sandwiched therebetween, and a portion buried in the plurality of second trenches 21 with the base insulating film 72 sandwiched therebetween. The base insulating film 72 may be formed by a CVD method.

[0318] 14J, unnecessary portions of the first base electrode film 73 are removed by etching until the base insulating film 72 is exposed. The etching may be either wet etching or dry etching, or both. As a result, a plurality of first buried electrodes 18 and a plurality of second buried electrodes 23 are formed. Also, a plurality of gate structures 15 and a plurality of source structures 20 are formed.

[0319] 14K, an interlayer film 41 is formed on the first wafer main surface 61 (specifically, the first base electrode film 73). The interlayer film 41 collectively covers the first surface portion 8, the second surface portion 9, the first to fourth connection surface portions 10A to 10D, the plurality of gate structures 15, and the plurality of source structures 20. The interlayer film 41 may be formed by a CVD method.

[0320] 14L, a third mask 74 having a predetermined layout is formed on the interlayer film 41. The third mask 74 may be an organic mask (resist mask). The third mask 74 exposes regions where the source openings 42 and the gate openings 43 are to be formed, and covers other regions. Next, unnecessary portions of the interlayer film 41 are removed by etching through the third mask 74. The etching may be either or both of wet etching and dry etching.

[0321] Next, unnecessary portions of the base insulating film 72 are removed by etching via the third mask 74. The etching method may be either wet etching or dry etching, or both. The unnecessary portions of the base insulating film 72 may be removed simultaneously with the interlayer film 41. As a result, a plurality of source openings 42 and a plurality of gate openings 43 are formed in the interlayer film 41. The base insulating film 72 is also divided into a plurality of first insulating films 17, a plurality of second insulating films 22, and a main surface insulating film 40. The third mask 74 is then removed.

[0322] 14M, a second base electrode film 75 is formed on the interlayer film 41. The second base electrode film 75 is a base for the source electrode 45, the gate electrode 50, and the gate wiring 51. The second base electrode film 75 has a layered structure including a lower electrode film 46 and a main electrode film 47. The lower electrode film 46 has a layered structure including a first electrode film 48 and a second electrode film 49.

[0323] The first electrode film 48 may be formed by either or both of a sputtering method and a vapor deposition method. The first electrode film 48 is formed in a film shape along the first wafer main surface 61, the interlayer film 41, the wall surfaces of the plurality of source openings 42, and the wall surfaces of the plurality of gate openings 43. The second electrode film 49 may be formed by either or both of a sputtering method and a vapor deposition method. The second electrode film 49 is stacked on the first electrode film 48 and is formed in a film shape along the first wafer main surface 61, the interlayer film 41, the wall surfaces of the plurality of source openings 42, and the wall surfaces of the plurality of gate openings 43.

[0324] The main electrode film 47 is formed on the lower electrode film 46. The main electrode film 47 may be formed by either or both of a sputtering method and a vapor deposition method. The main electrode film 47 is laminated on the lower electrode film 46 and is formed in a film shape along the first wafer main surface 61, the interlayer film 41, the wall surfaces of the plurality of source openings 42, and the wall surfaces of the plurality of gate openings 43.

[0325] Next, the second base electrode film 75 is divided into the source electrode 45, the gate electrode 50, and the gate wiring 51. In this process, a mask (not shown) having a predetermined layout is formed on the main electrode film 47. The mask (not shown) covers the regions where the source electrode 45, the gate electrode 50, and the gate wiring 51 are to be formed, and leaves the other regions exposed.

[0326] Next, unnecessary portions of the main electrode film 47 are removed by etching using a mask (not shown). The unnecessary portions of the main electrode film 47 are removed until the lower electrode film 46 is exposed. The etching method may be either wet etching or dry etching, or both. The mask (not shown) is removed after the etching process of the main electrode film 47.

[0327] Next, unnecessary portions of the lower electrode film 46 are removed by etching using the main electrode film 47 as a mask. The unnecessary portions of the lower electrode film 46 are removed until the interlayer film 41 is exposed. The step of removing the lower electrode film 46 includes a step of removing the second electrode film 49 by etching and a step of removing the first electrode film 48 by etching. The etching method may be either or both of wet etching and dry etching.

[0328] This forms the source electrode 45, the gate electrode 50, and the gate wiring 51. Of course, unnecessary portions of the lower electrode film 46 may be removed by etching using a mask (not shown) in the etching step of the main electrode film 47.

[0329] 14N, a drain electrode 52 is formed on the second wafer main surface 62. The drain electrode 52 may be formed by either or both of a sputtering method and a vapor deposition method. Thereafter, the wafer 60 is cut along the cutting lines 66 (see FIG. 13) to cut out a plurality of semiconductor devices 1. The semiconductor device 1 is manufactured through the steps including those described above.

[0330] First to fourth modified examples of the semiconductor device 1 will be described below with reference to FIGS. 15 to 18. FIG. 15 is a cross-sectional view showing the semiconductor device 1 according to the first modified example. FIG. 16 is a cross-sectional view showing the semiconductor device 1 according to the second modified example. FIG. 17 is a cross-sectional view showing the semiconductor device 1 according to the third modified example. FIG. 18 is a cross-sectional view showing the semiconductor device 1 according to the fourth modified example.

[0331] The semiconductor device 1 may include the features of any one of the first to fourth modifications. Of course, the features of the first to fourth modifications may be combined as appropriate. Therefore, the semiconductor device 1 may include at least two of the features of the first to fourth modifications simultaneously in the same or different regions.

[0332] 15 (first modified example), semiconductor device 1 may include a gate column region 25g that crosses the bottom of low-concentration region 7a and has a bottom located within first semiconductor region 6. Semiconductor device 1 may also include a source column region 25s that crosses the bottom of low-concentration region 7a and has a bottom located within first semiconductor region 6.

[0333] In this case, the plurality of intermediate drift regions 30 may have portions interposed between the plurality of gate column regions 25 g and the plurality of source column regions 25 s in the first semiconductor region 6. In other words, the plurality of intermediate drift regions 30 may have portions formed by part of the first semiconductor region 6.

[0334] 16 (second modification), semiconductor device 1 may include gate column regions 25g formed in high concentration region 7b at intervals from the bottom of high concentration region 7b toward first main surface 3. Semiconductor device 1 may also include source column regions 25s formed in high concentration region 7b at intervals from the bottom of high concentration region 7b toward first main surface 3. In this case, the plurality of intermediate drift regions 30 may have portions formed by high concentration region 7b.

[0335] 17 (third modification), semiconductor device 1 does not necessarily need to simultaneously include both low-concentration regions 7 a and high-concentration regions 7 b in second semiconductor region 7. Second semiconductor region 7 may have a substantially constant n-type impurity concentration in the stacking direction (thickness direction).

[0336] In this case, the plurality of gate column regions 25g and the plurality of source column regions 25s are each formed inside the second semiconductor region 7 having a constant n-type impurity concentration. Also, the plurality of intermediate drift regions 30 are each formed by a part of the second semiconductor region 7 having a constant n-type impurity concentration.

[0337] 18 (fourth modification), the semiconductor device 1 may include an n-type buffer region 80 interposed between the first semiconductor region 6 and the second semiconductor region 7. The buffer region 80 may have an n-type impurity concentration that is lower than the n-type impurity concentration of the first semiconductor region 6 and higher than the n-type impurity concentration of the second semiconductor region 7 (low-concentration region 7 a). The n-type impurity concentration of the buffer region 80 may be higher than the n-type impurity concentration of the high-concentration region 7 b, or may be lower than the n-type impurity concentration of the high-concentration region 7 b.

[0338] The buffer region 80 may extend horizontally in a layered manner, be interposed across the entire areas of the first semiconductor region 6 and the second semiconductor region 7, and extend in a layered manner along the first main surface 3 (second main surface 4). The buffer region 80 may be exposed from the first to fourth side surfaces 5A to 5D. The buffer region 80 may be made of an n-type epitaxial layer (i.e., a SiC epitaxial layer).

[0339] The buffer region 80 may have a thickness equal to or less than the thickness of the second semiconductor region 7. The thickness of the buffer region may be 0.5 μm or more and 5 μm or less. The thickness of the buffer region 80 may have a value belonging to any one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0340] The above-described embodiments (including variations) can be implemented in other forms. For example, in the above-described embodiments, a structure may be adopted in which the conductivity type of an "n-type" semiconductor region is inverted to "p-type" and the conductivity type of a "p-type" semiconductor region is inverted to "n-type." A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

[0341] In the above-described embodiment, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. Similarly, the first semiconductor region 6 may include a silicon single crystal. Similarly, the second semiconductor region 7 may include a silicon single crystal.

[0342] In the above-described embodiment, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0343] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0344] [A1] A semiconductor device (1) including: a chip (2) having a main surface (3); a semiconductor region (7) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); a trench-type source structure (20) formed in the main surface (3) and positioned within the semiconductor region (7); and an impurity region (25, 25s) of a second conductivity type (p-type) formed in a region directly below the source structure (20) within the chip (2) and forming a pn junction with the semiconductor region (7).

[0345] [A2] The semiconductor device (1) according to A1, wherein the chip (2) includes SiC.

[0346] [A3] The semiconductor device (1) according to A1 or A2, wherein the impurity region (25, 25s) is formed at a distance from the bottom wall of the source structure (20).

[0347] [A4] The semiconductor device (1) according to A3, wherein the bottom wall of the source structure (20) is formed flat.

[0348] [A5] A semiconductor device (1) according to any one of A1 to A4, wherein the impurity regions (25, 25s) are formed in a columnar shape extending in the thickness direction (Z) of the chip (2) in a cross-sectional view.

[0349] [A6] A semiconductor device (1) according to any one of A1 to A5, wherein the impurity region (25, 25s) has a depth that crosses the intermediate portion between the bottom of the semiconductor region (7) and the bottom wall of the source structure (20).

[0350] [A7] The semiconductor device (1) according to any one of A1 to A6, further comprising a body region (13) of a second conductivity type (p-type) formed in a surface layer portion of the main surface (3), and the source structure (20) penetrates the body region (13).

[0351] [A8] The semiconductor device (1) described in A7 further includes a second conductivity type (p-type) contact region (35, 35s) formed in a region along the source structure (20) within the chip (2) and having an impurity concentration higher than the impurity concentration of the body region (13).

[0352] [A9] The semiconductor device (1) according to A8, wherein the contact region (35, 35s) has a portion interposed between the source structure (20) and the impurity region (25, 25s).

[0353] [A10] The semiconductor device (1) according to A8 or A9, wherein the contact region (35, 35s) electrically connects the impurity region (25, 25s) to the body region (13).

[0354] [A11] The semiconductor device (1) according to any one of A1 to A10, further comprising a trench-type gate structure (15) formed on the main surface (3) and positioned within the semiconductor region (7), wherein the source structure (20) is formed at a distance from the gate structure (15).

[0355] [A12] The semiconductor device (1) according to A11, wherein the source structure (20) has a depth equal to the depth of the gate structure (15).

[0356] [A13] The semiconductor device (1) according to A11 or A12, wherein the source structure (20) has a width equal to the width of the gate structure (15).

[0357] [A14] The semiconductor device (1) according to any one of A11 to A13, further comprising a gate impurity region (25, 25g) of a second conductivity type (p-type) formed in a region directly below the gate structure (15) within the chip (2) and forming a pn junction with the semiconductor region (7), the impurity region (25, 25s) being formed at a distance from the gate impurity region (25, 25g).

[0358] [A15] The semiconductor device (1) according to A14, wherein the impurity region (25, 25s) has a depth equal to a depth of the gate impurity region (25, 25g).

[0359] [A16] The semiconductor device (1) according to A14 or A15, wherein the impurity region (25, 25s) has a width equal to the width of the gate impurity region (25, 25g).

[0360] [A17] The semiconductor device (1) according to any one of A14 to A16, further comprising a first conductivity type (n-type) intermediate drift region (30) formed in a region between the impurity region (25, 25s) and the gate impurity region (25, 25g) within the chip (2), and constituting a super junction structure together with the impurity region (25, 25s) and the gate impurity region (25, 25g).

[0361] [A18] A semiconductor device (1) including: a chip (2) having a main surface (3); a semiconductor region (7) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); a trench-type gate structure (15) formed on the main surface (3) and positioned within the semiconductor region (7); a trench-type source structure (20) formed on the main surface (3) at a distance from the gate structure (15) and positioned within the semiconductor region (7); a first impurity region (25, 25g) of a second conductivity type (p-type) formed in a region immediately below the gate structure (15) within the chip (2); and a second impurity region (25, 25s) of a second conductivity type (p-type) formed in a region immediately below the source structure (20) at a distance from the first impurity region (25, 25g) within the chip (2).

[0362] [A19] A semiconductor device (1) according to A18, wherein the pitch between the center of the first impurity region (25, 25g) and the center of the second impurity region (25, 25s) is equal to the pitch between the center of the gate structure (15) and the center of the source structure (20).

[0363] [A20] A semiconductor device (1) according to A18 or A19, wherein a plurality of the gate structures (15) are formed on the main surface (3) at intervals, a plurality of the source structures (20) are respectively formed in regions between the plurality of the gate structures (15) on the main surface (3), a plurality of the first impurity regions (25, 25g) are respectively formed in regions directly below the plurality of the gate structures (15), and a plurality of the second impurity regions (25, 25s) are respectively formed in regions directly below the plurality of the source structures (20) at intervals from the plurality of the first impurity regions (25, 25g).

[0364] [B1] A method for manufacturing a semiconductor device (1), comprising the steps of: preparing a wafer (60) having a semiconductor region (7) of a first conductivity type (n-type) in a surface layer portion of a main surface (61); forming a source trench (21) in the main surface (61) so as to be positioned within the semiconductor region (7); and introducing a second conductivity type (p-type) impurity into the semiconductor region (7) through a bottom wall of the source trench (21) to form a second conductivity type (p-type) impurity region (25, 25s) that forms a pn junction with the semiconductor region (7) in a region directly below the source trench (21).

[0365] [B2] The method for manufacturing a semiconductor device (1) according to B1, wherein the wafer (60) contains SiC.

[0366] [B3] The method for manufacturing a semiconductor device (1) according to B1 or B2, wherein the impurity region (25, 25s) is formed at a distance from the bottom wall of the source trench (21).

[0367] [B4] A method for manufacturing a semiconductor device (1) according to any one of B1 to B3, wherein the bottom wall of the source trench (21) is formed flat.

[0368] [B5] A method for manufacturing a semiconductor device (1) according to any one of B1 to B4, wherein the impurity regions (25, 25s) are formed in a columnar shape extending in the thickness direction of the wafer (60) in a cross-sectional view.

[0369] [B6] A method for manufacturing a semiconductor device (1) according to any one of B1 to B5, wherein the impurity region (25, 25s) is formed so as to cross an intermediate portion between the bottom of the semiconductor region (7) and the bottom wall of the source trench (21).

[0370] [B7] A method for manufacturing a semiconductor device (1) according to any one of B1 to B6, further comprising the step of introducing a second conductivity type (p-type) impurity into a surface layer portion of the main surface (61) to form a body region (13), and the source trench (21) is formed so as to penetrate the body region (13).

[0371] [B8] A method for manufacturing a semiconductor device (1) according to B7, further comprising the step of introducing a second conductivity type (p-type) impurity into the semiconductor region (7) through a wall surface of the source trench (21) to form a second conductivity type (p-type) contact region (35, 35s) along the wall surface of the source trench (21) having an impurity concentration higher than the impurity concentration of the body region (13).

[0372] [B9] The method for manufacturing the semiconductor device (1) according to B8, wherein the contact region (35, 35s) is formed having a portion interposed between the source trench (21) and the impurity region (25, 25s).

[0373] [B10] The method for manufacturing the semiconductor device (1) according to B8 or B9, wherein the contact region (35, 35s) is formed to electrically connect the impurity region (25, 25s) to the body region (13).

[0374] [B11] A method for manufacturing a semiconductor device (1) according to any one of B1 to B10, further comprising a step of forming a gate trench (16) in the main surface (61) so as to be positioned within the semiconductor region (7), the source trench (21) being formed at a distance from the gate structure.

[0375] [B12] A method for manufacturing a semiconductor device (1) according to B11, wherein the source trench (21) is formed to have a depth equal to that of the gate trench (16).

[0376] [B13] A method for manufacturing a semiconductor device (1) according to B11 or B12, wherein the source trench (21) is formed to have the same width as the gate trench (16).

[0377] [B14] A method for manufacturing a semiconductor device (1) according to any one of B11 to B13, further comprising the step of introducing a second conductivity type (p-type) impurity into the semiconductor region (7) through a bottom wall of the gate trench (16) to form a second conductivity type (p-type) gate impurity region (25, 25g) that forms a pn junction with the semiconductor region (7) in a region directly below the gate trench (16), wherein the impurity region (25, 25s) is formed at a distance from the gate impurity region (25, 25g).

[0378] [B15] The method for manufacturing the semiconductor device (1) according to B14, wherein the impurity region (25, 25s) is formed to have a depth equal to that of the gate impurity region (25, 25g).

[0379] [B16] The method for manufacturing the semiconductor device (1) according to B14 or B15, wherein the impurity region (25, 25s) is formed to have a width equal to that of the gate impurity region (25, 25g).

[0380] [B17] A method for manufacturing a semiconductor device (1) according to any one of B14 to B16, wherein a plurality of the gate trenches (16) are formed, a plurality of the source trenches are formed, a plurality of the gate impurity regions (25, 25g) are formed in regions directly below the plurality of the gate trenches (16), and a plurality of the impurity regions (25, 25s) are formed in regions directly below the plurality of the source trenches (21).

[0381] [B18] A method for manufacturing a semiconductor device (1) according to B17, wherein the gate trenches (16) are formed in a stripe pattern in a planar view, and the source trenches (21) are formed in a stripe pattern extending along the gate trenches (16) in a planar view.

[0382] [B19] A method for manufacturing a semiconductor device (1) according to any one of B14 to B18, wherein the step of forming the impurity regions (25, 25s) and the gate impurity regions (25, 25s) includes a step of forming a first conductivity type (n-type) intermediate drift region (30) that forms a super junction structure with the impurity regions (25, 25s) and the gate impurity regions (25, 25s) within the wafer (60).

[0383] [B20] A method for manufacturing a semiconductor device (1) according to any one of B1 to B19, wherein the wafer has an off angle tilted toward the off direction, and the step of forming the impurity region (25, 25s) includes a step of introducing impurities of the second conductivity type (p-type) into the wafer (60) by a channeling ion implantation method to form the impurity region (25, 25s) extending in a band shape along the off direction in a planar view.

[0384] Although specific embodiments have been described in detail above, these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiment examples.

[0385] REFERENCE SIGNS LIST 1 semiconductor device 2 chip 3 first main surface 7 second semiconductor region (semiconductor region) 13 body region 15 gate structure 20 source structure 25 column region (impurity region) 25g gate column region (first impurity region) 25s source column region (second impurity region) 30 intermediate drift region 35 contact region 35g gate contact region (first contact region) 35s source contact region (second contact region) Z vertical direction (thickness direction)

Claims

1. A chip having a main surface, A first conductivity type semiconductor region formed on the surface layer of the main surface, A trench-type source structure formed on the main surface and located within the semiconductor region, A semiconductor device comprising: a second conductivity type impurity region formed in the region directly beneath the source structure within the chip, which forms a pn junction with the semiconductor region.

2. The semiconductor device according to claim 1, wherein the chip includes SiC.

3. The semiconductor device according to claim 1, wherein the impurity region is formed at a distance from the bottom wall of the source structure.

4. The semiconductor device according to claim 3, wherein the bottom wall of the source structure is formed flat.

5. The semiconductor device according to claim 1, wherein the impurity region is formed in a columnar shape extending in the thickness direction of the chip in a cross-sectional view.

6. The semiconductor device according to claim 1, wherein the impurity region has a depth that crosses the intermediate portion between the bottom of the semiconductor region and the bottom wall of the source structure.

7. The body further includes a second conductive type body region formed on the surface layer of the main surface, The semiconductor device according to any one of claims 1 to 6, wherein the source structure penetrates the body region.

8. The semiconductor device according to claim 7, further comprising a second conductivity type contact region formed in a region along the source structure within the chip and having an impurity concentration higher than that of the body region.

9. The semiconductor device according to claim 8, wherein the contact region has a portion interposed between the source structure and the impurity region.

10. The semiconductor device according to claim 8, wherein the contact region electrically connects the impurity region to the body region.

11. The present invention further includes a trench-type gate structure formed on the main surface and located within the semiconductor region, The semiconductor device according to any one of claims 1 to 6, wherein the source structure is formed at a distance from the gate structure.

12. The semiconductor device according to claim 11, wherein the source structure has a depth equal to the depth of the gate structure.

13. The semiconductor device according to claim 11, wherein the source structure has a width equal to the width of the gate structure.

14. The chip further includes a second conductivity type gate impurity region formed in the region directly beneath the gate structure, which forms a pn junction with the semiconductor region. The semiconductor device according to claim 11, wherein the impurity region is formed at a distance from the gate impurity region.

15. The semiconductor device according to claim 14, wherein the impurity region has a depth equal to the depth of the gate impurity region.

16. The semiconductor device according to claim 14, wherein the impurity region has a width equal to the width of the gate impurity region.

17. The semiconductor device according to claim 14, further comprising an intermediate drift region of a first conductivity type formed in the region between the impurity region and the gate impurity region within the chip, and which constitutes a superjunction structure with the impurity region and the gate impurity region.

18. A chip having a main surface, A first conductivity type semiconductor region formed on the surface layer of the main surface, A trench-type gate structure formed on the main surface and located within the semiconductor region, A trench-type source structure is formed on the main surface at a distance from the gate structure and located within the semiconductor region, A first impurity region of a second conductivity type formed in the region directly beneath the gate structure within the chip, A semiconductor device comprising: a second impurity region of a second conductivity type formed in the chip at a distance from the first impurity region and in a region directly beneath the source structure.

19. The semiconductor device according to claim 18, wherein the pitch between the central part of the first impurity region and the central part of the second impurity region is equal to the pitch between the central part of the gate structure and the central part of the source structure.

20. Multiple gate structures are formed on the main surface at intervals, Multiple source structures are formed in the regions between the multiple gate structures on the main surface, Multiple of the first impurity regions are formed in the regions directly beneath each of the gate structures. The semiconductor device according to claim 18 or 19, wherein a plurality of the second impurity regions are formed in regions directly beneath a plurality of source structures, spaced apart from a plurality of the first impurity regions.