Semiconductor device

Abstract

This semiconductor device comprises: a first impurity region of a first conductivity type formed on a surface layer portion of a first main surface of a chip; a second impurity region of a second conductivity type formed on a surface layer portion of the first impurity region; a third impurity region of the first conductivity type formed on a surface layer portion of the second impurity region; a plurality of trenches arranged at intervals in a first direction, the trenches extending in a second direction intersecting the first direction; a first electric field relaxation structure of the second conductivity type formed integrally with the second impurity region in contact with a first trench among the plurality of trenches and formed on one side in the first direction with respect to the first trench; and a second electric field relaxation structure of the second conductivity type formed integrally with the second impurity region in contact with the first trench and formed on the other side in the first direction with respect to the first trench. The plurality of first electric field relaxation structures and the plurality of second electric field relaxation structures are alternately arranged along the second direction.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2023-118661 filed with the Japan Patent Office on July 20, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] US Pat. No. 6,299,499 discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.

[0004] US Patent Application Publication No. 2015 / 0028351

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device capable of improving the effect of reducing electric field concentration in a trench insulating film.

[0006] a first impurity region of a first conductivity type formed in a surface layer portion of the first impurity region; a third impurity region of the first conductivity type formed in a surface layer portion of the second impurity region; a plurality of trenches arranged at intervals in a first direction, each of the plurality of trenches being formed so as to extend from the first main surface through the third impurity region and the second impurity region to the first impurity region, the plurality of trenches extending in a second direction intersecting the first direction; a first electric field relief structure of a second conductivity type formed integrally with the second impurity region in contact with a first trench of the plurality of trenches and formed on one side of the first trench in the first direction; and a second electric field relief structure of a second conductivity type formed integrally with the second impurity region in contact with the first trench and formed on the other side of the first trench in the first direction, the plurality of first electric field relief structures and the plurality of second electric field relief structures being arranged alternately along the second direction.

[0007] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of a chip. FIG. 4 is a perspective view showing an example layout of a chip. FIG. 5 is a plan view showing an active region and a trench structure. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 . FIG. 7 is a cross-sectional perspective view corresponding to FIG. 6 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5 . FIG. 9 is a cross-sectional perspective view corresponding to FIG. 8 . FIG. 10 is a perspective view showing a configuration of a peripheral region. FIG. 11 is a cross-sectional view showing a main portion of the peripheral region. FIG. 12 is a schematic diagram showing a wafer used in manufacturing a semiconductor device. FIG. 13 is a flowchart showing an example method for manufacturing a semiconductor device. FIG. 14A is a view showing an example method for manufacturing a semiconductor device. FIG. 14B is a view showing a process subsequent to FIG. 14A . FIG. 14C is a view showing a process subsequent to FIG. 14B . FIG. 14D is a view showing a process subsequent to FIG. 14C . FIG. 14E is a view showing a process subsequent to FIG. 14D . Fig. 14F is a diagram showing a step subsequent to Fig. 14E. Fig. 14G is a diagram showing a step subsequent to Fig. 14F. Fig. 14H is a diagram showing a step subsequent to Fig. 14G. Fig. 15 is a diagram showing a first modified example of the semiconductor device. Fig. 16 is a cross-sectional view taken along line XVI-XVI shown in Fig. 15. Fig. 17 is a diagram showing a second modified example of the semiconductor device. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 17. Fig. 19 is a diagram showing a third modified example of the semiconductor device. Fig. 20 is a diagram showing a fourth modified example of the semiconductor device. Fig. 21 is a diagram showing a fifth modified example of the semiconductor device. Fig. 22 is a diagram showing a sixth modified example of the semiconductor device.

[0008] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0009] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a plan view showing an example layout of a chip 2. FIG. 4 is a perspective view showing an example layout of the chip 2. FIG. 5 is a plan view showing a trench structure 16 together with an active region 9. FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 5. FIG. 7 is a cross-sectional perspective view corresponding to FIG. 6. FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5. FIG. 9 is a cross-sectional perspective view corresponding to FIG. 8.

[0013] 1 to 9 , a semiconductor device 1 includes a chip 2 including a SiC single crystal. The chip 2 may be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, the chip 2 is made of a hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, a 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the chip 2 is made of a 4H-SiC single crystal, but the chip 2 may be made of another polytype.

[0014] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0015] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0016] In the circumferential direction of the chip 2 (counterclockwise in FIG. 1 ) starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0017] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0018] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0019] 4, the chip 2 (first main surface 3 and second main surface 4) has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Do by the off angle θo. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θo.

[0020] The off-direction Do is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle θo may be greater than 0° and less than or equal to 10°. The off-angle θo may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0021] The off angle θo is preferably 5° or less. The off angle θo is particularly preferably 2° or more and 4.5° or less. The off angle θo is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θo is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0022] The chip 2 includes an n-type base layer 6 made of SiC single crystal. The base layer 6 may also be referred to as a "drain region," a "base SiC layer," a "base region," or the like. The base layer 6 extends horizontally in a layered manner and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base layer 6 is made of a substrate made of SiC single crystal (i.e., a SiC substrate). The base layer 6 has the off direction Do and off angle θo described above.

[0023] The base layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration of the base layer 6 may have the following peak value. The base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted with a single pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted with a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted with nitrogen.

[0024] The base layer 6 has a first thickness T1. The first thickness T1 may be 5 μm or more and 300 μm or less. The first thickness T1 may have a value belonging to any one of the following ranges: 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or more, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or more and 300 μm or less. The first thickness T1 is preferably 50 μm or more and 250 μm or less.

[0025] The chip 2 includes a semiconductor layer 7 made of single crystal SiC stacked on a base layer 6. The semiconductor layer 7, which is an example of a first impurity region, may also be referred to as a "drift region," an "SiC layer," a "semiconductor region," or the like. The semiconductor layer 7 extends horizontally in a layered manner and forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the base layer 6.

[0026] The semiconductor layer 7 has a lower end and an upper end. The lower end of the semiconductor layer 7 is the starting point of crystal growth, and the upper end of the semiconductor layer 7 is the ending point of crystal growth. The lower end of the semiconductor layer 7 is also the bottom of the semiconductor layer 7. Since the semiconductor layer 7 is grown continuously from the base layer 6, the lower end of the semiconductor layer 7 coincides with the upper end of the base layer 6.

[0027] The semiconductor layer 7 includes an n-type drift region 8. In this embodiment, the drift region 8 is formed by a portion (n-type portion) of the semiconductor layer 7. More specifically, the drift region 8 is formed by a portion of the semiconductor layer 7 on the second main surface 4 side in the vertical direction Z with respect to a body region 15 (described later) and electric field relaxation structures 21A and 21B (described later).

[0028] The boundary between the base layer 6 and the semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The semiconductor layer 7 has an off-direction Do and an off-angle θo that are approximately identical to the off-direction Do and the off-angle θo of the base layer 6.

[0029] The n-type impurity concentration of the semiconductor layer 7 (drift region 8) is preferably lower than the n-type impurity concentration of the base layer 6. The semiconductor layer 7 has an n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the semiconductor layer 7 may have a peak value of the following: The n-type impurity concentration of the semiconductor layer 7 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the semiconductor layer 7 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0030] In this embodiment, the n-type impurity concentration of the semiconductor layer 7 is adjusted by nitrogen. The semiconductor layer 7 may have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the semiconductor layer 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the semiconductor layer 7 contains a pentavalent element other than phosphorus.

[0031] The semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 1 μm or more and 10 μm or less. The second thickness T2 may have a value that belongs to any one of the following ranges: 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The second thickness T2 is preferably 2 μm or more and 8 μm or less.

[0032] The semiconductor device 1 includes an active region 9 set in the chip 2. The active region 9 is set in an inner portion of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 9 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 9 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0033] The semiconductor device 1 includes a peripheral region 10 that is set outside the active region 9 in the chip 2. The peripheral region 10 is provided in a region between the periphery of the chip 2 and the active region 9 in a plan view. The peripheral region 10 extends in a band shape along the active region 9 in a plan view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 9.

[0034] The semiconductor device 1 includes an active surface 11, an outer surface 12, and first to fourth connecting surfaces 13A to 13D formed on a first main surface 3. The active surface 11, the outer surface 12, and the first to fourth connecting surfaces 13A to 13D define an active plateau 14 on the first main surface 3.

[0035] The active surface 11 may be referred to as the “first surface portion,” the outer peripheral surface 12 may be referred to as the “second surface portion,” the first to fourth connecting surfaces 13A to 13D may be referred to as “connecting surface portions,” and the active plateau 14 may be referred to as the “active mesa portion.” The active surface 11, the outer peripheral surface 12, and the first to fourth connecting surfaces 13A to 13D (i.e., the active plateaus 14) may be considered to be components of the chip 2 (first main surface 3).

[0036] The active surface 11 is formed in the active region 9. That is, the active surface 11 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 11 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 11 is formed by the c-plane (Si-plane). In this embodiment, the active surface 11 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0037] The outer peripheral surface 12 is formed in the outer peripheral region 10. In other words, the outer peripheral surface 12 is formed outside the active surface 11. The outer peripheral surface 12 is recessed in the thickness direction of the chip 2 (toward the second main surface 4) with respect to the active surface 11. Specifically, in this embodiment, the outer peripheral surface 12 is recessed to a depth less than the thickness of the semiconductor layer 7 so as to expose the semiconductor layer 7. In other words, the outer peripheral surface 12 faces the base layer 6 with a part of the semiconductor layer 7 sandwiched therebetween, exposing the semiconductor layer 7.

[0038] The outer peripheral surface 12 extends in a band shape along the active surface 11 in a plan view and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 11. The outer peripheral surface 12 has a flat surface extending in the first direction X and the second direction Y and is formed substantially parallel to the active surface 11. In this embodiment, the outer peripheral surface 12 is formed by a c-plane (Si-plane). The outer peripheral surface 12 is continuous with the first to fourth side surfaces 5A to 5D.

[0039] The outer peripheral surface 12 has a circumferential depth DO. The circumferential depth DO may be 0.1 μm or more and 2 μm or less. The circumferential depth DO may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The circumferential depth DO is preferably 0.1 μm or more and 1.5 μm or less.

[0040] The first to fourth connection surfaces 13A to 13D extend in the vertical direction Z and connect the active surface 11 and the outer peripheral surface 12. The first connection surface 13A is located on the first side surface 5A side, the second connection surface 13B is located on the second side surface 5B side, the third connection surface 13C is located on the third side surface 5C side, and the fourth connection surface 13D is located on the fourth side surface 5D side. The first connection surface 13A and the third connection surface 13C extend in the first direction X and face the second direction Y. The second connection surface 13B and the fourth connection surface 13D extend in the second direction Y and face the first direction X.

[0041] The first to fourth connection surfaces 13A to 13D may extend substantially perpendicularly between the active surface 11 and the outer peripheral surface 12 so as to define the square-prism-shaped active plateaus 14. The first to fourth connection surfaces 13A to 13D may be inclined obliquely downward from the active surface 11 toward the outer peripheral surface 12 so as to define the square-pyramid-shaped active plateaus 14. In this manner, the active plateaus 14 are defined in a protruding shape on the semiconductor layer 7 at the first main surface 3. The active plateaus 14 are formed only on the semiconductor layer 7, and not on the base layer 6.

[0042] 5 to 9, semiconductor device 1 includes p-type body region 15 formed in a surface layer portion of first main surface 3 (active surface 11). In this embodiment, body region 15, which is an example of a second impurity region, is formed in a layer extending along active surface 11. Body region 15 may be formed throughout active surface 11 and exposed from first to fourth connecting surfaces 13A to 13D. Body region 15 is formed at a distance from the lower end of semiconductor layer 7 toward active surface 11. Preferably, body region 15 is formed at a distance from a depth position of outer peripheral surface 12 toward active surface 11 and exposed from active surface 11.

[0043] The body region 15 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the body region 15 may have the following peak value: The p-type impurity concentration of the body region 15 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 15 may be at least one of boron, aluminum, gallium, and indium.

[0044] The semiconductor device 1 includes a plurality of trench electrode-type trench structures 16 formed in the first main surface 3 (active surface 11) in the active region 9. The trench structures 16 may also be referred to as "gate structures," "trench gate structures," or the like. A gate potential is applied to the plurality of trench structures 16 as a control potential. The plurality of trench structures 16 controls the inversion and non-inversion of a channel (current path) in the body region 15 in response to the gate potential.

[0045] The plurality of trench structures 16 are arranged at intervals inward from the periphery (first to fourth connection surfaces 13A to 13D) of the active surface 11 in the active region 9. In this embodiment, the plurality of trench structures 16 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y.

[0046] That is, the trench structures 16 are arranged at intervals in the m-axis direction and extend in the a-axis direction. In this embodiment, the trench structures 16 are arranged in stripes extending in the a-axis direction (second direction Y). The extension direction of the trench structures 16 coincides with the off-direction Do of the semiconductor layer 7.

[0047] The plurality of trench structures 16 are formed at intervals from the lower end (base layer 6) of the semiconductor layer 7 toward the first main surface 3 (active surface 11), and face the base layer 6 across a part of the semiconductor layer 7. The plurality of trench structures 16 define a lower region 7 a in a region between the bottom walls of the plurality of trench structures 16 and the lower end (base layer 6) of the semiconductor layer 7.

[0048] Each trench structure 16 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z. The trench width WT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench width WT may be 0.1 μm or more and 5 μm or less.

[0049] The trench width WT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0050] The trench depth DT is preferably less than the second thickness T2 of the semiconductor layer 7. It is particularly preferable that the trench depth DT is approximately equal to the aforementioned peripheral depth DO. Of course, the trench depth DT may be equal to or greater than the peripheral depth DO, or may be less than the peripheral depth DO.

[0051] The trench depth DT is preferably greater than the trench width WT. That is, the trench structures 16 preferably each have an aspect ratio DT / WT such that they extend in a vertically elongated columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The trench depth DT may be 0.1 μm or more and 5 μm or less.

[0052] The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, and 4 μm to 5 μm. The trench depth DT is preferably 0.1 μm to 1.5 μm, and more preferably 0.5 μm to 1.5 μm.

[0053] The trench structures 16 are arranged at intervals of a trench pitch PT in the first direction X. The trench pitch PT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench pitch PT is preferably less than the trench depth DT. The trench pitch PT may be 0.1 μm or more and 5 μm or less.

[0054] The trench pitch PT may have a value belonging to any one of the following ranges: 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The trench pitch PT is preferably 0.5 μm to 3 μm, and more preferably 0.5 μm to 1.5 μm.

[0055] Each trench structure 16 includes a trench 17, an insulating film 18, and a buried electrode 19. The trench 17 is formed in the active surface 11 and defines the wall surfaces (sidewalls and bottom wall) of the trench structure 16. The bottom wall of the trench 17 preferably has a flat portion. A mesa portion 20 formed by a part of the semiconductor layer 7 is formed between adjacent trenches 17. The mesa portion 20 may also be referred to as an "element mesa portion." In this embodiment, the plurality of trenches 17 and the plurality of mesa portions 20 are strip-shaped extending along the second direction Y and are alternately arranged in the first direction X. The plurality of trenches 17 and the plurality of mesa portions 20 are arranged in a stripe pattern as a whole.

[0056] It is particularly preferable that the flat portion of the bottom wall of trench 17 extends substantially parallel to first main surface 3. In other words, it is preferable that the bottom wall of trench 17 has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane. In other words, it is preferable that the bottom wall of trench 17 has a flat portion extending in the off direction Do. Of course, the bottom wall of trench 17 may be curved in an arc shape toward the lower end side of semiconductor layer 7.

[0057] The insulating film 18 covers the wall surface of the trench 17. The insulating film 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 18 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 18 include a silicon oxide film made of an oxide of the chip 2.

[0058] The buried electrode 19 is buried in the trench 17 and faces the channel across the insulating film 18. In this embodiment, the buried electrode 19 faces the body region 15 across the insulating film 18. The buried electrode 19 may include p-type or n-type conductive polysilicon.

[0059] The semiconductor device 1 includes a plurality of p-type electric field relief structures 21A, 21B formed at intervals in the horizontal direction in the semiconductor layer 7. Specifically, the plurality of electric field relief structures 21A, 21B are formed in the mesa portion 20 and the lower region 7a in the semiconductor layer 7. The plurality of electric field relief structures 21A, 21B are formed in a thickness range between the lower end of the semiconductor layer 7 and the bottom walls of the plurality of trench structures 16. In this embodiment, the plurality of electric field relief structures 21A, 21B include a plurality of first electric field relief structures 21A and a plurality of second electric field relief structures 21B.

[0060] 5 to 7 , the multiple first electric field relaxation structures 21A are arranged at intervals in the first direction X in the lower region 7a and are also arranged at intervals in the second direction Y. Each first electric field relaxation structure 21A may be formed in a quadrangular shape in plan view. That is, the multiple first electric field relaxation structures 21A are arranged at intervals in the m-axis direction and are also arranged at intervals in the a-axis direction of the SiC single crystal.

[0061] 6, the plurality of first electric field relief structures 21A are arranged at intervals of a first relaxation pitch PR1 in the first direction X. The first relaxation pitch PR1 may be the same as the trench pitch PT. Referring to FIG. 5, the plurality of first electric field relief structures 21A are arranged at intervals of a second relaxation pitch PR2 in the second direction Y. The second relaxation pitch PR2 may be the same as the first relaxation pitch PR1.

[0062] The first relaxed pitch PR1 and the second relaxed pitch PR2 may have a value belonging to any one of the ranges of 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The first relaxed pitch PR1 and the second relaxed pitch PR2 are preferably 0.5 μm to 3.0 μm.

[0063] Each first electric field relief structure 21A is formed integrally with the body region 15, and is formed on one side of the trench 17 in the first direction X. In this embodiment, each first electric field relief structure 21A extends downward in the vertical direction Z from a part of the body region 15 sandwiched between two adjacent trenches 17 below the bottom wall of the trench 17, and spreads in the horizontal direction along the first main surface 3, overlapping the bottom wall of the trench 17.

[0064] Each first electric field relief structure 21A covers the bottom wall of the trench 17. In other words, each first electric field relief structure 21A forms at least a part of one of the side walls and the bottom wall of a pair of opposing trenches 17, and is in contact with the insulating film 18. Each first electric field relief structure 21A has a substantially L-shaped exposed surface in each trench 17 that is exposed as the lower part of the side wall of the trench 17 and the bottom wall of the trench 17 that is continuous with the lower part of the side wall.

[0065] 5, 8, and 9, the second electric field relaxation structures 21B are arranged in the lower region 7a at intervals in the first direction X and at intervals in the second direction Y. Each second electric field relaxation structure 21B may be formed in a rectangular shape in plan view. That is, the second electric field relaxation structures 21B are arranged at intervals in the m-axis direction and at intervals in the a-axis direction of the SiC single crystal.

[0066] 8, the second electric field relief structures 21B are arranged at intervals of a third relaxation pitch PR3 in the first direction X. The third relaxation pitch PR3 may be the same as the first relaxation pitch PR1 and the trench pitch PT. Referring to FIG. 5, the second electric field relief structures 21B are arranged at intervals of a fourth relaxation pitch PR4 in the second direction Y. The fourth relaxation pitch PR4 may be the same as the second relaxation pitch PR2 and the third relaxation pitch PR3.

[0067] The third relaxation pitch PR3 and the fourth relaxation pitch PR4 may have a value belonging to any one of the ranges of 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The third relaxation pitch PR3 and the fourth relaxation pitch PR4 are preferably 0.5 μm to 3.0 μm.

[0068] Each second electric field relief structure 21B is formed integrally with the body region 15, and is formed on the other side of the trench 17 in the first direction X. In this embodiment, each second electric field relief structure 21B extends downward in the vertical direction Z from a part of the body region 15 sandwiched between two adjacent trenches 17 below the bottom wall of the trench 17, and spreads in the horizontal direction along the first main surface 3, overlapping the bottom wall of the trench 17.

[0069] Each second electric field relief structure 21B covers the bottom wall of the trench 17. In other words, each second electric field relief structure 21B forms at least a part of the other of the side walls of a pair of opposing trenches 17 (the side wall opposite to the first electric field relief structure 21A) and the bottom wall, and is in contact with the insulating film 18. Each second electric field relief structure 21B has a substantially L-shaped exposed surface in each trench 17 that is exposed as the lower part of the side wall of the trench 17 and the bottom wall of the trench 17 that is continuous with the lower part of the side wall.

[0070] In this embodiment, for each trench 17, a plurality of first electric field relief structures 21A and a plurality of second electric field relief structures 21B are alternately arranged along the second direction Y. With reference to Fig. 5 , in a plan view, the first electric field relief structures 21A protruding from each trench 17 to one side in the first direction X and the second electric field relief structures 21B protruding to the other side in the first direction X (the opposite side to the first electric field relief structures 21A) are alternately arranged along the second direction Y.

[0071] In this embodiment, a plurality of trenches 17 are arranged at intervals in the first direction X. The layout of a plurality of first electric field relaxation structures 21A and second electric field relaxation structures 21B formed in a pair of adjacent trenches 17 will be described.

[0072] 5 selectively picks out a pair of adjacent trenches 17 from the plurality of trenches 17, and indicates one trench 17 as a first trench 17A and the other trench 17 as a first trench 17B. Of course, although not shown, a pair of adjacent trenches 17 that are not defined as first trenches 17A and 17B may also be defined as first trenches 17A and 17B.

[0073] 5 , the second electric field relief structures 21B of the first trench 17B are arranged at positions adjacent in the first direction X to regions between the plurality of first electric field relief structures 21A of the first trench 17A. In other words, the first electric field relief structures 21A of the first trench 17B are arranged at positions adjacent in the first direction X to regions between the plurality of second electric field relief structures 21B of the first trench 17B.

[0074] As a result, in each mesa portion 20, the multiple first electric field relief structures 21A of the first trench 17A and the multiple second electric field relief structures 21B of the first trench 17B are alternately arranged along the second direction Y. The multiple first electric field relief structures 21A of the first trench 17A and the multiple second electric field relief structures 21B of the first trench 17B may not overlap with each other in the second direction Y as shown in FIG.

[0075] In this embodiment, in each of the first trenches 17A and 17B, the multiple first electric field relief structures 21A and the multiple second electric field relief structures 21B are arranged without any gaps between them in the second direction Y. As a result, in each mesa portion 20, the multiple first electric field relief structures 21A in the first trench 17A and the multiple second electric field relief structures 21B in the first trench 17B are arranged without any gaps between them in the second direction Y. In other words, the end of each first electric field relief structure 21A in the first trench 17A in the second direction Y may be aligned linearly along the first direction X with the end of each second electric field relief structure 21B in the first trench 17B in the second direction Y. Furthermore, each first electric field relief structure 21A in the first trench 17A may partially overlap with each second electric field relief structure 21B in the first trench 17B in the first direction X.

[0076] In this embodiment, the first electric field relief structures 21A of the multiple trenches 17 are arranged linearly along the first direction X. Similarly, the second electric field relief structures 21B of the multiple trenches 17 are arranged linearly along the first direction X. As a result, the multiple first electric field relief structures 21A and the multiple second electric field relief structures 21B are arranged in a staggered pattern as a whole in a plan view.

[0077] 6 and 8 , the body region 15 includes a channel portion 22 and a non-channel portion 23. The channel portion 22 is physically separated from the first electric field relief structure 21A and the second electric field relief structure 21B. A channel is formed along the wall surface of the trench 17 adjacent to the channel portion 22. The non-channel portion 23 is physically integrated with the first electric field relief structure 21A and the second electric field relief structure 21B. The non-channel portion 23 has a bottom wall covered from below by the first electric field relief structure 21A and the second electric field relief structure 21B.

[0078] As described above, in this embodiment, in each mesa portion 20, the multiple first electric field relief structures 21A in the first trench 17A and the multiple second electric field relief structures 21B in the first trench 17B are arranged without any gaps in the second direction Y. As a result, in each mesa portion 20, the multiple channel portions 22 are arranged in a zigzag pattern in the second direction Y.

[0079] Of the multiple channel portions 22, the channel portion 22 along the first trench 17A is sandwiched between a pair of first electric field relief structures 21A in the second direction Y, and is sandwiched between the first trench 17A and the second electric field relief structure 21B of the first trench 17B in the first direction X. On the other hand, of the multiple channel portions 22, the channel portion 22 along the first trench 17B is sandwiched between a pair of second electric field relief structures 21B in the second direction Y, and is sandwiched between the first trench 17B and the first electric field relief structure 21A of the first trench 17A in the first direction X.

[0080] In other words, in this form, in a planar view, each channel portion 22 is surrounded on three sides by a plurality of electric field relaxation structures 21A, 21B formed as diffusion regions that are physically independent of each other, and is adjacent to the trench 17 on the remaining side.

[0081] 6 and 8 , first electric field relaxation structure 21A and second electric field relaxation structure 21B form boundary portion 24 with the bottom of non-channel portion 23 between adjacent trenches 17. Boundary portion 24 divides mesa portion 20 into body region 15 (non-channel portion 23) on the first main surface 3 side and electric field relaxation structures 21A, 21B on the second main surface 4 side.

[0082] The boundary portion 24 does not need to be clearly defined by image analysis (for example, SEM image analysis, etc.) because both the body region 15 (non-channel portion 23) and the electric field relaxation structures 21A, 21B are p-type. The fact that the body region 15 and the electric field relaxation structures 21A, 21B are continuous in the vertical direction Z may be confirmed, for example, by obtaining a profile of the p-type impurity concentration in the vertical direction Z from the first main surface 3 to the second main surface 4.

[0083] Referring to Figures 6 and 8, each electric field relaxation structure 21A, 21B may integrally have a base portion 28 on the second main surface 4 side of the bottom wall of the trench 17 and a protrusion portion 29 sandwiched between two adjacent trenches 17.

[0084] The base portion 28 overlaps each trench 17 and crosses the sidewall of each trench 17 in the first direction X. The base portion 28 has an end portion that protrudes outward in the horizontal direction beyond the region directly below the mesa portion 20.

[0085] The protrusions 29 extend from the base 28 along the sidewalls of each trench 17 to the inside of the mesa 20 and are connected to the bottom of the body region 15. The protrusions 29 are formed from the bottom walls of the trenches 17 to the body region 15 in the vertical direction Z.

[0086] 6 to 9 , each electric field relaxation structure 21A, 21B may have an end portion 30 at a central position of the bottom wall of trench 17 in the width direction of trench 17. As a result, the bottom wall of trench 17 may have a first portion 31 formed on the non-channel portion 23 side in the width direction of trench 17 and covered by electric field relaxation structure 21A, 21B. The bottom wall of trench 17 may also have a second portion 32 formed on the channel portion 22 side with respect to first portion 31 and covered by semiconductor layer 7 (drift region 8). Because the portion of the bottom wall of trench 17 on the channel portion 22 side is covered by drift region 8, a sufficient current path can be secured along the wall surface (sidewall and bottom wall) of trench 17 on the channel portion 22 side. This reduces on-resistance.

[0087] The bottom of each of the electric field relaxation structures 21A, 21B may be planar and parallel or substantially parallel to the first main surface 3 in the first direction X and the second direction Y. Therefore, in this embodiment, the portion of each of the electric field relaxation structures 21A, 21B closer to the second main surface 4 than the bottom wall of the trench 17 is formed to have a substantially rectangular shape in cross section.

[0088] The p-type impurity concentration of the electric field relaxation structures 21A and 21B is preferably higher than the p-type impurity concentration of the body region 15. The electric field relaxation structures 21A and 21B have a p-type impurity concentration of 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The p-type impurity concentration of the electric field relaxation structures 21A, 21B may have the following peak value: The p-type impurity concentration of the electric field relaxation structures 21A, 21B may be substantially constant in the thickness direction. Of course, the p-type impurity concentration of the electric field relaxation structures 21A, 21B may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0089] The electric field relaxation structures 21A, 21B have a relaxation depth DR in the vertical direction Z that is greater than that of the trench 17. More preferably, the relaxation depth DR of the electric field relaxation structures 21A, 21B is at least twice the trench depth DT. Of course, the relaxation depth DR may be less than twice the trench depth DT.

[0090] The relaxation depth DR may have a value in any one of the ranges of more than 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, and 4 μm to 5 μm. The relaxation depth DR is preferably 2 μm to 3 μm, in which case the trench depth DT is preferably 0.5 μm to 1.5 μm.

[0091] Each of the electric field relaxation structures 21A, 21B has a relaxation width WR in the arrangement direction. The relaxation width WR may be 0.25 μm or more and 5 μm or less. The relaxation width WR may have a value belonging to any one of the following ranges: 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0092] The semiconductor device 1 includes a plurality of source regions 33 formed on one side of a plurality of trench structures 16 in a surface layer portion of the first main surface 3 (active surface 11). The plurality of source regions 33, which are an example of third impurity regions, are formed in a surface layer portion of the body region 15. In this embodiment, the plurality of source regions 33 are selectively formed in the channel portion 22 of the plurality of body regions 15, which include the channel portion 22 and the non-channel portion 23. Therefore, as shown in FIG. 5 , the plurality of source regions 33 are arranged in a zigzag pattern in the second direction Y.

[0093] The plurality of source regions 33 have a higher n-type impurity concentration (peak value) than the semiconductor layer 7. The plurality of source regions 33 have a peak value of 1×10 １８ cm－３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0094] 5 , the multiple source regions 33 are arranged at intervals in the extension direction of the corresponding trench structures 16 in a plan view. The multiple source regions 33 are formed at intervals from the bottom of the body region 15 toward the active surface 11, and face the drift region 8 directly below, with part of the body region 15 sandwiched between them in the vertical direction Z. The multiple source regions 33, together with the multiple drift regions 8 directly below, define channels (current paths) extending along the wall surfaces of the corresponding trench structures 16.

[0095] The semiconductor device 1 includes a plurality of contact regions 34 formed in regions between the plurality of trench structures 16 in the surface layer portion of the first main surface 3 (active surface 11). The plurality of contact regions 34 are formed in the surface layer portion of the body region 15.

[0096] The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 15. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of electric field relaxation structures 21A, 21B. The plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of electric field relaxation structures 21A, 21B. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0097] A plurality of contact regions 34 are formed in the non-channel portion 23. Each contact region 34 is interposed in a region between the source region 33 and the trench 17 in the first direction X in the mesa portion 20. In this embodiment, the contact region 34 includes a first portion 25 extending in a strip shape in the extension direction of the plurality of trench structures 16 in each mesa portion 20, and a second portion 26 selectively protruding from the first portion 25 in the first direction X.

[0098] The second portion 26 is interposed between a plurality of source regions 33 adjacent to each other in the second direction Y, and is sandwiched between a pair of source regions 33 in the second direction Y. The contact region 34 is formed at an interval from the bottom of the body region 15 toward the active surface 11, and faces the drift region 8 directly below, with a part of the body region 15 sandwiched between them in the vertical direction Z.

[0099] In this way, the source region 33 is selectively formed in the channel portion 22 out of the channel portion 22 and the non-channel portion 23. On the other hand, the source region 33 is not formed in the non-channel portion 23, and a contact region 34 is formed instead. This makes it possible to separate the function of the channel portion 22, which forms a current path, from the function of the non-channel portion 23, which ensures electrical contact with the body region 15. As a result, an efficient on-state operation can be achieved.

[0100] In the non-channel portion 23, the lower portion of the body region 15 is completely covered by the electric field relaxation structures 21A and 21B, and therefore the non-channel portion 23 does not function effectively as a channel. Therefore, by forming the contact region 34 over the entire surface portion of the body region 15 in the non-channel portion 23, the potential of the body region 15 can be stabilized.

[0101] The configuration of the outer peripheral region 10 will be described below. Fig. 10 is a perspective view showing the configuration of the outer peripheral region 10. Fig. 11 is a cross-sectional view showing a main part of the outer peripheral region 10.

[0102] The semiconductor device 1 includes a p-type well region 37 formed in a surface layer portion of the outer peripheral surface 12. The well region 37 is formed at an interval from the periphery of the outer peripheral surface 12 (first to fourth side surfaces 5A to 5D) toward the active surface 11 in a plan view, and extends in a band shape along the active surface 11. In this embodiment, the well region 37 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 11 in a plan view.

[0103] The well region 37 is drawn out from the surface layer portion of the outer peripheral surface 12 toward the first to fourth connection surfaces 13A to 13D and extends along the surface layer portions of the first to fourth connection surfaces 13A to 13D. The well region 37 is electrically connected to the body region 15 in the surface layer portion of the active surface 11.

[0104] The well region 37 is formed at a distance from the lower end of the semiconductor layer 7 toward the outer peripheral surface 12, and faces the base layer 6 across a part of the semiconductor layer 7. The well region 37 forms a pn junction with the semiconductor layer 7. The well region 37 has a density of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The well region 37 may have the following p-type impurity concentration as a peak value: The well region 37 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 34 .

[0105] The p-type impurity concentration of the well region 37 may be higher than the p-type impurity concentration of the body region 15. Of course, the p-type impurity concentration of the well region 37 may be lower than the body region 15. The p-type impurity concentration of the well region 37 is preferably adjusted by at least one kind of trivalent element. The trivalent element of the well region 37 may be the same as the trivalent element of the electric field relaxation structures 21A and 21B, or may be a different kind from the trivalent element of the electric field relaxation structures 21A and 21B. The trivalent element of the well region 37 may be at least one kind of boron, aluminum, gallium, and indium.

[0106] The semiconductor device 1 includes at least one (preferably two to 20) p-type field region 38 formed in the surface layer of the outer peripheral surface 12 (first main surface 3) in the outer peripheral region 10. The number of the multiple field regions 38 is typically four to eight. The multiple field regions 38 are formed in an electrically floating state and relieve the electric field within the chip 2 at the periphery of the first main surface 3. The number, width, depth, p-type impurity concentration, etc. of the field region 38 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0107] In this embodiment, the field regions 38 are arranged at intervals from the periphery (first to fourth connection surfaces 13A to 13D) of the active surface 11 and the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Specifically, the field regions 38 are arranged at intervals from the well region 37 toward the periphery of the outer circumferential surface 12.

[0108] The multiple field regions 38 are formed in strip shapes extending along the active region 9 in plan view. Each of the multiple field regions 38 has a strip-like portion extending in the first direction X and a strip-like portion extending in the second direction Y. In this embodiment, the multiple field regions 38 are formed in an annular (specifically, a rectangular annular) shape surrounding the active region 9 (i.e., the multiple electric field relaxation structures 21A, 21B) in plan view. Note that only the electric field relaxation structure 21A is shown in FIG. 11 .

[0109] The plurality of field regions 38 are formed in the semiconductor layer 7 at intervals from the lower end of the semiconductor layer 7 toward the outer peripheral surface 12, and form pn junctions with the semiconductor layer 7. The plurality of field regions 38 preferably have bottoms located closer to the outer peripheral surface 12 than the intermediate portion of the thickness range of the semiconductor layer 7.

[0110] In this embodiment, the plurality of field regions 38 are formed at intervals from the plurality of electric field relaxation structures 21A, 21B toward the periphery of the chip 2. Therefore, the plurality of field regions 38 do not face the plurality of electric field relaxation structures 21A, 21B in the vertical direction Z. The plurality of field regions 38 are located closer to the second main surface 4 of the semiconductor layer 7 than the bottom wall of the trench structure 16.

[0111] The bottoms of the plurality of field regions 38 may be located closer to the first main surface 3 of the semiconductor layer 7 than the depth positions of the bottoms of the plurality of electric field relaxation structures 21A, 21B. Of course, the bottoms of the plurality of field regions 38 may be located closer to the second main surface 4 of the semiconductor layer 7 than the depth positions of the bottoms of the plurality of electric field relaxation structures 21A, 21B.

[0112] The plurality of field regions 38 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the field region 38 may be approximately equal to the p-type impurity concentration of the body region 15. The p-type impurity concentrations of the plurality of field regions 38 may be higher than the p-type impurity concentration of the body region 15. The p-type impurity concentrations of the plurality of field regions 38 may be lower than the p-type impurity concentration of the body region 15.

[0113] The p-type impurity concentrations of the plurality of field regions 38 are preferably adjusted by at least one trivalent element. The trivalent element in field region 38 may be the same as the trivalent element in electric field relaxation structure 21, or may be a different element from the trivalent element in electric field relaxation structures 21A and 21B. The trivalent element in field region 38 may be at least one of boron, aluminum, gallium, and indium.

[0114] The field regions 38 preferably have a width different from the relaxation width WR of the electric field relaxation structures 21A, 21B. In other words, the electric field relaxation effect of the field regions 38 is preferably adjusted separately from the electric field relaxation structures 21A, 21B. It is particularly preferable that the widths of the field regions 38 be smaller than the relaxation width WR. Of course, the widths of the field regions 38 may be larger than the relaxation width WR. Alternatively, the widths of the field regions 38 may be approximately equal to the relaxation width WR.

[0115] The field regions 38 are preferably formed at a pitch different from the relaxed pitch PR of the electric field relaxation structures 21A, 21B. The pitch of the field regions 38 is particularly preferably smaller than the relaxed pitch PR. The pitch of the field regions 38 may be larger than the relaxed pitch PR. The pitch of the field regions 38 may also be approximately equal to the relaxed pitch PR.

[0116] The semiconductor device 1 includes an interlayer insulating film 39 covering the first main surface 3. The interlayer insulating film 39 may also be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this embodiment, the interlayer insulating film 39 has a stacked structure including a first insulating film 40 and a second insulating film 41. The first insulating film 40 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 40 include a silicon oxide film made of an oxide of the chip 2 (semiconductor layer 7).

[0117] The first insulating film 40 selectively covers the first main surface 3 in the active region 9 and the peripheral region 10. Specifically, the first insulating film 40 selectively covers the active surface 11, the peripheral surface 12, and the first to fourth connecting surfaces 13A to 13D. The first insulating film 40 is connected to the insulating film 18 in the active surface 11, exposing the buried electrode 19.

[0118] The first insulating film 40 covers the well region 37 and the multiple field regions 38 on the outer peripheral surface 12. In this embodiment, the first insulating film 40 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the first insulating film 40 may be formed at an interval inward from the periphery of the outer peripheral surface 12, exposing the semiconductor layer 7 from the periphery of the outer peripheral surface 12. The first insulating film 40 covers the body region 15 and the well region 37 on the first to fourth connecting surfaces 13A to 13D.

[0119] The second insulating film 41 is stacked on the first insulating film 40. The second insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 39 preferably includes a silicon oxide film. The second insulating film 41 covers the first main surface 3 in the active region 9 and the peripheral region 10, sandwiching the first insulating film 40 therebetween. Specifically, the second insulating film 41 selectively covers the active surface 11, the peripheral surface 12, and the first to fourth connecting surfaces 13A to 13D, sandwiching the first insulating film 40 therebetween.

[0120] The second insulating film 41 covers the multiple trench structures 16 (buried electrodes 19) in the active region 9. The second insulating film 41 covers the well region 37 and the multiple field regions 38 in the peripheral region 10, sandwiching the first insulating film 40 therebetween. In this embodiment, the second insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the second insulating film 41 may be formed at a distance inward from the periphery of the peripheral surface 12, and may expose the periphery of the first main surface 3 together with the first insulating film 40.

[0121] The semiconductor device 1 includes a plurality of contact openings 42 formed in the interlayer insulating film 39. The plurality of contact openings 42 include a plurality of contact openings 42 (not shown) that expose the plurality of trench structures 16 (buried electrodes 19) and a plurality of contact openings 42 that expose the plurality of source regions 33. The plurality of contact openings 42 for the source regions 33 are formed in regions between the plurality of adjacent trench structures 16, and expose the plurality of source regions 33 and the plurality of contact regions 34.

[0122] The semiconductor device 1 includes a sidewall structure 43 disposed in the interlayer insulating film 39 so as to cover at least one of the first to fourth connecting surfaces 13A to 13D. The sidewall structure 43 is disposed on the first insulating film 40 and is covered by the second insulating film 41. The sidewall structure 43 reduces a step formed between the active surface 11 and the outer peripheral surface 12.

[0123] The sidewall structure 43 is formed in a strip shape extending along at least one of the first to fourth connecting surfaces 13A to 13D. In this embodiment, the sidewall structure 43 is formed in a ring shape (specifically, a rectangular ring shape) extending along the first to fourth connecting surfaces 13A to 13D so as to surround the active surface 11 in a plan view.

[0124] The sidewall structure 43 may have a portion extending in a film-like manner along the outer peripheral surface 12 and a portion extending in a film-like manner along the first to fourth connecting surfaces 13A to 13D. In this embodiment, the sidewall structure 43 is formed at a distance from the innermost field region 38 toward the active surface 11, and faces the well region 37 in the horizontal and vertical directions Z, with the first insulating film 40 sandwiched therebetween. The sidewall structure 43 may face the body region 15, with the first insulating film 40 sandwiched therebetween.

[0125] 1 , semiconductor device 1 includes a gate pad 44 disposed on interlayer insulating film 39. Gate pad 44 is an electrode to which a gate potential is applied from the outside. Gate pad 44 may also be referred to as a "gate pad electrode," a "first pad electrode," or the like. Gate pad 44 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 39 side.

[0126] In this embodiment, the gate pad 44 is disposed on a portion of the interlayer insulating film 39 that covers the active region 9. Specifically, the gate pad 44 is disposed on the active surface 11 at a distance from the outer peripheral surface 12 in a plan view. The gate pad 44 is disposed in a region close to the center of one side of the active surface 11 (the second connection surface 13B in this embodiment) in a plan view.

[0127] Of course, the gate pad 44 may be disposed in a region along any of the central portions of the first to fourth connection surfaces 13A to 13D. Of course, the gate pad 44 may be disposed at any corner of the active surface 11 in a plan view. The gate pad 44 may also be disposed at the central portion of the active surface 11 in a plan view. In this embodiment, the gate pad 44 is formed in a quadrangular shape in a plan view.

[0128] The semiconductor device 1 includes at least one gate wiring 45 (a plurality of gate wirings in this embodiment) extending from the gate pad 44 onto the interlayer insulating film 39. The gate wiring 45 may also be referred to as a "wiring" or "wiring electrode." In this embodiment, the plurality of gate wirings 45 are arranged on the active surface 11 at intervals from the outer peripheral surface 12 in a plan view.

[0129] The plurality of gate wirings 45 may have a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the side of the interlayer insulating film 39. In this embodiment, the plurality of gate wirings 45 include a first gate wiring 45A and a second gate wiring 45B.

[0130] The first gate wiring 45A is drawn out from the gate pad 44 toward the first connection surface 13A and extends in a line along the periphery of the active surface 11 so as to intersect (specifically, perpendicular to) part of (specifically, one end portion) of the multiple trench structures 16. The first gate wiring 45A penetrates the interlayer insulating film 39 via the multiple contact openings 42 and is electrically connected to one end portion of the multiple trench structures 16.

[0131] The second gate wiring 45B is drawn out from the gate pad 44 toward the third connection surface 13C and extends in a line along the periphery of the active surface 11 so as to intersect (specifically, perpendicular to) part of (specifically, the other end portions of) the multiple trench structures 16. The second gate wiring 45B penetrates the interlayer insulating film 39 via the multiple contact openings 42 and is electrically connected to the other end portions of the multiple trench structures 16.

[0132] The semiconductor device 1 includes a source pad 46 disposed on the interlayer insulating film 39 at a distance from the gate pad 44 and the gate wiring 45. The source pad 46 is an electrode to which a source potential is applied from the outside. The source pad 46 may also be referred to as a "source pad electrode," a "second pad electrode," or the like. The source pad 46 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 39 side.

[0133] In this embodiment, the source pad 46 is disposed on the active surface 11 at a distance from the outer peripheral surface 12 in a plan view. In this embodiment, the source pad 46 is formed in a polygonal shape having a recess that is recessed along the gate pad 44 in a plan view. Of course, the source pad 46 may also be formed in a quadrangular shape in a plan view.

[0134] The source pad 46 penetrates the interlayer insulating film 39 via the plurality of contact openings 42, and is electrically connected to the body region 15, the plurality of source regions 33, and the plurality of contact regions 34. In other words, the source pad 46 is electrically connected to the plurality of electric field relaxation structures 21A, 21B via the body region 15.

[0135] The semiconductor device 1 includes a drain pad 47 covering the second main surface 4. The drain pad 47 is an electrode to which a drain potential is applied from the outside. The drain pad 47 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 47 forms ohmic contact with the base layer 6 exposed from the second main surface 4.

[0136] That is, the drain pad 47 is electrically connected to the plurality of drift regions 8 via the base layer 6. The drain pad 47 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 47 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0137] The breakdown voltage that can be applied between source pad 46 and drain pad 47 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0138] 12 is a schematic diagram showing a wafer 50 used in manufacturing the semiconductor device 1. The wafer 50 is a substrate of the base layer 6 and contains a SiC single crystal. The wafer 50 is formed in a flat disk shape. Of course, the wafer 50 may also be formed in a flat rectangular parallelepiped shape. The wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.

[0139] The first wafer main surface 51 corresponds to the upper end of the base layer 6, and the second wafer main surface 52 corresponds to the lower end of the base layer 6. The first wafer main surface 51 and the second wafer main surface 52 are formed by the c-plane of the SiC single crystal. The first wafer main surface 51 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 52 is formed by the carbon surface of the SiC single crystal. The wafer 50 (the first wafer main surface 51 and the second wafer main surface 52) has the off-direction Do and the off-angle θo described above.

[0140] The wafer 50 has a mark 54 on the wafer side surface 53 that indicates the crystal orientation of the SiC single crystal. The mark 54 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 51 in a plan view.

[0141] The mark 54 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 54 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction. Figure 12 shows an orientation flat extending in the m-axis direction (first direction X) in a plan view.

[0142] For example, a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like. Each device region 55 corresponds to a semiconductor device 1. Each of the plurality of device regions 55 is set to have a quadrangular shape in a plan view.

[0143] In this embodiment, the device regions 55 are set in a matrix along the first direction X and the second direction Y in a plan view. The device regions 55 are set at intervals inward from the periphery of the first wafer main surface 51 in a plan view. The cutting lines 56 are set in a grid pattern extending along the first direction X and the second direction Y to partition the device regions 55.

[0144] Fig. 13 is a flowchart showing an example of a method for manufacturing the semiconductor device 1. Fig. 14A to Fig. 14H are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1. Fig. 14A to Fig. 14H are cross-sectional views corresponding to Fig. 6.

[0145] 14A, the aforementioned wafer 50 preparation step is performed (step S1 in FIG. 13). Next, the semiconductor layer 7 formation step is performed (step S2 in FIG. 13). The semiconductor layer 7 is formed by epitaxial growth starting from the first wafer main surface 51 (wafer 50).

[0146] 14B , the step of forming body region 15 is performed (step S3 in FIG. 13 ). In the step of forming body region 15, p-type impurities are introduced into the entire semiconductor layer 7. As a result, body region 15 is formed over the entire surface portion of semiconductor layer 7.

[0147] Next, referring to FIG. 14C , a step of forming a first mask 60 having a predetermined pattern is performed (step S4 in FIG. 13 ). The first mask 60 is preferably an inorganic mask (hard mask). The first mask 60 is disposed on the upper end of the semiconductor layer 7 and has a plurality of first openings 61 that expose regions where the plurality of electric field relaxation structures 21A, 21B are to be formed. Next, a step of forming the plurality of electric field relaxation structures 21A, 21B is performed (step S5 in FIG. 13 ). In the step of forming the electric field relaxation structures 21A, 21B, p-type impurities are selectively introduced into the semiconductor layer 7 through the first mask 60. This forms the electric field relaxation structures 21A, 21B connected to the lower portion of the body region 15.

[0148] Various ion implantation methods can be used to form the electric field relaxation structures 21A, 21B. For example, the electric field relaxation structures 21A, 21B may be formed by a channeling ion implantation method. The channeling implantation process is performed based on data (information) of the off-angle θo. The channeling implantation process allows the electric field relaxation structures 21A, 21B to be selectively and easily formed at a deep position in the semiconductor layer 7. When the electric field relaxation structures 21A, 21B are formed by a channeling ion implantation method, the electric field relaxation structures 21A, 21B may be formed before the body region 15.

[0149] 14D, the first mask 60 is removed (step S6 in FIG. 13). Next, referring to FIG. 14E, a step of forming a plurality of source regions 33 is performed (step S7 in FIG. 13). The plurality of source regions 33 are formed by introducing n-type impurities into the surface layer of the semiconductor layer 7 by ion implantation using a mask (not shown) having a predetermined layout.

[0150] 14F, a step of forming a plurality of contact regions 34 is performed (step S8 in FIG. 13). The plurality of contact regions 34 are formed by introducing p-type impurities into the surface layer of the semiconductor layer 7 by ion implantation using a mask (not shown) having a predetermined layout. The step of forming the contact regions 34 may be performed prior to the step of forming the source regions 33.

[0151] Next, referring to FIG. 14G, a process for forming multiple trenches 17 is performed. First, a second mask (not shown) having a predetermined pattern is formed (step S9 in FIG. 13). The second mask is preferably an inorganic mask (hard mask). Next, unnecessary portions of the semiconductor layer 7 are removed by etching through the second mask. The etching method may be either wet etching or dry etching, or both. The etching method is preferably RIE (reactive ion etching). This forms multiple trenches 17 at the upper end of the semiconductor layer 7 (step S10 in FIG. 13). In addition, the active surface 11, the outer peripheral surface 12, and the first to fourth connection surfaces 12A to 12D are formed at the upper end of the semiconductor layer 7. After the process for forming the multiple trenches 17, the second mask is removed.

[0152] Next, referring to FIG. 14H , a step of forming insulating film 18 is performed (step S11 in FIG. 13 ). The step of forming insulating film 18 also serves as a step of forming first insulating film 40. Insulating film 18 may be formed by either or both of a CVD (Chemical Vapor Deposition) method and an oxidation treatment method. Insulating film 18 and first insulating film 40 are typically formed by a thermal oxidation treatment method. Insulating film 18 is formed in the form of a film on the wall surfaces of the plurality of trenches 17, and first insulating film 40 is formed in the form of a film in the region of the upper end of semiconductor layer 7 outside the plurality of trenches 17.

[0153] Next, a buried electrode 19 formation step is performed (step S12 in FIG. 13 ). This step includes a step of forming a base electrode film on the insulating film 18. In this embodiment, the base electrode film includes conductive polysilicon. The base electrode film backfills the multiple trenches 17 and covers the upper end of the semiconductor layer 7. The base electrode film may be formed by a CVD method. Next, unnecessary portions of the buried electrode 19 are removed by an etching method. The unnecessary portions of the buried electrode 19 are removed until the insulating film 18 is exposed. The etching method may be either a wet etching method or a dry etching method, or both. As a result, multiple buried electrodes 19 are respectively embedded in the multiple trenches 17, and multiple trench structures 16 are formed.

[0154] Next, a step of forming an interlayer insulating film 39 (second insulating film 41) is performed (step S13 in FIG. 13). The interlayer insulating film 39 may be formed by a CVD method. A plurality of contact openings 42 having a predetermined layout are formed in the interlayer insulating film 39 by an etching method using a mask (not shown) having a predetermined layout.

[0155] Next, a process for forming the gate pad 44, the gate wiring 45, and the source pad 46 is performed (step S14 in FIG. 13). The gate pad 44, the gate wiring 45, and the source pad 46 are formed by depositing a metal film on the interlayer insulating film 39 by sputtering, and then shaping the metal film into a predetermined layout by etching using a mask (not shown) having a predetermined layout.

[0156] Next, a step of forming drain pads 47 is carried out (step S15 in FIG. 13). The drain pads 47 are formed by depositing a metal film on the second wafer main surface 52 by sputtering. Thereafter, the wafer 50 is cut along a plurality of cutting lines 56 (step S16 in FIG. 13). Through the steps including those described above, a plurality of semiconductor devices 1 are manufactured from a single wafer 50.

[0157] As described above, the electric field relaxation structures 21A, 21B are formed on the bottom wall of the trench 17, so that the electric field concentration on the bottom wall of the trench 17 in the trench gate structure related to the MISFET (Metal Insulator Semiconductor Field Effect Transistor) can be relaxed.

[0158] 5 , in each mesa portion 20, a plurality of first electric field relief structures 21A in the first trench 17A and a plurality of second electric field relief structures 21B in the first trench 17B are alternately arranged along the second direction Y. That is, the plurality of first electric field relief structures 21A and the plurality of second electric field relief structures 21B are arranged in a staggered pattern in a plan view as a whole. As a result, each channel portion 22 is sandwiched between and surrounded by the electric field relief structures 21A and 21B on both sides in the first direction X and the second direction Y. As a result, the electric field can be relieved from above, below, left, and right of each channel portion 22, thereby improving the effect of alleviating electric field concentration in the insulating film 18 of the trench 17.

[0159] For example, in a configuration in which strip-shaped electric field relaxation structures 21A, 21B extending in the second direction Y are selectively formed only on one widthwise side of each trench 17, the electric field can only be relaxed from both sides (both left and right sides of the page) in the first direction X. In contrast, in the configuration in Fig. 5, the electric field can be relaxed from above, below, left and right of each channel portion 22, so that the electric field concentration on the insulating film 18 of the trench 17 can be effectively relaxed.

[0160] Furthermore, in each mesa portion 20, the plurality of first electric field relief structures 21A in the first trench 17A and the plurality of second electric field relief structures 21B in the first trench 17B are arranged without any gaps in the second direction Y. This allows the plurality of first electric field relief structures 21A and the plurality of second electric field relief structures 21B to be arranged closely together, further improving the electric field relaxation effect.

[0161] Furthermore, the portions of the body region 15 that are physically integrated with the electric field relaxation structures 21A and 21B are covered with the second conductivity type portions (the body region 15 and the electric field relaxation structures 21A and 21B) from the sidewalls to the bottom wall of the trench 17. Because the range in which an inversion layer should be formed along the inner wall of the trench 17 is longer, the voltage (threshold voltage) required to form a channel tends to be selectively higher than that in the channel portion 22. Therefore, by making the portions of the body region 15 that are physically integrated with the electric field relaxation structures 21A and 21B into non-channel portions 23, it is possible to suppress variations in the threshold voltage of the semiconductor device 1.

[0162] 15 to 22 are diagrams showing first to sixth modified examples of the semiconductor device 1. Next, the modified examples of the semiconductor device 1 will be described with reference to FIGS.

[0163] 15 and 16 , in each of the first trenches 17A, 17B, the multiple first electric field relief structures 21A and the multiple second electric field relief structures 21B are arranged at intervals along the second direction Y. As a result, in each mesa portion 20, the multiple first electric field relief structures 21A of the first trench 17A and the multiple second electric field relief structures 21B of the first trench 17B are arranged at intervals in the second direction Y. In other words, the first electric field relief structures 21A of the first trench 17A do not overlap with the second electric field relief structures 21B of the first trench 17B in the first direction X.

[0164] As a result, a channel section 27 is formed in each mesa portion 20, in which neither the first electric field relief structure 21A nor the second electric field relief structure 21B is formed. The channel section 27 is a region having a constant width in the second direction Y. Referring to Fig. 16, in the channel section 27, source regions 33 are formed on the side walls of the trench 17 on both sides of the mesa portion 20 in the first direction X. In this embodiment, the contact region 34 (first portion 25) is sandwiched between a pair of source regions 33 in the first direction X.

[0165] In another aspect, in each mesa portion 20, a plurality of source regions 33 are arranged at intervals in the extension direction of the trench structure 16 on both sides in the first direction X. Unlike the embodiment in Fig. 5 , the source region 33 on one side and the source region 33 on the other side each have an end in the channel section 27 and partially overlap in the first direction X. In contrast, in the embodiment in Fig. 5 , the source region 33 on one side and the source region 33 on the other side are formed so as not to overlap in the first direction X.

[0166] According to this configuration, a plurality of first electric field relief structures 21A and a plurality of second electric field relief structures 21B are arranged at intervals along the second direction Y, thereby forming a channel section 27. In the channel section 27, channels can be formed on the side walls of the trench 17 on both sides of the mesa portion 20 in the first direction X. As a result, the channel density in each mesa portion 20 can be improved. In other words, the embodiments in FIGS. 15 and 16 can effectively reduce electric field concentration on the insulating film 18 of the trench 17 and also improve the channel density.

[0167] Referring to Figures 17 and 18, the first electric field relaxation structure 21A of the first trench 17A and the second electric field relaxation structure 21B of the first trench 17B are integrated to form a single electric field relaxation structure 35 spanning the first trench 17A and the first trench 17B.

[0168] The electric field relaxation structures 35 are arranged in a staggered pattern in a plan view. For example, the multiple mesas 20 are defined as alternating first mesa portions 20A and second mesa portions 20B in the first direction X. In the first mesa portion 20A, multiple electric field relaxation structures 35A (which may also be referred to as "first electric field relaxation structures") are arranged at intervals in the extension direction of the trench structure 16. In the second mesa portion 20B, multiple electric field relaxation structures 35B (which may also be referred to as "second electric field relaxation structures") are arranged at intervals in the extension direction of the trench structure 16. The multiple electric field relaxation structures 35A and the multiple electric field relaxation structures 35B are arranged so as not to overlap each other in the first direction X. As a result, the multiple electric field relaxation structures 35A and the multiple electric field relaxation structures 35B are arranged in a staggered pattern as a whole.

[0169] In each mesa portion 20A, 20B, the region where the plurality of electric field relaxation structures 35A, 35B are not formed is a channel section 36. The channel section 36 is a region having a constant width in the second direction Y. On the other hand, in each mesa portion 20A, 20B, the region where the plurality of electric field relaxation structures 35A, 35B are formed is a non-channel section 48. The non-channel section 48 is a region having a constant width in the second direction Y. In each mesa portion 20A, 20B, the channel sections 36 and the non-channel sections 48 are arranged alternately in the extension direction of the trench structure 16.

[0170] 18 , in the channel section 36, source regions 33 are formed on the side walls of the trenches 17 on both sides of the mesas 20A and 20B in the first direction X. In this configuration, the contact region 34 (first portion 25) is sandwiched between the pair of source regions 33 in the first direction X. On the other hand, in the non-channel section 48, the contact region 34 is formed across the entire first main surface 3 between the trench structure 16 on one side of the mesas 20A and 20B and the trench structure 16 on the other side. That is, in the non-channel section 48, the contact region 34 traverses the mesas 20A and 20B from the trench structure 16 on one side of the mesas 20A and 20B to the trench structure 16 on the other side.

[0171] According to this configuration, electric field relaxation structures 35A and 35B are formed around the channel section 36 on the top, bottom, left, and right sides of the page. As a result, the electric field can be relaxed from above, below, left, and right of each channel section 36, thereby improving the effect of relaxing the electric field concentration in the insulating film 18 of the trench 17.

[0172] Furthermore, in each mesa portion 20A, 20B, the channel sections 36 and the non-channel sections 48 are arranged alternately and clearly defined along the extension direction of the trench structure 16. This allows the function of the channel sections 36, which form a current path, to be separated from the function of the non-channel sections 48, which ensure electrical contact with the body region 15. As a result, an efficient on-state operation can be achieved.

[0173] 19 , each of the electric field relaxation structures 21A, 21B (only the electric field relaxation structure 21A is shown in FIG. 19 ) may have an end portion 30 at the position of the wall surface (sidewall) of the trench 17 in the width direction of the trench 17. For example, in a cross-sectional view, the wall surface (sidewall) of the trench 17 and the end portions 30 of the electric field relaxation structures 21A, 21B may be linearly continuous in the vertical direction Z.

[0174] With this configuration, the bottom wall of trench 17 is completely covered by electric field relaxation structures 21A and 21B, further reducing the electric field concentration on the bottom wall of trench 17. However, compared to the structures shown in Figures 6 to 9, electric field relaxation structures 21A and 21B act as an obstacle, making it more difficult for a current path to form in the bottom wall of trench 17. Therefore, compared to the structures shown in Figures 6 to 9, there is a possibility that the on-resistance may increase. In other words, the structures shown in Figures 6 to 9 can achieve a good balance between reducing the electric field concentration on the bottom wall of trench 17 and reducing the on-resistance.

[0175] Referring to Figure 20, the end 30 of each electric field relaxation structure 21A, 21B may not be a flat surface parallel or approximately parallel to the vertical direction Z from the bottom wall of the trench 17, but may be a curved surface bulging toward the horizontal direction (at least one of the first direction X and the second direction Y).

[0176] 21 , the element structure of semiconductor device 1 may be an IGBT (Insulated Gate Bipolar Transistor) structure, different from the MISFET structure of FIGS. 6 to 9. In this case, a p-type collector region 71 may be formed instead of base layer 6. Furthermore, a p-type base region 72 may be formed by body region 15, and an n-type emitter region 73 may be formed by source region 33.

[0177] In this configuration as well, each channel portion 22 is sandwiched between and surrounded by the electric field relaxation structures 21A, 21B on both sides in the first direction X and the second direction Y. As a result, the electric field can be relaxed from above, below, left, and right of each channel portion 22, thereby improving the effect of relaxing the electric field concentration in the insulating film 18 of the trench 17 in the trench gate structure related to the IGBT.

[0178] 22, trench 17 may include second trench 17C in which electric field relaxation structures 21A, 21B are not formed. In other words, electric field relaxation structures 21A, 21B do not need to be formed in all of the plurality of trenches 17 formed in chip 2, and electric field relaxation structures 21A, 21B may not be formed in some trenches 17 (second trench 17C).

[0179] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0180] For example, in each of the above-described embodiments, the base layer 6 and the semiconductor layer 7 each include a SiC single crystal. However, at least one of the base layer 6 and the semiconductor layer 7 or all of them may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0181] Wide bandgap semiconductors are semiconductors that have a bandgap larger than that of silicon. Wide bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga ２ O ３ ) are examples. The base layer 6 and the semiconductor layer 7 may be made of the same type of single crystal, or may be made of different types of single crystal. Furthermore, at least one of the base layer 6 and the semiconductor layer 7 or all of them may be made of silicon (Si).

[0182] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0183] [Supplementary Note 1-1] A chip (2) having a first main surface (3) and a second main surface (4) opposite thereto; a first impurity region (7) of a first conductivity type formed in a surface layer portion of the first main surface (3); a second impurity region (15, 72) of a second conductivity type formed in a surface layer portion of the first impurity region (7); a third impurity region (33, 73) of the first conductivity type formed in a surface layer portion of the second impurity region (15, 72); a plurality of trenches (17) arranged at intervals in a first direction (X), each of which is formed so as to extend from the first main surface (3) through the third impurity region (33, 73) and the second impurity region (15, 72) to the first impurity region (7), and which extends in a second direction (Y) intersecting the first direction (X); a first electric field relaxation structure (21A) of a second conductivity type formed integrally with the second impurity region (15, 72) in contact with a first trench (17A, 17B) of the plurality of trenches (17), and formed on one side of the first trench (17A, 17B) in the first direction (X); and a second electric field relaxation structure (21B) of the second conductivity type formed integrally with the second impurity region (15, 72) in contact with the first trench (17A, 17B), and formed on the other side of the first trench (17A, 17B) in the first direction (X), wherein the plurality of first electric field relaxation structures (21A) and the plurality of second electric field relaxation structures (21B) are alternately arranged along the second direction (Y).

[0184] According to this configuration, the first electric field relief structure (21A) and the second electric field relief structure (21B) are formed on the bottom wall of the first trench (17A, 17B), thereby making it possible to relieve electric field concentration on the bottom wall of the trench (17A, 17B). Furthermore, a plurality of first electric field relief structures (21A) and a plurality of second electric field relief structures (21B) are alternately arranged along the second direction (Y). This makes it possible to relieve the electric field in the regions adjacent to the first electric field relief structure (21A) and the second electric field relief structure (21B) from above, below, left, and right, thereby making it possible to effectively relieve electric field concentration in the trench (17A, 17B).

[0185] [Supplementary Note 1-2] The semiconductor device (1) according to Supplementary Note 1-1, wherein a pair of the first trenches (17A, 17B) are adjacent to each other in the first direction (X), and the second electric field relaxation structure (21B) of one of the first trenches (17A) of the pair of first trenches (17A, 17B) is disposed at a position adjacent to a region between the plurality of first electric field relaxation structures (21A) of the other first trench (17B) in the first direction (X).

[0186] [Appendix 1-3] The semiconductor device (1) according to Appendix 1-2, wherein the first electric field relaxation structure (21A) of the one first trench (17A) and the first electric field relaxation structure (21A) of the other first trench (17B) are linearly arranged along the first direction (X).

[0187] [Appendix 1-4] The semiconductor device (1) according to Appendix 1-2 or Appendix 1-3, wherein in each of the first trenches (17A, 17B), the plurality of first electric field relaxation structures (21A) and the plurality of second electric field relaxation structures (21B) are arranged without any gaps along the second direction (Y).

[0188] According to this configuration, the plurality of first electric field relaxation structures (21A) and the plurality of second electric field relaxation structures (21B) can be densely arranged close to each other, so that the electric field relaxation effect can be further improved.

[0189] [Appendix 1-5] The semiconductor device (1) according to Appendix 1-2 or Appendix 1-3, wherein in each of the first trenches (17A, 17B), the plurality of first electric field relaxation structures (21A) and the plurality of second electric field relaxation structures (21B) are arranged at intervals along the second direction (Y).

[0190] This configuration can effectively reduce the concentration of the electric field in the trenches (17A, 17B) and improve the channel density.

[0191] [Supplementary Note 1-6] The semiconductor device (1) according to Supplementary Note 1-1, wherein a pair of the first trenches (17A, 17B) are adjacent to each other in the first direction (X), and the first electric field relaxation structure (21A) of one of the pair of first trenches (17A, 17B) and the second electric field relaxation structure (21B) of the other of the pair of first trenches (17A, 17B) are integrated to form a single electric field relaxation structure (35) spanning the one first trench (17A) and the other first trench (17B).

[0192] [Appendix 1-7] The semiconductor device (1) according to any one of Appendices 1-1 to 1-6, wherein the second impurity region (15, 72) includes: a channel portion (22) that is physically separated from the first electric field relaxation structure (21A) and the second electric field relaxation structure (21B), and in which a channel is formed along the first trench (17A, 17B); and a non-channel portion (23) that is physically integrated with the first electric field relaxation structure (21A) and the second electric field relaxation structure (21B), and has a bottom wall covered by the first electric field relaxation structure (21A) and the second electric field relaxation structure (21B).

[0193] The portion of the second impurity region (15, 72) that is physically integrated with the first electric field relaxation structure (21A) and the second electric field relaxation structure (21B) is covered with the second conductivity type portion (the second impurity region (15, 72), and the first electric field relaxation structure (21A) and the second electric field relaxation structure (21B)) from the side wall to the bottom wall of the trench (17). Since the range in which an inversion layer should be formed along the inner wall of the trench (17) becomes longer, the voltage required for channel formation (threshold voltage) tends to be selectively high in that portion. Therefore, by making the portion of the second impurity region (15, 72) that is physically integrated with the first electric field relaxation structure (21A) and the second electric field relaxation structure (21B) a non-channel portion (23), it is possible to suppress variations in the threshold voltage.

[0194] [Appendix 1-8] The semiconductor device (1) according to appendix 1-7, wherein the third impurity region (33, 73) is selectively formed in the channel portion (22) of the channel portion (22) and the non-channel portion (23), and further includes a fourth impurity region (34) of a second conductivity type formed in a surface layer portion of the second impurity region (15, 72) and having a higher impurity concentration than the second impurity region (15, 72), and the fourth impurity region (34) includes a contact region (34) formed in the non-channel portion (23).

[0195] [Appendix 1-9] The semiconductor device (1) according to any one of Appendices 1-1 to 1-8, wherein at least one of the first electric field relaxation structure (21A) and the second electric field relaxation structure (21B) has an end (30) at a central position in the width direction of the first trench (17A, 17B).

[0196] According to this configuration, since there is a gap between the first electric field relaxation structure (21A) and the second electric field relaxation structure (21B) and the wall surface of the trench (17), a current path can be sufficiently secured along the wall surface of the trench (17), thereby reducing the on-resistance.

[0197] [Appendix 1-10] The semiconductor device (1) according to Appendix 1-9, wherein a bottom wall of the first trench (17A, 17B) includes a first portion (31) covered by at least one of the first electric field relaxation structure (21A) and the second electric field relaxation structure (21B), and a second portion (32) adjacent to the first portion (31) and covered by the first impurity region (7).

[0198] With this configuration, a portion of the bottom wall of the trench (17) is covered with the first impurity region (7, 8) (first conductivity type), so that a sufficient current path can be secured along the wall surface of the trench (17), thereby reducing the on-resistance.

[0199] [Appendix 1-11] The semiconductor device (1) according to any one of Appendices 1-1 to 1-10, including: a drain region (6) of a first conductivity type formed on the second main surface (4) side of the first impurity region (7); a body region (15) formed by the second impurity region (15, 72); a source region (33) formed by the third impurity region (33, 73); and a trench gate structure (16) formed by the trench (17), an insulating film (18) covering a wall surface of the trench (17), and a buried electrode (19) buried in the trench (17).

[0200] This configuration effectively reduces electric field concentration on the bottom wall of the trench gate structure (16) associated with a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

[0201] [Appendix 1-12] The semiconductor device (1) according to any one of Appendices 1-1 to 1-10, including: a collector region (71) of a second conductivity type formed on the second main surface (4) side of the first impurity region (7); a base region (72) formed by the second impurity region (15, 72); an emitter region (73) formed by the third impurity region (33, 73); and a trench gate structure (19) formed by the trench (17), an insulating film (18) covering a wall surface of the trench (17), and a buried electrode (19) buried in the trench (17).

[0202] This configuration effectively reduces the electric field concentration on the bottom wall of the trench gate structure (16) of an IGBT (Insulated Gate Bipolar Transistor).

[0203] [Appendix 1-13] The semiconductor device (1) according to any one of Appendices 1-1 to 1-12, wherein the chip (2) includes a SiC chip (2).

[0204] [Appendix 1-14] The semiconductor device (1) according to any one of Appendices 1-1 to 1-13, wherein the first electric field relaxation structure (21A) and the second electric field relaxation structure (21B) have a higher impurity concentration than the second impurity region (15, 72).

[0205] [Note 1-15] The impurity concentration of the second impurity region (15, 72) is 1×10 １５ cm －３ 1x10 or more １８ cm －３ the impurity concentration of the first electric field relaxation structure (21A) and the second electric field relaxation structure (21B) is 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The semiconductor device (1) described in Appendix 1-14 below.

[0206] 1: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: Base layer 7: Semiconductor layer 7a: Lower region 8: Drift region 9: Active region 10: Peripheral region 11: Active surface 12: Peripheral surface 12A: First connection surface 12B: Second connection surface 12C: Third connection surface 12D: Fourth connection surface 13A: First connection surface 13B: Second connection surface 13C: Third connection surface 13D: Fourth connection surface 14: Active plateau 15: Body region 16: Trench structure 17: Trench 18: Insulating film 19: Buried electrode 20: Mesa portion 20A: First mesa portion 20B: Second mesa portion 21A: First electric field relaxation structure 21B: Second electric field relaxation structure 22: Channel portion 23: Non-channel portion 24: Boundary portion 25: (Contact region) First portion 26: (Contact region) Second portion 27: Channel section 28: Base portion 29: Protruding portion 30: End portion 31: (Trench bottom wall) First portion 32: (Trench bottom wall) Second portion 33: Source region 34: Contact region 35: Electric field relaxation structure 36: Channel section 37: Well region 38: Field region 39: Interlayer insulating film 40: First insulating film 41: Second insulating film 42: Contact opening 43: Sidewall structure 44: Gate pad 45: Gate wiring 45A: First gate wiring 45B: Second gate wiring 46: Source pad 47: Drain pad 48: Non-channel section 50: Wafer 51: First wafer main surface 52: Second wafer main surface 53: Wafer side surface 54: Mark 55: Device region 56: Cutting line 60: First mask 61: First opening 71: Collector region 72: Base region 73: Emitter region

Claims

1. A chip having a first main surface and a second main surface on the opposite side, A first impurity region of a first conductivity type formed on the surface layer of the first main surface, A second impurity region of the second conductivity type formed on the surface of the first impurity region, A third impurity region of the first conductivity type formed on the surface of the second impurity region, A plurality of trenches arranged at intervals in a first direction, each formed so as to reach the first impurity region from the first main surface through the third impurity region and the second impurity region, and a plurality of trenches extending in a second direction intersecting the first direction, A first field relaxation structure of a second conductivity type is formed integrally with the second impurity region in contact with the first trench among the plurality of trenches, and is formed on one side in the first direction relative to the first trench, It includes a second field relaxation structure of a second conductivity type, which is integrally formed with the second impurity region in contact with the first trench and formed on the other side in the first direction relative to the first trench, A semiconductor device in which a plurality of the first field relaxation structures and a plurality of the second field relaxation structures are arranged alternately along the second direction.

2. The pair of first trenches are adjacent to each other in the first direction, The semiconductor device according to claim 1, wherein the second field relaxation structure of the other first trench is positioned adjacent in the first direction to the region between the plurality of first field relaxation structures of one of the pair of first trenches.

3. The semiconductor device according to claim 2, wherein the first field relaxation structure of one of the first trenches and the first field relaxation structure of the other first trench are arranged linearly along the first direction.

4. The semiconductor device according to claim 2, wherein in each of the first trenches, the plurality of first field relaxation structures and the plurality of second field relaxation structures are arranged without spacing along the second direction.

5. The semiconductor device according to claim 2, wherein in each of the first trenches, the plurality of first field relaxation structures and the plurality of second field relaxation structures are arranged at intervals along the second direction.

6. The pair of first trenches are adjacent to each other in the first direction, The semiconductor device according to claim 1, wherein the first field relaxation structure of one of the pair of first trenches and the second field relaxation structure of the other first trench are integrated to form a single field relaxation structure spanning the one first trench and the other first trench.

7. The semiconductor device according to any one of claims 1 to 6, wherein the second impurity region is a channel portion physically separated from the first field relaxation structure and the second field relaxation structure, the channel portion having a channel formed along the first trench, and a non-channel portion that is physically integrated with the first field relaxation structure and the second field relaxation structure and has a bottom wall covered by the first field relaxation structure and the second field relaxation structure.

8. The third impurity region is selectively formed in the channel portion of the channel portion and the non-channel portion. The material further includes a fourth impurity region of a second conductivity type, which is formed on the surface of the second impurity region and has a higher impurity concentration than the second impurity region. The semiconductor device according to claim 7, wherein the fourth impurity region includes a contact region formed in the non-channel portion.

9. The semiconductor device according to any one of claims 1 to 6, wherein at least one of the first field relaxation structure and the second field relaxation structure has an end at a central position in the width direction of the first trench.

10. The semiconductor device according to claim 9, wherein the bottom wall of the first trench includes a first portion covered by at least one of the first field relaxation structure and the second field relaxation structure, and a second portion adjacent to the first portion and covered by the first impurity region.

11. A drain region of the first conductivity type formed on the second main surface side with respect to the first impurity region, The body region formed by the second impurity region, The source region formed by the third impurity region, A semiconductor device according to any one of claims 1 to 6, comprising the trench, an insulating film covering the wall surface of the trench, and a trench gate structure formed by embedded electrodes embedded in the trench.

12. A second conductivity type collector region formed on the second main surface side with respect to the first impurity region, The base region formed by the second impurity region, The emitter region formed by the third impurity region, A semiconductor device according to any one of claims 1 to 6, comprising the trench, an insulating film covering the wall surface of the trench, and a trench gate structure formed by embedded electrodes embedded in the trench.

13. The semiconductor device according to any one of claims 1 to 6, wherein the chip includes a SiC chip.

14. The semiconductor device according to any one of claims 1 to 6, wherein the first field relaxation structure and the second field relaxation structure have an impurity concentration higher than that of the second impurity region.

15. The impurity concentration in the second impurity region is 1 × 10⁻⁶ １５ cm －３ The above 1 x 10 １８ cm －３ The following: The impurity concentrations of the first and second electric field relaxation structures are 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２０ cm －３ The semiconductor device according to claim 14, which is as follows: