Semiconductor device

Abstract

This semiconductor device comprises: a first impurity region of a first conductivity type formed on a surface layer portion of a first main surface of a chip; a second impurity region of a second conductivity type formed on a surface layer portion of the first impurity region; a third impurity region of the first conductivity type formed on a surface layer portion of the second impurity region; a trench reaching the first impurity region from the first main surface; an electric field relaxation structure of the second conductivity type that is formed on a bottom portion of the trench; a first contact region that is formed along a side surface on one side of the trench from the first main surface toward a second main surface of the chip and that is electrically connected to the second impurity region and the electric field relaxation structure; and a second contact region that is formed along a side surface on the other side of the trench from the first main surface toward the second main surface and that is electrically connected to the second impurity region and the electric field relaxation structure. A plurality of first contact regions and a plurality of second contact regions are arranged along the length direction of the trench.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2023-118662 filed with the Japan Patent Office on July 20, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] US Pat. No. 6,299,499 discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.

[0004] US Patent Application Publication No. 2015 / 0028351

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device capable of preventing local current concentration and improving breakdown resistance.

[0006] a first impurity region of a first conductivity type formed in a surface layer portion of the first main surface; a second impurity region of a second conductivity type formed in a surface layer portion of the first impurity region; a third impurity region of the first conductivity type formed in a surface layer portion of the second impurity region; a trench extending from the first main surface through the third impurity region and the second impurity region to reach the first impurity region; an electric field relaxation structure of the second conductivity type formed in a bottom of the trench; a first contact region formed along one side surface of the trench from the first main surface toward the second main surface and electrically connected to the second impurity region and the electric field relaxation structure; and a second contact region formed along the other side surface of the trench from the first main surface toward the second main surface and electrically connected to the second impurity region and the electric field relaxation structure, wherein a plurality of the first contact regions and a plurality of the second contact regions are alternately arranged along the length direction of the trench.

[0007] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example chip layout. FIG. 4 is a perspective view showing an example chip layout. FIG. 5 is a plan view showing an active region and a trench structure. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 . FIG. 7 is a cross-sectional perspective view corresponding to FIG. 6 . FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5 . FIG. 9 is a cross-sectional perspective view corresponding to FIG. 8 . FIG. 10 is a cross-sectional view taken along line XX in FIG. 5 . FIG. 11 is a perspective view showing a configuration of a peripheral region. FIG. 12 is a cross-sectional view showing a main portion of the peripheral region. FIG. 13 is a schematic diagram showing a wafer used in manufacturing a semiconductor device. FIG. 14 is a flowchart showing an example semiconductor device manufacturing method. FIG. 15A is a view showing an example semiconductor device manufacturing method. FIG. 15B is a view showing a process subsequent to FIG. 15A . FIG. 15C is a view showing a process subsequent to FIG. 15B . FIG. 15D is a view showing a process subsequent to FIG. 15C . Fig. 15E is a diagram showing a step subsequent to Fig. 15D. Fig. 15F is a diagram showing a step subsequent to Fig. 15E. Fig. 15G is a diagram showing a step subsequent to Fig. 15F. Fig. 16 is a diagram showing a first modified example of the semiconductor device. Fig. 17 is a diagram showing a second modified example of the semiconductor device. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 17. Fig. 19 is a diagram showing a third modified example of the semiconductor device. Fig. 20 is a diagram showing a fourth modified example of the semiconductor device. Fig. 21 is a diagram showing a fifth modified example of the semiconductor device. Fig. 22 is a diagram showing a sixth modified example of the semiconductor device.

[0008] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0009] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing an example layout of a chip 2. FIG. 4 is a perspective view showing an example layout of the chip 2. FIG. 5 is a plan view showing a trench structure 16 together with an active region 9. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5. FIG. 7 is a cross-sectional perspective view corresponding to FIG. 6. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 5. FIG. 9 is a cross-sectional perspective view corresponding to FIG. 8. FIG. 10 is a cross-sectional view taken along line XX in FIG. 5.

[0013] 1 to 10 , a semiconductor device 1 includes a chip 2 including a SiC single crystal. The chip 2 may be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, the chip 2 is made of a hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. The hexagonal SiC single crystal has a plurality of polytypes including a 2H (Hexagonal)-SiC single crystal, a 4H-SiC single crystal, a 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which the chip 2 is made of a 4H-SiC single crystal, but the chip 2 may be made of another polytype.

[0014] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0015] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0016] In the circumferential direction of the chip 2 (counterclockwise in FIG. 1 ) starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0017] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0018] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0019] 4, the chip 2 (first main surface 3 and second main surface 4) has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Do by the off angle θo. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θo.

[0020] The off-direction Do is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-angle θo may be greater than 0° and less than or equal to 10°. The off-angle θo may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0021] The off angle θo is preferably 5° or less. The off angle θo is particularly preferably 2° or more and 4.5° or less. The off angle θo is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θo is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0022] The chip 2 includes an n-type base layer 6 made of SiC single crystal. The base layer 6 may also be referred to as a "drain region," a "base SiC layer," a "base region," or the like. The base layer 6 extends horizontally in a layered manner and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base layer 6 is made of a substrate made of SiC single crystal (i.e., a SiC substrate). The base layer 6 has the off direction Do and off angle θo described above.

[0023] The base layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration of the base layer 6 may have the following peak value. The base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction. The n-type impurity concentration of the base layer 6 is preferably adjusted with a single pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted with a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted with nitrogen.

[0024] The base layer 6 has a first thickness T1. The first thickness T1 may be 5 μm or more and 300 μm or less. The first thickness T1 may have a value belonging to any one of the following ranges: 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or more, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or more and 300 μm or less. The first thickness T1 is preferably 50 μm or more and 250 μm or less.

[0025] The chip 2 includes a semiconductor layer 7 made of single crystal SiC stacked on a base layer 6. The semiconductor layer 7, which is an example of a first impurity region, may also be referred to as a "drift region," an "SiC layer," a "semiconductor region," or the like. The semiconductor layer 7 extends horizontally in a layered manner and forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the base layer 6.

[0026] The semiconductor layer 7 has a lower end and an upper end. The lower end of the semiconductor layer 7 is the starting point of crystal growth, and the upper end of the semiconductor layer 7 is the ending point of crystal growth. The lower end of the semiconductor layer 7 is also the bottom of the semiconductor layer 7. Since the semiconductor layer 7 is grown continuously from the base layer 6, the lower end of the semiconductor layer 7 coincides with the upper end of the base layer 6.

[0027] The semiconductor layer 7 includes an n-type drift region 8. In this embodiment, the drift region 8 is formed by a portion (n-type portion) of the semiconductor layer 7. More specifically, the drift region 8 is formed by a portion of the semiconductor layer 7 on the second main surface 4 side with respect to a body region 15 (described later) and an electric field relaxation structure 21 (described later) in the vertical direction Z.

[0028] The boundary between the base layer 6 and the semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The semiconductor layer 7 has an off-direction Do and an off-angle θo that are approximately identical to the off-direction Do and the off-angle θo of the base layer 6.

[0029] The n-type impurity concentration of the semiconductor layer 7 (drift region 8) is preferably lower than the n-type impurity concentration of the base layer 6. The semiconductor layer 7 has an n-type impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the semiconductor layer 7 may have a peak value of the following: The n-type impurity concentration of the semiconductor layer 7 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the semiconductor layer 7 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0030] In this embodiment, the n-type impurity concentration of the semiconductor layer 7 is adjusted by nitrogen. The semiconductor layer 7 may have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the semiconductor layer 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the semiconductor layer 7 contains a pentavalent element other than phosphorus.

[0031] The semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 1 μm or more and 10 μm or less. The second thickness T2 may have a value that belongs to any one of the following ranges: 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and 10 μm or less. The second thickness T2 is preferably 2 μm or more and 8 μm or less.

[0032] The semiconductor device 1 includes an active region 9 set in the chip 2. The active region 9 is set in an inner portion of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 9 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 9 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0033] The semiconductor device 1 includes a peripheral region 10 that is set outside the active region 9 in the chip 2. The peripheral region 10 is provided in a region between the periphery of the chip 2 and the active region 9 in a plan view. The peripheral region 10 extends in a band shape along the active region 9 in a plan view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 9.

[0034] The semiconductor device 1 includes an active surface 11, an outer surface 12, and first to fourth connecting surfaces 13A to 13D formed on a first main surface 3. The active surface 11, the outer surface 12, and the first to fourth connecting surfaces 13A to 13D define an active plateau 14 on the first main surface 3.

[0035] The active surface 11 may be referred to as the “first surface portion,” the outer peripheral surface 12 may be referred to as the “second surface portion,” the first to fourth connecting surfaces 13A to 13D may be referred to as “connecting surface portions,” and the active plateau 14 may be referred to as the “active mesa portion.” The active surface 11, the outer peripheral surface 12, and the first to fourth connecting surfaces 13A to 13D (i.e., the active plateaus 14) may be considered to be components of the chip 2 (first main surface 3).

[0036] The active surface 11 is formed in the active region 9. That is, the active surface 11 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The active surface 11 has a flat surface extending in the first direction X and the second direction Y. In this embodiment, the active surface 11 is formed by the c-plane (Si-plane). In this embodiment, the active surface 11 is formed in a quadrilateral shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0037] The outer peripheral surface 12 is formed in the outer peripheral region 10. In other words, the outer peripheral surface 12 is formed outside the active surface 11. The outer peripheral surface 12 is recessed in the thickness direction of the chip 2 (toward the second main surface 4) with respect to the active surface 11. Specifically, in this embodiment, the outer peripheral surface 12 is recessed to a depth less than the thickness of the semiconductor layer 7 so as to expose the semiconductor layer 7. In other words, the outer peripheral surface 12 faces the base layer 6 with a part of the semiconductor layer 7 sandwiched therebetween, exposing the semiconductor layer 7.

[0038] The outer peripheral surface 12 extends in a band shape along the active surface 11 in a plan view and is formed in a ring shape (specifically, a quadrangular ring) surrounding the active surface 11. The outer peripheral surface 12 has a flat surface extending in the first direction X and the second direction Y and is formed substantially parallel to the active surface 11. In this embodiment, the outer peripheral surface 12 is formed by a c-plane (Si-plane). The outer peripheral surface 12 is continuous with the first to fourth side surfaces 5A to 5D.

[0039] The outer peripheral surface 12 has a circumferential depth DO. The circumferential depth DO may be 0.1 μm or more and 2 μm or less. The circumferential depth DO may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less. The circumferential depth DO is preferably 0.1 μm or more and 1.5 μm or less.

[0040] The first to fourth connection surfaces 13A to 13D extend in the vertical direction Z and connect the active surface 11 and the outer peripheral surface 12. The first connection surface 13A is located on the first side surface 5A side, the second connection surface 13B is located on the second side surface 5B side, the third connection surface 13C is located on the third side surface 5C side, and the fourth connection surface 13D is located on the fourth side surface 5D side. The first connection surface 13A and the third connection surface 13C extend in the first direction X and face the second direction Y. The second connection surface 13B and the fourth connection surface 13D extend in the second direction Y and face the first direction X.

[0041] The first to fourth connection surfaces 13A to 13D may extend substantially perpendicularly between the active surface 11 and the outer peripheral surface 12 so as to define the square-prism-shaped active plateaus 14. The first to fourth connection surfaces 13A to 13D may be inclined obliquely downward from the active surface 11 toward the outer peripheral surface 12 so as to define the square-pyramid-shaped active plateaus 14. In this way, the active plateaus 14 are defined in a protruding shape on the semiconductor layer 7 at the first main surface 3. The active plateaus 14 are formed only on the semiconductor layer 7, and not on the base layer 6.

[0042] 5 to 10 , semiconductor device 1 includes p-type body region 15 formed in a surface layer portion of first main surface 3 (active surface 11). In this embodiment, body region 15, which is an example of a second impurity region, is formed in a layer extending along active surface 11. Body region 15 may be formed throughout active surface 11 and exposed from first to fourth connecting surfaces 13A to 13D. Body region 15 is formed at a distance from the lower end of semiconductor layer 7 toward active surface 11. Preferably, body region 15 is formed at a distance from a depth position of outer circumferential surface 12 toward active surface 11 and exposed from active surface 11.

[0043] The body region 15 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the body region 15 may have the following peak value: The p-type impurity concentration of the body region 15 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 15 may be at least one of boron, aluminum, gallium, and indium.

[0044] The semiconductor device 1 includes a plurality of trench electrode-type trench structures 16 formed in the first main surface 3 (active surface 11) in the active region 9. The trench structures 16 may also be referred to as "gate structures," "trench gate structures," or the like. A gate potential is applied to the plurality of trench structures 16 as a control potential. The plurality of trench structures 16 controls the inversion and non-inversion of a channel (current path) in the body region 15 in response to the gate potential.

[0045] The plurality of trench structures 16 are arranged at intervals inward from the periphery (first to fourth connection surfaces 13A to 13D) of the active surface 11 in the active region 9. In this embodiment, the plurality of trench structures 16 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y.

[0046] That is, the trench structures 16 are arranged at intervals in the m-axis direction and extend in the a-axis direction. In this embodiment, the trench structures 16 are arranged in stripes extending in the a-axis direction (second direction Y). The extension direction of the trench structures 16 coincides with the off-direction Do of the semiconductor layer 7.

[0047] The plurality of trench structures 16 are formed at intervals from the lower end (base layer 6) of the semiconductor layer 7 toward the first main surface 3 (active surface 11), and face the base layer 6 across a part of the semiconductor layer 7. The plurality of trench structures 16 define a lower region 7 a in a region between the bottom walls of the plurality of trench structures 16 and the lower end (base layer 6) of the semiconductor layer 7.

[0048] Each trench structure 16 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z. The trench width WT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench width WT may be 0.1 μm or more and 5 μm or less.

[0049] The trench width WT may have a value belonging to any one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0050] The trench depth DT is preferably less than the second thickness T2 of the semiconductor layer 7. It is particularly preferable that the trench depth DT is approximately equal to the aforementioned peripheral depth DO. Of course, the trench depth DT may be equal to or greater than the peripheral depth DO, or may be less than the peripheral depth DO.

[0051] The trench depth DT is preferably greater than the trench width WT. That is, the trench structures 16 each preferably have an aspect ratio DT / WT such that they extend in a vertically elongated columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The aspect ratio DT / WT may be, for example, 1 or more and 5 or less, and is preferably 1 or more and 3 or less.

[0052] The trench depth DT may be 0.1 μm or more and 5 μm or less. The trench depth DT may have a value belonging to any one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less, and more preferably 0.5 μm or more and 1.5 μm or less.

[0053] The trench structures 16 are arranged at intervals of a trench pitch PT in the first direction X. The trench pitch PT is preferably less than the second thickness T2 of the semiconductor layer 7. The trench pitch PT is preferably less than the trench depth DT. The trench pitch PT may be 0.1 μm or more and 5 μm or less.

[0054] The trench pitch PT may have a value belonging to any one of the following ranges: 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The trench pitch PT is preferably 0.5 μm to 3 μm, and more preferably 0.5 μm to 1.5 μm.

[0055] Each trench structure 16 includes a trench 17, an insulating film 18, and a buried electrode 19. The trench 17 is formed in the active surface 11 and defines the wall surfaces (sidewalls and bottom wall) of the trench structure 16. The bottom wall of the trench 17 preferably has a flat portion. A mesa portion 20 formed by a part of the semiconductor layer 7 is formed between adjacent trenches 17. The mesa portion 20 may also be referred to as an "element mesa portion." In this embodiment, the plurality of trenches 17 and the plurality of mesa portions 20 are strip-shaped extending along the second direction Y and are alternately arranged in the first direction X. The plurality of trenches 17 and the plurality of mesa portions 20 are arranged in a stripe pattern as a whole.

[0056] It is particularly preferable that the flat portion of the bottom wall of trench 17 extends substantially parallel to first main surface 3. In other words, it is preferable that the bottom wall of trench 17 has an off angle θo inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane. In other words, it is preferable that the bottom wall of trench 17 has a flat portion extending in the off direction Do. Of course, the bottom wall of trench 17 may be curved in an arc shape toward the lower end side of semiconductor layer 7.

[0057] The insulating film 18 covers the wall surface of the trench 17. The insulating film 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 18 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 18 include a silicon oxide film made of an oxide of the chip 2.

[0058] The buried electrode 19 is buried in the trench 17 and faces the channel across the insulating film 18. In this embodiment, the buried electrode 19 faces the body region 15 across the insulating film 18. The buried electrode 19 may include p-type or n-type conductive polysilicon.

[0059] The semiconductor device 1 includes a plurality of p-type electric field relaxation structures 21 formed at intervals in the horizontal direction in the semiconductor layer 7. Specifically, the plurality of electric field relaxation structures 21 are formed in the lower region 7a in the semiconductor layer 7. The plurality of electric field relaxation structures 21 are formed in a thickness range between the lower end of the semiconductor layer 7 and the bottom walls of the plurality of trench structures 16.

[0060] The electric field relaxation structures 21 are arranged at intervals in the first direction X in the lower region 7a, and are each formed in a strip shape extending in the second direction Y. That is, the electric field relaxation structures 21 are arranged at intervals in the m-axis direction and extend in the a-axis direction of the SiC single crystal. The electric field relaxation structures 21 are formed in stripes extending in the a-axis direction (second direction Y), and the extending direction of the electric field relaxation structures 21 coincides with the off-direction Do of the semiconductor layer 7.

[0061] The plurality of electric field relaxation structures 21 overlap with the plurality of trench structures 16 in the stacking direction. Specifically, the plurality of electric field relaxation structures 21 overlap with the plurality of trench structures 16 in a one-to-one correspondence in the stacking direction. The plurality of electric field relaxation structures 21 are formed in the active region 9 at intervals inward from the periphery of the active surface 11 (first to fourth connection surfaces 13A to 13D).

[0062] In this embodiment, the plurality of electric field relaxation structures 21 are connected to the bottom walls of the corresponding trench structures 16. As a result, the upper ends of the electric field relaxation structures 21 are exposed at the bottom walls of the trench structures 16 (trench 17). Specifically, each electric field relaxation structure 21 has side surfaces 22 that are flush with both side surfaces of the trench 17 in the depth direction of the trench structure 16. The side surfaces 22 of the electric field relaxation structure 21 extend in the depth direction of the trench structure 16 and form boundaries with the semiconductor layer 7 (lower region 7 a). Therefore, the electric field relaxation structure 21 is physically separated from the body region 15 in the depth direction of the trench structure 16 and forms the entire bottom wall of the trench structure 16.

[0063] 12 , both ends of the plurality of electric field relaxation structures 21 may be located closer to the periphery of the active region 9 than both ends of the plurality of trench structures 16. Both ends of the plurality of electric field relaxation structures 21 may be located closer to the inside of the active region 9 than both ends of the plurality of trench structures 16.

[0064] 6 and 8 , the multiple electric field relaxation structures 21 are arranged at intervals of a relaxation pitch PR in the first direction X. The relaxation pitch PR may be the same as the trench pitch PT. The relaxation pitch PR may have a value belonging to any one of the following ranges: 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The relaxation pitch PR is preferably 0.5 μm to 3.0 μm.

[0065] The p-type impurity concentration of the electric field relaxation structure 21 is preferably higher than the p-type impurity concentration of the body region 15. １６ cm －３ 1x10 or more １９ cm －３The p-type impurity concentration of the electric field relaxation structure 21 may have the following peak value: The p-type impurity concentration of the electric field relaxation structure 21 may be approximately constant in the thickness direction. Of course, the p-type impurity concentration of the electric field relaxation structure 21 may have a concentration gradient that gradually increases and / or gradually decreases in the stacking direction (crystal growth direction).

[0066] The electric field relaxation structure 21 has a relaxation depth DR in the vertical direction Z that is greater than that of the trench 17. More preferably, the relaxation depth DR of the electric field relaxation structure 21 is at least twice the trench depth DT. Of course, the relaxation depth DR may be less than twice the trench depth DT.

[0067] The relaxation depth DR may have a value in any one of the ranges of more than 0.25 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, and 4 μm to 5 μm. The relaxation depth DR is preferably 2 μm to 3 μm, in which case the trench depth DT is preferably 0.5 μm to 1.5 μm.

[0068] Each of the electric field relaxation structures 21 has a relaxation width WR in the arrangement direction. The relaxation width WR may be 0.25 μm or more and 5 μm or less. The relaxation width WR may have a value belonging to any one of the following ranges: 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0069] The semiconductor device 1 includes a plurality of contact regions 34A, 34B formed in regions between the plurality of trench structures 16 in the surface layer portion of the first main surface 3 (active surface 11). The plurality of contact regions 34A, 34B are regions physically separated from each other, and both are formed in the surface layer portion of the body region 15.

[0070] The plurality of contact regions 34A, 34B have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 15. The p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of electric field relaxation structures 21. The plurality of contact regions 34A, 34B have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of electric field relaxation structures 21. １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value: In this embodiment, the plurality of contact regions 34 includes a plurality of first contact regions 34A and a plurality of second contact regions 34B.

[0071] 5 to 7 , the first contact regions 34A are selectively formed on one of both side surfaces of each trench 17 and are arranged at intervals in the second direction Y. Each first contact region 34A extends along one sidewall of each trench 17 in the depth direction of each trench 17 from the first main surface 3 toward the second main surface 4, and is electrically connected to the body region 15 and the electric field relaxation structure 21.

[0072] More specifically, each first contact region 34A integrally includes a first portion 23, a second portion 24, and a third portion 25, each of which extends in a different direction. Of the multiple portions of the first contact region 34A, the first portion 23 extends in the depth direction of the trench 17 (i.e., the vertical direction Z), the second portion 24 extends in a horizontal direction (first direction X in this embodiment) perpendicular to the vertical direction, and the third portion 25 extends in the horizontal direction (first direction X in this embodiment) and on the opposite side from the second portion 24.

[0073] In this embodiment, the first portion 23 of the first contact region 34A extends along one side surface of the trench 17 from the first main surface 3 toward the second main surface 4. The first portion 23 is formed throughout the depth direction of the trench 17, from the top to the bottom of the trench 17. The first portion 23 has a lower end near the bottom of the trench 17 and an upper end near the top of the trench 17.

[0074] The first portion 23 penetrates the body region 15 and straddles the body region 15 and the electric field relaxation structure 21, which are separated from each other. Of the first portion 23, the second portion 24, and the third portion 25, at least the first portion 23 forms a boundary with the body region 15 and is connected to the body region 15. The first portion 23 is also connected to the semiconductor layer 7 (drift region 8) below the body region 15. That is, a pn junction is formed between the first contact region 34A and the drift region 8 between the body region 15 and the electric field relaxation structure 21. The first portion 23 is exposed from the side surface of the trench 17 and is in contact with the insulating film 18 at the side surface of the trench 17. A lower end of the first portion 23 may be in contact with a side surface 22 of the electric field relaxation structure 21.

[0075] The second portion 24 of the first contact region 34A extends from one side surface of the trench 17 toward the inside in the width direction of the trench 17 along the bottom surface of the trench 17. The second portion 24 penetrates from the lower end of the first portion 23 through the side surface 22 of the electric field relaxation structure 21 and is formed on the bottom wall of the trench 17 up to the middle of the trench 17 in the width direction. In this embodiment, the second portion 24 has an end in the horizontal direction approximately at the center of the trench 17 in the width direction.

[0076] Of the first portion 23, the second portion 24, and the third portion 25, at least the second portion 24 forms a boundary with the electric field relaxation structure 21 and is connected to the electric field relaxation structure 21. The second portion 24 is exposed from the bottom surface of the trench 17 and is in contact with the insulating film 18 at the bottom surface of the trench 17. Therefore, on the side surface and bottom surface of the trench 17, a first contact region 34A that is L-shaped in cross section and formed by integrating the first portion 23 and the second portion 24 partially covers the buried electrode 19 via the insulating film 18.

[0077] The third portion 25 of the first contact region 34A extends along the first main surface 3 from one side surface of the trench 17 toward the outer side of the trench 17 in the width direction (the side opposite to the extension direction of the second portion 24). The third portion 25 is formed on the top wall of the mesa portion 20 from the upper end of the first portion 23 to the middle of the mesa portion 20 in the width direction. In this embodiment, the third portion 25 has an end in the horizontal direction at approximately the center of the mesa portion 20 in the width direction. The third portion 25 is exposed from the first main surface 3. Therefore, on the side surface, bottom surface, and first main surface 3 of the trench 17, the first contact region 34A, which is formed by integrating the first portion 23, the second portion 24, and the third portion 25 and has a generally Z-shaped cross section, partially covers the buried electrode 19 via the insulating film 18 and is exposed from the first main surface 3 for contact.

[0078] The first portion 23 has a first thickness T1A. The first thickness T1A may be the thickness of the first portion 23 in the horizontal direction from the side surface of the trench 17. The first thickness T1A may be, for example, not less than 10 nm and not more than 500 nm, preferably not less than 50 nm and not more than 200 nm.

[0079] The second portion 24 has a second thickness T2A. The second thickness T2A may be the thickness of the second portion 24 in the vertical direction Z from the bottom surface of the trench 17. In this embodiment, the second thickness T2A is greater than the first thickness T1A. The second thickness T2A may be, for example, not less than 100 nm and not more than 700 nm, preferably not less than 200 nm and not more than 500 nm.

[0080] The third portion 25 has a third thickness T3A. The third thickness T3A may be the thickness of the third portion 25 in the vertical direction Z from the bottom surface of the trench 17. In this embodiment, the third thickness T3A is greater than the first thickness T1A. The third thickness T3A may be approximately the same as the second thickness T2A. The third thickness T3A may be, for example, not less than 100 nm and not more than 700 nm, preferably not less than 200 nm and not more than 500 nm.

[0081] 5, the first portion 23, the second portion 24, and the third portion 25 of the first contact region 34A have the same width WA in the longitudinal direction of the trench 17. As a result, the first contact region 34A is formed in a quadrangular shape (in this embodiment, a rectangular shape) in plan view.

[0082] 5 , 8 , and 9 , the second contact regions 34B are selectively formed on the other of the two side surfaces of each trench 17 and are arranged at intervals in the second direction Y. Each second contact region 34B extends along the other sidewall of each trench 17 in the depth direction of each trench 17 from the first main surface 3 toward the second main surface 4, and is electrically connected to the body region 15 and the electric field relaxation structure 21.

[0083] More specifically, each second contact region 34B integrally includes a first portion 26, a second portion 27, and a third portion 28, each of which extends in a different direction. Of the multiple portions of the second contact region 34B, the first portion 26 extends in the depth direction of the trench 17 (i.e., the vertical direction Z), the second portion 27 extends in a horizontal direction (first direction X in this embodiment) perpendicular to the vertical direction, and the third portion 28 extends in the horizontal direction (first direction X in this embodiment) and on the opposite side from the second portion 27.

[0084] In this embodiment, the first portion 26 of the second contact region 34B extends from the first main surface 3 toward the second main surface 4 along the other side surface of the trench 17. The first portion 26 is formed throughout the depth direction of the trench 17, from the top to the bottom of the trench 17. The first portion 26 has a lower end near the bottom of the trench 17 and an upper end near the top of the trench 17.

[0085] The first portion 26 penetrates the body region 15 and straddles the body region 15 and the electric field relaxation structure 21, which are separated from each other. Of the first portion 26, the second portion 27, and the third portion 28, at least the first portion 26 forms a boundary with the body region 15 and is connected to the body region 15. The first portion 26 is also connected to the semiconductor layer 7 (drift region 8) below the body region 15. That is, a pn junction is formed between the second contact region 34B and the drift region 8 between the body region 15 and the electric field relaxation structure 21. The first portion 26 is exposed from the side surface of the trench 17 and is in contact with the insulating film 18 at the side surface of the trench 17. A lower end of the first portion 26 may be in contact with a side surface 22 of the electric field relaxation structure 21.

[0086] The second portion 27 of the second contact region 34B extends along the bottom surface of the trench 17 from the other side surface of the trench 17 toward the inside in the width direction of the trench 17. The second portion 27 penetrates from the lower end of the first portion 26 through the side surface 22 of the electric field relaxation structure 21 and is formed on the bottom wall of the trench 17 to the middle of the trench 17 in the width direction. In this embodiment, the second portion 27 has an end in the horizontal direction approximately at the center in the width direction of the trench 17.

[0087] Of the first portion 26, the second portion 27, and the third portion 28, at least the second portion 27 forms a boundary with the electric field relaxation structure 21 and is connected to the electric field relaxation structure 21. The second portion 27 is exposed from the bottom surface of the trench 17 and is in contact with the insulating film 18 at the bottom surface of the trench 17. Therefore, on the side surface and bottom surface of the trench 17, a second contact region 34B that is L-shaped in cross section and formed by integrating the first portion 26 and the second portion 27 partially covers the buried electrode 19 via the insulating film 18.

[0088] The third portion 28 of the second contact region 34B extends along the first main surface 3 from the other side surface of the trench 17 toward the outer side of the trench 17 in the width direction (the side opposite to the extension direction of the second portion 27). The third portion 28 is formed on the top wall of the mesa portion 20 from the upper end of the first portion 26 to the middle of the mesa portion 20 in the width direction. In this embodiment, the third portion 28 has an end in the horizontal direction at approximately the center of the mesa portion 20 in the width direction. The third portion 28 is exposed from the first main surface 3. Therefore, on the side surface, bottom surface, and first main surface 3 of the trench 17, the second contact region 34B, which is generally Z-shaped in cross section and is formed by integrating the first portion 26, the second portion 27, and the third portion 28, partially covers the buried electrode 19 via the insulating film 18 and is exposed from the first main surface 3 for contact.

[0089] The first portion 26 has a first thickness T1B. The first thickness T1B may be the thickness of the first portion 26 in the horizontal direction from the side surface of the trench 17. The first thickness T1B may be, for example, not less than 10 nm and not more than 500 nm, preferably not less than 50 nm and not more than 200 nm.

[0090] The second portion 27 has a second thickness T2B. The second thickness T2B may be the thickness of the second portion 27 in the vertical direction Z from the bottom surface of the trench 17. In this embodiment, the second thickness T2B is greater than the first thickness T1B. The second thickness T2B may be, for example, not less than 100 nm and not more than 700 nm, preferably not less than 200 nm and not more than 500 nm.

[0091] The third portion 28 has a third thickness T3B. The third thickness T3B may be the thickness of the third portion 28 in the vertical direction Z from the bottom surface of the trench 17. In this embodiment, the third thickness T3B is greater than the first thickness T1B. The third thickness T3B may be approximately the same as the second thickness T2B. The third thickness T3B may be, for example, not less than 100 nm and not more than 700 nm, preferably not less than 200 nm and not more than 500 nm.

[0092] 5, the first portion 26, the second portion 27, and the third portion 28 of the second contact region 34B have the same width WB in the longitudinal direction of the trench 17. As a result, the second contact region 34B is formed in a quadrangular shape (a rectangular shape in this embodiment) in plan view.

[0093] 5, the first contact regions 34A and the second contact regions 34B are arranged at intervals in the longitudinal direction of the trenches 17. In this embodiment, the multiple first contact regions 34A are uniformly arranged on one side of each trench 17 in the width direction across the multiple trenches 17. The multiple second contact regions 34B are uniformly arranged on the other side of each trench 17 in the length direction across the multiple trenches 17. In other words, the multiple first contact regions 34A are formed on one side of all trenches 17 in the width direction, and the multiple second contact regions 34B are formed on the other side.

[0094] In this embodiment, the first contact regions 34A and the second contact regions 34B are arranged alternately at intervals in each mesa portion 20. In other words, the second contact region 34B of one trench 17B of a pair of trenches 17A, 17B among the plurality of trenches 17 is arranged adjacent to a region 29 between the plurality of first contact regions 34A of the other trench 17A in the first direction X (the width direction of the trench 17). Furthermore, the first contact region 34A of one trench 17B is arranged adjacent to a region 30 between the plurality of second contact regions 34B of the other trench 17B in the first direction X (the width direction of the trench 17). As a result, the first contact regions 34A and the second contact regions 34B are arranged in a staggered pattern in a plan view as a whole.

[0095] In each mesa portion 20, the body region 15 includes a channel portion 31 and a non-channel portion 32. The channel portion 31 is a region in the body region 15 where the multiple contact regions 34A, 34B are not formed. In this embodiment, the regions 29 and 30 are the channel portion 31. A channel is formed along the wall surface of the trench 17 adjacent to the channel portion 31. In the non-channel portion 32, the wall surface of the adjacent trench 17 is covered with the contact regions 34A, 34B from the top to the bottom of the trench 17.

[0096] The semiconductor device 1 includes a source region 33 formed in a region between the plurality of trench structures 16 in a surface layer portion of the first main surface 3 (active surface 11). The source region 33, which is an example of a third impurity region, is formed in a surface layer portion of the body region 15. In this embodiment, the source region 33 is formed in a region of the mesa portion 20 where the plurality of contact regions 34A, 34B are not formed. As described above, in each mesa portion 20, the first contact regions 34A and the second contact regions 34B are arranged alternately on the left and right in the length direction of the trench 17, with a space therebetween. The region of the body region 15 where the source region 33 is formed is the aforementioned channel portion 31. As shown in FIG. 5 , the source region 33 is formed in a zigzag pattern in the second direction Y, passing between the plurality of first contact regions 34A and the plurality of second contact regions 34B arranged alternately on the left and right.

[0097] As a result, in each mesa portion 20, a plurality of first channel sections 35 and a plurality of second channel sections 36 are alternately arranged in the second direction Y (the length direction of the trench 17). The first channel sections 35 are channel portions 31 corresponding to the region 29, and the second channel sections 36 are channel portions 31 corresponding to the region 30. The first channel sections 35 and the second channel sections 36 may have overlapping channel sections 49 that overlap in the first direction X. In the overlapping channel sections 49, channels are formed on both wall surfaces of the trench 17 on both sides of the mesa portion 20 in the first direction X.

[0098] The source region 33 has a higher n-type impurity concentration (peak value) than the semiconductor layer 7. The source region 33 has a peak value of 1×10 １８ cm－３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0099] The source regions 33 are formed at intervals from the bottom of the body region 15 toward the active surface 11, and face the drift regions 8 directly below, sandwiching a part of the body region 15 in the vertical direction Z. The multiple source regions 33, together with the multiple drift regions 8 directly below, define channels (current paths) that extend along the wall surfaces of the corresponding trench structures 16.

[0100] The configuration of the outer peripheral region 10 will be described below. Fig. 11 is a perspective view showing the configuration of the outer peripheral region 10. Fig. 12 is a cross-sectional view showing a main part of the outer peripheral region 10.

[0101] The semiconductor device 1 includes a p-type well region 37 formed in a surface layer portion of the outer peripheral surface 12. The well region 37 is formed at an interval from the periphery of the outer peripheral surface 12 (first to fourth side surfaces 5A to 5D) toward the active surface 11 in a plan view, and extends in a band shape along the active surface 11. In this embodiment, the well region 37 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 11 in a plan view.

[0102] The well region 37 is drawn out from the surface layer portion of the outer peripheral surface 12 toward the first to fourth connection surfaces 13A to 13D and extends along the surface layer portions of the first to fourth connection surfaces 13A to 13D. The well region 37 is electrically connected to the body region 15 in the surface layer portion of the active surface 11.

[0103] The well region 37 is formed at a distance from the lower end of the semiconductor layer 7 toward the outer peripheral surface 12, and faces the base layer 6 across a part of the semiconductor layer 7. The well region 37 forms a pn junction with the semiconductor layer 7. The well region 37 has a density of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The well region 37 may have the following p-type impurity concentration as a peak value: The well region 37 has a p-type impurity concentration lower than the p-type impurity concentrations of the plurality of contact regions 34A, 34B.

[0104] The p-type impurity concentration of the well region 37 may be higher than the p-type impurity concentration of the body region 15. Of course, the p-type impurity concentration of the well region 37 may be lower than the body region 15. The p-type impurity concentration of the well region 37 is preferably adjusted by at least one kind of trivalent element. The trivalent element of the well region 37 may be the same as the trivalent element of the electric field relaxation structure 21, or may be a different kind from the trivalent element of the electric field relaxation structure 21. The trivalent element of the well region 37 may be at least one kind of boron, aluminum, gallium, and indium.

[0105] The semiconductor device 1 includes at least one (preferably two to 20) p-type field region 38 formed in the surface layer of the outer peripheral surface 12 (first main surface 3) in the outer peripheral region 10. The number of the multiple field regions 38 is typically four to eight. The multiple field regions 38 are formed in an electrically floating state and relieve the electric field within the chip 2 at the periphery of the first main surface 3. The number, width, depth, p-type impurity concentration, etc. of the field region 38 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0106] In this embodiment, the field regions 38 are arranged at intervals from the periphery (first to fourth connection surfaces 13A to 13D) of the active surface 11 and the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. Specifically, the field regions 38 are arranged at intervals from the well region 37 toward the periphery of the outer circumferential surface 12.

[0107] The plurality of field regions 38 are formed in strip shapes extending along the active region 9 in plan view. Each of the plurality of field regions 38 has a portion extending in strip shape in the first direction X and a portion extending in strip shape in the second direction Y. In this embodiment, the plurality of field regions 38 are formed in an annular shape (specifically, a quadrangular annular shape) surrounding the active region 9 (i.e., the plurality of electric field relaxation structures 21) in plan view.

[0108] The plurality of field regions 38 are formed in the semiconductor layer 7 at intervals from the lower end of the semiconductor layer 7 toward the outer peripheral surface 12, and form pn junctions with the semiconductor layer 7. The plurality of field regions 38 preferably have bottoms located closer to the outer peripheral surface 12 than the intermediate portion of the thickness range of the semiconductor layer 7.

[0109] In this embodiment, the multiple field regions 38 are formed at intervals from the electric field relaxation structure 21 toward the periphery of the chip 2. Therefore, the multiple field regions 38 do not face the electric field relaxation structure 21 in the vertical direction Z. The multiple field regions 38 are located closer to the second main surface 4 of the semiconductor layer 7 than the bottom wall of the trench structure 16.

[0110] The bottoms of the plurality of field regions 38 may be located closer to the first main surface 3 of the semiconductor layer 7 than the depth position of the bottom of the electric field relaxation structure 21. Of course, the bottoms of the plurality of field regions 38 may be located closer to the second main surface 4 of the semiconductor layer 7 than the depth position of the bottom of the electric field relaxation structure 21.

[0111] The plurality of field regions 38 are 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the field region 38 may be approximately equal to the p-type impurity concentration of the body region 15. The p-type impurity concentrations of the plurality of field regions 38 may be higher than the p-type impurity concentration of the body region 15. The p-type impurity concentrations of the plurality of field regions 38 may be lower than the p-type impurity concentration of the body region 15.

[0112] The p-type impurity concentrations of the plurality of field regions 38 are preferably adjusted by at least one trivalent element. The trivalent element in the field regions 38 may be the same as or different from the trivalent element in the electric field relaxation structure 21. The trivalent element in the field regions 38 may be at least one of boron, aluminum, gallium, and indium.

[0113] The field regions 38 preferably have a width different from the relaxed width WR of the electric field relaxation structure 21. In other words, the electric field relaxation effect of the field regions 38 is preferably adjusted separately from the electric field relaxation structures 21. It is particularly preferable that the width of the field regions 38 be smaller than the relaxed width WR. Of course, the width of the field regions 38 may be larger than the relaxed width WR. Alternatively, the width of the field regions 38 may be approximately equal to the relaxed width WR.

[0114] The field regions 38 are preferably formed at a pitch different from the relaxed pitch PR of the electric field relaxation structure 21. It is particularly preferable that the pitch of the field regions 38 be smaller than the relaxed pitch PR. The pitch of the field regions 38 may be larger than the relaxed pitch PR. The pitch of the field regions 38 may also be approximately equal to the relaxed pitch PR.

[0115] The semiconductor device 1 includes an interlayer insulating film 39 covering the first main surface 3. The interlayer insulating film 39 may also be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. In this embodiment, the interlayer insulating film 39 has a stacked structure including a first insulating film 40 and a second insulating film 41. The first insulating film 40 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 40 include a silicon oxide film made of an oxide of the chip 2 (semiconductor layer 7).

[0116] The first insulating film 40 selectively covers the first main surface 3 in the active region 9 and the peripheral region 10. Specifically, the first insulating film 40 selectively covers the active surface 11, the peripheral surface 12, and the first to fourth connecting surfaces 13A to 13D. The first insulating film 40 is connected to the insulating film 18 in the active surface 11, exposing the buried electrode 19.

[0117] The first insulating film 40 covers the well region 37 and the multiple field regions 38 on the outer peripheral surface 12. In this embodiment, the first insulating film 40 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the first insulating film 40 may be formed at an interval inward from the periphery of the outer peripheral surface 12, exposing the semiconductor layer 7 from the periphery of the outer peripheral surface 12. The first insulating film 40 covers the body region 15 and the well region 37 on the first to fourth connecting surfaces 13A to 13D.

[0118] The second insulating film 41 is stacked on the first insulating film 40. The second insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 39 preferably includes a silicon oxide film. The second insulating film 41 covers the first main surface 3 in the active region 9 and the peripheral region 10, sandwiching the first insulating film 40 therebetween. Specifically, the second insulating film 41 selectively covers the active surface 11, the peripheral surface 12, and the first to fourth connecting surfaces 13A to 13D, sandwiching the first insulating film 40 therebetween.

[0119] The second insulating film 41 covers the multiple trench structures 16 (buried electrodes 19) in the active region 9. The second insulating film 41 covers the well region 37 and the multiple field regions 38 in the peripheral region 10, sandwiching the first insulating film 40 therebetween. In this embodiment, the second insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D. Of course, the second insulating film 41 may be formed at a distance inward from the periphery of the peripheral surface 12, and may expose the periphery of the first main surface 3 together with the first insulating film 40.

[0120] The semiconductor device 1 includes a plurality of contact openings 42 formed in the interlayer insulating film 39. The plurality of contact openings 42 include a plurality of contact openings 42 (not shown) that expose the plurality of trench structures 16 (buried electrodes 19) and a plurality of contact openings 42 that expose the plurality of source regions 33. The plurality of contact openings 42 for the source regions 33 are formed in regions between the plurality of adjacent trench structures 16, and expose the plurality of source regions 33 and the plurality of contact regions 34.

[0121] The semiconductor device 1 includes a sidewall structure 43 disposed in the interlayer insulating film 39 so as to cover at least one of the first to fourth connecting surfaces 13A to 13D. The sidewall structure 43 is disposed on the first insulating film 40 and is covered by the second insulating film 41. The sidewall structure 43 reduces a step formed between the active surface 11 and the outer peripheral surface 12.

[0122] The sidewall structure 43 is formed in a strip shape extending along at least one of the first to fourth connecting surfaces 13A to 13D. In this embodiment, the sidewall structure 43 is formed in a ring shape (specifically, a rectangular ring shape) extending along the first to fourth connecting surfaces 13A to 13D so as to surround the active surface 11 in a plan view.

[0123] The sidewall structure 43 may have a portion extending in a film-like manner along the outer peripheral surface 12 and a portion extending in a film-like manner along the first to fourth connecting surfaces 13A to 13D. In this embodiment, the sidewall structure 43 is formed at a distance from the innermost field region 38 toward the active surface 11, and faces the well region 37 in the horizontal and vertical directions Z, with the first insulating film 40 sandwiched therebetween. The sidewall structure 43 may face the body region 15, with the first insulating film 40 sandwiched therebetween.

[0124] 1 , semiconductor device 1 includes a gate pad 44 disposed on interlayer insulating film 39. Gate pad 44 is an electrode to which a gate potential is applied from the outside. Gate pad 44 may also be referred to as a "gate pad electrode," a "first pad electrode," or the like. Gate pad 44 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 39 side.

[0125] In this embodiment, the gate pad 44 is disposed on a portion of the interlayer insulating film 39 that covers the active region 9. Specifically, the gate pad 44 is disposed on the active surface 11 at a distance from the outer peripheral surface 12 in a plan view. The gate pad 44 is disposed in a region close to the center of one side of the active surface 11 (the second connection surface 13B in this embodiment) in a plan view.

[0126] Of course, the gate pad 44 may be disposed in a region along any of the central portions of the first to fourth connection surfaces 13A to 13D. Of course, the gate pad 44 may be disposed at any corner of the active surface 11 in a plan view. The gate pad 44 may also be disposed at the central portion of the active surface 11 in a plan view. In this embodiment, the gate pad 44 is formed in a quadrangular shape in a plan view.

[0127] The semiconductor device 1 includes at least one gate wiring 45 (a plurality of gate wirings in this embodiment) extending from the gate pad 44 onto the interlayer insulating film 39. The gate wiring 45 may also be referred to as a "wiring" or "wiring electrode." In this embodiment, the plurality of gate wirings 45 are arranged on the active surface 11 at intervals from the outer peripheral surface 12 in a plan view.

[0128] The plurality of gate wirings 45 may have a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the side of the interlayer insulating film 39. In this embodiment, the plurality of gate wirings 45 include a first gate wiring 45A and a second gate wiring 45B.

[0129] The first gate wiring 45A is drawn out from the gate pad 44 toward the first connection surface 13A and extends in a line along the periphery of the active surface 11 so as to intersect (specifically, perpendicular to) part of (specifically, one end portion) of the multiple trench structures 16. The first gate wiring 45A penetrates the interlayer insulating film 39 via the multiple contact openings 42 and is electrically connected to one end portion of the multiple trench structures 16.

[0130] The second gate wiring 45B is drawn out from the gate pad 44 toward the third connection surface 13C and extends in a line along the periphery of the active surface 11 so as to intersect (specifically, perpendicular to) part of (specifically, the other end portions of) the multiple trench structures 16. The second gate wiring 45B penetrates the interlayer insulating film 39 via the multiple contact openings 42 and is electrically connected to the other end portions of the multiple trench structures 16.

[0131] The semiconductor device 1 includes a source pad 46 disposed on the interlayer insulating film 39 at a distance from the gate pad 44 and the gate wiring 45. The source pad 46 is an electrode to which a source potential is applied from the outside. The source pad 46 may also be referred to as a "source pad electrode," a "second pad electrode," or the like. The source pad 46 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 39 side.

[0132] In this embodiment, the source pad 46 is disposed on the active surface 11 at a distance from the outer peripheral surface 12 in a plan view. In this embodiment, the source pad 46 is formed in a polygonal shape having a recess that is recessed along the gate pad 44 in a plan view. Of course, the source pad 46 may also be formed in a quadrangular shape in a plan view.

[0133] The source pad 46 penetrates the interlayer insulating film 39 via the contact openings 42, and is electrically connected to the body region 15, the source regions 33, and the contact regions 34A and 34B. That is, the source pad 46 is electrically connected to the electric field relaxation structures 21 via the body region 15 and the contact regions 34A and 34B.

[0134] The semiconductor device 1 includes a drain pad 47 covering the second main surface 4. The drain pad 47 is an electrode to which a drain potential is applied from the outside. The drain pad 47 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 47 forms ohmic contact with the base layer 6 exposed from the second main surface 4.

[0135] That is, the drain pad 47 is electrically connected to the plurality of drift regions 8 via the base layer 6. The drain pad 47 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 47 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0136] The breakdown voltage that can be applied between source pad 46 and drain pad 47 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0137] 13 is a schematic diagram showing a wafer 50 used in manufacturing the semiconductor device 1. The wafer 50 is a substrate of the base layer 6 and contains SiC single crystal. The wafer 50 is formed in a flat disk shape. Of course, the wafer 50 may also be formed in a flat rectangular parallelepiped shape. The wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.

[0138] The first wafer main surface 51 corresponds to the upper end of the base layer 6, and the second wafer main surface 52 corresponds to the lower end of the base layer 6. The first wafer main surface 51 and the second wafer main surface 52 are formed by the c-plane of the SiC single crystal. The first wafer main surface 51 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 52 is formed by the carbon surface of the SiC single crystal. The wafer 50 (the first wafer main surface 51 and the second wafer main surface 52) has the off-direction Do and the off-angle θo described above.

[0139] The wafer 50 has a mark 54 on the wafer side surface 53 that indicates the crystal orientation of the SiC single crystal. The mark 54 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 51 in a plan view.

[0140] The mark 54 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 54 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction. Figure 12 shows an orientation flat extending in the m-axis direction (first direction X) in a plan view.

[0141] For example, a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like. Each device region 55 corresponds to a semiconductor device 1. Each of the plurality of device regions 55 is set to have a quadrangular shape in a plan view.

[0142] In this embodiment, the device regions 55 are set in a matrix along the first direction X and the second direction Y in a plan view. The device regions 55 are set at intervals inward from the periphery of the first wafer main surface 51 in a plan view. The cutting lines 56 are set in a grid pattern extending along the first direction X and the second direction Y to partition the device regions 55.

[0143] Fig. 14 is a flowchart showing an example of a method for manufacturing the semiconductor device 1. Fig. 15A to Fig. 15G are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1. Fig. 15A to Fig. 15G are cross-sectional views corresponding to Fig. 6.

[0144] 15A, the aforementioned wafer 50 preparation step is performed (step S1 in FIG. 14). Next, the semiconductor layer 7 formation step is performed (step S2 in FIG. 14). The semiconductor layer 7 is formed by epitaxial growth starting from the first wafer main surface 51 (wafer 50).

[0145] 15B , the step of forming body region 15 is performed (step S3 in FIG. 14 ). In the step of forming body region 15, p-type impurities are introduced into the entire semiconductor layer 7. As a result, body region 15 is formed over the entire surface portion of semiconductor layer 7.

[0146] 15C , a step of forming source region 33 is performed (step S4 in FIG. 14 ). In the step of forming source region 33, n-type impurities are selectively introduced into semiconductor layer 7 (surface portion of body region 15). As a result, source region 33 is formed in the surface portion of body region 15.

[0147] Next, referring to FIG. 15D , a process for forming multiple trenches 17 is performed. First, a first mask 60 having a predetermined pattern is formed (step S5 in FIG. 14 ). The first mask 60 is preferably an inorganic mask (hard mask). The first mask 60 has multiple first openings 61 that expose regions where the multiple trenches 17 will be formed. Next, unnecessary portions of the semiconductor layer 7 are removed by etching through the first mask 60. The etching method may be either wet etching or dry etching, or both. The etching method is preferably RIE (reactive ion etching). This forms multiple trenches 17 at the upper end of the semiconductor layer 7 (step S6 in FIG. 14 ). Furthermore, the active surface 11, the outer peripheral surface 12, and the first to fourth connecting surfaces 12A to 12D are formed at the upper end of the semiconductor layer 7.

[0148] 15E , a step of forming a plurality of electric field relaxation structures 21 is performed (step S7 in FIG. 14 ) with the first mask 60 remaining on the semiconductor layer 7. In the step of forming the electric field relaxation structures 21, p-type impurities are selectively introduced into the semiconductor layer 7 through the first mask 60. As a result, the electric field relaxation structures 21 are formed at the bottom of each trench 17.

[0149] Various ion implantation methods can be applied as a method for forming the electric field relaxation structure 21. For example, the electric field relaxation structure 21 may be formed by a channeling ion implantation method. The channeling implantation process is performed based on data (information) of the off-angle θo. The channeling implantation process allows the electric field relaxation structure 21 to be selectively and easily formed at a deep position in the semiconductor layer 7. When the electric field relaxation structure 21 is formed by a channeling ion implantation method, the electric field relaxation structure 21 may be formed before the body region 15. Thereafter, the first mask 60 is removed.

[0150] Next, referring to FIG. 15F, the step of forming the plurality of contact regions 34A, 34B is performed. First, a second mask 62 having a predetermined pattern is formed (step S8 in FIG. 14). The second mask 62 is preferably an inorganic mask (hard mask). The second mask 62 has a plurality of second openings 63 that expose regions where the plurality of contact regions 34A, 34B will be formed.

[0151] Next, p-type impurities are introduced into the surface portion of the semiconductor layer 7 by ion implantation through a second mask 62, thereby forming multiple contact regions 34A and 34B. In this embodiment, oblique implantation is performed at a predetermined angle relative to the first wafer main surface 51. This allows ions to be implanted into the side surfaces of the trench 17 as well as into the first wafer main surface 51 and the bottom of the trench 17. Meanwhile, as described above, the trench structure 16 has an aspect ratio DT / WT (e.g., 1 to 5) that extends vertically like a long column, and the trench depth DT is much larger than the trench width WT. Therefore, the implantation angle must be large to implant ions evenly into the entire side surfaces of the trench 17. As a result, the ion implantation depth from the side surfaces of the trench 17 becomes shallow, and the resulting multiple contact regions 34A and 34B have the following relationships: second thickness T2A < first thickness T1A, third thickness T3A, and second thickness T2B < first thickness T1B, third thickness T3B.

[0152] Next, referring to FIG. 15G , the step of forming the insulating film 18 is performed (step S10 in FIG. 14 ). The step of forming the insulating film 18 also serves as the step of forming the first insulating film 40. The insulating film 18 may be formed by either or both of a CVD (Chemical Vapor Deposition) method and an oxidation treatment method. The insulating film 18 and the first insulating film 40 are typically formed by a thermal oxidation treatment method. The insulating film 18 is formed in the form of a film on the wall surfaces of the plurality of trenches 17, and the first insulating film 40 is formed in the form of a film in the region of the upper end of the semiconductor layer 7 outside the plurality of trenches 17.

[0153] Next, a buried electrode 19 formation process is performed (step S11 in FIG. 14 ). This process includes a step of forming a base electrode film on the insulating film 18. In this embodiment, the base electrode film includes conductive polysilicon. The base electrode film backfills the multiple trenches 17 and covers the upper end of the semiconductor layer 7. The base electrode film may be formed by a CVD method. Next, unnecessary portions of the buried electrode 19 are removed by an etching method. The unnecessary portions of the buried electrode 19 are removed until the insulating film 18 is exposed. The etching method may be either a wet etching method or a dry etching method, or both. As a result, multiple buried electrodes 19 are respectively embedded in the multiple trenches 17, and multiple trench structures 16 are formed.

[0154] Next, a step of forming an interlayer insulating film 39 (second insulating film 41) is performed (step S12 in FIG. 14). The interlayer insulating film 39 may be formed by a CVD method. A plurality of contact openings 42 having a predetermined layout are formed in the interlayer insulating film 39 by an etching method using a mask (not shown) having a predetermined layout.

[0155] Next, a process for forming the gate pad 44, the gate wiring 45, and the source pad 46 is performed (step S13 in FIG. 14). The gate pad 44, the gate wiring 45, and the source pad 46 are formed by depositing a metal film on the interlayer insulating film 39 by sputtering, and then shaping the metal film into a predetermined layout by etching using a mask (not shown) having a predetermined layout.

[0156] Next, a step of forming drain pads 47 is carried out (step S14 in FIG. 14). The drain pads 47 are formed by depositing a metal film on the second wafer main surface 52 by sputtering. Thereafter, the wafer 50 is cut along a plurality of cutting lines 56 (step S15 in FIG. 14). Through the steps including those described above, a plurality of semiconductor devices 1 are manufactured from a single wafer 50.

[0157] As described above, the electric field relaxation structure 21 is formed on the bottom wall of the trench 17, which can relax the electric field concentration on the bottom wall of the trench 17 in a trench gate structure related to a MISFET (Metal Insulator Semiconductor Field Effect Transistor). Furthermore, the electric field relaxation structure 21 is connected to the plurality of contact regions 34A, 34B, which can fix the electric field relaxation structure 21 to a predetermined potential (the source potential in this embodiment) via the plurality of contact regions 34A, 34B. For example, by setting the source potential to the ground potential, the electric field concentration on the bottom wall of the trench 17 can be stably relaxed.

[0158] Furthermore, multiple contact regions 34A, 34B for contacting the electric field relaxation structure 21 are separately arranged on one side and the other side of each trench 17 in the width direction. In this configuration, the first contact regions 34A and the second contact regions 34B are arranged alternately on the left and right sides along the length of the trench 17 of each mesa portion 20, with a gap therebetween. This results in the source region 33 being formed in a zigzag pattern in the second direction Y, and multiple first channel sections 35 and multiple second channel sections 36 being arranged alternately in the second direction Y (the length direction of the trench 17). As a result, channels can be formed evenly along the length of the trench 17, thereby achieving an even current balance during a short circuit. This prevents local current concentration in the mesa portion 20 and improves breakdown resistance.

[0159] For example, in a configuration in which the contact region 34A is selectively formed only on one side in the width direction of each trench 17, the channel current is biased toward the other side in the width direction of each trench 17. As a result, current concentrates on the other side in the width direction of each trench 17, increasing the number of cases in which breakdown occurs in the event of a short circuit. In contrast, in the configuration described above, the channel can be formed evenly and balanced along the length of the trench 17, preventing current concentration and improving breakdown resistance.

[0160] 16 to 22 are diagrams showing first to sixth modified examples of the semiconductor device 1. Next, the modified examples of the semiconductor device 1 will be described with reference to FIGS.

[0161] 16 , the side surface 22 of the plurality of electric field relief structures 21 may be located at the center in the width direction of the trench 17. More specifically, each electric field relief structure 21 is formed integrally with the body region 15 and is formed on one side of the trench 17 in the first direction X. In this embodiment, each electric field relief structure 21 extends downward in the vertical direction Z from a part of the body region 15 sandwiched between two adjacent trenches 17 below the bottom wall of the trench 17, spreads along the horizontal direction along the first main surface 3, and overlaps the bottom wall of the trench 17. As a result, each electric field relief structure 21 has a substantially L-shaped exposed surface in each trench 17 that is exposed as the lower part of the side wall of the trench 17 and the bottom wall of the trench 17 that is continuous with the lower part of the side wall.

[0162] The electric field relaxation structure 21 may integrally include a base portion 57 located closer to the second main surface 4 than the bottom wall of the trench 17 , and a protruding portion 58 sandwiched between two adjacent trenches 17 .

[0163] The base portion 57 overlaps each trench 17 and crosses the sidewall of each trench 17 in the first direction X. The base portion 57 has an end that protrudes outward in the horizontal direction beyond the region directly below the mesa portion 20. The protrusion 58 extends from the base portion 57 along the sidewall of each trench 17 toward the inside of the mesa portion 20 and is connected to the bottom of the body region 15. The protrusion 58 is formed from the bottom wall of the trench 17 to the body region 15 in the vertical direction Z.

[0164] The plurality of first contact regions 34A and the plurality of second contact regions 34B penetrate the body region 15 and the protruding portion 58 in the vertical direction Z, and are further connected to the base portion 57 .

[0165] Although not shown, a plurality of electric field relaxation structures 21 may be arranged at intervals in the second direction Y. In this case, the electric field relaxation structure 21 corresponding to the second contact region 34B may be formed on the other side of the trench 17 in the first direction X (i.e., on the opposite side of the trench 17 from the electric field relaxation structure 21 in FIG. 16 ). This allows the second contact region 34B to be connected to the protrusion 58 and base 57 of the electric field relaxation structure 21.

[0166] According to this configuration, multiple contact regions 34A, 34B for contacting the electric field relaxation structure 21 are separately arranged on one side and the other side of each trench 17 in the width direction (only the first contact region 34 is shown in FIG. 16 ). This allows channels to be formed evenly in the length direction of the trench 17, thereby making it possible to evenly balance the current during a short circuit. As a result, it is possible to prevent local current concentration in the mesa portion 20 and improve the breakdown resistance.

[0167] 17 and 18 , a first contact region 34A formed along the side surface of one trench 17A of a pair of trenches 17A, 17B among the plurality of trenches 17 and a second contact region 34B formed along the side surface of the other trench 17B may be integrated to form one contact region 59 spanning one trench 17A and the other trench 17B. Note that, although reference symbols "17A" and "17B" are shown one by one as an example in FIGS. 17 and 18 , the pair of trenches 17A, 17B may be selected from any pair of trenches 17.

[0168] The contact regions 59 are arranged in a staggered pattern in a plan view. For example, a pair of the multiple mesas 20 in the first direction X is defined as a first mesa 20A and a second mesa 20B. In the first mesa 20A, multiple contact regions 59A (which may also be referred to as "first contact regions") are arranged at intervals in the extension direction of the trench structure 16. In the second mesa 20B, multiple contact regions 59B (which may also be referred to as "second contact regions") are arranged at intervals in the extension direction of the trench structure 16. The multiple contact regions 59A and the multiple contact regions 59B are arranged so as not to overlap with each other in the first direction X. As a result, the multiple contact regions 59A and the multiple contact regions 59B are arranged in a staggered pattern as a whole.

[0169] In each mesa portion 20, a region in which the multiple contact regions 59 are not formed is a channel section 64. The channel section 64 is a region having a constant width in the second direction Y. On the other hand, in each mesa portion 20, a region in which the multiple contact regions 59 are formed is a non-channel section 65. The non-channel section 65 is a region having a constant width in the second direction Y. In each mesa portion 20, the channel sections 64 and the non-channel sections 65 are arranged alternately in the extension direction of the trench structure 16.

[0170] According to this configuration, the channel sections 64 and non-channel sections 65 are alternately arranged on both sides of each trench 17. This allows channels to be formed evenly in the longitudinal direction of the trench 17, thereby making it possible to evenly balance the current during a short circuit. As a result, it is possible to prevent local current concentration in the mesa portion 20 and improve the breakdown resistance.

[0171] Referring to Figure 19, the side surface 22 of each electric field relaxation structure 21 does not need to be a planar shape that is flush with the side surface of the trench 17 in the vertical direction Z, and may have a bulge portion 66 that bulges toward the horizontal direction (at least one of the first direction X and the second direction Y).

[0172] 20, the element structure of semiconductor device 1 may be an IGBT (Insulated Gate Bipolar Transistor) structure, different from the MISFET structure of FIGS. 6 to 10. In this case, a p-type collector region 71 may be formed instead of base layer 6. Furthermore, a p-type base region 72 may be formed by body region 15, and an n-type emitter region 73 may be formed by source region 33.

[0173] According to this configuration, multiple contact regions 34A, 34B for contacting the electric field relaxation structure 21 are separately arranged on one side and the other side of each trench 17 in the width direction (only the first contact region 34 is shown in FIG. 20 ). This allows channels to be formed evenly in the length direction of the trench 17, thereby making it possible to evenly balance the current when the IGBT is short-circuited. As a result, it is possible to prevent local current concentration in the mesa portion 20 and improve the breakdown resistance.

[0174] The multiple first contact regions 34A and multiple second contact regions 34B do not need to be arranged one by one in the second direction Y, alternately spaced from one another on the left and right; for example, as shown in FIG. 21, they may be arranged multiple by multiple (two by two in FIG. 21) in the second direction Y, alternately spaced from one another on the left and right, or as shown in FIG. 22, they may be arranged alternately without space between them in the second direction Y.

[0175] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0176] For example, in each of the above-described embodiments, the base layer 6 and the semiconductor layer 7 each include a SiC single crystal. However, at least one of the base layer 6 and the semiconductor layer 7 or all of the base layer 6 and the semiconductor layer 7 may include a single crystal of a wide bandgap semiconductor other than a SiC single crystal.

[0177] Wide bandgap semiconductors are semiconductors that have a bandgap larger than that of silicon. Wide bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga ２ O ３ ) are examples. The base layer 6 and the semiconductor layer 7 may be made of the same type of single crystal, or may be made of different types of single crystal. Furthermore, at least one of the base layer 6 and the semiconductor layer 7 or all of them may be made of silicon (Si).

[0178] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0179] [Supplementary Note 1-1] A chip (2) having a first main surface (3) and a second main surface (4) on the opposite side thereof; a first impurity region (7) of a first conductivity type formed in a surface layer portion of the first main surface (3); a second impurity region (15) of a second conductivity type formed in a surface layer portion of the first impurity region (7); a third impurity region (33) of a first conductivity type formed in a surface layer portion of the second impurity region (15); a trench (17) extending from the first main surface (3) through the third impurity region (33) and the second impurity region (15) to reach the first impurity region (7); an electric field relaxation structure (21) of a second conductivity type formed at the bottom of the trench (17); and a first contact region (34A) formed along one side surface of the trench (17) from the first main surface (3) toward the second main surface (4) and electrically connected to the second impurity region (15) and the electric field relaxation structure (21). and a second contact region (34B) formed along the other side surface of the trench (17) from the first main surface (3) toward the second main surface (4), electrically connected to the second impurity region (15) and the electric field relaxation structure (21), and physically separated from the first contact region (34A), wherein a plurality of the first contact regions (34A) and a plurality of the second contact regions (34B) are arranged along the longitudinal direction of the trench (17).

[0180] According to this configuration, the electric field relaxation structure (21) is formed at the bottom of the trench (17), thereby alleviating electric field concentration at the bottom of the trench (17). Furthermore, the electric field relaxation structure (21) is connected to the plurality of first contact regions (34A) and second contact regions (34B), thereby making it possible to fix the electric field relaxation structure (21) to a predetermined potential via the plurality of first contact regions (34A) and second contact regions (34B).

[0181] In addition, a plurality of first contact regions (34A) and second contact regions (34B) for contacting the electric field relaxation structure (21) are arranged separately on one side and the other side of the width direction of the trench (17). This allows a channel to be formed evenly in the length direction of the trench (17), thereby making it possible to evenly balance the current during a short circuit. This prevents local current concentration and improves breakdown resistance.

[0182] For example, in a configuration in which a contact region is selectively formed only on one side of the trench (17) in the width direction, the channel current is biased toward the other side of the trench (17) in the width direction. As a result, current concentrates on the other side of the trench (17) in the width direction, increasing the number of cases in which breakdown occurs during a short circuit. In contrast, in the above configuration, the channel can be formed evenly and balanced along the length of the trench (17), preventing current concentration and improving breakdown resistance.

[0183] [Supplementary Note 1-2] The semiconductor device (1) according to Supplementary Note 1-1, wherein the first contact region (34A) and the second contact region (34B) each integrally include a first portion (23, 26) that extends along a side surface of the trench (17) in the depth direction of the trench (17) and has a first thickness (T1A, T1B) from the side surface of the trench (17), and a second portion (24, 27) that extends from the first portion (23, 26) along a bottom surface of the trench (17) and has a second thickness (T2A, T2B) from the bottom surface of the trench (17) that is greater than the first thickness (T1A, T1B).

[0184] [Appendix 1-3] The semiconductor device (1) according to Appendix 1-2, wherein the first contact region (34A) and the second contact region (34B) each have a third portion (25, 28) formed along the first main surface (3) from an upper end of the first portion (23, 26) toward an opposite side of the trench (17), and the third portion (25, 28) is integral with the first portion (23, 26) and the second portion (24, 27).

[0185] [Appendix 1-4] The semiconductor device (1) according to Appendix 1-3, wherein the first portion (23, 26), the second portion (24, 27), and the third portion (25, 28) of the first contact region (34A) and the second contact region (34B) have the same width (WA, WB) in the longitudinal direction of the trench (17).

[0186] [Appendix 1-5] The semiconductor device (1) according to any one of Appendices 1-1 to 1-4, wherein a plurality of the first contact regions (34A) and a plurality of the second contact regions (34B) are arranged at intervals along the longitudinal direction of the trench (17).

[0187] [Appendix 1-6] The semiconductor device (1) according to any one of Appendices 1-1 to 1-5, wherein a plurality of the first contact regions (34A) and a plurality of the second contact regions (34B) are alternately arranged at intervals along the longitudinal direction of the trench (17).

[0188] [Supplementary Note 1-7] The semiconductor device (1) according to Supplementary Note 1-6, wherein a plurality of trenches (17) are arranged at intervals in a first direction (X), the plurality of first contact regions (34A) are uniformly arranged on one side of each of the trenches (17) in the first direction (X) throughout the plurality of trenches (17), and the plurality of second contact regions (34B) are uniformly arranged on the other side of each of the trenches (17) in the first direction (X) throughout the plurality of trenches (17).

[0189] [Supplementary Note 1-8] The semiconductor device (1) according to Supplementary Note 1-7, wherein the second contact region (34B) of one of a pair of trenches (17A) among the plurality of trenches (17) is arranged at a position adjacent to the first direction (X) in a region (29) between the plurality of first contact regions (34A) of the other trench (17B).

[0190] [Appendix 1-9] The semiconductor device (1) according to Appendix 1-8, wherein in the mesa portion (20) of the chip (2) sandwiched between the pair of trenches (17), the third impurity region (33) is formed in a zigzag shape along a second direction (Y) intersecting the first direction (X), passing between the plurality of first contact regions (34A) and the plurality of second contact regions (34B).

[0191] [Appendix 1-10] The semiconductor device (1) according to any one of Appendices 1-1 to 1-9, wherein the electric field relaxation structure (21) has side surfaces (22) that are flush with both side surfaces of the trench (17) in the depth direction of the trench (17).

[0192] [Appendix 1-11] The semiconductor device (1) according to any one of Appendices 1-1 to 1-10, wherein the electric field relaxation structure (21) has a bulge (66) that bulges laterally from at least one of the side surfaces of the trench (17).

[0193] [Appendix 1-12] The semiconductor device (1) according to any one of Appendices 1-1 to 1-4, 1-10, and 1-11, wherein a plurality of the trenches (17) are arranged at intervals, and the first contact region (34A) formed along the side surface of one of a pair of trenches (17A) of the plurality of trenches (17) and the second contact region (34B) formed along the side surface of the other trench (17B) are integrated to form a single contact region (59) spanning the one trench (17A) and the other trench (17B).

[0194] [Appendix 1-13] The semiconductor device (1) according to any one of Appendices 1-1 to 1-12, comprising: a drain region (6) of a first conductivity type formed on the second main surface (4) side of the first impurity region (7); a body region (15) formed by the second impurity region (15); a source region (33) formed by the third impurity region (33); and a trench gate structure (16) formed by the trench (17), an insulating film (18) covering the wall surface of the trench (17), and a buried electrode (19) buried in the trench (17).

[0195] [Appendix 1-14] The semiconductor device (1) according to any one of Appendices 1-1 to 1-12, comprising: a collector region (71) of a second conductivity type formed on the second main surface (4) side of the first impurity region (7); a base region (72) formed by the second impurity region (15); an emitter region (73) formed by the third impurity region (33); and a trench gate structure (16) formed by the trench (17), an insulating film (18) covering the wall surface of the trench (17), and a buried electrode (19) buried in the trench (17).

[0196] [Appendix 1-15] The semiconductor device (1) according to any one of Appendices 1-1 to 1-14, wherein the chip (2) includes a SiC chip (2).

[0197] 1: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5C: Fourth side surface 5D: Fourth side surface 6: Base layer 7: Semiconductor layer 7a: Lower region 8: Drift region 9: Active region 10: Peripheral region 11: Active surface 12: Peripheral surface 12A: Fourth connection surface 12B: Fourth connection surface 12C: Fourth connection surface 12D: Fourth connection surface 13A: First connection surface 13B: Second connection surface 13C: Third connection surface 13C: Fourth connection surface 13D: Fourth connection surface 14: Active plateau 15: Body region 16: Trench structure 17: Trench 17A : trench 17B : trench 18 : insulating film 19 : buried electrode 20 : mesa portion 20A : first mesa portion 20B : second mesa portion 21 : electric field relaxation structure 22 : side surface 23 : first portion 24 : second portion 25 : third portion 26 : first portion 27 : second portion 28 : third portion 29 : region 30 : region 31 : channel portion 32 : non-channel portion 33 : source region 34A : first contact region 34B : second contact region 35 : first channel section 36 : second channel section 37 : well region 38 : field region 39 : interlayer insulating film 40 : first insulating film 41 : second insulating film 42 : contact opening 43 : sidewall structure 44 : Gate pad 45 : Gate wiring 45A : First gate wiring 45B : Second gate wiring 46 : Source pad 47 : Drain pad 49 : Overlapping channel section 50 : Wafer 51 : First wafer main surface 52 : Second wafer main surface 53 : Wafer side surface 54 : Mark 55 : Device region 56 : Cutting line 57 : Base portion 58 : Protrusion 59 : Contact region 59A : Contact region 59B : Contact region 60 : First mask 61 : First opening 62 : Second mask 63 : Second opening 64 : Channel section 65 : Non-channel section 66 : Bulging portion 71 : Collector region 72 : Base region 73 : Emitter region

Claims

1. A chip having a first main surface and a second main surface on the opposite side, A first impurity region of a first conductivity type formed on the surface layer of the first main surface, A second impurity region of a second conductivity type formed on the surface of the first impurity region, A third impurity region of the first conductivity type formed on the surface of the second impurity region, A trench extending from the first main surface through the third impurity region and the second impurity region to the first impurity region, A second conductivity type field relaxation structure formed at the bottom of the trench, A first contact region is formed along one side surface of the trench from the first main surface toward the second main surface and is electrically connected to the second impurity region and the electric field relaxation structure, Formed along the other side surface of the trench from the first main surface toward the second main surface, and including the second impurity region and the electric field relaxation structure, and a second contact region that is electrically connected to the electric field relaxation structure and physically separated from the first contact region, A semiconductor device in which a plurality of the first contact regions and a plurality of the second contact regions are arranged along the length direction of the trench.

2. The semiconductor device according to claim 1, wherein the first contact region and the second contact region each integrally include a first portion having a first thickness extending from the side surface of the trench in the depth direction of the trench, and a second portion having a second thickness greater than the first thickness extending from the first portion along the bottom surface of the trench, and a second portion extending from the bottom surface of the trench.

3. The semiconductor device according to claim 2, wherein the first contact region and the second contact region each integrally have a third portion formed along the first main surface from the upper end of the first portion toward the opposite side of the trench, and the third portion is formed toward the first and second portions.

4. The semiconductor device according to claim 3, wherein the first, second, and third portions of the first and second contact regions have the same width in the longitudinal direction of the trench.

5. The semiconductor device according to claim 1, wherein a plurality of the first contact regions and a plurality of the second contact regions are arranged at intervals along the length of the trench.

6. The semiconductor device according to claim 1, wherein a plurality of the first contact regions and a plurality of the second contact regions are arranged alternately with spacings along the length of the trench.

7. Multiple trenches are arranged at intervals in the first direction. The plurality of first contact regions are uniformly arranged across the entire plurality of trenches, on one side of each trench in the first direction. The semiconductor device according to claim 6, wherein the plurality of second contact regions are uniformly arranged across the entire plurality of trenches on the other side of each trench in the first direction.

8. The semiconductor device according to claim 7, wherein the second contact region of the other trench is positioned adjacent in the first direction to the region between the plurality of first contact regions of one of the pair of trenches.

9. The semiconductor device according to claim 8, wherein in the mesa portion of the chip sandwiched between the pair of trenches, the third impurity region is formed in a zigzag pattern along a second direction intersecting the first direction, passing between the plurality of first contact regions and the plurality of second contact regions.

10. The semiconductor device according to claim 1, wherein the electric field relaxation structure has a surface that is flush with both sides of the trench in the depth direction of the trench.

11. The semiconductor device according to claim 1, wherein the electric field relaxation structure has a bulge that bulges laterally from at least one side surface of both sides of the trench.

12. Multiple trenches are arranged at intervals, The semiconductor device according to claim 1, wherein a first contact region formed along one side of one of the pair of trenches among the plurality of trenches and a second contact region formed along the other side of the trench are integrated to form a single contact region spanning the one trench and the other trench.

13. A drain region of the first conductivity type formed on the second main surface side with respect to the first impurity region, The body region formed by the second impurity region, The source region formed by the third impurity region, A semiconductor device according to any one of claims 1 to 12, comprising a trench, an insulating film covering the wall surface of the trench, and a trench gate structure formed by embedded electrodes embedded in the trench.

14. A second conductivity type collector region formed on the second main surface side with respect to the first impurity region, The base region formed by the second impurity region, The emitter region formed by the third impurity region, A semiconductor device according to any one of claims 1 to 12, comprising a trench, an insulating film covering the wall surface of the trench, and a trench gate structure formed by embedded electrodes embedded in the trench.

15. The semiconductor device according to any one of claims 1 to 12, wherein the chip includes a SiC chip.