Semiconductor device

Abstract

A semiconductor device according to the present invention comprises: a first lead; a semiconductor element that is mounted on one side of the first lead in the thickness direction and has a semiconductor layer; and a bonding layer that is interposed between the first lead and the semiconductor layer to bond the first lead and the semiconductor element. The bonding layer includes a first intermetallic compound layer containing Sn and Cu.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Various configurations have been proposed for semiconductor devices including semiconductor elements. Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a die pad and a semiconductor element. The semiconductor element is mounted on the die pad. The die pad has a pad main surface. The semiconductor element is mounted on the pad main surface by die bonding using a conductive bonding layer. The die pad is made of Cu (copper) or a copper alloy. The pad main surface is plated with Ag (silver) for bonding purposes, etc. This configuration of forming Ag plating on the pad main surface increases manufacturing costs.

[0003] Japanese Patent Application Laid-Open No. 2019-121745

[0004] [Summary] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device suitable for improving the bondability to leads of a semiconductor element while suppressing an increase in manufacturing costs.

[0005] A semiconductor device according to one aspect of the present disclosure includes a first lead, a semiconductor element mounted on one side of the first lead in a thickness direction and having a semiconductor layer, and a bonding layer interposed between the first lead and the semiconductor layer and bonding the first lead and the semiconductor element, the bonding layer including Sn and Cu.

[0006] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0007] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a perspective view showing a main portion of the semiconductor device according to the first embodiment of the present disclosure. FIG. 4 is a perspective view showing a main portion of the semiconductor device according to the first embodiment of the present disclosure. FIG. 5 is a plan view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 6 is a bottom view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 7 is a front view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 8 is a side view showing a semiconductor device according to the first embodiment of the present disclosure. FIG. 9 is a plan view showing a main portion of the semiconductor device according to the first embodiment of the present disclosure. FIG. 10 is a bottom view showing a main portion of the semiconductor device according to the first embodiment of the present disclosure. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 10. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 10. FIG. 14 is a partially enlarged cross-sectional view of FIG. 11. FIG. 15 is a partially enlarged cross-sectional view showing a step in the manufacture of the semiconductor device according to the first embodiment of the present disclosure. Fig. 16 is a partially enlarged cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. Fig. 17 is a partially enlarged cross-sectional view showing a step in the manufacture of the semiconductor device according to the second embodiment of the present disclosure. Fig. 18 is a partially enlarged cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure. Fig. 19 is a partially enlarged cross-sectional view showing a step in the manufacture of the semiconductor device according to the third embodiment of the present disclosure.

[0008] DETAILED DESCRIPTION Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0009] Terms such as "first," "second," and "third" in this disclosure are used merely as labels and are not necessarily intended to dictate any ordering of their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0011] 1 to 14 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a semiconductor element 1, a first lead 2, a second lead 3, a third lead 4, a first bonding wire 5, a second bonding wire 6, a bonding layer 7, and a sealing resin 8. The use of the semiconductor device A1 is not limited in any way, and it may be used in electronic devices equipped with a power conversion circuit, such as a DC-DC converter.

[0012] 1 and 2 are perspective views showing the semiconductor device A1. FIGS. 3 and 4 are perspective views of a main portion of the semiconductor device A1. In FIGS. 3 and 4, the outline of the sealing resin 8 is indicated by an imaginary line (two-dot chain line). FIG. 5 is a plan view showing the semiconductor device A1. FIG. 6 is a bottom view showing the semiconductor device A1. FIG. 7 is a front view showing the semiconductor device A1. FIG. 8 is a side view showing the semiconductor device A1. FIG. 9 is a plan view of a main portion of the semiconductor device A1. FIG. 10 is a bottom view of a main portion of the semiconductor device A1. In FIGS. 9 and 10, the outline of the sealing resin 8 is indicated by an imaginary line (two-dot chain line). FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 10. FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 10. FIG. 14 is a partially enlarged cross-sectional view of FIG. 11.

[0013] In these figures, for example, an example of the thickness direction in the present disclosure is referred to as the "thickness direction z." An example of a direction perpendicular to the thickness direction z is referred to as the "first direction x." An example of a direction perpendicular to the thickness direction z and the first direction is referred to as the "second direction y." Furthermore, one side of the thickness direction z is an example of the "one side of the thickness direction" in the present disclosure and is referred to as the "z1 side of the thickness direction z," and the other side of the thickness direction z is an example of the "other side of the thickness direction" in the present disclosure and is referred to as the "z2 side of the thickness direction z." One side of the first direction x is an example of the "one side of the first direction" in the present disclosure and is referred to as the "x1 side of the first direction x," and the other side of the first direction x is an example of the "other side of the first direction" in the present disclosure and is referred to as the "x2 side of the first direction x." An example of one side of the second direction y is referred to as the "y1 side of the second direction y," and an example of the other side of the second direction y is referred to as the "y2 side of the second direction y."

[0014] The semiconductor element 1 is an element that performs the electrical function of the semiconductor device A1. In this embodiment, the semiconductor element 1 is a three-terminal element having three electrodes, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Alternatively, the semiconductor element 1 may be a switching element such as an insulated gate bipolar transistor (IGBT) or a diode. In the description of the semiconductor device A1, the semiconductor element 1 is an n-channel, vertically structured MOSFET. The semiconductor element 1 has a rectangular shape when viewed in the thickness direction z. As shown in FIGS. 4 and 10 to 14 , the semiconductor element 1 has a semiconductor layer 10, a first electrode 11, a second electrode 12, and a third electrode 13.

[0015] The semiconductor layer 10 is a layer containing a semiconductor. The composition of the semiconductor contains, for example, silicon (Si), silicon carbide (SiC), etc. Furthermore, unlike the present embodiment, when the semiconductor element 1 is a switching element with a lateral structure, the semiconductor layer 10 contains, for example, gallium nitride (GaN).

[0016] 11 to 13, the first electrode 11 is disposed on the z2 side in the thickness direction z of the semiconductor layer 10. A current corresponding to the power before being converted by the semiconductor element 1 flows through the first electrode 11. In other words, the first electrode 11 corresponds to the drain electrode of the semiconductor element 1.

[0017] The second electrode 12 is disposed on the z1 side in the thickness direction z of the semiconductor layer 10. A current corresponding to the power converted by the semiconductor element 1 flows through the second electrode 12. In other words, the second electrode 12 corresponds to the source electrode of the semiconductor element 1.

[0018] The third electrode 13 is disposed on the z1 side in the thickness direction z of the semiconductor layer 10. A gate voltage for driving the semiconductor element 1 is applied to the third electrode 13. That is, the third electrode 13 corresponds to the gate electrode of the semiconductor element 1. When viewed in the thickness direction z, the area of ​​the third electrode 13 is smaller than the area of ​​the second electrode 12.

[0019] As shown in FIG. 14 , the first electrode 11 includes a first intermediate metal layer 111 and a second metal layer 112 .

[0020] The first intermediate metal layer 111 is interposed between the semiconductor layer 10 and the second metal layer 112 and is in contact with the semiconductor layer 10. The first intermediate metal layer 111 includes, for example, Ti (titanium), Ni (nickel), or the like. The first intermediate metal layer 111 may be a single layer or may be configured with multiple layers stacked together. The thickness of the first intermediate metal layer 111 (dimension in the thickness direction z) is, for example, 0.05 μm or more and 2.0 μm or less. The first intermediate metal layer 111 is a layer for preventing the semiconductor layer 10 from being damaged when the second metal layer 112 is formed.

[0021] The second metal layer 112 is in contact with the first intermediate metal layer 111. The second metal layer 112 contains, for example, Ag (silver) or Cu (copper). In the following description, a case where the second metal layer 112 is primarily composed of Ag (silver) will be described as an example. Specific examples of the second metal layer 112 primarily composed of Ag (silver) include an Ag (silver) plated layer and an Ag (silver) layer formed by a film formation technique such as sputtering. The thickness of the second metal layer 112 is, for example, 0.50 μm or more and 5.0 μm or less. In the illustrated example, the second metal layer 112 forms a surface layer of the first electrode 11.

[0022] The first lead 2, the second lead 3, and the third lead 4 are formed, for example, by punching or bending a metal plate (lead frame). The first lead 2, the second lead 3, and the third lead 4 contain, for example, Cu (copper) or Ni (nickel). In this embodiment, the constituent material of each of the first lead 2, the second lead 3, and the third lead 4 contains Fe (iron) and Ni (nickel), and is, for example, a 42 alloy.

[0023] The first lead 2 includes a portion disposed on the z1 side in the thickness direction z with respect to the semiconductor element 1. The first lead 2 includes a first pad portion 21 and a first terminal portion 22, as shown in FIGS.

[0024] The first pad portion 21 is a portion on which the semiconductor element 1 is mounted. The first pad portion 21 has a first main surface 201 and a second main surface 202. The first main surface 201 faces the z1 side in the thickness direction z. The second main surface 202 faces the z2 side in the thickness direction z.

[0025] As shown in Figures 4 and 10 to 14, the semiconductor element 1 is bonded to the first main surface 201 of the first pad portion 21 via a bonding layer 7. In this embodiment, the bonding layer 7 is made of a conductive material. The first electrode 11 of the semiconductor element 1 faces the first main surface 201. The first electrode 11 and the first main surface 201 are electrically bonded via the bonding layer 7. The semiconductor element 1 is mounted on the first main surface 201 of the first pad portion 21 by die bonding.

[0026] 14 , in this embodiment, the first pad portion 21 (first lead 2) has a base material 20A and a first plating layer 20B. The base material 20A contains Fe (iron) and Ni (nickel), and is, for example, a 42 alloy. The first plating layer 20B covers a portion of the base material 20A. The first plating layer 20B covers at least the portion of the first pad portion 21 on which the semiconductor element 1 is mounted. The constituent material of the first plating layer 20B includes Cu (copper). In this embodiment, the surface of the first plating layer 20B facing the z1 side in the thickness direction z constitutes at least a portion of the first main surface 201.

[0027] 14 , the bonding layer 7 includes a first intermetallic compound layer 71, a first metal layer 72, and a second intermetallic compound layer 73. The first intermetallic compound layer 71 is in contact with the first pad portion 21 (first lead 2). More specifically, the first intermetallic compound layer 71 is in contact with the first plating layer 20B of the first pad portion 21. The first plating layer 20B in contact with the first intermetallic compound layer 71 in the first pad portion 21 contains Cu (copper) as described above.

[0028] The first metal layer 72 is interposed between the first intermetallic compound layer 71 and the semiconductor layer 10, and is in contact with the first intermetallic compound layer 71. The first metal layer 72 contains Sn (tin).

[0029] The second intermetallic compound layer 73 is interposed between the first intermetallic compound layer 71 and the semiconductor layer 10. In the illustrated example, the second intermetallic compound layer 73 is interposed between the first metal layer 72 and the second metal layer 112 and is in contact with the first metal layer 72 and the second metal layer 112.

[0030] The first intermetallic compound layer 71 contains Sn (tin) and Cu (copper). The first intermetallic compound layer 71 is formed by combining Sn (tin) constituting the first metal layer 72 with Cu (copper) constituting the first plating layer 20B. The thickness t1 of the first intermetallic compound layer 71 is greater than the thickness t2 of the first metal layer 72. The thickness t1 of the first intermetallic compound layer 71 is, for example, 0.50 μm or more and 5.0 μm or less. The thickness t2 of the first metal layer 72 is, for example, 0 μm or more and 3.0 μm or less. Note that, although the attached drawings show flat boundaries between the first intermetallic compound layer 71 and other adjacent layers on both sides in the thickness direction z, these boundaries may include irregularities.

[0031] The second intermetallic compound layer 73 contains Sn (tin) and Ag (silver). The second intermetallic compound layer 73 is formed by combining Sn (tin) constituting the first metal layer 72 with Ag (silver) constituting the second metal layer 112. The thickness of the second intermetallic compound layer 73 is, for example, 0.05 μm or more and 3.0 μm or less. Note that in the attached drawings, the boundary surfaces between the second intermetallic compound layer 73 and other adjacent layers on both sides in the thickness direction z are depicted as flat, but the boundary surfaces may include uneven shapes.

[0032] The first terminal 22 is connected to the y1 side of the first pad 21 in the second direction y. The first terminal 22 extends in the second direction y when viewed in the thickness direction z. As shown in FIGS. 2 , 4 to 6 , 8 to 10 , and 13 , the first terminal 22 is exposed from the sealing resin 8 and has a portion that protrudes from the sealing resin 8 toward the y1 side in the second direction y, a portion that is folded back toward the z1 side in the thickness direction z, and a portion that is located on the z1 side in the thickness direction z. The first terminal 22 is used as a terminal when mounting the semiconductor device A1. The first terminal 22 is electrically connected to the first electrode 11 of the semiconductor element 1. The first terminal 22 is a drain terminal of the semiconductor device A1.

[0033] A plating layer made of an alloy containing Sn (tin) as a main component may be formed on the portion (first terminal portion 22) of the first lead 2 that is exposed from the sealing resin 8. In the illustrated example, a plating layer 203 is formed on the first terminal portion 22.

[0034] The second lead 3 is disposed on the x1 side in the first direction x with respect to the first lead 2. The second lead 3 includes a second pad portion 31 and a second terminal portion 32, as shown in FIGS.

[0035] The second pad 31 is located on the x1 side in the first direction x with respect to the first pad 21. Although detailed illustration is omitted, a plating layer is formed on the surface of the second pad 31 facing the z1 side in the thickness direction z. Like the first pad 21, the second pad 31 has a base material made of 42 alloy and a plating layer covering the surface of the base material on the z1 side in the thickness direction z. The constituent material of the plating layer includes Cu (copper). A first bonding wire 5 is connected to the surface of the second pad 31 facing the z1 side in the thickness direction z.

[0036] The second terminal portion 32 is connected to the y2 side of the second pad portion 31 in the second direction y. The second terminal portion 32 extends in the second direction y when viewed in the thickness direction z. As shown in FIGS. 1 and 3 to 10 , the second terminal portion 32 is exposed from the sealing resin 8 and has a portion that protrudes from the sealing resin 8 to the y2 side in the second direction y, a portion that is folded back to the z1 side in the thickness direction z, and a portion that is located on the z1 side in the thickness direction z. The second terminal portion 32 is used as a terminal when mounting the semiconductor device A1.

[0037] A plating layer made of an alloy containing Sn (tin) as a main component may be formed on a portion (second terminal 32) of the second lead 3 that is exposed from the sealing resin 8. Although detailed illustration is omitted, a plating layer is formed on the second terminal 32 in the same manner as the first terminal 22 described above.

[0038] The third lead 4 is disposed on the x2 side in the first direction x with respect to the first lead 2. As shown in FIGS. 1 to 7 and 9 to 13, the third lead 4 includes a third pad portion 41 and a third terminal portion 42.

[0039] The third pad 41 is located on the x2 side in the first direction x with respect to the first pad 21. Although detailed illustration is omitted, a plating layer is formed on the surface of the third pad 41 facing the z1 side in the thickness direction z. Like the first pad 21, the third pad 41 has a base material made of 42 alloy and a plating layer covering the surface of the base material on the z1 side in the thickness direction z. The constituent material of the plating layer includes Cu (copper). A second bonding wire 6 is connected to the surface of the third pad 41 facing the z1 side in the thickness direction z.

[0040] The third terminal 42 is connected to the y2 side of the third pad 41 in the second direction y. The third terminal 42 extends in the second direction y when viewed in the thickness direction z. As shown in FIGS. 1 , 3 to 7 , 9 , 10 , and 13 , the third terminal 42 is exposed from the sealing resin 8 and has a portion that protrudes from the sealing resin 8 toward the y2 side in the second direction y, a portion that is folded back toward the z1 side in the thickness direction z, and a portion that is located on the z1 side in the thickness direction z. When viewed in the first direction x, the third terminal 42 has a shape and size that generally overlaps with the second terminal 32. The third terminal 42 is used as a terminal when mounting the semiconductor device A1.

[0041] A plating layer made of an alloy containing Sn (tin) as a main component may be formed on a portion (third terminal 42) of the third lead 4 that is exposed from the sealing resin 8. Although detailed illustration is omitted, a plating layer is formed on the third terminal 42 in the same manner as the first terminal 22 described above.

[0042] The first bonding wire 5 is bonded to the second electrode 12 of the semiconductor element 1 and the second pad portion 31 of the second lead 3. The constituent material of the first bonding wire 5 is not limited in any way and includes metals such as Al (aluminum), Cu (copper), and Au (gold). The number of first bonding wires 5 is also not limited in any way and multiple first bonding wires 5 may be provided. In the illustrated example, the first bonding wire 5 includes Au (gold). The second terminal portion 32 of the second lead 3 is electrically connected to the second electrode 12 of the semiconductor element 1 via the first bonding wire 5. The second terminal portion 32 is a source terminal of the semiconductor device A1.

[0043] The second bonding wire 6 is bonded to the third electrode 13 of the semiconductor element 1 and the third pad portion 41 of the third lead 4. The constituent material of the first bonding wire 5 is not limited in any way and includes metals such as Al (aluminum), Cu (copper), and Au (gold). In the illustrated example, the first bonding wire 5 includes Au (gold). The third terminal portion 42 of the third lead 4 is electrically connected to the third electrode 13 of the semiconductor element 1 via the second bonding wire 6. The third terminal portion 42 is a gate terminal of the semiconductor device A1.

[0044] As shown in FIGS. 1 to 15 , the sealing resin 8 covers the semiconductor element 1, the first bonding wire 5, the second bonding wire 6, and a portion of each of the first lead 2, the second lead 3, and the third lead 4. More specifically, the sealing resin 8 covers the first pad portion 21, the second pad portion 31, and the third pad portion 41 of the first lead 2, the second lead 3, and the third lead 4. The sealing resin 8 has electrical insulation properties. The sealing resin 8 is made of a material containing, for example, black epoxy resin. The shape of the sealing resin 8 is not limited in any way. As shown in FIGS. 1 to 13 , the sealing resin 8 of this embodiment has a first resin surface 81, a second resin surface 82, a third resin surface 83, a fourth resin surface 84, a fifth resin surface 85, and a sixth resin surface 86.

[0045] The first resin surface 81 is a surface facing the z1 side in the thickness direction z. The second resin surface 82 is a surface facing the z2 side in the thickness direction z. In the illustrated example, the first resin surface 81 and the second resin surface 82 are flat surfaces, but are not limited to this and may be curved or bent surfaces, for example.

[0046] The third resin surface 83 is a surface facing the x1 side in the first direction x. The fourth resin surface 84 is a surface facing the x2 side in the first direction x. In the illustrated example, the third resin surface 83 and the fourth resin surface 84 are slightly curved surfaces, but are not limited to this and may be, for example, curved surfaces or flat surfaces.

[0047] The fifth resin surface 85 is a surface facing the y1 side in the second direction y. The sixth resin surface 86 is a surface facing the y2 side in the second direction y. In the illustrated example, the fifth resin surface 85 and the sixth resin surface 86 are slightly curved surfaces, but this is not limited thereto and may be, for example, a curved surface or a flat surface. In this embodiment, the first terminal 22 protrudes from the fifth resin surface 85, and the second terminal 32 and the third terminal 42 protrude from the sixth resin surface 86.

[0048] Next, an example of a method for forming the bonding layer 7 will be described below with reference to Fig. 15. Fig. 15 is a partially enlarged view showing one step in the manufacture of the semiconductor device A1. Fig. 15 shows a cross section similar to that of Fig. 14.

[0049] FIG. 15 illustrates a state before the semiconductor element 1 is mounted on the first pad portion 21 by the die bonding process. A bonding material portion 70 is formed on the z1 side of the first electrode 11 of the semiconductor element 1 in the thickness direction z. The bonding material portion 70 contains Sn (tin). In the die bonding process of the semiconductor element 1, the bonding material portion 70 is pressed against the first plating layer 20B of the first pad portion 21 with a predetermined load at a predetermined temperature and in a predetermined gas atmosphere. The ambient temperature here is set to, for example, the melting point of Sn (tin) (approximately 232°C) or higher. In this die bonding process, Cu (copper), which is a constituent material of the first plating layer 20B, diffuses into the bonding material portion 70. This forms a first intermetallic compound layer 71. In addition, Ag (silver), which is a constituent material of the second metal layer 112, diffuses into the bonding material portion 70. This forms a second intermetallic compound layer 73. A first metal layer 72 containing Sn (tin) is formed between the first intermetallic compound layer 71 and the second intermetallic compound layer 73 .

[0050] Next, the operation of the semiconductor device A1 will be described.

[0051] According to this embodiment, the bonding layer 7 contains Sn (tin) and Cu (copper). Specifically, the bonding layer 7 includes a first intermetallic compound layer 71, and the first intermetallic compound layer 71 contains Sn (tin) and Cu (copper). With this configuration, it is possible to improve the bonding of the semiconductor element 1 to the first pad portion 21 (first lead 2) without forming Ag (silver) plating on the first pad portion 21. In the semiconductor device A1, since it is not necessary to form Ag (silver) plating, it is possible to suppress an increase in manufacturing costs.

[0052] The first intermetallic compound layer 71 is in contact with the first pad portion 21 (first lead 2). The first plating layer 20B, which is the portion of the first pad portion 21 (first lead 2) in contact with the first intermetallic compound layer 71, contains Cu (copper). With this configuration, the first intermetallic compound layer 71 can be easily formed.

[0053] 16 to 19 show other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals, and redundant explanations will be omitted. Furthermore, the configurations of the various parts in each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0054] Second Embodiment: Fig. 16 shows a semiconductor device according to a second embodiment of the present disclosure. Fig. 16 is a partially enlarged cross-sectional view showing a semiconductor device A2 of this embodiment, and shows a cross section similar to that of Fig. 14.

[0055] The semiconductor device A2 differs from the semiconductor device A1 in the configurations of the first electrode 11 and the bonding layer 7. Unlike the semiconductor device A1, the semiconductor device A2 differs from the semiconductor device A1 in that the first electrode 11 does not include the second metal layer 112. Furthermore, the bonding layer 7 does not include the second intermetallic compound layer 73. The first metal layer 72 is interposed between the first intermetallic compound layer 71 and the first intermediate metal layer 111 and is in contact with the first intermetallic compound layer 71 and the first intermediate metal layer 111.

[0056] An example of a method for forming the bonding layer 7 will be described with reference to Fig. 17. Fig. 17 is a partially enlarged view showing one step in the manufacture of the semiconductor device A2. Fig. 17 shows a cross section similar to that of Fig. 16.

[0057] FIG. 17 illustrates a state before the semiconductor element 1 is mounted on the first pad portion 21 by the die bonding process. A bonding material portion 70 is formed on the z1 side of the first electrode 11 of the semiconductor element 1 in the thickness direction z. The bonding material portion 70 contains Sn (tin). In the die bonding process of the semiconductor element 1, the bonding material portion 70 is pressed against the first plating layer 20B of the first pad portion 21 with a predetermined load at a predetermined temperature and in a predetermined gas atmosphere. The ambient temperature here is set to, for example, the melting point of Sn (tin) or higher (approximately 232°C). During the die bonding process, Cu (copper), a constituent material of the first plating layer 20B, diffuses into the bonding material portion 70. This forms a first intermetallic compound layer 71. A first metal layer 72 containing Sn (tin) is formed between the first intermetallic compound layer 71 and the first intermediate metal layer 111.

[0058] According to this embodiment, the bonding layer 7 contains Sn (tin) and Cu (copper). Specifically, the bonding layer 7 includes a first intermetallic compound layer 71, which contains Sn (tin) and Cu (copper). This configuration improves the bonding of the semiconductor element 1 to the first pad 21 (first lead 2) without forming Ag (silver) plating on the first pad 21. In the semiconductor device A2, the formation of Ag (silver) plating is not necessary, which prevents an increase in manufacturing costs.

[0059] The first intermetallic compound layer 71 is in contact with the first pad portion 21 (first lead 2). The first plating layer 20B, which is the portion of the first pad portion 21 (first lead 2) in contact with the first intermetallic compound layer 71, contains Cu (copper). With this configuration, the first intermetallic compound layer 71 can be easily formed.

[0060] 18 shows a semiconductor device according to a third embodiment of the present disclosure. Fig. 18 is a partially enlarged cross-sectional view showing a semiconductor device A3 of this embodiment, and shows a cross section similar to that of Fig. 14.

[0061] The semiconductor device A3 differs from the semiconductor device A1 in the configuration of the first pad portion 21. In the semiconductor device A1 of the above embodiment, the first pad portion 21 includes a base material 20A and a first plating layer 20B, but in this embodiment, the first pad portion 21 is made of a base material 20C. The base material 20C includes Cu (copper).

[0062] The first intermetallic compound layer 71 of the bonding layer 7 is in contact with the base material 20C of the first pad portion 21 (first lead 2). The base material 20C in contact with the first intermetallic compound layer 71 in the first pad portion 21 contains Cu (copper).

[0063] An example of a method for forming the bonding layer 7 will be described with reference to Fig. 19. Fig. 19 is a partially enlarged view showing one step in the manufacture of the semiconductor device A3. Fig. 19 shows a cross section similar to that of Fig. 18.

[0064] FIG. 19 illustrates a state before the semiconductor element 1 is mounted on the first pad 21 by the die bonding process. A bonding material portion 70 is formed on the z1 side of the first electrode 11 of the semiconductor element 1 in the thickness direction z. The bonding material portion 70 contains Sn (tin). In the die bonding process of the semiconductor element 1, the bonding material portion 70 is pressed against the first pad 21 (base material 20C) with a predetermined load at a predetermined temperature and in a predetermined gas atmosphere. The ambient temperature here is set to, for example, the melting point of Sn (tin) or higher (approximately 232°C). In this die bonding process, Cu (copper), which is a constituent material of the base material 20C, diffuses into the bonding material portion 70. This forms a first intermetallic compound layer 71. In addition, Ag (silver), which is a constituent material of the second metal layer 112, diffuses into the bonding material portion 70. This forms a second intermetallic compound layer 73. A first metal layer 72 containing Sn (tin) is formed between the first intermetallic compound layer 71 and the second intermetallic compound layer 73 .

[0065] According to this embodiment, the bonding layer 7 contains Sn (tin) and Cu (copper). Specifically, the bonding layer 7 includes a first intermetallic compound layer 71, which contains Sn (tin) and Cu (copper). This configuration improves the bonding of the semiconductor element 1 to the first pad 21 (first lead 2) without forming Ag (silver) plating on the first pad 21. In the semiconductor device A3, the formation of Ag (silver) plating is not necessary, which prevents an increase in manufacturing costs.

[0066] The first intermetallic compound layer 71 is in contact with the first pad portion 21 (first lead 2). The base material 20C, which is the portion of the first pad portion 21 (first lead 2) in contact with the first intermetallic compound layer 71, contains Cu (copper). With this configuration, the first intermetallic compound layer 71 can be easily formed.

[0067] The semiconductor device according to the present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways.

[0068] The present disclosure includes configurations related to the following appendices. Appendix 1. A semiconductor device comprising: a first lead; a semiconductor element mounted on one side of the first lead in a thickness direction and having a semiconductor layer; and a bonding layer interposed between the first lead and the semiconductor layer and bonding the first lead and the semiconductor element, wherein the bonding layer contains Sn and Cu. Appendix 2. The semiconductor device according to Appendix 1, wherein the bonding layer includes a first intermetallic compound layer containing Sn and Cu. Appendix 3. The semiconductor device according to Appendix 2, wherein the first intermetallic compound layer is in contact with the first lead, and a portion of the first lead in contact with the first intermetallic compound layer contains Cu. Appendix 4. The semiconductor device according to Appendix 2 or 3, wherein the bonding layer includes a second intermetallic compound layer interposed between the first intermetallic compound layer and the semiconductor layer. Appendix 5. The semiconductor device according to Appendix 4, wherein the second intermetallic compound layer contains Sn and Ag. Appendix 6. The semiconductor device according to any one of Appendixes 2 to 5, wherein the bonding layer includes a first metal layer interposed between the first intermetallic compound layer and the semiconductor layer and in contact with the first intermetallic compound layer, and the first metal layer contains Sn. Appendix 7. The semiconductor device according to Appendix 6, wherein the thickness of the first intermetallic compound layer is greater than the thickness of the first metal layer. Appendix 8. The semiconductor device according to any one of Appendixes 1 to 7, further including a first intermediate metal layer interposed between the bonding layer and the semiconductor layer and in contact with the semiconductor layer. Appendix 9. The semiconductor device according to Appendix 8, further including a second metal layer interposed between the bonding layer and the first intermediate metal layer and in contact with the first intermediate metal layer. Appendix 10. The semiconductor device according to Appendix 9, wherein the second metal layer contains Ag. Appendix 11. The semiconductor device according to any one of claims 2 to 7, wherein the first lead has a base material and a first plating layer formed on one side of the base material in the thickness direction and in contact with the first intermetallic compound layer, and the first plating layer contains Cu. 12. The semiconductor device according to claim 11, wherein the base material contains Fe and Ni.Appendix 13. The semiconductor device according to Appendix 9 or 10, wherein the semiconductor element has a first electrode arranged on the other side in the thickness direction of the semiconductor layer, the first lead includes a first pad portion on which the semiconductor element is mounted, and the first electrode is configured to include the second metal layer and the first intermediate metal layer. Appendix 14. The semiconductor device according to Appendix 13, further comprising: a second lead arranged spaced apart from the first lead; and a first bonding wire, wherein the second lead includes a second pad portion located on one side in a first direction perpendicular to the thickness direction with respect to the first pad portion, the semiconductor element has a second electrode arranged on one side in the thickness direction of the semiconductor layer, and the first bonding wire is conductively joined to the second electrode and the second pad portion. Appendix 15. The semiconductor device according to claim 14, further comprising: a third lead arranged at a distance from the first lead and the second lead; and a second bonding wire, wherein the third lead includes a third pad portion located on the other side of the first pad portion in the first direction, the semiconductor element has a third electrode arranged on one side of the semiconductor layer in the thickness direction, and the second bonding wire is conductively joined to the third electrode and the third pad portion. Appendix 16. The semiconductor device according to claim 15, further comprising a sealing resin covering the semiconductor element, the first pad portion, the second pad portion, the third pad portion, the first bonding wire, and the second bonding wire.

[0069] A1, A2, A3: semiconductor device 1: semiconductor element 10: semiconductor layer 11: first electrode 111: first intermediate metal layer 112: second metal layer 12: second electrode 13: third electrode 2: first lead 20A: substrate 20B: first plating layer 20C: base material 201: first main surface 202: second main surface 203: plating layer 21: first pad portion 22: first terminal portion 3: second lead 31: second pad portion 32: second terminal portion 4: third lead 41: third pad portion 42: third terminal portion 5: first bonding wire 6: second bonding wire 7: bonding layer 70: bonding material portion 71: first intermetallic compound layer 72: first metal layer 73: second intermetallic compound layer 8: sealing resin 81: first resin surface 82: Second resin surface 83: Third resin surface 84: Fourth resin surface 85: Fifth resin surface t1, t2: Thickness

Claims

1. First lead, A semiconductor element having a semiconductor layer is mounted on one side in the thickness direction of the first lead, The device comprises a bonding layer interposed between the first lead and the semiconductor layer, which bonds the first lead and the semiconductor element, The bonding layer comprises Sn and Cu, and is a semiconductor device.

2. The semiconductor device according to claim 1, wherein the bonding layer includes a first intermetallic compound layer containing Sn and Cu.

3. The first intermetallic compound layer is in contact with the first lead, The semiconductor device according to claim 2, wherein the portion of the first lead in contact with the first intermetallic compound layer contains Cu.

4. The semiconductor device according to claim 2 or 3, wherein the bonding layer includes a second intermetallic compound layer interposed between the first intermetallic compound layer and the semiconductor layer.

5. The semiconductor device according to claim 4, wherein the second intermetallic compound layer comprises Sn and Ag.

6. The bonding layer includes a first metal layer interposed between the first intermetallic compound layer and the semiconductor layer, and in contact with the first intermetallic compound layer. The semiconductor device according to claim 2 or 3, wherein the first metal layer comprises Sn.

7. The semiconductor device according to claim 6, wherein the thickness of the first intermetallic compound layer is greater than the thickness of the first metal layer.

8. The semiconductor device according to claim 1, further comprising a first intermediate metal layer interposed between the bonding layer and the semiconductor layer and in contact with the semiconductor layer.

9. The semiconductor device according to claim 8, further comprising a second metal layer interposed between the bonding layer and the first intermediate metal layer and in contact with the first intermediate metal layer.

10. The semiconductor device according to claim 9, wherein the second metal layer contains Ag.

11. The first lead comprises a substrate and a first plating layer formed on one side of the substrate in the thickness direction and in contact with the first intermetallic compound layer. The semiconductor device according to claim 2 or 3, wherein the first plating layer contains Cu.

12. The semiconductor device according to claim 11, wherein the substrate comprises Fe and Ni.

13. The semiconductor element has a first electrode disposed on the other side of the semiconductor layer in the thickness direction, The first lead includes a first pad portion on which the semiconductor element is mounted, The semiconductor device according to claim 9 or 10, wherein the first electrode is configured to include the second metal layer and the first intermediate metal layer.

14. The device further comprises a second lead positioned at a distance from the first lead, and a first bonding wire. The second lead includes a second pad portion located on one side of the first pad portion in a first direction perpendicular to the thickness direction, The semiconductor element has a second electrode disposed on one side of the semiconductor layer in the thickness direction, The semiconductor device according to claim 13, wherein the first bonding wire is electrically bonded to the second electrode and the second pad portion.

15. The device further comprises a third lead positioned at a distance from the first and second leads, and a second bonding wire. The third lead includes a third pad portion located on the other side in the first direction relative to the first pad portion, The semiconductor element has a third electrode disposed on one side of the semiconductor layer in the thickness direction, The semiconductor device according to claim 14, wherein the second bonding wire is electrically bonded to the third electrode and the third pad portion.

16. The semiconductor device according to claim 15, further comprising the semiconductor element, the first pad portion, the second pad portion, the third pad portion, the first bonding wire, and a sealing resin covering the second bonding wire.