N-type diamond mosfet and method for manufacturing same

Abstract

Provided is an n-type MOSFET which uses a single crystal diamond semiconductor that has excellent electric characteristics. One embodiment of the present invention provides an n-type MOSFET 101 that comprises: a substrate 11 which has a single crystal diamond layer on at least a part of the surface thereof; a first semiconductor layer 12 which is in contact with the substrate 11 and is composed of an n- type diamond single crystal; a gate electrode part in which an insulating film 14 and a gate electrode 15 are sequentially superposed on the first semiconductor layer 12; a source electrode part in which a second semiconductor layer 13, which is composed of an n+ type diamond, and a source electrode 16 are sequentially superposed on the first semiconductor layer 12; and a drain electrode part in which a drain electrode 17 is formed on the second semiconductor layer 13. The first semiconductor layer 13 contains an n-type impurity at a concentration of 2 × 1018 cm-3 or less, with the hydrogen content being equal to or less than the concentration of the same order as that of the n-type impurity. The surface of a region of the gate electrode part in the first semiconductor layer 12 is terminated with oxygen. The second semiconductor layer 13 contains an n-type impurity at a concentration of 2 × 1022 cm-3 or less, with the hydrogen content being 2 × 1022 cm-3 or less, and the second semiconductor layer 13 is in electrical contact with the first semiconductor layer 12.

Description

N-type diamond MOSFET and method of manufacturing the same REFERENCE TO RELATED APPLICATIONS

[0001] This application benefits from the priority of an earlier Japanese application, Patent Application No. 2023-115578 (filing date: July 14, 2023), the entire disclosure of which is incorporated herein by reference.

[0002] The present invention relates to an n-type diamond MOSFET and a method for manufacturing the same.

[0003] Single-crystal semiconductor diamond has a wide band gap energy (5.47 eV), a low dielectric constant (5.7), and a high breakdown field strength (10 MV cm －１ ), high carrier saturation velocity (1.5-2.7×10 for electrons and holes, respectively) ７ cm・s －１ and 0.85 to 1.2 × 10 ７ cm・s －１ ), high thermal conductivity (22 W cm －１ ・K －１ ) and high carrier mobility (4500 cm for electrons and holes, respectively) ２ ・V －１ ・s －１ and 3800 cm ２ ・V －１ ・s －１ (The above properties are measured at room temperature.) Therefore, electronic devices using single-crystal diamond as a semiconductor are expected to exhibit high-power operation, high-speed and high-frequency operation, high voltage resistance, and high thermal limit.

[0004] In particular, MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) semiconductor devices that use single-crystal diamond as a semiconductor are highly anticipated as core elements in constructing high-performance inverters and high-power high-frequency amplifiers, as well as elements that can withstand harsh environments such as high temperatures and radiation.

[0005] Against this background, the development of MOSFETs using single-crystal diamond semiconductors has been progressing, but the diamond semiconductor MOSFETs reported so far are limited to p-type MOSFETs that use vacancies (holes) as carriers, as disclosed in Non-Patent Documents 1 and 2.

[0006] As n-type MOSFETs that use electrons as carriers, there have been reports of those that use microcrystalline diamond containing carbon or the like as the semiconductor layer (for example, Patent Documents 1 and 2), but there have been no reports of n-type MOSFETs that use single-crystal diamond with the above-mentioned remarkably excellent physical properties and that exhibit excellent electrical characteristics.

[0007] CMOS (Complementary Metal-Oxide Semiconductor) circuits are used in a wide variety of devices due to their high noise resistance and low power consumption characteristics. Low power consumption is a market and technological trend, and demand is expected to increase further in the future. For this reason, there are high expectations for the application of single-crystal diamond semiconductor devices to CMOS.

[0008] CMOS requires n-type MOSFETs and p-type MOSFETs as essential components, and from this perspective, n-type MOSFETs using single crystal diamond as the semiconductor layer are desired.

[0009] JP 2007-141974 A JP 2011-181763 A

[0010] K. Kudara, et al. , High Output Power Density of 2DHG Diamond MOSFETs With Thick ALD-Al2O3, IEEE Transactions on Electron Devices, vol. 68, p. p. 3942-3949 (2021) T. T. Pham et al. , Dee-Depletion Mode Boron-Doped Monocrystalline Diamond Metal Oxide Semiconductor Field Effect Transistor, IEEE Electron Letters, vol. 38, p. p. 1571-1574 (2017)

[0011] The problem that the present invention is to solve is to provide an n-type MOSFET (also called an n-type diamond MOSFET) that uses single-crystal diamond as a semiconductor layer, and a method for manufacturing the same.

[0012] The present invention solves the above problems by providing the following configurations: (Configuration 1) A substrate having a single crystal diamond layer on at least a part of its surface; － a first semiconductor layer made of a single crystal diamond; an insulating film stacked on a first region of the first semiconductor layer and functioning as a gate insulating film; and a gate electrode portion having a gate electrode stacked on the insulating film; and a second region stacked on a second region different from the first region of the first semiconductor layer and having an n-type diamond single crystal. ＋ a source electrode section having a second semiconductor layer made of diamond and a source electrode laminated on the second semiconductor layer; and a drain electrode section having the second semiconductor layer laminated on a third region different from the first region and the second region in the first semiconductor layer and a drain electrode laminated on the second semiconductor layer, wherein the first semiconductor layer has a concentration of 1×10 in a channel formation depth region of a MOSFET. １５ cm －３ 2x10 or more １８ cm －３ The hydrogen content is 1×10１０ cm －３ the n-type impurity concentration is 1×10 or more and is equal to or less than the concentration of the n-type impurity, at least the surface of the first region of the first semiconductor layer is terminated with oxygen, and the second semiconductor layer has a concentration of 1×10 or more and is equal to or less than the concentration of the n-type impurity, １９ cm －３ 2x10 or more ２２ cm －３ The hydrogen content is 1×10 １０ cm －３ 2x10 or more ２２ cm －３ and the second semiconductor layer is electrically connected to the first semiconductor layer. １０ cm －３ 5x10 or more １７ cm －３ An n-type diamond MOSFET according to configuration 1, which is as follows: (Configuration 3) An n-type diamond MOSFET according to configuration 1 or 2, wherein the n-type impurity comprises one or more selected from the group consisting of phosphorus (P), sulfur (S), arsenic (As), and boron-oxygen complexes (B—O). (Configuration 4) An n-type diamond MOSFET according to configuration 3, wherein the n-type impurity comprises phosphorus (P). (Configuration 5) An n-type diamond MOSFET according to configuration 3, wherein the insulating film comprises alumina (Al ２ O ３ ), hafnium dioxide (HfO ２ ), hafnium silicon dioxide (HfSiO ２ ), aluminum nitride (AlN), boron nitride (BN), silicon dioxide (SiO ２ ), calcium difluoride (CaF ２ ), silicon oxynitride (SiON), silicon nitride (SiN ｘ , x is more than 0 and not more than 1.34), tantalum pentoxide (Ta ２ O ５ ) and magnesium difluoride (MgF ２(Structure 6) An n-type diamond MOSFET according to any one of structures 1 to 4, wherein the substrate is one or more selected from the group consisting of a single crystal diamond substrate. (Structure 7) An n-type diamond MOSFET according to structure 6, wherein the single crystal diamond substrate is a nitrogen-containing Ib-type single crystal diamond substrate or a IIa-type single crystal diamond substrate. (Structure 8) An n-type diamond MOSFET according to structure 7 or 8, wherein the plane orientation of the single crystal diamond substrate is one selected from the group consisting of (111), (100) and (110). (Structure 9) The n-type diamond MOSFET according to any one of structures 1 to 8, wherein the material of the gate electrode, the source electrode and the drain electrode is selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), iridium (Ir), rhenium (Re), palladium (Pd), rhodium (Rd), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), magnesium (Mg), tungsten (W), copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), iron (Fe), zinc (Zn), cadmium (Cd), mercury (Hg), gallium (Ga), indium (In), boron (B), carbon (C), silicon (Si) and germanium (Ge). (Configuration 10) The n-type diamond MOSFET according to configuration 9, wherein the material of the source electrode and the drain electrode in contact with the second semiconductor layer includes one selected from the group consisting of titanium (Ti), chromium (Cr), molybdenum (Mo), and tungsten (W). (Configuration 11) An n-type diamond MOSFET comprising: preparing a substrate having a single-crystal diamond layer formed on at least a part of its surface; － forming a first semiconductor layer made of a single-crystal diamond; forming an insulating film on a first region of the first semiconductor layer; forming a gate electrode on the insulating film; and forming n-type ... ＋forming a second semiconductor layer made of diamond of type 10; forming a source electrode on the second semiconductor layer in the second region; and forming a drain electrode on the second semiconductor layer in the third region; wherein the first semiconductor layer has a concentration of 1×10 in a channel formation depth region of a MOSFET. １５ cm －３ 2 x 10 or more １８ cm －３ The hydrogen content is 1×10 １０ cm －３ the n-type impurity concentration is 1×10 or more and is equal to or less than the concentration of the n-type impurity, at least the surface of the first region of the first semiconductor layer is terminated with oxygen, and the second semiconductor layer has a concentration of 1×10 or more and is equal to or less than the concentration of the n-type impurity, １９ cm －３ 2 x 10 or more ２２ cm －３ The hydrogen content is 1×10 １０ cm －３ 2 x 10 or more ２２ cm －３ and wherein the second semiconductor layer is in electrical contact with the first semiconductor layer. (Configuration 12) A method for manufacturing an n-type diamond MOSFET includes the steps of: preparing a substrate having a single-crystal diamond layer formed on at least a part of its surface; － forming a first semiconductor layer made of a single crystal of n-type diamond; and ＋forming a second semiconductor layer made of diamond; forming a first conductive film on the second semiconductor layer; performing lithography and etching on the first conductive film to form a source electrode and a drain electrode; etching the second semiconductor layer using oxygen plasma at least in a region where a gate electrode or a channel is to be formed until the first semiconductor layer is exposed; forming an insulating film on a region including at least the region on the first semiconductor layer; and forming a gate electrode made of the second conductive film on the insulating film, wherein the first semiconductor layer has a concentration of 1×10 in a channel formation depth region of a MOSFET. １５ cm －３ 2 x 10 or more １８ cm －３ The hydrogen content is 1×10 １０ cm －３ The second semiconductor layer has a concentration of 1×10 or more and the concentration is equal to or less than the same order as the n-type impurity. １９ cm －３ 2 x 10 or more ２２ cm －３ The hydrogen content is 1×10 １０ cm －３ 2 x 10 or more ２２ cm －３ (Configuration 13) A method for manufacturing an n-type diamond MOSFET, wherein the second conductive film is formed at an atmospheric pressure of 1×10 －１２ Pa or more 2×10 －６ The method for manufacturing an n-type diamond MOSFET according to structure 12, wherein the n-type diamond MOSFET is formed in a vacuum environment of 10 Pa or less. (Structure 14) The method for manufacturing an n-type diamond MOSFET according to structure 12 or 13, wherein, before forming the first conductive film, the surface of the second semiconductor layer is treated with an acidic solution at 50°C or higher and 400°C or lower, to terminate the second semiconductor layer with oxygen. (Structure 15) The method for manufacturing an n-type diamond MOSFET according to structure 14, wherein the acidic solution is a mixed acid composed of sulfuric acid and nitric acid, with a volume ratio of nitric acid to sulfuric acid being 3. (Structure 16) The hydrogen content of the first semiconductor layer is 1 x 10 １０ cm－３ 5x10 or more １７ cm －３ A method for manufacturing an n-type diamond MOSFET according to any one of structures 11 to 15, which is as follows: (Structure 17) A method for manufacturing an n-type diamond MOSFET according to any one of structures 11 to 16, wherein the first semiconductor layer and the second semiconductor layer are formed by microwave plasma chemical vapor deposition (MPCVD). (Structure 18) A method for manufacturing an n-type diamond MOSFET according to any one of structures 11 to 17, wherein the insulating film is formed by atomic layer deposition (ALD).

[0013] According to the present invention, there is provided an n-type MOSFET using single crystal diamond as a semiconductor layer and a method for manufacturing the same.

[0014] FIG. 1 is a cross-sectional view showing the structure of a key portion of an n-type MOSFET according to an embodiment. FIGS. 2(a) to 2(d) are cross-sectional views showing the manufacturing process of an n-type MOSFET according to an embodiment. FIGS. 3(a) to 3(c) are cross-sectional views showing the manufacturing process of an n-type MOSFET according to an embodiment. FIGS. 4(a) and 4(b) are cross-sectional views showing the manufacturing process of an n-type MOSFET according to an embodiment. FIGS. 5(a) and 5(b) are cross-sectional views showing the manufacturing process of an n-type MOSFET according to an embodiment. FIGS. 6(a) and 6(b) are cross-sectional views showing the manufacturing process of an n-type MOSFET according to an embodiment. FIGS. 7(a) and 7(b) are cross-sectional views showing the manufacturing process of an n-type MOSFET according to an embodiment. FIG. 8 is a manufacturing flow diagram showing a first manufacturing process of an n-type MOSFET according to an embodiment. FIG. 9 is a manufacturing flow diagram showing a second manufacturing process of an n-type MOSFET according to an embodiment. FIG. 10 is an impurity distribution diagram showing the impurity distribution in single-crystal diamond, which is the first semiconductor layer. Measurements were performed using SIMS. Figure 11 is a surface roughness measurement diagram showing the surface irregularities of the single-crystal diamond, which is the first semiconductor layer. Measurements were performed using an AFM. Figure 12 is an optical microscope image of the prototype device, photographed from above. Figures 13(a) to 13(d) are cross-sectional views of key parts showing the manufacturing process of the n-type MOSFET of Example 2. Figures 14(a) to 14(c) are cross-sectional views of key parts showing the manufacturing process of the n-type MOSFET of Example 2. Figures 15(a) and 15(b) are cross-sectional views of key parts showing the manufacturing process of the n-type MOSFET of Example 2. Figures 16(a) and 16(b) are cross-sectional views of key parts showing the manufacturing process of the n-type MOSFET of Example 2. Figures 17(a) and 17(b) are characteristic diagrams examining the relationship between drain voltage and drain current, using gate voltage as a parameter. Here, Figure 17(a) shows the results of measurements performed at room temperature, and Figure 17(b) shows the results of measurements performed in a 300°C environment. 18(a) and 18(b) are characteristic diagrams showing the relationship between the gate voltage applied and the drain current. Here, FIG. 18(a) shows the results of measurements taken at room temperature, and FIG. 18(b) shows the results of measurements taken at 300°C. FIGS. 19(a) and 19(b) are characteristic diagrams showing the relationship between the gate voltage applied and the transconductance.Here, Fig. 19(a) shows the results of measurements taken at room temperature, and Fig. 19(b) shows the results of measurements taken in a 300°C environment. Fig. 20 is a characteristic diagram examining the relationship between environmental temperature and gate threshold voltage. Fig. 21 is a characteristic diagram showing the relationship between gate applied voltage and field-effect mobility. Here, the temperature of the measurement environment is 300°C.

[0015] <Element Structure> The structure of an n-type MOSFET 101 of this embodiment using a single-crystal diamond semiconductor will be described with reference to FIG. 1, which is a cross-sectional view of a main part.

[0016] As shown in FIG. 1, the MOSFET 101 of the first embodiment includes a substrate 11 having a single-crystal diamond layer on at least a portion of the surface thereof, － a first semiconductor layer 12 made of n-type single crystal diamond; ＋ The transistor comprises a second semiconductor layer 13 made of single-crystal diamond, an insulating film 14 functioning as a gate insulating film, a gate electrode 15, a source electrode 16, and a drain electrode 17, and a gate (G) electrode portion having the gate electrode 15 is disposed between the second semiconductor layers 13, and the surface portion of the first semiconductor layer 12 between the second semiconductor layers 13 functions as a channel 31.

[0017] Therefore, the n-type MOSFET 101 of this embodiment has a substrate 11 having a single-crystal diamond layer on at least a part of its surface, and a semiconductor layer 12 that is in contact with the surface of the single-crystal diamond layer and is n － a first semiconductor layer (12) made of a single crystal diamond; an insulating film (14) laminated on a first region (R1) of the first semiconductor layer (12) and functioning as a gate insulating film; a gate electrode section having a gate electrode (15) laminated on the insulating film (14); and a second region (R2) laminated on a second region (R2) different from the first region (R1) of the first semiconductor layer (12) and having an n-type diamond single crystal. ＋The semiconductor device has a source electrode section having a second semiconductor layer 13 made of type diamond and a source electrode 16 laminated on the second semiconductor layer 13, and a drain electrode section having a second semiconductor layer 13 laminated on a third region R3 different from the first region R1 and the second region R2 in the first semiconductor layer 12 and a drain electrode section having a drain electrode 17 laminated on the second semiconductor layer 13 laminated on the third region R3. The gate electrode 15 is disposed on the first semiconductor layer 12 via an insulating layer 14.

[0018] The MOSFET 101 of the first embodiment further has a structure in which the impurity concentrations and hydrogen concentrations of the first semiconductor layer 12 and the second semiconductor layer 13 satisfy the following conditions, and the surface (channel 31) of the first region R1, which is the region in the first semiconductor layer 12 where at least the gate electrode portion is formed, is terminated with oxygen. － In the first semiconductor layer 12 made of a single-crystal diamond, each carbon atom in the diamond is covalently bonded to four surrounding atoms, but on the surface of the diamond, there are excess bonds of each carbon atom. These dangling bonds are unstable and behave as surface states. In this specification, the state in which the dangling bonds of the carbon atoms present on the surface of at least the first region of the first semiconductor layer are bonded to oxygen is called oxygen termination. Whether the surface of the gate electrode region is terminated with oxygen can be confirmed by X-ray photoelectron spectroscopy.

[0019] Based on extensive experiments, the inventors have found that an n-type diamond MOSFET exhibiting good electrical characteristics can be provided when the impurity concentrations and hydrogen concentrations of the first semiconductor layer 12 and the second semiconductor layer 13 have the following relationship, and that if the surface layer of the channel 31 is terminated with hydrogen, holes will move therethrough, inhibiting the operation of the n-type MOSFET, but that such inhibition can be avoided because the surface layer of the channel 31 is terminated with oxygen.

[0020] In the channel formation depth region of the MOSFET, the n-type impurity concentration of the first semiconductor layer 12 is 1×10 １５ cm －３ 2x10 or more １８ cm －３The hydrogen content of the first semiconductor layer 12 is 1×10 １０ cm －３ The concentration of the n-type impurity in the first semiconductor layer 12 is equal to or greater than 1×10. Here, the "channel formation depth region" refers to the region from the surface of the first semiconductor layer to the depth where the channel is formed, and may refer to, for example, a region including the surface layer of the first semiconductor layer. Specifically, the channel formation depth region may be a region from the surface of the first semiconductor layer to a position of 0.1 μm to 5 μm in the depth direction of the first semiconductor layer, which is doped with n-type impurity. Furthermore, "the same order of magnitude" means that the hydrogen content of the first semiconductor layer may be greater or smaller than the n-type impurity concentration of the first semiconductor layer, as long as the hydrogen content of the first semiconductor layer is of the same order of magnitude as the n-type impurity concentration of the first semiconductor layer. Furthermore, in the channel formation depth region of the MOSFET, the n-type impurity concentration of the first semiconductor layer 12 is equal to or greater than 1×10. １５ cm －３ 5x10 or more １８ cm －３ or less or 1 x 10 １６ cm －３ 2 x 10 or more １８ cm －３ The hydrogen content of the first semiconductor layer 12 may be 1×10 or less. １０ cm －３ 5x10 or more １７ cm －３ The n-type impurity concentration and hydrogen content of the first semiconductor layer 12 are each measured by a secondary ion mass spectrometry (SIMS) device (IMS-7f, manufactured by CAMECA).

[0021] The n-type impurity concentration of the second semiconductor layer 13 is 1×10 １９ cm －３ 2 x 10 or more ２２ cm －３ The hydrogen content of the second semiconductor layer 13 is 1×10 or less. １０ cm －３ 2 x 10 or more ２２ cm －３ The n-type impurity concentration and hydrogen content of the second semiconductor layer 13 are measured by the same method as that for the first semiconductor layer 12.

[0022] As shown in FIG. 1, the second semiconductor layer 13 is in contact with the first semiconductor layer 12, and due to the relationship of the impurity concentrations described above, the second semiconductor layer 13 is in ohmic electrical contact with the first semiconductor layer 12, which helps to obtain good MOSFET characteristics.

[0023] Here, examples of the n-type impurity include one or more selected from the group consisting of phosphorus (P), sulfur (S), arsenic (As), and boron-oxygen complexes (B—O). In particular, phosphorus is preferably used because it is likely to bring out good electrical characteristics and is non-toxic and easy to handle.

[0024] The film thickness of the first semiconductor layer 12 can be 5 nm or more and 5 μm or less. By making the film thickness of the first semiconductor layer 12 5 nm or more, preferably 50 nm or more, a channel with few defects can be ensured, and by making the film thickness 5 μm or less, preferably 1 μm or less, productivity can be ensured and stress generation, which is the basis for distorting the element, can be suppressed. The film thickness of the first semiconductor layer 12 is preferably, for example, 50 nm or more and 1 μm or less.

[0025] The film thickness of the second semiconductor layer 13 can be 1 nm or more and 1000 nm or less. By making the film thickness of the second semiconductor layer 13 1 nm or more, preferably 10 nm or more, ohmic contact can be achieved with both the source and drain, and contact resistance can be sufficiently reduced. By making the film thickness of the second semiconductor layer 13 1000 nm or less, preferably 100 nm or less, contact resistance can be suppressed and productivity can be improved. The film thickness of the second semiconductor layer 13 is preferably, for example, 10 nm or more and 100 nm or less.

[0026] The substrate 11 is not particularly limited as long as it has a single crystal diamond layer on at least a portion of its surface, and examples thereof include single crystal diamond substrates, substrates on which a single crystal diamond layer is epitaxially formed, and substrates in which a single crystal diamond film cut by cleavage or the like is bonded to a rigid base, such as metal substrates such as Si wafers and aluminum substrates, and glass substrates such as synthetic quartz substrates.

[0027] As the single crystal diamond layer, in addition to non-doped single crystal diamond, doped single crystal diamond that is added with nitrogen, boron, phosphorus, etc. can also be used.As the type of single crystal diamond, for example, Ib type and IIa type can be mentioned.In addition, as the plane orientation of the single crystal diamond layer, other than (100) plane, (111) plane, (110) plane, etc. can be used.

[0028] When the substrate 11 is a substrate made of single crystal diamond (single crystal diamond substrate), the single crystal diamond substrate may be a nitrogen-containing type Ib single crystal diamond substrate or a type IIa single crystal diamond substrate, and the surface orientation of the substrate may be one selected from the group consisting of (111), (100) and (110). When this substrate and this substrate surface orientation are used, the first semiconductor layer 12 formed thereon, which is a n-type single crystal diamond substrate, can be formed. － This tends to result in high-quality single-crystal diamonds with fewer crystal defects.

[0029] The thickness of the insulating film 14 is not particularly limited, but can be 10 nm or more and 400 nm or less, which is suitable as a gate insulating film.

[0030] The insulating film 14 is made of alumina (Al ２ O ３ ), hafnium dioxide (HfO ２ ), hafnium silicon dioxide (HfSiO ２ ), aluminum nitride (AlN), boron nitride (BN), silicon dioxide (SiO ２ ), calcium difluoride (CaF ２ ), silicon oxynitride (SiON), silicon nitride (SiN ｘ , x is more than 0 and not more than 1.34), tantalum pentoxide (Ta ２ O ５ ) and magnesium difluoride (MgF ２ In particular, alumina (Al ２ O ３ ), hafnium dioxide (HfO ２ ) and silicon dioxide (SiO ２) can be preferably used because they have few defects and impurity levels.

[0031] The thickness of the gate electrode 15, the source electrode 16, and the drain electrode 17 is not particularly limited, but may be in the range of 10 nm to 500 nm.

[0032] Examples of materials for the gate electrode 15, source electrode 16, and drain electrode 17 include one or more selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), iridium (Ir), rhenium (Re), palladium (Pd), rhodium (Rd), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), magnesium (Mg), tungsten (W), copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), iron (Fe), zinc (Zn), cadmium (Cd), mercury (Hg), gallium (Ga), indium (In), boron (B), carbon (C), silicon (Si), and germanium (Ge). These materials may be used as a single layer film or a laminated film. In particular, the material of the source electrode 16 and the drain electrode 17 in contact with the second semiconductor layer 13 is preferably one selected from the group consisting of titanium (Ti), chromium (Cr), molybdenum (Mo), and tungsten (W), from the viewpoints of adhesion to the second semiconductor layer 13 and ohmic contact.

[0033] In the MOSFET 101 shown in Figure 1, the gate electrode 15 is arranged inside the end of the insulating film 14 in the thickness direction of the single crystal diamond substrate 11, but as in the MOSFET 102 shown in Figure 16(b), an on-the-line arrangement may be used in which the ends of the insulating film 14 and the gate electrode 15 are in a linear positional relationship in the thickness direction of the single crystal diamond substrate 11. The on-the-line arrangement of the gate electrode shown in Figure 1 is a structure that is less susceptible to the effects of contamination and is suitable for stable transistor operation, while the on-the-line arrangement shown in Figure 16(b) is a structure characterized by a small number of manufacturing steps, high productivity, and ease of increasing the packing density of the element.

[0034] <Element Manufacturing 1> A method for manufacturing the n-type MOSFET 101 of the present invention will be described below with reference to FIGS.

[0035] First, a substrate 11 having a single-crystal diamond layer formed on at least a portion of its surface is prepared (step S51 in FIG. 8, FIG. 2(a)).

[0036] Next, n is deposited on the surface of the substrate 11 on which the single crystal diamond layer is formed. － A first semiconductor layer 12 made of a single-crystal diamond is formed (step S52, FIG. 2(b)).

[0037] The method for forming the first semiconductor layer 12 can be one selected from the group consisting of microwave plasma chemical vapor deposition (MPCVD), direct current plasma chemical vapor deposition (DCPCVD), hot filament chemical vapor deposition (HFCVD), and combustion flame deposition, and microwave plasma chemical vapor deposition, which is less likely to form crystal defects or unintended levels, can be preferably used.

[0038] The first semiconductor layer 12 has a thickness of 1×10 in the channel formation depth region of the MOSFET. １５ cm －３ 2 x 10 or more １８ cm －３ The hydrogen content is 1×10 １０ cm －３ In the channel formation depth region of the MOSFET, the n-type impurity concentration of the first semiconductor layer 12 is 1×10 １５ cm －３ 5x10 or more １８ cm －３ or less or 1 x 10 １６ cm －３ 2 x 10 or more １８ cm －３ The hydrogen content of the first semiconductor layer 12 may be 1×10 or less. １０ cm －３ 5x10 or more １７ cm －３ It may be the following:

[0039] The n-type impurity may be one or more selected from the group consisting of phosphorus (P), sulfur (S), arsenic (As), and boron-oxygen complex (B—O), and phosphorus is particularly preferred. ３ The phosphorus can be introduced into the first semiconductor layer 12 by adding a gas containing phosphorus such as the above and performing microwave plasma vapor deposition.

[0040] The thickness of the first semiconductor layer 12 can be set to 5 nm or more and 5 μm or less. Setting the thickness of the first semiconductor layer 12 to 5 nm or more ensures a channel with few defects, while setting the thickness to 5 μm or less ensures productivity and suppresses the generation of stress that causes distortion in the element.

[0041] Then, n is formed on the first semiconductor layer 12. ＋ A second semiconductor layer 13a made of diamond is formed (step S53, FIG. 2(c)).

[0042] The method for forming the second semiconductor layer 13a may be one selected from the group consisting of microwave plasma chemical vapor deposition (MPCVD), direct current plasma chemical vapor deposition (DCPCVD), hot filament chemical vapor deposition (HFCVD), and combustion flame deposition, with microwave plasma chemical vapor deposition being particularly preferred. The use of microwave plasma chemical vapor deposition makes it possible to share the facilities for forming the first semiconductor layer 12, thereby improving production efficiency, including equipment maintenance.

[0043] The second semiconductor layer 13a has a thickness of 1×10 １９ cm －３ 2 x 10 or more ２２ cm －３ The hydrogen content is 1×10 １０ cm －３ 2 x 10 or more ２２ cm －３ The following applies.

[0044] The n-type impurity may be one or more selected from the group consisting of phosphorus (P), sulfur (S), arsenic (As), and boron-oxygen complex (B—O), and phosphorus is particularly preferred. ３ The phosphorus can be introduced by adding a phosphorus-containing gas such as the above and carrying out microwave plasma vapor deposition.

[0045] The thickness of the second semiconductor layer 13a can be 1 nm or more and 1000 nm or less. By making the thickness of the second semiconductor layer 13a 1 nm or more, preferably 10 nm or more, ohmic contact can be achieved with both the source and drain, and contact resistance can be sufficiently reduced. By making the thickness of the second semiconductor layer 13a 1000 nm or less, preferably 100 nm or less, contact resistance can be suppressed and productivity can be improved.

[0046] Subsequently, before forming the first conductive film 16a in the next step, it is preferable to treat the surface of the second semiconductor layer 13a with an acidic solution at 50°C to 400°C to oxygen-terminate the surface of the second semiconductor layer 13a. Here, as the acidic solution, a mixed acid of sulfuric acid and nitric acid, in which the volume ratio of nitric acid to sulfuric acid (volume of nitric acid / volume of sulfuric acid) is 3, is preferably used, which is widely used as a cleaning solution and allows stable processing including cleaning. The temperature of the acidic solution is preferably 100°C to 350°C or 150°C to 350°C.

[0047] Thereafter, a first conductive film 16a is formed on the second semiconductor layer 13a (step S54, FIG. 2(d)).

[0048] The first conductive film 16a may be made of one or more of the following materials: gold (Au), silver (Ag), platinum (Pt), iridium (Ir), rhenium (Re), palladium (Pd), rhodium (Rd), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), magnesium (Mg), tungsten (W), copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), iron (Fe), zinc (Zn), cadmium (Cd), mercury (Hg), gallium (Ga), indium (In), boron (B), carbon (C), silicon (Si), and germanium (Ge). These materials may be used as a single layer or a multilayer film. The first conductive film 16a can be formed by one or more methods selected from the group consisting of sputtering, thermal and electron beam evaporation, and atomic layer deposition (ALD).

[0049] Thereafter, lithography is performed to form a resist pattern 21 for forming source and drain electrodes on the first conductive film 16a (FIG. 3(a)), and etching is performed using the resist pattern 21 as an etching mask to process the first conductive film 16a into the shapes of the source electrode 16 and the drain electrode 17 (step S55, FIG. 3(b)).

[0050] Subsequently, the second semiconductor layer 13a is etched using oxygen plasma until the first semiconductor layer 12 is exposed in at least the first region R1 where the gate electrode is to be formed or the region R4 where the channel is to be formed, thereby processing the second semiconductor layer 13a into the second semiconductor layer 13 that serves as an electrical contact layer for the source electrode 16 and the drain electrode 17 to make ohmic contact with the first semiconductor layer 12 (FIG. 3(c)). By this step, the surface of the first semiconductor layer 12 in at least the first region where the gate electrode is to be formed or the region R4 where the channel is to be formed is oxygen-terminated, and the second semiconductor layer 13 is formed on the second and third regions. The resist pattern 21 is also removed.

[0051] Examples of etching using oxygen plasma include reactive ion etching using oxygen plasma, focused ion beam etching, and laser beam etching.

[0052] Through the above steps, the source electrode 16 and the drain electrode 17 are formed, which have low contact resistance with the first semiconductor layer 12 and can make ohmic contact (step S56, FIG. 3C).

[0053] Next, an insulating film 14a is deposited so as to cover the exposed surfaces of the first semiconductor layer 12, the source electrode 16, and the drain electrode 17 (FIG. 4A). The deposition method can be one or more selected from the group consisting of atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, and coating methods. The ALD method, which has excellent controllability of film thickness and chemical composition, is particularly preferred. The insulating film 14a can be a single-layer film or a multilayer film.

[0054] The thickness of the insulating film 14a can be 10 nm to 400 nm, which is suitable for a gate insulating film. ２ O ３ ), hafnium dioxide (HfO ２ ), hafnium silicon dioxide (HfSiO ２ ), aluminum nitride (AlN), boron nitride (BN), silicon dioxide (SiO ２ ), calcium difluoride (CaF ２ ), silicon oxynitride (SiON), silicon nitride (SiN ｘ , x is more than 0 and not more than 1.34), tantalum pentoxide (Ta ２ O ５ ) and magnesium difluoride (MgF ２ In particular, alumina (Al ２ O ３ ), hafnium dioxide (HfO ２ ) and silicon dioxide (SiO ２ ) can be preferably used because it generates fewer defects and impurity levels.

[0055] Thereafter, a second conductive film 15a is formed on the insulating film 14a (FIG. 4B). The thickness of the second conductive film 15a is not particularly limited, but may be in the range of 10 nm to 500 nm.

[0056] Examples of materials for the second conductive film 15 a include one or more selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), iridium (Ir), rhenium (Re), palladium (Pd), rhodium (Rd), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), magnesium (Mg), tungsten (W), copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), iron (Fe), zinc (Zn), cadmium (Cd), mercury (Hg), gallium (Ga), indium (In), boron (B), carbon (C), silicon (Si), and germanium (Ge), and the second conductive film 15 a may be used as a single layer film or a laminated film. The method for forming the second conductive film 15a may be one or more selected from the group consisting of sputtering, thermal and electron beam evaporation, and ALD.

[0057] The second conductive film 15a is heated to a pressure of 1×10 －１２ Pa or more 2×10 －６ Pa or less, preferably 1×10 －１２ Pa or more 1×10 －６ When formed in a vacuum environment of 0.1 Pa or less, the purity is excellent.

[0058] Thereafter, a resist pattern 22 is formed by lithography (FIG. 5(a)), and etching is performed using the resist pattern 22 as an etching mask to form the gate electrode 15 from the second conductive film 15a (FIG. 5(b)). After the resist pattern 22 is removed by ashing and / or using a stripping solution (FIG. 6(a)), a resist pattern 23 is formed by lithography (FIG. 6(b)).

[0059] Subsequently, the insulating film 14a is etched using the resist pattern 23 as an etching mask to form the insulating film 14 as a gate insulating film in the region including the region R4 (step S57, FIG. 7A).

[0060] Thereafter, the resist pattern 23 is removed by ashing and / or using a remover, thereby completing the manufacture of the n-type MOSFET 101 using single crystal diamond as the semiconductor layer (step S58, FIG. 7(b)).

[0061] In the above steps, after forming the gate electrode 15, the insulating film 14 is fabricated as a gate insulating film. However, it is also possible to form the insulating film 14 covering at least the region R4 prior to forming the second conductive film 15a, and then form the gate electrode 15.

[0062] The above-described method for manufacturing the element 1 is characterized in that it is easy to increase the electrical conductivity of the second semiconductor layers 13a and 13b, and the contact characteristics of the source (S) and drain (D) with the first semiconductor layer 12 are excellent.

[0063] <Element Manufacturing 2> In the method described above, the source (S) and drain (D) are formed before the gate (G), but the gate may be formed before the source and drain. The steps in this case will be described with reference to FIG.

[0064] First, a substrate having a single-crystal diamond layer formed on at least a portion of its surface is prepared (step S11 in FIG. 9). Here, the substrate is the same as that in the above-described element production 1.

[0065] Next, n is deposited on the surface of the substrate on which the single-crystal diamond layer has been formed. － A first semiconductor layer made of a single-crystal diamond is formed (step S12). The conditions for forming the first semiconductor layer are the same as those in the above-mentioned element production 1.

[0066] Thereafter, an insulating film is formed on a first region that is a part of the first semiconductor layer (step S13). The first region and the insulating film are also similar to those in the above-described element production 1.

[0067] Thereafter, a gate electrode is formed on the insulating film (step S14). The conditions for the gate electrode and the method for fabricating the gate electrode are the same as those in the above-mentioned element fabrication 1.

[0068] Next, n is formed on a second region and a third region different from the first region of the first semiconductor layer. ＋ Then, a second semiconductor layer made of diamond is formed on each of the semiconductor layers (step S15). The material and manufacturing method for the second semiconductor layer are the same as those in the above-mentioned element manufacturing 1.

[0069] A source electrode is formed on the second semiconductor layer in the second region (step S16), and a drain electrode is formed on the second semiconductor layer in the third region (step S17), thereby producing an n-type MOSFET 101 using single crystal diamond as the semiconductor layer (step S20).

[0070] The above-mentioned method 2 for manufacturing an element is a method in which the gate is fabricated first, and has the advantage of suppressing degradation of the insulator and making it less likely to cause a decrease in yield.

[0071] (Example 1) In Example 1, n － Type and n ＋ A single-crystal diamond thin film of this type was formed by microwave plasma chemical vapor deposition (MPCVD) and evaluated using SIMS (Secondary Ion Mass Spectrometry) and AFM (Atomic Force Microscopy).

[0072] <Film formation> 1. n － Type Single Crystal Diamond Film (First Semiconductor Layer) A 450 μm thick Ib type (111) oriented high pressure, high temperature (HPHT) synthetic single crystal diamond substrate (Sumicrystal, manufactured by Sumitomo Electric Hardmetal Corp.) was prepared. － Before forming a diamond thin film, the surface of the substrate was treated with nitric acid (HNO ３ ) and sulfuric acid (H ２ SO ４ The volume ratio of sulfuric acid to nitric acid was 1:1, and the treatment was carried out at a boiling temperature of 250°C or higher for 2 to 3 hours.

[0073] Then, microwave plasma chemical vapor deposition (MPCVD) was carried out under the following conditions to form n-type layers on the surface of the synthetic single crystal diamond. － A single crystal diamond film was formed using the MPCVD equipment. The MPCVD equipment was a homemade equipment. Raw material gas: methane (CH ４ ), flow rate 0.5 sccm Carrier (dilution) gas: Hydrogen (H ２ ), flow rate 1000sccm CH ４ / H ２ Ratio: 0.05% PH ３ / CH ４ : 0 to 100 ppm Film formation pressure: 100 Torr (13.3 kPa) Microwave power: 500 W Substrate temperature: 920°C Growth time: 1.5 hours Film thickness (thickness of epitaxial layer): 0.5 μm

[0074] 2. n ＋ n-type single crystal diamond film (second semiconductor layer) － Following the deposition of the n-type single crystal diamond film, － Highly phosphorus-doped n-type single crystal diamond film ＋ A diamond layer is epitaxially formed on a synthetic single crystal diamond substrate. － type single crystal diamond film and n ＋ The deposition conditions are as follows: Growth technique: Microwave plasma chemical vapor deposition (MPCVD) method Source gas: Methane (CH ４ ), flow rate 0.5 sccm Carrier (dilution) gas: Hydrogen (H ２ ), flow rate 1000sccm CH ４ / H ２ Ratio: 0.05% PH ３ / CH ４: 1% Pressure during growth: 100 Torr (13.3 kPa) Microwave power: 500 W Substrate temperature: 920°C Growth time: 2 hours Film thickness (thickness of epitaxial layer): 0.1 μm

[0075] n ＋ After the deposition of the n-type single crystal diamond film was completed and the supply of methane gas was stopped, ＋ The n-type single crystal diamond film was kept at the substrate temperature in a hydrogen atmosphere for 30 minutes. ＋ The surface of the single crystal diamond film was once hydrogen-terminated. Then, in order to remove the surface conductive layer and obtain an oxygen-terminated surface, the sample was left at 300°C for 60 minutes in a mixed acid solution consisting of 1 part sulfuric acid and 3 parts nitric acid by volume. ＋ The sample obtained was a single crystal diamond film with the surface terminated with oxygen.

[0076] <Characteristics evaluation> n ＋ In a sample in which the surface of a type single crystal diamond film was terminated with oxygen, the concentration distribution of phosphorus (P) and hydrogen (H) in the sample depth direction was investigated using SIMS (IMS-7f, manufactured by CAMECA). The results are shown in Figure 10. As a result, a n-type single crystal diamond film with a thickness of about 0.1 μm, which corresponds to the second semiconductor layer formed on the surface of the sample, was found to have a thickness of about 0.1 μm. ＋ The concentration of the layer is about 9×10 １９ cm －３ , hydrogen is 3 x 10 １９ cm －３ ~1 x 10 １８ cm －３ It was.

[0077] On the other hand, the n-type semiconductor layer corresponding to the first semiconductor layer formed to a thickness of about 0.5 μm below and in contact with the second semiconductor layer. － The concentration of the layer is 1×10 １５ cm －３ ~1 x 10 １８ cm －３ and hydrogen (H) is within the range of 1 × 10 １５ cm －３ ~1 x 10 １8 cm －３It was within the range of n － A sharp peak in concentration is observed at the interface between the layer and the substrate, which is thought to be due to the influence of crystal defects on the substrate surface. － This peak is to be excluded when determining the phosphorus and hydrogen concentrations of the layer.

[0078] Furthermore, another sample was formed up to the first semiconductor layer according to the above process, and the surface roughness of the first semiconductor layer was measured using an AFM (AFM5200S, manufactured by Hitachi High-Tech Science Corporation). An example of the measurement is shown in Figure 11. Here, the measurement area was 10 μm × 10 μm, and measurements were made in tapping mode using a needle with a tip radius of 2 nm. The height difference between each step in Figure 11 is 0.5 nm.

[0079] As is clear from Figure 11, a slope of the surface is observed from the upper right to the lower left, but no significant difference in surface roughness is observed. The surface roughness R (rms) measured in a measurement area of ​​1000 nm x 1000 nm was approximately 1 nm, which was a small enough surface to sufficiently suppress carrier scattering as a channel layer interface for a MOS transistor.

[0080] In Example 2, MOSFETs conforming to the first embodiment were fabricated and their characteristics were evaluated. The MOSFETs fabricated were of two shapes, a circle and a rectangle, as shown in FIG.

[0081] <Sample Preparation> First, according to Example 1, a 450 μm thick Ib type (111) oriented high pressure, high temperature (HPHT) synthetic single crystal diamond substrate 11 (FIG. 13(a)) was prepared (step S51 in FIG. 8), and a n-type diamond substrate having a thickness of about 0.5 μm was formed on the single crystal diamond substrate 11. － a first semiconductor layer 12 made of single-crystal diamond (FIG. 13(b), step S52), and a n-type single-crystal diamond layer having a thickness of about 0.1 μm. ＋ Then, a second semiconductor layer 13a (FIG. 13(c), step S53) made of single crystal diamond was formed.

[0082] Thereafter, the second semiconductor layer 13a is washed with a boiling mixed acid solution (250° C. or higher) of nitric acid and sulfuric acid to remove contamination from the surface of the second semiconductor layer 13a, i.e., n＋ The surface of the diamond single crystal was oxidized using a volume ratio of nitric acid to sulfuric acid of 1:2.

[0083] Next, a conductive film 16a made of titanium (Ti), platinum (Pt), and gold (Au) was sequentially deposited on the second semiconductor layer 13a using an electron beam evaporator (ADS-RDEB, manufactured by R-Dec) (FIG. 13(d), step S54). The thicknesses of Ti, Pt, and Au were 50 nm, 10 nm, and 100 nm, respectively. Here, the degree of vacuum was 10 －６ After depositing the conductive film 16a, the film was annealed in vacuum at 500° C. for 30 minutes in order to reduce the contact resistance of the electrode.

[0084] Thereafter, a resist pattern 21 for forming source (S) and drain (D) electrodes was formed on the conductive film 16a by photolithography (FIG. 14(a)). Thereafter, using the resist pattern 21 as an etching mask, the conductive film 16a was etched by RIE (Reactive Ion Etching) using oxygen gas until the second semiconductor layer 13a was exposed, thereby forming the source electrode 16 and the drain electrode 17 (FIG. 14(b), step S55).

[0085] Subsequently, using the source electrode 16 and the drain electrode 17 as a main etching mask, the second semiconductor layer 13a was dry-etched using oxygen plasma until the surface of the first semiconductor layer 12 was exposed, thereby exposing the first region of the first semiconductor layer and forming the second semiconductor layer 13 on the second and third regions of the first semiconductor layer. ＋ A source electrode 16 and a drain electrode 17 were formed to provide ohmic contact via the second semiconductor layer 13 made of a diamond layer (FIG. 14(c), step S56). Here, the exposed first semiconductor layer 12 was exposed to oxygen plasma, so its surface became an oxygen-terminated surface, and the resist pattern 21 was also removed. The dry etching apparatus used was an RIE-101iPH manufactured by Samco Corporation.

[0086] Then, an alumina (Al ) film with a thickness of 30 nm was deposited by atomic layer deposition (ALD). ２ O ３ An insulating film 14a made of a SiO 2 film was deposited on the surface of the sample (FIG. 15A, step S57). This deposition was carried out at 200° C. using trimethylaluminum (TMA) as a precursor.

[0087] Next, after the insulating film 14a was washed with ultrapure water, a conductive film 15a consisting of a 10 nm thick Ti layer and a 60 nm thick Au layer was deposited by electron beam evaporation (FIG. 15(b)). Here, a deposition apparatus (ADS-RDEB, manufactured by R-Dec Co., Ltd.) was used, and the base pressure was 1×10 －５ The temperature was set to Pa.

[0088] Thereafter, a resist pattern 22 for fabricating a gate electrode was formed on the conductive film 15a by photolithography (FIG. 16(a)), and the conductive film 15a and the insulating film 14a were processed by dry etching (RIE etching) to fabricate a gate (G) consisting of the gate electrode 15 and the gate insulating film 14 (FIG. 16(b), step S58). Here, an RIE-200NL manufactured by Samco Corporation was used as the etching device, and carbon tetrafluoride (CF ４ ) / oxygen mixed gas for etching the insulating film 14a, and boron trichloride (BCl ３ A mixed gas of chlorine and argon was used. The resist pattern 22 was removed by ashing and using a stripper. Through the above steps, the n-type MOSFET 102 of Example 2 was fabricated (FIG. 16B, step S60).

[0089] An optical microscope photograph of the fabricated n-type diamond MOSFET 102 viewed from above is shown in Figure 12. The circular MOSFET transistor shown on the left side of Figure 12 had a gate length (Lg) of 10 μm, a gate width (Wg) of 700 μm, a source 16-gate 15 (Lsg) distance of 10 μm, and a gate 15-drain 17 (Lgd) distance of 10 μm, while the rectangular MOSFET transistor shown on the right side of Figure 12 had a gate length (Lg) of 10 μm, a gate width (Wg) of 900 μm, a source 16-gate 15 (Lsg) distance of 10 μm, and a gate 15-drain 17 (Lgd) distance of 10 μm.

[0090] <Characteristics Evaluation> <<Drain Voltage Dependence of Drain Current>> For the circular MOSFET described above, the gate voltage Vg was varied from -20 V to 10 V in 5 V increments to examine the drain current dependency on the drain voltage, and the results are shown in Figure 17. Here, Figure 17(a) shows the results measured at room temperature, and Figure 17(b) shows the results measured in an environment of 300°C. The measurement device used was a Model 2600 (manufactured by Keithley).

[0091] As shown in FIGS. 17(a) and 17(b), n-type MOSFET operation was confirmed in the circular MOSFET, and the drain saturation current at 300° C. was 100 μA, which is approximately 4000 times higher than that at room temperature (drain voltage: 20 V, gate voltage: 10 V).

[0092] <<Drain Current Dependence on Gate Voltage>> Figure 18 shows the results of measuring the gate voltage dependence of the drain current for the circular MOSFET. Figure 18(a) shows the results measured at room temperature, and Figure 18(b) shows the results measured in an environment of 300°C. The circular MOSFET exhibits good operation as an n-type MOSFET at both room temperature and 300°C.

[0093] <<Gate Voltage Dependence of Transconductance>> Figure 19 shows the results of measuring the gate voltage dependence of transconductance for the above circular MOSFET. Figure 19(a) shows the measurement at room temperature, and Figure 19(b) shows the measurement at 300°C. The gate length L was 900 μm. Figure 19(a) shows that the transconductance at a gate voltage of 0 V is approximately 0.001 μS at room temperature, but Figure 19(b) shows that this increases to approximately 4 μS at 300°C.

[0094] <<Temperature Dependence of Threshold Voltage>> For the above circular MOSFET, the threshold voltage V ｔｈ The temperature dependence of the threshold voltage V ｔｈ It can be seen that the threshold voltage V ｔｈ The temperature dependence of the insulating layer is believed to be due to the insulating layer.

[0095] <<Gate Voltage Dependence of Mobility>> FIG. 21 shows the results of measuring the gate voltage dependency of mobility at 300° C. for the circular MOSFET. ２ It can be seen that a mobility of 1 / Vs or more is ensured.

[0096] From the above, it was demonstrated that the diamond MOSFET 102 shown in Example 2 is a MOSFET that operates well as an n-type transistor even at a high temperature of 300°C.

[0097] According to the present invention, an n-type MOSFET using single-crystal diamond as a semiconductor layer, which operates stably even at temperatures as high as 300°C, and a method for manufacturing the same, are provided. Single-crystal diamond has outstanding physical properties, such as a wide bandgap energy, a low dielectric constant, a high dielectric breakdown field strength, a high carrier saturation velocity, a high thermal conductivity, and a high carrier mobility. Therefore, the present invention makes it possible to provide an n-type MOSFET that is high-performance and highly resistant to harsh environments.

[0098] Furthermore, by combining the n-type diamond MOSFET of the present invention with a p-type MOSFET using a single-crystal diamond semiconductor layer that has already been developed, it will be possible to provide a CMOS using a single-crystal diamond semiconductor. Therefore, the present invention has great potential for industrial use.

[0099] 11: Substrate, single crystal diamond substrate 12: First semiconductor layer 13, 13a: Second semiconductor layer 14: Insulating film 14a: Insulating film 15: Gate electrode 15a: Second conductive film 16: Source electrode 16a: First conductive film 17: Drain electrode 21: Resist pattern 22: Resist pattern 23: Resist pattern 31: Channel 101: n-type MOSFET 102: n-type MOSFET

Claims

1. A substrate having a single-crystal diamond layer on at least a portion of its surface, In contact with the surface of the single-crystal diamond layer, and n － A first semiconductor layer made of a diamond single crystal, A gate electrode portion having an insulating film laminated on a first region of the first semiconductor layer and functioning as a gate insulating film, and a gate electrode laminated on the insulating film, It is stacked on a second region different from the first region in the first semiconductor layer, and n ＋ A source electrode portion having a second semiconductor layer made of type diamond, and a source electrode laminated on the second semiconductor layer, The device comprises a second semiconductor layer laminated on a third region of the first semiconductor layer that is different from the first and second regions, and a drain electrode portion having a drain electrode laminated on the second semiconductor layer, The first semiconductor layer has a concentration of 1 × 10 in the channel formation depth region of the MOSFET. １５ cm －３ The above 2 x 10 １８ cm －３ It contains the following n-type impurities and has a hydrogen content of 1 × 10⁻⁶ １０ cm －３ The above concentrations are below the same order of magnitude as the aforementioned n-type impurities. The surface of at least the first region of the first semiconductor layer is terminated with oxygen. Each of the second semiconductor layers contains n-type impurities with a concentration of 1×10 １９ cm －３ or more and 2×10 ２２ cm －３ or less, and has a hydrogen content of 1×10 １０ cm －３ or more and 2×10 ２２ cm －３ or less, and Each of the second semiconductor layers is electrically in contact with the first semiconductor layer, and the n-type diamond MOSFET is provided.

2. The hydrogen content of the first semiconductor layer is 1 × 10 １０ cm －３ The above 5 x 10 １７ cm －３ The following is the n-type diamond MOSFET according to claim 1.

3. The n-type diamond MOSFET according to claim 1, wherein the n-type impurity consists of one or more selected from the group consisting of phosphorus (P), sulfur (S), arsenic (As), and boron-oxygen complex (B-O).

4. The n-type diamond MOSFET according to claim 3, wherein the n-type impurity is phosphorus (P).

5. The insulating film is made of alumina (Al ２ O ３ ), hafnium dioxide (HfO ２ ), hafnium silicon dioxide (HfSiO ２ ), aluminum nitride (AlN), boron nitride (BN), silicon dioxide (SiO ２ ), calcium difluoride (CaF ２ ), silicon oxide nitride (SiON), silicon nitride (SiN ｘ , x is greater than 0 and less than or equal to 1.34), tantalum pentoxide (Ta ２ O ５ ) and magnesium difluoride (MgF ２ An n-type diamond MOSFET according to claim 1, comprising one or more selected from the group consisting of ).

6. The n-type diamond MOSFET according to claim 1, wherein the substrate is a single-crystal diamond substrate.

7. The n-type diamond MOSFET according to claim 6, wherein the single-crystal diamond substrate is a nitrogen-containing Ib-type single-crystal diamond substrate or a IIa-type single-crystal diamond substrate.

8. The n-type diamond MOSFET according to claim 7, wherein the plane orientation of the single-crystal diamond substrate is one selected from the group consisting of (111), (100), and (110).

9. The n-type diamond MOSFET according to claim 1, wherein the materials of the gate electrode, source electrode, and drain electrode include one or more selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), iridium (Ir), rhenium (Re), palladium (Pd), rhodium (Rd), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), magnesium (Mg), tungsten (W), copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), iron (Fe), zinc (Zn), cadmium (Cd), mercury (Hg), gallium (Ga), indium (In), boron (B), carbon (C), silicon (Si), and germanium (Ge).

10. The n-type diamond MOSFET according to claim 9, wherein the material of the source electrode and the drain electrode in contact with the second semiconductor layer includes one selected from the group consisting of titanium (Ti), chromium (Cr), molybdenum (Mo), and tungsten (W).

11. Prepare a substrate in which a single-crystal diamond layer is formed on at least a portion of the surface, n － To form a first semiconductor layer made of a diamond single crystal, Forming an insulating film on a first region of a portion of the first semiconductor layer, Forming a gate electrode on the insulating film, n ＋ Forming a second semiconductor layer made of diamond, Forming a source electrode on the second semiconductor layer in the second region, This includes forming a drain electrode on the second semiconductor layer in the third region, The first semiconductor layer has a concentration of 1 × 10 in the channel formation depth region of the MOSFET. １５ cm －３ The above 2 x 10 １８ cm －３ It contains the following n-type impurities and has a hydrogen content of 1 × 10⁻⁶ １０ cm －３ The above concentrations are below the same order of magnitude as the aforementioned n-type impurities. The surface of at least the first region of the first semiconductor layer is terminated with oxygen. Each of the second semiconductor layers has a concentration of 1 × 10 １９ cm －３ The above 2 x 10 ２２ cm －３ It contains the following n-type impurities and has a hydrogen content of 1 × 10⁻⁶ １０ cm －３ The above 2 x 10 ２２ cm －３ The following and A method for manufacturing an n-type diamond MOSFET, wherein each of the second semiconductor layers is electrically in contact with the first semiconductor layer.

12. Prepare a substrate in which a single-crystal diamond layer is formed on at least a portion of the surface, n － To form a first semiconductor layer made of a diamond single crystal, n ＋ To form a second semiconductor layer made of type diamond, Forming a first conductive film on the second semiconductor layer, The first conductive film is subjected to lithography and etching to form a source electrode and a drain electrode, Etching the second semiconductor layer with respect to at least the region where the gate electrode is formed or the channel is formed, using oxygen plasma until the first semiconductor layer is exposed, Forming an insulating film on at least the region including the said region on the first semiconductor layer, This includes forming a gate electrode consisting of a second conductive film on the insulating film, The first semiconductor layer has a concentration of 1 × 10 in the channel formation depth region of the MOSFET. １５ cm －３ The above 2 x 10 １８ cm －３ It contains the following n-type impurities and has a hydrogen content of 1 × 10⁻⁶ １０ cm －３ The above is below the same order of magnitude as the n-type impurity, and The second semiconductor layer has a concentration of 1 × 10 １９ cm －３ The above 2 x 10 ２２ cm －３ It contains the following n-type impurities and has a hydrogen content of 1 × 10⁻⁶ １０ cm －３ The above 2 x 10 ２２ cm －３ The following is a method for manufacturing an n-type diamond MOSFET.

13. The second conductive film is subjected to a pressure of 1 × 10⁻⁶. －１２ Pa or more 2×10 －６ A method for manufacturing an n-type diamond MOSFET according to claim 12, formed in a vacuum environment of Pa or less.

14. A method for manufacturing an n-type diamond MOSFET according to claim 12, wherein, before forming the first conductive film, the surface of the second semiconductor layer is treated with an acidic solution at 50°C to 400°C to terminate the second semiconductor layer with oxygen.

15. The method for producing an n-type diamond MOSFET according to claim 14, wherein the acidic solution is a mixed acid consisting of sulfuric acid and nitric acid, with a volume ratio of nitric acid to sulfuric acid of 3.

16. The hydrogen content of the first semiconductor layer is 1 × 10⁻⁶ １０ cm －３ The above 5 x 10 １７ cm －３ The method for manufacturing an n-type diamond MOSFET according to claim 11 or 12, which is as follows:

17. A method for manufacturing an n-type diamond MOSFET according to claim 11 or 12, wherein the first semiconductor layer and the second semiconductor layer are formed by microwave plasma vapor deposition (MPCVD).

18. The method for manufacturing an n-type diamond MOSFET according to claim 11 or 12, wherein the insulating film is formed by atomic layer deposition (ALD) method.