Semiconductor device

Abstract

Provided is a semiconductor device comprising an active part and a temperature-sensitive part, the semiconductor device comprising: a semiconductor substrate; and an interlayer insulating film provided above the semiconductor substrate. The active part includes an active trench part provided on a front surface of the semiconductor substrate, and an active contact part provided in the interlayer insulating film above the active trench part. The temperature-sensitive part has a temperature-sensitive diode provided above the semiconductor substrate, and a temperature-sensitive contact part provided in the interlayer insulating film above the temperature-sensitive diode. The contact width of the temperature-sensitive contact part is larger than the contact width of the active contact part. In the depth direction of the semiconductor substrate, the extension depth of the temperature-sensitive trench contact portion extending from an upper surface of the temperature-sensitive diode in the depth direction of the semiconductor substrate is shallower than the extension depth of the plurality of active trench contact portions extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Patent Document 1 describes a "semiconductor device with an integrated PN diode temperature sensor and a method for manufacturing the same." [Prior art documents] [Patent documents] [Patent document 1] U.S. Patent Application Publication No. 2019 / 0172770 General disclosure

[0003] In a first aspect of the present invention, there is provided a semiconductor device comprising an active portion and a temperature-sensing portion, the semiconductor device comprising: a semiconductor substrate of a first conductivity type; and an interlayer insulating film provided above a front surface of the semiconductor substrate; the active portion has an active trench portion provided on the front surface of the semiconductor substrate and an active contact portion provided in the interlayer insulating film; the temperature-sensing portion has a temperature-sensing diode provided above or on the front surface side of the semiconductor substrate, and a temperature-sensing contact portion provided in the interlayer insulating film above the temperature-sensing diode; and the contact width of the temperature-sensing contact portion is larger than the contact width of the active contact portion.

[0004] In the semiconductor device, a temperature-sensitive contact width where the temperature-sensitive contact portion contacts the temperature-sensitive diode may be larger than a first active contact width where the active contact portion contacts the top surface of a mesa portion of the semiconductor substrate.

[0005] In any of the above semiconductor devices, a temperature-sensitive contact width where the temperature-sensitive contact portion is in contact with the temperature-sensitive diode may be larger than a second active contact width where the active contact portion is in contact with the active trench portion.

[0006] In any of the above semiconductor devices, the sidewall of the temperature-sensitive contact portion may be in contact with the interlayer insulating film from its upper end to its lower end.

[0007] In any of the above semiconductor devices, the temperature sensing portion may have a recessed region in the upper surface of the semiconductor substrate, and the temperature sensing diode may be provided in the recessed region.

[0008] In any of the above semiconductor devices, the height position of the upper surface of the interlayer insulating film in the active portion may be the same as the height position of the upper surface of the interlayer insulating film in the recess region in the depth direction of the semiconductor substrate.

[0009] In any of the above semiconductor devices, the temperature sensing portion may have a housing portion provided below the temperature sensing contact portion. A corner of a bottom surface of the temperature sensing contact portion may be in contact with the temperature sensing diode. A bottom surface of the temperature sensing contact portion may be in contact with the housing portion.

[0010] In any of the above semiconductor devices, a side surface of the temperature sensitive diode may be in contact with a side surface of the housing portion.

[0011] In any of the above semiconductor devices, the interlayer insulating film may include a first interlayer insulating film provided above the temperature-sensitive diode, and a second interlayer insulating film provided between the temperature-sensitive diode and the semiconductor substrate in the depth direction of the semiconductor substrate.

[0012] In any of the above semiconductor devices, the upper surface of the second interlayer insulating film may be in contact with the lower surface of the temperature sensitive diode and the lower surface of the housing portion.

[0013] In any of the above semiconductor devices, the housing portion may be a region of the first interlayer insulating film that is provided below the temperature-sensitive contact portion.

[0014] In any of the above semiconductor devices, the housing portion may be the second interlayer insulating film provided above the semiconductor substrate.

[0015] In any of the above semiconductor devices, the housing portion may have a polycrystalline semiconductor having a conductivity type different from that of the contact region of the temperature sensitive diode.

[0016] In any of the above semiconductor devices, the housing portion may include a polycrystalline semiconductor having the same conductivity type as the contact region of the temperature sensitive diode and a lower doping concentration than the contact region.

[0017] In any of the above semiconductor devices, the bottom surface of the temperature-sensitive contact portion may be in contact with the temperature-sensitive diode and the housing portion.

[0018] In any of the above semiconductor devices, the temperature-sensitive contact portion may have a barrier metal film provided at the corners of the bottom surface of the temperature-sensitive contact portion, and a plug portion provided in contact with the inner side of the barrier metal film.

[0019] In any of the above semiconductor devices, the temperature sensitive diode may contact the bottom surface of the temperature sensitive contact portion over an area from the bottom corner to 10% to 40% of the bottom surface of the temperature sensitive contact portion.

[0020] In any of the above semiconductor devices, the sidewall of the temperature-sensitive contact portion may be in contact with the temperature-sensitive diode and the first interlayer insulating film, and the temperature-sensitive diode may be in contact with the sidewall of the temperature-sensitive contact portion over an area from the bottom corner to 10% to 90% of the sidewall of the temperature-sensitive contact portion.

[0021] In any of the above semiconductor devices, the temperature-sensing portion may have a temperature-sensing trench contact portion extending in the depth direction of the semiconductor substrate from the upper surface of the interlayer insulating film to a position below the upper surface of the temperature-sensing diode.

[0022] In any of the above semiconductor devices, the active portion may have an active trench contact portion extending from an upper surface of the interlayer insulating film to a position below the front surface of the semiconductor substrate in a depth direction of the semiconductor substrate.

[0023] In any of the above semiconductor devices, the temperature-sensitive diode may have a temperature-sensitive anode region provided above the semiconductor substrate, and a temperature-sensitive cathode region provided above the semiconductor substrate and in contact with the temperature-sensitive anode region.

[0024] Any of the above semiconductor devices may further include a well region of a second conductivity type provided on a front surface of the semiconductor substrate, and the temperature sensing unit may be provided above the well region or on the front surface side of the semiconductor substrate of the well region.

[0025] In a second aspect of the present invention, there is provided a semiconductor device comprising: an active portion having a plurality of active trench contact portions provided on the front surface of a semiconductor substrate of a first conductivity type; and a temperature-sensing portion provided above the semiconductor substrate or on the front surface side of the semiconductor substrate, wherein the temperature-sensing portion has a temperature-sensing diode provided above the semiconductor substrate, an interlayer insulating film provided above the temperature-sensing diode, and a temperature-sensing trench contact portion extending from the upper surface of the interlayer insulating film to a position below the upper surface of the temperature-sensing diode in the depth direction of the semiconductor substrate, and wherein, in the depth direction of the semiconductor substrate, the extension depth of the temperature-sensing trench contact portion from the upper surface of the temperature-sensing diode in the depth direction of the semiconductor substrate is shallower than the extension depth of the plurality of active trench contact portions from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

[0026] In the semiconductor device, the temperature sensing portion may have a recessed region in the upper surface of the semiconductor substrate, and the temperature sensing diode may be provided in the recessed region.

[0027] In any of the above semiconductor devices, a contact width where the temperature-sensitive trench contact portion comes into contact with the temperature-sensitive diode may be larger than a contact width of each of the plurality of active trench contact portions.

[0028] In any of the above semiconductor devices, a contact width where the temperature-sensitive trench contact portion comes into contact with the temperature-sensitive diode may be smaller than a contact width of each of the plurality of active trench contact portions.

[0029] Any of the above semiconductor devices may further include a well region of a second conductivity type provided on a front surface of the semiconductor substrate, and the temperature sensing unit may be provided above the well region or on the front surface side of the semiconductor substrate of the well region.

[0030] In a third aspect of the present invention, there is provided a semiconductor device having a main region and a peripheral region, the semiconductor device comprising: a semiconductor substrate of a first conductivity type; and an interlayer insulating film provided above a front surface of the semiconductor substrate, the main region having a main region contact portion provided in the interlayer insulating film, the peripheral region having a polycrystalline portion provided above or on the front surface side of the semiconductor substrate, and a first peripheral region contact portion provided in the interlayer insulating film above the polycrystalline portion, the contact width of the first peripheral region contact portion being larger than the contact width of the main region contact portion.

[0031] In the semiconductor device, the sidewall of the first outer peripheral region contact portion may be in contact with the interlayer insulating film from its upper end to its lower end.

[0032] In any of the above semiconductor devices, the peripheral region may have a recess region in which a depression is provided in an upper surface of the semiconductor substrate, and the polycrystalline portion may be provided in the recess region.

[0033] In any of the above semiconductor devices, the height position of the upper surface of the interlayer insulating film in the main region may be the same as the height position of the upper surface of the interlayer insulating film in the recess region in the depth direction of the semiconductor substrate.

[0034] In any of the above semiconductor devices, the peripheral region may have a housing portion provided below the first peripheral region contact portion, a bottom corner of the first peripheral region contact portion may be in contact with the polycrystalline portion, or a bottom surface of the first peripheral region contact portion may be in contact with the housing portion.

[0035] In any of the above semiconductor devices, a side surface of the polycrystalline portion may be in contact with a side surface of the housing portion.

[0036] In any of the above semiconductor devices, the housing portion may be a region of the interlayer insulating film that is provided below the first outer periphery region contact portion.

[0037] In any of the above semiconductor devices, the bottom surface of the first outer periphery region contact portion may be in contact with the polycrystalline portion and the housing portion.

[0038] In any of the above semiconductor devices, the first outer periphery region contact portion may have a barrier metal film provided at the bottom corner portion of the first outer periphery region contact portion, and a plug portion provided in contact with the inner side of the barrier metal film.

[0039] In any of the above semiconductor devices, the polycrystalline portion may contact the bottom surface of the first outer peripheral region contact portion from the bottom surface corner to an area of ​​10% to 40% of the bottom surface of the first outer peripheral region contact portion.

[0040] In any of the semiconductor devices described above, a sidewall of the first peripheral region contact portion may be in contact with the polycrystalline portion and the interlayer insulating film, and the polycrystalline portion may be in contact with the sidewall of the first peripheral region contact portion over an area from the bottom corner to 10% to 90% of the sidewall of the first peripheral region contact portion.

[0041] In any of the above semiconductor devices, the peripheral region may have a first peripheral region trench contact portion extending in the depth direction of the semiconductor substrate from the upper surface of the interlayer insulating film to a position below the upper surface of the polycrystalline portion.

[0042] In any of the above semiconductor devices, the main region may have a main region trench contact portion extending from an upper surface of the interlayer insulating film to a position below the front surface of the semiconductor substrate in a depth direction of the semiconductor substrate.

[0043] The semiconductor device may further include a gate trench portion provided on a front surface of the semiconductor substrate and having a gate conductive portion, and a gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion, wherein the polycrystalline portion may be connected to the gate metal layer via the first outer periphery region contact portion.

[0044] The semiconductor device may further include a dummy trench portion provided on the front surface of the semiconductor substrate and having a dummy conductive portion, and an emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate, wherein the polycrystalline portion may be connected to the emitter electrode via the first outer peripheral region contact portion and to the dummy conductive portion.

[0045] The semiconductor device may further include a guard ring of a second conductivity type provided on the front surface of the semiconductor substrate between the main region and an edge of the semiconductor substrate, and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring, and the polycrystalline portion may be connected to the edge metal layer via the first outer periphery region contact portion.

[0046] A fourth aspect of the present invention provides a semiconductor device having a main region and a peripheral region, wherein the main region has a plurality of main region trench contact portions provided on a front surface of a semiconductor substrate of a first conductivity type, and the peripheral region has a polycrystalline portion provided above the semiconductor substrate, an interlayer insulating film provided above the polycrystalline portion, and a peripheral region trench contact portion provided extending from an upper surface of the interlayer insulating film to a position below an upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate, and wherein, in the depth direction of the semiconductor substrate, the extension depth of the peripheral region trench contact portion from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate is shallower than the extension depth of the plurality of main region trench contact portions from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

[0047] In the semiconductor device, the peripheral region may have a recess region in which a depression is provided in an upper surface of the semiconductor substrate, and the polycrystalline portion may be provided in the recess region.

[0048] In any of the above semiconductor devices, a contact width where the peripheral region trench contact portion contacts the polycrystalline portion may be larger than the contact width of each of the plurality of main region trench contact portions.

[0049] In any of the above semiconductor devices, a contact width where the peripheral region trench contact portion contacts the polycrystalline portion may be smaller than each of the contact widths of the plurality of main region trench contact portions.

[0050] The semiconductor device may further include a gate trench portion provided on a front surface of the semiconductor substrate and having a gate conductive portion, and a gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion, wherein the polycrystalline portion may be connected to the gate metal layer via the peripheral region trench contact portion.

[0051] The semiconductor device may further include a dummy trench portion provided on the front surface of the semiconductor substrate and having a dummy conductive portion, and an emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate, wherein the polycrystalline portion may be connected to the emitter electrode via the peripheral region trench contact portion and to the dummy conductive portion.

[0052] The semiconductor device may further include a guard ring of a second conductivity type provided on the front surface of the semiconductor substrate between the main region and an edge of the semiconductor substrate, and an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring, and the polycrystalline portion may be connected to the edge metal layer via the peripheral region trench contact portion.

[0053] In any of the above semiconductor devices, the peripheral region may have a second peripheral region trench contact portion extending from an upper surface of the interlayer insulating film to a depth below an upper surface of the semiconductor substrate in a region where the polycrystalline portion is not provided, and an extension depth of the first peripheral region trench contact portion from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate may be shallower than an extension depth of the second peripheral region trench contact portion from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

[0054] In any of the above-described semiconductor devices, the periphery region may have a second periphery region trench contact portion extending from an upper surface of the interlayer insulating film to a depth below an upper surface of the semiconductor substrate in a region where the polycrystalline portion is not provided, The extension depth of the first periphery region trench contact portion from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate and the extension depth of the second periphery region trench contact portion from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate may be shallower than the extension depth of the plurality of main region trench contact portions from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

[0055] A fourth aspect of the present invention provides a semiconductor device comprising a main region and a pad region, wherein the main region has a plurality of main region trench contact portions provided on a front surface of a semiconductor substrate of a first conductivity type, and the pad region has a pad for connecting to an external circuit, a polycrystalline portion provided above the semiconductor substrate, an interlayer insulating film provided above the polycrystalline portion, and a pad region trench contact portion provided extending from an upper surface of the interlayer insulating film to a position below an upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate, and wherein, in the depth direction of the semiconductor substrate, an extension depth of the pad region trench contact portion from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate is shallower than an extension depth of the plurality of main region trench contact portions from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

[0056] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0057] 1A shows an example of an enlarged view of the top surface of the semiconductor device 100. 1B shows an example of a cross section taken along the line a-a' in FIG. 1A. 1C shows an enlarged view of the top surface of a modified example of the semiconductor device 100. 2B shows an example of a cross section taken along the line b-b' in FIG. 2A. 2D shows an example of a top view of the semiconductor device 100. 2E shows an example of a cross section of the semiconductor device 100 including a temperature sensitive section 180. 2F shows another example of a cross section of the semiconductor device 100 including a temperature sensitive section 180. 2G shows a cross section of a modified example of the semiconductor device 100 including a temperature sensitive section 180. 2G shows a cross section of a modified example of the semiconductor device 100 including a temperature sensitive section 180. 2G shows an example of an enlarged view of a cross section of the semiconductor device 100. 2G shows an enlarged view of a cross section of a modified example ... 9 shows a cross section of a modified example of the semiconductor device 100 including a temperature sensing section 180. 9 shows a cross section of a modified example of the semiconductor device 100 including a temperature sensing section 180. 9 shows an example of an enlarged view of the top surface of the semiconductor device 100. 9 shows an example of a dd-d' cross section in FIG. 9. 9 shows an example of a dd-d' cross section in FIG. 9. 9 shows an example of a dd-d' cross section in FIG. 9. 9 shows an example of a dd-d' cross section in FIG. 9. 9 shows an example of an enlarged view of the dd' cross section in FIG. 9. 9 shows an example of a dd' cross section in FIG. 9. 9 shows an example of an enlarged view of the dd' cross section in FIG. 9. 9 shows an example of an e-e' cross section in FIG. 9. 9 shows an example of an e-e' cross section in FIG. 9. 9 shows an example of an e-e' cross section in FIG. 9. 9 shows an example of an e-e' cross section in FIG. 9. 9 shows an example of an enlarged view of the e-e' cross section in FIG. 9. 9 shows an example of an e-e' cross section in FIG. 9. 9 shows an example of an e-e' cross section in FIG. 9. 9 shows an example of an enlarged view of the e-e' cross section in FIG. 9. 9 shows an example of a top view of the semiconductor device 100. An example of region R in Fig. 18A is shown. An example of an ff' cross section in Fig. 18B is shown. An example of an ff' cross section in Fig. 18B is shown. An example of an ff' cross section in Fig. 18B is shown. An example of an ff' cross section in Fig. 18B is shown. An example of an ff' cross section in Fig. 18B is shown. An example of an ff' cross section in Fig. 18B is shown. An example of an ff' cross section in Fig. 18B is shown.An example of an enlarged view of the f-f' cross section in FIG. 18B is shown. ... 18A , 18B, 18C, 18D, 18E, 18F, 18G, 18G, 18H, 18H, 18I, 18B, 18C, 18D, 18E, 18F, 18G, 18G, 18H ...

[0058] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0059] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0060] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0061] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0062] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0063] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0064] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, if the donor concentration is ND and the acceptor concentration is NA, the net doping concentration at any position is ND-NA. In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0065] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of receiving electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects in semiconductors, where vacancies (V), oxygen (O), and hydrogen (H) are bonded, Si-i-H defects in which interstitial silicon (Si-i) and hydrogen are bonded, and CiOi-H defects in which interstitial carbon (Ci) and interstitial oxygen (Oi) and hydrogen are bonded, function as donors that supply electrons. In this specification, these VOH defects may be referred to as hydrogen donors.

[0066] In this specification, the terms P+ type and N+ type refer to a doping concentration higher than that of P type or N type, and the terms P- type and N- type refer to a doping concentration lower than that of P type or N type. In addition, in this specification, the terms P++ type and N++ type refer to a doping concentration higher than that of P+ type or N+ type.

[0067] In this specification, chemical concentration refers to the concentration atomic density of impurities measured regardless of the state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be referred to as the net doping concentration. Carriers refer to charge carriers of electrons or holes. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. Furthermore, in an N-type region, the donor concentration is sufficiently greater than the acceptor concentration, so the carrier concentration in that region may also be referred to as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be referred to as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0068] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the donor, acceptor, or net doping concentration in the region. In cases where the donor, acceptor, or net doping concentration is approximately uniform, the average value of the donor, acceptor, or net doping concentration in the region may be taken as the donor, acceptor, or net doping concentration.

[0069] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. A decrease in carrier mobility occurs when carriers are scattered due to a disorder in the crystalline structure caused by lattice defects or the like. The reason for the decrease in carrier concentration is as follows. In the SR method, spreading resistance is measured and the carrier concentration is calculated from the measured spreading resistance. At this time, the carrier mobility is calculated using the carrier mobility in the crystalline state. On the other hand, at locations where lattice defects are introduced, the carrier mobility is decreased, but the carrier concentration is calculated using the carrier mobility in the crystalline state. Therefore, the value obtained is lower than the actual carrier concentration, i.e., the donor or acceptor concentration.

[0070] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen. In this specification, the SI unit system is adopted. In this specification, distance and length units may be expressed in cm (centimeter). In this case, various calculations may be performed by converting them to m (meter). Regarding numerical representations of powers of 10, for example, 1E+16 is expressed as 1×10 １６ , and the display of 1E-16 is 1×10 －１６ Shows.

[0071] 1A shows an example of an enlarged view of the top surface of a semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including a transistor portion 70. The semiconductor device 100 is not limited to a transistor, as long as it is a semiconductor element having a MOS gate structure on a semiconductor substrate 10. The configuration in this figure may be arranged periodically or continuously in the +X-axis direction and the −X-axis direction.

[0072] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. However, the transistor section 70 may be another transistor such as a MOSFET.

[0073] In this figure, the area around the active section 120 of the semiconductor device 100 is shown, and other areas are omitted. The active section 120 is the portion between the front surface 21 and the back surface 23 of the semiconductor substrate 10 through which the main current flows. The active section 120 will be described later. For example, an edge termination structure may be provided in the region on the negative side of the Y-axis direction of the semiconductor device 100 in this example. The edge termination structure relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, in this example, the edge on the negative side of the Y-axis direction will be described, but the same applies to other edges of the semiconductor device 100.

[0074] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, another compound semiconductor substrate, or a diamond semiconductor substrate. The semiconductor substrate 10 in this example is a silicon substrate. Note that, in this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 has a front surface 21 and a back surface 23, as described below.

[0075] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are examples of a front surface side metal layer. The gate trench portion 40 is an example of a MOS gate structure included in the semiconductor device 100. Note that although the semiconductor device 100 of this example is a transistor with a MOS gate structure, it may also be a diode with a MOS gate structure.

[0076] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The gate metal layer 50 is provided above the connection portion 25 and the well region 17.

[0077] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal film made of titanium or a titanium compound below the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0078] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in Fig. 1A. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0079] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70 via the connection portion 25. Inside the contact hole 55, a barrier metal film made of titanium or a titanium compound or the like and / or a plug portion made of tungsten or the like may be formed.

[0080] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a barrier metal film made of titanium or a titanium compound or the like and / or a plug portion made of tungsten or the like may be formed.

[0081] The connection portion 25 is connected to a front surface side metal layer such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. In this example, the connection portion 25 is provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0082] The gate trench portion 40 is an example of an active trench portion 122 provided in the front surface 21 of the semiconductor substrate 10. That is, the active trench portion 122 may be a trench portion provided in the active portion 120. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 of this example may have two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 that connects the two extension portions 41.

[0083] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25.

[0084] The dummy trench portion 30 is an example of an active trench portion 122 provided on the front surface 21 of the semiconductor substrate 10. That is, the active trench portion 122 may be a trench portion provided in the active portion 120. The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The dummy trench portion 30 in this example has an I-shape on the front surface 21 of the semiconductor substrate 10, but may also have a U-shape on the front surface 21 of the semiconductor substrate 10, like the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions extending along the extension direction and a connection portion connecting the two extension portions.

[0085] The transistor section 70 of this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extension sections 41.

[0086] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 may be greater than the ratio of the dummy trench portions 30, or the ratio of the dummy trench portions 30 may be greater than the ratio of the gate trench portions 40. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all trench portions as gate trench portions 40 and may not have dummy trench portions 30.

[0087] The well region 17 is a second conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18 described below. The well region 17 is an example of a well region provided on the peripheral side of the active portion 120. The well region 17 is, for example, P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0088] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0089] The mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0090] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.

[0091] The base region 14 is a region of a second conductivity type provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 in the Y-axis direction. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

[0092] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0093] The emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0094] The contact region 15 is provided above the base region 14 and is a second conductivity type region having a higher doping concentration than the base region 14. In this example, the contact region 15 is P+ type, for example. The contact region 15 in this example is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0095] 1B shows an example of the aa' cross section in FIG. 1A. The aa' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the aa' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, a collector electrode 24, and an active contact section 124. The collector electrode 24 is an example of a back-side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0096] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0097] The buffer region 20 is a region of a first conductivity type provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, the buffer region 20 is, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type. Note that the buffer region 20 may be omitted.

[0098] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The collector region 22 has the second conductivity type. In this example, the collector region 22 is, for example, a P+ type.

[0099] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0100] The base region 14 is a region of the second conductivity type provided above the drift region 18. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0101] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0102] The accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. The accumulation region 16 in this example is, for example, an N+ type. However, the accumulation region 16 does not necessarily have to be provided.

[0103] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose of ion implantation into the accumulation region 16 is 1.0E+12 cm －２ Above, 1.0E+13cm －２ The ion implantation dose of the accumulation region 16 may be 3.0E+12 cm －２ Above, 6.0E + 12cm －２ By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0104] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion may be an active trench portion 122 included in the active portion 120. Each trench portion is provided from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions to reach the drift region 18. The trench portion penetrating the doped region does not necessarily mean that the trench portion is formed in the order of forming the doped region and then the trench portion. The trench portion penetrating the doped region also includes a trench portion formed after the trench portion is formed.

[0105] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0106] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0107] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered on the front surface 21 with an interlayer insulating film 38.

[0108] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Similarly, contact holes 55 and 56 may be provided penetrating the interlayer insulating film 38. The interlayer insulating film 38 may be a borophosphosilicate glass (BPSG) film, a borosilicate glass (BSG) film, a phosphosilicate glass (PSG) film, an HTO film, or a laminate of these materials. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited to this.

[0109] The active contact portion 124 is provided in the interlayer insulating film 38 above the active trench portion 122. The active contact portion 124 may include a first active contact portion 1241 and a second active contact portion 1242 (described later). The first active contact portion 1241 may be in contact with the upper surface of the mesa portion of the semiconductor substrate 10. The first active contact portion 1241 may have a contact hole 54 and a metal layer filled in the contact hole 54. The contact hole 54 may be filled with the same material as the emitter electrode 52, or may be filled with a material different from that of the emitter electrode 52. The active contact portion 124 may include a barrier metal film 1243 provided in the contact hole 54 and in contact with the semiconductor substrate 10. The active contact portion 124 may include a plug portion 1244 in contact with the barrier metal film 1243 and provided to fill the contact hole 54. The barrier metal film 1243 of the active contact portion 124 may contain titanium or a titanium compound, etc. The plug portion 1244 of the active contact portion 124 may contain a plug metal such as tungsten. An alloy layer may be formed in contact with the barrier metal film 1243, and the alloy layer may be made of a metal contained in the barrier metal film 1243 and a layer such as the semiconductor substrate 10 below the contact hole 54. A region with a high impurity concentration may be formed in the layer such as the semiconductor substrate 10 below the contact hole 54 at a location in contact with the alloy layer. The active contact portion 124 of this example is an example of a main region contact portion 224 provided in the main region 220, which will be described later.

[0110] The back side lifetime control region 151 may be provided in the transistor portion 70. However, the back side lifetime control region 151 may be omitted. The back side lifetime control region 151 is a region in which a lifetime killer is intentionally formed by, for example, injecting impurities into the semiconductor substrate 10. In one example, the back side lifetime control region 151 is formed by injecting helium into the semiconductor substrate 10. The back side lifetime control region 151 may also be formed by injecting protons. By providing the back side lifetime control region 151, it is possible to reduce the turn-off time and suppress the tail current, thereby reducing losses during switching.

[0111] The lifetime killer is a carrier recombination center. The lifetime killer may be a lattice defect. For example, the lifetime killer may be a vacancy, a divacancy, a complex defect of these with an element constituting the semiconductor substrate 10, or a dislocation. The lifetime killer may also be a rare gas element such as helium or neon, or a metal element such as platinum. Electron beams or protons may be used to form the lattice defects.

[0112] The lifetime killer concentration is the concentration of carrier recombination centers. The lifetime killer concentration may be the concentration of lattice defects. For example, the lifetime killer concentration may be the concentration of vacancies such as vacancies and divacancies, the concentration of complex defects formed between these vacancies and elements constituting the semiconductor substrate 10, or the concentration of dislocations. The lifetime killer concentration may also be the chemical concentration of a rare gas element such as helium or neon, or the chemical concentration of a metal element such as platinum.

[0113] The back surface-side lifetime control region 151 may be formed by implantation from the back surface 23 side. This makes it easier to avoid any influence on the front surface 21 side of the semiconductor device 100. For example, the back surface-side lifetime control region 151 is formed by irradiating helium or protons from the back surface 23 side. Here, whether the back surface-side lifetime control region 151 is formed by implantation from the front surface 21 side or the back surface 23 side can be determined by acquiring the state of the front surface 21 side by the SR method or by measuring leakage current.

[0114] 2A shows an enlarged view of the top surface of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a transistor section 70 and a diode section 80. The configuration in this figure may be arranged periodically or continuously in the +X-axis direction and the −X-axis direction.

[0115] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17, which are provided inside the front surface 21 side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of an active trench portion 122.

[0116] The dummy trench portion 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.

[0117] The semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor section 70 of this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80. However, the semiconductor device 100 does not necessarily have to include the boundary section 90.

[0118] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The boundary portion 90 in this example does not have an emitter region 12. In one example, the trench portion in the boundary portion 90 is a dummy trench portion 30. The boundary portion 90 in this example is arranged so that both ends in the X-axis direction are dummy trench portions 30.

[0119] The contact holes 54 are provided above the base region 14 in the diode section 80. The contact holes 54 are provided above the contact regions 15 in the boundary section 90. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction.

[0120] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0121] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a well region 17 on the negative side in the Y-axis direction.

[0122] The emitter region 12 is provided in the mesa portion 71, but may not be provided in the mesa portion 81 or the mesa portion 91. The contact region 15 is provided in the mesa portion 71 and the mesa portion 91, but may not be provided in the mesa portion 81.

[0123] 2B shows an example of the b-b' cross section in FIG. 2A. The semiconductor device 100 of this example includes a back surface-side lifetime control region 151 and a front surface-side lifetime control region 152. However, the semiconductor device 100 does not necessarily have to include either the back surface-side lifetime control region 151 or the front surface-side lifetime control region 152. The semiconductor device 100 of this example includes a collector region 22 and a cathode region 82 on the back surface 23 side of the buffer region 20.

[0124] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross sections, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

[0125] The accumulation region 16 is provided in the transistor section 70 and the diode section 80. In this example, the accumulation region 16 is provided on the entire surface of the transistor section 70 and the diode section 80. However, the accumulation region 16 does not have to be provided in the diode section 80.

[0126] The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below the boundary section 90 in this example.

[0127] The back side lifetime control region 151 may be provided in both the transistor portion 70 and the diode portion 80, or may be provided only in the transistor portion 70, or may be provided only in the diode portion 80. This enables the semiconductor device 100 of this example to speed up the turn-off operation of the transistor portion 70 or the reverse recovery operation in the diode portion 80, thereby further improving switching loss. The back side lifetime control region 151 may be formed by a method similar to that used for the back side lifetime control region 151 of the other embodiments.

[0128] The front surface side lifetime control region 152 is provided closer to the front surface 21 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the front surface side lifetime control region 152 is provided in the drift region 18. The front surface side lifetime control region 152 may be provided in both the transistor portion 70 and the diode portion 80, or may be provided only in the diode portion 80. The front surface side lifetime control region 152 is provided in the diode portion 80 and the boundary portion 90, and may not be provided in part of the transistor portion 70. The front surface side lifetime control region 152 can suppress hole injection from the transistor portion 70 and the diode portion 80, thereby reducing reverse recovery loss.

[0129] The front surface side lifetime control region 152 may be formed by any method among the methods for forming the back surface side lifetime control region 151. The elements, doses, etc. for forming the back surface side lifetime control region 151 and the front surface side lifetime control region 152 may be the same or different.

[0130] The front surface side lifetime control region 152 is provided extending from the diode section 80 to the transistor section 70. The front surface side lifetime control region 152 may be formed by introducing a lifetime killer from the front surface 21 of the semiconductor substrate 10. The front surface side lifetime control region 152 may also be formed by irradiation from the back surface 23 side of the semiconductor substrate 10. In this example, the front surface side lifetime control region 152 is provided below the gate trench section 40. When a particle beam or the like for forming the front surface side lifetime control region 152 passes through the MOS gate structure of the semiconductor device 100, defects may occur at the interface between the gate oxide film and the semiconductor substrate.

[0131] The semiconductor device 100 may be a power semiconductor device for controlling power, etc. The semiconductor device 100 of this example may have a vertical semiconductor structure including a backside metal layer on the backside 23 side of the semiconductor substrate 10. However, the semiconductor device 100 may also have a lateral semiconductor structure that does not include a metal layer on the backside 23 side.

[0132] In this example, an RC-IGBT with a trench gate structure is described as an example of the semiconductor device 100. However, the semiconductor device 100 may be a semiconductor device with a planar gate structure, or may be another semiconductor device such as a diode. The semiconductor device 100 may include an N-channel MOSFET or a P-channel MOSFET.

[0133] 3 shows an example of a top view of the semiconductor device 100. The semiconductor device 100 of this example includes a temperature-sensing unit 180. In this example, only some of the components of the semiconductor device 100 are shown, and some other components are omitted.

[0134] The semiconductor substrate 10 has edges 102 in a top view. The semiconductor substrate 10 of this example has two pairs of edges 102 that face each other in a top view. In this example, the X-axis and the Y-axis are parallel to either of the edges 102.

[0135] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region through which a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode 52 is provided above the active portion 120, but is not shown in the figure.

[0136] The active section 120 may be provided with at least one of a transistor section 70 including a transistor element such as an IGBT and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 3 , the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front surface 21 of the semiconductor substrate 10. In another example, the active section 120 may be provided with only one of the transistor section 70 and the diode section 80. That is, the active section 120 may be provided with only the transistor section 70 as shown in FIG. 1A , or may be provided with both the transistor section 70 and the diode section 80 as shown in FIG. 2A , or may be provided with only the diode section 80.

[0137] In this example, the region where the transistor section 70 is disposed is marked with the symbol "I," and the region where the diode section 80 is disposed is marked with the symbol "F." The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of the gate trench section 40 and the dummy trench section 30.

[0138] The diode section 80 may be a region obtained by projecting a cathode region 82 provided on the rear surface 23 of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The region obtained by projecting the cathode region 82 onto the upper surface of the semiconductor substrate 10 may be located inside the diode section 80. A P+ type collector region 22 may be provided in a region of the rear surface 23 of the semiconductor substrate 10 other than the cathode region 82.

[0139] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. When viewed from above, the edge termination structure 140 is provided between the active section 120 and the edge 102. The edge termination structure 140 relieves electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active section 120.

[0140] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example includes a gate pad 112, a sense electrode 114, an anode pad 116, and a cathode pad 118. Each pad may be located near an edge 102 of the semiconductor substrate 10. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode 52 in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0141] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 in the active portion 120. The semiconductor device 100 may include a gate wiring that connects the gate pad 112 and the gate trench portion 40. The gate wiring may be configured by either the gate metal layer 50 or the connection portion 25, or by combining both appropriately.

[0142] The sense electrode 114 is electrically connected to a current sense unit 115 provided below the sense electrode 114. The sense electrode 114 detects the current flowing in the current sense unit 115. The current sense unit 115 detects the current flowing in the transistor unit 70. The current sense unit 115 has a structure corresponding to the transistor unit 70. The current flowing in the current sense unit 115 is smaller than the current flowing in the transistor unit 70. A current proportional to the current flowing in the transistor unit 70 may flow in the current sense unit 115, simulating the operation of the transistor unit 70. The ratio of the current flowing in the current sense unit 115 to the current flowing in the transistor unit 70 is appropriately set. The current flowing in the transistor unit 70 can be monitored by using the current sense unit 115.

[0143] The temperature sensing unit 180 is provided on or inside the semiconductor substrate 10. In this example, the temperature sensing unit 180 is provided between the transistor units 70 in the center of the semiconductor device 100. The temperature sensing unit 180 detects the temperature of the active unit 120. The temperature sensing unit 180 may include a diode formed of monocrystalline or polycrystalline silicon. The temperature sensing unit 180 is used to detect the temperature of the semiconductor device 100 and protect the semiconductor chip (semiconductor substrate 10) from overheating. The temperature sensing unit 180 is connected to a constant current source. When the temperature of the semiconductor device 100 changes, the forward voltage of the current flowing through the temperature sensing unit 180 changes. The semiconductor device 100 can detect the temperature based on the change in the forward voltage of the temperature sensing unit 180.

[0144] The anode pad 116 is electrically connected to the temperature-sensitive anode region 182 of the temperature-sensitive unit 180. The anode pad 116 is electrically connected to the temperature-sensitive anode region 182 of the temperature-sensitive unit 180 by an anode wiring part 117 that is electrically connected to the temperature-sensitive anode region 182. The temperature-sensitive anode region 182 will be described later.

[0145] The cathode pad 118 is electrically connected to a temperature-sensitive cathode region 181 of the temperature-sensitive unit 180. The cathode pad 118 is electrically connected to the temperature-sensitive cathode region 181 of the temperature-sensitive unit 180 by a cathode wiring part 119 that is electrically connected to the temperature-sensitive cathode region 181. The temperature-sensitive cathode region 181 will be described later.

[0146] FIG. 4A shows an example of a cross section of a semiconductor device 100 including a temperature-sensitive portion 180. The cross section in this example is a cross section taken along line c-c' in FIG. 3, which is an XZ plane passing through the contact hole 54 in the active portion 120. The temperature-sensitive portion 180 includes a temperature-sensitive diode 183 and a temperature-sensitive contact portion 188. The interlayer insulating film 38 may include a first interlayer insulating film 36 and a second interlayer insulating film 37. The interlayer insulating film 38 may be thinner than the emitter electrode 52. The first interlayer insulating film 36 may be thinner than the emitter electrode 52, and the second interlayer insulating film 37 may be thinner than the emitter electrode 52. The temperature-sensitive contact portion 188 may include a barrier metal film 1882 and a plug portion 1884. The barrier metal film 1882 and the plug portion 1884 of the temperature-sensitive contact portion 188 will be described later.

[0147] The temperature-sensitive diode 183 is provided above the semiconductor substrate 10. "Above" may refer to the positive direction of the Z-axis relative to the front surface 21 of the semiconductor substrate 10. The temperature-sensitive diode 183 may be a PN diode including a temperature-sensitive anode region 182 provided above the semiconductor substrate 10 and a temperature-sensitive cathode region 181 provided above the semiconductor substrate 10 and in contact with the temperature-sensitive anode region 182. The temperature-sensitive cathode region 181 may be formed of an N-type semiconductor and function as the cathode of the PN diode. The temperature-sensitive anode region 182 may be formed of a P-type semiconductor and function as the anode of the PN diode. The material of the temperature-sensitive cathode region 181 and the temperature-sensitive anode region 182 may be a polycrystalline semiconductor, for example, polysilicon.

[0148] A well region 17 may be provided in the semiconductor substrate 10 below the temperature-sensitive diode 183. The well region 17 provided below the temperature-sensitive diode 183 may be the same as the well region 17 provided on the peripheral side of the active portion 120 in FIG. 1A and may be formed in the same process.

[0149] The temperature-sensitive contact portion 188 is provided in the interlayer insulating film 38 above the temperature-sensitive diode 183. The interlayer insulating film 38 in which the temperature-sensitive contact portion 188 is provided may be the first interlayer insulating film 36. The temperature-sensitive contact portion 188 may have a contact hole 58 and a metal layer filled inside the contact hole 58. The sidewall of the temperature-sensitive contact portion 188 may be in contact with the interlayer insulating film 38 from the upper end to the lower end. In other words, the contact hole 58 may be provided to penetrate the first interlayer insulating film 36.

[0150] The contact width Wd at which the temperature-sensitive contact portion 188 contacts the temperature-sensitive diode 183 may be larger than the contact width of the active contact portion 124. The contact width Wd of the temperature-sensitive contact portion 188 may be larger than a first active contact width Wt1 of the first active contact portion 1241. The first active contact width Wt1 may be the width at which the first active contact portion 1241 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10. The active contact portion 124 in this example is an example of a main region contact portion 224 provided in the main region 220, which will be described later.

[0151] The cathode wiring portion 119 is electrically connected to the temperature-sensitive cathode region 181 via the contact hole 58. The cathode wiring portion 119 may be formed of a metal material. The cathode wiring portion 119 may be formed of the same material as the emitter electrode 52. The temperature-sensitive cathode region 181 may be electrically connected to the cathode pad 118 by the cathode wiring portion 119.

[0152] The anode wiring portion 117 is electrically connected to the temperature-sensitive anode region 182 via the contact hole 58. The anode wiring portion 117 may be made of a metal material. The anode wiring portion 117 may be made of the same material as the emitter electrode 52. The temperature-sensitive anode region 182 may be electrically connected to the anode pad 116 via the anode wiring portion 117.

[0153] The first interlayer insulating film 36 may be provided above the temperature sensitive diode 183. The first interlayer insulating film 36 may be a BPSG film, a BSG film, a PSG film, an HTO film, or a laminate of these materials.

[0154] The second interlayer insulating film 37 may be provided between the temperature sensing diode 183 and the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The second interlayer insulating film 37 may be any oxide film. The second interlayer insulating film 37 may be the same thermal oxide film as the gate insulating film 42 or the dummy insulating film 32. The second interlayer insulating film 37 may be a BPSG film, a BSG film, a PSG film, or an HTO film.

[0155] 4B shows another example of a cross section of the semiconductor device 100 including the temperature sensitive portion 180. The cross section in this example is an XZ plane passing through the contact hole 56 in the active portion 120. The active contact portion 124 may include a second active contact portion 1242.

[0156] The second active contact portion 1242 may be in contact with the active trench portion 122. In this example, the second active contact portion 1242 is in contact with the dummy trench portion 30. The second active contact portion 1242 may have a contact hole 56 and a metal layer filled inside the contact hole 56. The inside of the contact hole 56 may be filled with the same material as the emitter electrode 52, or may be filled with a material different from the emitter electrode 52.

[0157] The contact width Wd at which the temperature-sensitive contact portion 188 contacts the temperature-sensitive diode 183 may be larger than the contact width of the active contact portion 124. The contact width Wd of the temperature-sensitive contact portion 188 may be larger than a second active contact width Wt2 of the second active contact portion 1242. The second active contact width Wt2 may be the width at which the second active contact portion 1242 contacts the active trench portion 122.

[0158] 4C shows a cross section of a modified example of the semiconductor device 100 including the temperature-sensitive portion 180. The semiconductor device 100 of this example differs from the embodiment of FIG. 4A in that the temperature-sensitive portion 180 has a temperature-sensitive trench contact portion 1885 and the active portion 120 has an active trench contact portion 1245. In this example, differences from the embodiment of FIG. 4A will be particularly described, and the rest may be the same as the embodiment of FIG. 4A. That is, the contact width of the temperature-sensitive contact portion 188 may be larger than the contact width of the active contact portion 124.

[0159] The active portion 120 may have a plurality of active trench contact portions 1245 extending from the upper surface of the interlayer insulating film 38 to below the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The active trench contact portions 1245 are an example of the active contact portions 124. The active trench contact portions 1245 are portions that are deeper toward the back surface 23 of the semiconductor substrate 10 than the front surface 21. The active contact portions 124 in this example are an example of the main region contact portions 224 provided in the main region 220, which will be described later. The active trench contact portions 1245 in this example are an example of the main region trench contact portions 2245.

[0160] In the depth direction of the semiconductor substrate 10, the extension depth Dd of the temperature-sensitive trench contact portion 1885 extending from the upper surface of the temperature-sensitive diode in the depth direction of the semiconductor substrate may be the same as the extension depth Dt of the multiple active trench contact portions 1245 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.

[0161] The contact width Wtd at which the temperature-sensitive trench contact portion 1885 contacts the temperature-sensitive diode 183 may be larger, the same as, or smaller than the contact width Wtt1 of the first active contact portion 1241. The contact width Wtd of the temperature-sensitive trench contact portion 1885 may be the width at which the temperature-sensitive trench contact portion 1885 contacts the upper surface of the temperature-sensitive diode 183. The first active contact width Wtt1 may be the width at which the first active contact portion 1241 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10. The embodiment shown in FIG. 4B may also have the active trench contact portion 1245 and the temperature-sensitive trench contact portion 1885, as in this example.

[0162] As described above, in the semiconductor device 100 of this example, the contact width of the temperature-sensitive contact portion 188 is larger than the contact width of the active contact portion 124. By making the contact width of the temperature-sensitive contact portion 188 larger than the contact width of the active contact portion 124, the semiconductor device 100 can be manufactured stably and stable characteristics can be obtained even when the semiconductor device 100 is miniaturized. In this case, the active contact portion 124 and the temperature-sensitive contact portion 188 may be formed in different processes.

[0163] FIG. 5A shows a cross section of a modified example of the semiconductor device 100 including a temperature-sensing portion 180. The semiconductor device 100 of this example differs from the embodiment of FIG. 4A in that it includes a recess region 194. In this example, differences from the embodiment of FIG. 4A will be particularly described, and the remaining features may be the same as the embodiment of FIG. 4A. That is, the contact width of the temperature-sensing contact portion 188 may be larger than the contact width of the active contact portion 124. The active contact portion 124 of this example is an example of a main region contact portion 224 provided in the main region 220, which will be described later.

[0164] The temperature sensing portion 180 may have a recess region 194 in which a depression is provided in the upper surface of the semiconductor substrate 10. The temperature sensing diode 183 may be provided in the recess region 194. The temperature sensing diode 183 may be provided above an insulating film 196 in the recess region 194. The insulating film 196 may be any oxide film. The insulating film 196 may be the same thermal oxide film as the edge termination structure 140, the gate insulating film 42, the dummy insulating film 32, or the like. The insulating film 196 may be a BPSG film, a BSG film, a PSG film, or an HTO film.

[0165] In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the active portion 120 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 194. The height positions being the same may include the height positions being approximately (substantially) the same. The height positions being approximately (substantially) the same may mean that the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the active portion 120 and the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the recess region 194 are within 20% of the average of both distances, or may be within 10% of the average. When the height positions of the upper surface of the interlayer insulating film 38 in the active portion 120 and the upper surface of the interlayer insulating film in the recess region 194 are approximately the same, the active contact portion 124 and the temperature-sensitive contact portion 188 can be formed simultaneously by the same etching process. That is, if the upper surfaces of the interlayer insulating film 38 in the active portion 120 and the interlayer insulating film 38 in the recess region 194 are both at the same height from the front surface 21 of the semiconductor substrate 10, there is no deviation in the focus of exposure during the photolithography process. This allows for smaller dimensional tolerances for the interlayer insulating film, emitter electrode, and the like. Furthermore, the active contact portion 124 and the temperature-sensitive contact portion 188 can be formed with the same dimensional tolerances. This allows for easier manufacturing with fewer steps than when each contact portion is formed in separate steps. However, if the contact width of the temperature-sensitive contact portion 188 is larger than the contact width of the active contact portion 124, the active contact portion 124 and the temperature-sensitive contact portion 188 may be formed in different steps. This example may also have the active trench contact portion 1245 and the temperature-sensitive trench contact portion 1885.

[0166] FIG. 5B shows a cross section of a modified example of the semiconductor device 100 including the temperature-sensing portion 180. The semiconductor device 100 of this example differs from the embodiment of FIGS. 4A and 5A in that the temperature-sensing portion 180 has a housing portion 198. In this example, differences from the embodiment of FIGS. 4A and 5A will be particularly described, and the remaining features may be the same as the embodiment of FIGS. 4A and / or 5A. That is, the contact width of the temperature-sensing contact portion 188 may be larger than the contact width of the active contact portion 124. The active contact portion 124 of this example is an example of the main region contact portion 224 provided in the main region 220, which will be described later.

[0167] The housing portion 198 is provided below the temperature-sensitive contact portion 188. The material of the housing portion 198 may be the same as the material of the first interlayer insulating film 36, the same as the material of the second interlayer insulating film 37, or the same as the material of the temperature-sensitive diode 183. The detailed configuration of the housing portion 198 will be described later.

[0168] 6A shows an example of an enlarged cross-sectional view of the semiconductor device 100. This figure shows a region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10.

[0169] A bottom corner 1880 of the temperature sensitive contact portion 188 may be in contact with the temperature sensitive diode 183. The bottom corner 1880 of the temperature sensitive contact portion 188 may be the intersection of the bottom surface of the temperature sensitive contact portion 188 and the side surface of the temperature sensitive contact portion 188. The bottom corner 1880 being in contact with the temperature sensitive diode 183 may be in contact with the temperature sensitive diode 183 on the top surface of the temperature sensitive diode 183, on the side surface of the temperature sensitive diode 183, or in an internal region of the temperature sensitive diode 183. In this example, the bottom corner 1880 is in contact with the temperature sensitive diode 183 on the top surface of the temperature sensitive diode 183.

[0170] The temperature-sensitive contact portion 188 in this example has two bottom corners 1880. One of the two bottom corners 1880 may be in contact with the temperature-sensitive diode 183. The other of the two bottom corners 1880 may or may not be in contact with the housing portion 198. The temperature-sensitive contact portion 188a in this example has one bottom corner 1880a in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183, and the other bottom corner 1880b in contact with the housing portion 198.

[0171] The bottom surface of the temperature-sensitive contact portion 188 may be in contact with the housing portion 198. The bottom surface of the temperature-sensitive contact portion 188 may be the surface between two bottom corner portions 1880 of the temperature-sensitive contact portion 188. The bottom surface of the temperature-sensitive contact portion 188 in contact with the housing portion 198 may be in contact with the housing portion 198 at the top surface of the housing portion 198, or may be in contact with the housing portion 198 in an internal region of the housing portion 198. In this example, the bottom surface of the temperature-sensitive contact portion 188 is in contact with the housing portion 198 at the top surface of the housing portion 198.

[0172] The bottom surface of the temperature-sensitive contact portion 188 may be in contact with the temperature-sensitive diode 183 and the housing portion 198. In the present example, one bottom corner portion 1880a of the temperature-sensitive contact portion 188a is in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183, and the other bottom corner portion 1880b is in contact with the housing portion 198, so that the bottom surface of the temperature-sensitive contact portion 188a is in contact with the temperature-sensitive diode 183 and the housing portion 198.

[0173] The temperature-sensitive diode 183 may contact the bottom surface of the temperature-sensitive contact portion 188 from the bottom corner 1880 to an area of ​​10% to 40% of the bottom surface of the temperature-sensitive contact portion 188. That is, the ratio of the area of ​​the surface of the bottom surface of the temperature-sensitive contact portion 188 that contacts the temperature-sensitive diode 183 to the area of ​​the bottom surface of the temperature-sensitive contact portion 188 may be 10% to 40%. Referring to FIG. 5A , length L1 is the length of the bottom surface of the temperature-sensitive contact portion 188 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the temperature-sensitive contact portion 188 that contacts the temperature-sensitive diode 183 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the temperature sensitive diode 183 contacts the bottom surface of the temperature sensitive contact portion 188a from the bottom corner 1880a to an area that is 25% of the bottom surface of the temperature sensitive contact portion 188. In other words, in this example, the ratio of length L2 to length L1 is 25%.

[0174] In the above explanation, the bottom surface, bottom corners 1880a, and bottom corners 1880b of the temperature-sensitive contact portion 188a that contact the temperature-sensitive cathode region 181 have been given as examples, but the same may be true for the temperature-sensitive contact portion 188b that contacts the temperature-sensitive anode region 182. That is, the bottom corners 1880 of the temperature-sensitive contact portion 188b may contact the temperature-sensitive diode 183, the bottom surface of the temperature-sensitive contact portion 188b may contact the housing portion 198, the bottom surface of the temperature-sensitive contact portion 188b may contact the temperature-sensitive diode 183 and the housing portion 198, and the temperature-sensitive diode 183 may contact the bottom surface of the temperature-sensitive contact portion 188b from the bottom corners 1880 over an area of ​​10% to 40% of the bottom surface of the temperature-sensitive contact portion 188b. Furthermore, the lengths L1 and L2 of the temperature sensitive contact portion 188b may be the same as those of the temperature sensitive contact portion 188a.

[0175] In this example, the temperature-sensitive contact portion 188 is provided such that the bottom corners 1880 contact the temperature-sensitive diode 183 and the bottom surface contacts the housing portion 198. This ensures reliable electrical connection between the anode pad 116, the cathode pad 118, and the temperature-sensitive diode 183. If the plug portion 1884 and the barrier metal film 1882 near the center of the bottom surface of the temperature-sensitive contact portion 188 are over-etched during the etch-back process of the plug portion 1884, voids may be generated inside the temperature-sensitive contact portion 188. Even in this case, the electrical connection can be ensured by the barrier metal film 1882 and / or the plug portion 1884 remaining at the bottom corners 1880 of the temperature-sensitive contact portion 188. The barrier metal film 1882 and the plug portion 1884 will be described later.

[0176] The temperature-sensitive contact portion 188 of this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the temperature-sensitive contact portion near the center of its bottom surface, the effect on the electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 at the bottom corners 1880 is suppressed. This improves the yield of semiconductor devices 100 with desired characteristics. The temperature-sensitive portion 180 of this example ensures electrical connection between the temperature-sensitive contact portion 188 and the temperature-sensitive diode 183 through the bottom corners 1880 rather than the bottom center of the temperature-sensitive contact portion 188. This ensures stable quality and improved yield, even if a void forms in the region near the center of the temperature-sensitive contact portion 188 that contacts the housing portion 198.

[0177] The temperature-sensitive contact portion 188 may have a barrier metal film 1882 and a plug portion 1884. In this example, the barrier metal film 1882 and the plug portion 1884 are formed of different materials, but they may also be formed of the same material.

[0178] The barrier metal film 1882 may be provided at the bottom corners 1880 of the temperature-sensitive contact portion 188. In this example, the barrier metal film 1882 is provided over the entire side and bottom surfaces of the temperature-sensitive contact portion 188, but this is not limiting. The barrier metal film 1882 may be provided so as to cover at least the bottom corners 1880, or may be provided so as not to cover the center portion of the bottom surface of the temperature-sensitive contact portion 188. The barrier metal film 1882 may extend beyond the contact hole 58 and extend above the first interlayer insulating film 36. The material of the barrier metal film 1882 may be titanium, a titanium compound, or the like.

[0179] The plug portion 1884 may be provided in contact with the inner side of the barrier metal film 1882. In this example, the plug portion 1884 is provided by filling the temperature-sensitive contact portion 188, but this is not limiting. The plug portion 1884 may be provided in a portion of the temperature-sensitive contact portion 188, or may extend beyond the contact hole 58 and extend above the first interlayer insulating film 36. When the plug portion 1884 is provided in a portion of the temperature-sensitive contact portion 188, the remaining region of the temperature-sensitive contact portion 188 may be filled with the same material as the anode wiring portion 117 or the cathode wiring portion 119. The material of the plug portion 1884 may be a plug metal such as tungsten.

[0180] The side surfaces of the temperature sensitive diode 183 may contact the side surfaces of the housing portion 198. In the temperature sensitive diode 183 of this example, the side surfaces of the temperature sensitive cathode region 181 and the temperature sensitive anode region 182 contact the side surfaces of the housing portion 198.

[0181] The upper surface of the second interlayer insulating film 37 may be in contact with the lower surface of the temperature-sensitive diode 183 and the lower surface of the housing portion 198. In this example, the upper surface of the second interlayer insulating film 37 is in contact with the lower surface of the housing portion 198 provided in contact with the temperature-sensitive cathode region 181, the lower surface of the temperature-sensitive cathode region 181, the lower surface of the temperature-sensitive anode region 182, and the lower surface of the housing portion 198 provided in contact with the temperature-sensitive anode region 182.

[0182] The housing portion 198 may be a region of the first interlayer insulating film 36 that is provided below the temperature-sensitive contact portion 188. The housing portion 198 may be formed in the process of providing the first interlayer insulating film 36, and may be formed from the same material as the first interlayer insulating film 36. When the housing portion 198 is formed as a region of the first interlayer insulating film 36 that is provided below the temperature-sensitive contact portion 188, the housing portion 198 is a virtual region, as shown by the dotted line in FIG. 6A . In other words, the housing portion 198 may be formed integrally as part of the first interlayer insulating film 36.

[0183] 6B shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows a region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the example of FIG. 6A in that the shapes of the first interlayer insulating film 36 and the second interlayer insulating film 37 are different. In this example, differences from the example of FIG. 6A will be particularly described, and the rest may be the same as the example of FIG. 6A.

[0184] The second interlayer insulating film 37 may have a recess 200 on its upper surface. The temperature-sensitive diode 183 may be provided in the recess 200 in the second interlayer insulating film 37. The recess 200 may be formed by etching the upper surface of the second interlayer insulating film 37. The upper surface of the temperature-sensitive diode 183 in this example may be flush with the upper surface of the recess 200, or may be lower than the upper surface of the recess 200.

[0185] The housing portion 198 may be the second interlayer insulating film 37 provided above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the second interlayer insulating film 37 and may be formed of the same material as the second interlayer insulating film 37. When the housing portion 198 is formed as the second interlayer insulating film 37, the housing portion 198 is a virtual region, as indicated by the dotted line in FIG. 6B . That is, the housing portion 198 may be formed integrally with the second interlayer insulating film 37. Note that if the upper surface of the temperature sensitive diode 183 is higher than the upper surface of the recess 200, the lower end of the temperature sensitive contact portion 188 does not reach the second interlayer insulating film 37 but is located in the first interlayer insulating film 36. The housing portion 198 may be considered to be part of the first interlayer insulating film 36, or may be considered to be made up of both the first interlayer insulating film 36 and the second interlayer insulating film 37. Furthermore, even if the portion of the second interlayer insulating film 37 that does not have the recess 200 is narrow and the lower end of the temperature-sensitive contact portion 188 is located at the boundary between the first interlayer insulating film 36 and the second interlayer insulating film 37, the housing portion 198 may be considered to be part of the second interlayer insulating film 37, or may be considered to be made up of both the first interlayer insulating film 36 and the second interlayer insulating film 37.

[0186] FIG. 6C shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows a region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIGS. 6A and 6B in that a housing portion 198 is provided separately from the first interlayer insulating film 36 and the second interlayer insulating film 37. In this example, differences from the embodiment of FIGS. 6A and 6B will be particularly described, and the rest may be the same as the embodiment of FIGS. 6A and / or 6B. The housing portion 198 of this example is provided in the region of the first interlayer insulating film 36 corresponding to the housing portion 198 in FIG. 6A, but may also be provided in the region of the second interlayer insulating film 37 corresponding to the housing portion 198 in FIG. 6B.

[0187] The housing portion 198 may have polysilicon of a different conductivity type from that of the contact region 300 of the temperature-sensitive diode 183. The contact region 300 of the temperature-sensitive diode 183 may be the temperature-sensitive cathode region 181 or the temperature-sensitive anode region 182 of the temperature-sensitive diode 183 with which the housing portion 198 is in contact. The housing portion 198a in this example is in contact with the temperature-sensitive cathode region 181. Therefore, the housing portion 198a may have polysilicon of a different conductivity type from that of the temperature-sensitive cathode region 181, which is the contact region 300 of the temperature-sensitive diode 183. That is, the housing portion 198a may have P-type polysilicon or undoped polysilicon. The housing portion 198b in this example is in contact with the temperature-sensitive anode region 182. Therefore, the housing portion 198b may have polysilicon of a different conductivity type from that of the temperature-sensitive anode region 182, which is the contact region 300 of the temperature-sensitive diode 183. That is, the housing portion 198b may include N-type polysilicon or undoped polysilicon.

[0188] In the present example, the temperature sensitive contact portion 188 is in contact with the temperature sensitive diode 183 at a bottom corner 1880 of the temperature sensitive contact portion 188. In the present example, the temperature sensitive contact portion 188 is provided such that the bottom surface of the temperature sensitive contact portion 188 is in contact with the housing portion 198. The housing portion 198 and a contact region 300 of the temperature sensitive diode 183 with the housing portion 198 may have the same potential.

[0189] When the housing portion 198 and the contact region 300 of the temperature-sensitive diode 183 are at the same potential, no current flows between the housing portion 198 and the temperature-sensitive diode 183, and the operation of the temperature-sensitive diode 183 is not affected by the housing portion 198. As an example, if the housing portion 198a has P-type polysilicon, which is a different conductivity type from the temperature-sensitive cathode region 181, the housing portion 198a and the temperature-sensitive cathode region 181 have the same potential, so substantially no current flows through the PN junction at the contact interface. Therefore, the operation of the temperature-sensitive diode 183 is not affected by the housing portion 198. Similarly, even if the housing portion 198b has N-type polysilicon, which is a different conductivity type from the temperature-sensitive anode region 182, the housing portion 198b and the temperature-sensitive anode region 182 have the same potential, so the PN junction at the contact interface does not function and does not impede the operation of the temperature-sensitive diode 183.

[0190] The housing portion 198 may have the same conductivity type as the contact region 300 of the temperature sensitive diode 183 and may include polysilicon with a lower doping concentration than the contact region 300. The housing portion 198a in this example is in contact with the temperature sensitive cathode region 181. Therefore, the housing portion 198a may have the same conductivity type as the temperature sensitive cathode region 181, which is the contact region 300 of the temperature sensitive diode 183, and may include polysilicon with a lower doping concentration than the temperature sensitive cathode region 181. In other words, the housing portion 198a may include N-type polysilicon. The housing portion 198b in this example is in contact with the temperature sensitive anode region 182. Therefore, the housing portion 198b may have the same conductivity type as the temperature sensitive anode region 182, which is the contact region 300 of the temperature sensitive diode 183, and may include polysilicon with a lower doping concentration than the temperature sensitive anode region 182. In other words, the housing portion 198b may include P-type polysilicon.

[0191] Even if the housing part 198 has the same conductivity type as the contact region 300 of the temperature sensitive diode 183, the doping concentration of the housing part 198 is lower than the doping concentration of the contact region 300, so the housing part 198 has little effect on the operation of the temperature sensitive diode 183. Therefore, the housing part 198 is unlikely to interfere with the operation of the temperature sensitive diode 183.

[0192] As described above, the housing portion 198a in contact with the temperature-sensitive cathode region 181 of the temperature-sensitive diode 183 may have P-type, non-doped, or N-type polysilicon, and the housing portion 198b in contact with the temperature-sensitive anode region 182 of the temperature-sensitive diode 183 may have N-type, non-doped, or P-type polysilicon. If the width of the polysilicon is narrow, a portion of the lower end of the temperature-sensitive contact portion 188 may overlap the interlayer insulating film 38. In this case, the housing portion 198 can be considered to be made of a mixture of polysilicon and the first interlayer insulating film 36 and / or the second interlayer insulating film 37.

[0193] 7A shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows a region of the temperature-sensitive portion 180 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIG. 6A in that the temperature-sensitive portion 180 has a temperature-sensitive trench contact portion 1885. In this example, differences from the embodiment of FIG. 6A will be particularly described, and the rest may be the same as the embodiment of FIG. 6A.

[0194] The temperature sensitive portion 180 may have a temperature sensitive trench contact portion 1885 extending from the upper surface of the interlayer insulating film 38 to a position below the upper surface of the temperature sensitive diode 183 in the depth direction of the semiconductor substrate 10. The temperature sensitive trench contact portion 1885 is an example of a temperature sensitive contact portion 188. The temperature sensitive trench contact portion 1885 is a portion that is deeper toward the back surface 23 than the surface of the temperature sensitive diode 183. In this example, a bottom corner portion 1880 of the temperature sensitive contact portion 188 contacts the temperature sensitive diode 183 on the side surface of the temperature sensitive diode 183.

[0195] The sidewall of the temperature-sensitive contact portion 188 may be in contact with the temperature-sensitive diode 183 and the first interlayer insulating film 36. The temperature-sensitive diode 183 may be in contact with the sidewall of the temperature-sensitive contact portion 188 from the bottom corner 1880 to an area of ​​10% to 90% of the sidewall of the temperature-sensitive contact portion. That is, the ratio of the area of ​​the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 to the area of ​​the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 may be 10% to 90%. Referring to FIG. 6A , length L3 is the length of the sidewall of the temperature-sensitive contact portion 188 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10, and length L4 is the length of the sidewall of the temperature-sensitive contact portion 188 that is in contact with the temperature-sensitive diode 183 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less. In this example, the temperature sensitive diode 183 contacts the sidewall of the temperature sensitive contact portion 188 from the bottom corner 1880 to 36% of the area of ​​the sidewall of the temperature sensitive contact portion 188. In other words, in this example, the ratio of length L4 to length L3 is 36%.

[0196] 7B shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This figure shows the region of the temperature-sensing portion 180 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIG. 7A in that the housing portion 198 is the second interlayer insulating film 37 provided above the semiconductor substrate 10. Other aspects may be the same as the embodiment of FIG. 7A.

[0197] 7C shows an enlarged cross-sectional view of a modified example of the semiconductor device 100. This view shows the region of the temperature-sensitive portion 180 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIGS. 7A and 7B in that the housing portion 198 includes polysilicon. Other aspects may be the same as the embodiment of FIGS. 7A and / or 7B.

[0198] FIG. 8A shows a cross section of a modified example of a semiconductor device 100 including a temperature-sensitive portion 180. The semiconductor device 100 of this example differs from the example of FIG. 4C in that the extension depth Dd of the temperature-sensitive trench contact portion 1885 extending from the top surface of the temperature-sensitive diode in the depth direction of the semiconductor substrate 10 may be shallower than the extension depth Dt of the multiple active trench contact portions 1245 extending from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, differences from the example of FIG. 4C will be particularly described, and the rest may be the same as the example of FIG. 4C . That is, the contact width of the temperature-sensitive contact portion 188 may be larger than the contact width of the active contact portion 124. The active contact portion 124 of this example is an example of a main region contact portion 224 provided in the main region 220, which will be described later. The active trench contact portion 1245 of this example is an example of a main region trench contact portion 2245.

[0199] In the depth direction of the semiconductor substrate 10, the extension depth Dd of the temperature-sensitive trench contact portion 1885 from the top surface of the temperature-sensitive diode in the depth direction of the semiconductor substrate may be shallower than the extension depth Dt of the multiple active trench contact portions 1245 from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. By making the extension depth Dd of the temperature-sensitive trench contact portion 1885 shallower than the extension depth Dt of the active trench contact portion 1245, it is possible to prevent the temperature-sensitive contact portion 188 from penetrating the temperature-sensitive diode 183 and extending through the second interlayer insulating film 37, thereby preventing insulation between the temperature-sensitive diode 183 and the semiconductor substrate 10 from being lost. Furthermore, because the active trench contact portion 1245 extends deeper than the temperature-sensitive trench contact portion 1885, the active contact portion 124 is formed sufficiently deep in the contact region 15, thereby preventing latch-up. The temperature-sensitive trench contact portion 1885 and the active trench contact portion 1245 can be formed in the same process, but may be formed in different processes.

[0200] The contact width Wtd at which the temperature-sensitive trench contact portion 1885 contacts the temperature-sensitive diode 183 may be larger than, the same as, or smaller than the contact width Wtt1 of the first active contact portion 1241. The contact width Wtd of the temperature-sensitive trench contact portion 1885 may be the width at which the temperature-sensitive trench contact portion 1885 contacts the upper surface of the temperature-sensitive diode 183. The first active contact width Wtt1 may be the width at which the first active contact portion 1241 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10.

[0201] FIG. 8B shows a cross section of a modified example of a semiconductor device 100 including a temperature-sensitive portion 180. The semiconductor device 100 of this example differs from the example of FIG. 8A in that the contact width of the temperature-sensitive contact portion 188 is the same as or narrower than the contact width of the active contact portion 124. The remaining configuration may be the same as the example of FIG. 8A. That is, the extension depth Dd of the temperature-sensitive trench contact portion 1885 may be shallower than the extension depth Dt of the active trench contact portion 1245. The active contact portion 124 of this example is an example of a main region contact portion 224 provided in the main region 220, which will be described later. The active trench contact portion 1245 of this example is an example of a main region trench contact portion 2245.

[0202] FIG. 8C shows a cross section of a modified example of the semiconductor device 100 including the temperature-sensitive portion 180. The semiconductor device 100 of this example differs from the embodiment of FIGS. 8A and 8B in that the extension depth Dd of the temperature-sensitive trench contact portion 1885 is substantially zero. The remaining features may be the same as the embodiment of FIGS. 8A and / or 8B. That is, the temperature-sensitive contact portion 188 does not extend to the temperature-sensitive diode 183, and the active trench contact portion 1245 may extend to a depth Dt. The active contact portion 124 of this example is an example of the main region contact portion 224 provided in the main region 220, which will be described later. The active trench contact portion 1245 of this example is an example of the main region trench contact portion 2245.

[0203] The examples shown in Figures 8A, 8B and 8C have been described as modified examples of Figure 4C, but are not limited to this. In the examples shown in Figures 5A, 7A, 7B or 7C, the extension depth Dd of the temperature-sensitive trench contact portion 1885 may be shallower than the extension depth Dt of the active trench contact portion 1245, and in the examples shown in Figures 5A, 6A, 6B or 6C, the temperature-sensitive contact portion 188 may not extend to the temperature-sensitive diode 183, and the active trench contact portion 1245 may extend to a depth Dt.

[0204] As described above, the semiconductor device 100 of the present invention may satisfy at least one of the following conditions: the contact width of the temperature-sensitive contact portion 188 is larger than the contact width of the active contact portion 124, or the extension depth of the temperature-sensitive contact portion 188 is smaller than the extension depth of the active contact portion 124. As one example, the contact width of the temperature-sensitive contact portion 188 may be larger than the contact width of the active contact portion 124, and the extension depth of the temperature-sensitive contact portion 188 may be the same as the extension depth of the active contact portion 124. As another example, the contact width of the temperature-sensitive contact portion 188 may be the same as the contact width of the active contact portion 124, and the extension depth of the temperature-sensitive contact portion 188 may be smaller than the extension depth of the active contact portion 124. As yet another example, the contact width of the temperature-sensitive contact portion 188 may be larger than the contact width of the active contact portion 124, and the extension depth of the temperature-sensitive contact portion 188 may be smaller than the extension depth of the active contact portion 124. The temperature sensitive contact portion 188 may not extend to the temperature sensitive diode 183 , and the active contact portion 124 may extend to the mesa portions 71 , 81 , 91 or the active trench portion 122 .

[0205] In this way, the active contact portion 124 and the temperature-sensitive contact portion 188 have different widths and / or depths, i.e., the active contact portion 124 and the temperature-sensitive contact portion 188 have different shapes, thereby ensuring stable electrical connection at each contact portion.

[0206] 9 shows an example of an enlarged view of the top surface of the semiconductor device 100. The semiconductor device 100 of this example differs from the embodiment of FIG. 1A in that a connection portion 25 is provided between the emitter electrode 52 and the dummy conductive portion 34. In this example, differences from the embodiment of FIG. 1A will be particularly described, and the rest may be the same as the embodiment of FIG. 1A.

[0207] The semiconductor device 100 includes a main region 220, which is a portion through which a main current flows between the front surface 21 and the back surface 23 of the semiconductor substrate 10, and a peripheral region 230 that is provided surrounding the main region 220. For example, the boundary between the main region 220 and the peripheral region 230 is the boundary between the base region 14 and the well region 17.

[0208] An interlayer insulating film 38 is provided above the front surface 21 of the semiconductor substrate 10, but the interlayer insulating film 38 is omitted in Fig. 9. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0209] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion 44 in the transistor portion 70 via the connection portion 25. The contact hole 56 electrically connects the emitter electrode 52 and the dummy conductive portion 34 in the dummy trench portion 30 via the connection portion 25. The connection portion 25 is a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. Polysilicon is an example of a polycrystalline semiconductor. The connection portion 25 is an example of a polycrystalline portion 232 provided above the semiconductor substrate 10 or on the front surface 21 side of the semiconductor substrate 10. The connection portion 25 is an example of a polycrystalline portion 232 included in the peripheral region 230.

[0210] 9. The dd' cross section is a YZ plane passing through contact hole 56 in peripheral region 230. In the dd' cross section, semiconductor device 100 of this example has semiconductor substrate 10, interlayer insulating film 38, emitter electrode 52, collector electrode 24, and first peripheral region contact portion 234.

[0211] The polycrystalline portion 232 is provided above the semiconductor substrate 10. The polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10 or on the front surface 21 side of the semiconductor substrate 10. The polycrystalline portion 232 in this example is provided above the front surface 21 of the semiconductor substrate 10. The polycrystalline portion 232 in this example is the connection portion 25. The polycrystalline portion 232 may be provided above a third interlayer insulating film 238. The third interlayer insulating film 238 may be made of, for example, the same material as the dummy insulating film 32. The interlayer insulating film 38 is provided above the polycrystalline portion 232.

[0212] The first outer periphery region contact portion 234 is provided in the interlayer insulating film 38 above the polycrystalline portion 232. The first outer periphery region contact portion 234 may have a contact hole 56 and a metal layer filled inside the contact hole 56. The detailed configuration of the first outer periphery region contact portion 234 will be described later.

[0213] The polycrystalline portion 232 may be connected to the emitter electrode 52 via the first outer peripheral region contact portion 234. The polycrystalline portion 232 may be connected to the dummy conductive portion 34. The connection portion 25 in this example is connected to the emitter electrode 52 via the first outer peripheral region contact portion 234, and is also connected to the dummy conductive portion 34.

[0214] The main region 220 may have a main region contact portion 224 provided in the interlayer insulating film 38. Since this figure is a cross-sectional view of the peripheral region 230, the main region contact portion 224 is not shown. The main region contact portion 224 is, for example, the active contact portion 124 shown in FIG. 4A. The contact width Wo1 of the first peripheral region contact portion 234 may be larger than the contact width Wt1 of the main region contact portion 224. The contact width Wo1 of the first peripheral region contact portion 234 may be the width at which the first peripheral region contact portion 234 contacts the polycrystalline portion 232. The sidewalls of the first peripheral region contact portion 234 may be the interlayer insulating film 38 from the top end to the bottom end.

[0215] In the semiconductor device 100 of this example, the contact width of the first outer periphery region contact portion 234 is larger than the contact width of the main region contact portion 224. By making the contact width of the first outer periphery region contact portion 234 larger than the contact width of the main region contact portion 224, the semiconductor device 100 can be manufactured stably and stable characteristics can be obtained even when the semiconductor device 100 is miniaturized. In this case, the main region contact portion 224 and the first outer periphery region contact portion 234 may be formed in different processes.

[0216] 10B shows an example of a cross section taken along the line dd' in FIG. 9. The semiconductor device 100 of this example differs from the embodiment of FIG. 10A in that the periphery region 230 has a first periphery region trench contact portion 2345. In this example, differences from the embodiment of FIG. 10A will be particularly described, and the rest may be the same as the embodiment of FIG. 10A.

[0217] The peripheral region 230 may have a first peripheral region trench contact portion 2345 that extends from the upper surface of the interlayer insulating film 38 downward beyond the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10. The first peripheral region trench contact portion 2345 is an example of the first peripheral region contact portion 234. The first peripheral region trench contact portion 2345 is a portion that is deeper toward the back surface 23 of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 232.

[0218] The polycrystalline portion 232 may be connected to the emitter electrode 52 via the first outer periphery region trench contact portion 2345. The polycrystalline portion 232 may be connected to the dummy conductive portion 34. The connection portion 25 in this example is connected to the emitter electrode 52 via the first outer periphery region trench contact portion 2345, and is connected to the dummy conductive portion 34.

[0219] The main region 220 may have a main region trench contact portion 2245 extending from the upper surface of the interlayer insulating film 38 to below the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. Because this figure is a cross-sectional view of the peripheral region 230, the main region trench contact portion 2245 is not shown. The main region trench contact portion 2245 is, for example, the active trench contact portion 1245 shown in FIG. 4C . The main region trench contact portion 2245 is an example of the main region contact portion 224. The main region trench contact portion 2245 is a portion that is deeper toward the back surface 23 of the semiconductor substrate 10 than the front surface 21 of the semiconductor substrate 10. The main region 220 may have a plurality of main region trench contact portions 2245 provided on the front surface 21 of the semiconductor substrate 10.

[0220] In the depth direction of the semiconductor substrate 10, an extension depth Do1 of the first outer periphery region trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 is shallower than an extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The extension depth Do1 of the first outer periphery region trench contact portion 2345 may be 0, and the extension depth Dt of the main region trench contact portion 2245 may be a value equal to or greater than 0. By making the extension depth Do1 of the first outer periphery region trench contact portion 2345 shallower than the extension depth Dt of the main region trench contact portion 2245, it is possible to prevent the first outer periphery region contact portion 234 from penetrating the polycrystalline portion 232 and extending through the third interlayer insulating film 238, thereby preventing insulation between the polycrystalline portion 232 and the semiconductor substrate 10 from being lost. In this example, the connection portion 25 that connects to the dummy conductive portion 34 does not need to be insulated from the semiconductor substrate 10, but it should be noted that this may cause problems for the first periphery region contact portion 234 in another region that is formed at the same time. Furthermore, since the main region trench contact portion 2245 extends deeper than the first periphery region trench contact portion 2345, latch-up can be suppressed by forming the main region contact portion 2244 sufficiently deep in the contact region 15. The first periphery region trench contact portion 2345 and the main region trench contact portion 2245 can be formed in the same process. However, the first periphery region trench contact portion 2345 and the main region trench contact portion 2245 may be formed in different processes.

[0221] The contact width Wto1 at which the first outer periphery region trench contact portion 2345 contacts the polycrystalline portion 232 may be larger than, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245. The contact width Wto1 of the first outer periphery region trench contact portion 2345 may be the width at which the first outer periphery region trench contact portion 2345 contacts the upper surface of the polycrystalline portion 232. The contact width Wtt1 of the main region trench contact portion 2245 may be the width at which the active trench contact portion 1245 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10, as shown in FIG. 4C .

[0222] 11A shows an example of a cross section taken along the line dd' in FIG. 9. The semiconductor device 100 of this example differs from the embodiment of FIG. 10A in that the peripheral region 230 has a recess region 236. In this example, differences from the embodiment of FIG. 10A will be particularly described, and the rest may be the same as the embodiment of FIG. 10A. In other words, the contact width Wo1 of the first peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0223] The peripheral region 230 may have a recess region 236 in which a depression is provided in the upper surface of the semiconductor substrate 10. The polycrystalline portion 232 may be provided in the recess region 236. In this example, the polycrystalline portion 232 is provided on the front surface 21 side of the semiconductor substrate 10. In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 236. The height positions being the same may include the height positions being approximately (substantially) the same. The height positions being approximately (substantially) the same may mean that the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the main region 220 and the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the recess region 236 are within 20% of the average value of both the distances, or may be within 10% of the average value.

[0224] When the height position of the upper surface of the interlayer insulating film 38 in the main region 220 is approximately the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 236, the main region contact portion 224 and the first outer periphery region contact portion 234 can be formed simultaneously using the same etching process. That is, if the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 236 are at the same height from the front surface 21 of the semiconductor substrate 10, there is no deviation in the focus of exposure in the photolithography process. This reduces the dimensional tolerances of the interlayer insulating film 38, the emitter electrode 52, and the like. Furthermore, the main region contact portion 224 and the first outer periphery region contact portion 234 can be formed with the same dimensional tolerances. This allows for easier manufacturing with fewer processes than when each contact portion is formed in separate processes. However, if the contact width of the first outer periphery region contact portion 234 is made larger than the contact width of the main region contact portion 224, the main region contact portion 224 and the first outer periphery region contact portion 234 may be formed in different processes.

[0225] 11B shows an example of a cross section taken along the line dd' in FIG. 9. The semiconductor device 100 of this example differs from the embodiment of FIG. 10B in that the peripheral region 230 has a recess region 236, and differs from the embodiment of FIG. 11A in that the peripheral region 230 has a first peripheral region trench contact portion 2345. The rest may be the same as the embodiment of FIG. 10B and / or FIG. 11A.

[0226] 12A shows an example of a cross section taken along the line dd' in FIG. 9. The semiconductor device 100 of this example differs from the embodiment of FIG. 10A in that the outer periphery region 230 has a housing portion 198. In this example, differences from the embodiment of FIG. 10A will be particularly described, and the rest may be the same as the embodiment of FIG. 10A. In other words, the contact width Wo1 of the first outer periphery region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0227] The housing portion 198 is provided below the first outer periphery region contact portion 234. The material of the housing portion 198 may be the same as that of the interlayer insulating film 38.

[0228] Fig. 12B shows an example of an enlarged view of the dd' cross section in Fig. 9. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230.

[0229] A bottom corner 2340 of the first outer periphery region contact portion 234 may be in contact with the polycrystalline portion 232. The bottom corner 2340 of the first outer periphery region contact portion 234 may be the intersection of the bottom surface of the first outer periphery region contact portion 234 and the side surface of the first outer periphery region contact portion 234. The bottom corner 2340 being in contact with the polycrystalline portion 232 may be in contact with the polycrystalline portion 232 on the top surface of the polycrystalline portion 232, may be in contact with the polycrystalline portion 232 on the side surface of the polycrystalline portion 232, or may be in contact with the polycrystalline portion 232 in an internal region of the polycrystalline portion 232. In this example, the bottom corner 2340 is in contact with the polycrystalline portion 232 on the top surface of the polycrystalline portion 232.

[0230] The first outer periphery region contact portion 234 of this example has two bottom corners 2340. One of the two bottom corners 2340 may contact the polycrystalline portion 232. The other of the two bottom corners 2340 may or may not contact the housing portion 198. The first outer periphery region contact portion 234 of this example has one bottom corner 2340a in contact with the polycrystalline portion 232 and the other bottom corner 2340b in contact with the housing portion 198.

[0231] The bottom surface of the first outer periphery region contact portion 234 may be in contact with the housing portion 198. The bottom surface of the first outer periphery region contact portion 234 may be the surface between two bottom corner portions 2340 of the first outer periphery region contact portion 234. The bottom surface of the first outer periphery region contact portion 234 in contact with the housing portion 198 may be in contact with the housing portion 198 at the upper surface of the housing portion 198, or may be in contact with the housing portion 198 in a region inside the housing portion 198. In this example, the bottom surface of the first outer periphery region contact portion 234 is in contact with the housing portion 198 at the upper surface of the housing portion 198.

[0232] The bottom surface of first outer periphery region contact portion 234 may be in contact with polycrystalline portion 232 and housing portion 198. In this example, first outer periphery region contact portion 234 has one bottom corner portion 2340 a in contact with polycrystalline portion 232 and the other bottom corner portion 2340 b in contact with housing portion 198, so that the bottom surface of first outer periphery region contact portion 234 is in contact with polycrystalline portion 232 and housing portion 198.

[0233] The polycrystalline portion 232 may contact the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340 over an area of ​​10% to 40% of the bottom surface of the first outer peripheral region contact portion 234. That is, the area ratio of the surface of the bottom surface of the first outer peripheral region contact portion 234 that is in contact with the polycrystalline portion 232 to the area of ​​the bottom surface of the first outer peripheral region contact portion 234 may be 10% to 40%. Referring to FIG. 12B , length L1 is the length of the bottom surface of the first outer peripheral region contact portion 234 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the first outer peripheral region contact portion 234 that is in contact with the polycrystalline portion 232 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the polycrystalline portion 232 contacts the bottom surface of the first outer peripheral region contact portion 234 from the bottom surface corner 2340a to an area that is 20% of the bottom surface of the first outer peripheral region contact portion 234. That is, in this example, the ratio of length L2 to length L1 is 20%.

[0234] The first outer periphery region contact portion 234 may have a barrier metal film 2342 and a plug portion 2344. In this example, the barrier metal film 2342 and the plug portion 2344 are formed of different materials, but they may also be formed of the same material.

[0235] The barrier metal film 2342 may be provided on the bottom corners 2340 of the first outer periphery region contact portion 234. In this example, the barrier metal film 2342 is provided over the entire side and bottom surface of the first outer periphery region contact portion 234, but this is not limiting. The barrier metal film 2342 may be provided so as to cover at least the bottom corners 2340, or may be provided so as not to cover the central portion of the bottom surface of the first outer periphery region contact portion 234. The barrier metal film 2342 may extend beyond the contact hole 56 and extend above the interlayer insulating film 38. The material of the barrier metal film 2342 may be titanium, a titanium compound, or the like.

[0236] The plug portion 2344 may be provided in contact with the inner side of the barrier metal film 2342. In this example, the plug portion 2344 is provided by filling the first outer periphery region contact portion 234, but this is not limiting. The plug portion 2344 may be provided in a portion of the first outer periphery region contact portion 234, or may extend beyond the contact hole 56 and be provided up to above the interlayer insulating film 38. When the plug portion 2344 is provided in a portion of the first outer periphery region contact portion 234, the remaining region of the first outer periphery region contact portion 234 may be filled with the same material as the emitter electrode 52. The material of the plug portion 2344 may be a plug metal such as tungsten.

[0237] The side surface of the polycrystalline portion 232 may contact the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the first outer periphery region contact portion 234. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed of the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 that is provided below the first outer periphery region contact portion 234, the housing portion 198 is a virtual region, as shown by the dotted line in FIG. 12B . In other words, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be a third interlayer insulating film 238 that is provided above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 238 and may be formed of the same material as the third interlayer insulating film 238. That is, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 238. In this case, the polycrystalline portion 232 may be provided in a recess formed by etching the upper surface of the thick third interlayer insulating film 238. In still another example, the housing portion 198 may be polysilicon having a lower impurity concentration than the polycrystalline portion 232 or undoped polysilicon.

[0238] In this example, the first outer periphery region contact portion 234 is provided such that the bottom corners 2340 are in contact with the polycrystalline portion 232 and the bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the emitter electrode 52 and the polycrystalline portion 232. If the plug portion 2344 and the barrier metal film 2342 near the center of the bottom surface of the first outer periphery region contact portion 234 are over-etched and removed during the etch-back process of the plug portion 2344, voids may occur inside the first outer periphery region contact portion 234. Even in this case, the electrical connection can be ensured by the barrier metal film 2342 and / or the plug portion 2344 remaining at the bottom corners 2340 of the first outer periphery region contact portion 234.

[0239] In this example, the first outer periphery region contact portion 234 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the first outer periphery region contact portion 234 near the center of the bottom surface, the influence on the electrical connection between the first outer periphery region contact portion 234 and the polycrystalline portion 232 at the bottom corners 2340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. In this example, the outer periphery region 230 ensures electrical connection between the first outer periphery region contact portion 234 and the polycrystalline portion 232 via the bottom corners 2340 rather than the bottom center of the first outer periphery region contact portion 234. This ensures stable quality and improved yield, even if a void forms in the region near the center of the first outer periphery region contact portion 234 that contacts the housing portion 198.

[0240] Figure 13A shows an example of a cross section taken along the line dd' in Figure 9. The semiconductor device 100 of this example differs from the embodiment of Figure 10B in that the peripheral region 230 has a housing portion 198, and differs from the embodiment of Figure 12A in that the peripheral region 230 has a first peripheral region trench contact portion 2345. The rest may be the same as the embodiment of Figure 10B and / or Figure 12A.

[0241] 13B shows an example of an enlarged view of the dd' cross section in FIG. 9. This view shows a region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230. The semiconductor device 100 of this example differs from the embodiment of FIG. 12B in that the peripheral region 230 has a first peripheral region trench contact portion 2345. In this example, differences from the embodiment of FIG. 12B will be particularly described, and the rest may be the same as the embodiment of FIG. 12B.

[0242] The sidewall of the first outer periphery region contact portion 234 may be in contact with the polycrystalline portion 232 and the interlayer insulating film 38. The polycrystalline portion 232 may be in contact with the sidewall of the first outer periphery region contact portion 234 from the bottom corner 2340 over an area of ​​10% to 90% of the sidewall of the first outer periphery region contact portion 234. In other words, the ratio of the area of ​​the sidewall of the first outer periphery region contact portion 234 that is in contact with the polycrystalline portion 232 to the area of ​​the sidewall of the first outer periphery region contact portion 234 that is in contact with the polycrystalline portion 232 may be 10% to 90%. 13B , length L3 is the length of the sidewall of first outer periphery region contact portion 234 in a cross section perpendicular to front surface 21 of semiconductor substrate 10, and length L4 is the length of the sidewall of first outer periphery region contact portion 234 that contacts polycrystalline portion 232 in a cross section perpendicular to front surface 21 of semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less. In this example, polycrystalline portion 232 contacts the sidewall of first outer periphery region contact portion 234 from bottom corner 2340 to 35% of the sidewall of first outer periphery region contact portion 234. That is, in this example, the ratio of length L4 to length L3 is 35%.

[0243] 9. The ee' cross section is a YZ plane passing through contact hole 55 in peripheral region 230. In the ee' cross section, semiconductor device 100 of this example has semiconductor substrate 10, interlayer insulating film 38, gate metal layer 50, collector electrode 24, and first peripheral region contact portion 234.

[0244] The polycrystalline portion 232 is provided above the semiconductor substrate 10. The polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10 or on the front surface 21 side of the semiconductor substrate 10. The polycrystalline portion 232 in this example is provided above the front surface 21 of the semiconductor substrate 10. The polycrystalline portion 232 in this example is the connection portion 25. The polycrystalline portion 232 may be provided above a third interlayer insulating film 238. The third interlayer insulating film 238 may be made of, for example, the same material as the gate insulating film 42. The interlayer insulating film 38 is provided above the polycrystalline portion 232.

[0245] The first outer periphery region contact portion 234 is provided in the interlayer insulating film 38 above the polycrystalline portion 232. The first outer periphery region contact portion 234 may have a contact hole 55 and a metal layer filled inside the contact hole 55.

[0246] The polycrystalline portion 232 may be connected to the gate metal layer 50 via the first outer periphery region contact portion 234. The polycrystalline portion 232 may be connected to the gate conductive portion 44. The connection portion 25 of this example is connected to the gate metal layer 50 via the first outer periphery region contact portion 234, and is connected to the gate conductive portion 44.

[0247] The contact width Wo1 of the first outer peripheral region contact portion 234 may be larger than the contact width Wt1 of the main region contact portion 224. The sidewall of the first outer peripheral region contact portion 234 may be the interlayer insulating film 38 from the top end to the bottom end.

[0248] In the semiconductor device 100 of this example, the contact width of the first outer periphery region contact portion 234 is larger than the contact width of the main region contact portion 224. By making the contact width of the first outer periphery region contact portion 234 larger than the contact width of the main region contact portion 224, the semiconductor device 100 can be manufactured stably and stable characteristics can be obtained even when the semiconductor device 100 is miniaturized. In this case, the main region contact portion 224 and the first outer periphery region contact portion 234 may be formed in different processes.

[0249] 14B shows an example of the e-e' cross section in FIG. 9. The semiconductor device 100 of this example differs from the embodiment of FIG. 14A in that the periphery region 230 has a first periphery region trench contact portion 2345. In this example, differences from the embodiment of FIG. 14A will be particularly described, and the rest may be the same as the embodiment of FIG. 14A.

[0250] The peripheral region 230 may have a first peripheral region trench contact portion 2345 that extends from the upper surface of the interlayer insulating film 38 downward beyond the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10. The first peripheral region trench contact portion 2345 is an example of the first peripheral region contact portion 234. The first peripheral region trench contact portion 2345 is a portion that is deeper toward the back surface 23 of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 232.

[0251] The polycrystalline portion 232 may be connected to the gate metal layer 50 via the first outer periphery region trench contact portion 2345. The polycrystalline portion 232 may be connected to the gate conductive portion 44. The connection portion 25 in this example is connected to the gate metal layer 50 via the first outer periphery region trench contact portion 2345, and is connected to the gate conductive portion 44.

[0252] In the depth direction of the semiconductor substrate 10, an extension depth Do1 of the first outer periphery region trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 is shallower than an extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The extension depth Do1 of the first outer periphery region trench contact portion 2345 may be 0, and the extension depth Dt of the main region trench contact portion 2245 may be a value equal to or greater than 0. By making the extension depth Do1 of the first outer periphery region trench contact portion 2345 shallower than the extension depth Dt of the main region trench contact portion 2245, it is possible to prevent the first outer periphery region contact portion 234 from penetrating the polycrystalline portion 232 and extending through the third interlayer insulating film 238, thereby preventing insulation between the polycrystalline portion 232 and the semiconductor substrate 10 from being lost. Furthermore, since the main region trench contact portion 2245 extends deeper than the first periphery region trench contact portion 2345, latch-up can be suppressed by forming the main region contact portion 224 sufficiently deep in the contact region 15. In particular, in this example, insulation between the connection portion 25 and the well region 17 can be maintained. The first periphery region trench contact portion 2345 and the main region trench contact portion 2245 can be formed in the same process. However, the first periphery region trench contact portion 2345 and the main region trench contact portion 2245 may be formed in different processes.

[0253] The contact width Wto1 at which the first outer periphery region trench contact portion 2345 contacts the polycrystalline portion 232 may be larger than, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245.

[0254] 15A shows an example of the e-e' cross section in FIG. 9. The semiconductor device 100 of this example differs from the embodiment of FIG. 14A in that the peripheral region 230 has a recess region 236. In this example, differences from the embodiment of FIG. 14A will be particularly described, and the rest may be the same as the embodiment of FIG. 14A. In other words, the contact width Wo1 of the first peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0255] The peripheral region 230 may have a recess region 236 in which a depression is provided in the upper surface of the semiconductor substrate 10. The polycrystalline portion 232 may be provided in the recess region 236. In this example, the polycrystalline portion 232 is provided on the front surface 21 side of the semiconductor substrate 10. In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 236.

[0256] When the height position of the upper surface of the interlayer insulating film 38 in the main region 220 is approximately the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 236, the main region contact portion 224 and the first outer periphery region contact portion 234 can be formed simultaneously using the same etching process. That is, when the upper surfaces of the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 236 are at the same height from the front surface 21 of the semiconductor substrate 10, there is no deviation in the focus of exposure in the photolithography process. This reduces the dimensional tolerances of the interlayer insulating film 38, the emitter electrode 52, the gate metal layer 50, and the like. Furthermore, the main region contact portion 224 and the first outer periphery region contact portion 234 can be formed with the same dimensional tolerances. This allows for easier manufacturing with fewer processes than when each contact portion is formed in separate processes. However, if the contact width of the first outer periphery region contact portion 234 is made larger than the contact width of the main region contact portion 224, the main region contact portion 224 and the first outer periphery region contact portion 234 may be formed in different processes.

[0257] Figure 15B shows an example of the e-e' cross section in Figure 9. The semiconductor device 100 of this example differs from the embodiment of Figure 14B in that the peripheral region 230 has a recess region 236, and differs from the embodiment of Figure 15A in that the peripheral region 230 has a first peripheral region trench contact portion 2345. Other aspects may be the same as the embodiment of Figure 14B and / or Figure 15A.

[0258] 16A shows an example of the e-e' cross section in FIG. 9. The semiconductor device 100 of this example differs from the embodiment of FIG. 14A in that the outer periphery region 230 has a housing portion 198. In this example, differences from the embodiment of FIG. 14A will be particularly described, and the rest may be the same as the embodiment of FIG. 14A. In other words, the contact width Wo1 of the first outer periphery region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0259] The housing portion 198 is provided below the first outer periphery region contact portion 234. The material of the housing portion 198 may be the same as that of the interlayer insulating film 38.

[0260] Fig. 16B shows an example of an enlarged view of the ee' cross section in Fig. 9. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230.

[0261] A bottom corner 2340 of the first outer periphery region contact portion 234 may be in contact with the polycrystalline portion 232. In this example, the bottom corner 2340 is in contact with the polycrystalline portion 232 on the top surface of the polycrystalline portion 232.

[0262] The bottom surface of the first outer periphery region contact portion 234 may be in contact with the housing portion 198. In this example, the bottom surface of the first outer periphery region contact portion 234 is in contact with the housing portion 198 on the upper surface of the housing portion 198.

[0263] The bottom surface of first outer periphery region contact portion 234 may be in contact with polycrystalline portion 232 and housing portion 198. In this example, first outer periphery region contact portion 234 has one bottom corner portion 2340 a in contact with polycrystalline portion 232 and the other bottom corner portion 2340 b in contact with housing portion 198, so that the bottom surface of first outer periphery region contact portion 234 is in contact with polycrystalline portion 232 and housing portion 198.

[0264] The polycrystalline portion 232 may contact the bottom surface of the first outer peripheral region contact portion 234 from the bottom corner 2340 over an area of ​​10% to 40% of the bottom surface of the first outer peripheral region contact portion 234. In this example, the polycrystalline portion 232 contacts the bottom surface of the first outer peripheral region contact portion 234 over an area of ​​20% of the bottom surface of the first outer peripheral region contact portion 234 from the bottom corner 2340a. That is, in this example, the ratio of length L2 to length L1 is 20%.

[0265] The barrier metal film 2342 may be provided on the bottom corners 2340 of the first outer periphery region contact portion 234. In this example, the barrier metal film 2342 is provided over the entire side and bottom surface of the first outer periphery region contact portion 234, but this is not limiting. The barrier metal film 2342 may be provided so as to cover at least the bottom corners 2340, or may be provided so as not to cover the central portion of the bottom surface of the first outer periphery region contact portion 234. The barrier metal film 2342 may extend beyond the contact hole 55 and extend above the interlayer insulating film 38. The material of the barrier metal film 2342 may be titanium, a titanium compound, or the like.

[0266] The plug portion 2344 may be provided in contact with the inner side of the barrier metal film 2342. In this example, the plug portion 2344 is provided by filling the first outer periphery region contact portion 234, but this is not limiting. The plug portion 2344 may be provided in a portion of the first outer periphery region contact portion 234, or may extend beyond the contact hole 55 and be provided up to above the interlayer insulating film 38. When the plug portion 2344 is provided in a portion of the first outer periphery region contact portion 234, the remaining region of the first outer periphery region contact portion 234 may be filled with the same material as the gate metal layer 50. The material of the plug portion 2344 may be a plug metal such as tungsten.

[0267] The side surface of the polycrystalline portion 232 may contact the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the first outer periphery region contact portion 234. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed of the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 that is provided below the first outer periphery region contact portion 234, the housing portion 198 is a virtual region, as shown by the dotted line in FIG. 16B . In other words, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be a third interlayer insulating film 238 that is provided above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 238 and may be formed of the same material as the third interlayer insulating film 238. That is, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 238. In yet another example, the housing portion 198 may be polysilicon having a lower impurity concentration than the polycrystalline portion 232 or undoped polysilicon.

[0268] In this example, the first outer periphery region contact portion 234 is provided such that the bottom corner portions 2340 are in contact with the polycrystalline portion 232 and the bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the gate metal layer 50 and the polycrystalline portion 232. If the plug portion 2344 and the barrier metal film 2342 near the center of the bottom surface of the first outer periphery region contact portion 234 are over-etched during the etch-back process of the plug portion 2344, voids may occur inside the first outer periphery region contact portion 234. Even in this case, the electrical connection can be ensured by the barrier metal film 2342 and / or the plug portion 2344 remaining at the bottom corner portions 2340 of the first outer periphery region contact portion 234.

[0269] In this example, the first outer periphery region contact portion 234 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the first outer periphery region contact portion 234 near the center of the bottom surface, the influence on the electrical connection between the first outer periphery region contact portion 234 and the polycrystalline portion 232 at the bottom corners 2340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. In this example, the outer periphery region 230 ensures electrical connection between the first outer periphery region contact portion 234 and the polycrystalline portion 232 via the bottom corners 2340 rather than the bottom center of the first outer periphery region contact portion 234. This ensures stable quality and improved yield, even if a void forms in the region near the center of the first outer periphery region contact portion 234 that contacts the housing portion 198.

[0270] Figure 17A shows an example of the e-e' cross section in Figure 9. The semiconductor device 100 of this example differs from the embodiment of Figure 14B in that the outer periphery region 230 has a housing portion 198, and differs from the embodiment of Figure 16A in that the first outer periphery region 230 has a first outer periphery region trench contact portion 2345. The rest may be the same as the embodiment of Figure 14B and / or Figure 16A.

[0271] 17B shows an example of an enlarged view of the e-e' cross section in FIG. 9. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230. The semiconductor device 100 of this example differs from the embodiment of FIG. 16B in that the peripheral region 230 has a first peripheral region trench contact portion 2345. In this example, differences from the embodiment of FIG. 16B will be particularly described, and the rest may be the same as the embodiment of FIG. 16B.

[0272] The sidewall of the first outer periphery region contact portion 234 may be in contact with the polycrystalline portion 232 and the interlayer insulating film 38. The polycrystalline portion 232 may be in contact with the sidewall of the first outer periphery region contact portion 234 from the bottom corner 2340 over an area of ​​10% to 90% of the sidewall of the first outer periphery region contact portion 234. In this example, the polycrystalline portion 232 is in contact with the sidewall of the first outer periphery region contact portion 234 over an area of ​​35% of the sidewall of the first outer periphery region contact portion 234 from the bottom corner 2340. That is, in this example, the ratio of length L4 to length L3 is 35%.

[0273] 18A shows an example of a top view of the semiconductor device 100. The semiconductor device 100 of this example includes a guard ring 142 in the edge termination structure 140. The semiconductor device 100 may include multiple guard rings 142.

[0274] The guard ring 142 is a second conductivity type region provided on the front surface 21 of the semiconductor substrate 10 between the active portion 120 and the edge 102 of the semiconductor substrate 10. The guard ring 142 is, for example, a P+ type. The guard ring 142 may surround the active portion 120 in a top view. The guard ring 142 arranged on the outside may surround the guard ring 142 arranged on the inside. The "outside" refers to the side closer to the edge 102, and the "inside" refers to the side closer to the center of the semiconductor substrate 10 in a top view. By providing the guard ring 142, the depletion layer on the front surface 21 side of the active portion 120 can be extended toward the edge 102, thereby improving the breakdown voltage of the semiconductor device 100. The semiconductor device 100 may further include at least one of a field plate or a resurf provided in the edge termination structure 140 to surround the active portion 120.

[0275] 18B shows an example of region R in FIG. 18A . In this example, semiconductor device 100 includes guard ring 142 and field plate 144 in edge termination structure 140. Edge termination structure 140 is an example of peripheral region 230. Semiconductor device 100 may include interlayer insulating film 38, edge metal layer 146, and field insulating film 148 in edge termination structure 140. Interlayer insulating film 38, edge metal layer 146, and field insulating film 148 are omitted in FIG. 13B . Contact holes 57 and 59 are provided penetrating interlayer insulating film 38.

[0276] The field plate 144 is a conductive member provided above the semiconductor substrate 10. In this example, the field plate 144 is formed of polysilicon doped with impurities. The field plate 144 is an example of a polycrystalline portion 232. The field plate 144 is provided above the guard ring 142. The field plate 144 may be electrically connected to the corresponding guard ring 142.

[0277] The guard ring 142 has a non-corner region 1420 and a corner region 1422. The non-corner region 1420 is, for example, a region of the guard ring 142 that extends along the edge 102 of the semiconductor substrate 10, and the corner region 1422 is, for example, a portion of the guard ring 142 that connects the regions that extend along the edge 102 of the semiconductor substrate 10.

[0278] Contact hole 57 connects edge metal layer 146 and field plate 144. Inside contact hole 57, a barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed.

[0279] The contact hole 59 connects the edge metal layer 146 and the guard ring 142. Inside the contact hole 59, a barrier metal film made of titanium or a titanium compound and / or a plug made of tungsten may be formed.

[0280] The contact holes 57 and 59 may be provided above the corner regions 1422 of the guard ring 142. However, at least one of the contact holes 57 and 59 may be provided above the non-corner regions 1420 of the guard ring 142, or both the contact holes 57 and 59 may be provided above the non-corner regions 1420 of the guard ring 142.

[0281] In this example, contact holes 57 and 59 have their length in the direction in which guard ring 142 and field plate 144 extend, and are provided side by side from the center toward edge 102. In another example, contact holes 57 and 59 may be arranged in the direction in which guard ring 142 and field plate 144 extend, the length of each contact hole may be from the center toward edge 102, and each contact hole may consist of multiple holes.

[0282] The width d2 of the corner region 1422 may be wider than the width d1 of the non-corner region 1420. That is, the radius of curvature r1 on the side of the edge 102 (outside) may be smaller than the sum of the radii of curvature r2 and d1 on the central side (inside). In this example, r1 is smaller than d2. The edge metal layer 146 may be provided at or near the widest point of the corner region 1422. In another example, the width d2 of the corner region 1422 may be equal to the width d1 of the non-corner region 1420. In yet another example, the edge metal layer 146 may be provided in the non-corner region 1420, or may be provided across the non-corner region 1420 and the corner region 1422.

[0283] 19A shows an example of the ff' cross section in Figure 18B. The ff' cross section is a plane parallel to the Z-axis direction that passes through contact holes 57 and 59 in peripheral region 230. In the ff' cross section, semiconductor device 100 of this example has semiconductor substrate 10, interlayer insulating film 38, field insulating film 148, edge metal layer 146, collector electrode 24, first peripheral region contact portion 234, and second peripheral region contact portion 235.

[0284] The field insulating film 148 is provided above the semiconductor substrate 10. The field insulating film 148 may be provided between the well region 17 and the guard ring 142 and between the guard rings 142 so as to cover the drift region 18 exposed on the front surface 21 of the semiconductor substrate 10. The field insulating film 148 may be provided along the guard ring 142 so as to surround the main region 220.

[0285] The field insulating film 148 may include an insulating film obtained by oxidizing or nitriding the semiconductor substrate 10, an insulating film deposited by CVD or the like, or another insulating film. The field insulating film 148 may be a single-layer insulating film, or may be an insulating film in which multiple films formed by different methods are stacked.

[0286] The edge metal layer 146 is provided above the semiconductor substrate 10 and is electrically connected to the guard ring 142. The edge metal layer 146 is provided above the semiconductor substrate 10 with the interlayer insulating film 38 sandwiched therebetween. The edge metal layer 146 may be electrically connected to the field plate 144. The edge metal layer 146 may be electrically floating. For example, when a voltage V is applied to the collector electrode 24 with the gate of the semiconductor device 100 in an off state, a predetermined voltage lower than the voltage V may be applied to the edge metal layer 146.

[0287] The edge metal layer 146 is formed of a material containing metal. At least a portion of the edge metal layer 146 may be formed of a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). The edge metal layer 146 may have a barrier metal film formed of titanium or a titanium compound below the region formed of aluminum or the like.

[0288] The polycrystalline portion 232 is provided above the semiconductor substrate 10. The polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10 or on the front surface 21 side of the semiconductor substrate 10. In this example, the polycrystalline portion 232 is provided above the front surface 21 of the semiconductor substrate 10. In this example, the polycrystalline portion 232 is a field plate 144. The polycrystalline portion 232 may be provided above a third interlayer insulating film 238. The third interlayer insulating film 238 may be made of the same material as the gate insulating film 42 and / or the dummy insulating film 32, for example. The third interlayer insulating film 238 may be a thermal oxide film, for example. The interlayer insulating film 38 is provided above the polycrystalline portion 232.

[0289] The first outer periphery region contact portion 234 is provided in the interlayer insulating film 38 above the polycrystalline portion 232. The first outer periphery region contact portion 234 may have a contact hole 57 and a metal layer filled inside the contact hole 57. The second outer periphery region contact portion 235 is provided in the interlayer insulating film 38 in a region where the polycrystalline portion 232 is not provided. The second outer periphery region contact portion 235 may have a contact hole 59 and a metal layer filled inside the contact hole 59. The second outer periphery region contact portion 235 may include a barrier metal film 2352 and a plug portion 2354.

[0290] The polycrystalline portion 232 may be connected to the edge metal layer 146 via a first periphery region contact portion 234. The field plate 144 of this example is connected to the edge metal layer 146 via the first periphery region contact portion 234. The semiconductor substrate 10 may be connected to the edge metal layer 146 via a second periphery region contact portion 235. The guard ring 142 of this example is connected to the edge metal layer 146 via the second periphery region contact portion 235.

[0291] The contact width Wo1 of the first outer peripheral region contact portion 234 may be larger than the contact width Wt1 of the main region contact portion 224. The sidewall of the first outer peripheral region contact portion 234 may be the interlayer insulating film 38 from the top end to the bottom end.

[0292] In the semiconductor device 100 of this example, the contact width of the first outer periphery region contact portion 234 is larger than the contact width of the main region contact portion 224. By making the contact width of the first outer periphery region contact portion 234 larger than the contact width of the main region contact portion 224, the semiconductor device 100 can be manufactured stably and stable characteristics can be obtained even when the semiconductor device 100 is miniaturized. In this case, the main region contact portion 224 and the first outer periphery region contact portion 234 may be formed in different processes.

[0293] Figure 19B shows an example of the ff' cross section in Figure 18B. The semiconductor device 100 of this example differs from the embodiment of Figure 19A in that the periphery region 230 has a first periphery region trench contact portion 2345 and a second periphery region trench contact portion 2355. In this example, differences from the embodiment of Figure 19A will be particularly described, and the rest may be the same as the embodiment of Figure 19A.

[0294] The peripheral region 230 may have a first peripheral region trench contact portion 2345 extending from the upper surface of the interlayer insulating film 38 downward beyond the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10. The first peripheral region trench contact portion 2345 is an example of the first peripheral region contact portion 234. The first peripheral region trench contact portion 2345 is a portion deeper toward the back surface 23 of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 232. The peripheral region 230 may have a second peripheral region trench contact portion 2355 extending from the upper surface of the interlayer insulating film 38 downward beyond the upper surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The second peripheral region trench contact portion 2355 is an example of the second peripheral region contact portion 235. The second peripheral region trench contact portion 2355 is a portion deeper toward the back surface 23 of the semiconductor substrate 10 than the upper surface of the semiconductor substrate 10.

[0295] The polycrystalline portion 232 may be connected to the edge metal layer 146 via a first periphery region trench contact portion 2345. The field plate 144 of this example is connected to the edge metal layer 146 via the first periphery region trench contact portion 2345. The semiconductor substrate 10 may be connected to the edge metal layer 146 via a second periphery region trench contact portion 2355. The guard ring 142 of this example is connected to the edge metal layer 146 via the second periphery region trench contact portion 2355.

[0296] In the depth direction of the semiconductor substrate 10, an extension depth Do1 of the first outer periphery region trench contact portion 2345 extending from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 is shallower than an extension depth Dt of the multiple main region trench contact portions 2245 extending from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The extension depth Do1 of the first outer periphery region trench contact portion 2345 may be 0, and the extension depth Dt of the main region trench contact portion 2245 may be a value equal to or greater than 0. By making the extension depth Do1 of the first outer periphery region trench contact portion 2345 shallower than the extension depth Dt of the main region trench contact portion 2245, it is possible to prevent the first outer periphery region contact portion 234 from penetrating the polycrystalline portion 232 and extending through the third interlayer insulating film 238, thereby preventing insulation between the polycrystalline portion 232 and the semiconductor substrate 10 from being lost. In this example, the field plate 144 does not need to be insulated from the guard ring 142, but it should be noted that this may cause problems for the first periphery region contact portion 234 in another region that is formed at the same time. Also, since the main region trench contact portion 2245 extends deeper than the first periphery region trench contact portion 2345, latch-up can be suppressed by forming the main region contact portion 2244 sufficiently deep in the contact region 15. The first periphery region trench contact portion 2345 and the main region trench contact portion 2245 can be formed in the same process. However, the first periphery region trench contact portion 2345 and the main region trench contact portion 2245 may be formed in different processes.

[0297] Both the extension depth Do1 of the first outer periphery region trench contact portion 2345 and the extension depth Do2 of the second outer periphery region trench contact portion 2355 may be shallower than the extension depth Dt of the main region trench contact portion 2245. That is, the extension depth Do1 to which the first outer periphery region trench contact portion 2345 extends from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 and the extension depth Do2 to which the second outer periphery region trench contact portion 2355 extends from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10 may be shallower than the extension depth Dt to which the multiple main region trench contact portions 2245 extend from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10.

[0298] When the extension depth Do1 of the first outer periphery region trench contact portion 2345 and the extension depth Do2 of the second outer periphery region trench contact portion 2355 are both shallower than the extension depth Dt of the main region trench contact portion 2245, the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 can be formed in the same process. For example, when the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 are formed in different processes, the aperture ratio of the mask used in the process of forming the main region trench contact portion 2245 differs from the aperture ratio of the mask used in the process of forming the first outer periphery region trench contact portion 2345, and therefore the shapes of the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 may differ from the design. By forming the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 in the same process, the mask aperture ratio in the process of forming the main region trench contact portion 2245 is similar to the mask aperture ratios in the processes of forming the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355, and the first outer periphery region trench contact portion 2345 is formed in the designed shape. However, the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 may be formed in different processes.

[0299] A contact width Wto1 at which the first outer periphery region trench contact portion 2345 contacts the polycrystalline portion 232 may be larger than, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245. A contact width Wto2 at which the second outer periphery region trench contact portion 2355 contacts the front surface 21 of the semiconductor substrate 10 may be larger than, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245.

[0300] Figure 19C shows an example of the ff' cross section in Figure 18B. The semiconductor device 100 of this example differs from the embodiment of Figure 19B in that the extension depths of the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 are different. In this example, differences from the embodiment of Figure 19B will be particularly described, and the rest may be the same as the embodiment of Figure 19B.

[0301] An extension depth Do1 to which the first outer periphery region trench contact portion 2345 extends from the upper surface of the polycrystalline portion 232 in the depth direction of the semiconductor substrate 10 may be shallower than an extension depth Do2 to which the second outer periphery region trench contact portion 2355 extends from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this case, the first outer periphery region trench contact portion 2345 and the second outer periphery region trench contact portion 2355 may be formed in different processes, and the second outer periphery region trench contact portion 2355 and the main region trench contact portion 2245 may be formed in the same process.

[0302] In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the main region 220 is approximately the same as the height position of the upper surface of the interlayer insulating film 38 in the portion where the second periphery region trench contact portion 2355 is provided. This allows the main region trench contact portion 2245 and the second periphery region trench contact portion 2355 to be formed simultaneously by the same etching process. In other words, if the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the portion where the second periphery region trench contact portion 2355 is provided are at the same height from the front surface 21 of the semiconductor substrate 10, there is no deviation in the focus of exposure in the photolithography process. This allows for reduced dimensional tolerances of the interlayer insulating film 38, the emitter electrode 52, the edge metal layer 146, and the like. Furthermore, the main region trench contact portion 2245 and the second periphery region trench contact portion 2355 can be formed with the same dimensional tolerances.

[0303] 20A shows an example of the ff' cross section in FIG. 18B. The semiconductor device 100 of this example differs from the embodiment of FIG. 19A in that the peripheral region 230 has a recess region 236. In this example, differences from the embodiment of FIG. 19A will be particularly described, and the rest may be the same as the embodiment of FIG. 19A. In other words, the contact width Wo1 of the first peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0304] The peripheral region 230 may have a recess region 236 in which a depression is provided in the upper surface of the semiconductor substrate 10. The polycrystalline portion 232 may be provided in the recess region 236. In this example, the polycrystalline portion 232 is provided on the front surface 21 side of the semiconductor substrate 10. In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 236.

[0305] When the height position of the upper surface of the interlayer insulating film 38 in the main region 220 is approximately the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 236, the main region contact portion 224 and the first outer periphery region contact portion 234 can be formed simultaneously using the same etching process. That is, if the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 236 are at the same height from the front surface 21 of the semiconductor substrate 10, there is no deviation in the focus of exposure in the photolithography process. This reduces the dimensional tolerances of the interlayer insulating film 38, the emitter electrode 52, the edge metal layer 146, and the like. Furthermore, the main region contact portion 224 and the first outer periphery region contact portion 234 can be formed with the same dimensional tolerances. This allows for easier manufacturing with fewer processes than when each contact portion is formed in separate processes. However, if the contact width of the first outer periphery region contact portion 234 is made larger than the contact width of the main region contact portion 224, the main region contact portion 224 and the first outer periphery region contact portion 234 may be formed in different processes.

[0306] Figure 20B shows an example of the ff' cross section in Figure 18B. The semiconductor device 100 of this example differs from the embodiment of Figure 19B in that the periphery region 230 has a recess region 236, and differs from the embodiment of Figure 20A in that the periphery region 230 has a first periphery region trench contact portion 2345 and a second periphery region trench contact portion 2355. The rest may be the same as the embodiment of Figure 19B and / or Figure 20A.

[0307] In this example, the height positions of the upper surface of the interlayer insulating film 38 in the main region 220, the upper surface of the interlayer insulating film 38 in the recess region 236, and the upper surface of the interlayer insulating film 38 in the portion where the second periphery region trench contact portion 2355 is provided are substantially the same. Therefore, the main region trench contact portion 2245, the first periphery region trench contact portion 2345, and the second periphery region trench contact portion 2355 can be formed simultaneously by the same etching process. This allows for easier manufacturing with fewer steps than when each contact portion is formed in a separate process. However, each contact portion may be formed in a different process.

[0308] 21A shows an example of the ff' cross section in FIG. 18B. The semiconductor device 100 of this example differs from the embodiment of FIG. 19A in that the peripheral region 230 has a housing portion 198. In this example, differences from the embodiment of FIG. 19A will be particularly described, and the rest may be the same as the embodiment of FIG. 19A. In other words, the contact width Wo1 of the first peripheral region contact portion 234 may be larger than the contact width of the main region contact portion 224.

[0309] The housing portion 198 is provided below the first outer periphery region contact portion 234. The material of the housing portion 198 may be the same as or different from the material of the interlayer insulating film 38.

[0310] 21B shows an example of an enlarged view of the ff' cross section in FIG. 18B. This view shows the region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230.

[0311] A bottom corner 2340 of the first outer periphery region contact portion 234 may be in contact with the polycrystalline portion 232. In this example, the bottom corner 2340 is in contact with the polycrystalline portion 232 on the top surface of the polycrystalline portion 232.

[0312] The bottom surface of the first outer periphery region contact portion 234 may be in contact with the housing portion 198. In this example, the bottom surface of the first outer periphery region contact portion 234 is in contact with the housing portion 198 on the upper surface of the housing portion 198.

[0313] The bottom surface of first outer periphery region contact portion 234 may be in contact with polycrystalline portion 232 and housing portion 198. In this example, first outer periphery region contact portion 234 has one bottom corner portion 2340 a in contact with polycrystalline portion 232 and the other bottom corner portion 2340 b in contact with housing portion 198, so that the bottom surface of first outer periphery region contact portion 234 is in contact with polycrystalline portion 232 and housing portion 198.

[0314] The polycrystalline portion 232 may contact the bottom surface of the first outer peripheral region contact portion 234 from the bottom corner 2340 over an area of ​​10% to 40% of the bottom surface of the first outer peripheral region contact portion 234. In this example, the polycrystalline portion 232 contacts the bottom surface of the first outer peripheral region contact portion 234 over an area of ​​20% of the bottom surface of the first outer peripheral region contact portion 234 from the bottom corner 2340a. That is, in this example, the ratio of length L2 to length L1 is 20%.

[0315] The barrier metal film 2342 may be provided on the bottom corners 2340 of the first outer periphery region contact portion 234. In this example, the barrier metal film 2342 is provided over the entire side and bottom surfaces of the first outer periphery region contact portion 234, but this is not limiting. The barrier metal film 2342 may be provided so as to cover at least the bottom corners 2340, or may be provided so as not to cover the central portion of the bottom surface of the first outer periphery region contact portion 234. The barrier metal film 2342 may extend beyond the contact hole 57 and extend above the interlayer insulating film 38. The material of the barrier metal film 2342 may be titanium, a titanium compound, or the like.

[0316] The plug portion 2344 may be provided in contact with the inner side of the barrier metal film 2342. In this example, the plug portion 2344 is provided by filling the first outer periphery region contact portion 234, but this is not limiting. The plug portion 2344 may be provided in a portion of the first outer periphery region contact portion 234, or may extend beyond the contact hole 57 and extend above the interlayer insulating film 38. When the plug portion 2344 is provided in a portion of the first outer periphery region contact portion 234, the remaining region of the first outer periphery region contact portion 234 may be filled with the same material as the edge metal layer 146. The material of the plug portion 2344 may be a plug metal such as tungsten.

[0317] The side surface of the polycrystalline portion 232 may contact the side surface of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the first outer periphery region contact portion 234. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed of the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 that is provided below the first outer periphery region contact portion 234, the housing portion 198 is a virtual region, as shown by the dotted line in FIG. 21B . In other words, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. In another example, the housing portion 198 may be a third interlayer insulating film 238 that is provided above the semiconductor substrate 10. The housing portion 198 may be formed in the process of providing the third interlayer insulating film 238 and may be formed of the same material as the third interlayer insulating film 238. That is, the housing portion 198 may be integrally formed as part of the third interlayer insulating film 238 .

[0318] In this example, the first outer periphery region contact portion 234 is provided such that the bottom corners 2340 are in contact with the polycrystalline portion 232 and the bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the edge metal layer 146 and the polycrystalline portion 232. If the plug portion 2344 and the barrier metal film 2342 near the center of the bottom surface of the first outer periphery region contact portion 234 are over-etched during the etch-back process of the plug portion 2344, voids may occur inside the first outer periphery region contact portion 234. Even in this case, the electrical connection can be ensured by the barrier metal film 2342 and / or the plug portion 2344 remaining at the bottom corners 2340 of the first outer periphery region contact portion 234.

[0319] In this example, the first outer periphery region contact portion 234 is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the first outer periphery region contact portion 234 near the center of the bottom surface, the influence on the electrical connection between the first outer periphery region contact portion 234 and the polycrystalline portion 232 at the bottom corners 2340 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. In this example, the outer periphery region 230 ensures electrical connection between the first outer periphery region contact portion 234 and the polycrystalline portion 232 via the bottom corners 2340 rather than the bottom center of the first outer periphery region contact portion 234. This ensures stable quality and improved yield, even if a void forms in the region near the center of the first outer periphery region contact portion 234 that contacts the housing portion 198.

[0320] 21C shows an example of an enlarged view of the ff' cross section in FIG. 18B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the first outer periphery region 230. The semiconductor device 100 of this example differs from the embodiment of FIG. 21B in that the housing portion 198 is a region of the field insulating film 148 that is provided below the first outer periphery region contact portion 234. Other aspects may be the same as the embodiment of FIG. 21B.

[0321] 21D shows an example of an enlarged view of the ff' cross section in FIG. 18B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the first outer periphery region 230. The semiconductor device 100 of this example differs from the embodiments of FIGS. 21B and 21C in that a housing portion 198 is provided separately from the interlayer insulating film 38 and the field insulating film 148. In this example, differences from the embodiments of FIGS. 21B and 21C will be particularly described, and the rest may be the same as the embodiment of FIGS. 21B and / or 21C.

[0322] Housing portion 198 may have polysilicon with a lower impurity concentration than contact region 300 of polycrystalline portion 232. Contact region 300 of polycrystalline portion 232 may be a region of polycrystalline portion 232 that is in contact with housing portion 198. For example, housing portion 198 has polysilicon with a lower impurity concentration than polycrystalline portion 232 or undoped polysilicon.

[0323] Figure 22A shows an example of the ff' cross section in Figure 18B. The semiconductor device 100 of this example differs from the embodiment of Figure 19B in that the peripheral region 230 has a housing portion 198, and differs from the embodiment of Figure 21A in that the peripheral region 230 has a first peripheral region trench contact portion 2345 and a second peripheral region trench contact portion 2355. The rest may be the same as the embodiment of Figure 19B and / or Figure 21A.

[0324] Figure 22B shows an example of the ff' cross section in Figure 18B. The semiconductor device 100 of this example differs from the embodiment of Figure 19C in that the periphery region 230 has a housing portion 198, and differs from the embodiment of Figure 22A in that the extension depths of the first periphery region trench contact portion 2345 and the second periphery region trench contact portion 2355 are different. Other aspects may be the same as the embodiments of Figure 19C and / or Figure 22A.

[0325] 22C shows an example of an enlarged view of the ff' cross section in FIG. 18B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230. The semiconductor device 100 of this example differs from the embodiment of FIG. 21B in that the peripheral region 230 has a first peripheral region trench contact portion 2345. In this example, differences from the embodiment of FIG. 21B will be particularly described, and the rest may be the same as the embodiment of FIG. 21B.

[0326] The sidewall of the first outer periphery region contact portion 234 may be in contact with the polycrystalline portion 232 and the interlayer insulating film 38. The polycrystalline portion 232 may be in contact with the sidewall of the first outer periphery region contact portion 234 from the bottom corner 2340 over an area of ​​10% to 90% of the sidewall of the first outer periphery region contact portion 234. In this example, the polycrystalline portion 232 is in contact with the sidewall of the first outer periphery region contact portion 234 over an area of ​​35% of the sidewall of the first outer periphery region contact portion 234 from the bottom corner 2340. That is, in this example, the ratio of length L4 to length L3 is 35%.

[0327] 22D shows an example of an enlarged view of the ff' cross section in FIG. 18B. This figure shows a region in the peripheral region 230 above the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example differs from the embodiment of FIG. 21C in that the peripheral region 230 has a first peripheral region trench contact portion 2345, and differs from the embodiment of FIG. 22C in that the housing portion 198 is a region of the field insulating film 148 that is provided below the first peripheral region contact portion 234. Other aspects may be the same as the embodiment of FIG. 21C and / or FIG. 22C.

[0328] 22E shows an example of an enlarged view of the ff' cross section in FIG. 18B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the periphery region 230. The semiconductor device 100 of this example differs from the embodiment of FIG. 21D in that the periphery region 230 has a first periphery region trench contact portion 2345, and differs from the embodiments of FIGS. 22C and 22D in that a housing portion 198 is provided separately from the interlayer insulating film 38 and the field insulating film 148. The rest may be the same as the embodiments of FIGS. 21D, 22C, and / or 22D.

[0329] Figure 23A shows an example of the ff' cross section in Figure 18B. The semiconductor device 100 of this example differs from the embodiment of Figure 21A in that the first outer periphery region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148. Other aspects may be the same as the embodiment of Figure 21A.

[0330] 23B shows an example of an enlarged view of the ff' cross section in FIG. 18B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230. The semiconductor device 100 of this example differs from the embodiment of FIG. 21B in that the first peripheral region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148. Other aspects may be the same as the embodiment of FIG. 21B.

[0331] 23C shows an example of an enlarged view of the ff' cross section in FIG. 18B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the peripheral region 230. The semiconductor device 100 of this example differs from the embodiment of FIG. 21D in that a first peripheral region contact portion 234 is provided above a polycrystalline portion 232 above a field insulating film 148, and differs from the embodiment of FIG. 23B in that a housing portion 198 is provided separately from the interlayer insulating film 38. The rest may be the same as the embodiment of FIG. 21D and / or FIG. 23B.

[0332] Figure 24A shows an example of the ff' cross section in Figure 18B. The semiconductor device 100 of this example differs from the embodiment of Figure 22A in that the first periphery region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment of Figure 23A in that the periphery region 230 has a first periphery region trench contact portion 2345 and a second periphery region trench contact portion 2355. The rest may be the same as the embodiment of Figure 22A and / or Figure 23A.

[0333] Figure 24B shows an example of the ff' cross section in Figure 18B. The semiconductor device 100 of this example differs from the embodiment of Figure 22B in that the first periphery region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment of Figure 24A in that the extension depths of the first periphery region trench contact portion 2345 and the second periphery region trench contact portion 2355 are different. Other aspects may be the same as the embodiments of Figure 22B and / or Figure 24A.

[0334] 24C shows an example of an enlarged view of the ff' cross section in FIG. 18B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the periphery region 230. The semiconductor device 100 of this example differs from the embodiment of FIG. 22C in that the first periphery region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment of FIG. 23B in that the periphery region 230 has a first periphery region trench contact portion 2345. The rest may be the same as the embodiment of FIG. 22C and / or FIG. 23B.

[0335] 24D shows an example of an enlarged view of the ff' cross section in FIG. 18B. This figure shows a region above the front surface 21 of the semiconductor substrate 10 in the periphery region 230. The semiconductor device 100 of this example differs from the embodiment of FIG. 22E in that the first periphery region contact portion 234 is provided above the polycrystalline portion 232 above the field insulating film 148, and differs from the embodiment of FIG. 23C in that the periphery region 230 has a first periphery region trench contact portion 2345. The rest may be the same as the embodiment of FIG. 22E and / or FIG. 23C.

[0336] FIG. 25 shows an example of the gg' cross section in FIG. 18A. The gg' cross section is an XZ plane passing through the contact hole 53 near the gate pad 112. The gate pad 112 is provided in a pad region 330. The pad region 330 is separated from the main region 220 by a well region 17 or the like, and includes each pad. The pad region 330 may be disposed near the edge 102 of the semiconductor substrate 10. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode 52 in a top view. In another example, the pad region 330 may be provided in a region between multiple separated emitter electrodes 52. When mounting or testing the semiconductor device 100, each pad may be connected to an external circuit via wiring such as a wire. The gate pad 112 is an example of a pad. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, a pad electrode 51, a collector electrode 24, and a pad region contact portion 334 in the gg' cross section.

[0337] The polycrystalline portion 332 is provided above the semiconductor substrate 10. The polycrystalline portion 332 is provided above the front surface 21 of the semiconductor substrate 10 or on the front surface 21 side of the semiconductor substrate 10. The polycrystalline portion 332 in this example is provided above the front surface 21 of the semiconductor substrate 10. The polycrystalline portion 332 in this example is the pad connection portion 125. The polycrystalline portion 332 may be provided above a pad region insulating film 338. The pad region insulating film 338 may be made of the same material as the gate insulating film 42, for example. The pad region insulating film 338 may be a thermal oxide film. The interlayer insulating film 38 is provided above the polycrystalline portion 332.

[0338] The pad region contact portion 334 is provided in the interlayer insulating film 38 above the polycrystalline portion 332. The pad region contact portion 334 may have a contact hole 53 and a metal layer filled in the contact hole 53. The detailed configuration of the pad region contact portion 334 will be described later.

[0339] The polycrystalline portion 332 may be connected to the pad electrode 51 via the pad region contact portion 334. The pad connection portion 125 of this example is connected to the pad electrode 51 via the pad region contact portion 334.

[0340] The pad region contact portion 334 may include a barrier metal film 3342 and a plug portion 3344 provided in the contact hole 53. The barrier metal film 3342 of the pad region contact portion 334 may include titanium, a titanium compound, or the like. The plug portion 3344 of the pad region contact portion 334 may include a plug metal such as tungsten. In this example, the barrier metal film 3342 is provided above the interlayer insulating film 38 and is in contact with the pad electrode 51. In the main region 220, the peripheral region 230, and / or the temperature sensing portion 180, etc., a barrier metal film 2242, a barrier metal film 2342, and / or a barrier metal film 1882 may also be provided above the interlayer insulating film 38. The plug portion 3344 of this example is provided inside the contact hole 53. In another example, the plug portion 3344 may be provided above the barrier metal film 3342 outside the contact hole 53 and in contact with the pad electrode 51, and also in the main region 220, the peripheral region 230, and / or the temperature sensing portion 180, the plug portion 2244, the plug portion 2344, and / or the plug portion 1884 may be provided above the barrier metal film 2242, the barrier metal film 2342, and / or the barrier metal film 1882 outside the contact hole 54, the contact hole 55, the contact hole 56, the contact hole 57, the contact hole 58, and / or the contact hole 59. In yet another example, the barrier metal film 3342 may not be provided above the interlayer insulating film 38, but may be provided only inside the contact hole 53.

[0341] The pad connection portion 125 may be made of the same polycrystalline material as the gate conductive portion 44 and the dummy conductive portion 34. In another example, the pad connection portion 125 may be made of polycrystalline material formed simultaneously with the polycrystalline material constituting the temperature-sensitive diode 183 and made conductive by ion implantation or the like as necessary. The pad region insulating film 338 below the polycrystalline portion 332 may have the same configuration as the second interlayer insulating film 37 of the temperature-sensitive portion 180, rather than the same configuration as the gate insulating film 42. The pad connection portion 125 may be electrically connected to nothing other than the pad electrode 51. In this case, the respective pad connection portions 125 may or may not be connected to each other at locations different from the cross section of FIG. 25 . In this case, the pad electrode 51 may be directly connected to the gate metal layer 50. The pad connection portion 125 may also not be conductive. In another example, the pad connection portion 125 may be electrically connected to something other than the pad electrode 51. In this case, the respective pad connection portions 125 may be connected to each other at locations different from the cross section of FIG. 25 . For example, the pad connection portion 125 may be connected to the connection portion 25. Furthermore, the pad electrode 51 may not be directly connected to the gate metal layer 50 but may be connected via the pad connection portion 125. In this case, the pad connection portion 125 has conductivity and may be connected to the gate metal layer 50 outside the gate pad 112 in top view, and may be connected to the gate metal layer 50 in the same manner as the connection to the pad electrode 51.

[0342] The barrier metal film 3342 may be provided up to the edge of the pad electrode 51. The pad electrode 51 may be provided wider than the edge of the pad connection portion 125. In another example, the pad electrode 51 does not have to be provided up to the edge of the pad connection portion 125.

[0343] The pad region 330 may have a pad region trench contact portion 3345 extending from the upper surface of the interlayer insulating film 38 downward beyond the upper surface of the polycrystalline portion 332 in the depth direction of the semiconductor substrate 10. The pad region trench contact portion 3345 is an example of the pad region contact portion 334. The pad region trench contact portion 3345 is a portion that is deeper toward the back surface 23 of the semiconductor substrate 10 than the upper surface of the polycrystalline portion 332.

[0344] The polycrystalline portion 332 may be connected to the pad electrode 51 via the pad region trench contact portion 3345. The pad connection portion 125 of this example is connected to the pad electrode 51 via the pad region trench contact portion 3345.

[0345] The main region 220 may have a main region trench contact portion 2245 extending from the upper surface of the interlayer insulating film 38 to below the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. Because this figure is a cross-sectional view of the pad region 330, the main region trench contact portion 2245 is not shown. The main region trench contact portion 2245 is, for example, the active trench contact portion 1245 shown in FIG. 4C . The main region trench contact portion 2245 is an example of the main region contact portion 224. The main region trench contact portion 2245 is a portion that is deeper toward the back surface 23 of the semiconductor substrate 10 than the front surface 21 of the semiconductor substrate 10. The main region 220 may have a plurality of main region trench contact portions 2245 provided on the front surface 21 of the semiconductor substrate 10.

[0346] In the depth direction of the semiconductor substrate 10, the extension depth Dp of the pad region trench contact portion 3345 from the upper surface of the polycrystalline portion 332 in the depth direction of the semiconductor substrate 10 is shallower than the extension depth Dt of the multiple main region trench contact portions 2245 from the front surface of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. By making the extension depth Dp of the pad region trench contact portion 3345 shallower than the extension depth Dt of the main region trench contact portion 2245, it is possible to prevent the pad region contact portion 334 from penetrating the pad connection portion 125 and the pad region insulating film 338, thereby preventing insulation between the pad connection portion 125 and the semiconductor substrate 10 from being lost. Furthermore, because the main region trench contact portion 2245 extends deeper than the pad region trench contact portion 3345, latch-up can be suppressed by forming the main region contact portion 224 sufficiently deep in the contact region 15. The pad region trench contact portion 3345 and the main region trench contact portion 2245 may be formed in the same process. However, the pad region trench contact portion 3345 and the main region trench contact portion 2245 may be formed in different processes.

[0347] The contact width Wtp at which the pad region trench contact portion 3345 contacts the polycrystalline portion 332 may be larger than, the same as, or smaller than the contact width Wtt1 of each of the multiple main region trench contact portions 2245. The contact width Wtp of the pad region trench contact portion 3345 may be the width at which the pad region trench contact portion 3345 contacts the upper surface of the polycrystalline portion 332. The contact width Wtt1 of the main region trench contact portion 2245 may be the width at which the active trench contact portion 1245 contacts the upper surface of the mesa portion 71 of the semiconductor substrate 10, as shown in FIG. 4C .

[0348] In another example, the extension depth Dp of the pad region trench contact portion 3345 may be substantially 0. The pad region contact portion 334 may not extend to the pad connection portion 125, and the main region trench contact portion 2245 may extend to a depth Dt.

[0349] Although FIG. 25 illustrates the gate pad 112, the configuration described with respect to the gate pad 112 may also be applied to other pads. For example, the configuration may be used for the anode pad 116, cathode pad 118, sense electrode 114, and / or any pad not shown in FIG. 18A . The pad electrode 51 may be in direct contact with the anode wiring portion 117 or the cathode wiring portion 119, or may be indirectly connected via the polycrystalline portion 332. If the pad is a Kelvin emitter pad (not shown) that has the same potential as the emitter electrode 52, the pad region contact portion 334 may extend from the upper surface of the pad region insulating film 338 in the depth direction of the semiconductor substrate 10. The thickness T of the pad region insulating film 338 below the pad region contact portion 334 may be thinner, or the pad region contact portion 334 may penetrate the pad region insulating film 338 to reach the semiconductor substrate 10. Note that although the XZ cross section has been described using FIG. 25 , the longitudinal direction of the contact hole 53 does not have to be the Y-axis direction. For example, the longitudinal direction of the contact holes 53 may be the X-axis direction or any other direction, and contact holes 53 oriented in different directions may be combined and used.

[0350] 26 shows an example of the gg' cross section in FIG. 18A. The semiconductor device 100 of this example differs from the embodiment of FIG. 25 in that the pad region 330 has a recess region 336. In this example, differences from the embodiment of FIG. 25 will be particularly described, and the rest may be the same as the embodiment of FIG. 25. In other words, the contact depth Dp of the pad region contact portion 334 may be shallower than the contact depth of the main region contact portion 224.

[0351] The pad region 330 may have a recess region 336 in which a depression is provided in the upper surface of the semiconductor substrate 10. The polycrystalline portion 332 may be provided in the recess region 336. In this example, the polycrystalline portion 332 is provided on the front surface 21 side of the semiconductor substrate 10. In the depth direction of the semiconductor substrate 10, the height position of the upper surface of the interlayer insulating film 38 in the main region 220 may be the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 336. The height positions being the same may include the height positions being approximately (substantially) the same. The height positions being approximately (substantially) the same may mean that the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the main region 220 and the distance from the front surface 21 of the semiconductor substrate 10 to the upper surface of the interlayer insulating film 38 in the recess region 336 are within 20% of the average value of both the distances, or may be within 10% of the average value.

[0352] When the height position of the upper surface of the interlayer insulating film 38 in the main region 220 is approximately the same as the height position of the upper surface of the interlayer insulating film 38 in the recess region 336, the main region contact portion 224 and the pad region contact portion 334 can be formed simultaneously using the same etching process. That is, if the upper surfaces of both the interlayer insulating film 38 in the main region 220 and the interlayer insulating film 38 in the recess region 336 are at the same height from the front surface 21 of the semiconductor substrate 10, there is no deviation in the focus of exposure during the photolithography process. This reduces the dimensional tolerances of the interlayer insulating film 38, the emitter electrode 52, and the like. Furthermore, the main region contact portion 224 and the pad region contact portion 334 can be formed with the same dimensional tolerances. This allows for easier manufacturing with fewer processes than when each contact portion is formed in separate processes. However, the main region contact portion 224 and the pad region contact portion 334 may be formed in different processes.

[0353] Figure 27 shows an example of a cross section taken along line gg' in Figure 18A. The semiconductor device 100 of this example differs from the embodiment of Figure 25 in that the pad region 330 has a housing portion 198. In this example, differences from the embodiment of Figure 25 will be particularly described, and the rest may be the same as the embodiment of Figure 25.

[0354] The housing portion 198 is provided below the pad region contact portion 334. The material of the housing portion 198 may be the same as that of the interlayer insulating film 38.

[0355] A bottom corner 3340 of the pad region contact portion 334 may be in contact with the polycrystalline portion 332. The bottom corner 3340 of the pad region contact portion 334 may be the intersection of the bottom surface of the pad region contact portion 334 and the side surface of the pad region contact portion 334. The bottom corner 3340 being in contact with the polycrystalline portion 332 may be in contact with the polycrystalline portion 332 on the top surface of the polycrystalline portion 332, may be in contact with the polycrystalline portion 332 on the side surface of the polycrystalline portion 332, or may be in contact with the polycrystalline portion 332 in an internal region of the polycrystalline portion 332. In this example, the bottom corner 3340 is in contact with the polycrystalline portion 332 on the top surface of the polycrystalline portion 332.

[0356] The pad area contact portion 334 of this example has two bottom corners 3340. One of the two bottom corners 3340 may be in contact with the polycrystalline portion 332. The other of the two bottom corners 3340 may be in contact with the housing portion 198, or may not be in contact with the housing portion 198. The pad area contact portion 334 of this example has one bottom corner 3340a in contact with the polycrystalline portion 332 and the other bottom corner 3340b in contact with the housing portion 198.

[0357] The bottom surface of the pad area contact portion 334 may be in contact with the housing portion 198. The bottom surface of the pad area contact portion 334 may be the surface between two bottom corner portions 3340 of the pad area contact portion 334. The bottom surface of the pad area contact portion 334 in contact with the housing portion 198 may be in contact with the housing portion 198 at the top surface of the housing portion 198, or may be in contact with the housing portion 198 in an area inside the housing portion 198. In this example, the bottom surface of the pad area contact portion 334 is in contact with the housing portion 198 at the top surface of the housing portion 198.

[0358] The bottom surface of the pad area contact portion 334 may be in contact with the polycrystalline portion 332 and the housing portion 198. In the present example, one bottom corner portion 3340 a of the pad area contact portion 334 is in contact with the polycrystalline portion 332, and the other bottom corner portion 3340 b is in contact with the housing portion 198, so that the bottom surface of the pad area contact portion 334 is in contact with the polycrystalline portion 332 and the housing portion 198.

[0359] The polycrystalline portion 332 may contact the bottom surface of the pad region contact portion 334 from the bottom corner 3340 to an area of ​​10% to 40% of the bottom surface of the pad region contact portion 334. That is, the area ratio of the surface of the bottom surface of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 to the area of ​​the bottom surface of the pad region contact portion 334 may be 10% to 40%. Referring to FIG. 27 , length L1 is the length of the bottom surface of the pad region contact portion 334 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Length L2 is the length of the bottom surface of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L2 to length L1 may be 10% to 40%. In this example, the polycrystalline portion 332 contacts the bottom surface of the pad region contact portion 334 from the bottom surface corner 3340a to an area that is 20% of the bottom surface of the pad region contact portion 334. That is, in this example, the ratio of the length L2 to the length L1 is 20%.

[0360] The pad region contact portion 334 may have a barrier metal film 3342 and a plug portion 3344. In this example, the barrier metal film 3342 and the plug portion 3344 are formed of different materials, but they may also be formed of the same material.

[0361] The barrier metal film 3342 may be provided on the bottom corners 3340 of the pad region contact portion 334. In this example, the barrier metal film 3342 is provided over the entire side and bottom surfaces of the pad region contact portion 334, but this is not limiting. The barrier metal film 3342 may be provided so as to cover at least the bottom corners 3340, or may be provided so as not to cover the central portion of the bottom surface of the pad region contact portion 334. The barrier metal film 3342 may extend beyond the contact hole 53 and extend above the interlayer insulating film 38. The material of the barrier metal film 3342 may be titanium, a titanium compound, or the like.

[0362] The plug portion 3344 may be provided in contact with the inner side of the barrier metal film 3342. In this example, the plug portion 3344 is provided by filling the pad region contact portion 334, but this is not limiting. The plug portion 3344 may be provided in a part of the pad region contact portion 334, or may extend beyond the contact hole 56 and extend above the interlayer insulating film 38. When the plug portion 3344 is provided in a part of the pad region contact portion 334, the remaining region of the pad region contact portion 334 may be filled with the same material as the pad electrode 51. The material of the plug portion 3344 may be a plug metal such as tungsten.

[0363] The side of the polycrystalline portion 332 may contact the side of the housing portion 198. The housing portion 198 may be a region of the interlayer insulating film 38 that is provided below the pad region contact portion 334. The housing portion 198 may be formed in the process of providing the interlayer insulating film 38 and may be formed of the same material as the interlayer insulating film 38. When the housing portion 198 is formed as a region of the interlayer insulating film 38 that is provided below the pad region contact portion 334, the housing portion 198 may be a virtual region. As an example, the housing portion 198 may be formed integrally as part of the interlayer insulating film 38. As another example, the housing portion 198 may be polysilicon having a lower impurity concentration than the polycrystalline portion 332 or undoped polysilicon. As another example, the housing portion 198 may be the pad region insulating film 338 that is provided above the semiconductor substrate 10. In this case, the housing portion 198 may be formed in the process of providing the pad region insulating film 338 and may be formed of the same material as the pad region insulating film 338. That is, the housing portion 198 may be integrally formed as part of the pad region insulating film 338 .

[0364] In this example, the pad region contact portion 334 is provided such that the bottom corners 3340 are in contact with the polycrystalline portion 332 and the bottom surface is in contact with the housing portion 198. This ensures reliable electrical connection between the pad electrode 51 and the polycrystalline portion 332. If the plug portion 3344 and the barrier metal film 3342 near the center of the bottom surface of the pad region contact portion 334 are over-etched and removed in the etch-back process of the plug portion 3344, voids may occur inside the pad region contact portion 334. Even in this case, the electrical connection can be ensured by the barrier metal film 3342 and / or the plug portion 3344 remaining at the bottom corners 3340 of the pad region contact portion 334.

[0365] The pad region contact portion 334 in this example is provided with its bottom surface in contact with the housing portion 198. Therefore, even if a void occurs inside the pad region contact portion 334 near the center of the bottom surface, the influence on the electrical connection at the bottom corners 3340 between the pad region contact portion 334 and the polycrystalline portion 332 is suppressed. This improves the yield of semiconductor devices 100 having desired characteristics. The pad region 330 in this example ensures electrical connection between the pad region contact portion 334 and the polycrystalline portion 332 through the bottom corners 3340 rather than the bottom center of the pad region contact portion 334. This ensures stable quality and improved yield, even if a void forms in the region near the center of the pad region contact portion 334 that contacts the housing portion 198.

[0366] Fig. 28 shows an example of the gg' cross section in Fig. 18A. The semiconductor device 100 of this example differs from the embodiment of Fig. 27 in that the pad region 330 has a pad region trench contact portion 3345. Other aspects may be the same as the embodiment of Fig. 27.

[0367] The sidewall of the pad region contact portion 334 may be in contact with the polycrystalline portion 332 and the interlayer insulating film 38. The polycrystalline portion 332 may be in contact with the sidewall of the pad region contact portion 334 from the bottom corner 3340 over an area of ​​10% to 90% of the sidewall of the pad region contact portion 334. That is, the ratio of the area of ​​the sidewall of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 to the area of ​​the sidewall of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 may be 10% to 90%. Referring to FIG. 28 , length L3 is the length of the sidewall of the pad region contact portion 334 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10, and length L4 is the length of the sidewall of the pad region contact portion 334 that is in contact with the polycrystalline portion 332 in a cross section perpendicular to the front surface 21 of the semiconductor substrate 10. Therefore, the ratio of length L4 to length L3 may be 10% or more and 90% or less. In this example, polycrystalline portion 232 contacts the sidewall of pad region contact portion 334 from bottom corner 3340 to 35% of the sidewall of pad region contact portion 334. That is, in this example, the ratio of length L4 to length L3 is 35%.

[0368] FIG. 29 shows an example of electrical connections between the various components of the semiconductor device 100. In this example, a Zener diode 170 is provided in anti-parallel between the cathode pad 118 and the anode pad 116 to protect against voltage breakdown. The Zener diode 170 may have a configuration similar to that of the temperature-sensitive diode 183. In this case, the forward voltage of the Zener diode 170 may differ from that of the temperature-sensitive diode 183. When the temperature-sensitive diode 183 is composed of a plurality of temperature-sensitive cathode regions 181 and temperature-sensitive anode regions 182 connected in series, the Zener diode 170 may be provided between each of the temperature-sensitive cathode regions 181 and the temperature-sensitive anode region 182. Furthermore, when the Zener diode 170 is provided between the temperature-sensitive section 180 and the active section 120 for field protection, the Zener diode 170 may have a configuration similar to that of the temperature-sensitive diode 183. In this case, the breakdown voltage of the Zener diode 170 may differ from that of the temperature-sensitive diode 183. A plurality of Zener diodes 170 may be connected in series. In other examples, the Zener diodes 170 may be connected in different positions, or the Zener diode 170 may not be provided.

[0369] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0370] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0371] 10: Semiconductor substrate, 12: Emitter region, 14: Base region, 15: Contact region, 16: Accumulation region, 17: Well region, 18: Drift region, 20: Buffer region, 21: Front surface, 22: Collector region, 23: Back surface, 24: Collector electrode, 25: Connection portion, 30: Dummy trench portion, 31: Extension portion, 32: Dummy insulating film, 33: Connection portion, 34: Dummy conductive portion, 36: First interlayer insulating film, 37: Second interlayer insulating film, 38: Interlayer insulating film, 40: Gate trench portion, 41...extension portion, 42...gate insulating film, 43...connection portion, 44...gate conductive portion, 50...gate metal layer, 51...pad electrode, 52...emitter electrode, 53...contact hole, 54...contact hole, 55...contact hole, 56...contact hole, 57...contact hole, 58...contact hole, 59...contact hole, 70...transistor portion, 71...mesa portion, 80...diode portion, 81...mesa portion, 82...cathode region, 90...boundary portion, 91...mesa 1. Sub-section, 100: semiconductor device, 102: edge, 112: gate pad, 114: sense electrode, 115: current sense section, 116: anode pad, 117: anode wiring section, 118: cathode pad, 119: cathode wiring section, 120: active section, 122: active trench section, 124: active contact section, 125: pad connection section, 140: edge termination structure section, 142: guard ring, 144: field plate, 146: edge metal layer, 148: field insulating film, 151: backside Front surface side lifetime control region, 152...front surface side lifetime control region, 170...zener diode, 180...temperature sensing portion, 181...temperature sensing cathode region, 182...temperature sensing anode region, 183...temperature sensing diode, 188...temperature sensing contact portion, 194...recess region, 196...insulating film, 198...housing portion, 200...dent, 220...main region, 224...main region contact portion, 230...periphery region, 232...polycrystalline portion, 234...first peripheral region contact portion, 235...second peripheral region contact portion,236: Recess region, 238: Third interlayer insulating film, 300: Contact region, 330: Pad region, 332: Polycrystalline portion, 336: Recess region, 334: Pad region contact portion, 338: Pad region insulating film, 1241: First active contact portion, 1242: Second active contact portion, 1243: Barrier metal film, 1244: Plug portion, 1245: Active trench contact portion, 1420: Non-corner region, 1422: Corner region, 1880: Bottom corner portion, 1882: Barrier metal film, 1884: Plug portion, 1885...temperature-sensitive trench contact portion, 2242...barrier metal film, 2244...plug portion, 2245...main region trench contact portion, 2340...bottom corner portion, 2342...barrier metal film, 2344...plug portion, 2345...first outer periphery region trench contact portion, 2352...barrier metal film, 2354...plug portion, 2355...second outer periphery region trench contact portion, 3340...bottom corner portion, 3342...barrier metal film, 3344...plug portion, 3345...pad region trench contact portion,

Claims

1. A semiconductor device comprising a main region and a peripheral region, the main region has a plurality of main region trench contacts provided on a front surface of a semiconductor substrate of a first conductivity type; The outer peripheral region is a polycrystalline portion provided above the semiconductor substrate; an interlayer insulating film provided above the polycrystalline portion; a first outer periphery region trench contact portion extending from an upper surface of the interlayer insulating film to a position below an upper surface of the polycrystalline portion in a depth direction of the semiconductor substrate; and In the depth direction of the semiconductor substrate, an extension depth of the first outer periphery region trench contact portion from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate is shallower than an extension depth of the plurality of main region trench contact portions from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate. Semiconductor device.

2. the peripheral region has a recess region in which a depression is provided in the upper surface of the semiconductor substrate, The polycrystalline portion is provided in the recess region. The semiconductor device according to claim 1 .

3. A contact width where the first outer peripheral region trench contact portion contacts the polycrystalline portion is larger than each of the contact widths of the plurality of main region trench contact portions. The semiconductor device according to claim 1 .

4. A contact width where the first outer peripheral region trench contact portion contacts the polycrystalline portion is smaller than each of the contact widths of the plurality of main region trench contact portions. The semiconductor device according to claim 1 .

5. a gate trench portion provided on the front surface of the semiconductor substrate and having a gate conductive portion; a gate metal layer provided above the semiconductor substrate and electrically connected to the gate conductive portion; Equipped with The polycrystalline portion is the first peripheral region trench contact portion is connected to the gate metal layer; connected to the gate conductive portion The semiconductor device according to claim 1 .

6. a dummy trench portion provided on the front surface of the semiconductor substrate and having a dummy conductive portion; an emitter electrode provided above the semiconductor substrate and electrically connected to the semiconductor substrate; Equipped with The polycrystalline portion is connected to the emitter electrode via the first outer peripheral region trench contact portion, connected to the dummy conductive portion The semiconductor device according to claim 1 .

7. a second conductivity type guard ring provided on the front surface of the semiconductor substrate between the main region and an edge of the semiconductor substrate; an edge metal layer provided above the semiconductor substrate and electrically connected to the guard ring; Equipped with The polycrystalline portion is connected to the edge metal layer through the first outer periphery region trench contact portion. The semiconductor device according to claim 1 .

8. the peripheral region has a second peripheral region trench contact portion extending from an upper surface of the interlayer insulating film to a position below an upper surface of the semiconductor substrate in a depth direction of the semiconductor substrate in a region where the polycrystalline portion is not provided, The extension depth of the first outer periphery region trench contact portion from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate is shallower than the extension depth of the second outer periphery region trench contact portion from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate. The semiconductor device according to claim 7 .

9. the peripheral region has a second peripheral region trench contact portion extending from an upper surface of the interlayer insulating film to a position below an upper surface of the semiconductor substrate in a depth direction of the semiconductor substrate in a region where the polycrystalline portion is not provided, An extension depth of the first periphery region trench contact portion extending from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate and an extension depth of the second periphery region trench contact portion extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate are shallower than an extension depth of the plurality of main region trench contact portions extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate. The semiconductor device according to claim 7 .

10. A semiconductor device comprising a main region and a pad region, the main region has a plurality of main region trench contacts provided on a front surface of a semiconductor substrate of a first conductivity type; The pad area is pads for connecting to external circuits; a polycrystalline portion provided above the semiconductor substrate; an interlayer insulating film provided above the polycrystalline portion; a pad region trench contact portion extending from the upper surface of the interlayer insulating film to a position below an upper surface of the polycrystalline portion in a depth direction of the semiconductor substrate; and In the depth direction of the semiconductor substrate, the extension depth of the pad region trench contact portion from the upper surface of the polycrystalline portion in the depth direction of the semiconductor substrate is shallower than the extension depth of the plurality of main region trench contact portions from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate. Semiconductor device.