Semiconductor device and manufacturing method for same

Abstract

The present invention provides a semiconductor device comprising: a drift region, drain region, and source region of a first conductivity type; a well region of a second conductivity type; a control electrode disposed via an insulating film inside a groove formed in a major surface of a substrate; and an electric field relaxation region of the second conductivity type disposed below the bottom of the groove. The source region, well region, and drift region are in contact with a lateral surface of the groove. Part of the electric field relaxation region extends from the lateral surface of the groove to the drift region side. The second conductivity type impurity concentration in the electric field relaxation region is higher than the second conductivity type impurity concentration in the well region.

Description

Semiconductor device and manufacturing method thereof

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] Patent Document 1 discloses a trench-gate MOSFET in which a trench is formed in a semiconductor substrate and a control electrode is provided inside the formed trench. An N-type drift region and a P-type drift region are disposed in the drift region through which the main current flows. The thicknesses of the N-type and P-type drift regions are selected so that the N-type and P-type drift regions become substantially complete depletion layers when a voltage lower than the rated voltage is applied between the main electrodes of the MOSFET, thereby increasing the breakdown voltage.

[0003] JP 2006-303543 A

[0004] However, since the N-type drift region and the P-type drift region become substantially completely depleted layers, the electric field due to the drain voltage is concentrated at the edge of the trench gate, resulting in a decrease in breakdown voltage.

[0005] The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a semiconductor device and a manufacturing method thereof that can alleviate electric field concentration at the end of a control electrode arranged inside a groove.

[0006] A semiconductor device according to one aspect of the present invention includes a first conductivity type drift region, a drain region, and a source region, a second conductivity type well region, a control electrode disposed within a trench formed from a main surface of a substrate via an insulating film, and a second conductivity type electric field relaxation region disposed below the bottom of the trench. The source region, the well region, and the drift region are in contact with a side surface of the trench. A portion of the electric field relaxation region extends from the side surface of the trench toward the drift region. The second conductivity type impurity concentration of the electric field relaxation region is higher than the second conductivity type impurity concentration of the well region.

[0007] According to one aspect of the present invention, it is possible to reduce the electric field concentration at the end of the control electrode disposed inside the groove.

[0008] FIG. 1 is a cross-sectional perspective view showing the structure of a semiconductor device 100 according to the first embodiment. FIG. 2 is a cross-sectional view showing the XY cross-section of the semiconductor device 100 of FIG. 1 . FIG. 3 is a cross-sectional view showing the XY cross-section of the semiconductor device 100 of FIG. 1 , in which the end 12 a of the electric field reduction region 12 is extended to the center of the P-type column region 51. FIG. 4A is a cross-sectional perspective view showing a manufacturing process of the semiconductor device 100 of FIG. 1 (part 1). FIG. 4B is a cross-sectional perspective view showing a manufacturing process of the semiconductor device 100 of FIG. 1 (part 2). FIG. 4C is a cross-sectional perspective view showing a manufacturing process of the semiconductor device 100 of FIG. 1 (part 3). FIG. 4D is a cross-sectional perspective view showing a manufacturing process of the semiconductor device 100 of FIG. 1 (part 4). FIG. 4E is a cross-sectional perspective view showing a manufacturing process of the semiconductor device 100 of FIG. 1 (part 5). FIG. 4F is a cross-sectional perspective view showing a manufacturing process of the semiconductor device 100 of FIG. 1 (part 6). FIG. 4G is a cross-sectional perspective view showing a manufacturing process of the semiconductor device 100 of FIG. 1 (part 7). FIG. 5 is a cross-sectional view showing the XY cross-sectional structure of a semiconductor device 100A according to a first modification of the first embodiment. FIG. 6 is a plan view of a semiconductor device 100B according to a second modification of the first embodiment, viewed from the X direction. FIG. 7 is a cross-sectional view showing the XY cross-sectional structure of a semiconductor device 102 according to a second embodiment. FIG. 8A is a cross-sectional perspective view (part 1) showing a manufacturing process of the semiconductor device 102 of FIG. 7. FIG. 8B is a cross-sectional perspective view (part 2) showing a manufacturing process of the semiconductor device 102 of FIG. 7. FIG. 9 is a cross-sectional perspective view showing the structure of a semiconductor device 103 according to a third embodiment.

[0009] The embodiments will be described with reference to the drawings. In the drawings, the same parts are designated by the same reference numerals, and the description thereof will be omitted. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each part, etc. may differ from the actual ones. Furthermore, the drawings may include parts with different dimensional relationships or ratios.

[0010] Furthermore, the embodiments described below are merely examples of devices or methods for embodying the technical ideas, and are not intended to limit the shape, structure, arrangement, etc. of the components to those described below. Various modifications can be made to these embodiments within the scope of the claims.

[0011] First Embodiment [Structure of Semiconductor Device] A semiconductor device 100 according to the embodiment is a metal-oxide-semiconductor field effect transistor (MOSFET) having a trench gate structure and a lateral structure. FIG. 1 is a cross-sectional perspective view showing the structure of a semiconductor device according to the first embodiment. FIG. 1 shows a unit cell structure of a MOSFET. In an actual device, unit cell structures are repeated in the Z direction, and structures that are plane-symmetric with respect to the Y-direction side surfaces of the unit cell structures are repeated in the Y direction.

[0012] 1 , the semiconductor device 100 includes a substrate 1, a first conductivity type drift region 7, a first conductivity type drain region 10, a second conductivity type well region 3, a first conductivity type source region 9, a second conductivity type column region 5, and a second conductivity type electric field relaxation region 12. The semiconductor device 100 also includes a drain electrode 17 and a control electrode 15 joined to the drain region 10, a source electrode 16 and a control electrode 15 joined to the source region 9.

[0013] The first conductivity type and the second conductivity type are different from each other. That is, if the first conductivity type is P type, the second conductivity type is N type, and if the first conductivity type is N type, the second conductivity type is P type. In this embodiment, a case where the first conductivity type is N type and the second conductivity type is P type will be described.

[0014] The substrate 1 is an insulating semiconductor substrate. This simplifies the element isolation process when integrating multiple semiconductor devices on the same substrate 1. Here, an insulating substrate refers to a substrate having a resistivity of several kΩ cm or more. However, the substrate 1 may also be a semi-insulating semiconductor substrate.

[0015] For example, an insulating silicon carbide substrate (SiC substrate) can be used for the substrate 1. SiC is a wide bandgap semiconductor with a small number of intrinsic carriers, so it is easy to obtain high insulating properties, and a semiconductor device 100 with high breakdown voltage can be realized. There are several polytypes (crystal polymorphs) of SiC, and a typical 4H SiC substrate of the hexagonal system can be used for the substrate 1. By using a SiC substrate for the substrate 1, the insulating properties of the substrate 1 can be increased.

[0016] Furthermore, the substrate 1 is not limited to a SiC substrate, and may be a semiconductor substrate made of a semiconductor material with a wide band gap, such as III-V compound semiconductors using nitrogen as a group V element, such as GaN (gallium nitride), AlN (aluminum nitride), AlGaN (aluminum gallium nitride), and indium nitride (InN), as well as diamond and ZnO (zinc oxide).

[0017] The N-type drift region 7 is formed in the substrate 1 in contact with the main surface 1a of the substrate 1, and is a region through which the main current of the semiconductor device flows when the semiconductor device is in an on-state. The drift region 7 is in contact with the P-type well region 3 and also with the N+-type drain region 10. The well region 3 and the drain region 10 are not in direct contact with each other, but are electrically connected via the drift region 7. The N-type impurity concentration of the drift region 7 is, for example, 1×10 １５ / cm ３ 1x10 or more １９ / cm ３ The drift region 7 is preferably formed from a wide bandgap semiconductor, which can achieve both low on-resistance and a high breakdown field. The substrate 1, well region 3, and drift region 7 may be formed from the same material. This prevents performance degradation due to lattice mismatch and the like that occurs when different materials are used.

[0018] An N+ type drain region 10 is formed in the substrate 1 in contact with the drift region 7. The N type impurity concentration of the drain region 10 is higher than that of the drift region 7, for example, 1×10 １８ / cm ３ 1x10 or more２１ / cm ３ The following is an explanation. In this specification, "N+ type" indicates that the N-type impurity concentration is high. Similarly, "P+ type" indicates that the P-type impurity concentration is high. The drain region 10 is joined to the drain electrode 17 on the main surface 1a of the substrate 1. The junction between the drain region 10 and the drain electrode 17 forms a metal-semiconductor junction that does not have a rectifying effect, a so-called ohmic contact.

[0019] The P-type well region 3 is formed in the substrate 1 in contact with the drift region 7. The contact surface between the well region 3 and the drift region 7 forms a PN junction. The P-type impurity concentration of the well region 3 is, for example, 1×10 １５ / cm ３ 1x10 or more １９ / cm ３ Like the drift region 7, the well region 3 is preferably formed of a wide bandgap semiconductor, which can achieve both a low on-resistance and a high breakdown field.

[0020] An N+ type source region 9 is formed in the substrate 1 in contact with the well region 3. The contact surface between the source region 9 and the well region 3 forms a PN junction. The N type impurity concentration of the source region 9 is higher than that of the drift region 7, for example, 1×10 １８ / cm ３ 1x10 or more ２１ / cm ３ The source region 9 is in contact with the source electrode 16 on the main surface 1a of the substrate 1. The contact between the source region 9 and the source electrode 16 forms an ohmic contact.

[0021] The control electrode 15 is disposed within a groove 13 formed in the substrate 1 from the main surface 1a of the substrate 1 via an insulating film 14. The control electrode 15 may be made of, for example, polycrystalline silicon doped with a high concentration of N-type or P-type impurities. The insulating film 14 contacts the side surface 13a and bottom 13b of the groove 13. The control electrode 15 contacts the insulating film 14 and backfills the entire groove 13. The control electrode 15 does not directly contact the side surface 13a or bottom 13b of the groove 13. The bottom 13b may have a flat or curved surface. In the semiconductor device 100, the bottom 13b has a flat bottom. The depth of the groove 13 and the depth of the drift region 7 may be the same or different. In the semiconductor device 100, the bottom 13b of the groove 13 is located in the same depth direction as the bottom of the drift region 7.

[0022] The source region 9, well region 3, and drift region 7 are in contact with the side surface 13a of the trench 13. In other words, the source region 9, well region 3, and drift region 7 are in contact with the control electrode 15 at the side surface 13a of the trench 13 via the insulating film 14. From the main surface 1a of the substrate 1 toward the depth direction of the trench 13 (the opposite direction to the X direction), the source region 9, well region 3, and drift region 7 are in contact with the side surface 13a of the trench 13 in this order. The MOS structure of the semiconductor device 100 corresponds to a structure in which the control electrode 15 and the well region 3 sandwich the insulating film 14.

[0023] The P+ type electric field relaxation region 12 is disposed in the substrate 1 below the bottom 13b of the trench 13. "Disposed below the bottom 13b of the trench 13" includes both being disposed in contact with the bottom of the bottom 13b of the trench 13 and being disposed below and spaced apart from the bottom 13b of the trench 13. In the semiconductor device 100 shown in FIG. 1 , the electric field relaxation region 12 is disposed in contact with the bottom of the bottom 13b of the trench 13. In other words, the electric field relaxation region 12 is disposed in contact with the bottom of the insulating film 14 that is in contact with the bottom 13b of the trench 13. The P type impurity concentration of the electric field relaxation region 12 is higher than that of the well region 3, for example, 1×10 １８ / cm ３ 1x10 or more ２１ / cm ３ The following is the result.

[0024] The electric field relaxation region 12 extends from the side surface 13a of the trench 13 toward the drift region 7, i.e., in the Y direction. Although not shown in the drawing, the electric field relaxation region 12 extends in the Z direction while maintaining the cross-sectional shape of the cross-sectional perspective view of FIG. 1, i.e., the shape shown in FIG. 2. In other words, when viewed from the X direction, the electric field relaxation region 12 in FIG. 1 has a rectangular shape that overlaps with the trench 13 and part of the source region 9. Furthermore, the extension 12L of the electric field relaxation region 12 contacts the bottom of the drift region 7, forming a PN junction. This is because the bottom 13b of the trench 13 is located in the same depth direction as the bottom of the drift region 7.

[0025] The length of extension 12L of electric field relaxation region 12, which extends from side surface 13a of trench 13 toward drift region 7, is a length that can block the electric field applied from drain region 10 to end EF (see FIG. 2) of trench 13 when a voltage is applied between source region 9 and drain region 10. Extension 12L of electric field relaxation region 12 blocks the electric field applied from drain region 10 to end EF of trench 13 when a voltage is applied between source region 9 and drain region 10, thereby mitigating electric field concentration at the end of control electrode 15 disposed inside trench 13. Note that end EF of trench 13 refers to the portion of side surface 13a of trench 13 that contacts drift region 7, as shown in FIG. 2.

[0026] 2 and 3 , the end 12 a of the electric field relaxation region 12 extending toward the drift region 7 needs only to be located within a range from the side surface 13 a of the trench 13 to the center of the P-type column region 51 in the direction MC of the main current of the semiconductor device 100 flowing through the drift region 7. Simulation results performed by the inventors of the present application have revealed that if the end 12 a of the electric field relaxation region 12 is located within this range, the effect of relaxing the electric field concentration at the end of the control electrode 15 can be obtained. If the end 12 a of the electric field relaxation region 12 does not extend beyond the side surface 13 a of the trench 13 toward the drift region 7, the effect of relaxing the electric field concentration at the end of the control electrode 15 cannot be obtained. Furthermore, if the end 12 a of the electric field relaxation region 12 extends beyond the center of the P-type column region 51 toward the drain region 10, punch-through occurs between the drain region 10 and the electric field relaxation region 12, leading to a deterioration in breakdown voltage.

[0027] As shown in FIGS. 1 to 3, the P-type column region 5 is formed in a part of the drift region 7. The P-type column region 5 is in contact with the well region 3 and extends along the direction MC in which the main current of the semiconductor device flows. The P-type impurity concentration of the P-type column region 5 is, for example, 1×10 １５ / cm ３ 1x10 or more １９ / cm ３ The P-type column region 5 has multiple P-type column regions 51, 52. The number of P-type column regions 51, 52 is not limited to two and may be three or more. An N-type drift region 7 is disposed between the P-type column regions 51, 52. The P-type column regions 51, 52 and the N-type drift region 7 between the P-type column regions 51, 52 form a super junction (SJ) structure in which the P-type column regions 51, 52 and the N-type drift region 7 between the P-type column regions 51, 52 are alternately disposed in a direction (Z direction) perpendicular to the direction MC in which the main current of the semiconductor device 100 flows. The shape and impurity concentration conditions of each region for the P-type column regions 51, 52 and the drift region 7 therebetween to form a super junction (SJ) structure will be described later.

[0028] The P-type column region 5 is not connected to the drain region 10, and an end of the P-type column region 5 faces the drain region 10 via the drift region 7. The P-type column region 51 contacts the main surface 1a of the substrate 1 and also extends in the depth direction of the substrate 1 (the opposite direction to the X direction). The depth length of the P-type column region 5 can be set arbitrarily as long as the P-type column region 5 does not contact the electric field relaxation region 12. For example, as shown in FIGS. 2 and 3, the depth length of the P-type column region 5 may be approximately half that of the well region 3. Alternatively, as shown in FIGS. 1 and 2, if the end 12a of the electric field relaxation region 12 is located closer to the control electrode 15 than the side surface of the well region 3 on the drift region 7 side, the P-type column region 51 may extend to the interface between the substrate 1 and the drift region 7. Although only the P-type column region 51 has been shown in FIGS. 2 and 3, the other P-type column regions 52 and the like included in the P-type column region 5 are the same as the P-type column region 51.

[0029] The source electrode 16 is formed on the main surface 1a of the substrate 1 and is electrically connected to the source region 9. The drain electrode 17 is formed on the main surface 1a of the substrate 1 and is electrically connected to the drain region 10.

[0030] The operation of the semiconductor device 100 shown in FIGS. 1 to 3 will be described below.

[0031] When a positive potential is applied to the drain electrode 17 with the source electrode 16 set as a reference potential, a depletion layer spreads from the interface between the drift region 7 and the P-type column region 5, and when the voltage increases to a certain level, the drift region 7 and the P-type column region 5 enter a completely depleted state (pinch-off state). The pinch-off state causes the electric field distribution in the drift region 7 and the P-type column region 5 to become a uniform rectangular distribution, significantly reducing the maximum electric field applied to the semiconductor device 100. This improves the breakdown voltage of the semiconductor device 100.

[0032] In order to completely deplete the SJ structure, it is necessary to set the ratio between the total amount of N-type impurities in the N-type semiconductor region and the total amount of P-type impurities in the P-type semiconductor region to close to 1. In order to achieve this charge balance, the concentration (donor concentration) Nd of the N-type impurity in the drift region 7, the concentration (acceptor concentration) Na of the P-type impurity in the P-type column region 5, the width Wn of the drift region 7 sandwiched between the P-type column regions 5, and the width Wp of the P-type column region 5 are set to satisfy the following formula (1). The widths Wn and Wp are widths in the direction (Z direction) in which the drift region 7 and the P-type column regions 5 are alternately arranged.

[0033] Na×Wp=Nd×Wn (1) By setting the impurity concentrations of the drift region 7 and the P-type column region 5 so as to satisfy formula (1), it is possible to achieve a charge balance between the P-type impurities and the N-type impurities at the interface between the drift region 7 and the P-type column region 5. As a result, the drift region 7 and the P-type column region 5 are depleted by a depletion layer extending from the interface between the drift region 7 and the P-type column region 5, thereby obtaining a high breakdown voltage. Furthermore, by increasing the impurity concentration of the drift region 7 while satisfying the relationship of formula (1), it is possible to lower the resistance value of the drift region 7, and therefore the on-resistance.

[0034] By controlling the potential of the control electrode 15 while applying a positive potential to the drain electrode 17 with the source electrode 16 as a reference potential, the semiconductor device 100 functions as a transistor. That is, when the voltage between the control electrode 15 and the source electrode 16 is set to a predetermined threshold voltage or higher, electrons, which are minority carriers, are attracted to the well region 3 that contacts the control electrode 15 via the insulating film 14, forming an N-type inversion layer. The connection between the source region 9 and the drift region 7 by the N-type inversion layer turns the semiconductor device 100 on, and a current flows from the drain electrode 17 to the source electrode 16. When the voltage between the control electrode 15 and the source electrode 16 is set to a value less than the predetermined threshold voltage, the N-type inversion layer disappears, the semiconductor device 100 turns off, and the current from the drain electrode 17 to the source electrode 16 is cut off.

[0035] In the off state, an electric field is generated inside the substrate 1 by applying a positive potential to the drain electrode 17 with the source electrode 16 as the reference potential. This electric field does not concentrate in the area where the SJ structure is located, but concentrates at the end of the control electrode 15, which is prone to dielectric breakdown. To suppress the electric field concentration at the end of the control electrode 15, a P-type electric field relaxation region 12 is disposed near the end of the control electrode 15, and the potential of the electric field relaxation region 12 is set to the same potential as the source region 9. The electric field relaxation region 12 is then extended toward the drift region 7 beyond the side surface 13a of the groove 13 in which the control electrode 15 is embedded. As a result, an electric field is formed between the electric field relaxation region 12 extended toward the drift region 7 and the drain electrode 17, and the electric field concentration at the end of the control electrode 15 is alleviated.

[0036] [Method of Manufacturing Semiconductor Device] Next, an example of a method of manufacturing the semiconductor device 100 according to this embodiment will be described with reference to FIGS. 4A to 4G.

[0037] First, a substrate 1 without any impurities added is prepared. Next, as shown in FIG. 4A , a mask material 2 formed on the main surface 1 a of the substrate 1 is patterned to expose a region where the well region 3 will be formed. Then, using the mask material 2 as a mask, ion implantation is performed to selectively add P-type impurities to the substrate 1, thereby forming the well region 3. Subsequently, ion implantation is performed to selectively add N-type impurities to the substrate 1, using the mask material 2 as is, thereby forming a portion 7 a of the drift region that is in contact with the underside of the well region 3. The depth direction position of the impurities added into the substrate 1 can be controlled by adjusting the acceleration energy of the impurity ions during ion implantation. The acceleration energy of the N-type impurity ions used to form the portion 7 a of the drift region is set higher than the acceleration energy of the P-type impurity ions used to form the well region 3.

[0038] A typical mask material 2 can be a silicon oxide film, and a thermal CVD method or a plasma CVD method can be used as a deposition method. A photolithography method can be used as a patterning method. That is, the mask material 2 is etched using a patterned photoresist film as a mask. Etching methods that can be used include wet etching using hydrofluoric acid and dry etching such as reactive ion etching. After etching the mask material 2, the photoresist film is removed using oxygen plasma, sulfuric acid, or the like. In this way, the mask material 2 is patterned. Note that, to make the structure easier to understand, only the outer edge of the mask material 2 is shown in the figure. The same applies to not only the mask material 2 but also other mask materials.

[0039] After forming the drift region 7 and a portion 7a of the drift region, a P-type impurity is selectively added from the main surface 1a of the substrate 1 by ion implantation using the patterned new mask material 4 as a mask, as shown in FIG. 4B, to form a P-type column region 5 in contact with the well region 3.

[0040] 4C , the remaining portion 7b of the drift region is formed by selectively adding P-type impurities to the main surface 1a of the substrate 1 by ion implantation using the patterned new mask material 6 as a mask. The N-type impurity concentration of the drift regions 7a and 7b may be the same as the P-type impurity concentration of the P-type column region 5. Alternatively, the P-type impurity concentration of the P-type column region 5 may be lower than the P-type impurity concentration of the well region 3.

[0041] 4D , using the patterned new mask material 8 as a mask, N-type impurity ions are selectively implanted from the main surface 1 a of the substrate 1 to simultaneously form a source region 9 and a drain region 10 doped with a high concentration of N-type impurity. By implanting N-type impurity ions into a part of the well region 3, a source region 9 in contact with the main surface 1 a of the substrate 1 is formed in the well region 3. By implanting N-type impurity ions into a part of the drift region 7, a drain region 10 in contact with the main surface 1 a of the substrate 1 is formed in the drift region 7.

[0042] 4E, using the patterned new mask material 11 as a mask, P-type impurities are selectively added from the main surface 1a of the substrate 1 by ion implantation to form an electric field relaxation region 12. By sufficiently increasing the acceleration energy of the P-type impurity ions, the P-type impurity ions can be implanted into the bottom of a trench to be formed later and below the drift region 7. In the example shown in FIG. 4E, the electric field relaxation region 12 is formed using the mask material 11 in which the region where the trench 13 (control electrode 15 and insulating film 14) will be formed and part of the source region 9 are exposed.

[0043] In the ion implantation steps up to this point, for example, group V elements such as nitrogen (N) and phosphorus (P) can be used as N-type impurities, and group III elements such as boron (B), gallium (Ga), and aluminum (Al) can be used as P-type impurities. By implanting ions while the substrate 1 is heated to a temperature of about 600°C, it is possible to prevent crystal defects from occurring in the ion-implanted region. The implanted impurities are then activated by heat treatment (annealing). For example, heat treatment is performed at about 1700°C in an argon or nitrogen atmosphere.

[0044] 4F , using the patterned new mask material 18 as a mask, a portion of the substrate 1 is selectively etched from the main surface 1 a of the substrate 1 by anisotropic dry etching or wet etching to form a trench 13. The source region 9, well region 3, and drift region 7 are exposed on the side surface 13 a of the trench 13. The electric field relaxation region 12 is exposed on the bottom 13 b of the trench 13.

[0045] 4G, an insulating film 14 and a control electrode 15 are formed inside the trench 13. The control electrode 15 is formed so as to be in contact with each of the source region 9, the well region 3, the drift region 7, and the electric field relaxation region 12 via the insulating film 14.

[0046] The insulating film 14 is formed on the inner wall surfaces of the trench 13, including the side surfaces 13a and bottom 13b of the trench 13. The insulating film 14 can be formed using, for example, a thermal oxidation method or a deposition method. As an example, in the case of the thermal oxidation method, the substrate 1 is heated to about 1100°C in an oxygen atmosphere, and a silicon oxide film is formed as the insulating film 14 in all parts of the substrate 1 that come into contact with oxygen. However, instead of a silicon oxide film, the insulating film 14 may be a silicon nitride film or a stacked film of a silicon oxide film and a silicon nitride film. In the case of a silicon nitride film, isotropic etching can be performed by cleaning with hot phosphoric acid at 160°C.

[0047] After forming the insulating film 14, in order to reduce the interface state at the interface between the well region 3 and the insulating film 14, nitrogen, argon, zinc nitride (N ２ Alternatively, the film may be subjected to a heat treatment (annealing) at about 1000° C. in an atmosphere of nitrogen monoxide (NO) or nitrogen oxide (N). ２ Thermal oxidation may be performed in an O atmosphere. In this case, the temperature is preferably 1100° C. to 1400° C. The thickness of the insulating film 14 is about several tens of nanometers.

[0048] The control electrode 15 is formed so as to be deposited inside the groove 13 with the insulating film 14 formed therein. The material of the control electrode 15 may be, for example, a polysilicon film.

[0049] The polysilicon film can be deposited by a low-pressure CVD method or the like. For example, the thickness of the polysilicon film to be deposited is set to a value greater than half the width of the trench 13, and the trench 13 is filled with the polysilicon film. Since the polysilicon film is formed from the inner wall surface of the trench 13, the trench 13 can be filled with the polysilicon film by setting the thickness of the polysilicon film as described above. For example, if the width of the trench 13 is 2 μm, the polysilicon film is formed to a thickness greater than 1 μm. Furthermore, after the polysilicon film is deposited, phosphorus oxychloride (POCl ３ By annealing the control electrode 15 at 950° C. in a nitrogen atmosphere, an N-type polysilicon film is formed, and the control electrode 15 is made conductive.

[0050] The polysilicon film is planarized by etching or the like. The etching method may be isotropic etching or anisotropic selective etching. The etching amount is set so that the polysilicon film remains inside the trench 13. For example, if a polysilicon film is deposited to a thickness of 1.5 μm for a trench 13 with a width of 2 μm, the etching amount of the polysilicon film is set to 1.5 μm. However, in etching control, over-etching by a few percent for the etching amount of 1.5 μm does not cause any problems. Note that although N-type polysilicon is used in the description here, P-type polysilicon may also be used. Furthermore, other semiconductor materials or conductive materials such as metal materials may also be used. For example, P-type polysilicon carbide, SiGe, Al, etc. may be used.

[0051] Thereafter, although not shown, an interlayer insulating film made of a silicon oxide film is formed on the main surface 1a of the substrate 1 using, for example, thermal CVD or plasma CVD. A silicon nitride film may also be used for the interlayer insulating film. Then, photolithography is used to form contact holes in the interlayer insulating film, exposing the source region 9 and the drain region 10. The electrode film formed so as to fill the contact holes is patterned to form the source electrode 16 and the drain electrode 17. This completes the semiconductor device 100 shown in FIGS. 1 and 2. When forming the semiconductor device 100 shown in FIG. 3, the shape of the mask material 11 shown in FIG. 4E may be changed to match the electric field relaxation region 12. The interlayer insulating film is not shown.

[0052] The source electrode 16 and the drain electrode 17 can be preferably made of a metal material used for metal wiring, such as titanium (Ti), nickel (Ni), or molybdenum (Mo). Alternatively, the source electrode 16 and the drain electrode 17 may be made of a laminated film in which titanium (Ti), nickel (Ni), and silver (Ag) are laminated in this order from the main surface 1a of the substrate 1. The source electrode 16 and the drain electrode 17 are formed by depositing a metal material over the entire surface by sputtering or electron beam (EB) evaporation, and then etching the metal material. Alternatively, the source electrode 16 and the drain electrode 17 may be formed by filling contact holes with a metal material by a plating process.

[0053] Next, the effects of the semiconductor device 100 according to this embodiment and the manufacturing method thereof will be described. A portion of the electric field relaxation region 12 extends from the side surface 13a of the trench 13 toward the drift region 7. This allows the electric field relaxation region 12 to mitigate the concentration of the electric field formed in the substrate 1 at the end EF of the trench 13 when a voltage is applied between the source region 9 and the drain region 10. In other words, it is possible to mitigate the electric field concentration at the end of the control electrode 15 disposed inside the trench 13. Furthermore, in a lateral structure transistor, an inversion layer is formed along the side surface 13a of the trench 13 perpendicular to the main surface 1a of the substrate 1, thereby improving the channel density.

[0054] When a voltage is applied between the source region 9 and the drain region 10, the electric field relaxation region 12 blocks the electric field applied from the drain region 10 to the end EF of the trench 13, thereby mitigating the electric field concentration at the end of the control electrode 15 arranged inside the trench 13.

[0055] Electric field relaxation region 12 is in contact with bottom 13b of groove 13. This brings electric field relaxation region 12 closer to drift region 7 compared to when electric field relaxation region 12 is disposed away from bottom 13b of groove 13, thereby mitigating electric field concentration on side surface 13a of groove 13 that contacts drift region 7.

[0056] The electric field relaxation region 12 has the same potential as the source region 9. As a result, when a voltage is applied between the source region 9 and the drain region 10, the electric field relaxation region 12, which has the same potential as the source region 9, extends from the side surface 13a of the groove 13 toward the drift region 7, and an electric field is formed between the electric field relaxation region 12 and the drift region 7, thereby mitigating the electric field concentration at the end of the control electrode 15.

[0057] The end 12a of the electric field relaxation region 12, which extends toward the drift region 7, is located in a range from the side surface 13a of the trench 13 to the center of the P-type column region 51 in the direction MC of the main current of the semiconductor device flowing through the drift region 7 (see FIG. 3 ). This makes it possible to alleviate the electric field concentration at the end of the control electrode 15 disposed inside the trench 13. If the end 12a of the electric field relaxation region 12 were located closer to the drain region 10 than the center of the P-type column region 51, punch-through might occur between the electric field relaxation region 12 and the drain region 10. If the end 12a of the electric field relaxation region 12 does not extend beyond the side surface 13a of the trench 13, no electric field would be formed between the electric field relaxation region 12 and the drift region 7, and therefore the electric field concentration at the end of the control electrode 15 could not be alleviated.

[0058] The well region 3 and the drift region 7 are made of a wide bandgap semiconductor, which allows both a low on-resistance and a high breakdown field to be achieved.

[0059] The semiconductor device 100 further includes a source electrode 16 formed on the main surface 1a of the substrate 1 and electrically connected to the source region 9, and a drain electrode 17 formed on the main surface 1a of the substrate 1 and electrically connected to the drain region 10. This allows the semiconductor device 100 to be formed as a device with a lateral structure on the substrate 1. By forming a channel on the side surface 13a of the trench 13, it is possible to improve the degree of element integration.

[0060] The substrate 1 is a semi-insulating substrate or an insulating substrate. This can simplify the element isolation process when integrating multiple semiconductor devices on the same substrate 1. Furthermore, when mounting the semiconductor device 100 on a cooler, it is possible to omit the insulating substrate that is placed between the substrate 1 and the cooler.

[0061] The substrate 1, well region 3, and drift region 7 are made of the same material, which prevents performance degradation due to lattice mismatch or the like that occurs when different materials are used.

[0062] The substrate 1 is made of silicon carbide. This allows for the attainment of characteristics such as high heat dissipation, low on-resistance, and high breakdown field. SiC is a wide bandgap semiconductor with a small number of intrinsic carriers, making it easy to obtain high insulation properties and realize a semiconductor device with high withstand voltage. By using a SiC substrate for the substrate 1, the insulation properties and thermal conductivity of the substrate 1 can be increased. Therefore, the back surface of the substrate 1 can be directly attached to a cooling mechanism, allowing the semiconductor device 100 to be efficiently cooled. With this structure, the high thermal conductivity of the SiC substrate allows for efficient dissipation of heat generated by the main current when the semiconductor device 100 is in the on state.

[0063] The main current of the semiconductor device 100 flows through the drift region 7 in a direction MC parallel to the main surface 1a of the substrate 1. The source region 9, the well region 3, and the drift region 7 contact the side surface 13a of the trench 13. In the semiconductor device 100 having a lateral structure, the density of the channels formed along the side surface 13a of the trench 13 can be increased.

[0064] The drift region 7, the drain region 10, the well region 3, the source region 9, and the electric field relaxation region 12 are formed by ion implantation. By using ion implantation, the degree of freedom in designing each of the semiconductor regions 7, 10, 3, 9, and 12 can be improved.

[0065] (First Modification) A semiconductor device 100A according to a first modification of the first embodiment will be described with reference to FIG. 5. In the first modification, multiple P-type column regions 511-514 are arranged at intervals in a direction perpendicular to the main surface 1a of the substrate 1. The P-type column region 51 in FIGS. 1 to 3 has the P-type column regions 511-514 shown in FIG. 5. The number of P-type column regions 511-514 included in the P-type column region 51 is not limited to four, and may be two, three, five, or more. The P-type column regions 511-514 and the N-type drift regions 7 between the P-type column regions 511-514 form a superjunction (SJ) structure in which they are alternately arranged in a direction perpendicular to the direction MC in which the main current of the semiconductor device 100 flows.

[0066] Note that an N-type column region may be formed between the P-type column regions 511 to 514 instead of the N-type drift region 7. The conditions for the shape and impurity concentration of each region to form a super junction (SJ) structure between the P-type column regions 511 to 514 and the N-type drift region 7, or between the P-type column regions 511 to 514 and the N-type column regions, satisfy formula (1).

[0067] 1 to 3 also includes a plurality of P-type column regions arranged at intervals in a direction perpendicular to the main surface 1a of the substrate 1, similar to the P-type column region 51. The N-type impurity concentration of the N-type column region may be the same as or different from the N-type impurity concentration of the drift region 7.

[0068] The P-type column regions 511 to 514 can be manufactured by controlling the implantation depth by adjusting the acceleration energy during ion implantation. The P-type column regions 511 to 514 can be manufactured by implanting impurity ions with uniform acceleration energy in multiple stages. The same applies to forming N-type column regions between the P-type column regions 511 to 514. The other configurations and manufacturing methods of the semiconductor device 100A are the same as those of the semiconductor device 100, so a description thereof will be omitted.

[0069] The N-type column regions and P-type column regions 511 to 514 are alternately arranged in a direction perpendicular to the main surface 1a of the substrate 1. Alternatively, the P-type column regions 511 to 514 are arranged at predetermined intervals in a direction perpendicular to the main surface 1a of the substrate 1. This makes it possible to form an SJ structure in each of the two directions (X direction and Z direction) perpendicular to the direction MC in which the main current flows, thereby forming a more uniform electric field and reducing the on-resistance.

[0070] (Second Modification) Figure 6 is a plan view of a semiconductor device 100B according to a second modification of the first embodiment, as viewed from the X direction. As shown in Figure 6, N-type column regions 181, 182, and 183 may be formed between and on both sides of the P-type column regions 51 and 52, instead of the N-type drift region 7. The P-type column regions 51 to 54 and the N-type column regions 181 to 183 are alternately arranged in a direction perpendicular to the direction MC in which the main current flows in the semiconductor device 100B. The P-type column regions 51 to 54 and the N-type column regions 181 to 183 are alternately arranged in a direction parallel to the main surface 1a of the substrate 1. The other configurations and manufacturing methods of the semiconductor device 100B are the same as those of the semiconductor device 100, and therefore will not be described again.

[0071] The N-type impurity concentrations of the N-type column regions 181, 182, and 183 may be the same as or different from the N-type impurity concentration of the drift region 7. The conditions for the shape and impurity concentration of each region, which allow the P-type column regions 51 to 54 and the N-type column regions 181 to 183 to form a super junction (SJ) structure, are the same as those in formula (1). Furthermore, the second modification can be implemented in combination with the first modification. That is, each of the P-type column regions 51 to 54 may be divided into a plurality of P-type column regions arranged in a direction perpendicular to the main surface 1a of the substrate 1, similar to the P-type column region 51 in FIG. 5.

[0072] The semiconductor device 100B further includes N-type column regions 181-183 and P-type column regions 51-54 formed in the drift region 7. The N-type column regions 181-183 and P-type column regions 51-54 are designed to be in a pinch-off state when a voltage is applied between the source region 9 and the drain region 10. This makes the electric field distribution in the drift region 7 uniform. This significantly reduces the maximum electric field and improves the breakdown voltage.

[0073] The N-type column regions 181-183 and the P-type column regions 51-54 are alternately arranged in a direction perpendicular to the direction of the main current of the semiconductor device 100B flowing through the drift region 7. Furthermore, the N-type column regions 181-183 and the P-type column regions 51-54 are alternately arranged in a direction perpendicular to the main surface 1a of the substrate 1. Since the impurity concentrations of the drift region 7 and the N-type column regions 181-183 can be increased while maintaining the breakdown voltage, the on-resistance of the semiconductor device 100B can be reduced.

[0074] Second Embodiment As shown in FIG. 7 , a semiconductor device 102 according to the second embodiment differs from the semiconductor device 100 shown in FIGS. 1 and 2 in that the electric field relaxation region 12 extends to the end 3 a of the well region 3 on the drift region 7 side. As shown in FIGS. 2 and 3 , the effect of relaxing the electric field concentration at the end of the control electrode 15 can be obtained as long as the end 12 a of the electric field relaxation region 12 is located in the range from the side surface 13 a of the trench 13 to the center of the P-type column region 51. The condition for achieving the greatest effect of relaxing the electric field concentration at the end of the control electrode 15 is that the electric field relaxation region 12 extends to the end 3 a of the well region 3 on the drift region 7 side. In other words, when the position of the end 12 a of the electric field relaxation region 12 coincides with the position of the end 3 a of the well region 3 on the drift region 7 side as viewed from the X direction, the effect of relaxing the electric field concentration at the end of the control electrode 15 is maximized.

[0075] The method for manufacturing the semiconductor device 102 also has the advantage of being able to manufacture the electric field buffer region 12 and the well region 3 in a self-aligned manner using the same mask material 2. As shown in FIG. 8A , the mask material 2 formed on the main surface 1 a of the substrate 1 is patterned to expose the region where the well region 3 will be formed. Then, using the mask material 2 as a mask, the well region 3 is formed by ion implantation, selectively adding P-type impurities to the substrate 1. Thereafter, as shown in FIG. 8B , the same mask material 2 is used to implant P-type impurity ions at a high concentration with a higher acceleration energy than the well region 3. The electric field buffer region 12 can be formed below and separated from the well region 3 by self-alignment. When viewed from the X direction, the position of the end 12 a of the electric field buffer region 12 can be accurately aligned with the position of the end 3 a of the well region 3 on the drift region 7 side. Using the same mask material 2 can reduce the number of processes. Except for the above points, the method for manufacturing the semiconductor device 102 is the same as the manufacturing method described in the first embodiment, and therefore a description thereof will be omitted. It goes without saying that the first and second modifications can also be applied to the semiconductor device 102 according to the second embodiment. Note that, except for the steps shown in Figures 8A and 8B, the method for manufacturing the semiconductor device 102 is the same as the method for manufacturing the semiconductor device 100, and therefore a description thereof will be omitted.

[0076] The manufacturing method of the semiconductor device 102 uses the same mask pattern (mask material 2) to form the electric field relaxation region 12 and the well region 3 so that, when viewed from a direction perpendicular to the main surface 1a of the substrate 1 (X direction), the end 12a of the electric field relaxation region 12 on the drift region 7 side coincides with the end 3a of the well region 3 on the drift region 7 side. Forming the electric field relaxation region 12 and the well region 3 using the same mask pattern, so-called self-alignment, can reduce the number of processes. Furthermore, the end 12a of the electric field relaxation region 12 on the drift region 7 side can be accurately aligned with the end 3a of the well region 3 on the drift region 7 side.

[0077] Third Embodiment The structure of a semiconductor device 103 according to a third embodiment will be described with reference to Fig. 9. In the semiconductor device 100 of Fig. 1, the electric field relaxation region 12 is disposed below and in contact with the bottom 13b of the groove 13. In contrast, the semiconductor device 103 according to the third embodiment differs from the semiconductor device 100 of Fig. 1 in that the electric field relaxation region 12 is disposed below and spaced apart from the bottom 13b of the groove 13. Apart from this difference, the semiconductor device 103 has the same configuration as the semiconductor device 100 of Fig. 1, and therefore will not be described again.

[0078] The electric field relaxation region 12 is spaced apart from the bottom 13b of the groove 13 and the bottom of the drift region 7. The substrate 1 is disposed between the bottom 13b of the groove 13 and the bottom of the drift region 7 and the electric field relaxation region 12, respectively.

[0079] The position of the electric field relaxation region 12 in the depth direction (X direction) can be controlled by adjusting the acceleration energy of the P-type impurity ions in the manufacturing process shown in FIG. 4E.

[0080] When electric field relaxation region 12, which is doped with a high concentration of P-type impurities, comes into contact with drift region 7, a depletion layer spreads in drift region 7, which may narrow the path through which the main current of the semiconductor device flows. By arranging electric field relaxation region 12 below and spaced apart from bottom 13b of groove 13, it is possible to prevent the path of the main current flowing through drift region 7 from being narrowed. In other words, according to the third embodiment, it is possible to alleviate the electric field concentration on control electrode 15 and simultaneously prevent the drift region 7 from being narrowed by the depletion layer in electric field relaxation region 12.

[0081] REFERENCE SIGNS LIST 1 substrate 1a main surface 3 well region 3a end portion 5 P-type column region (second conductivity type column region) 7 drift region 9 source region 10 drain region 12 electric field relaxation region 12a end portion 12L extension portion 13 groove 13a side surface 13b bottom portion 14 insulating film 15 control electrode 16 source electrode 17 drain electrode 51 to 54 P-type column region 100, 100A, 100B, 102, 103 semiconductor device 181 to 183 N-type column region 511 to 514 P-type column region

Claims

1. circuit board and A first conductivity type drift region formed within the substrate in contact with the main surface of the substrate, A drain region of a first conductivity type formed in the substrate adjacent to the drift region, A second conductivity type well region formed in the substrate adjacent to the drift region, A first conductivity type source region formed in the substrate adjacent to the well region, A control electrode is disposed within a groove formed in the substrate from the main surface, with an insulating film in between. A second conductivity type field relaxation region is located below the bottom of the groove, A semiconductor device equipped with, The source region, the well region, and the drift region are in contact with the side surface of the groove. A portion of the electric field relaxation region extends from the side of the groove toward the drift region, The concentration of the second conductivity type impurity in the field relaxation region is higher than the concentration of the second conductivity type impurity in the well region. Semiconductor equipment.

2. The length of the electric field relaxation region, which extends from the side surface of the groove toward the drift region, is such that it can block the electric field from the drain region to the end of the groove when a voltage is applied between the source region and the drain region. The semiconductor device according to claim 1.

3. The field relaxation region extends to the drift region side end of the well region. The semiconductor device according to claim 1.

4. The electric field relaxation region is in contact with the bottom of the groove. The semiconductor device according to claim 1.

5. The electric field relaxation region is positioned at a distance below the bottom of the groove. The semiconductor device according to claim 1.

6. The electric field relaxation region is at the same potential as the source region. The semiconductor device according to claim 1.

7. The drift region further comprises a first conductivity type column region and a second conductivity type column region formed within the drift region. The semiconductor device according to claim 1.

8. The end of the electric field relaxation region, which extends toward the drift region, is located in the range from the side surface of the groove to the center of the second conductivity type column region in the direction of the main current of the semiconductor device flowing through the drift region. The semiconductor device according to claim 7.

9. The first conductivity type column region and the second conductivity type column region are alternately arranged in a direction perpendicular to the direction of the main current of the semiconductor device flowing through the drift region. The semiconductor device according to claim 7.

10. The first conductive column region and the second conductive column region are arranged alternately in a direction perpendicular to the main surface of the substrate. The semiconductor device according to claim 9.

11. The well region and the drift region are formed from a wide-bandgap semiconductor. A semiconductor device according to any one of claims 1 to 10.

12. A source electrode formed on the main surface of the substrate and electrically connected to the source region, A drain electrode formed on the main surface of the substrate and electrically connected to the drain region, A semiconductor device according to any one of claims 1 to 10, further comprising the above.

13. The substrate is a semi-insulating substrate or an insulating substrate. A semiconductor device according to any one of claims 1 to 10.

14. The substrate, the well region, and the drift region are formed from the same material. A semiconductor device according to any one of claims 1 to 10.

15. The substrate is formed from silicon carbide. A semiconductor device according to any one of claims 1 to 10.

16. The main current of the semiconductor device flows through the drift region in a direction parallel to the main surface of the substrate. A semiconductor device according to any one of claims 1 to 10.

17. A method for manufacturing a semiconductor device according to any one of claims 1 to 10, The drift region, the drain region, the well region, the source region, and the electric field relaxation region are formed by ion implantation. A method for manufacturing a semiconductor device.

18. A method for manufacturing a semiconductor device according to any one of claims 1 to 10, When viewed from a direction perpendicular to the main surface of the substrate, the electric field relaxation region and the well region are formed using the same mask pattern such that the end of the electric field relaxation region on the drift region side coincides with the end of the well region on the drift region side. A method for manufacturing a semiconductor device.