Oxide semiconductor layer, method for manufacturing oxide semiconductor layer, semiconductor device, and method for manufacturing semiconductor device

Abstract

In the present invention, provided is a transistor that has favorable electrical characteristics. Provided is a transistor that has high on-current. Provided is a transistor that has low parasitic capacitance. Provided is a transistor, a semiconductor device, or a storage device that allows for extremely small size or high integration. This oxide semiconductor layer comprises indium, zinc, and an element M. The element M is at least one of gallium, tin, and yttrium. The oxide semiconductor layer comprises a first region, a second region over the first region, and a third region over the second region. The first region is located at 0–3 nm in a direction roughly perpendicular from a shaped surface of the oxide semiconductor layer. In cross-sectional examination of the oxide semiconductor layer using a transmission electron microscope, bright spots lined up in strata in a direction parallel to the shaped surface are confirmed in each of the first region, the second region, and the third region. The concentration of aluminum in the oxide semiconductor layer as determined by STEM-EDX is 3 atomic% or less.

Description

OXIDE SEMICONDUCTOR LAYER, METHOD FOR MANUFACTURING OXIDE SEMICONDUCTOR LAYER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and large scale integration (LSI), central processing units (CPU), memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] Furthermore, Non-Patent Document 2 discloses CAAC-IGZO as a crystalline oxide semiconductor, and also discloses the growth mechanism of CAAC-IGZO.

[0010] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0011] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53 Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO: FUNDAMENTALS”, (USA), Wiley-SID Series in Display Technology, 2017, pp. 50-150

[0012] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a transistor with low parasitic capacitance. Another object of one embodiment of the present invention is to provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio. Another object of one embodiment of the present invention is to provide a highly reliable transistor, a semiconductor device, a display device, or a memory device. Another object of one embodiment of the present invention is to provide a semiconductor device, a display device, or a memory device with low power consumption. Another object of one embodiment of the present invention is to provide a memory device with high operating speed. Another object of one embodiment of the present invention is to provide a manufacturing method of the transistor, the semiconductor device, the display device, or the memory device.

[0013] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0014] One embodiment of the present invention is an oxide semiconductor layer containing indium, zinc, and an element M, where the element M is one or more of gallium, tin, and yttrium. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located at a distance of 0 nm to 3 nm from a surface where the oxide semiconductor layer is to be formed, in a direction substantially perpendicular to the surface where the oxide semiconductor layer is to be formed. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the surface where the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region. The aluminum concentration of the oxide semiconductor layer measured by STEM-EDX is 3 atomic % or less.

[0015] Another embodiment of the present invention is an oxide semiconductor layer containing indium, zinc, and an element M, where the element M is one or more of gallium, tin, and yttrium. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located at a distance of 0 nm to 3 nm from a surface where the oxide semiconductor layer is to be formed, in a direction substantially perpendicular to the surface where the oxide semiconductor layer is to be formed. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the surface where the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region. The aluminum concentration of the oxide semiconductor layer measured by SIMS is 1×10 ２０ atoms / cm ３ The following is an oxide semiconductor layer.

[0016] In the above embodiment, it is preferable that the second region contains zinc, the second region contains crystals, and the c-axes of the crystals are approximately parallel to a normal to a surface on which the oxide semiconductor layer is formed.

[0017] In the above aspect, the c-axis orientation rate in the second region is preferably higher than the c-axis orientation rate in the first region.

[0018] In the above aspect, the c-axis orientation rate in the third region is preferably higher than the c-axis orientation rate in the first region.

[0019] In the above aspect, it is preferable that the indium content in the first region is higher than the indium content in the second region, and that the indium content in the third region is higher than the indium content in the second region.

[0020] Another embodiment of the present invention is a method for forming an oxide semiconductor layer by forming a first metal oxide, forming a second metal oxide over the first metal oxide, and forming a third metal oxide over the second metal oxide, in which each of the first metal oxide and the third metal oxide is formed by an ALD method using a precursor containing indium and an oxidizing agent, and the aluminum content of the precursor containing indium is 100 ppm or less. The second metal oxide is formed by a sputtering method using a sputtering target containing indium.

[0021] In the above embodiment, it is preferable that the sputtering target contains zinc and the sputtering method is carried out in an atmosphere containing oxygen.

[0022] In the above embodiment, the substrate heating temperature in the ALD method is preferably 100° C. or higher and 350° C. or lower.

[0023] In the above-described embodiment, it is preferable that, in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in each of the first metal oxide, the second metal oxide, and the third metal oxide.

[0024] In the above aspect, it is preferable that no clear boundary is observed between the first metal oxide and the second metal oxide, and no clear boundary is observed between the second metal oxide and the third metal oxide.

[0025] In the above embodiment, it is preferable to perform a heat treatment at 350° C. or higher and 550° C. or lower after forming the third metal oxide on the second metal oxide.

[0026] Alternatively, one embodiment of the present invention includes a transistor over a first insulating layer and a second insulating layer. The transistor includes a first conductive layer over the first insulating layer, a second conductive layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode. The oxide semiconductor layer contains indium, zinc, and an element M, where the element M is one or more of gallium, tin, and yttrium. The aluminum concentration in the oxide semiconductor layer measured by STEM-EDX is 3 atomic % or less. The second insulating layer is located between the first conductive layer and the second conductive layer, and the second conductive layer is located over the second insulating layer. The second insulating layer and the second conductive layer have first openings reaching the first conductive layer. is in contact with a side surface of the second insulating layer in the first opening and a side surface of the second conductive layer in the first opening, the gate insulating layer is located on the oxide semiconductor layer, the gate electrode has a region in the first opening that overlaps with the oxide semiconductor layer with the gate insulating layer sandwiched therebetween, the oxide semiconductor layer has a first region, a second region on the first region, and a third region on the second region, the first region is located at a distance of 0 nm to 3 nm substantially perpendicularly from a surface on which the oxide semiconductor layer is to be formed, and in cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in layers in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are confirmed in each of the first region, the second region, and the third region.

[0027] In the above aspect, it is preferable that the side surface of the second insulating layer within the first opening has a fourth region that forms an angle of 75 degrees or more and 90 degrees or less with the top surface of the first conductive layer, and that the first region is in contact with the fourth region.

[0028] In the above aspect, the thickness of the second insulating layer in a region sandwiched between the first conductive layer and the second conductive layer is preferably greater than the width of the first opening.

[0029] In the above embodiment, it is preferable that the second conductive layer has a two-layer stacked structure, with ruthenium, tungsten, titanium nitride, or tantalum nitride being used for the lower layer, and indium tin oxide or indium tin oxide with silicon added being used for the upper layer.

[0030] Alternatively, one embodiment of the present invention includes forming a first insulating layer over a first conductive layer, forming a second conductive layer over the first insulating layer, removing part of the second conductive layer and part of the first insulating layer to form a first opening reaching the first conductive layer and exposing a top surface of the first conductive layer, forming a first metal oxide so as to be in contact with the top surface of the first conductive layer, a side surface of the first insulating layer in the first opening, a side surface of the second conductive layer in the first opening, and a top surface of the second conductive layer, respectively, forming a second metal oxide over the first metal oxide, and forming a second metal oxide over the second metal oxide. a third metal oxide is formed on a substrate; a second insulating layer is formed so as to be in contact with an upper surface of the third metal oxide; a third conductive layer is formed on the second insulating layer; each of the first metal oxide and the third metal oxide is formed by an ALD method using a precursor containing indium and an oxidizer, the aluminum content of the indium-containing precursor being 100 ppm or less; and the second metal oxide is formed by a sputtering method using a sputtering target containing indium.

[0031] In the above embodiment, the third conductive layer is preferably formed by a metal CVD method at a temperature of 250° C. or higher.

[0032] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to another embodiment of the present invention, a transistor with high on-state current can be provided. According to another embodiment of the present invention, a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a display device with high definition or a high aperture ratio can be provided. According to another embodiment of the present invention, a highly reliable transistor, a semiconductor device, a display device, or a memory device can be provided. According to another embodiment of the present invention, a semiconductor device, a display device, or a memory device with low power consumption can be provided. According to another embodiment of the present invention, a memory device with high operating speed can be provided. According to another embodiment of the present invention, a manufacturing method of the above-described transistor, semiconductor device, display device, or memory device can be provided.

[0033] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0034] FIGS. 1A to 1D are cross-sectional views illustrating an example of a method for forming an oxide semiconductor. FIGS. 2A to 2D are cross-sectional views illustrating an example of an oxide semiconductor. FIGS. 3A to 3E are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 4A to 4D are views illustrating the atomic arrangement of a metal oxide film according to one embodiment of the present invention. FIGS. 5A to 5D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 6A to 6C are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIG. 7A is a plan view illustrating an example of a semiconductor device. FIGS. 7B and 7C are cross-sectional views illustrating an example of a semiconductor device. FIG. 8 is a cross-sectional view illustrating an example of a semiconductor device. FIGS. 9A and 9B are cross-sectional views illustrating an example of a semiconductor device. FIG. 10A is a plan view illustrating an example of a semiconductor device. FIGS. 10B and 10C are cross-sectional views illustrating an example of a semiconductor device. FIG. 11A is a plan view illustrating an example of a semiconductor device. FIG. 11B is a cross-sectional view illustrating an example of a semiconductor device. FIG. 12A is a plan view illustrating an example of a semiconductor device. FIG. 12B is a cross-sectional view illustrating an example of a semiconductor device. 13A to 13C are cross-sectional views showing an example of a semiconductor device. FIG. 14A is a plan view showing an example of a semiconductor device. FIGS. 14B and 14C are cross-sectional views showing an example of a semiconductor device. FIG. 15A is a plan view showing an example of a semiconductor device. FIGS. 15B and 15C are cross-sectional views showing an example of a semiconductor device. FIGS. 16A to 16C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 17A is a plan view showing an example of a memory device. FIGS. 17B and 17C are cross-sectional views showing an example of a memory device. FIGS. 18A and 18B are cross-sectional views showing an example of a memory device. FIG. 19A is a plan view showing an example of a memory device. FIG. 19B is a cross-sectional view showing an example of a memory device. FIG. 20 is a cross-sectional view showing an example of a memory device. FIG. 21 is a cross-sectional view showing an example of a memory device. FIG. 22 is a block diagram illustrating a structural example of a semiconductor device. FIGS. 23A to 23H are diagrams illustrating a circuit structural example of a memory cell. FIGS. 24A and 24B are perspective views illustrating a structural example of a semiconductor device. FIG. 25A is a block diagram illustrating a CPU. 25B and 25C are circuit diagrams illustrating part of the configuration of the CPU.26A and 26B are perspective views of a semiconductor device. FIGS. 27A and 27B are perspective views of a semiconductor device. FIGS. 28A and 28B are views showing various types of storage devices by layer. FIGS. 29A and 29B are perspective views showing an example of a display device. FIG. 30 is a cross-sectional view showing an example of a display device. FIG. 31 is a cross-sectional view showing an example of a display device. FIGS. 32A to 32C are views showing an example of the configuration of a display device. FIGS. 33A and 33B are views showing an example of an electronic component. FIGS. 34A to 34C are views showing an example of a mainframe computer. FIG. 34D is a view showing an example of space equipment. FIG. 34E is a view showing an example of a storage system applicable to a data center. FIGS. 35A to 35F are views showing an example of electronic equipment. FIGS. 36A to 36G are views showing an example of electronic equipment. FIGS. 37A to 37F are views showing an example of electronic equipment. FIG. 38 is a view showing the transition of on-current of a transistor. FIGS. 39A and 39B are views showing the transition of on-current of a transistor. FIG. 40 is a diagram showing changes in the S value of a transistor. FIG. 41 is a diagram showing changes in the S value of a transistor. FIGS. 42A and 42B are diagrams showing SIMS analysis results. FIGS. 43A and 43B are diagrams showing Id-Vg characteristics of a transistor. FIGS. 44A and 44B are diagrams showing Id-Vg characteristics of a transistor. FIGS. 45A and 45B are diagrams showing Id-Vg characteristics of a transistor. FIGS. 46A and 46B are diagrams showing Id-Vg characteristics of a transistor. FIGS. 47A and 47B are diagrams showing Id-Vg characteristics of a transistor. FIGS. 48A and 48B are diagrams showing Id-Vd characteristics of a transistor. FIGS. 49A and 49B are diagrams showing Id-Vd characteristics of a transistor. FIG. 50 is a diagram showing Id-Vd characteristics of a transistor. FIGS. 51A and 51B are diagrams showing evaluation results of transistor reliability. FIG. 52 is a circuit diagram used in circuit simulation. Fig. 53 is a circuit diagram used in the circuit simulation. Fig. 54A and Fig. 54B are cross-sectional views showing an example of a memory device.

[0035] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0036] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0037] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0038] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0039] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0040] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0041] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0042] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0043] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0044] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0045] To analyze the content of elements such as hydrogen, oxygen, carbon, and nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0046] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0047] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0048] In this specification, "electrically connected" includes connection via "something that has some kind of electrical function." Here, "something that has some kind of electrical function" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical function" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0049] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0050] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0051] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0052] In this specification, "top surface shapes that are approximately the same" means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, the term "top surface shapes that are approximately the same" may also be used. Furthermore, when the top surface shapes are the same or approximately the same, it can also be said that the edges are aligned or approximately aligned, or that the side edges are aligned or approximately aligned.

[0053] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0054] In this specification and the like, when it is stated that A is in contact with B, it means that at least a part of A is in contact with B. Therefore, for example, it can be rephrased as saying that A has a region in contact with B.

[0055] In this specification and the like, when it is stated that A is located on B, it means that at least a part of A is located on B. Therefore, for example, it can be rephrased as, A has a region located on B.

[0056] In this specification and the like, when it is stated that A covers B, it means that at least a part of A covers B. Therefore, for example, it can be rephrased as saying that A has a region that covers B.

[0057] In this specification and the like, when it is stated that A overlaps with B, it means that at least a part of A overlaps with B. Therefore, for example, it can be rephrased as saying that A has an overlapping region with B.

[0058] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0059] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0060] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0061] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, a light-receiving element (also referred to as a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

[0062] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0063] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like EL layer refers to a state in which the EL layer is physically separated from an adjacent EL layer.

[0064] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0065] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0066] Embodiment 1 In this embodiment, an oxide semiconductor layer of one embodiment of the present invention will be described. The oxide semiconductor layer of one embodiment of the present invention is preferably used as a semiconductor layer of a transistor. When the oxide semiconductor layer of one embodiment of the present invention is used as a semiconductor layer of a transistor, the oxide semiconductor layer preferably has a channel formation region. In addition, the oxide semiconductor layer preferably has a source region and a drain region.

[0067] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0068] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. When a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM), it can be seen that metal atoms are arranged in a layered manner in the crystal parts. Thus, the oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as a row of bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. It is preferable that the cross section of the oxide semiconductor layer observed using a TEM image confirm that the metal atoms are arranged in a layered manner in a direction parallel to or approximately parallel to the formation surface. In addition, the c-axis of the CAAC structure of the oxide semiconductor layer is preferably approximately parallel to the normal direction of a surface on which the oxide semiconductor layer is formed.

[0069] A polycrystalline structure has grain boundaries. Furthermore, when a polycrystalline oxide semiconductor layer is formed and then heat treatment is performed, tiny gaps (also referred to as nanocracks or microcracks) or tiny spaces (also referred to as nanospaces or microspaces) can be formed between crystalline portions. When tiny gaps or tiny spaces are formed in the oxide semiconductor layer, the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the tiny gaps or tiny spaces is very high, for example, infinite. When an oxide semiconductor layer having tiny gaps or tiny spaces is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. The CAAC structure can realize a highly reliable semiconductor device because grain boundaries are not clearly observed in the a-b plane. Furthermore, because there are fewer grain boundaries, the energy barrier against carrier conduction in the transistor channel is small, and an improvement in on-current is expected.

[0070] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0071] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0072] Examples of metal oxides contained in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Note that element M is a metal element or a metalloid element having a high bond energy with oxygen, e.g., a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Examples of element M include gallium, tin, and yttrium. Other elements applicable to element M include titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, boron, germanium, strontium, barium, silicon, antimony, and aluminum. The element M contained in the metal oxide is preferably one or more of the above elements. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from the group consisting of indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0073] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0074] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0075] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0076] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0077] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0078] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0079] In the present embodiment, an In—Ga—Zn oxide may be used as an example of the metal oxide.

[0080] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by two different deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by a first deposition method and a second deposition method. Note that an oxide semiconductor layer formed by two different deposition methods may be referred to as a hybrid OS.

[0081] The oxide semiconductor layer of one embodiment of the present invention has crystallinity and preferably has a CAAC structure.

[0082] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a crystalline metal oxide is deposited by the first deposition method. The deposited metal oxide preferably has a CAAC structure. For example, a metal oxide deposited by a sputtering method is likely to have crystallinity.

[0083] When a metal oxide is formed using the first film-forming method, a mixed layer may be formed at the interface between the metal oxide and a layer on which the metal oxide is to be formed. For example, when a sputtering method is used as the first film-forming method, the mixed layer may be formed by particles (also called sputtering particles) emitted from a target or the like, or by energy imparted to the substrate by the sputtering particles. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide.

[0084] For example, when an insulating layer having silicon, such as silicon oxide, is used as a surface to be formed, silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide using the first film formation method, and there is a concern that the mixing of impurities such as silicon into the metal oxide may inhibit the crystallization of the metal oxide.

[0085] Therefore, in one embodiment of the present invention, a metal oxide is formed by a second film formation method before a metal oxide is formed by a first film formation method. That is, a metal oxide is formed as a first layer by a second film formation method, and then a metal oxide is formed as a second layer on the first layer by a first film formation method. In this case, it is preferable to use a film formation method that causes less damage to a surface on which the oxide semiconductor layer is to be formed compared to the first film formation method as the second film formation method. By using a film formation method that causes less damage to a surface on which the oxide semiconductor layer is to be formed as the second film formation method, formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is to be formed can be suppressed. Furthermore, since the incorporation of impurities such as silicon into the second layer can be suppressed, the crystallinity of the second layer can be potentially improved. For example, atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can suppress damage to the surface to be formed compared to sputtering.

[0086] In addition, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure may be formed as the first layer. By forming a second layer with high crystallinity on the first layer with low crystallinity or by performing heat treatment after the formation, the crystallinity of the first layer may be increased using the second layer as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0087] In the oxide semiconductor layer of one embodiment of the present invention, it is preferable that a metal oxide be first formed over a surface to be formed by the second film formation method, and then a metal oxide be formed above the metal oxide by the first film formation method.

[0088] Examples of the first film formation method include a sputtering method and a pulsed laser deposition (PLD) method.

[0089] Examples of the second film formation method include an ALD method, a plasma enhanced CVD (PECVD) method, a thermal CVD method, a photo-assisted CVD method, a metal organic CVD (MOCVD) method, and a molecular beam epitaxy (MBE) method. The MBE method is a film formation method that grows a thin film having a crystalline structure that reflects the crystalline system of the substrate, and can be said to be one of the film formation methods that causes little damage to the surface on which the film is formed. Also, a wet method can be used as the second film formation method. The wet method is one of the film formation methods that causes little damage to the surface on which the film is formed. For example, a spray coating method can be used as the wet method.

[0090] As described above, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by the second deposition method and then forming a metal oxide as a second layer by the first deposition method. Specifically, an ALD method can be used as the second deposition method, and a sputtering method can be used as the first deposition method. The metal oxide formed by the first deposition method preferably has a CAAC structure.

[0091] Furthermore, a third layer can be formed on the second layer. Because the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by using a film formation method that provides higher coverage than the second layer for the third layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the entire layer. Furthermore, for example, by using a film formation method that causes less damage than the second layer for the third layer, damage to the second layer can be reduced, and the oxide semiconductor layer can have high crystallinity throughout the entire layer.

[0092] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0093] The third layer is the uppermost layer of the oxide semiconductor layer, and is in contact with, for example, a gate insulating layer when the oxide semiconductor layer is used as a semiconductor layer of a transistor described later. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on state.

[0094] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide as a first layer by the second deposition method, forming a metal oxide as a second layer by the first deposition method, and forming a metal oxide as a third layer by the second deposition method. Specifically, an ALD method can be used as the second deposition method, and a sputtering method can be used as the first deposition method. That is, a metal oxide can be formed as a first layer by the ALD method, a metal oxide can be formed as a second layer by the sputtering method, and a metal oxide can be formed as a third layer by the ALD method. The metal oxide formed by the first deposition method preferably has a CAAC structure. The ALD method has better coverage than the sputtering method. The use of the ALD method for the first and third layers can improve the coverage of the oxide semiconductor layer. Therefore, the oxide semiconductor layer can be well covered over steps, openings, and the like with a high aspect ratio.

[0095] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0096] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0097] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling ultrathin film formation, film formation on high aspect ratio structures or surfaces with large steps, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. Furthermore, the PEALD method may be preferable in some cases because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain larger amounts of elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. However, since the ALD method employs a high substrate temperature during film formation and / or an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0098] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0099] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. Furthermore, the thermal CVD method produces films with fewer defects because no plasma damage occurs during film formation.

[0100] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0101] [Method for Manufacturing Oxide Semiconductor Layer] The oxide semiconductor layer 230 can be manufactured, for example, by forming an oxide semiconductor layer 230a over a layer 229 that is a surface to be formed by an ALD method, forming an oxide semiconductor layer 230b over the oxide semiconductor layer 230a by a sputtering method, and forming an oxide semiconductor layer 230c over the oxide semiconductor layer 230b by an ALD method. After the oxide semiconductor layer 230 is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer 230. The heat treatment here is not limited to heat treatment. For example, it may be heat applied during the manufacturing process. The layer 229 is an insulating film, and is, for example, an insulating film made of silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like. The layer 229 can be a film described later as an insulator included in a semiconductor device.

[0102] Alternatively, the layer 229 may be a conductive film. For example, the oxide semiconductor layer 230 can be formed over a conductive film that functions as an electrode of a semiconductor device.

[0103] The layer 229 does not need to have crystallinity. In other words, the layer 229 may have an amorphous structure. When the layer 229 has crystallinity, the layer 229 may have a crystal structure with low lattice matching with a metal oxide included in the oxide semiconductor layer 230.

[0104] An example of a method for manufacturing the oxide semiconductor layer 230 will be described with reference to FIGS. 1A to 2D.

[0105] First, an oxide semiconductor layer 230a is formed on the layer 229 (FIG. 1A). Subsequently, an oxide semiconductor layer 230b is formed on the oxide semiconductor layer 230a (FIG. 1B).

[0106] The oxide semiconductor layer 230b is preferably formed by a sputtering method and has a composition suitable for forming a CAAC structure.

[0107] The oxide semiconductor layer 230a is preferably formed by a deposition method that causes less damage to a surface on which the oxide semiconductor layer 230a is formed than the deposition method for the oxide semiconductor layer 230b. Here, the oxide semiconductor layer 230a is formed by an ALD method.

[0108] When a metal oxide film is formed by sputtering, damage to the surface on which the film is to be formed may cause alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed. When alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when heat treatment, which will be described later, is performed. Furthermore, there is a concern that using an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is preferable to suppress alloying between components contained in the metal oxide film and components contained in the layer on which the film is to be formed.

[0109] In a method for forming an oxide semiconductor layer according to one embodiment of the present invention, the oxide semiconductor layer 230a is formed over the layer 229, and then the oxide semiconductor layer 230b is formed by a sputtering method. The oxide semiconductor layer 230a is preferably formed by a deposition method that causes little damage to a surface on which the oxide semiconductor layer 230a is to be formed. By forming the oxide semiconductor layer 230a between the oxide semiconductor layer 230b and the layer 229 by a deposition method that causes little damage to the surface on which the oxide semiconductor layer 230a is to be formed, alloying of components contained in the oxide semiconductor layer 230 and components contained in the layer 229 can be suppressed, and the crystallinity of the oxide semiconductor layer 230 can be further improved.

[0110] By using the above structure, the thickness of the alloyed region can be reduced, or the thickness can be reduced to such an extent that the alloyed region is not observable. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm. Note that FIGS. 1A and 1B show an example in which no alloyed region is formed between the layer 229 and the oxide semiconductor layer 230a.

[0111] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0112] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor layer 230a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor layer 230a contains In) that is the main component of the oxide semiconductor layer 230a but is not the main component of the layer that will become the surface (here, layer 229) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor layer 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor layer 230a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the alloyed region can be calculated.

[0113] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0114] Furthermore, for example, when a silicon oxide layer is used as the layer 229 and SIMS analysis is performed on the oxide semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0115] By setting the thickness t_s2 to a value within the above range, the thickness of the alloyed region can be reduced, thereby setting the thickness t_s2 to a value within the above range.

[0116] Note that by reducing the thickness of the alloyed region, it is possible to form the CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor layer 230 that is approximately perpendicular to the formation surface and is located between more than 0 nm and 3 nm, preferably between more than 0 nm and 2 nm, more preferably between 1 nm and 2 nm.

[0117] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of the oxide semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0118] Alternatively, the CAAC structure near the surface to be formed can sometimes be evaluated from a map showing the crystal orientation. The map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing a fast Fourier transform (FFT) process on each region in the cross-sectional TEM image to create an FFT pattern, and calculating the crystal axis direction of each region. The FFT pattern reflects reciprocal lattice space information similar to an electron diffraction pattern. For example, a region in which the calculated crystal axis direction of each region is 70° or more and 100° or less relative to the surface to be formed can be considered to have a CAAC structure.

[0119] When the oxide semiconductor layer 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 1A , the oxide semiconductor layer 230a may have a region having lower crystallinity than the oxide semiconductor layer 230b.

[0120] Here, a method for forming an In-M-Zn oxide as the oxide semiconductor layer 230a by an ALD method will be described. Details of the formation of a metal oxide by an ALD method will be described later.

[0121] First, a source gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed onto the surface of the layer 229. Here, the substrate heating temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor.

[0122] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacts with the adsorbed precursors to desorb components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer in which indium and oxygen are combined. Ozone, oxygen, water, etc. can be used as the oxidizing agent. Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge excess reactants and reaction products from the chamber.

[0123] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the layer of indium and oxygen. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0124] Next, the introduction of the source gas is stopped, the chamber is purged, and excess precursor, reaction products, etc. are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are bonded. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactant, reaction products, etc. are discharged from the chamber.

[0125] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the layer of the combined element M and oxygen. Here, the substrate is preferably heated to a temperature corresponding to the decomposition temperature of the precursor.

[0126] Here, in the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the substrate heating temperature is, for example, 100°C or higher and 350°C or lower, preferably 150°C or higher and 300°C or lower.

[0127] Next, the introduction of the source gas is stopped, the chamber is purged, and excess precursors and reaction products are discharged from the chamber. Next, an oxidizing agent is introduced into the chamber as a reactant, and reacted with the adsorbed precursor, leaving zinc adsorbed on the substrate while desorbing components other than zinc, thereby forming a layer in which zinc and oxygen are combined. Next, the introduction of the oxidizing agent is stopped, the chamber is purged, and excess reactants and reaction products are discharged from the chamber.

[0128] Next, the first layer is formed again on the layer in which zinc and oxygen are bonded by the above-described method. By repeating the above-described method, an In-M-Zn oxide can be formed as the oxide semiconductor layer 230a on the layer 229 by an ALD method.

[0129] The ALD method can control the composition of the resulting film by adjusting the amount of source gas introduced. For example, the ALD method can form a film of any composition by adjusting the amount of source gas introduced, the number of introductions (also referred to as the number of pulses), the time required for one pulse (also referred to as the pulse time), etc. Furthermore, for example, the ALD method can form a film whose composition changes continuously by changing the source gas while forming the film. When forming a film while changing the source gas, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0130] After the oxide semiconductor layer 230a is formed by an ALD method, an In-M-Zn oxide is formed as the oxide semiconductor layer 230b over the oxide semiconductor layer 230a by a sputtering method.

[0131] The oxide semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure.

[0132] Here, when the oxide semiconductor layer 230b is formed by sputtering, a mixed layer 231 is formed on or near the surface of the oxide semiconductor layer 230a. Furthermore, when the oxide semiconductor layer 230b is formed, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, causing at least a part of the oxide semiconductor layer 230a to crystallize.

[0133] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0134] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0135] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0136] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease by up to about 50% compared to the sputtering target.

[0137] In the formation of the oxide semiconductor layer 230b by a sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, a metal oxide with high crystallinity can be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide. In the formation of the oxide semiconductor layer 230b by a sputtering method, the substrate heating temperature is preferably 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0138] As a result, as shown in FIG. 1B, an oxide semiconductor layer 230a can be formed over the layer 229, and an oxide semiconductor layer 230b can be formed over the oxide semiconductor layer 230a.

[0139] Increasing the zinc content of the oxide semiconductor layer can improve the crystallinity of the oxide semiconductor layer. It is particularly preferable that the oxide semiconductor layer 230a contains zinc. For example, when the oxide semiconductor layer 230a is formed by an ALD method and the oxide semiconductor layer 230b is formed by a sputtering method, zinc contained in the oxide semiconductor layer 230a may diffuse into the oxide semiconductor layer 230b. The diffusion of zinc from the oxide semiconductor layer 230a to the oxide semiconductor layer 230b is expected to improve the crystallinity. Alternatively, the diffusion of zinc from the oxide semiconductor layer 230a to the oxide semiconductor layer 230b is expected to promote the lateral growth of crystal parts having c-axis orientation, thereby facilitating the formation of CAAC.

[0140] The diffusion of zinc from the oxide semiconductor layer 230a to the oxide semiconductor layer 230b may be caused by, for example, heat treatment. The heat treatment may be performed after the formation of the oxide semiconductor layer 230b and before the step of forming the oxide semiconductor layer 230c (described later), or may be performed after the formation of the oxide semiconductor layer 230c.

[0141] After the oxide semiconductor layer 230b is formed, the oxide semiconductor layer 230c is formed on the oxide semiconductor layer 230b ( FIG. 1C ). Here, the oxide semiconductor layer 230c is formed using an ALD method. For the formation of the oxide semiconductor layer 230c using an ALD method, the method for forming the oxide semiconductor layer 230a can be referred to. Note that although it is preferable to form the oxide semiconductor layer 230c, it is not necessary to provide the oxide semiconductor layer 230c. If the oxide semiconductor layer 230c is not provided, it is possible to reduce the number of steps and reduce manufacturing costs.

[0142] When an oxide semiconductor layer 230c having lower crystallinity than the CAAC structure is formed on an oxide semiconductor layer 230b having the CAAC structure by using an ALD method, the oxide semiconductor layer 230c may grow epitaxially using the oxide semiconductor layer 230b as a nucleus. Therefore, when the oxide semiconductor layer 230c is formed, the oxide semiconductor layer 230c may have a region having the CAAC structure. Furthermore, the region having the CAAC structure is preferably formed over the entire oxide semiconductor layer 230c.

[0143] A heat treatment step may be performed after the formation of the oxide semiconductor layer 230c. Note that, in the case where the oxide semiconductor layer 230c is not formed, a heat treatment step can be performed after the formation of the oxide semiconductor layer 230b.

[0144] The heat treatment may be performed at a temperature of, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. Typically, the heat treatment may be performed at 400° C.±25° C. (375° C. to 425° C.). The treatment time may be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time may be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level gaps in the crystal portions of the CAAC structure of the oxide semiconductor layer 230b with the oxide semiconductor layer 230c (in other words, crystal molecules formed by the ALD method).

[0145] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0146] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor layer 230c. Furthermore, if the region having the CAAC structure is formed only below the oxide semiconductor layer 230c after the ALD process, the heat treatment step may cause the region having the CAAC structure to expand upward (FIG. 1D). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire oxide semiconductor layer 230c.

[0147] Furthermore, the heat treatment process may further repair the oxide semiconductor layer 230b by the oxide semiconductor layer 230c (in other words, the crystal molecules formed by the ALD method) that fills gaps in the atomic-level crystal portions of the CAAC structure of the oxide semiconductor layer 230b.

[0148] Furthermore, it is preferable that at least a part of the oxide semiconductor layer 230a is converted into CAAC by the heat treatment ( FIG. 1D ). It is expected that the CAAC is easily generated because the mixed layer 231 formed in the oxide semiconductor layer 230a during the formation of the oxide semiconductor layer 230b acts as a nucleus or seed. It is preferable that the region in the oxide semiconductor layer 230a that is converted into CAAC is wide, and it is preferable that the CAAC is converted into CAAC up to the vicinity of the layer 229.

[0149] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor layer 230a, the CAAC can be formed up to the vicinity of the layer 229 without being limited by the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor layer 230a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0150] Furthermore, the heat treatment can reduce hydrogen in the oxide semiconductor layer 230. Note that when the oxide semiconductor layers 230a and 230c are formed by an ALD method, hydrogen might be contained in the oxide semiconductor layers after film formation due to hydrogen contained in a precursor and an oxidizing agent. In such a case, the heat treatment can reduce hydrogen in the oxide semiconductor layers. Furthermore, the heat treatment can increase the crystallinity of the oxide semiconductor layers 230a and 230c, thereby reducing defects in the oxide semiconductor layers that might cause hydrogen capture and the like, and thus further reducing the hydrogen concentration.

[0151] The heat treatment may be performed, for example, in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. When the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas content is preferably about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen. The heat treatment may also be performed in an atmosphere of ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, and preferably 10 ppb or less).

[0152] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the metal oxide as much as possible.

[0153] By carrying out the heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be converted to CO ２ and CO, and hydrogen in the metal oxide is released as H ２ It can be released as O.

[0154] After the oxide semiconductor layer 230c is formed, microwave treatment may be performed.

[0155] It is preferable to perform microwave treatment in an atmosphere containing oxygen to reduce the impurity concentration in the oxide semiconductor layer 230. Examples of impurities include hydrogen and carbon. Although the above example illustrates a configuration in which microwave treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave treatment may be performed on an insulating film, more specifically, a silicon oxide film, located near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave treatment may increase the crystallinity of the oxide semiconductor layer.

[0156] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 Pa to 1000 Pa, and more preferably from 300 Pa to 700 Pa. The microwave treatment is preferably carried out while the substrate is heated. The substrate temperature can be from room temperature (e.g., 25°C) to 500°C, preferably from 100°C to 500°C, more preferably from 200°C to 500°C, even more preferably from 300°C to 500°C, and even more preferably from 400°C to 500°C. For example, it can be from 400°C to 450°C.

[0157] Alternatively, after the microwave treatment or plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The heat treatment temperature is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0158] The microwave treatment can be performed using, for example, oxygen gas and argon gas. By performing the microwave treatment in an atmosphere containing oxygen, the oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the oxide semiconductor layer. The V in the oxide semiconductor layer can be formed by the action of plasma, microwaves, or the like. Ｏ By splitting H into oxygen vacancies and hydrogen, it is possible to remove hydrogen as an impurity from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave treatment. Furthermore, oxygen radicals generated by the oxygen plasma can be supplied to oxygen vacancies formed in the oxide semiconductor layer, thereby further reducing the oxygen vacancies in the oxide semiconductor layer.

[0159] Oxygen to be implanted into the oxide semiconductor layer can be in various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also referred to as O radicals). Note that the oxygen to be implanted into the oxide semiconductor layer may be in one or more of the above forms, and is particularly preferably an oxygen radical.

[0160] In this manner, impurities in the oxide semiconductor layer can be reduced. Thus, crystal growth can be performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, thereby further improving the crystallinity. Note that one or both of the heat treatment and the microwave treatment may be performed directly on the oxide semiconductor layer, or may be performed after an insulating film or the like is formed after the oxide semiconductor layer is formed.

[0161] 1A to 1D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Also, FIGS. 1A to 1D can be regarded as conceptual diagrams illustrating a film formation model of a metal oxide according to one embodiment of the present invention. As illustrated in FIGS. 1A to 1D , the oxide semiconductor layer 230a and the oxide semiconductor layer 230c each have high crystallinity using the highly crystalline oxide semiconductor layer 230b as a nucleus or seed. Specifically, the crystallinity of the oxide semiconductor layer 230a may be increased by heat treatment during the formation of the oxide semiconductor layer 230b or after the formation of the oxide semiconductor layer 230c. The crystallinity of the oxide semiconductor layer 230c may be increased by heat treatment during the formation of the oxide semiconductor layer 230c or after the formation of the oxide semiconductor layer 230c. Note that the heat treatment has an assisting effect of increasing the crystallinity.

[0162] As described above, in the method for forming a metal oxide film according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the oxide semiconductor layers 230a and 230c here) can be increased by using the oxide semiconductor layer 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown by solid-phase growth using the oxide semiconductor layer 230b as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, i.e., a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC). Note that although FIGS. 1A to 1D illustrate a structure including the oxide semiconductor layers 230a, 230b, and 230c, the present invention is not limited thereto. For example, the structure including the oxide semiconductor layers 230a and 230b can also be an AG CAAC.

[0163] It is preferable that a region having a CAAC structure is widely present throughout the entire oxide semiconductor layer 230, including the oxide semiconductor layer 230a and the oxide semiconductor layer 230c. FIG. 2A shows the crystallized states of the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the oxide semiconductor layer 230c. The region having the CAAC structure in the oxide semiconductor layer 230a is crystalline and connected to the region having the CAAC structure in the oxide semiconductor layer 230b. The region having the CAAC structure in the oxide semiconductor layer 230c is crystalline and connected to the region having the CAAC structure in the oxide semiconductor layer 230b. As a result, the boundary between the oxide semiconductor layer 230a and the oxide semiconductor layer 230b may not be observed. Furthermore, the boundary between the oxide semiconductor layer 230b and the oxide semiconductor layer 230c may not be observed. The oxide semiconductor layer 230 may be expressed as a single layer whose interface is not clearly observable. The oxide semiconductor layer 230 may be expressed as a single layer.

[0164] The regions having the CAAC structure in the oxide semiconductor layers 230 a, 230 b, and 230 c can be observed as bright spots aligned parallel to the surface on which they are formed, for example, in cross-sectional observation using a high-resolution TEM. Furthermore, it is preferable that the c-axes of the CAAC structures in the oxide semiconductor layers 230 a, 230 b, and 230 c are each approximately parallel to the normal direction of the surface on which the oxide semiconductor layers are formed.

[0165] Furthermore, there are cases where a portion of the oxide semiconductor layer 230a or the oxide semiconductor layer 230c is not crystallized. The example shown in Fig. 2B shows a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor layer 230a is not crystallized. Fig. 2C shows a state in which the vicinity of the surface in the oxide semiconductor layer 230c is not crystallized. Fig. 2D shows a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor layer 230a and the vicinity of the surface of the oxide semiconductor layer 230c are not crystallized.

[0166] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0167] According to the method for forming an oxide semiconductor layer of one embodiment of the present invention, the crystallinity of metal oxides located above and below a metal oxide having a CAAC structure can be improved, and the entire oxide semiconductor layer can be made into a layer with high crystallinity.

[0168] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor layer 230, the boundaries between the stacked oxide semiconductor layers 230a, 230b, and 230c may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0169] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c, crystals that reflect the crystal orientation of the oxide semiconductor layer 230b are formed, thereby suppressing polycrystallization.

[0170] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor layer 230b and the crystals of the oxide semiconductor layer 230a or the oxide semiconductor layer 230c is small. This allows the oxide semiconductor layer 230a or the oxide semiconductor layer 230c to form crystals that reflect the orientation of the crystals of the oxide semiconductor layer 230b. In this case, for example, in cross-sectional observation of the oxide semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the oxide semiconductor layer 230a or the oxide semiconductor layer 230c.

[0171] As long as the lattice mismatch between the crystals of the oxide semiconductor layer 230b and the crystals of the oxide semiconductor layer 230a or the oxide semiconductor layer 230c is small, the crystal structure of the oxide semiconductor layer 230a or the oxide semiconductor layer 230c is not particularly limited. The crystal structure of the oxide semiconductor layer 230a or the oxide semiconductor layer 230c may be any of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0172] [Composition of Oxide Semiconductor Layer] As described above, the oxide semiconductor layer 230b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor layer 230b can be formed by, for example, a sputtering method. The oxide semiconductor layer 230b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor layer 230b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor layer 230b preferably contains an element M in addition to zinc. By containing the element M in the oxide semiconductor layer 230b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Therefore, the reliability of a transistor using the oxide semiconductor layer can be improved. Specifically, the oxide semiconductor layer 230b may be a metal oxide having a composition of In:M:Zn = 1:1:1 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:1.2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:0.5 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:2 (atomic ratio) or a composition thereabout, In:M:Zn = 4:2:3 (atomic ratio) or a composition thereabout, In:M:Zn = 1:3:2 (atomic ratio) or a composition thereabout, or In:M:Zn = 1:3:4 (atomic ratio) or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0173] The oxide semiconductor layer 230b may not contain the element M. For example, it may be an In-Zn oxide. Specifically, it may have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Alternatively, indium oxide may be used. Furthermore, it may have a composition containing a trace amount of the element M. For example, it may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, it may have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, or an In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout.

[0174] The oxide semiconductor layer 230a and the oxide semiconductor layer 230c can be a metal oxide having a high proportion of indium. The oxide semiconductor layer 230a and the oxide semiconductor layer 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of indium than the element M. By using a metal oxide having a high proportion of indium, when the oxide semiconductor layer is used in a transistor, the on-state current and frequency characteristics can be increased.

[0175] Alternatively, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c may not contain the element M. For example, they may be In-Zn oxide. Specifically, they may have a composition of In:Zn=1:1 (atomic ratio) or a composition close to that, a composition of In:Zn=2:1 (atomic ratio) or a composition close to that, or a composition of In:Zn=4:1 (atomic ratio) or a composition close to that. Alternatively, indium oxide may be used. Furthermore, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c may contain a trace amount of the element M. Specifically, the composition may be In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition close thereto, In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, or In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition close thereto.

[0176] Note that, when the oxide semiconductor layer 230a and the oxide semiconductor layer 230c are configured without the element M or with a trace amount of the element M, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c preferably contain zinc. For example, the inclusion of zinc may facilitate CAAC formation when the oxide semiconductor layer 230a and the oxide semiconductor layer 230c are converted into CAAC using the oxide semiconductor layer 230b as a nucleus. Furthermore, the inclusion of zinc may reduce the concentration of oxygen vacancies during film formation of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c compared to indium oxide that does not contain zinc as a main component. Therefore, when oxygen is added to the entire oxide semiconductor layer 230, oxygen can be sufficiently distributed throughout the entire layer. This suppresses negative shifts in the threshold voltage of the transistor, increases in the S value of the transistor, and the like, thereby achieving favorable transistor characteristics.

[0177] The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is kept constant in the subthreshold region.

[0178] One or more of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c can be a metal oxide having a higher proportion of indium than the oxide semiconductor layer 230b.

[0179] Furthermore, a metal oxide containing a higher proportion of indium than the oxide semiconductor layer 230b can be used for the oxide semiconductor layer 230a and the oxide semiconductor layer 230c, and a metal oxide containing indium, the element M, and zinc can be used for the oxide semiconductor layer 230b. When the oxide semiconductor layer 230b contains zinc and the element M, the crystallinity of the oxide semiconductor layer 230b can be improved, oxygen vacancies can be suppressed, and the reliability of the transistor can be improved. Furthermore, when a metal oxide containing a higher proportion of indium than the oxide semiconductor layer 230b is used for the oxide semiconductor layer 230a and the oxide semiconductor layer 230c, the current flowing through the oxide semiconductor layer when the transistor is on can be increased.

[0180] Alternatively, for example, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c may be made of a metal oxide having a higher proportion of gallium than the oxide semiconductor layer 230b. For example, the oxide semiconductor layer 230a and the oxide semiconductor layer 230c may preferably be made of a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereof, a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereof, or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 or a composition thereof. Increasing the proportion of gallium may result in the band gaps of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c being larger than those of the oxide semiconductor layer 230b. As a result, the oxide semiconductor layer 230b is sandwiched between the oxide semiconductor layer 230a and the oxide semiconductor layer 230c, which have larger band gaps, and the oxide semiconductor layer 230b mainly functions as a current path (channel). By sandwiching the oxide semiconductor layer 230b between the oxide semiconductor layer 230a and the oxide semiconductor layer 230c, it is possible to reduce trap states at the interface of the oxide semiconductor layer 230b and in the vicinity thereof. This makes it possible to realize a buried channel transistor in which the channel is located away from the insulating layer interface, thereby increasing the field-effect mobility. In addition, the influence of interface states that may be formed on the back channel side is reduced, which makes it possible to suppress light degradation of the transistor (e.g., negative bias light degradation) and improve the reliability of the transistor.

[0181] Alternatively, for example, a metal oxide having a higher proportion of gallium than the oxide semiconductor layer 230a and the oxide semiconductor layer 230c can be used as the oxide semiconductor layer 230b. This may allow the band gaps of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c to be smaller than that of the oxide semiconductor layer 230b. This allows the oxide semiconductor layer 230c closer to the conductive layer 260 functioning as a gate electrode to function as a channel. Furthermore, when the transistor has a second gate electrode, the oxide semiconductor layer 230a closer to the second gate electrode can function as a channel. In this case, by using a metal oxide having a higher proportion of indium than the oxide semiconductor layer 230b for the oxide semiconductor layer 230a and the oxide semiconductor layer 230c, the current flowing through the oxide semiconductor layer when the transistor is on can be increased. Furthermore, when the difference in band gap between the oxide semiconductor layer 230c (oxide semiconductor layer 230a) and the oxide semiconductor layer 230b is small, both the oxide semiconductor layer 230b and the oxide semiconductor layer 230c can function as channels.

[0182] Furthermore, by making the oxide semiconductor layer 230a closer to the conductive layer 220 function as a current path and increasing the current by using a metal oxide having a high proportion of indium as the oxide semiconductor layer 230a, it may be possible to reduce the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230a. Furthermore, by making the oxide semiconductor layer 230c closer to the conductive layer 240 function as a current path and increasing the current by using a metal oxide having a high proportion of indium as the oxide semiconductor layer 230c, it may be possible to reduce the contact resistance between the conductive layer 240 and the oxide semiconductor layer 230c.

[0183] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductor layer 230a and the oxide semiconductor layer 230c have compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the oxide semiconductor layer 230b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductor layer 230a and the oxide semiconductor layer 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c and in a region including the oxide semiconductor layer 230b.

[0184] In particular, even when the oxide semiconductor layers 230 a and 230 c have a high indium content, they can have suitable crystallinity for use as semiconductor layers of transistors. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the indium content can improve the on-state characteristics of the transistor, while the CAAC structure with high crystallinity can improve reliability.

[0185] The oxide semiconductor layer 230a and the oxide semiconductor layer 230c may have different compositions.

[0186] The oxide semiconductor layer 230a and the oxide semiconductor layer 230c may be formed using a metal oxide having the same composition as that of the oxide semiconductor layer 230b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0187] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness or both than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0188] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0189] The composition of the metal oxide used in the oxide semiconductor layer 230 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0190] [Oxide Semiconductor Layer of Transistor] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0191] When the oxide semiconductor layer 230 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer 230 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. In a transistor used in a smaller semiconductor device, the thickness of the oxide semiconductor layer 230 is preferably 1 nm to 3 nm, or 5 nm, and is preferably 20 nm to 15 nm, 12 nm to 10 nm.

[0192] The thickness of the oxide semiconductor layer 230b is preferably, for example, 200 nm or less. When the oxide semiconductor layer 230b has a layer shape, the thickness is preferably, for example, 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and even more preferably 2 nm or more and 100 nm or less.

[0193] Alternatively, if the oxide semiconductor layer 230b can function as a crystal nucleus, the oxide semiconductor layer 230b may not exist as a layer but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor layer 230b exist discretely.

[0194] The oxide semiconductor layer 230a and the oxide semiconductor layer 230c each have a thickness of, for example, 1 nm to 50 nm, preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and even more preferably 2 nm to 20 nm.

[0195] The oxide semiconductor layer of one embodiment of the present invention contains a metal oxide.

[0196] Metal oxides may have lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, planar defects such as grain boundaries, and volume defects such as voids. Factors that cause lattice defects include a discrepancy in the ratio of the number of atoms of the constituent elements (an excess or deficiency of constituent atoms) and impurities.

[0197] When a metal oxide is used for the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used for the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used for the semiconductor layer of a transistor has few lattice defects.

[0198] The type of lattice defects likely to exist in a metal oxide and the amount of lattice defects present vary depending on the structure of the metal oxide or the method for forming the metal oxide film.

[0199] Therefore, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer of a transistor. For example, it is preferable to use a metal oxide having a CAAC structure or a metal oxide with a single crystal structure. By using such a metal oxide for a transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.

[0200] Furthermore, a metal oxide that increases the on-state current of the transistor is preferably used for the channel formation region of the transistor. To increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. To increase the mobility of the metal oxide, it is necessary to improve the transport of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transport of carriers. Carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0201] [Impurities in Oxide Semiconductor] Here, the influence of each impurity in an oxide semiconductor will be described.

[0202] It is preferable that the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer have fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or metal elements than the source and drain regions. Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H may be formed, generating electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics. Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0203] Therefore, reducing the impurity concentration in an oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in an oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0204] For example, if an oxide semiconductor does not contain aluminum as a main component, the physical properties of the oxide semiconductor may be affected if the oxide semiconductor contains a large amount of aluminum as an impurity. Examples of oxide semiconductors that do not contain aluminum as a main component include indium zinc oxide (In—Zn oxide) and indium gallium zinc oxide (In—Ga—Zn oxide).

[0205] For example, when aluminum is present in an IGZO film in an oxidized state (Al ２ O ３ When such a high-resistance IGZO film is used as a semiconductor layer, the on-current of the transistor decreases.

[0206] On the other hand, aluminum has a high bond dissociation energy with oxygen and functions as a carrier suppressing element. Specifically, the bond dissociation energy between aluminum and oxygen is higher than the bond dissociation energy between Ga and oxygen. For this reason, the presence of aluminum in the IGZO film can make it difficult for oxygen vacancies (Vo) to be generated. When an IGZO film in which Vo is difficult to generate is used as a semiconductor layer, negative bias light photodegradation of a transistor can be suppressed. For this reason, aluminum in the oxide semiconductor does not need to be completely removed, and in some cases it may be contained in the oxide semiconductor to an extent that does not have an adverse effect.

[0207] Therefore, the aluminum concentration in the oxide semiconductor is preferably low so that the reliability and electrical characteristics of the transistor are both good, or the aluminum concentration is preferably extremely low so that the on-state current of the transistor is sufficiently high.

[0208] For example, the aluminum concentration in the channel formation region of the oxide semiconductor obtained by STEM-EDX is preferably 3 atomic % or less, and more preferably 1 atomic % or less.

[0209] The aluminum concentration of the oxide semiconductor obtained by SIMS was 1×10 ２０ atoms / cm ３ Less than 5 x 10 is more preferable. １９ atoms / cm ３ More preferably, 1×10 or less １９ atoms / cm ３ The following are more preferable: In particular, it is preferable that the aluminum concentration is low in the channel formation region.

[0210] The presence of aluminum and the state of the aluminum present can be confirmed from the Al2p spectrum obtained by XPS analysis of an oxide semiconductor. For example, when the peak position is in the range of 74.2 eV to 74.8 eV, it can be said that aluminum is present in an oxidized state.

[0211] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably１９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0212] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0213] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ In addition, the oxide semiconductor layer used in the transistor has a hydrogen concentration measured by SIMS after deposition of less than 1×10 １９ atoms / cm ３ or more, or 5 x 10 １９ atoms / cm ３ or more, or 1 x 10 ２０ atoms / cm ３ In particular, an oxide semiconductor layer formed by an ALD method may contain hydrogen after deposition due to hydrogen contained in a precursor or an oxidizing agent. In such a case, it is preferable to reduce the hydrogen concentration in the oxide semiconductor layer by heat treatment after deposition. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer obtained by SIMS is 5×10 ２０ atoms / cm ３ Less than or 1 x 10 ２０ atoms / cm ３ Less than or 5 x 10１９ atoms / cm ３ The hydrogen concentration in the oxide semiconductor layer is preferably reduced to less than 1×10 １９ atoms / cm ３ When the oxide semiconductor layer contains a small amount of oxygen, the resistance can be preferably reduced in some cases in a low-resistance region that functions as a source region or a drain region, for example.

[0214] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0215] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0216] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0217] The crystal orientation can be obtained from the fast Fourier transform (FFT) pattern by performing FFT processing on the TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0218] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystalline portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0219] The c-axis orientation rate can be calculated by calculating the percentage of c-axis oriented regions in a map showing crystal orientation. Here, the c-axis oriented regions are defined as regions whose orientation coincides with the c-axis and regions whose orientation differs from the c-axis by 20° or less.

[0220] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by TEM observation of a cross section or a plan view of the oxide semiconductor layer. The region where FFT is performed (also referred to as an FFT window) can be a circle with a diameter of 1.0 nm, for example. Note that the region where FFT is performed is not limited to a circle.

[0221] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 50% or more, preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more.

[0222] The c-axis orientation rates of the region formed as the oxide semiconductor layer 230a, the region formed as the oxide semiconductor layer 230b, and the region formed as the oxide semiconductor layer 230c are denoted by Rc1, Rc2, and Rc3, respectively. Rc2 is 50% or more, preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is 50% or more, preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0223] After the oxide semiconductor layer 230 is formed, the boundaries between the oxide semiconductor layers 230a, 230b, and 230c may not be clearly observed.

[0224] The oxide semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, starting from the top of the layer 229. Each region has a layer shape.

[0225] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rate of the third region is 50% or more, preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. The c-axis orientation rate of the second region is 50% or more, preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0226] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor layer 230 .

[0227] Alternatively, the layer thickness in each region may be approximately the same, for example.

[0228] [Method for Producing Metal Oxide Using ALD] Here, an example of a method for forming a metal oxide film having a three-layered crystalline structure using ALD is described with reference to FIGS. 3A to 3E . First, a precursor 611a is introduced into a chamber and adsorbed onto the surface of a substrate 610 (see FIG. 3A ; hereinafter, this step may be referred to as the first step). Here, as shown in FIG. 3A , adsorption of the precursor 611a onto the surface of the substrate 610 activates a self-limiting mechanism for the surface chemical reaction, preventing further adsorption of the precursor 611a onto the layer of the precursor 611a on the substrate 610. The appropriate substrate temperature range within which the self-limiting mechanism for the surface chemical reaction operates is also referred to as the ALD window. The ALD window is determined by the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor, and may be, for example, 100°C to 600°C, preferably 200°C to 400°C.

[0229] Next, an inert gas (argon, helium, nitrogen, or the like) is introduced into the chamber to evacuate the excess precursor 611a and reaction products from the chamber (hereinafter, this step may be referred to as the second step). Alternatively, instead of introducing an inert gas into the chamber, the excess precursor and reaction products may be evacuated from the chamber by vacuum evacuation. The second step is also called purging.

[0230] Next, reactant 612a (e.g., oxidant (ozone (O ３ ), oxygen (O ２ ), water (H ２ O), and their plasma, radicals, ions, etc.) are introduced into the chamber and reacted with precursor 611a adsorbed on the surface of substrate 610, causing some of the components contained in precursor 611a to be desorbed while leaving the constituent molecules of precursor 611a adsorbed on substrate 610 (see FIG. 3B ; hereinafter, this step may be referred to as the third step). As a result, a layer of oxide 613a formed by oxidizing part of precursor 611a is formed on the surface of substrate 610.

[0231] Next, excess reactant 612a or reaction products are discharged from the chamber by introducing an inert gas or evacuating (hereinafter, this step may be referred to as the fourth step).

[0232] Next, precursor 611b having a metal element different from precursor 611a is introduced, and a process similar to the first step is performed to adsorb precursor 611b onto the surface of oxide 613a (see FIG. 3C). Here, as shown in FIG. 3C, the adsorption of precursor 611b onto the oxide 613a layer triggers a self-limiting mechanism of the surface chemical reaction, preventing further adsorption of precursor 611b onto the layer of precursor 611b on substrate 610.

[0233] Next, as in the second step, excess precursor 611b and reaction products are discharged from the chamber by introducing an inert gas or evacuating the chamber.

[0234] Next, as in the third step, reactant 612b is introduced into the chamber. Here, reactant 612b may be the same as reactant 612a or may be different (see FIG. 3D). As a result, a layer of oxide 613b, which is formed by oxidizing a portion of precursor 611b, is formed on the layer of oxide 613a.

[0235] Next, as in the fourth step, excess reactant 612b and reaction products are discharged from the chamber by introducing an inert gas or by vacuum evacuation.

[0236] Furthermore, the first to fourth steps can be performed in a similar manner to form a layer of oxide 613c on the layer of oxide 613b. In this manner, by repeatedly performing the steps of forming the oxides 613a to 613c, a metal oxide having a layered crystal structure in which the stacked structure of the oxides 613a to 613c is repeated can be formed (see FIG. 3E). That is, the first to fourth steps can be used as one set to form an oxide layer, and by repeating this set, a layered crystal structure in which multiple oxide layers are stacked can be formed.

[0237] The thickness of the metal oxide having a layered crystal structure may be 1 nm or more and less than 100 nm, preferably 3 nm or more and less than 20 nm.

[0238] 3A to 3E are preferably performed while heating the substrate. For example, the substrate temperature may be set to 200° C. or higher and 600° C. or lower, preferably 300° C. or higher and lower than the decomposition temperature of the precursor. When forming a film by the ALD method using multiple precursors of different types, the substrate temperature is preferably set to lower than the decomposition temperature of the lowest precursor among the multiple precursors. This allows the multiple precursors used to be adsorbed onto the target (e.g., substrate) without being decomposed during film formation by the ALD method.

[0239] By performing the above film formation while heating the substrate in such a temperature range, impurities such as hydrogen or carbon contained in the precursor and reactant can be removed from the metal oxide in each process of steps 1 to 4. For example, carbon in the metal oxide can be removed by converting it into CO ２ and CO, and hydrogen in the metal oxide is released as H ２ Furthermore, at the same time as the removal of the impurities, the metal atoms and oxygen atoms are rearranged, and the layers of the oxides can be arranged in a highly ordered manner. Therefore, a metal oxide with a highly crystalline layered crystal structure can be formed.

[0240] In order to perform film formation while heating the substrate within the above temperature range, it is preferable that the precursor used in the film formation has a high decomposition temperature. For example, the decomposition temperature of the precursor is preferably 200°C or higher and 700°C or lower, and more preferably 300°C or higher and 600°C or lower. As a precursor with such a high decomposition temperature, it is preferable to use a precursor formed from an inorganic substance (hereinafter referred to as an inorganic precursor). Inorganic precursors generally tend to have a higher decomposition temperature than precursors formed from organic substances (hereinafter referred to as organic precursors), and therefore some have an ALD window within the above temperature range. Furthermore, since inorganic precursors do not contain impurities such as hydrogen or carbon, an increase in the concentration of impurities such as hydrogen or carbon in the metal oxide film can be prevented.

[0241] Furthermore, it is preferable to perform a heat treatment after the metal oxide film is formed. In particular, it is preferable to perform a heat treatment continuously after the film is formed by the ALD method without exposing it to the outside air. The heat treatment can be performed under the conditions described in FIGS. 1A to 1D.

[0242] By carrying out the heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be converted to CO ２ and CO, and hydrogen in the metal oxide is released as H ２ The impurities can be removed by the reaction of the metal atoms and oxygen atoms, and the metal atoms and oxygen atoms can be released as O. Furthermore, at the same time as the removal of the impurities, the rearrangement of the metal atoms and oxygen atoms can be performed, improving the crystallinity. Therefore, a metal oxide with a highly crystalline layered crystal structure can be formed.

[0243] Furthermore, after forming the metal oxide film, it is preferable to perform microwave treatment in an oxygen-containing atmosphere to reduce the impurity concentration in the metal oxide. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave treatment is performed on a metal oxide in an oxygen-containing atmosphere, the present invention is not limited to this. For example, microwave treatment may be performed on an insulating film, more specifically, a silicon oxide film, located near the metal oxide in an oxygen-containing atmosphere.

[0244] By carrying out the impurity removal treatment, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be removed by CO ２ and CO, and hydrogen in the metal oxide is released as H ２ O can be released. Furthermore, simultaneously with the removal of the impurities, rearrangement of metal atoms and oxygen atoms occurs, improving crystallinity. Therefore, a metal oxide having a crystalline portion can be formed. Furthermore, a metal oxide having a highly crystalline layered crystal structure, particularly a metal oxide having the above-mentioned CAAC structure, can be formed.

[0245] The impurity removal treatment may be performed not only after the metal oxide film is formed, but also during the metal oxide film formation. For example, the impurity removal treatment may be performed intermittently during the metal oxide film formation process.

[0246] Examples of the impurity removal treatment include plasma treatment, microwave treatment, and heat treatment. The impurity removal treatment may be performed while irradiating light.

[0247] When performing the plasma treatment or microwave treatment, the substrate may be heated to a temperature preferably equal to or higher than room temperature (e.g., 25°C), 100°C, 200°C, 300°C, or 400°C, and 500°C or lower, or 450°C or lower.

[0248] 3A to 3E, the stacked structure of the oxides 613a to 613c is repeated, but the present invention is not limited to this. For example, a metal oxide having a single layer, two layers, or four or more oxide layers repeatedly formed may be used.

[0249] Furthermore, unless otherwise specified, in the present specification and the like, when ozone, oxygen, or water is used as a reactant or oxidant, these are not limited to gaseous or molecular states, but also include plasma, radical, and ionic states. When forming a film using an oxidant in a plasma, radical, or ionic state, a plasma ALD apparatus may be used.

[0250] To remove impurities such as carbon or hydrogen contained in the precursor, it is preferable to allow the precursor to react sufficiently with the oxidizing agent. For example, the pulse time for introducing the oxidizing agent may be increased. Alternatively, the oxidizing agent may be introduced multiple times. When introducing the oxidizing agent multiple times, the same type of oxidizing agent may be introduced, or different types of oxidizing agents may be introduced. For example, water may be introduced into the chamber as a first oxidizing agent, followed by evacuation, and ozone or oxygen containing no hydrogen may be introduced into the chamber as a second oxidizing agent, followed by evacuation.

[0251] In the above description, an example is shown in which the first source gas is introduced into the chamber and then the second source gas is introduced into the chamber, but the present invention is not limited to this. The second source gas may be introduced into the chamber and then the first source gas may be introduced into the chamber. That is, the third and fourth steps may be performed first, followed by the first, second, third, and fourth steps, and then the first to fourth steps may be repeated to form a film. Furthermore, the third and fourth steps may be repeated multiple times, and then the first to fourth steps may be repeated to form a film.

[0252] In this way, it is preferable to perform the third step and the fourth step once or multiple times before the first step, since this allows the film formation atmosphere in the chamber to be controlled. For example, in the third step, O ３ , and O ２ By introducing oxygen into the chamber, the chamber can be filled with an oxygen atmosphere. By depositing a film in an oxygen atmosphere, the oxygen concentration in the film can be increased, which is preferable. Furthermore, oxygen can also be supplied to the insulator and oxide underlying the film. A semiconductor device formed using such a method has excellent characteristics and high reliability. Furthermore, for example, by introducing water as an oxidizing agent in the third step, hydrophilic groups can be formed on the surface to be formed. This can further improve the adsorption of the precursor.

[0253] Furthermore, after the first and second steps, the introduction of the second source gas in the third step and the evacuation or introduction of an inert gas in the fourth step may be repeated multiple times. That is, the first and second steps may be performed after the first, second, third, fourth, third, fourth steps, and so on are repeated.

[0254] For example, in the third step, O ３ , and O ２ In the third step, an inert gas is introduced, and in the fourth step, this process may be repeated several times. When the third and fourth steps are repeated, it is not necessary to repeatedly introduce the same type of raw material gas. For example, in the first third step, H is used as the oxidizing agent. ２ O was used as the oxidizing agent in the third step from the second time onwards. ３ may also be used.

[0255] In this way, by repeatedly introducing an oxidizing agent and an inert gas (or evacuating) into the chamber multiple times in a short period of time, excess hydrogen atoms, carbon atoms, chlorine atoms, etc. can be more reliably removed from the precursor adsorbed on the substrate surface and expelled to the outside of the chamber. Furthermore, by increasing the number of types of oxidizing agents to two, more excess hydrogen atoms, etc. can be removed from the precursor adsorbed on the substrate surface. In this way, by preventing hydrogen atoms from being incorporated into the film during film formation, the amount of water, hydrogen, etc. contained in the formed film can be reduced.

[0256] By using this method, the amount of desorption of water molecules was found to be 1.0 × 10 in the surface temperature range of 100°C to 700°C or 100°C to 500°C in TDS analysis. １３ molecule / cm ２ Above 1.0 x 10 １６ molecule / cm ２ or less, preferably 1.0 × 10 １３ molecule / cm ２ Above 3.0 x 10 １５ molecule / cm ２ The following films can be formed:

[0257] The ALD method is a film formation method in which precursors and reactants are reacted using thermal energy. The temperature required for the reaction of the precursors and reactants is determined by their temperature characteristics, vapor pressure, decomposition temperature, etc., but is generally 100°C to 600°C, preferably 200°C to 600°C, and more preferably 300°C to 600°C.

[0258] Furthermore, an ALD method in which, in addition to the reaction between the precursor and reactant, a plasma-excited reactant is introduced into the chamber as a third source gas, is sometimes called a plasma ALD method. In this case, a plasma generating device is provided at the introduction portion of the third source gas. Inductively coupled plasma (ICP) can be used to generate the plasma. In contrast, an ALD method in which the reaction between the precursor and reactant is carried out using thermal energy is sometimes called a thermal ALD method.

[0259] In the plasma ALD method, a plasma-excited reactant is introduced in the third step to form a film. Alternatively, the first to fourth steps are repeatedly performed while a plasma-excited reactant (second reactant) is introduced, thereby forming a film. In this case, the reactant introduced in the third step is called the first reactant. In the plasma ALD method, the second reactant used in the third source gas can be the same material as the oxidizer. That is, plasma-excited ozone, oxygen, and water can be used as the second reactant. In addition to the oxidizer, a nitriding agent may also be used as the second reactant. Nitrogen (N ２ ) or ammonia (NH ３ ) can be used. Nitrogen (N ２ ) and hydrogen (H ２ ) can be used as a nitriding agent. ２ ) 5%, hydrogen (H ２A 95% mixed gas of nitrogen and ammonia can be used as a nitriding agent. By conducting film formation while introducing plasma-excited nitrogen or ammonia, nitride films such as metal nitride films can be formed.

[0260] The carrier gas for the second reactant may be argon (Ar), helium (He), or nitrogen (N ２ ) may also be used. Using a carrier gas such as argon, helium, or nitrogen is preferable because it facilitates plasma discharge and facilitates the generation of a plasma-excited second reactant. Note that when forming an oxide film such as a metal oxide film using the plasma ALD method, using nitrogen as the carrier gas may result in nitrogen being mixed into the film, making it impossible to obtain the desired film quality. In this case, it is preferable to use argon or helium as the carrier gas.

[0261] The ALD method can deposit extremely thin films with uniform thickness and has a high surface coverage even on uneven surfaces.

[0262] Furthermore, plasma ALD allows deposition at temperatures even lower than those achieved by thermal ALD. For example, plasma ALD may allow deposition at temperatures below 100° C. without reducing the deposition rate.

[0263] Furthermore, when performing plasma ALD, plasma damage can be suppressed by generating plasma from a plasma source such as an inductively coupled plasma (ICP) or electron cyclotron resonance plasma (ECR) at a distance from the substrate.

[0264] Here, the atomic arrangement in the crystal when the metal oxide with a layered crystal structure is In-M-Zn oxide will be described with reference to Figures 4A to 4D. In Figures 4B and 4D, atoms are represented by spheres (circles), and bonds between metal atoms and oxygen atoms are represented by lines. In Figures 4B and 4D, the c-axis direction in the crystal structure of In-M-Zn oxide is represented by an arrow. The a-b plane direction in the crystal structure of In-M-Zn oxide is perpendicular to the c-axis direction represented by the arrow in Figures 4B and 4D.

[0265] 4A is a diagram showing an oxide 660 having an In-M-Zn oxide formed in a structure 650. Here, the structure refers to an element constituting a semiconductor device such as a transistor. The structure 650 includes a substrate, a conductor such as a gate electrode, a source electrode, and a drain electrode, an insulator such as a gate insulating film, an interlayer insulating film, and a base insulating film, a metal oxide, and a semiconductor such as silicon. FIG. 4A shows a case where the surface to be deposited of the structure 650 is arranged parallel to the substrate (or base, not shown).

[0266] 4B is an enlarged view showing the atomic arrangement in the crystal in a region 653, which is a part of the oxide 660 in FIG. 4A. The composition of the oxide 660 shown in FIGS. 4A and 4B is In:M:Zn=1:1:1 [atomic ratio], and the crystal structure is YbFe ２ O ４ The element M is a metal element with a valence of +3.

[0267] 4B , the crystals of the oxide 660 are formed by repeatedly stacking a layer 621 containing indium (In) and oxygen, a layer 631 containing the element M and oxygen, and a layer 641 containing zinc (Zn) and oxygen, in this order. The layers 621, 631, and 641 are arranged substantially parallel to the deposition surface of the structure 650. That is, the a-b plane of the oxide 660 is substantially parallel to the deposition surface of the structure 650, and the c-axis of the oxide 660 is substantially parallel to the normal to the deposition surface of the structure 650.

[0268] As shown in FIG. 4B , each of the layers 621, 631, and 641 of the crystal is composed of one metal element and oxygen, and is arranged with good crystallinity, thereby increasing the mobility of the metal oxide.

[0269] Note that the In-M-Zn oxide with an atomic ratio of In:M:Zn=1:1:1 is not limited to the structure shown in FIG. 4B . The stacking order of the layers 621, 631, and 641 may be changed. For example, the layers 621, 641, and 631 may be repeatedly stacked in this order. Alternatively, the layers 621, 631, 641, 621, 641, and 631 may be repeatedly stacked in this order. Furthermore, part of the element M in the layer 631 may be substituted with zinc, and part of the zinc in the layer 641 may be substituted with the element M.

[0270] In the above, an example of forming an In-M-Zn oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] was shown. （１＋α） M （１−α） O ３ (ZnO) ｍ (α is a real number greater than 0 and less than 1, and m is a positive number) can similarly have a layered crystal structure. As an example, an In-M-Zn oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] is shown in FIGS. 4C and 4D.

[0271] Figure 4C shows an oxide 662 having an In-M-Zn oxide formed on the structure 650. Figure 4D is an enlarged view showing the atomic arrangement in the crystal in a region 654 that is part of the oxide 662 in Figure 4C.

[0272] 4D , the crystals of the oxide 662 include a layer 622 containing indium (In), the element M, and oxygen, a layer 641 containing zinc (Zn) and oxygen, and a layer 631 containing the element M and oxygen. In the oxide 662, multiple layers are repeatedly stacked in the order of the layer 622, the layer 641, the layer 631, and the layer 641. The layers 622, 631, and 641 are arranged substantially parallel to the deposition surface of the structure 650. That is, the a-b plane of the oxide 662 is substantially parallel to the deposition surface of the structure 650, and the c-axis of the oxide 662 is substantially parallel to the normal to the deposition surface of the structure 650.

[0273] 4D , the In-M-Zn oxide having an atomic ratio of In:M:Zn=1:3:4 may have a structure that is different from that shown in FIG. 4D within the range of the atomic ratio of In:M:Zn=1:3:4. For example, the stacking order of the layers 622, 631, and 641 may be changed. Furthermore, part of the element M in the layer 631 may be substituted with zinc, and part of the zinc in the layer 641 may be substituted with the element M. Furthermore, the layer 621 or the layer 631 may be formed instead of the layer 622.

[0274] Next, a method for forming the oxide 660 having the In-M-Zn oxide shown in FIGS. 4A and 4B will be described in detail with reference to FIGS. 5A to 6C.

[0275] First, a source gas containing an indium-containing precursor is introduced into the chamber, and the precursor is adsorbed onto the surface of the structure 650 (see FIG. 5A ). Here, the source gas contains not only the precursor but also a carrier gas such as argon, helium, or nitrogen.

[0276] The aluminum content of the indium-containing precursor is preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, even more preferably 10 ppm or less, and still more preferably 1 ppm or less.

[0277] By using a precursor with a low aluminum content, a metal oxide that does not contain aluminum as a main component can be produced, which prevents the aluminum concentration in the formed metal oxide film from becoming too high.

[0278] Furthermore, as the precursor used in this embodiment, it is preferable to use a precursor purified by distillation (also called rectification) two or more times. By using such a precursor, it is easy to form a metal oxide film with few impurities, which is preferable. By performing distillation multiple times, it is possible to further suppress impurities originating from the starting materials used in the precursor production from remaining in the precursor, which is preferable. Note that the present invention is not limited to the above, and a precursor purified by one distillation, i.e., simple distillation, may also be used. By using simple distillation, it is possible to reduce production costs, which is preferable.

[0279] Here, the precursor-containing source gas contains a carrier gas such as argon, helium, or nitrogen in addition to the precursor.

[0280] Examples of precursors containing indium that can be used include trimethylindium (structural formula (101) below), triethylindium (structural formula (102) below), ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedioate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, dimethyl(2-propanolato)indium, trifluoroindium (indium(III) fluoride), indium(III) chloride, indium(III) bromide, and indium(III) iodide.

[0281] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as indium trichloride, indium tribromide, and indium triiodide. The decomposition temperature of indium trichloride is approximately 500°C or higher and 700°C or lower. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C or higher and 600°C or lower, for example, at 500°C.

[0282] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0283] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than indium while leaving indium adsorbed on the substrate, thereby forming a layer 621 in which indium and oxygen are combined (see Figure 5B).

[0284] The oxidizing agent may be ozone, oxygen, water, nitrogen dioxide, hydrogen peroxide, or their plasma, radicals, ions, etc. Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge excess reactants, reaction products, etc. from the chamber.

[0285] Next, a source gas containing a precursor having element M is introduced into the chamber, and the precursor is adsorbed onto layer 621 (see FIG. 5C). In addition to the precursor, the source gas contains a carrier gas such as argon, helium, or nitrogen.

[0286] The aluminum content of the precursor having element M is preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, even more preferably 10 ppm or less, and still more preferably 1 ppm or less.

[0287] When gallium is used as the element M, examples of precursors containing gallium include trimethylgallium, triethylgallium (structural formula (103) below), tris(dimethylamido)gallium (structural formula (104) below), triphenylgallium, diethyl(3-methyl-2,4-cyclopropanedien-1-yl)gallium, [4-(1,1-dimethyl)phenyl]dimethylgallium, dimethyl(4-methylphenyl)gallium, dimethylphenylgallium, methyldiphenylgallium, ethyldimethylgallium, dimethylmethylenegallium, gallium(III) acetylacetonate, and tris(2,2,6,6-tetramethylphenyl)gallium. Examples of suitable gallium nitrate include gallium tetramethyl-3,5-heptanedionate, dimethyl(2-methyl-2-propanolato)gallium, methoxydimethylgallium, hydroxydimethylgallium, (methanethiolato)dimethylgallium, dimethylchlorogallium, diethylchlorogallium, chlorodipropylgallium, bromodimethylgallium, bromodiethylgallium, dimethylgallium isopropoxide, dimethyliodogallium, chlorobis(2,2-dimethylpropyl)gallium, gallium(III) fluoride, gallium(III) chloride, gallium(III) bromide, and gallium(III) iodide.

[0288] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the gallium-containing precursor. Examples of the gallium-containing inorganic precursor include halogen-based gallium compounds such as gallium trichloride, gallium tribromide, and gallium triiodide. Gallium trichloride has a decomposition temperature of approximately 550°C to 700°C. Therefore, by using gallium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 450°C to 650°C, for example, 550°C.

[0289] Examples of precursors containing tin include tetramethyltin, tetraethyltin, tetraethenyltin, tetraallyltin, tributylvinyltin, allyltributyltin, tetrakisdimethylamidotin(IV), tributylstannylacetylene, tributylphenyltin, chlorotrimethyltin, chlorotriethyltin, tin(IV) fluoride, tin(IV) chloride, tin(IV) bromide, and tin(IV) iodide.

[0290] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0291] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming layer 631 in which element M and oxygen are combined (see FIG. 5D). At this time, some of the oxygen constituting layer 641 may be adsorbed onto layer 631. Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge excess reactant, reaction products, etc. from the chamber.

[0292] Next, a source gas containing a zinc-containing precursor is introduced into the chamber, and the precursor is adsorbed onto layer 631 (see FIG. 6A). At this time, a part of layer 641 in which zinc and oxygen are combined may be formed. In addition to the precursor, the source gas contains a carrier gas such as argon, helium, or nitrogen.

[0293] The aluminum content of the zinc-containing precursor is preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, even more preferably 10 ppm or less, and still more preferably 1 ppm or less.

[0294] Examples of precursors that can be used that contain zinc include dimethylzinc, diethylzinc (structural formula (105) below), bis(1-methylethyl)zinc, bis(1,1-dimethylethyl)zinc, dibutylzinc, diethenylzinc, dicyclohexylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc acetate, zinc fluoride, zinc chloride, chloromethylzinc, zinc bromide, bromomethylzinc, and zinc iodide.

[0295] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the zinc-containing precursor. Examples of the zinc-containing inorganic precursor include halogen-based zinc compounds such as zinc dichloride, zinc dibromide, and zinc diiodide. The decomposition temperature of zinc dichloride is approximately 450°C to 700°C. Therefore, by using zinc dichloride, film formation can be performed by the ALD method while heating the substrate at approximately 350°C to 550°C, for example, at 450°C.

[0296] Next, the introduction of the source gas is stopped, and the chamber is purged to discharge excess precursors and reaction products from the chamber.

[0297] Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, and components other than zinc are desorbed while zinc remains adsorbed on the substrate, thereby forming a layer 641 in which zinc and oxygen are combined (see FIG. 6B). Next, the introduction of the oxidizing agent is stopped, and the chamber is purged to discharge excess reactant and reaction products from the chamber.

[0298] Next, the layer 621 is formed again on the layer 641 by the above-described method (see FIG. 6C). By repeating the above-described method, an oxide 660 can be formed on the substrate or the structure.

[0299] Here, an example of the precursors listed above is shown below.

[0300]

[0301] The precursors listed above may contain one or both of carbon and chlorine in addition to the metal element. A film formed using a precursor containing carbon may contain carbon. Furthermore, a film formed using a precursor containing a halogen, such as chlorine, may contain halogen, such as chlorine.

[0302] As described above, by forming the oxide 660 by the ALD method, a metal oxide can be formed whose c-axis is oriented approximately parallel to the normal direction of the deposition surface. For example, in the oxide semiconductor layer 230 shown in FIGS. 7B and 7C (described later), layered crystals can be formed that are approximately parallel to the sidewall of the opening 290, particularly to the side surface of the insulating layer 280. With this structure, the layered crystals of the oxide semiconductor layer 230 are formed approximately parallel to the channel length direction of the transistor 200, thereby increasing the on-state current of the transistor.

[0303] 5A to 6C are preferably performed while heating the substrate, for example, at a substrate temperature of 200° C. to 600° C., preferably 300° C. to the decomposition temperature of the precursor.

[0304] In order to form a film while heating the substrate within the above temperature range, it is preferable that the precursor used in the film formation has a high decomposition temperature. For example, the decomposition temperature of the precursor is preferably 200°C or higher and 700°C or lower, and more preferably 300°C or higher and 600°C or lower. As a precursor with such a high decomposition temperature, it is preferable to use an inorganic precursor. Inorganic precursors generally tend to have a higher decomposition temperature than organic precursors, so even if film formation is performed while heating the substrate as described above, the precursor is less likely to decompose.

[0305] Examples of inorganic precursors that can be used include the aforementioned indium trichloride, gallium trichloride, and zinc dichloride. As described above, these precursors have decomposition temperatures of approximately 350°C or higher and 700°C or lower, which is significantly higher than the decomposition temperatures of typical organic precursors. However, as described above, the decomposition temperatures of indium trichloride, gallium trichloride, and zinc dichloride are different from one another. When performing film formation by ALD using multiple different types of precursors, it is preferable to set the substrate temperature below the decomposition temperature of the lowest precursor among the multiple precursors. In the above example, the substrate temperature may be set within a range in which zinc dichloride, the precursor with the lowest decomposition temperature, does not decompose. This allows other indium trichloride and gallium trichloride to be adsorbed onto the target (e.g., a substrate) without decomposing.

[0306] 5A to 6C show an example in which the layer 621 containing indium is formed, the layer 631 containing the element M is formed thereon, and the layer 641 containing zinc is further formed thereon, but this embodiment is not limited to this. One of the layer 631 and the layer 641 may be formed, the layer 621 may be formed thereon, and the other of the layer 631 and the layer 641 may be further formed thereon. Alternatively, one of the layer 631 and the layer 641 may be formed, the other of the layer 631 and the layer 641 may be formed thereon, and the layer 621 may be further formed thereon.

[0307] Furthermore, when forming a metal oxide having an atomic ratio different from In:M:Zn=1:1:1 (atomic ratio), the layers 621, 631, and 641 may be formed appropriately according to the atomic ratio. For example, as shown in FIG. 6A , the formation of the layer 641 may be repeated multiple times before and after the formation of the layer 631, thereby forming a stack of the layers 631 and 641 between the two layers 621, with the desired number of atoms, number of layers, and thickness.

[0308] When various semiconductor devices are manufactured, both the metal oxide of one embodiment of the present invention and another metal oxide may be used. For example, the metal oxide of one embodiment of the present invention may be used in combination with a metal oxide containing at least one of indium and zinc and aluminum (which may further contain at least one of gallium and tin).

[0309] Examples of metal oxides containing aluminum and at least one of indium and zinc include indium gallium aluminum oxide (In—Ga—Al oxide), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO, IGZAO, or IAGZO).

[0310] Examples of aluminum-containing precursors include trimethylaluminum, triethylaluminum, chlorodimethylaluminum, dichloromethylaluminum, bromodimethylaluminum, iododimethylaluminum, aluminum acetylacetonate, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), dimethylchloroaluminum, diethylchloroaluminum, aluminum(III) chloride, aluminum(III) bromide, and aluminum(III) iodide.

[0311] <Heat Treatment> The heat treatment temperature may be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, and more preferably 350°C or higher and 550°C or lower. A typical temperature is 400°C ± 25°C (375°C or higher and 425°C or lower). The treatment time may be 10 hours or less, or 1 minute to 5 hours or lower, or 1 minute to 2 hours or lower. When an RTA apparatus is used, the treatment time may be, for example, 1 second to 5 minutes.

[0312] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0313] The heat treatment can be carried out, for example, in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. When the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to set the oxygen gas concentration at about 20%. The heat treatment may also be carried out under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment may be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen. The heat treatment may also be carried out in an atmosphere of ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less).

[0314] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the metal oxide as much as possible.

[0315] <Microwave Treatment> Microwave treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves, for example. In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave treatment can also be called microwave-excited high-density plasma treatment.

[0316] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves in the microwave treatment device is preferably 1000 W to 10,000 W, preferably 2000 W to 5,000 W. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the film.

[0317] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, and more preferably from 300 to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0318] The microwave treatment can be carried out using, for example, oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O２ +Ar)) is set to 10% or more and 30% or less. By performing microwave treatment in an atmosphere containing oxygen in this manner, the carrier concentration of the oxide semiconductor layer can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration of the oxide semiconductor layer can be prevented.

[0319] Note that the microwave treatment may be performed after the oxide semiconductor layer is formed. For example, the microwave treatment may be performed after an insulating layer (for example, the insulating layer 250 described in a later embodiment) is formed over the oxide semiconductor layer. When the insulating layer includes an insulating layer (for example, an aluminum oxide film) that has a function of capturing or fixing hydrogen, the microwave treatment is preferably performed after the insulating layer is formed. This allows hydrogen generated by the microwave treatment to be captured or fixed to the insulating layer. Therefore, the V included in the channel formation region can be more effectively reduced. Ｏ H can be reduced.

[0320] Furthermore, microwave treatment can improve the film quality and suppress the diffusion of impurities such as hydrogen and water. For example, microwave treatment can be performed after forming a gate insulating layer to improve the film quality of the gate insulating layer, thereby improving the reliability of the transistor. When the gate insulating layer has a stacked structure, microwave treatment may be performed once or multiple times. For example, microwave treatment may be performed after each layer is formed, or after at least one layer is formed. Microwave treatment may also be performed before forming a gate insulating layer. Depending on the treatment temperature, microwave treatment may also serve as a heat treatment.

[0321] This embodiment mode can be combined with other embodiment modes and examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0322] Embodiment 2 In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0323] A semiconductor device of one embodiment of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a first insulating layer, and a second insulating layer.

[0324] The first insulating layer is located over the first conductive layer, and the second conductive layer is located over the first insulating layer. The first insulating layer and the second conductive layer have openings that reach the first conductive layer. The oxide semiconductor layer is in contact with at least a top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer in the openings. The second insulating layer is located over the oxide semiconductor layer in the openings. The third conductive layer overlaps with the oxide semiconductor layer in the openings, with the second insulating layer sandwiched therebetween. Note that the openings are also referred to as openings.

[0325] The first conductive layer functions as one of a source electrode and a drain electrode of the transistor, the second conductive layer functions as the other of the source electrode and the drain electrode of the transistor, the third conductive layer functions as a gate electrode of the transistor, and the second insulating layer functions as a gate insulating layer.

[0326] In this specification, the term "in a cross-sectional view" is used, but it can be specifically rephrased as "in a cross-sectional view from the same direction." For example, when explaining the relationship between multiple components, the relationship in a cross-sectional view from the same direction is explained. In this case, the relationship between the multiple components can be explained using one cross-sectional view.

[0327] In a transistor according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in the height direction. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0328] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0329] In this specification, "edges coincide" means that, in a plan view, at least a portion of the contours of stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "edges coincide" is also used.

[0330] In general, it may be difficult to clearly distinguish between an "exact match" and an "approximate match." For this reason, in this specification and elsewhere, "match" may include both an exact match and an approximate match.

[0331] <Structural Example of Semiconductor Device> The structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 7A to 14C . FIG. 7A is a plan view of a semiconductor device including a transistor 200. FIG. 7B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 7A . FIG. 7C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 7A . FIG. 9A is a cross-sectional view in the XY plane including an insulating layer 280. Note that some elements are omitted in the plan view of FIG. 7A for clarity. Some elements may also be omitted in the subsequent plan views.

[0332] 7A to 7C and 9A includes an insulating layer 210 over a substrate (not shown), a transistor 200 over the insulating layer 210, an insulating layer 280 over the insulating layer 210, and insulating layers 283 and 285 over the transistor 200. The insulating layer 210, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0333] The transistor 200 includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The conductive layer 220 and the conductive layer 240 are located at different heights.

[0334] In the transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode.

[0335] Regions of the oxide semiconductor layer 230 which are in contact with the conductive layer 220 and the conductive layer 240 preferably function as low-resistance regions.

[0336] 7B and 7C , an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220. A recess overlapping the opening 290 is provided in the conductive layer 220. The opening 290 and the recess in the conductive layer 220 form a continuous opening. The bottom of this continuous opening becomes the upper surface of the conductive layer 220.

[0337] The sidewalls of the opening 290 are the side surfaces of the insulating layer 280 and the conductive layer 240. The opening 290 includes an opening in the insulating layer 280 and an opening in the conductive layer 240. In other words, the opening in the region where the insulating layer 280 overlaps with the conductive layer 220 is a part of the opening 290, and the opening in the region where the conductive layer 240 overlaps with the conductive layer 220 is another part of the opening 290. Note that, among the openings 290, the opening 290 provided in the insulating layer 280 is referred to as opening 290a, and the opening 290 provided in the conductive layer 240 is referred to as opening 290b.

[0338] At least some of the components of the transistor 200 are disposed inside the opening 290. Specifically, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed such that at least some of them are located inside the opening 290. Within the opening 290, the oxide semiconductor layer 230 contacts the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the side surface of the conductive layer 240.

[0339] Furthermore, insulating layer 280 has insulating layer 280a, insulating layer 280b on insulating layer 280a, and insulating layer 280c on insulating layer 280b. Insulating layer 280a has a region in contact with the upper surface of insulating layer 210, a region in contact with the side surface of conductive layer 220, and a region in contact with the upper surface of conductive layer 220. Insulating layer 280c has a region in contact with the lower surface of conductive layer 240.

[0340] The oxide semiconductor layer 230 is provided inside an opening 290 in the insulating layer 280. The transistor 200 has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 in this case) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 in this case) is located above, and thus, a current flows vertically. That is, a channel is formed along the sidewall of the opening 290a.

[0341] The oxide semiconductor layer 230 contacts the upper surface of the conductive layer 220 and the side surface of the conductive layer 240 inside the opening 290. The oxide semiconductor layer 230 also contacts a part of the upper surface of the conductive layer 240. In this way, the oxide semiconductor layer 230 contacts not only the side surface but also the upper surface of the conductive layer 240, so that the contact area between the oxide semiconductor layer 230 and the conductive layer 240 can be made larger compared to, for example, a case where the oxide semiconductor layer 230 contacts the side surface of the conductive layer 240 but not the upper surface. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0342] The conductive layer 240 has an opening 290b in a region overlapping with the conductive layer 220. Furthermore, the conductive layer 240 is preferably not provided inside the opening 290a of the insulating layer 280. That is, the conductive layer 240 preferably does not have a region in contact with the side surface of the insulating layer 280 in the opening 290a. With this structure, the opening 290b of the conductive layer 240 and the opening 290a of the insulating layer 280 can be formed simultaneously. Furthermore, by configuring the side surface of the conductive layer 240 in the opening 290b to coincide or substantially coincide with the side surface of the insulating layer 280 in the opening 290a, the film thickness distribution of the oxide semiconductor layer 230 provided inside the opening 290 can be made uniform. Furthermore, the oxide semiconductor layer 230 can be prevented from being divided by a step between the conductive layer 240 and the insulating layer 280.

[0343] FIG. 9A is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 7A and is a modification of FIG. 7B. FIG. 9B is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 7A and is a modification of FIG. 7C. The conductive layer 240 shown in FIGS. 9A and 9B has a stacked structure of a conductive layer 240a and a conductive layer 240b over the conductive layer 240a. Note that the conductive layer 240 may be a single layer or may have a stacked structure of three or more layers. The details of the conductive layer 240a and the conductive layer 240b will be described later. Note that although the insulating layer 283 and the insulating layer 285 may be omitted in FIGS. 9A and 9B and subsequent drawings, the insulating layer 283 and the insulating layer 285 are preferably provided over the transistor 200.

[0344] 9A and 9B has a stacked structure of a conductive layer 260a and a conductive layer 260b on the conductive layer 260a. The conductive layer 260a is preferably formed using a film formation method that provides high coverage. Furthermore, by reducing the thickness of the conductive layer 260a, coverage of the sidewall of the opening 290 can be further improved. The conductive layer 260b can be thicker than the conductive layer 260a. By increasing the thickness of the conductive layer, the resistance of the conductive layer can be reduced. Note that the conductive layer 240 may be a single layer or may have a stacked structure of three or more layers. Details of the conductive layer 260a and the conductive layer 260b will be described later.

[0345] The width of the opening 290 is defined as width D. Width D may vary in the depth direction. For example, width D may be the width at the top end of the opening 290 in the insulating layer 280. Alternatively, width D may be the width at the bottom end. Alternatively, width D may be the width at half the depth of the opening 290 in the insulating layer 280. Alternatively, width D may be the width of the opening 290 in the conductive layer 240.

[0346] The portions of the oxide semiconductor layer 230 and the insulating layer 250 that are located inside the opening 290 are provided to reflect the shape of the opening 290. Specifically, the oxide semiconductor layer 230 is provided so as to cover the bottom and sidewall of the opening 290, and the insulating layer 250 is provided so as to cover the oxide semiconductor layer 230. The oxide semiconductor layer 230 is preferably provided so as to be in contact with the sidewall of the insulating layer 280 in the opening 290a. Furthermore, the insulating layer 250 is arranged so as to face the sidewall of the insulating layer 280 in the opening 290a, with the oxide semiconductor layer 230 sandwiched therebetween.

[0347] The conductive layer 260 is provided so as to fill a recess in the insulating layer 250 that reflects the shape of the opening 290. While miniaturization of the transistor 200 is possible by reducing the width D, when the width D is reduced and the aspect ratio of the opening 290 is high, only some layers of the stacked structure of the conductive layer 260 may be disposed inside the opening 290 depending on the formation method or thickness of the components disposed inside the opening. Here, an example is shown in which the conductive layer 260a is disposed inside the opening 290 and the conductive layer 260b is not disposed within the opening 290. The conductive layer 260a is preferably formed using a method with high coverage.

[0348] The angle of the sidewall of the opening 290 with respect to the top surface of the conductive layer 220 is preferably perpendicular or nearly perpendicular. By forming the opening 290 in such a shape, the area occupied by the transistor 200 can be reduced. Therefore, the semiconductor device can be miniaturized.

[0349] The film provided inside the opening 290 can be formed using an atomic layer deposition (ALD) method, a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, or the like.

[0350] 10B illustrates an example in which the sidewall of the opening 290 has a tapered shape, as compared with FIG. 7B. The angle θ280 formed between the top surface of the conductive layer 220 (or the top surface of the insulating layer 210) and the sidewall of the insulating layer 280 of the opening 290 is preferably 90 degrees or an angle close to 90 degrees. For example, the angle θ280 is preferably 75 degrees or more and 90 degrees or less.

[0351] The angle θ 280 may be less than 75 degrees, less than 70 degrees, less than 65 degrees, or less than 60 degrees. When the sidewall of the opening 290 is tapered, the oxide semiconductor layer 230 and the insulating layer 250 can be formed with good coverage.

[0352] In particular, when the sidewall of the opening 290 has a tapered shape, it is possible to improve the coverage of the sidewall of the opening 290. Therefore, as in the configuration shown in Fig. 10C, not only the thin conductive layer 260a but also the thick conductive layer 260b may be provided in the opening 290.

[0353] The opening 290 may have a tapered shape only at its upper end. In such a case, for example, at least a portion of the sidewall of the tapered region may be covered with the conductive layer 260b. Preferably, the opening 290 has a region deeper than the tapered region, where the sidewall is steeper than the upper end. For example, when the opening 290 has such a shape, the contact area with the conductive layer 240 increases in the tapered region, thereby reducing the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240. Furthermore, when part of the insulating layer 280 has a tapered shape, the region may function as a region for alleviating the electric field between the conductive layer 240 and the conductive layer 260.

[0354] The insulating layer 250 preferably has a configuration that provides good coverage of the sidewall of the opening 290 and can prevent short circuits between the conductive layer 240 and the conductive layer 260 .

[0355] The insulating layer 250 functions as a gate insulating layer of the transistor 200. By thinning the gate insulating layer, it is possible to reduce the gate potential applied during operation of the transistor 200. Furthermore, it is possible to operate the transistor 200 at high speed.

[0356] 7B and 7C show an example in which the edge of the oxide semiconductor layer 230 and the edge of the conductive layer 240 coincide with each other outside the opening 290. However, the present invention is not limited to this. For example, the semiconductor device shown in FIGS. 11A and 11B differs from FIGS. 7A and 7B in that the edge of the oxide semiconductor layer 230 is located outside the edge of the conductive layer 240. By positioning the edge of the oxide semiconductor layer 230 outside the edge of the conductive layer 240 and covering the edge of the conductive layer 240 with the oxide semiconductor layer 230, it may be possible to further increase the breakdown voltage between the conductive layer 240 and the conductive layer 260 and further reduce the leakage current of the insulating layer 250 located between the conductive layer 240 and the conductive layer 260. Furthermore, as shown in FIGS. 12A and 12B, the edge of the oxide semiconductor layer 230 may be located inside the edge of the conductive layer 240.

[0357] <OS Transistor> The transistor 200 includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. That is, the transistor 200 can be said to be an OS transistor.

[0358] The oxide semiconductor layer 230 described in the above embodiment can be used as the oxide semiconductor layer 230. The oxide semiconductor layer 230 described in the above embodiment can be formed by stacking an oxide semiconductor layer 230a, an oxide semiconductor layer 230b, and an oxide semiconductor layer 230c. FIG. 8 illustrates an enlarged view of a part of the cross-sectional view illustrated in FIG. 7B , showing the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the oxide semiconductor layer 230c. Note that in other drawings, the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the oxide semiconductor layer 230c may be omitted for clarity. The oxide semiconductor layer 230a is in contact with the top surface of the conductive layer 220, the side surfaces of the recesses of the conductive layer 220, the side surfaces of the openings 290a of the insulating layer 280, the side surfaces of the openings 290b of the conductive layer 240, and the top surface of the conductive layer 240. The oxide semiconductor layer 230b is provided over the oxide semiconductor layer 230a. The oxide semiconductor layer 230c, with the oxide semiconductor layer 230b sandwiched therebetween, covers the top surface of the conductive layer 220, the side surfaces of the recesses of the conductive layer 220, the side surfaces of the openings 290a of the insulating layer 280, the side surfaces of the openings 290b of the conductive layer 240, and the top surface of the conductive layer 240. The insulating layer 250 is provided in contact with the oxide semiconductor layer 230c. The conductive layer 260 covers the oxide semiconductor layer 230c with the insulating layer 250 sandwiched therebetween.

[0359] The oxide semiconductor layer 230 is provided in contact with a side surface of the opening 290a of the insulating layer 280. The angle between the side surface of the insulating layer 280 and the top surface of the conductive layer 220 (or the top surface of the insulating layer 210) is an angle θ280. Therefore, for example, the direction of the c-axis of the CAAC structure of the oxide semiconductor layer 230 is approximately perpendicular to the angle θ280.

[0360] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate, and reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy may become a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V ＯH) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0361] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance compared to a channel formation region, and the source and drain regions of the OS transistor preferably have a high carrier concentration and low resistance due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0362] A region of the oxide semiconductor layer 230 in contact with the insulating layer 280 and its vicinity function as a channel formation region of the transistor 200. One of a region of the oxide semiconductor layer 230 in contact with the conductive layer 220 and a region of the oxide semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0363] When the oxide semiconductor layer 230 and the conductive layer 220 come into contact with each other, a metal compound or oxygen vacancy is formed, and the region of the oxide semiconductor layer 230 in contact with the conductive layer 220 is reduced in resistance. This reduces the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220. Similarly, when the oxide semiconductor layer 230 and the conductive layer 240 come into contact with each other, the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 is reduced in resistance. This reduces the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240.

[0364] 10A , the insulating layer 280 is in contact with the entire outer periphery of the oxide semiconductor layer 230. Therefore, the channel formation region of the transistor 200 can be formed over the entire outer periphery of the oxide semiconductor layer 230 in the opening 290 (the entire region in contact with the insulating layer 280). Note that FIG. 10A can also be considered a cross-sectional view in the XY plane including the channel formation region of the oxide semiconductor layer 230.

[0365] The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulating layer 280 on the conductive layer 220. In FIG. 7C , the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the edge of the region where the oxide semiconductor layer 230 and the conductive layer 220 contact each other and the edge of the region where the oxide semiconductor layer 230 and the conductive layer 240 contact each other. In other words, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view. In some cases, the channel length L can be expressed as, for example, corresponding to the film thickness of the insulating layer 280 sandwiched between the conductive layer 220 and the conductive layer 240.

[0366] In a planar transistor, the channel length is limited by the exposure limit of lithography. However, in the transistor included in the semiconductor device of one embodiment of the present invention, the channel length can be set by the thickness of the insulating layer 280. Therefore, the channel length of the transistor 200 can be made into an extremely fine structure that is equal to or less than the exposure limit of lithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). As a result, the on-state current of the transistor 200 can be increased, and frequency characteristics can be improved.

[0367] Furthermore, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is determined by the thickness of the insulating layer 280 over the conductive layer 220. Therefore, even when the channel length is set to 60 nm or more, the area occupied by the transistor, specifically, the area of ​​the transistor as viewed from above, is roughly determined by the width of the opening 290. As described later, the width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. For example, even when the channel length is set to 150 nm, the width of the opening 290 can be set to be narrower than 150 nm. That is, the width of the opening can be narrower than the channel length of the transistor, thereby reducing the area occupied by the transistor and enabling high integration of the semiconductor device. Therefore, for example, the channel length of the transistor 200 may be greater than the width D of the opening 290.

[0368] Note that by setting the channel length of the transistor to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, and the like.

[0369] Therefore, the channel length of a transistor included in a semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0370] As described above, the channel length of the transistor 200 can be longer than the width D of the opening 290. Increasing the channel length of the transistor 200 may improve the operating characteristics, reliability, and the like of the transistor 200. For example, the subthreshold swing (also referred to as the S value) of the transistor 200 may be reduced. Alternatively, for example, the source-drain breakdown voltage of the transistor 200 may be increased. Therefore, for example, the channel length of the transistor is preferably greater than the width D and is 1 μm or less, 500 nm or less, or 300 nm or less. Here, the width D is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Therefore, for example, the film thickness of the insulating layer 280 in a region sandwiched between the conductive layer 220 and the conductive layer 240 is greater than the width D and is 1 μm or less, 500 nm or less, or 300 nm or less.

[0371] The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is kept constant in the subthreshold region.

[0372] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.

[0373] 10A , the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 located at the center faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, the entire periphery of the oxide semiconductor layer 230 forms a channel formation region in a plan view. In this case, for example, the channel width of the transistor 200 is determined by the periphery length of the oxide semiconductor layer 230. That is, the channel width of the transistor 200 can be determined by the width of the opening 290 (or the diameter when the opening 290 is circular in a plan view). In FIGS. 7C and 10A , the width D of the opening 290 is indicated by a double-headed, dashed arrow. In FIG. 10A , the channel width W of the transistor 200 is indicated by a double-headed, dashed arrow. Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current.

[0374] When the opening 290 is formed using lithography, the width D of the opening 290 is limited by the exposure limit of lithography. The width D of the opening 290 is set depending on the film thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0375] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0376] Furthermore, by forming the opening 290 so as to have a circular shape in a plan view, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the oxide semiconductor layer 230 approximately uniform, allowing a gate electric field to be applied to the oxide semiconductor layer 230 approximately uniformly.

[0377] In this embodiment, the opening 290 has a circular shape in plan view, but the present invention is not limited to this. For example, the opening 290 may have a substantially circular shape such as an oval, a polygonal shape such as a square, or a polygonal shape such as a square with rounded corners in plan view.

[0378] 13A shows an enlarged view of a portion of the cross section shown in FIG. 7B. As shown in FIG. 13A, a recess that overlaps with the opening 290 is formed in the conductive layer 220, and at least a part of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 is formed so as to fill the recess. With this structure, it is possible to easily apply the gate electric field of the conductive layer 260 up to the vicinity of the conductive layer 220 in the oxide semiconductor layer 230. The recess in the conductive layer 220 is formed, for example, by over-etching when the opening 290 is formed.

[0379] 13A, the opening 290 and the recess of the conductive layer 220 form a continuous opening. In this case, for example, the bottom of the continuous opening becomes the upper surface of the conductive layer 220.

[0380] 13B shows an example in which the conductive layer 220 has a three-layer stacked structure of a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, and a conductive layer 220c on the conductive layer 220b. The bottom surface of the recess in the conductive layer 220 corresponds to the top surface of the conductive layer 220b, and the side surface of the recess corresponds to the side surface of the conductive layer 220c on the opening 290 side. Here, the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220c that contacts the insulating layer 280 is preferably longer than the shortest distance Ta from the top surface of the insulating layer 210 to the top surface of the insulating layer 250. This can reduce the contact resistance between the side surface of the conductive layer 220c and the oxide semiconductor layer 230. This can suppress a decrease in the on-state current of the transistor 200.

[0381] 13C is a modification of FIG. 13B. In FIG. 13C, the bottom surface of the recess of the conductive layer 220 is located higher than the top surface of the conductive layer 220b. As shown in FIG. 13C, the oxide semiconductor layer 230 does not necessarily have to be in contact with the conductive layer 220a or the conductive layer 220b.

[0382] Note that there may be cases where the conductive layer 220 does not have a recess.

[0383] When the conductive layer 220 is in contact with the side surface of the oxide semiconductor layer 230, the contact area between the conductive layer 220 and the oxide semiconductor layer 230 can be increased, and the contact resistance can be reduced.

[0384] Furthermore, since the conductive layer 220 and the conductive layer 260 have a region where they overlap with each other, a gate electric field can be easily applied to a channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor. Furthermore, since a gate electric field can be easily applied to a region of the oxide semiconductor layer 230 that is in contact with the conductive layer 220, for example, the on-state current of the transistor can be increased.

[0385] 14A to 14C include an insulating layer 283 and an insulating layer 285 provided over an insulating layer 250, an opening 270 in which a conductive layer 260 is provided. FIG. 14A is a plan view of a semiconductor device including a transistor 200. FIG. 14B is a cross-sectional view taken along dashed line A1-A2 in FIG. 14A. FIG. 14C is a cross-sectional view taken along dashed line A3-A4 in FIG. 14A.

[0386] 14B and 14C , the opening 270 overlaps with the opening 290 in a plan view. The conductive layer 260 has a region located within the opening 270 provided in the insulating layer 285 and a region in contact with the top surface of the insulating layer 285. The insulating layer 283 has a region overlapping with the top surface of the conductive layer 240 with the insulating layer 250 and the oxide semiconductor layer 230 sandwiched therebetween, and a region sandwiched between the side surface of the opening 270 and the side surface of the conductive layer 260. The conductive layer 240 and the conductive layer 260 overlap with each other with the insulating layer 285 sandwiched therebetween.

[0387] In the semiconductor device shown in Figures 14B and 14C, insulating layers 283 and 285 are provided between the conductive layer 240 and the conductive layer 260, and therefore, by making the insulating layer 285 thicker, the parasitic capacitance between the conductive layer 240 and the conductive layer 260 can be reduced.

[0388] 15A to 15C include an insulating layer 283 and an insulating layer 285 on an insulating layer 250. The insulating layer 285 includes an opening 270, and a conductive layer 260a is provided in the opening 270. FIG. 15A is a plan view of a semiconductor device including a transistor 200. FIG. 15B is a cross-sectional view taken along dashed line A1-A2 in FIG. 15A. FIG. 15C is a cross-sectional view taken along dashed line A3-A4 in FIG. 15A.

[0389] 15B and 15C , the opening 270 overlaps with the opening 290 in a plan view. The conductive layer 260a has a region located within the opening 270 provided in the insulating layer 285. The insulating layer 283 has a region overlapping with the top surface of the conductive layer 240 with the oxide semiconductor layer 230 sandwiched therebetween, and a region sandwiched between the side surfaces of the opening 270 and the conductive layer 260a. The height of the top surface of the conductive layer 260a and the height of the top surface of the insulating layer 285 are preferably the same or approximately the same. The conductive layer 260b is provided over the conductive layer 260a, the insulating layer 285, and the insulating layer 283. The conductive layer 240 and the conductive layer 260b overlap with each other with the insulating layer 285 sandwiched therebetween. The conductive layer 260a is not provided in a region outside the opening 270 in a plan view.

[0390] 15B and 15C , insulating layers 283 and 285 are provided between conductive layer 240 and conductive layer 260b, and therefore, by making insulating layer 285 thicker, the parasitic capacitance between conductive layer 240 and conductive layer 260b can be reduced. Furthermore, conductive layer 260a is not provided in a region outside opening 270 in plan view, and therefore the area overlapping with conductive layer 240 is small. Therefore, the parasitic capacitance between conductive layer 260a and conductive layer 240 can be reduced.

[0391] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0392] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0393] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride.

[0394] Specifically, it is preferable to use a barrier insulating layer against impurities such as water and hydrogen, and oxygen.

[0395] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse, a property that makes it difficult for a corresponding substance to permeate, a property that makes it low permeable to a corresponding substance, a function to suppress the diffusion of a corresponding substance, or a function to suppress the permeation of a corresponding substance. Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0396] Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Other examples include oxides containing aluminum and hafnium (hafnium aluminate). Other examples include metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0397] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers that are likely to have a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0398] Furthermore, for example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer enables lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. Furthermore, using a material with a high dielectric constant as the dielectric layer of a capacitive element can result in an element with a larger capacitance value. On the other hand, using a material with a low dielectric constant for the insulating layer functioning as an interlayer film can reduce the parasitic capacitance generated between wirings. Therefore, it is advisable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0399] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0400] Examples of materials with a low dielectric constant include resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0401] Furthermore, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide can be applied to both layers in which a material with a high dielectric constant is preferably used, such as a gate insulating layer, and layers in which a material with a low dielectric constant is preferably used, such as an interlayer film. These materials have a relatively low dielectric constant compared to high-k materials such as hafnium oxide, and therefore may be referred to as "materials with a low dielectric constant" in this specification and the like.

[0402] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of the semiconductor device. Examples of the material capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ(X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. Ferroelectric materials include hafnium ... (here, element J2 can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close to 1:1. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0403] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0404] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0405] Although metal oxides and metal nitrides have been described above as examples of materials that can have ferroelectricity, the materials are not limited to these. For example, metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, may also be used.

[0406] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulating layer can have a laminated structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are referred to as ferroelectrics, but also as materials capable of exhibiting ferroelectricity.

[0407] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0408] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer. Also, in this specification, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device.

[0409] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals with an orthorhombic crystal structure is preferred because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystals. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0410] The insulating layer 250 functions as a gate insulating layer of the transistor 200. For the insulating layer 250, a material with a high dielectric constant is preferably used.

[0411] The insulating layer 250 preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor). Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0412] Examples of materials for insulating layers capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing magnesium. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with amorphous structures have dangling bonds in some oxygen atoms, which enhance their ability to capture or adsorb hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0413] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0414] When the insulating layer 250 has a stacked structure, it is preferable to use a layer having a function of capturing and fixing hydrogen as one of the layers (hereinafter referred to as a first insulating layer of the insulating layer 250). Furthermore, by using a layer having a function of capturing and fixing hydrogen as a layer in contact with the oxide semiconductor layer 230 when the insulating layer 250 has a stacked structure of two layers, or as a layer close to the oxide semiconductor layer 230 when the insulating layer 250 has a stacked structure of three or more layers, hydrogen contained in the oxide semiconductor layer 230 can be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0415] Furthermore, in addition to the first insulating layer, a barrier insulating layer against hydrogen is preferably used as the second insulating layer for the insulating layer 250. Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0416] The insulating layer 250 may be made of, for example, hafnium silicate as the first insulating layer. The insulating layer 250 preferably has an amorphous structure. The amorphous structure can suppress the formation of grain boundaries. Suppressing the formation of grain boundaries can improve the flatness of the insulating layer. This makes the film thickness distribution of the insulating layer uniform, reducing areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. Furthermore, the film thickness distribution of the film provided on the insulating layer can be made uniform.

[0417] Furthermore, by suppressing the formation of grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels in the grain boundaries, and thus the insulating layer can function as an insulating film with low leakage current.

[0418] Furthermore, since hafnium oxide is a material with a high dielectric constant, hafnium silicate can also be a material with a high dielectric constant depending on the silicon content. Therefore, when used as a gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0419] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the first insulating layer of the insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0420] Furthermore, by using a barrier insulating layer against hydrogen as the second insulating layer of the insulating layer 250, it is possible to suppress diffusion of impurities contained in the conductive layer 260 into the oxide semiconductor layer 230. Silicon nitride has a high barrier property against hydrogen and is therefore suitable for the insulating layer 250. Here, the second insulating layer is preferably an upper layer of the first insulating layer.

[0421] With such a structure, a semiconductor device having good electrical characteristics, high reliability, little variation in the electrical characteristics of the transistors, and a large on-state current can be provided.

[0422] Additionally, insulating layer 250 may comprise an insulating layer of a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0423] The insulating layer 250 preferably includes a layer capable of supplying oxygen to the oxide semiconductor layer 230. An oxide can be used as the layer capable of supplying oxygen. When the insulating layer 250 includes silicon oxide or silicon oxynitride, oxygen can be suitably supplied from the insulating layer 250 to the oxide semiconductor layer 230.

[0424] Furthermore, the insulating layer 250 may have an insulating layer having a thermally stable structure between a pair of insulating layers having the functions of capturing and fixing hydrogen.

[0425] The insulating layer 250 preferably has a barrier insulating layer against oxygen, which can suppress oxidation of the conductive layer 240, the conductive layer 260, and the like. When the insulating layer 250 has a stacked structure, it is preferable that the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 260 each be a barrier insulating layer against oxygen.

[0426] The layer of the insulating layer 250 that is in contact with the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280. The layer has a barrier property against oxygen, which can prevent the side surfaces of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0427] For example, by using a barrier insulating layer against hydrogen and oxygen as the second insulating layer, it is possible to suppress oxidation of the conductive layer 260. Furthermore, it is possible to suppress the oxygen contained in the oxide semiconductor layer 230 from diffusing into the conductive layer 260 and the formation of oxygen vacancies in the oxide semiconductor layer 230.

[0428] Examples of the barrier insulating layer against oxygen include oxides containing hafnium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0429] Hafnium and silicon oxides (hafnium silicates) function as a barrier insulating layer against oxygen, and as mentioned above, they are also excellent insulating layers that can easily achieve an amorphous structure and have the ability to capture or fix hydrogen.

[0430] Furthermore, silicon nitride is an excellent insulating layer that not only functions as a barrier insulating layer against oxygen but also has high barrier properties against hydrogen, as described above.

[0431] The insulating layer 250 preferably has a two-layer structure in which a first insulating layer having a function of capturing or fixing hydrogen and a second insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the oxide semiconductor layer 230 side.

[0432] For example, the first insulating layer can be made of an oxide containing one or both of aluminum and hafnium, and the second insulating layer can be made of silicon nitride.

[0433] The insulating layer 250 preferably has a three-layer structure in which, from the oxide semiconductor layer 230 side, a third insulating layer made of a material with a relatively low dielectric constant, a first insulating layer having a function of capturing or fixing hydrogen, and a second insulating layer having barrier properties against hydrogen and oxygen are stacked in this order. The material of the third insulating layer with a relatively low dielectric constant refers to, for example, a material with a lower dielectric constant than any one or more of the other layers in the stacked structure. Here, silicon oxide or silicon oxynitride can be used as the third insulating layer. The third insulating layer is a layer in contact with the oxide semiconductor layer 230. Using an oxide for the third insulating layer can supply oxygen to the oxide semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.

[0434] As an example, silicon oxide or silicon oxynitride can be used as the third insulating layer, an oxide containing one or both of aluminum and hafnium can be used as the first insulating layer, and silicon nitride can be used as the second insulating layer.

[0435] The insulating layer 250 preferably has a four-layer structure in which, from the oxide semiconductor layer 230 side, a fourth insulating layer having a barrier property against oxygen, a third insulating layer made of a material with a relatively low dielectric constant, a first insulating layer having a function of capturing or fixing hydrogen, and a second insulating layer having a barrier property against hydrogen and oxygen are stacked in this order. The first to third insulating layers can have the same structure as the layers used in the above-described three-layer structure. The fourth insulating layer is in contact with the oxide semiconductor layer 230. The fourth insulating layer has a barrier property against oxygen, which can prevent oxygen from being released from the oxide semiconductor layer 230. For example, aluminum oxide may be used as the fourth insulating layer. Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230.

[0436] As an example, aluminum oxide can be used as the fourth insulating layer, silicon oxide or silicon oxynitride can be used as the third insulating layer, an oxide containing one or both of aluminum and hafnium can be used as the first insulating layer, and silicon nitride can be used as the second insulating layer.

[0437] In particular, the thickness of the insulating layer 250 in a region overlapping with the channel formation region of the oxide semiconductor layer 230 is preferably 0.1 nm to 30 nm, more preferably 0.1 nm to 20 nm, still more preferably 0.1 nm to 10 nm, still more preferably 0.1 nm to 8.0 nm, and still more preferably 0.5 nm to 7.0 nm.

[0438] In order to miniaturize transistors, it is preferable that the thickness of each layer constituting the insulating layer 250 is thin. For example, the thickness of each layer constituting the insulating layer 250 is 0.1 nm to 10 nm, or 0.1 nm to 5 nm, or 0.5 nm to 5 nm, or 1 nm to less than 5 nm, or 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0439] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0440] Since the insulating layer 210 functions as an interlayer film, it is preferable that the insulating layer 210 has a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 210.

[0441] The concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0442] A barrier insulating layer against hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 provided on the outer side of the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed.

[0443] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0444] For example, it is preferable to use a silicon nitride film as the insulating layer 210 .

[0445] The insulating layer 210 may have a two-layer stacked structure. For example, an insulating layer having a function of capturing or fixing hydrogen can be used as an upper layer of the insulating layer 210. In this way, hydrogen in the oxide semiconductor layer 230 can be diffused to the upper layer of the insulating layer 210 through the conductive layer 220 and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0446] For example, it is preferable to use a silicon nitride film as the lower layer of the insulating layer 210 and an oxide film containing hafnium and silicon (hafnium silicate film) as the upper layer.

[0447] A barrier insulating layer against hydrogen is preferably used for one or more of the insulating layers 283 and 285. This can suppress diffusion of hydrogen from above the insulating layer 283 to the oxide semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 283.

[0448] It is particularly preferable to use silicon nitride deposited by a sputtering method as one or more of the insulating layers 283 and 285. The sputtering method does not require the use of molecules containing hydrogen in the deposition gas, and therefore can reduce the hydrogen concentration in the insulating layer 283. Furthermore, by depositing the insulating layer 283 by a sputtering method, silicon nitride with high density can be formed.

[0449] Alternatively, an insulating layer having a function of capturing or fixing hydrogen may be used as one or more of the insulating layers 283 and 285. With such a structure, diffusion of hydrogen from above the insulating layers 283 and 285 to the oxide semiconductor layer 230 can be suppressed, and further, hydrogen contained in the oxide semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. Hafnium silicate or the like can be used as one or more of the insulating layers 283 and 285.

[0450] Alternatively, the insulating layer 283 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 283 may be a stacked film of aluminum oxide and silicon nitride over the aluminum oxide.

[0451] In addition, the semiconductor device may have a structure in which either the insulating layer 283 or the insulating layer 285 is not provided.

[0452] Furthermore, for example, a material with a low relative dielectric constant can be used as the insulating layer 285. By using a material with a low relative dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced.

[0453] The concentration of impurities such as water and hydrogen in the insulating layer 285 is preferably reduced. This can prevent impurities such as water and hydrogen from entering a channel formation region of the oxide semiconductor layer 230.

[0454] The insulating layer 280 preferably includes the aforementioned barrier insulating layer against hydrogen. The insulating layer 280 is provided so as to surround the oxide semiconductor layer 230. When the insulating layer 280 provided on the outer side of the oxide semiconductor layer 230 has a barrier property against hydrogen, it is possible to suppress diffusion of hydrogen into the oxide semiconductor layer 230. For example, the insulating layer 280 preferably includes a silicon nitride film.

[0455] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 280, oxygen can be prevented from being extracted from the oxide semiconductor layer 230, and excessive oxygen vacancies can be prevented from being formed in the oxide semiconductor layer 230.

[0456] Furthermore, the use of silicon nitride for the insulating layer 280 can prevent excess oxygen from being supplied to the oxide semiconductor layer 230. Thus, excess oxygen can be prevented from being contained in the channel formation region of the oxide semiconductor layer 230, thereby improving the reliability of the transistor 200.

[0457] The insulating layer 280 preferably includes the above-described insulating oxide insulating film, the oxynitride insulating film, or the insulating layer having a region containing excess oxygen.

[0458] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method in which hydrogen-containing molecules are not used in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least some of the layers constituting the insulating layer 280 in this manner, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0459] The concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0460] Note that the thickness of the insulating layer 280 on the conductive layer 220 corresponds to the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 is set appropriately in accordance with the design value of the channel length of the transistor 200 .

[0461] The insulating layer 280 preferably has a stacked structure of, for example, an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b.

[0462] The insulating layer 280b is a layer in contact with a channel formation region of the oxide semiconductor layer 230. When an insulating layer containing oxygen is used as the insulating layer 280b, oxygen can be supplied to the oxide semiconductor layer 230.

[0463] The insulating layer 280b preferably has a region with a higher oxygen content than at least one of the insulating layer 280a and the insulating layer 280c. In particular, the insulating layer 280b preferably has a region with a higher oxygen content than each of the insulating layer 280a and the insulating layer 280c. Increasing the oxygen content of the insulating layer 280b makes it easier to form an i-type region in the oxide semiconductor layer 230 near the insulating layer 280b.

[0464] It is more preferable to use a film that releases oxygen by heating for the insulating layer 280b. When the insulating layer 280b releases oxygen due to heat applied during the manufacturing process of the transistor 200, oxygen can be supplied to the oxide semiconductor layer 230. When oxygen is supplied from the insulating layer 280b to the oxide semiconductor layer 230, particularly to the channel formation region of the oxide semiconductor layer 230, oxygen vacancies and V in the oxide semiconductor layer 230 can be reduced. Ｏ H can be reduced, and a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0465] To improve the electrical characteristics and reliability of an OS transistor, it is important to sufficiently reduce the hydrogen concentration in the oxide semiconductor and then optimize the amount of oxygen supplied to the oxide semiconductor.

[0466] As an example, the amount of oxygen molecules released from the insulating layer 280b is 1.0×10 １４ molecules / cm ２ That's it, 1.0 x 10 １５ molecules / cm ２ The amount of released oxygen molecules can be measured by thermal desorption spectroscopy.

[0467] In particular, when the channel length of the transistor 200 is small, oxygen vacancies in the channel formation region and V Ｏ The influence of H on the electrical characteristics and reliability is particularly large. Therefore, by sufficiently reducing the hydrogen concentration in the oxide semiconductor layer 230 and then optimizing the amount of oxygen supplied to the oxide semiconductor layer 230, a transistor with a short channel length, favorable electrical characteristics, and high reliability can be realized.

[0468] The insulating layer 280b is preferably formed by a deposition method such as a sputtering method or a PECVD method. In particular, when a sputtering method is used, hydrogen gas is not used as a deposition gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, supply of hydrogen to the oxide semiconductor layer 230 can be suppressed, and the electrical characteristics of the transistor 200 can be stabilized.

[0469] To increase the amount of oxygen supplied to the oxide semiconductor layer 230, for example, heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere may be performed after the insulating layer 280b is formed. Alternatively, oxygen may be supplied by forming an oxide film on the top surface of the insulating layer 280b by a sputtering method in an oxygen atmosphere. The oxide film may then be removed. By performing such treatment, oxygen can be supplied to the insulating layer 280b, and the amount of oxygen supplied to the oxide semiconductor layer 230 can be increased.

[0470] Furthermore, the region of the oxide semiconductor layer 230 in contact with the insulating layer 280a and the region of the oxide semiconductor layer 230 in contact with the insulating layer 280c receives a smaller amount of oxygen than the region of the oxide semiconductor layer 230 in contact with the insulating layer 280b. Therefore, the region of the oxide semiconductor layer 230 in contact with the insulating layer 280a and the region of the oxide semiconductor layer 230 in contact with the insulating layer 280c may have a lower resistance. In other words, by adjusting the thickness of the insulating layer 280a, the range of the region that functions as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulating layer 280c, the range of the region that functions as the other of the source region and the drain region can be controlled. In this way, the thicknesses of the insulating layers 280a and 280c can be appropriately set according to the characteristics desired for the transistor.

[0471] Furthermore, it is preferable to use a material with a low relative dielectric constant for the insulating layer 280b, which can reduce the parasitic capacitance that occurs between wirings. For example, silicon oxide or silicon oxynitride can be used for the insulating layer 280b.

[0472] It is preferable that the insulating layer 280a and the insulating layer 280c each be a barrier insulating layer against oxygen. By providing the insulating layer 280a between the insulating layer 280b and the conductive layer 220, it is possible to prevent the conductive layer 220 from being oxidized and the resistance of the conductive layer 220 from increasing. Furthermore, by providing the insulating layer 280c between the insulating layer 280b and the conductive layer 240, it is possible to prevent the conductive layer 240 from being oxidized and the resistance of the conductive layer 240 from increasing.

[0473] Alternatively, the insulating layer 280a may be an insulating layer having a function of capturing or fixing hydrogen. Such a structure can suppress diffusion of hydrogen from below the insulating layer 280a into the oxide semiconductor layer 230 and further allow hydrogen contained in the oxide semiconductor layer 230 to be captured or fixed. This reduces the hydrogen concentration in the oxide semiconductor layer 230. The insulating layer 280a may be made of magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon. Alternatively, the insulating layer 280a may be made of, for example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide. Similarly, the insulating layer 280c may be made of an insulating layer having a function of capturing or fixing hydrogen.

[0474] For example, the insulating layers 280a and 280c can be formed using silicon nitride, and the insulating layer 280b can be formed using silicon oxide.

[0475] [Conductive Layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, etc.) of the semiconductor device preferably contain a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, ruthenium nitride, nitride containing molybdenum, nitride containing tungsten, titanium, and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0476] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO®), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0477] Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.

[0478] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0479] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0480] The conductive layer 260 can be made of the above-mentioned metal elements, alloys containing the above-mentioned metal elements, or alloys combining the above-mentioned metal elements. For example, it is preferable to use a highly conductive material such as tungsten. Furthermore, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 260. As described above, examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 260.

[0481] The conductive layer 260 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used. Nitrogen-containing indium gallium zinc oxide may also be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0482] The conductive layer 260 may have a thickness of, for example, 3 nm or more and 500 nm or less. The thickness of the conductive layer 260 may be, for example, equal to or greater than the thickness of the insulating layer 250. By making the conductive layer 260 thicker, the resistance of the conductive layer 260 can be reduced.

[0483] Furthermore, it is preferable that the conductive layer 260 has a two-layer structure including a conductive layer 260a and a conductive layer 260b on the conductive layer 260a.

[0484] By using a conductive material having a function of suppressing oxygen diffusion as the conductive layer 260a, for example, release of oxygen from the oxide semiconductor layer 230 can be suppressed, and formation of oxygen vacancies in the oxide semiconductor layer 230 can be suppressed.

[0485] Furthermore, by using a conductive material that is resistant to oxidation as the conductive layer 260a, it is possible to prevent the conductive layer 260a from being oxidized and its conductivity from being reduced due to, for example, the release of oxygen from the oxide semiconductor layer 230 or the release of oxygen from the insulating layer 250.

[0486] The material used for the conductive layer 260b preferably has higher conductivity than the material used for the conductive layer 260a, for example. In addition, by making the conductive layer 260b thicker, the current flowing through the conductive layer 260b can be further increased.

[0487] By using a film formation method with high coverage for the conductive layer 260 a, the conductive layer 260 a can be suitably formed along the sidewall of the opening 290 .

[0488] The conductive layer 260a can be, for example, a conductive material containing nitrogen, a conductive material containing oxygen, etc. Alternatively, the conductive layer 260a can be, for example, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed.

[0489] For example, a conductive material containing the above-mentioned metal element and nitrogen can be used as the conductive layer 260a, such as tantalum nitride, titanium nitride, ruthenium nitride, nitrides containing molybdenum, nitrides containing tungsten, titanium, and aluminum, nitrides containing tantalum and aluminum, etc.

[0490] Furthermore, the conductive layer 260a can be made of a conductive material containing the aforementioned metal element and oxygen, such as ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel.

[0491] Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used.

[0492] Furthermore, as the conductive layer 260a, materials containing titanium, tantalum, ruthenium, and one or more selected from these metal elements are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen.

[0493] The conductive layer 260b may be made of, for example, the above-mentioned metal elements, alloys containing the above-mentioned metal elements, or alloys combining the above-mentioned metal elements. For example, tungsten may be used.

[0494] The conductive layer 260a may further have a stacked structure. The conductive layer 260b may further have a stacked structure. When the conductive layer 260a has a stacked structure, for example, a plurality of materials that can be used for the conductive layer 260a may be stacked. Alternatively, a plurality of materials selected from the materials that can be used for the conductive layer of one embodiment of the present invention may be stacked. When the conductive layer 260b has a stacked structure, for example, a plurality of materials that can be used for the conductive layer 260b may be stacked. Alternatively, a plurality of materials selected from the materials that can be used for the conductive layer of one embodiment of the present invention may be stacked.

[0495] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, an oxide conductive material, or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0496] By using a conductive material containing oxygen for the conductive layer 220 or the conductive layer 240, the conductive layer 220 or the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 210, the conductive layer 220 is preferable because it can maintain its conductivity. For example, ITO, ITSO, IZO (registered trademark), or the like is preferably used for each of the conductive layer 220 and the conductive layer 240.

[0497] When the conductive layer 220 has a three-layer structure of a first conductive layer (e.g., conductive layer 220a), a second conductive layer (e.g., conductive layer 220b), and a third conductive layer (e.g., conductive layer 220c) on the insulating layer 210 in this order, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the first conductive layer, a material with high conductivity as the second conductive layer, and a conductive material containing oxygen as the third conductive layer. Specifically, it is preferable to use titanium nitride as the first conductive layer, tungsten as the second conductive layer, and ITO or ITSO as the third conductive layer. In this case, titanium nitride is in contact with the insulating layer 210, and ITO or ITSO is in contact with the oxide semiconductor layer 230. With this structure, the conductive layer 220 can maintain conductivity even when in contact with the oxide semiconductor layer 230. When an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 can be suppressed by the insulating layer 210. When tungsten, which has high conductivity, is used for the second conductive layer, the conductivity of the conductive layer 220 can be increased.

[0498] Furthermore, when the conductive layer 240 has a two-layer stacked structure (e.g., conductive layer 240a and conductive layer 240b), it is preferable to use a material with higher conductivity for the lower layer than for the upper layer and a conductive material containing oxygen for the upper layer. Specifically, it is preferable to use ruthenium, tungsten, titanium nitride, or tantalum nitride for the lower layer and ITO, ITSO, zinc oxide, indium oxide, IZO (registered trademark), or the like for the upper layer. In this case, ITO or ITSO is in contact with the oxide semiconductor layer 230. With this structure, the conductive layer 240 can maintain conductivity even when in contact with the oxide semiconductor layer 230. Furthermore, by using a material with higher conductivity for the lower layer than for the upper layer, the conductivity of the conductive layer 240 can be increased.

[0499] In the case where the conductive layer 240 has a two-layer stacked structure, a highly conductive material may be used for the upper layer (e.g., the conductive layer 240b) and a conductive material containing oxygen may be used for the lower layer (e.g., the conductive layer 240a). In such a case, for example, the oxide semiconductor layer 230 may be in contact with the upper surface of the conductive layer 240a, thereby reducing the contact resistance between the conductive layer 240 and the oxide semiconductor layer 230.

[0500] [Oxide Semiconductor Layer 230] As the oxide semiconductor layer 230, the oxide semiconductor layer 230 described in the above embodiment can be used.

[0501] Hydrogen contained in the oxide semiconductor reacts with oxygen that bonds to metal atoms to form water, and oxygen vacancies (V Ｏ In addition, defects in which hydrogen enters oxygen vacancies (hereinafter referred to as V Ｏ Hydrogen atoms (H) may function as donors and generate electrons as carriers. Furthermore, some of the hydrogen atoms may bond with oxygen atoms that are bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics (i.e., a negative threshold voltage). Furthermore, hydrogen atoms in an oxide semiconductor are easily mobile due to stresses such as heat and an electric field. Therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced.

[0502] V in the oxide semiconductor layer 230 Ｏ It is preferable to reduce H as much as possible to make the oxide semiconductor layer 230 highly intrinsic or substantially highly intrinsic. Ｏ To obtain an oxide semiconductor in which H is sufficiently reduced, it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to repair oxygen vacancies. Ｏ Stable electrical characteristics can be obtained by using an oxide semiconductor in which impurities such as H are sufficiently reduced for a channel formation region of a transistor. Note that supplying oxygen to an oxide semiconductor to repair oxygen vacancies is sometimes referred to as oxygen-adding treatment.

[0503] The carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is 1×10 １８ cm −３ Preferably, it is 1×10 or less. １７ cm −３ More preferably, it is less than 1×10 １６ cm −３ More preferably, it is less than 1×10 １３ cm −３ More preferably, it is less than 1×10 １２ cm −３ The lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, but is preferably, for example, 1×10 −９ cm −３ It can be said that:

[0504] Here, the influence of each impurity in a metal oxide (oxide semiconductor) will be described.

[0505] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10 １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 3×10 １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0506] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than 1×10, more preferably 1×10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ Less than 1×10, more preferably 1×10 １８ atoms / cm３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0507] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Less than.

[0508] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0509] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0510] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region. Examples of such another semiconductor material include semiconductors made of simple elements or compound semiconductors. Examples of semiconductors made of simple elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that the aforementioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.

[0511] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0512] The semiconductor layer of a transistor may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0513] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0514] [Substrate] Substrates on which transistors are formed can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0515] <Example of Manufacturing Method of Semiconductor Device> A manufacturing method of a semiconductor device will be described with reference to Figures 16A to 16C. Here, as an example, a manufacturing method of the structure shown in Figures 7A to 7C will be described. Note that with regard to the materials and forming methods of each element, descriptions of parts that are the same as those described above may be omitted.

[0516] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed by a sputtering method, a CVD method, a vacuum evaporation method, a PLD method, an ALD method, or the like.

[0517] Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source; DC sputtering, which uses a direct current power source; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF-superimposed DC sputtering, which superimposes RF and DC, is also available. RF sputtering is preferred for film formation using insulating targets. DC sputtering is primarily used when forming films using conductive targets. DC sputtering can also form insulating films by reactive sputtering, in addition to forming conductive films. Pulsed DC sputtering is primarily used when depositing films of compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-superimposed DC sputtering allows for control of ion energy and target potential during film formation. Therefore, compared to RF sputtering, damage caused by film formation is reduced. Furthermore, high-quality films can be obtained.

[0518] Examples of sputtering methods that can be used include ionization sputtering and long-throw sputtering. Ionization sputtering is a method in which sputtering particles generated from a target are ionized by RF or the like, and anisotropic film formation is achieved by self-bias or the like. In addition, long-throw sputtering can form anisotropic films by increasing the distance between the sputtering target and the substrate.

[0519] CVD methods can be classified into PECVD, thermal CVD (TCVD) using heat, photo CVD (Photo CVD) using light, etc. They can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD) depending on the source gas used.

[0520] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0521] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD (Plasma Enhanced ALD) method in which a plasma-excited reactant is used, or the like can be used.

[0522] Furthermore, the ALD method can deposit atoms layer by layer, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. The PEALD (Plasma Enhanced ALD) method may be preferable because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. The amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. However, since the ALD method employs a high substrate temperature during film formation and / or an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0523] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as sputtering or CVD, which have a faster film formation rate. For example, when a metal oxide has a layered structure of a first metal oxide and a second metal oxide, a method can be used in which the first metal oxide is formed by sputtering and the second metal oxide is formed on the first metal oxide by ALD. For example, if the first metal oxide has crystalline portions, the second metal oxide may grow as crystals using the crystalline portions as nuclei.

[0524] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film whose composition changes continuously by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0525] Furthermore, in the ALD method, a film of any composition can be formed by adjusting the amount of source gas introduced, the number of introductions (also referred to as the number of pulses), the time required for one pulse (also referred to as the pulse time), etc. Also, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor.

[0526] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0527] Furthermore, when processing a thin film that constitutes a semiconductor device, a lithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0528] There are two typical lithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0529] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0530] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0531] First, the conductive layer 220 is formed over the insulating layer 210, the insulating layer 280 is formed over the conductive layer 220, and the conductive layer 240 is formed over the insulating layer 280. Note that here, the insulating layer 280 has a three-layer structure of an insulating layer 280a, an insulating layer 280b, and an insulating layer 280c.

[0532] Note that after the insulating layer 280 is formed, it is preferable to perform planarization treatment (also referred to as CMP treatment) using a chemical mechanical polishing (CMP) method to planarize the top surface of the insulating layer 280. By performing the planarization treatment on the insulating layer 280, the surface on which the conductive layer 240, which functions as a wiring, is formed can be flattened, and discontinuity of the conductive layer 240 can be suppressed. Note that the planarization treatment is not necessarily performed, and in that case, manufacturing costs can be reduced.

[0533] Next, openings 290 are formed in the conductive layer 240 and the insulating layer 280 at positions overlapping the conductive layer 220 (FIG. 16A). At this time, recesses are formed in the conductive layer 220 at positions overlapping the openings 290.

[0534] Because the opening 290 has a large aspect ratio, it is preferable to process a part of the conductive layer 240 and a part of the insulating layer 280 by anisotropic etching. In particular, processing by dry etching is preferable because it is suitable for fine processing. Furthermore, the processing may be performed under different conditions depending on the layer.

[0535] Here, it is preferable to use processing conditions that result in tapered sidewalls of the conductive layer 240 and the insulating layer 280c, and it is also preferable to use processing conditions that result in steep sidewalls of the insulating layer 280b.

[0536] Furthermore, the insulating layer 280a may be formed using processing conditions that result in tapered sidewalls, or may be formed using processing conditions that result in steep sidewalls.

[0537] Here, by devising the materials of the insulating layer 280c and the insulating layer 280b, it is possible to form the insulating layer 280c in a tapered shape and the insulating layer 280b in a steep shape using the same dry etching conditions.

[0538] Subsequently, heat treatment may be performed. The above description of <Heat Treatment> can be referred to for the heat treatment. For example, the heat treatment may be performed at a temperature of 350° C. to 550° C. for 1 minute to 1 hour, or 10 minutes to 30 minutes. By performing the heat treatment, impurities such as water contained in the insulating layer 280 and the like can be reduced before the formation of the oxide semiconductor layer 230. Furthermore, by performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the insulating layer 280 and the like as much as possible.

[0539] The conductive layer 240 and the insulating layer 280 may be opened using the same mask or different masks.

[0540] Subsequently, the oxide semiconductor layer 230 is formed so as to cover the opening 290. The oxide semiconductor layer 230 is formed in contact with the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the top surface and side surface of the conductive layer 240.

[0541] The oxide semiconductor layer 230 can be formed by stacking a plurality of layers. Here, the oxide semiconductor layer 230 is formed by depositing a first layer to a third layer in this order.

[0542] It is preferable to use a film formation method for the first layer that causes little damage to the insulating layer 280 and does not cause alloying with the insulating layer 280. For example, it is preferable to form the first layer using an ALD method, a PECVD method, a thermal CVD method, an MOCVD method, an MBE method, or the like.

[0543] Furthermore, it is preferable that the oxide semiconductor layer 230 has a high aspect ratio and high coverage on the sidewalls and bottom of the opening 290 having a small diameter. Therefore, it is preferable that at least some of the layers formed as the oxide semiconductor layer 230 be formed using a method with excellent coverage. In particular, by using the ALD method, it is possible to form a film with small thickness variation within the opening 290 along the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the side surface of the conductive layer 240.

[0544] Furthermore, the oxide semiconductor layer 230 preferably has high crystallinity. By increasing the crystallinity of the oxide semiconductor layer 230, diffusion of impurities in the oxide semiconductor layer 230 is suppressed, and therefore, the electrical characteristics of the transistor are less likely to fluctuate, and reliability can be improved. For example, a metal oxide formed by a sputtering method tends to have high crystallinity. Therefore, by forming at least some of the layers formed as the oxide semiconductor layer 230 by a sputtering method, the oxide semiconductor layer 230 can have crystallinity.

[0545] On the other hand, the sputtering method may have poorer coverage than methods such as the ALD method, etc. Therefore, in consideration of the coverage on the sidewalls and bottom of the opening 290, when the sputtering method is used for one layer of the multiple layers formed as the oxide semiconductor layer 230, it is preferable to use a layer formed by a method with excellent coverage in combination with the other layer.

[0546] The above embodiment can be referred to for the method of forming the oxide semiconductor layer 230. First, the oxide semiconductor layer 230a is formed (not shown).

[0547] Next, an oxide semiconductor layer 230b is formed by sputtering (not shown).

[0548] Next, an oxide semiconductor layer 230c is formed by ALD (not shown).

[0549] Heat treatment may be performed after the formation of the oxide semiconductor layer 230c. By performing the heat treatment, for example, the crystallinity of the oxide semiconductor layer 230 can be increased. In particular, the crystallinity of the oxide semiconductor layer 230a and the oxide semiconductor layer 230c can be increased. For example, the heat treatment conditions and the heat treatment method described in Embodiment 1 can be used for the heat treatment. Furthermore, the heat treatment does not necessarily have to be performed after the formation of the oxide semiconductor layer 230c. For example, the heat treatment may be performed after the formation of the insulating layer 250, which will be described later. Alternatively, the crystallinity of the oxide semiconductor layer 230 can be increased by using heat generated during the formation of the conductive layer 260, which will be described later. Furthermore, impurities in the oxide semiconductor layer 230 can be reduced by performing the heat treatment.

[0550] Furthermore, microwave treatment may be performed after the formation of the oxide semiconductor layer 230c. By performing the microwave treatment, for example, impurities in the oxide semiconductor layer 230 can be reduced. Furthermore, the crystallinity of the oxide semiconductor layer 230 may be improved.

[0551] Next, the conductive layer 240 and the oxide semiconductor layer 230 are processed into an island shape (FIG. 16B). Here, the conductive layer 240 and the oxide semiconductor layer 230 can be processed at the same time using the same mask.

[0552] Note that the step of processing the conductive layer 240 into an island shape and the step of processing the oxide semiconductor layer 230 into an island shape may be performed independently. In this case, for example, the step of processing the conductive layer 240 into an island shape and the step of providing the opening 290 in the conductive layer 240 can be performed independently, and the order of these steps does not matter. Furthermore, the island shape and the formation of the opening may be performed at the same time by performing exposure using a mask for processing the conductive layer 240 into a square island shape and exposure using a mask for providing a circular opening, followed by etching. Furthermore, exposure using a multi-tone mask (typically a half-tone mask or a gray-tone mask) may be used.

[0553] Subsequently, the insulating layer 250 is formed on the oxide semiconductor layer 230 and the insulating layer 280. The insulating layer 250 is formed in contact with the oxide semiconductor layer 230.

[0554] Heat generated during the formation of the insulating layer 250 can be used to enhance the crystallinity of the oxide semiconductor layer 230. When the temperature for forming the insulating layer is, for example, 250° C. or higher, more preferably 350° C. or higher, the heat generated during the formation of the insulating layer can enhance the crystallinity of the oxide semiconductor layer 230.

[0555] After the insulating layer 250 is formed, heat treatment may be performed. By performing the heat treatment, for example, the crystallinity of the oxide semiconductor layer 230 can be increased. In particular, the crystallinity of the oxide semiconductor layer 230c and the oxide semiconductor layer 230b can be increased. Furthermore, by performing the heat treatment, the impurity concentration in the insulating layer 250 can be reduced. Note that the heat treatment is not necessarily performed after the insulating layer 250 is formed.

[0556] When heat treatment is performed, it may be performed at, for example, 100° C. or higher and 800° C. or lower, preferably 250° C. or higher and 650° C. or lower, and more preferably 350° C. or higher and 550° C. For example, the treatment may be performed at a temperature of 350° C. or higher and 550° C. for 1 minute or higher and 1 hour or lower, or 10 minutes or higher and 30 minutes or lower.

[0557] The heat treatment can be performed using nitrogen gas, an inert gas, or an oxidizing gas. For example, the heat treatment can be performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By the heat treatment containing oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230 can be reduced.

[0558] The heat treatment may be carried out under reduced pressure.

[0559] For the conditions of the heat treatment, the description of the heat treatment in the previous embodiment can be referred to.

[0560] Furthermore, microwave treatment is preferably performed after the formation of the insulating layer 250. The insulating layer 250 functions as a gate insulating layer, and therefore preferably has a low impurity concentration. This can prevent impurities from being mixed into a channel formation region of the oxide semiconductor layer. By performing microwave treatment after the formation of the insulating layer 250, the impurity concentration in the insulating layer 250 can be reduced. Furthermore, by performing microwave treatment, the crystallinity of the oxide semiconductor layer 230 may be improved.

[0561] In addition, V in the oxide semiconductor layer is formed through the insulating layer 250. Ｏ By splitting H into oxygen vacancies and hydrogen, it is possible to remove hydrogen as an impurity from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave treatment. Furthermore, oxygen radicals generated by the oxygen plasma can be supplied to oxygen vacancies formed in the oxide semiconductor layer through the insulating layer 250, thereby further reducing the oxygen vacancies in the oxide semiconductor layer.

[0562] For the conditions of the microwave treatment, the description of the microwave treatment in the previous embodiment can be referred to.

[0563] In the case where the insulating layer 280 contains oxygen, oxygen is preferably supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230 by heat treatment. Ｏ H can be reduced.

[0564] Next, a conductive layer that becomes the conductive layer 260a is formed over the insulating layer 250. The conductive layer that becomes the conductive layer 260a is formed so as to cover the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the top surface and side surface of the conductive layer 240, with the oxide semiconductor layer 230 and the insulating layer 250 sandwiched therebetween. Next, a conductive layer that becomes the conductive layer 260b is formed.

[0565] The conductive layer 260a and the conductive layer 260b are formed in contact with the insulating layer 250 provided in the opening 290 with a large aspect ratio. Therefore, the conductive layer that becomes the conductive layer 260a and the conductive layer that becomes the conductive layer 260b are preferably formed by a film formation method with good coverage, and more preferably by an ALD method, a metal CVD method, or the like.

[0566] Here, heat generated during deposition of the conductive layer that will become the conductive layer 260 can be used to enhance the crystallinity of the oxide semiconductor layer 230. By setting the deposition temperature of the conductive layer that will become the conductive layer 260 to, for example, 250° C. or higher, more preferably 350° C. or higher, the heat generated during deposition of the conductive layer can enhance the crystallinity of the oxide semiconductor layer 230. Here, for example, the conductive layer is formed by a metal CVD method at a temperature of 250° C. or higher.

[0567] Subsequently, a mask is used to remove a portion of the conductive layer that will become the conductive layer 260b and a portion of the conductive layer that will become the conductive layer 260a, thereby forming the conductive layer 260b and the conductive layer 260a (FIG. 16C).

[0568] Next, an insulating layer 283 is formed over the conductive layer 260. Subsequently, an insulating layer 285 is formed over the insulating layer 283.

[0569] Here, heat used in forming the insulating layers 283 and 285 can be used to increase the crystallinity of the oxide semiconductor layer 230 in some cases. When the temperature at which the insulating layers are formed is, for example, 250° C. or higher, more preferably 350° C. or higher, the heat used in forming the insulating layers can increase the crystallinity of the oxide semiconductor layer 230 in some cases. Here, for example, the insulating layer 283 is formed by an ALD method at a temperature of 250° C. or higher, and then the insulating layer 285 is formed by a sputtering method.

[0570] Through the above steps, a semiconductor device of one embodiment of the present invention can be manufactured.

[0571] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0572] 17A to 21. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0573] 17A to 17C , the structure of a memory device including a transistor and a capacitor will be described. Fig. 17A is a plan view of a memory device including a transistor 200 and a capacitor 100. Fig. 17B is a cross-sectional view taken along dashed line A1-A2 in Fig. 17A . Fig. 17C is a cross-sectional view taken along dashed line A3-A4 in Fig. 17A .

[0574] 17A to 17C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, an insulating layer 180 over the conductive layer 110, an insulating layer 280, and an insulating layer 283 over the memory cell 150. The insulating layer 140, the insulating layer 180, the insulating layer 280, and the insulating layer 283 function as interlayer films. The conductive layer 110 functions as a wiring.

[0575] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0576] The capacitor 100 includes a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130. The conductive layer 120 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor.

[0577] As shown in FIGS. 17B and 17C , an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. The conductive layer 115 has a region in contact with the upper surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the upper surface of the insulating layer 180. The insulating layer 130 is disposed so that at least a portion of it is located in the opening 190. The conductive layer 120 is disposed so that at least a portion of it is located in the opening 190. As shown in FIGS. 17B and 17C , the conductive layer 120 is preferably disposed so as to fill the opening 190. The films disposed inside the opening 190 are preferably formed using a method with high coverage, such as an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are preferably formed by an ALD method, a metal CVD method, or the like.

[0578] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surface of the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, this can promote miniaturization or high integration of memory devices.

[0579] 17B and 17C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a structure, miniaturization or high integration of the memory device can be achieved.

[0580] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the upper surface of the conductive layer 110. A conductive layer 120 is provided on the insulating layer 130 so as to fill the opening 190. The capacitor element 100 having such a configuration may be called a trench capacitor or a trench capacitor.

[0581] An insulating layer 280 is disposed on the capacitor element 100. That is, the insulating layer 280 is disposed on the conductive layer 115, the insulating layer 130, and the conductive layer 120. In other words, the conductive layer 120 is disposed below the insulating layer 280.

[0582] The transistor 200 includes a conductive layer 120 (corresponding to the conductive layer 220 in FIG. 7B , etc.), a conductive layer 240 over an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 120 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and drain electrode.

[0583] The transistor 200 can be described in detail in Embodiment 2 ( FIGS. 7A to 7C , 9A and 9B , etc.), and therefore will not be described in detail again. The transistor included in the memory cell 150 is not limited to the transistor 200 shown in FIGS. 7A to 7C , 9A to 9B , etc., and any of the transistors exemplified in Embodiment 2 can be applied.

[0584] As shown in FIGS. 17A to 17C , the transistor 200 is provided so as to overlap ...

Claims

An oxide semiconductor layer containing indium, zinc, and an element M, the element M is one or more of gallium, tin, and yttrium; the oxide semiconductor layer has a first region, a second region on the first region, and a third region on the second region; the first region is located at a distance of 0 nm to 3 nm substantially perpendicularly from a surface on which the oxide semiconductor layer is to be formed, In a cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright points arranged in layers in a direction parallel to a surface on which the oxide semiconductor layer is formed are confirmed in each of the first region, the second region, and the third region; an aluminum concentration of the oxide semiconductor layer obtained by STEM-EDX is 3 atomic % or less; 　 An oxide semiconductor layer containing indium, zinc, and an element M, the element M is one or more of gallium, tin, and yttrium; the oxide semiconductor layer has a first region, a second region on the first region, and a third region on the second region; the first region is located at a distance of 0 nm to 3 nm substantially perpendicularly from a surface on which the oxide semiconductor layer is to be formed, In a cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright points arranged in layers in a direction parallel to a surface on which the oxide semiconductor layer is formed are confirmed in each of the first region, the second region, and the third region; The aluminum concentration of the oxide semiconductor layer obtained by SIMS is 1×10 ２０ atoms / cm ３ The oxide semiconductor layer is as follows: 　 In claim 1 or 2, the second region comprises zinc; the second region has crystals; The c-axis of the crystal is approximately parallel to a normal direction of a surface on which the oxide semiconductor layer is formed. 　 In claim 1 or 2, The second region has a higher c-axis orientation rate than the first region. 　 In claim 1 or 2, The third region has a higher c-axis orientation rate than the first region. 　 In claim 1 or 2, a content of indium in the first region is higher than a content of indium in the second region; an indium content in the third region being higher than an indium content in the second region; 　 forming a first metal oxide; forming a second metal oxide on the first metal oxide; A method for forming an oxide semiconductor layer by forming a third metal oxide over the second metal oxide, Each of the first metal oxide and the third metal oxide is formed by an ALD method using a precursor containing indium and an oxidizing agent; the aluminum content of the indium-containing precursor is 100 ppm or less; the second metal oxide is formed by a sputtering method using a sputtering target containing indium. 　 In claim 7, The sputtering target comprises zinc, The sputtering method is performed in an atmosphere containing oxygen. 　 In claim 7, The method for forming an oxide semiconductor layer, wherein the substrate is heated to a temperature of 100° C. or higher and 350° C. or lower in the ALD method. 　 In claim 7, a first metal oxide layer formed on the first metal oxide layer, a second metal oxide layer formed on the second metal oxide layer, and a third metal oxide layer formed on the third metal oxide layer. 　 In claim 7, No clear boundary is observed between the first metal oxide and the second metal oxide; A method for forming an oxide semiconductor layer, wherein no clear boundary is observed between the second metal oxide and the third metal oxide. 　 In claim 7, After forming the third metal oxide on the second metal oxide, A method for forming an oxide semiconductor layer, comprising the steps of: performing heat treatment at a temperature higher than or equal to 350° C. and lower than or equal to 550° C. 　 a transistor on a first insulating layer and a second insulating layer; the transistor includes a first conductive layer on the first insulating layer, a second conductive layer, an oxide semiconductor layer, a gate insulating layer, and a gate electrode; the oxide semiconductor layer contains indium, zinc, and an element M; the element M is one or more of gallium, tin, and yttrium; the aluminum concentration of the oxide semiconductor layer obtained by STEM-EDX is 3 atomic % or less; the second insulating layer is located between the first conductive layer and the second conductive layer; the second conductive layer is located on the second insulating layer; the second insulating layer and the second conductive layer have a first opening reaching the first conductive layer; the oxide semiconductor layer is in contact with a side surface of the second insulating layer in the first opening and a side surface of the second conductive layer in the first opening; the gate insulating layer is located on the oxide semiconductor layer; the gate electrode has a region in the first opening that overlaps with the oxide semiconductor layer with the gate insulating layer interposed therebetween; the oxide semiconductor layer has a first region, a second region on the first region, and a third region on the second region; the first region is located at a distance of 0 nm to 3 nm substantially perpendicularly from a surface on which the oxide semiconductor layer is to be formed, In a cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright points arranged in layers in a direction parallel to the formation surface are confirmed in each of the first region, the second region, and the third region. 　 In claim 13, a side surface of the second insulating layer in the first opening has a fourth region that forms an angle of 75 degrees or more and 90 degrees or less with respect to an upper surface of the first conductive layer; The first region is in contact with the fourth region. 　 In claim 13, A semiconductor device, wherein a thickness of the second insulating layer in a region sandwiched between the first conductive layer and the second conductive layer is greater than a width of the first opening. 　 In claim 13, the second conductive layer has a two-layer laminate structure, The lower layer is made of ruthenium, tungsten, titanium nitride, or tantalum nitride. A semiconductor device in which the top layer is made of indium tin oxide or indium tin oxide doped with silicon. 　 forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a first opening reaching the first conductive layer by removing a portion of the second conductive layer and a portion of the first insulating layer to expose an upper surface of the first conductive layer; forming a first metal oxide so as to be in contact with a top surface of the first conductive layer, a side surface of the first insulating layer within the first opening, a side surface of the second conductive layer within the first opening, and a top surface of the second conductive layer; forming a second metal oxide on the first metal oxide; forming a third metal oxide on the second metal oxide; forming a second insulating layer in contact with an upper surface of the third metal oxide; forming a third conductive layer on the second insulating layer; Each of the first metal oxide and the third metal oxide is formed by an ALD method using a precursor containing indium and an oxidizing agent; the aluminum content of the indium-containing precursor is 100 ppm or less; The second metal oxide is formed by a sputtering method using a sputtering target containing indium. In claim 17, The method for manufacturing a semiconductor device, wherein the third conductive layer is formed by a metal CVD method at a temperature of 250° C. or higher.