Semiconductor device

Abstract

This semiconductor device includes: a chip having a main surface; a first region of a first conductivity type formed in a surface layer part of the main surface in the chip; a second region of a second conductivity type formed in a region on the main surface side with respect to the first region in the chip; a trench-type gate structure formed on the main surface and spaced apart from a bottom part of the second region; an impurity region of the first conductivity type formed on the surface layer part of the main surface along the gate structure; and a drift region of the first conductivity type which is formed in a thickness range between the bottom part of the second region and a bottom wall of the gate structure and separates the impurity region and a channel.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-119282 filed with the Japan Patent Office on July 21, 2023, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2019 / 0280119A1) discloses a semiconductor device including a p-type doped region formed in an n-type epitaxial layer directly below a trench gate structure.

[0003] US Patent Application Publication No. 2019-0280119

[0004] SUMMARY The present disclosure provides a semiconductor device having a novel layout.

[0005] The present disclosure provides a semiconductor device including: a chip having a main surface; a first region of a first conductivity type formed within the chip in a surface layer portion of the main surface; a second region of a second conductivity type formed within the chip in a region on the main surface side of the first region; a trench-type gate structure formed in the main surface at a distance from a bottom of the second region; an impurity region of the first conductivity type formed in a surface layer portion of the main surface along the gate structure; and a drift region of the first conductivity type formed in a thickness range between the bottom of the second region and a bottom wall of the gate structure, and separating the impurity region from a channel.

[0006] The present disclosure provides a semiconductor device including: a chip having a main surface; a first region of a first conductivity type formed within the chip in a surface layer portion of the main surface; a second region of a second conductivity type formed within the chip in a region on the main surface side of the first region; a trench-type gate structure formed on the main surface spaced from a bottom of the second region; a drift region of the first conductivity type formed in a thickness range between the bottom of the second region and a bottom wall of the gate structure; and a high-concentration region of a second conductivity type formed within the second region on the side of the gate structure and having an impurity concentration higher than the impurity concentration of the second region.

[0007] The above and further objects, features and advantages will become more apparent from the accompanying drawings and detailed description.

[0008] FIG. 1 is a plan view showing a semiconductor device. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a perspective view showing the shape of a chip. FIG. 4 is a plan view showing an example layout of a first main surface. FIG. 5 is an enlarged plan view showing a main portion of the first main surface. FIG. 6 is a cross-sectional view showing a cross-sectional structure taken along line VI-VI in FIG. 5 , together with a high-concentration region according to a first embodiment. FIG. 7 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 6 . FIG. 8A is an enlarged cross-sectional view showing a high-concentration region according to a second embodiment. FIG. 8B is an enlarged cross-sectional view showing a high-concentration region according to a third embodiment. FIG. 8C is an enlarged cross-sectional view showing a high-concentration region according to a fourth embodiment. FIG. 8D is an enlarged cross-sectional view showing a high-concentration region according to a fifth embodiment. FIG. 8E is an enlarged cross-sectional view showing a high-concentration region according to a sixth embodiment. FIG. 8F is an enlarged cross-sectional view showing a high-concentration region according to a seventh embodiment. FIG. 8G is an enlarged cross-sectional view showing a high-concentration region according to an eighth embodiment. FIG. 8H is an enlarged cross-sectional view showing a high-concentration region according to a ninth embodiment. 8I is an enlarged cross-sectional view showing a high concentration region according to the tenth embodiment. FIG. 8J is an enlarged cross-sectional view showing a high concentration region according to the eleventh embodiment. FIG. 8K is an enlarged cross-sectional view showing a high concentration region according to the twelfth embodiment. FIG. 8L is an enlarged cross-sectional view showing a high concentration region according to the thirteenth embodiment. FIG. 8M is an enlarged cross-sectional view showing a high concentration region according to the fourteenth embodiment. FIG. 8N is an enlarged cross-sectional view showing a high concentration region according to the fifteenth embodiment. FIG. 8O is an enlarged cross-sectional view showing a high concentration region according to the sixteenth embodiment. FIG. 9 is a schematic diagram showing a wafer used in manufacturing a semiconductor device. FIG. 10A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. FIG. 10B is a cross-sectional view showing a step after FIG. 10A. FIG. 10C is a cross-sectional view showing a step after FIG. 10B. FIG. 10D is a cross-sectional view showing a step after FIG. 10C. FIG. 10E is a cross-sectional view showing a step after FIG. 10D. FIG. 10F is a cross-sectional view showing a step after FIG. 10E. FIG. 10G is a cross-sectional view showing a step after FIG. 10F. Fig. 10H is a cross-sectional view showing a step after Fig. 10G. Fig. 10I is a cross-sectional view showing a step after Fig. 10H. Fig. 10J is a cross-sectional view showing a step after Fig. 10I. Fig. 10K is a cross-sectional view showing a step after Fig. 10J. Fig. 10L is a cross-sectional view showing a step after Fig. 10K.Fig. 10M is a cross-sectional view showing a step after Fig. 10L. Fig. 10N is a cross-sectional view showing a step after Fig. 10M. Fig. 11 is an enlarged cross-sectional view showing a semiconductor device according to a modified example.

[0009] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] FIG. 1 is a plan view showing a semiconductor device 1. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1. FIG. 3 is a perspective view showing the shape of a chip 2. FIG. 4 is a plan view showing an example layout of a first main surface 3. FIG. 5 is an enlarged plan view showing a main portion of the first main surface 3. FIG. 6 is a cross-sectional view showing a cross-sectional structure taken along line VI-VI shown in FIG. 5 together with a high concentration region 30 according to a first embodiment. FIG. 7 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 6.

[0013] 1 to 7, semiconductor device 1 includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1 is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0014] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device."

[0015] The semiconductor device 1 may be referred to as a "SiC-MISFET." Hexagonal SiC single crystal has a variety of polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0018] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0019] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0020] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle from a vertical line along the vertical direction Z toward the off-direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off-angle with respect to the horizontal plane.

[0021] The off-direction is preferably the a-axis direction of the SiC single crystal (second direction Y in this embodiment). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0022] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0023] The semiconductor device 1 includes an n-type base region 6 formed in a surface layer portion of the second main surface 4. A drain potential as a first potential (high potential) is applied to the base region 6. The base region 6 may also be referred to as a "base layer," a "semiconductor layer," a "drain region," or the like.

[0024] The base region 6 is formed in a layer shape extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the base region 6 is made of an n-type semiconductor layer. Specifically, the base region 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The base region 6 (substrate) has the off direction and off angle described above.

[0025] The base region 6 may have a thickness of 10 μm to 500 μm. The thickness of the base region 6 may have a value belonging to at least one of the ranges of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 300 μm, 300 μm to 400 μm, and 400 μm to 500 μm.

[0026] The semiconductor device 1 includes an n-type first region 7 formed in a surface layer portion of the first main surface 3. The first region 7 may also be referred to as a "first semiconductor region," a "first semiconductor layer," a "base drift region (layer)," or the like. The first region 7 has an n-type impurity concentration lower than the n-type impurity concentration of the base region 6. The first region 7 is formed in a region on the first main surface 3 side of the base region 6 in a cross-sectional view, and is electrically connected to the base region 6.

[0027] The first region 7 is formed in a layer shape extending along the first main surface 3 and is exposed from the first to fourth side surfaces 5A to 5D. In this embodiment, the first region 7 is made of an n-type semiconductor layer. Specifically, the first region 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0028] The first region 7 (epitaxial layer) has the off-orientation and off-angle described above. The first region 7 preferably has a thickness less than that of the base region 6. Of course, the thickness of the first region 7 may be greater than that of the base region 6.

[0029] The thickness of the first region 7 may be 5 μm or more and 15 μm or less. The thickness of the first region 7 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0030] The semiconductor device 1 includes a first surface 8, a second surface 9, and first to fourth connection surface portions 10A to 10D formed on the first main surface 3. The first surface 8, the second surface 9, and the first to fourth connection surface portions 10A to 10D define mesas on the first main surface 3. The first surface 8, the second surface 9, and the first to fourth connection surface portions 10A to 10D (i.e., mesas) may be considered to be components of the chip 2 (first main surface 3).

[0031] The first surface portion 8 may be referred to as the "active surface," the second surface portion 9 may be referred to as the "outer surface," the first to fourth connecting surface portions 10A to 10D may be referred to as "connecting surfaces," and the mesa may be referred to as the "active mesa."

[0032] The first surface portion 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The first surface portion 8 has a flat surface extending horizontally and is formed by a c-plane (Si-plane). In this embodiment, the first surface portion 8 is formed in a polygonal shape (specifically, a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. The planar area of ​​the first surface portion 8 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0033] The second surface 9 is located closer to the periphery of the first main surface 3 than the first surface 8, and is recessed in the thickness direction of the chip 2 (toward the second main surface 4) from the height position of the first surface 8. The second surface 9 extends in a strip shape along the first surface 8 in a plan view, and is formed in a ring shape (specifically, a quadrangular ring) surrounding the first surface 8. The second surface 9 is continuous with the first to fourth side surfaces 5A to 5D.

[0034] The second surface 9 is formed substantially parallel to the first surface 8 and has a flat surface extending horizontally. In this embodiment, the second surface 9 is formed by the c-plane (Si-plane). The second surface 9 is formed in the first region 7 at a distance from the base region 6. In other words, the second surface 9 is recessed to a depth less than the thickness of the first region 7, exposing the first region 7.

[0035] The second surface portion 9 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the second surface portion 9 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the second surface portion 9 is preferably 0.5 μm or more and 1.5 μm or less.

[0036] The first to fourth connection surface portions 10A to 10D extend in the vertical direction Z and are connected to the first surface portion 8 and the second surface portion 9. The first connection surface portion 10A is located on the first side surface 5A side, the second connection surface portion 10B is located on the second side surface 5B side, the third connection surface portion 10C is located on the third side surface 5C side, and the fourth connection surface portion 10D is located on the fourth side surface 5D side. The first connection surface portion 10A and the second connection surface portion 10B extend in the first direction X and face the second direction Y. The third connection surface portion 10C and the fourth connection surface portion 10D extend in the second direction Y and face the first direction X.

[0037] In this way, the mesa is defined in a protruding (convex) shape on the first main surface 3. The mesa is formed only in the first region 7, and not in the base region 6. The first to fourth connection surface portions 10A to 10D may extend substantially perpendicularly between the first surface portion 8 and the second surface portion 9, defining a mesa shaped like a quadrangular pillar. The first to fourth connection surface portions 10A to 10D may slope obliquely downward from the first surface portion 8 toward the second surface portion 9, defining a mesa shaped like a quadrangular pyramid. The first to fourth connection surface portions 10A to 10D may be inclined at an angle greater than 90° and equal to or less than 135° with respect to the first surface portion 8.

[0038] The semiconductor device 1 includes an active region 11 set in a chip 2. The active region 11 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 11 is set in an inner portion of the chip 2. Specifically, the active region 11 is set in a first surface portion 8.

[0039] The semiconductor device 1 includes a peripheral region 12 set outside the active region 11 in the chip 2. The peripheral region 12 is a region that does not include a device structure (transistor structure Tr). The peripheral region 12 is set in the peripheral portion of the chip 2. Specifically, the peripheral region 12 is set in the second surface portion 9. In other words, the peripheral region 12 is set in the region between the peripheral edge of the first surface portion 8 and the peripheral edge of the second surface portion 9 in a plan view.

[0040] The semiconductor device 1 includes a p-type second region 13 formed in a surface layer portion of the first main surface 3 (first surface portion 8) in the active region 11. The second region 13 may also be referred to as a "second semiconductor region," "second semiconductor layer," "impurity region," "body region," or the like. The second region 13 is formed in a surface layer portion of the first region 7. The second region 13 has a p-type impurity concentration higher than the n-type impurity concentration of the first region 7, and inverts the conductivity type of the first region 7 from n-type to p-type.

[0041] The second region 13 is formed at a distance from the bottom (base region 6) of the first region 7 toward the first main surface 3 (first surface portion 8). That is, the second region 13 is formed in a region on the first main surface 3 (first surface portion 8) side of the first region 7 in a cross-sectional view, and is electrically connected to the first region 7. In other words, the second region 13 is formed in a thickness range between the first main surface 3 (first surface portion 8) and the first region 7 in a cross-sectional view, and forms a pn junction with the first region 7.

[0042] In this embodiment, the second region 13 is formed at a distance inward from the periphery of the first surface portion 8 (the first to fourth connection surface portions 10A to 10D), and has a periphery portion located within the active region 11. Of course, the second region 13 may be exposed from at least one (for example, all) of the first to fourth connection surface portions 10A to 10D.

[0043] The second region 13 may be drawn from the first surface 8 to the second surface 9 across at least one (for example, all) of the first to fourth connecting surface portions 10A to 10D, and may be exposed from part or all of the second surface 9. In this case, the second region 13 may be exposed from at least one (for example, all) of the first to fourth side surfaces 5A to 5D. Of course, the second region 13 may be formed spaced inward from at least one (for example, all) of the first to fourth side surfaces 5A to 5D.

[0044] The second region 13 has an upper end located on the first surface portion 8 side, and a bottom portion (lower end portion) located on the bottom side of the first region 7. The upper end portion of the second region 13 is located on the first surface portion 8 side with respect to the depth position of the middle portion of the first region 7. The upper end portion of the second region 13 is located on the first surface portion 8 side with respect to the depth position of the second surface portion 9. Although not specifically shown in the drawings, the upper end portion of the second region 13 may be exposed from the first surface portion 8. Of course, the upper end portion of the second region 13 may be formed with a gap from the first surface portion 8 to the bottom side of the first region 7.

[0045] The distance between the upper ends of the first surface portion 8 and the second region 13 may be 0 μm or more and 1 μm or less. The distance between the upper ends of the first surface portion 8 and the second region 13 may have a value belonging to any one of the ranges of 0 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less.

[0046] The bottom of the second region 13 faces the base region 6 with a part of the first region 7 sandwiched therebetween. The bottom of the second region 13 is located closer to the bottom of the first region 7 with respect to the depth position of the second surface portion 9. The bottom of the second region 13 is preferably located closer to the first surface portion 8 with respect to the depth position of the intermediate portion of the first region 7. Of course, the bottom of the second region 13 may also be located closer to the bottom of the first region 7 with respect to the depth position of the intermediate portion of the first region 7.

[0047] The distance between the bottom of the first region 7 and the bottom of the second region 13 may be greater than 0 μm and less than 10 μm. The distance between the bottom of the first region 7 and the bottom of the second region 13 may have a value belonging to any one of the ranges of greater than 0 μm and less than 1 μm, 1 μm or more and less than 2 μm, 2 μm or more and less than 4 μm, 4 μm or more and less than 6 μm, 6 μm or more and less than 8 μm, and 8 μm or more and less than 10 μm.

[0048] The second region 13 has a thickness less than that of the first region 7. The thickness of the second region 13 may be 1 μm or more and 10 μm or less. The thickness of the second region 13 may have a value belonging to any one of the ranges of 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, and 8 μm or more and less than 10 μm.

[0049] The thickness of the second region 13 is preferably less than the distance between the bottom of the first region 7 and the bottom of the second region 13. Of course, the thickness of the second region 13 may be greater than the distance between the bottom of the first region 7 and the bottom of the second region 13. Also, the second region 13 may cross the boundary between the base region 6 and the first region 7 and have its bottom located within the base region 6.

[0050] Second region 13 may be formed by introducing a trivalent element (p-type impurity) into n-type first region 7. Second region 13 is preferably formed by a single impurity region extending in the thickness direction in cross-sectional view. Of course, second region 13 may also be formed by a plurality of impurity regions introduced and stacked in multiple stages in the thickness direction in cross-sectional view.

[0051] The second region 13 may be a p-type channeling region extending along the axial channel of the chip 2 (first region 7) in a cross-sectional view. The axial channel is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the chip 2 (first region 7), and is surrounded by atomic rows constituting a crystal axis extending in the thickness direction (crystal growth direction).

[0052] That is, the axial channel is a region in which the atomic rows are sparse extending in the thickness direction and the atomic rows (atomic distance / atomic density) are sparse in the horizontal direction in a plan view. The axial channel is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values ​​of "a1", "a2", "a3", and "c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c).

[0053] In this embodiment, the axial channel is composed of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal. That is, the axial channel extends along the c-axis and has the off-direction and off-angle described above. In other words, the axial channel is inclined by the off-angle from the vertical axis toward the off-direction.

[0054] When the second region 13 is a channeling region, the second region 13 may be an impurity region introduced parallel or nearly parallel to a region (axial channel) surrounded by atomic rows along a low-index crystal axis in the chip 2, and may be obliquely inclined with respect to the first main surface 3. Of course, the second region 13 may be a p-type random region extending in a random direction intersecting the axial channel of the chip 2 (first region 7). For example, the random direction may be the vertical direction Z.

[0055] The semiconductor device 1 includes a plurality of trench-type (trench electrode-type) gate structures 15 formed in the first main surface 3 (first surface portion 8) in the active region 11. The gate structures 15 may also be referred to as "trench structures," "trench gate structures," or the like. A gate potential is applied to the plurality of gate structures 15 as a control potential. The plurality of gate structures 15 control inversion and non-inversion of the channel in the second region 13 in response to the gate potential.

[0056] The multiple gate structures 15 are arranged on the first surface portion 8 at intervals inward from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D). The multiple gate structures 15 are arranged at intervals in the first direction X (= m-axis direction) in plan view, and each extends in a strip-like manner in the second direction Y (= a-axis direction). In other words, the multiple gate structures 15 are arranged in a strip-like manner extending in the second direction Y (= a-axis direction) in plan view. The extension direction of the multiple gate structures 15 coincides with the off-direction of the SiC single crystal.

[0057] When the gate pitch is defined as the distance in the horizontal direction (first direction X) between the centers of the plurality of gate structures 15, the gate pitch may be 1 μm or more and 5 μm or less. The gate pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0058] The plurality of gate structures 15 are formed on the first surface portion 8 so as to be positioned within the second region 13. Specifically, the plurality of gate structures 15 are formed at intervals from the depth position of the bottom of the second region 13 toward the first surface portion 8. It is preferable that the plurality of gate structures 15 cross the depth position of the middle portion of the second region 13.

[0059] Of course, the plurality of gate structures 15 may be formed at intervals from the depth position of the middle part of the second region 13 toward the first surface portion 8. In this embodiment, the plurality of gate structures 15 are formed substantially perpendicular to the first surface portion 8. Of course, the plurality of gate structures 15 may be formed in a tapered shape toward the bottom of the first region 7.

[0060] The side walls (long sides) of the plurality of gate structures 15 are each formed by the m-plane ((1-100) plane) of the SiC single crystal. Of course, the side walls (long sides) of the plurality of gate structures 15 may each be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 15. The side walls of the plurality of gate structures 15 are formed approximately perpendicular to the first main surface 3.

[0061] The bottom walls of the gate structures 15 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the gate structures 15 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the gate structures 15 may be curved in an arc shape toward the second main surface 4.

[0062] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 15 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0063] The gate structure 15 may have a width of 0.1 μm to 2 μm, and may have a width in at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0064] The gate structure 15 may have a depth approximately equal to the depth of the second surface portion 9. Of course, the depth of the gate structure 15 may be greater than the depth of the second surface portion 9 or less than the depth of the second surface portion 9.

[0065] The depth of the gate structure 15 may be 0.1 μm or more and 3 μm or less. The depth of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less.

[0066] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0067] The following describes the configuration of one gate structure 15. The gate structure 15 includes a trench 16, an insulating film 17, and a buried electrode 18. The trench 16 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 15.

[0068] The insulating film 17 covers the wall surface of the trench 16. The insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 17 include a silicon oxide film made of an oxide of the chip 2.

[0069] The insulating film 17 includes a first film portion and a second film portion. The first film portion covers the sidewall of the trench 16 in a film-like manner. The second film portion covers the bottom wall of the trench 16 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to that of the first film portion.

[0070] The insulating film 17 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0071] The buried electrode 18 is buried in the trench 16 with the insulating film 17 sandwiched therebetween. The buried electrode 18 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried electrode 18 faces the second region 13 with the insulating film 17 sandwiched therebetween.

[0072] The buried electrode 18 has an electrode surface exposed from the trench 16. The electrode surface of the buried electrode 18 is located closer to the bottom wall of the trench 16 with respect to the height position of the first surface portion 8. The electrode surface of the buried electrode 18 is located closer to the first main surface 3 with respect to the depth position of the bottom of the second region 13. The electrode surface of the buried electrode 18 has a recess in an inner portion that tapers toward the bottom wall of the trench 16.

[0073] The semiconductor device 1 includes a plurality of n-type source regions 20 (impurity regions) formed in a surface layer portion of the first main surface 3 (first surface portion 8) in the active region 11. A source potential is applied to the plurality of source regions 20. The plurality of source regions 20 have an n-type impurity concentration higher than the n-type impurity concentration of the first region 7. The n-type impurity concentration of the plurality of source regions 20 is higher than the p-type impurity concentration of the second region 13.

[0074] The source regions 20 are formed in regions along the gate structures 15 in the surface layer portion of the second region 13. Specifically, the source regions 20 are formed in regions between the gate structures 15, and extend in strip shapes in the second direction Y along the gate structures 15.

[0075] The plurality of source regions 20 are formed on both sides of the plurality of gate structures 15, respectively, and face the corresponding buried electrodes 18 across the corresponding insulating films 17. In this form, the plurality of source regions 20 have bottom portions located on the bottom wall side of the gate structures 15 relative to the electrode surfaces of the buried electrodes 18, and surface portions located on the first surface 8 side of the electrode surfaces of the buried electrodes 18. The surface portions of the source regions 20 are exposed from the first surface 8.

[0076] The multiple source regions 20 are formed at intervals from the depth position of the bottom wall of the gate structure 15 toward the first surface portion 8, and extend in layers along the first surface portion 8. That is, the multiple source regions 20 are formed in a region on the first surface portion 8 side with respect to the second region 13 in a cross-sectional view, and are electrically connected to the second region 13. In other words, the multiple source regions 20 are formed in a thickness range between the first surface portion 8 and the second region 13 in a cross-sectional view. The multiple source regions 20 are formed at intervals from the depth position of the second surface portion 9 toward the first surface portion 8.

[0077] In this embodiment, the source regions 20 are formed at intervals inward from the periphery of the first surface portion 8 (the first to fourth connection surface portions 10A to 10D). Therefore, the source regions 20 are not exposed from the first to fourth connection surface portions 10A to 10D. Of course, the source regions 20 may be exposed from the first to fourth connection surface portions 10A to 10D.

[0078] The semiconductor device 1 includes a plurality of p-type contact regions 21 formed in a surface layer portion of the first main surface 3 (first surface portion 8) in the active region 11. The plurality of contact regions 21 have a p-type impurity concentration higher than the p-type impurity concentration of the second region 13.

[0079] The plurality of contact regions 21 are formed in regions along the plurality of gate structures 15 in the surface layer portion of the second region 13. Specifically, the plurality of contact regions 21 are formed in regions outside the plurality of source regions 20 between the plurality of gate structures 15. In this embodiment, the plurality of contact regions 21 are respectively interposed in regions between the plurality of adjacent source regions 20, and each extend in a strip shape in the second direction Y along the plurality of gate structures 15.

[0080] Of course, the plurality of contact regions 21 may be arranged at intervals in the second direction Y along the plurality of gate structures 15. Furthermore, the plurality of contact regions 21 may have portions connected to the plurality of gate structures 15.

[0081] In this embodiment, the multiple contact regions 21 have bottom portions located on the bottom wall side of the gate structure 15 relative to the electrode surface of the buried electrode 18, and surface portions located on the first surface 8 side of the electrode surface of the buried electrode 18. The surface portions of the multiple contact regions 21 are exposed from the first surface 8. The bottoms of the multiple contact regions 21 are located on the bottom wall side of the gate structure 15 relative to the depth positions of the bottoms of the multiple source regions 20. In other words, the multiple contact regions 21 are formed deeper than the multiple source regions 20.

[0082] The plurality of contact regions 21 are formed at intervals from the depth position of the bottom wall of the gate structure 15 toward the first main surface 3 (first surface portion 8) and extend in layers along the first surface portion 8. That is, the plurality of contact regions 21 are formed in a region on the first main surface 3 (first surface portion 8) side with respect to the second region 13 in a cross-sectional view, and are electrically connected to the second region 13. In other words, the plurality of contact regions 21 are formed in a thickness range between the first main surface 3 (first surface portion 8) and the second region 13 in a cross-sectional view. The plurality of contact regions 21 are formed at intervals from the depth position of the second surface portion 9 toward the first main surface 3 (first surface portion 8).

[0083] In this embodiment, the multiple contact regions 21 are formed at intervals inward from the periphery of the first surface portion 8 (the first to fourth connection surface portions 10A to 10D). Therefore, the multiple contact regions 21 are not exposed from the first to fourth connection surface portions 10A to 10D. Of course, the multiple contact regions 21 may be exposed from the first to fourth connection surface portions 10A to 10D.

[0084] The semiconductor device 1 includes a plurality of n-type drift regions 25 formed in regions directly below a plurality of gate structures 15 in the chip 2. The drift regions 25 may also be referred to as "JFET (Junction Field Effect Transistor) portions," "JFET regions (layers)," or the like.

[0085] Drift region 25 is formed by introducing a pentavalent element (n-type impurity) into second region 13, thereby converting the conductivity type of second region 13 from p-type to n-type. That is, drift region 25 has a higher n-type impurity concentration than the p-type impurity concentration of second region 13. The n-type impurity concentration of drift region 25 may be higher than the n-type impurity concentration of first region 7, or may be lower than the n-type impurity concentration of first region 7. The n-type impurity concentration of drift region 25 is preferably lower than the n-type impurity concentration of source region 20.

[0086] The plurality of drift regions 25 are formed at intervals from one another in the horizontal direction (first direction X) within the second region 13. The plurality of drift regions 25 are formed in the thickness range between the bottom of the second region 13 and the bottom walls of the plurality of gate structures 15, and overlap with the plurality of gate structures 15 in a one-to-one correspondence in the thickness direction.

[0087] In this embodiment, a single drift region 25 is interposed in each of the regions between the bottom of the second region 13 and the bottom walls of the plurality of gate structures 15, and extends in a strip-like manner in the second direction Y (= the a-axis direction) along the corresponding gate structure 15 in plan view. That is, the plurality of drift regions 25 are arranged in stripes extending in a strip-like manner in the second direction Y (= the a-axis direction) along the plurality of gate structures 15 in plan view.

[0088] The extension direction of the multiple drift regions 25 coincides with the off-direction of the SiC single crystal. Of course, when the multiple gate structures 15 extend in the first direction X, the multiple drift regions 25 may also extend in the first direction X. In this case, the multiple drift regions 25 intersect (specifically, are perpendicular to) the off-direction.

[0089] Of course, multiple drift regions 25 may be interposed in the region between the bottom of the second region 13 and the bottom wall of a corresponding one of the gate structures 15, with gaps in between in the second direction Y. In this case, the multiple drift regions 25 may each extend in a strip shape in the second direction Y in plan view.

[0090] When the distance between the centers of the plurality of drift regions 25 in the horizontal direction (first direction X) is defined as the drift pitch, the drift pitch is preferably approximately equal to the gate pitch of the plurality of gate structures 15. Of course, the drift pitch may be larger than the gate pitch or smaller than the gate pitch.

[0091] The drift pitch may be 1 μm or more and 5 μm or less. The drift pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0092] The ratio of the drift pitch to the gate pitch (pitch ratio) may be 0.8 or more and 1.2 or less. The pitch ratio may have a value belonging to any one of the ranges of 0.8 or more and 0.85 or less, 0.85 or more and 0.9 or less, 0.9 or more and 0.95 or less, 0.95 or more and 1 or less, 1 or more and 1.05 or less, 1.05 or more and 1.1 or less, 1.1 or more and 1.15 or less, and 1.15 or more and 1.2 or less. The pitch ratio is preferably 0.9 or more and 1.1 or less.

[0093] The plurality of drift regions 25 are formed at intervals from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) toward the inside of the first surface portion 8. Both end portions of the plurality of drift regions 25 may be located on the inside side of the gate structure 15 relative to both end portions of the gate structure 15. Both end portions of the plurality of drift regions 25 may be located on the periphery side of the first surface portion 8 relative to both end portions of the gate structure 15.

[0094] The following describes the configuration of one drift region 25. In this embodiment, the drift region 25 has a width greater than that of the gate structure 15, and extends from the region directly below it to both sides of the gate structure 15. Of course, the width of the drift region 25 may be less than that of the gate structure 15.

[0095] In this embodiment, drift region 25 is formed in a columnar shape extending horizontally along first surface 8 in a cross-sectional view. That is, drift region 25 has an aspect ratio of less than 1. The aspect ratio is the ratio of the depth of drift region 25 to the width of drift region 25. In this case, the aspect ratio may have a value belonging to at least one of the ranges of more than 0 and less than 0.25, 0.25 to 0.5, 0.5 to 0.75, and 0.75 to less than 1.

[0096] Of course, drift region 25 may be formed in a columnar shape extending in the thickness direction of chip 2 in a cross-sectional view. That is, drift region 25 may have an aspect ratio of 1 or greater. In this case, the aspect ratio may be 1 or greater and 3 or less. The aspect ratio may have a value belonging to at least one of the ranges of 1 or greater and 1.25 or less, 1.25 or greater and 1.5 or less, 1.5 or greater and 1.75 or less, 1.75 or greater and 2 or less, 2 or greater and 2.25 or less, 2.25 or greater and 2.5 or less, 2.5 or greater and 2.75 or less, and 2.75 or greater and 3 or less.

[0097] Drift region 25 is preferably formed of a single impurity region extending in the thickness direction in cross section. Of course, first drift region 26 may be formed of multiple impurity regions stacked and introduced in multiple stages in the thickness direction in cross section.

[0098] The drift region 25 has an upper end located on the bottom wall side of the gate structure 15 and a lower end (bottom) located on the bottom side of the second region 13. The upper end of the drift region 25 is connected to the bottom wall of the gate structure 15 and faces the buried electrode 18 in the vertical direction Z, with the insulating film 17 sandwiched therebetween.

[0099] The upper end of drift region 25 has extensions that extend from the region directly below gate structure 15 to both sides of gate structure 15 and extend along the sidewalls of gate structure 15 toward first surface portion 8. The extensions of drift region 25 extend in vertical direction Z. The thickness in the horizontal direction (first direction X) of the portion of drift region 25 that extends along the sidewalls of gate structure 15 (extensions) is preferably less than the thickness in the vertical direction Z of the portion of drift region 25 that extends along the bottom wall of gate structure 15.

[0100] The upper end of the drift region 25 preferably has an edge located closer to the gate structure 15 than the edge of the source region 20 on the opposite side from the gate structure 15. In other words, the upper end of the drift region 25 preferably does not face the contact region 21 in the thickness direction. Of course, the upper end of the drift region 25 may have a portion that partially faces the edge of the contact region 21 in the thickness direction.

[0101] The extension of the drift region 25 faces the buried electrode 18 in the horizontal direction (first direction X) with the insulating film 17 interposed therebetween. The extension of the drift region 25 is formed at intervals from the bottoms of the plurality of source regions 20 toward the bottom wall of the gate structure 15, and faces the source region 20 with a part of the second region 13 interposed therebetween.

[0102] As a result, the drift region 25, together with the plurality of source regions 20, defines the channel of the transistor structure Tr in the second region 13. That is, the drift region 25 forms a current path connecting the first region 7 and the plurality of source regions 20 via the channel. The inversion and non-inversion of the channel are controlled by the gate structure 15. The extension of the drift region 25 is preferably located on the bottom wall side of the gate structure 15 with respect to the depth position of the intermediate portion of the gate structure 15.

[0103] The lower end of drift region 25 crosses the bottom of second region 13 and is directly connected to first region 7. In this way, drift region 25 is electrically connected to first region 7. The lower end of drift region 25 is preferably located closer to the bottom of second region 13 than the depth position of the intermediate portion between the bottom of first region 7 and the bottom of second region 13. Of course, the lower end of drift region 25 may also be located closer to first region 7 than the depth position of the intermediate portion between the bottom of first region 7 and the bottom of second region 13.

[0104] The depth of drift region 25 may be equal to or greater than the distance between the bottom of second region 13 and the bottom wall of gate structure 15. The depth of drift region 25 may be equal to or less than 1, 1.25, 1.5, 1.75, or 2 times the distance between the bottom of second region 13 and the bottom wall of gate structure 15.

[0105] The semiconductor device 1 includes a plurality of p-type high concentration regions 30 formed on the sides of the plurality of gate structures 15 in the chip 2. The plurality of high concentration regions 30 are formed by introducing a trivalent element (p-type impurity) into the second region 13, and have a p-type impurity concentration higher than the p-type impurity concentration of the second region 13. The p-type impurity concentration of the high concentration regions 30 may be higher than the p-type impurity concentration of the contact region 21 or may be lower than the p-type impurity concentration of the contact region 21.

[0106] In this embodiment, a single high-concentration region 30 is formed in each region between adjacent gate structures 15, and extends in a strip-like manner in the second direction Y (= the a-axis direction) along the corresponding gate structure 15 in plan view. In other words, the multiple high-concentration regions 30 are arranged in stripes that extend in a strip-like manner in the second direction Y (= the a-axis direction) along the multiple gate structures 15 in plan view.

[0107] The extending direction of the multiple high-concentration regions 30 coincides with the off-direction of the SiC single crystal. Of course, when the multiple gate structures 15 extend in the first direction X, the multiple high-concentration regions 30 may also extend in the first direction X. In this case, the multiple high-concentration regions 30 intersect (specifically, are perpendicular to) the off-direction. Of course, the multiple high-concentration regions 30 may be formed at intervals in the second direction Y in regions between adjacent multiple gate structures 15. In this case, the multiple high-concentration regions 30 may each be formed in a strip shape extending in the second direction Y in a plan view.

[0108] The multiple high concentration regions 30 are formed at intervals from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) toward the inside of the first surface portion 8. Both end portions of the multiple high concentration regions 30 may be located on the inside side of the multiple gate structures 15 relative to both end portions of the multiple gate structures 15. Both end portions of the multiple high concentration regions 30 may be located on the periphery side of the first surface portion 8 relative to both end portions of the multiple gate structures 15.

[0109] The following describes the configuration of one high-concentration region 30. The high-concentration region 30 is formed at a distance in the horizontal direction (first direction X) from the multiple gate structures 15. The high-concentration region 30 is formed in a columnar shape extending in the thickness direction of the chip 2 (vertical direction Z).

[0110] The heavily doped region 30 faces at least a portion of the gate structure 15 where a channel is formed. In this embodiment, the heavily doped region 30 has a portion that faces the gate structure 15 in the horizontal direction, with part of the second region 13 in between, and a portion that faces the drift region 25 in the horizontal direction, with part of the second region 13 in between.

[0111] The high concentration region 30 has an upper end on the first surface portion 8 side and a lower end on the bottom side of the second region 13. The upper end of the high concentration region 30 is located on the first surface portion 8 side with respect to the depth position of the bottom wall of the gate structure 15. The upper end of the high concentration region 30 is located on the first surface portion 8 side with respect to the depth position of the second surface portion 9. The upper end of the high concentration region 30 is located on the first surface portion 8 side with respect to the depth position of the upper end (extension) of the drift region 25.

[0112] The upper end of the high concentration region 30 is formed at a distance from the first surface portion 8 toward the bottom of the second region 13, and faces the gate structure 15 in the horizontal direction (first direction X) across a part of the second region 13. In this embodiment, the upper end of the high concentration region 30 is formed at a distance from the bottom of the source region 20 toward the bottom of the second region 13. In this embodiment, the upper end of the high concentration region 30 is formed at a distance from the bottom of the contact region 21 toward the bottom of the second region 13.

[0113] In this embodiment, the high concentration region 30 has a width greater than the width of the contact region 21. Therefore, the upper end of the high concentration region 30 has a portion facing the entire contact region 21 with a portion of the second region 13 in between, and a portion facing the source region 20 with a portion of the second region 13 in between.

[0114] The high concentration region 30 is electrically connected to the contact region 21 via a part of the second region 13. Of course, the high concentration region 30 may have a width less than the width of the contact region 21 and may face either or both of the source region 20 and the contact region 21.

[0115] The width of the heavily doped region 30 may be less than the width of the gate structure 15 or may be greater than the width of the gate structure 15. The width of the heavily doped region 30 may be less than the width of the drift region 25 or may be greater than the width of the drift region 25.

[0116] The width of the high-concentration region 30 may be 0.1 μm or more and 2 μm or less. The width of the high-concentration region 30 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0117] The upper end of the high-concentration region 30 may be formed with a distance greater than 0 μm and equal to or less than 1.5 μm from the bottom of the contact region 21. The distance between the upper end of the high-concentration region 30 and the bottom of the contact region 21 may have a value belonging to at least one of the following ranges: greater than 0 μm and equal to or less than 0.1 μm, 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, and 1.25 μm to 1.5 μm.

[0118] The lower end of the high concentration region 30 is located closer to the bottom of the second region 13 than the depth position of the upper end (extension) of the drift region 25. The lower end of the high concentration region 30 is located closer to the bottom of the second region 13 than the depth position of the bottom wall of the gate structure 15. The lower end of the high concentration region 30 is located closer to the bottom of the second region 13 than the depth position of the second surface portion 9. Of course, the lower end of the high concentration region 30 may be located closer to the first surface portion 8 than the depth position of the second surface portion 9.

[0119] The lower end of the high concentration region 30 is located on the bottom wall side (first surface portion 8 side) of the gate structure 15 with respect to the depth position of the bottom of the second region 13. The lower end of the high concentration region 30 faces the first region 7 in the thickness direction with part of the second region 13 in between, and faces the drift region 25 in the horizontal direction (first direction X) with part of the second region 13 in between.

[0120] The lower end of high-concentration region 30 may be formed with a distance of more than 0 μm and not more than 5 μm from the bottom of second region 13. The distance between the lower end of high-concentration region 30 and the bottom of second region 13 may have a value belonging to at least one of the following ranges: more than 0 μm and not more than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0121] The high-concentration region 30 may cross the depth position of the intermediate portion of the second region 13. In other words, the upper end of the high-concentration region 30 may be located closer to the first surface portion 8 than the depth position of the intermediate portion of the second region 13, and the lower end of the high-concentration region 30 may be located closer to the bottom of the second region 13 than the depth position of the intermediate portion of the second region 13.

[0122] The high concentration region 30 may have a depth (thickness) less than the depth of the gate structure 15. The depth of the high concentration region 30 is the distance between the upper end and the lower end. Of course, the depth of the high concentration region 30 may be greater than the depth of the gate structure 15. The depth of the high concentration region 30 may be greater than the depth of the second surface portion 9 or less than the depth of the second surface portion 9. The depth of the high concentration region 30 may be greater than the depth of the drift region 25 or less than the depth of the drift region 25.

[0123] The ratio (depth ratio) of the depth of the high concentration region 30 to the depth of the gate structure 15 may be 0.1 or more and 2 or less. The depth ratio may have a value belonging to at least one of the ranges of 0.1 or more and 0.25 or less, 0.25 or more and 0.5 or less, 0.5 or more and 1 or less, 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, and 1.75 or more and 2 or less.

[0124] The depth of the high-concentration region 30 may be greater than 0 μm and less than or equal to 5 μm. The depth of the high-concentration region 30 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0125] The high-concentration region 30 may have an aspect ratio of 1 to 10. The aspect ratio of the high-concentration region 30 is the ratio of the depth of the high-concentration region 30 to the width of the high-concentration region 30. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0126] The semiconductor device 1 includes a plurality of p-type middle regions 31 formed in the second region 13. Each of the plurality of middle regions 31 is composed of a region defined by a plurality of drift regions 25 in the second region 13. That is, each of the plurality of middle regions 31 includes a portion of the second region 13 and a portion of the high-concentration region 30.

[0127] The middle regions 31 are arranged in stripes extending in the second direction Y (= the a-axis direction) in accordance with the arrangement of the drift regions 25. The extension direction of the middle regions 31 coincides with the off-direction of the SiC single crystal. Of course, if the drift regions 25 (the gate structures 15) extend in the first direction X, the middle regions 31 may also extend in the first direction X. In this case, the middle regions 31 intersect (specifically, are perpendicular to) the off-direction.

[0128] It is preferable that the middle region 31 has a width greater than that of the drift region 25. Of course, the width of the middle region 31 may be approximately equal to or less than the width of the drift region 25. The ratio of the width of the middle region 31 to the width of the drift region 25 (width ratio) may be 0.5 or more and 4 or less.

[0129] The width ratio may have a value belonging to at least one of the ranges of 0.5 to 0.75, 0.75 to 1, 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, 2.75 to 3, 3 to 3.25, 3.25 to 3.5, 3.5 to 3.75, and 3.75 to 4. The width ratio is preferably 0.75 to 2.25.

[0130] The multiple middle regions 31 form multiple pn junctions with the multiple drift regions 25. The multiple middle regions 31 may form a charge balance with the multiple drift regions 25 to form a superjunction structure. Charge balance refers to a state in which, for multiple middle regions 31 adjacent to each other across one drift region 25, a depletion layer extending from one middle region 31 and a depletion layer extending from the other middle region 31 are connected within the drift region 25 when a reverse bias voltage is applied.

[0131] Of course, the plurality of middle regions 31 do not necessarily have to form a superjunction structure, and may simply form a body diode structure together with the first region 7 and the plurality of drift regions 25 .

[0132] The semiconductor device 1 includes a main surface insulating film 35 covering the first main surface 3. The main surface insulating film 35 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 35 preferably includes the same type of insulating material as the insulating film 17. In this embodiment, the main surface insulating film 35 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 35 includes a silicon oxide film made of an oxide of the chip 2.

[0133] The main surface insulating film 35 selectively covers the first surface 8, the second surface 9, and the first to fourth connecting surface portions 10A to 10D. The main surface insulating film 35 is selectively connected to the insulating films 17 of the plurality of gate structures 15 on the first surface 8, and exposes the buried electrodes 18 of the plurality of gate structures 15.

[0134] In this embodiment, the main surface insulating film 35 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral portion of the second surface portion 9. Of course, the main surface insulating film 35 may be formed at a distance inward from the peripheral portion of the second surface portion 9, so that the peripheral portion of the second surface portion 9 is exposed.

[0135] The semiconductor device 1 includes an insulating interlayer film 36 that covers the main surface insulating film 35. The interlayer film 36 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 36 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 36 preferably includes a silicon oxide film.

[0136] The interlayer film 36 selectively covers the first surface 8, the second surface 9, and the first to fourth connecting surface portions 10A to 10D with the main surface insulating film 35 sandwiched therebetween. The interlayer film 36 covers the plurality of gate structures 15 (buried electrodes 18) on the first surface 8. In this embodiment, the interlayer film 36 is continuous with the first to fourth side surfaces 5A to 5D at the periphery of the second surface 9. Of course, the interlayer film 36 may be formed at a distance inward from the periphery of the second surface 9, leaving the periphery of the second surface 9 exposed.

[0137] The interlayer film 36 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer film 36 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0138] The semiconductor device 1 includes a plurality of source openings 37 formed in the interlayer film 36. The plurality of source openings 37 are formed in regions between the plurality of gate structures 15, respectively, and expose the corresponding plurality of source regions 20 and the corresponding contact regions 21. The plurality of source openings 37 each extend in a strip shape in the second direction Y along the plurality of gate structures 15. It is preferable that each of the plurality of source openings 37 has an opening end that is curved in an arc shape.

[0139] Of course, the plurality of source openings 37 may be formed in a one-to-many correspondence with the regions between the plurality of gate structures 15. In this case, the plurality of source openings 37 may be formed at intervals in the second direction Y in the regions between the plurality of gate structures 15. Furthermore, in this case, the plurality of source openings 37 may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, or the like in a plan view.

[0140] The semiconductor device 1 includes a plurality of gate openings 38 formed in an interlayer film 36 (see FIG. 4). Each of the plurality of gate openings 38 exposes a corresponding one of the gate structures 15 in a one-to-many correspondence. In this embodiment, the plurality of gate openings 38 are formed at both ends of the plurality of gate structures 15 (buried electrodes 18), respectively, and expose one end or the other end of the corresponding gate structure 15 (buried electrodes 18).

[0141] The plurality of gate openings 38 preferably each have an opening end curved in an arc shape, similar to the source opening 37. The plurality of gate openings 38 may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, or the like, in a plan view.

[0142] The semiconductor device 1 includes a source electrode 40 disposed on the first main surface 3. The source electrode 40 is a terminal electrode to which a source potential is applied from the outside. The source electrode 40 may also be referred to as a "source pad electrode," a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like. The source electrode 40 is disposed on a portion of the interlayer film 36 that covers the first surface portion 8.

[0143] In this embodiment, the source electrode 40 has a first pad portion 40a, a second pad portion 40b, and a third pad portion 40c. The first pad portion 40a has a relatively large planar area and forms the main body of the source electrode 40. In this embodiment, the first pad portion 40a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first surface portion 8.

[0144] The second pad portion 40b has a planar area smaller than that of the first pad portion 40a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 40a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 40c has a planar area smaller than that of the first pad portion 40a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 40a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 40b in the second direction Y.

[0145] The planar area of ​​the third pad portion 40c may be approximately equal to the planar area of ​​the second pad portion 40b. Of course, the planar area of ​​the third pad portion 40c may be larger than the planar area of ​​the second pad portion 40b, or may be smaller than the planar area of ​​the second pad portion 40b. Either or both of the second pad portion 40b and the third pad portion 40c may be used as a terminal portion for monitoring current.

[0146] The source electrode 40 does not necessarily have to have both the second pad portion 40b and the third pad portion 40c at the same time. The source electrode 40 may have only one of the second pad portion 40b and the third pad portion 40c. Of course, the source electrode 40 may be composed of only the first pad portion 40a and may not have both the second pad portion 40b and the third pad portion 40c.

[0147] The source electrode 40 extends from above the interlayer film 36 into the plurality of source openings 37 and is electrically connected to the plurality of source regions 20 and the plurality of contact regions 21 within the plurality of source openings 37 .

[0148] In this embodiment, the source electrode 40 has a layered structure including a lower electrode film 41 and a main electrode film 42, which are layered in this order from the chip 2 side. In this embodiment, the lower electrode film 41 has a layered structure including a first electrode film 43 and a second electrode film 44. In this embodiment, the first electrode film 43 includes a Ti film, and the second electrode film 44 includes a TiN film. The lower electrode film 41 does not necessarily have to have a layered structure, and may have a single-layer structure consisting of either the first electrode film 43 (Ti film) or the second electrode film 44 (TiN film).

[0149] The first electrode film 43 has a thickness less than the thickness of the interlayer film 36. The thickness of the first electrode film 43 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 43 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0150] The second electrode film 44 has a thickness less than that of the interlayer film 36. The thickness of the second electrode film 44 is preferably greater than the thickness of the first electrode film 43. The thickness of the second electrode film 44 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 44 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0151] The first electrode film 43 collectively covers the region of the interlayer film 36 where the multiple source openings 37 are formed, and extends from above the interlayer film 36 into the multiple source openings 37. The first electrode film 43 has a portion that covers the insulating main surface of the interlayer film 36 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 37 in a film-like manner, and a portion that covers the first main surface 3 within the multiple source openings 37. The first electrode film 43 covers the first main surface 3 (first surface portion 8) in the source openings 37 in a film-like manner, and is mechanically and electrically connected to the multiple source regions 20 and the multiple contact regions 21.

[0152] The second electrode film 44 directly covers the first electrode film 43. The second electrode film 44 collectively covers the region of the interlayer film 36 where the multiple source openings 37 are formed, sandwiching the first electrode film 43 therebetween, and extends from above the interlayer film 36 into the multiple source openings 37.

[0153] The second electrode film 44 has a portion that covers the insulating main surface of the interlayer film 36 in a film-like manner, sandwiching the first electrode film 43 therebetween, a portion that covers the wall surfaces of the plurality of source openings 37 in a film-like manner, sandwiching the first electrode film 43 therebetween, and a portion that covers the first main surface 3 in a film-like manner, sandwiching the first electrode film 43 therebetween, within the plurality of source openings 37. The second electrode film 44 covers the first main surface 3 (first surface portion 8) in a film-like manner, sandwiching the first electrode film 43 therebetween, within the source openings 37, and is electrically connected to the plurality of source regions 20 and the plurality of contact regions 21 via the first electrode film 43.

[0154] The main electrode film 42 contains a different conductive material from the lower electrode film 41 (the first electrode film 43 and the second electrode film 44). The main electrode film 42 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 42 has a thickness greater than the thickness (total thickness) of the lower electrode film 41. The thickness of the main electrode film 42 is preferably greater than the thickness of the interlayer film 36.

[0155] The thickness of the main electrode film 42 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 42 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0156] The main electrode film 42 directly covers the lower electrode film 41 (second electrode film 44). The main electrode film 42 backfills the source openings 37 and collectively covers the region of the interlayer film 36 where the source openings 37 are formed. The main electrode film 42 has a portion that covers the insulating principal surface of the interlayer film 36 with the lower electrode film 41 in between, a portion that covers the wall surfaces of the source openings 37 with the lower electrode film 41 in between, and a portion that covers the first principal surface 3 with the lower electrode film 41 in between.

[0157] The main electrode film 42 covers the first major surface 3 (first surface portion 8) within the source opening 37, sandwiching the lower electrode film 41 therebetween, and is electrically connected to a plurality of source regions 20 and a plurality of contact regions 21 via the lower electrode film 41.

[0158] The semiconductor device 1 includes a gate electrode 45 disposed on the first main surface 3. The gate electrode 45 is a terminal electrode to which a gate potential is applied from the outside. The gate electrode 45 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. Although not shown, the gate electrode 45, like the source electrode 40, includes a lower electrode film 41 and a main electrode film 42 stacked in this order from the chip 2 side.

[0159] The gate electrode 45 is disposed on a portion of the interlayer film 36 that covers the first surface 8, with a gap between it and the source electrode 40. In this embodiment, the gate electrode 45 is disposed in a region on the third side surface 5C side of the first pad 40a, and faces the first pad 40a in the first direction X. The gate electrode 45 is also interposed in a region between the second pad 40b and the third pad 40c, and faces both the second pad 40b and the third pad 40c in the second direction Y.

[0160] The gate electrode 45 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 45 has a planar area less than the planar area of ​​the source electrode 40. The gate electrode 45 has a planar area less than the planar area of ​​the first pad portion 40a. The gate electrode 45 may also have a planar area less than the planar area of ​​the second pad portion 40b (third pad portion 40c).

[0161] The gate electrode 45 partially faces the plurality of gate structures 15 across the interlayer film 36. Specifically, the gate electrode 45 is disposed inwardly from both ends of the plurality of gate structures 15 at a distance, and faces inner portions of the plurality of gate structures 15 across the interlayer film 36. In this embodiment, the gate electrode 45 does not have any direct electrical connection points to the plurality of gate structures 15.

[0162] Of course, the gate electrode 45 may be electrically connected to the plurality of gate structures 15 via the plurality of gate openings 38. The portions of the plurality of gate structures 15 that are located under the gate electrode 45 may be removed. In this case, the gate electrode 45 may face the second region 13 with the main surface insulating film 35 and the interlayer film 36 sandwiched therebetween.

[0163] The semiconductor device 1 includes a gate wiring 46 extending from the gate electrode 45 onto the first main surface 3. The gate wiring 46 may also be referred to as a "gate finger" or "gate finger electrode." The gate wiring 46 transmits the gate potential applied to the gate electrode 45 to other regions. Although not shown, the gate wiring 46 includes a lower electrode film 41 and a main electrode film 42 stacked in this order from the chip 2 side, similar to the source electrode 40 (gate electrode 45).

[0164] The gate wiring 46 is drawn out from the gate electrode 45 onto a portion of the interlayer film 36 that covers the first surface 8. The gate wiring 46 is routed in a strip shape in the region between the periphery of the first surface 8 and the source electrode 40. The gate wiring 46 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view. In this embodiment, the gate wiring 46 is formed in a strip shape with ends, having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 40.

[0165] The gate wiring 46 intersects (specifically, orthogonally crosses) the ends (both ends in this embodiment) of the plurality of gate structures 15. The gate wiring 46 enters the plurality of gate openings 38 from above the interlayer film 36 and is mechanically and electrically connected to the ends (both ends) of the plurality of gate structures 15 (buried electrodes 18) within the plurality of gate openings 38. As a result, the gate potential applied to the gate electrode 45 is applied to the plurality of gate structures 15 via the gate wiring 46.

[0166] The semiconductor device 1 includes a drain electrode 47 covering the second main surface 4. The drain electrode 47 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 47 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like. The drain electrode 47 is electrically connected to the base region 6. The drain electrode 47 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain electrode 47 may also partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.

[0167] The breakdown voltage that can be applied between the source electrode 40 and the drain electrode 47 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0168] 8A to 8O, second to sixteenth embodiments of the high concentration region 30 will be shown. 8A to 8O are enlarged cross-sectional views showing the high concentration region 30 according to the second to sixteenth embodiments. The semiconductor device 1 may include any one of the high concentration regions 30 according to the first to sixteenth embodiments.

[0169] Of course, the features of the high-concentration regions 30 according to the first to sixteenth embodiments can be combined as appropriate, and therefore the semiconductor device 1 can simultaneously include at least two of the features of the high-concentration regions 30 according to the first to sixteenth embodiments in the same or different regions.

[0170] 8A (second embodiment), the high concentration region 30 may be located closer to the first surface 8 than the depth position of the bottom of the contact region 21, and may have an upper end connected to the contact region 21. In this case, the upper end of the high concentration region 30 may be located closer to the first surface 8 than the depth positions of the bottoms of the plurality of source regions 20, and may be connected to the plurality of source regions 20. The upper end of the high concentration region 30 may be formed at an interval from the first surface 8 toward the bottom of the second region 13.

[0171] 8B (third embodiment), in the case of the second embodiment, the upper end of the high-concentration region 30 may be exposed from the first surface portion 8. In this case, the upper end of the high-concentration region 30 may overlap a part or the entire area of ​​the contact region 21. The upper end of the high-concentration region 30 may be formed as the contact region 21, and the contact region 21 may be omitted.

[0172] Referring to Figure 8C (fourth embodiment), in the case of the second embodiment, the upper end of the high concentration region 30 may be formed at a distance from the bottom of the multiple source regions 20 toward the bottom of the second region 13, and may be connected to the contact region 21 in the region between the bottom of the second region 13 (the depth position of the bottom wall of the gate structure 15) and the bottom of the multiple source regions 20.

[0173] 8D (fifth embodiment), the high concentration region 30 may cross the bottom of the second region 13 and have a lower end located within the first region 7. In other words, the high concentration region 30 may be directly electrically connected to the first region 7.

[0174] In this case, the lower end of high-concentration region 30 may be located closer to the bottom of first region 7 than the lower ends of the plurality of drift regions 25, or may be located closer to the bottom of second region 13 than the lower ends of the plurality of drift regions 25. The lower end of high-concentration region 30 is preferably located closer to the bottom of second region 13 than the depth position of the intermediate portion between the bottom of first region 7 and the bottom of second region 13.

[0175] Referring to Figure 8E (sixth embodiment), in the case of the fifth embodiment, the high concentration region 30 may have an upper end connected to the contact region 21, as in any one of the second to fourth embodiments.

[0176] 8F (seventh embodiment), the high concentration region 30 may have a lower end portion formed at a distance from the depth position of the bottom walls of the plurality of gate structures 15 toward the first surface portion 8. That is, the entire area of ​​the high concentration region 30 may be located in the area between the plurality of gate structures 15.

[0177] In this case, the high concentration region 30 may have either or both of a portion facing the gate structure 15 in the horizontal direction (first direction X) and a portion facing the drift region 25 in the horizontal direction (first direction X). The high concentration region 30 may have only a portion facing the gate structure 15 in the horizontal direction (first direction X), and may not have a portion facing the drift region 25 in the horizontal direction (first direction X).

[0178] Referring to Figure 8G (eighth embodiment), in the seventh embodiment, the high concentration region 30 may have an upper end connected to the contact region 21, as in any one of the second to fourth embodiments.

[0179] 8H (ninth embodiment), the heavily doped region 30 may have an upper end formed at a distance from the depth position of the bottom walls of the plurality of gate structures 15 toward the bottom of the second region 13. That is, the entire heavily doped region 30 may be located closer to the bottom of the second region 13 than the depth position of the bottom walls of the plurality of gate structures 15.

[0180] The heavily doped region 30 does not have a portion facing the gate structure 15 in the horizontal direction (first direction X), but only has a portion facing the drift region 25 in the horizontal direction (first direction X). That is, in this embodiment, the heavily doped region 30 is formed only in the region between the adjacent drift regions 25.

[0181] Referring to Figure 8I (10th embodiment), in the 9th embodiment, the high concentration region 30 may cross the bottom of the second region 13 and have a lower end located within the first region 7, as in the 5th embodiment.

[0182] Referring to FIG. 8J (eleventh embodiment), the high-concentration region 30 may have a low-concentration portion 50 extending in the thickness direction in the inner portion, and may be separated by the low-concentration portion 50 into a first high-concentration portion 51 on one side of the first direction X and a second high-concentration portion 52 on the other side of the first direction X.

[0183] The low concentration portion 50 may be formed by a part of the second region 13, or may have a p-type impurity concentration higher than the p-type impurity concentration of the second region 13. The low concentration portion 50 may be formed in a strip shape extending along the plurality of gate structures 15 in a plan view. In this case, the low concentration portion 50 may divide the high concentration region 30 into a first high concentration portion 51 and a second high concentration portion 52 over the entire area of ​​the high concentration region 30.

[0184] The first high concentration portion 51 has a p-type impurity concentration higher than the p-type impurity concentration of the low concentration portion 50. The first high concentration portion 51 is formed at a distance from the one and other gate structures 15 and is unevenly located on the one gate structure 15 side. The first high concentration portion 51 extends in a band shape in the second direction Y (= a-axis direction) along the one gate structure 15 in plan view.

[0185] The first high concentration portion 51 is formed at a distance from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) toward the inside of the first surface portion 8. Both ends of the first high concentration portion 51 may be located on the inside side of one gate structure 15 relative to both ends of the one gate structure 15. Both ends of the first high concentration portion 51 may be located on the periphery side of the first surface portion 8 relative to both ends of the one gate structure 15.

[0186] The first high concentration portion 51 is formed in a columnar shape extending in the thickness direction (vertical direction Z) of the chip 2. The first high concentration portion 51 faces a portion of at least one of the gate structures 15 where a channel is formed. In this embodiment, the first high concentration portion 51 has a portion facing one of the gate structures 15 in the horizontal direction with a portion of the second region 13 in between, and a portion facing the drift region 25 in the horizontal direction with a portion of the second region 13 in between.

[0187] The second high concentration portions 52 are formed at intervals from the one and the other gate structures 15 and are unevenly distributed toward the other gate structure 15. The second high concentration portions 52 face the first high concentration portions 51 in the horizontal direction (first direction X) with the low concentration portion 50 interposed therebetween. The second high concentration portions 52 extend in a strip shape in the second direction Y (= a-axis direction) along the other gate structure 15 in plan view. In other words, the second high concentration portions 52 extend substantially parallel to the first high concentration portions 51 so as to run in parallel with the first high concentration portions 51.

[0188] The second high concentration portion 52 is formed at a distance from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) toward the inside of the first surface portion 8. Both ends of the second high concentration portion 52 may be located on the inside side of the other gate structure 15 relative to both ends of the other gate structure 15. Both ends of the second high concentration portion 52 may be located on the periphery side of the first surface portion 8 relative to both ends of the other gate structure 15.

[0189] The second high-concentration portion 52 is formed in a columnar shape extending in the thickness direction (vertical direction Z) of the chip 2. The second high-concentration portion 52 faces at least a portion of the other gate structure 15 where a channel is formed. In this form, the second high-concentration portion 52 has a portion that faces the other gate structure 15 in the horizontal direction, with part of the second region 13 in between, and a portion that faces the drift region 25 in the horizontal direction, with part of the second region 13 in between.

[0190] The second high concentration region 52 may have a length in the thickness direction that is approximately equal to the length of the first high concentration region 51 and may face the first high concentration region 51 across the entire thickness direction, with the low concentration region 50 sandwiched between them. Of course, the second high concentration region 52 may have a length in the thickness direction that is different from the length of the first high concentration region 51 and may face a part or the entire first high concentration region 51 across the low concentration region 50. In this case, the length of the second high concentration region 52 may be greater than the length of the first high concentration region 51 or may be less than the length of the first high concentration region 51.

[0191] The upper end of the first high concentration portion 51 forms part of the upper end of the high concentration region 30, and the upper end of the first high concentration portion 51 forms part of the lower end of the high concentration region 30. The upper end of the second high concentration portion 52 forms part of the upper end of the high concentration region 30, and the upper end of the second high concentration portion 52 forms part of the lower end of the high concentration region 30.

[0192] The upper end of the second high concentration portion 52 is located at a depth position substantially equal to that of the upper end of the first high concentration portion 51. Of course, the upper end of the second high concentration portion 52 may be located closer to the first surface portion 8 than the depth position of the upper end of the first high concentration portion 51, or may be located closer to the bottom of the second region 13 than the depth position of the upper end of the first high concentration portion 51.

[0193] The lower end of the second high concentration portion 52 is located at a depth position substantially equal to that of the lower end of the first high concentration portion 51. Of course, the lower end of the second high concentration portion 52 may be located closer to the first surface portion 8 than the depth position of the lower end of the first high concentration portion 51, or may be located closer to the bottom of the second region 13 than the depth position of the lower end of the first high concentration portion 51.

[0194] The upper ends of the first and second heavily doped regions 51, 52 are located on the first surface portion 8 side with respect to the depth position of the bottom wall of the gate structure 15. The upper ends of the first and second heavily doped regions 51, 52 are located on the first surface portion 8 side with respect to the depth position of the second surface portion 9. The upper ends of the first and second heavily doped regions 51, 52 are located on the first surface portion 8 side with respect to the depth position of the upper end (extension) of the drift region 25.

[0195] The upper ends of the first and second high concentration portions 51, 52 are formed at intervals from the first surface portion 8 toward the bottom of the second region 13, and face the gate structure 15 in the horizontal direction (first direction X) across a part of the second region 13. The upper ends of the first and second high concentration portions 51, 52 are formed at intervals from the bottom of the source region 20 toward the bottom of the second region 13. The upper ends of the first and second high concentration portions 51, 52 are formed at intervals from the bottom of the contact region 21 toward the bottom of the second region 13.

[0196] In this embodiment, the first and second high concentration portions 51, 52 have a width less than the width of the contact region 21 and face either or both of a part of the source region 20 and a part of the contact region 21, with a part of the second region 13 sandwiched therebetween. Of course, the widths of the first and second high concentration portions 51, 52 may be greater than the width of the contact region 21. The first and second high concentration portions 51, 52 are electrically connected to the contact region 21 via a part of the second region 13.

[0197] The widths of the first and second heavily doped regions 51, 52 may be less than the width of the gate structure 15 or may be greater than the width of the gate structure 15. The widths of the first and second heavily doped regions 51, 52 may be less than the width of the drift region 25 or may be greater than the width of the drift region 25.

[0198] The widths of the first and second high concentration regions 51, 52 may be greater than 0 μm and less than 2 μm. The widths of the first and second high concentration regions 51, 52 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.1 μm, 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm. The widths of the first and second high concentration regions 51, 52 are preferably less than 1 μm.

[0199] The lower ends of the first and second heavily doped regions 51, 52 are located closer to the bottom of the second region 13 than the depth of the upper end (extension) of the drift region 25. The lower ends of the first and second heavily doped regions 51, 52 are located closer to the bottom of the second region 13 than the depth of the bottom wall of the gate structure 15. The lower ends of the first and second heavily doped regions 51, 52 are located closer to the bottom of the second region 13 than the depth of the second surface portion 9. Of course, the lower ends of the first and second heavily doped regions 51, 52 may be located closer to the first surface portion 8 than the depth of the second surface portion 9.

[0200] The lower ends of the first and second heavily doped regions 51, 52 are located on the bottom wall side (first surface portion 8 side) of the gate structure 15 with respect to the depth position of the bottom of the second region 13. The lower ends of the first and second heavily doped regions 51, 52 face the first region 7 in the thickness direction with part of the second region 13 in between, and face the drift region 25 in the horizontal direction (first direction X) with part of the second region 13 in between.

[0201] The first and second high concentration portions 51, 52 may cross the depth position of the intermediate portion of the second region 13. In other words, the upper ends of the first and second high concentration portions 51, 52 may be located closer to the first surface portion 8 than the depth position of the intermediate portion of the second region 13, and the lower ends of the first and second high concentration portions 51, 52 may be located closer to the bottom of the second region 13 than the depth position of the intermediate portion of the second region 13.

[0202] The first and second high concentration portions 51, 52 may have a depth (thickness) less than the depth of the gate structure 15. Of course, the depth of the first and second high concentration portions 51, 52 may be greater than the depth of the gate structure 15. The depth of the first and second high concentration portions 51, 52 may be less than the depth of the second surface portion 9 or greater than the depth of the second surface portion 9. The depth of the first and second high concentration portions 51, 52 may be less than the depth of the drift region 25 or greater than the depth of the drift region 25.

[0203] The ratio (depth ratio) of the depth of the first and second heavily doped regions 51, 52 to the depth of the gate structure 15 may be 0.1 or more and 2 or less. The depth ratio may have a value belonging to at least one of the ranges of 0.1 or more and 0.25 or less, 0.25 or more and 0.5 or less, 0.5 or more and 1 or less, 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, and 1.75 or more and 2 or less.

[0204] The depth of the first and second high concentration portions 51, 52 may be greater than 0 μm and less than or equal to 5 μm. The depth of the first and second high concentration portions 51, 52 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0205] The first and second high concentration regions 51, 52 may have an aspect ratio of 1 to 20. The aspect ratio of the first and second high concentration regions 51, 52 is the ratio of the depth of the first and second high concentration regions 51, 52 to the width of the first and second high concentration regions 51, 52. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 2, 2 to 4, 4 to 6, 6 to 8, 8 to 10, 10 to 12, 12 to 14, 14 to 16, 16 to 18, and 18 to 20.

[0206] 8K (twelfth embodiment), in the eleventh embodiment, the first and second high-concentration portions 51, 52 may have upper ends connected to the contact region 21, as in any one of the second to fourth embodiments. The upper ends of the first and second high-concentration portions 51, 52 may be connected to the source region 20. The upper ends of the first and second high-concentration portions 51, 52 may be connected to either or both of the contact region 21 and the source region 20.

[0207] Referring to Figure 8L (13th embodiment), in the 11th embodiment, the first and second high concentration regions 51, 52 may have lower ends that cross the bottom of the second region 13 and are positioned within the first region 7, as in the fifth embodiment.

[0208] Referring to Figure 8M (14th embodiment), in the case of the 13th embodiment, the first and second high concentration regions 51, 52 may have upper ends connected to either or both of the contact region 21 and the source region 20, as in any one of the second to fourth embodiments.

[0209] 8N (15th embodiment), in the 11th embodiment, the first and second high concentration portions 51, 52 may have lower end portions formed at intervals toward the first surface portion 8 from the depth positions of the bottom walls of the plurality of gate structures 15, similar to the seventh or eighth embodiment. In this case, the first and second high concentration portions 51, 52 may have upper end portions connected to either or both of the contact region 21 and the source region 20, similar to the 14th embodiment.

[0210] 8O (16th embodiment), in the 11th embodiment, the first and second heavily doped regions 51, 52 may have upper ends formed at intervals from the depth positions of the bottom walls of the plurality of gate structures 15 toward the bottom of the second region 13, as in the 9th or 10th embodiment. In this case, the first and second heavily doped regions 51, 52 may have lower ends located within the first region 7, as in the 13th embodiment.

[0211] As described above, the semiconductor device 1 includes the chip 2, the n-type (first conductivity type) first region 7, the p-type (second conductivity type) second region 13, the trench gate structure 15, the n-type source region 20, and the n-type drift region 25. The chip 2 has a first main surface 3. The first region 7 is formed in a surface layer portion of the first main surface 3 within the chip 2. The second region 13 is formed in a region within the chip 2 closer to the first main surface 3 than the first region 7.

[0212] The gate structure 15 is formed on the first main surface 3 and spaced apart from the bottom of the second region 13. The source region 20 is formed in a surface layer portion of the first main surface 3 along the gate structure 15. The drift region 25 is formed in a thickness range between the bottom of the second region 13 and the bottom wall of the gate structure 15, and separates the source region 20 from a channel.

[0213] According to this configuration, a current path connecting the first region 7 and the source region 20 via the channel is formed by the drift region 25. This makes it possible to provide a semiconductor device 1 having a novel layout.

[0214] For example, in this semiconductor device 1, the bottom wall of gate structure 15 is positioned below the depth position of the bottom of second region 13. Therefore, the depletion layer resulting from the boundary (pn junction) between first region 7 and second region 13 expands in a region below the bottom wall of gate structure 15. This allows the breakdown voltage to be improved with a relatively simple configuration.

[0215] The chip 2 may include SiC. This configuration provides a SiC semiconductor device as the semiconductor device 1 having a novel layout. The SiC semiconductor device can further improve the breakdown voltage by utilizing the physical properties of SiC.

[0216] Drift region 25 may cross the bottom of second region 13 and be connected to first region 7. Drift region 25 may be connected to the bottom wall of gate structure 15. Drift region 25 may be formed to be wider than gate structure 15. According to these configurations, a current path connecting first region 7 and source region 20 can be appropriately formed with a relatively simple configuration.

[0217] The drift region 25 may have a depth less than the depth of the gate structure 15 when the depth position of the bottom wall of the gate structure 15 is used as a reference. This configuration can suppress variations in the depth of the drift region 25. As a result, a current path connecting the first region 7 and the source region 20 can be appropriately formed.

[0218] Drift region 25 may have an extension that extends along the sidewall of gate structure 15 toward first main surface 3 and is formed at a distance from source region 20 on the bottom wall side of gate structure 15. According to this configuration, a current path connecting first region 7 and source region 20 can be appropriately formed by utilizing the extension of drift region 25.

[0219] A plurality of gate structures 15 may be formed at intervals on the first main surface 3. A plurality of source regions 20 may be formed along the plurality of gate structures 15. A plurality of drift regions 25 may be formed in a thickness range between the bottom of the second region 13 and the bottom wall of the gate structure 15, respectively.

[0220] According to this configuration, a current path connecting the first region 7 and the plurality of source regions 20 via the plurality of channels is formed by the plurality of drift regions 25. Furthermore, according to this configuration, in a configuration having the plurality of gate structures 15, the plurality of source regions 20, and the plurality of drift regions 25, the breakdown voltage can be improved.

[0221] The semiconductor device 1 may include a p-type high concentration region 30. The high concentration region 30 may be formed in the second region 13 on the side of the gate structure 15, and may have a p-type impurity concentration higher than the p-type impurity concentration of the second region 13. This configuration provides the semiconductor device 1 that can improve electrical characteristics.

[0222] For example, in this semiconductor device 1, the high concentration region 30 locally increases the p-type impurity concentration in the second region 13 near the gate structure 15, and suppresses an increase in the overall p-type impurity concentration in the second region 13. This allows the high concentration region 30 to reduce the electric field strength near the gate structure 15.

[0223] Furthermore, this configuration suppresses a decrease in the p-type impurity concentration of second region 13 on the side of gate structure 15, which is caused by the n-type impurity concentration of drift region 25. As a result, high-concentration region 30 can suppress the short-channel effect caused by the n-type impurity concentration of drift region 25 and the leakage current caused by the short-channel effect.

[0224] Furthermore, since the high concentration region 30 suppresses an increase in the overall p-type impurity concentration in the second region 13, it is possible to suppress a decrease in the n-type impurity concentration in the drift region 25 that would otherwise be caused by the high concentration in the second region 13. This makes it possible to suppress fluctuations in the electrical characteristics of the drift region 25.

[0225] The high concentration region 30 may be adjacent to the drift region 25 in a direction along the first main surface 3. The high concentration region 30 may be formed at an interval from the first main surface 3 toward the bottom of the second region 13. The high concentration region 30 may be formed at an interval from the bottom of the second region 13 toward the first main surface 3. The high concentration region 30 may have a portion located on the first main surface 3 side with respect to the depth position of the bottom wall of the gate structure 15. With this configuration, the short channel effect can be appropriately suppressed.

[0226] The high concentration region 30 may have a portion located on the bottom side of the second region 13 with respect to the depth position of the bottom wall of the gate structure 15. With this configuration, the electric field concentration on the bottom wall of the gate structure 15 can be appropriately alleviated.

[0227] In a cross-sectional view, the high concentration region 30 may extend in the thickness direction of the chip 2. According to this configuration, the high concentration region 30 extending in the thickness direction exerts an electric field relaxation effect and an effect of suppressing the short channel effect.

[0228] The high-concentration region 30 may be formed at a distance from the drift region 25. With this configuration, fluctuations in the electrical characteristics of the high-concentration region 30 due to the n-type impurity concentration of the drift region 25 can be suppressed, and at the same time, fluctuations in the electrical characteristics of the drift region 25 due to the p-type impurity concentration of the high-concentration region 30 can be suppressed.

[0229] The semiconductor device 1 may include a p-type contact region 21 formed in a surface layer portion of the second region 13 and having a p-type impurity concentration higher than the p-type impurity concentration of the second region 13. In this case, the high-concentration region 30 may be electrically connected to the contact region 21. With this configuration, the electrical response characteristics of the high-concentration region 30 can be improved by the contact region 21.

[0230] The high-concentration region 30 may be formed in a region that overlaps the contact region 21 in the thickness direction of the chip 2. The high-concentration region 30 may be formed wider than the contact region 21. The high-concentration region 30 may be directly connected to the contact region 21. The high-concentration region 30 may be formed at an interval from the contact region 21 on the bottom side of the second region 13, and may be electrically connected to the contact region 21 via a part of the second region 13.

[0231] From another perspective, the semiconductor device 1 includes a chip 2, an n-type (first conductivity type) first region 7, a p-type (second conductivity type) second region 13, a trench gate structure 15, an n-type drift region 25, and a p-type high-concentration region 30. The chip 2 has a first main surface 3. The first region 7 is formed in a surface layer portion of the first main surface 3 within the chip 2. The second region 13 is formed in a region within the chip 2 closer to the first main surface 3 than the first region 7.

[0232] The gate structure 15 is formed on the first main surface 3 and spaced apart from the bottom of the second region 13. The drift region 25 is formed in a thickness range between the bottom of the second region 13 and the bottom wall of the gate structure 15. The high concentration region 30 is formed in the second region 13 on the side of the gate structure 15, and has an impurity concentration higher than the impurity concentration of the second region 13.

[0233] This configuration makes it possible to provide a semiconductor device 1 having a novel layout. For example, in this semiconductor device 1, the high-concentration region 30 locally increases the p-type impurity concentration in the second region 13 near the gate structure 15, and the high-concentration region 30 suppresses an increase in the overall p-type impurity concentration in the second region 13. This allows the high-concentration region 30 to reduce the electric field strength near the gate structure 15.

[0234] Furthermore, this configuration suppresses a decrease in the p-type impurity concentration of second region 13 on the side of gate structure 15, which is caused by the n-type impurity concentration of drift region 25. As a result, high-concentration region 30 can suppress the short-channel effect caused by the n-type impurity concentration of drift region 25 and the leakage current caused by the short-channel effect.

[0235] Furthermore, since the high concentration region 30 suppresses an increase in the overall p-type impurity concentration in the second region 13, it is possible to suppress a decrease in the n-type impurity concentration in the drift region 25 that would otherwise be caused by the high concentration in the second region 13. This makes it possible to suppress fluctuations in the electrical characteristics of the drift region 25.

[0236] High concentration region 30 may have a portion facing drift region 25 in the direction along first main surface 3. According to this configuration, high concentration region 30 having a portion facing drift region 25 exerts an electric field relaxation effect and an effect of suppressing the short channel effect.

[0237] 9 is a schematic diagram showing a wafer 60 used in the manufacture of the semiconductor device 1. The wafer 60 is a base material for the chip 2 and includes a SiC single crystal. The wafer 60 is formed in a flat disk shape. Of course, the wafer 60 may also be formed in a flat rectangular parallelepiped shape. The wafer 60 has a first wafer main surface 61 on one side, a second wafer main surface 62 on the other side, and a wafer side surface 63 connecting the first wafer main surface 61 and the second wafer main surface 62.

[0238] The first wafer main surface 61 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 62 corresponds to the second main surface 4 of the chip 2. The first wafer main surface 61 and the second wafer main surface 62 are formed by the c-plane of the SiC single crystal. The first wafer main surface 61 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 62 is formed by the carbon surface of the SiC single crystal. The wafer 60 (the first wafer main surface 61 and the second wafer main surface 62) has the off-direction and off-angle described above.

[0239] The wafer 60 has a mark 64 on the wafer side surface 63 that indicates the crystal orientation of the SiC single crystal. The mark 64 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 61 in a plan view.

[0240] The mark 64 may include either or both of a first orientation flat extending in the a-axis direction and a second orientation flat extending in the m-axis direction. The mark 64 may include either or both of an orientation notch recessed in the a-axis direction and an orientation notch recessed in the m-axis direction.

[0241] The wafer 60 includes an n-type base region 6 formed in a surface layer portion of the second wafer main surface 62. The base region 6 is formed in a layer extending along the second wafer main surface 62 and is exposed from the second wafer main surface 62 and a wafer side surface 63. In this embodiment, the base region 6 is made of an n-type semiconductor wafer (SiC wafer) containing SiC single crystal (semiconductor single crystal), and has the off-direction and off-angle described above.

[0242] The wafer 60 includes an n-type first region 7 formed in a surface layer portion of the first wafer main surface 61. The first region 7 is formed in a layer shape extending along the first wafer main surface 61, and is exposed from the first wafer main surface 61 and a wafer side surface 63.

[0243] The first region 7 is made of an n-type epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal) and is stacked on the base region 6. That is, in this embodiment, the wafer 60 is made of an epitaxial wafer (so-called epi-wafer) having a stacked structure including a semiconductor wafer and an epitaxial layer. The first region 7 has the aforementioned off direction and off angle.

[0244] The wafer 60 includes a plurality of device regions 65 and a plurality of cutting lines 66. For example, the plurality of device regions 65 and the plurality of cutting lines 66 are defined by alignment marks or the like formed on the first wafer main surface 61 side. Each device region 65 is a region corresponding to a semiconductor device 1. The plurality of device regions 65 are each set to have a quadrangular shape in a plan view.

[0245] In this embodiment, the multiple device regions 65 are set in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 65 are set at intervals inward from the periphery of the first wafer main surface 61 in a plan view. The multiple cutting lines 66 are set in a grid pattern extending along the first direction X and the second direction Y to partition the multiple device regions 65.

[0246] 10A to 10N are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1. Each of the cross-sections of the region corresponding to that of FIG. 6 is shown in FIG. 10A. First, referring to FIG. 10A, the aforementioned wafer 60 (FIG. 9) is prepared.

[0247] 10B , second regions 13 are formed in the surface layer portion of the first wafer main surface 61. In this process, a mask (not shown) having a predetermined layout is first formed on the first wafer main surface 61. The mask (not shown) may have a single-layer structure or a multilayer structure including either or both of an inorganic mask and an organic mask (resist mask). The mask (not shown) exposes the region where the second regions 13 are to be formed and covers the other regions.

[0248] Next, p-type impurities are introduced into the first region 7 by ion implantation through a mask (not shown). The ion implantation may be either or both of channeling ion implantation and random ion implantation. In the channeling ion implantation process, the p-type impurities are introduced into the first region 7 along the axial channel of the first region 7 (wafer 60).

[0249] In the channeling ion implantation process, the p-type impurity is implanted deep into first region 7 while repeatedly undergoing small-angle scattering due to the channeling effect. That is, in the case of channeling implantation, the probability of the p-type impurity colliding with the atomic columns of the SiC single crystal is reduced. Therefore, the channeling ion implantation process is effective in forming a relatively deep second region 13.

[0250] On the other hand, in the random ion implantation process, p-type impurities are introduced into the first region 7 in a random direction. The random direction is a direction other than the axial channel of the first region 7 (i.e., a direction intersecting the axial channel). For example, the random direction is the vertical direction Z. In the random ion implantation process, the probability of collision of the p-type impurities with the atomic columns of the SiC single crystal is high, so the second region 13 is formed in a relatively shallow region. Therefore, the random ion implantation process is effective when forming a relatively shallow second region 13.

[0251] In this step, the p-type impurity is introduced into a region on the surface side of the first region 7, while leaving a region on the bottom side of the first region 7. The p-type impurity may be implanted into a single target depth range in the first region 7 (wafer 60) in one step. The p-type impurity may also be implanted into a plurality of different target depth ranges in the first region 7 (wafer 60) in multiple steps. As a result, the second region 13 is formed in the surface portion of the first wafer main surface 61.

[0252] 10C , a plurality of source regions 20 are formed in the surface layer portion of the first wafer main surface 61. In this process, a first mask 70 having a predetermined layout is first formed on the first wafer main surface 61. The first mask 70 may have a single-layer structure or a multilayer structure including either or both of an inorganic mask and an organic mask (resist mask). The first mask 70 exposes regions where the plurality of source regions 20 are to be formed and covers other regions.

[0253] Next, n-type impurities are introduced into the surface layer portion of the first wafer main surface 61 by ion implantation via the first mask 70. The ion implantation may be either or both of channeling ion implantation and random ion implantation. The ion implantation is preferably random ion implantation. As a result, a plurality of source regions 20 are formed in the surface layer portion of the first wafer main surface 61. The first mask 70 is then removed.

[0254] 10D , a plurality of contact regions 21 are formed in the surface layer portion of the first wafer main surface 61. In this process, a second mask 71 having a predetermined layout is first formed on the first wafer main surface 61. The second mask 71 may have a single-layer structure or a multilayer structure including either or both of an inorganic mask and an organic mask (resist mask). The second mask 71 exposes regions where the plurality of contact regions 21 are to be formed and covers the other regions.

[0255] Next, p-type impurities are introduced into the surface layer portion of the first wafer main surface 61 by ion implantation through the second mask 71. The ion implantation may be either or both of channeling ion implantation and random ion implantation. The ion implantation is preferably random ion implantation. As a result, a plurality of contact regions 21 are formed in the surface layer portion of the first wafer main surface 61. The second mask 71 is then removed.

[0256] In the process of forming the source regions 20, the n-type impurity may be formed over the entire surface layer portion of the first wafer main surface 61 without using the first mask 70. In this case, a base source region (20) that serves as a base for the multiple source regions 20 is formed over the entire surface layer portion of the first wafer main surface 61.

[0257] In the step of forming the contact region 21, p-type impurities are introduced into the surface layer portion of the first wafer main surface 61 by ion implantation via the second mask 71 so as to change the conductivity type of the base source region (20) from n-type to p-type. Of course, the order of the step of forming the source region 20 and the step of forming the contact region 21 may be reversed.

[0258] 10E , the second surface 9 and the plurality of trenches 16 are formed on the first wafer main surface 61. In this process, a third mask 72 having a predetermined layout is first formed on the first wafer main surface 61. The third mask 72 may have a single-layer structure or a multilayer structure including either or both of an inorganic mask and an organic mask (resist mask). The third mask 72 exposes the regions where the second surface 9 and the plurality of trenches 16 are to be formed and covers the other regions.

[0259] Next, unnecessary portions of the wafer 60 are removed by etching through the third mask 72. The etching method may be either wet etching or dry etching, or both. The etching method is preferably RIE (Reactive Ion Etching), which is an example of dry etching. This forms the second surface 9 and the plurality of trenches 16. In this process, the plurality of trenches 16 are formed substantially perpendicular to the first wafer main surface 61. The bottom walls of the plurality of trenches 16 are also formed flat.

[0260] 10F , multiple drift regions 25 are formed in wafer 60 (second region 13). In this process, first, a fourth mask 73 having a predetermined layout is formed on first wafer main surface 61. Fourth mask 73 may have a single-layer structure or a multilayer structure including either or both of an inorganic mask and an organic mask (resist mask). Fourth mask 73 exposes regions where multiple drift regions 25 are to be formed (i.e., multiple trenches 16) and covers other regions.

[0261] Next, n-type impurities are introduced into the second region 13 through the bottom walls of the trenches 16 by ion implantation using the fourth mask 73. The n-type impurities are introduced into a thickness range between the bottom walls of the trenches 16 and the bottom of the second region 13 so as to reach the first region 7. In this process, the n-type impurities are introduced so as to connect to the bottom walls of the trenches 16 and the bottom of the second region 13.

[0262] The ion implantation method may be either or both of a channeling ion implantation method and a random ion implantation method. The ion implantation method is preferably a random ion implantation method. The random ion implantation method may be either or both of a vertical ion implantation method and an oblique ion implantation method.

[0263] In the case of the vertical ion implantation method, the n-type impurity is introduced into the second region 13 at an implantation angle that is approximately perpendicular to the first wafer main surface 61. In the case of the oblique ion implantation method, the n-type impurity is introduced into the second region 13 at an implantation angle that is oblique to the first wafer main surface 61. In the case of the oblique ion implantation method, the n-type impurity is introduced into the second region 13 through the bottom walls of the plurality of trenches 16 and the lower ends of the sidewalls of the plurality of trenches 16.

[0264] The implantation angle of the n-type impurity relative to the vertical axis (0°) may be greater than 0° and less than or equal to 45°. The implantation angle may have a value belonging to at least one of the following ranges: greater than 0° and less than or equal to 5°, 5° to 10°, 10° to 15°, 15° to 20°, 20° to 25°, 25° to 30°, 30° to 35°, 35° to 40°, and 40° to 45°.

[0265] In the oblique ion implantation method, n-type impurities are implanted at positive and negative implantation angles relative to the vertical line. The positive and negative implantation angles are defined relative to each other. Therefore, when one side of the horizontal direction (first direction X in this embodiment) relative to the vertical line is defined as a positive implantation angle, the other side of the horizontal direction (first direction X in this embodiment) relative to the vertical line is defined as a negative implantation angle.

[0266] The n-type impurity may be implanted in a single step into a single target depth range in the second region 13 (wafer 60). The n-type impurity may be implanted in multiple steps into a plurality of different target depth ranges in the second region 13 (wafer 60).

[0267] The plurality of trenches 16 have flat bottom walls, which suppresses variations in the introduction depth of the n-type impurities caused by variations in the depth of the bottom walls of the trenches 16. This improves the accuracy of introduction of the n-type impurities into the second region 13, and appropriately forms the plurality of drift regions 25. This results in the formation of the plurality of drift regions 25.

[0268] 10G , a plurality of high-concentration regions 30 are formed inside the second region 13. In this process, p-type impurities are introduced into the second region 13 through the sidewalls of the plurality of trenches 16 at an implantation angle oblique to the first wafer main surface 61 by oblique ion implantation using a fourth mask 73. The p-type impurities are introduced into the regions between the plurality of trenches 16.

[0269] The implantation angle of the p-type impurity relative to the vertical axis (0°) may be greater than 0° and less than or equal to 45°. The implantation angle may have a value belonging to at least one of the following ranges: greater than 0° and less than or equal to 5°, 5° to 10°, 10° to 15°, 15° to 20°, 20° to 25°, 25° to 30°, 30° to 35°, 35° to 40°, and 40° to 45°.

[0270] In the oblique ion implantation method, p-type impurities are implanted at a positive implantation angle and a negative implantation angle with respect to the vertical line. The high concentration regions 30 according to the first to sixteenth embodiments (see FIGS. 7 and 8A to 8O) are formed by appropriately adjusting the implantation angle of the p-type impurities, the implantation energy of the p-type impurities, the opening width of the trenches 16, the depth of the trenches 16, the interval between the plurality of trenches 16 (gate pitch), the thickness of the fourth mask 73, and the like.

[0271] The p-type impurity may be implanted into a single target depth range in the second region 13 (wafer 60) in one step. The p-type impurity may also be implanted into a plurality of different target depth ranges in the second region 13 (wafer 60) in multiple steps. As a result, a plurality of high concentration regions 30 are formed in the second region 13 in the regions between the plurality of trenches 16.

[0272] The order of the step of forming the drift region 25 and the step of forming the high concentration region 30 is arbitrary. Therefore, the step of forming the drift region 25 may be performed after the step of forming the high concentration region 30. In this embodiment, the drift region 25 and the high concentration region 30 are formed using the fourth mask 73, but the drift region 25 and the high concentration region 30 may be formed using a plurality of masks having different materials and / or different thicknesses.

[0273] That is, while the drift region 25 is formed using the fourth mask 73, the high concentration regions 30 may be formed using a mask different from the fourth mask 73. When the multiple high concentration regions 30 are formed using a mask different from the fourth mask 73, the multiple high concentration regions 30 may be formed by introducing p-type impurities into the second region 13 (wafer 60) through the first wafer main surface 61.

[0274] In this case, a mask is formed that fills the trenches 16 and selectively exposes the first wafer main surface 61. P-type impurities are introduced into the second region 13 (wafer 60) by ion implantation through the mask. The ion implantation may be either or both of channeling ion implantation and random ion implantation.

[0275] 10H, a base insulating film 74 is formed on the first wafer main surface 61. The base insulating film 74 serves as a base for the plurality of insulating films 17 and the main surface insulating film 35. The base insulating film 74 collectively covers the first surface portion 8, the second surface portion 9, the first to fourth connecting surface portions 10A to 10D, and the wall surfaces of the plurality of trenches 16 in a film-like manner. The base insulating film 74 may be formed by either or both of a CVD method and an oxidation method (for example, a thermal oxidation method).

[0276] 10I, a first base electrode film 75 is formed on the base insulating film 74. The first base electrode film 75 serves as a base for the multiple buried electrodes 18. The first base electrode film 75 has a portion that covers the first wafer main surface 61 with the base insulating film 74 in between, and portions that are embedded in the multiple trenches 16 with the base insulating film 74 in between. The base insulating film 74 may be formed by a CVD method.

[0277] 10J, unnecessary portions of the first base electrode film 75 are removed by etching until the base insulating film 74 is exposed. The etching may be either wet etching or dry etching, or both. As a result, a plurality of buried electrodes 18 are formed. Also, a plurality of gate structures 15 are formed.

[0278] 10K, the interlayer film 36 is formed on the first wafer main surface 61 (specifically, the first base electrode film 75). The interlayer film 36 collectively covers the first surface 8, the second surface 9, the first to fourth connection surface portions 10A to 10D, and the plurality of gate structures 15. The interlayer film 36 may be formed by a CVD method.

[0279] 10L, a fifth mask 76 having a predetermined layout is formed on the interlayer film 36. The fifth mask 76 may be an organic mask (resist mask). The fifth mask 76 exposes regions where the source openings 37 and the gate openings 38 are to be formed and covers other regions. Next, unnecessary portions of the interlayer film 36 are removed by etching through the fifth mask 76. The etching may be either or both of wet etching and dry etching.

[0280] Next, unnecessary portions of the base insulating film 74 are removed by etching via the fifth mask 76. The etching method may be either wet etching or dry etching, or both. The unnecessary portions of the base insulating film 74 may be removed simultaneously with the interlayer film 36. As a result, a plurality of source openings 37 and a plurality of gate openings 38 are formed in the interlayer film 36. Furthermore, a plurality of insulating films 17 and a main surface insulating film 35 are formed. The fifth mask 76 is then removed.

[0281] 10M, a second base electrode film 77 is formed on the interlayer film 36. The second base electrode film 77 is a base for the source electrode 40, the gate electrode 45, and the gate wiring 46. The second base electrode film 77 has a layered structure including a lower electrode film 41 and a main electrode film 42. The lower electrode film 41 has a layered structure including a first electrode film 43 and a second electrode film 44.

[0282] The first electrode film 43 may be formed by either or both of a sputtering method and a vapor deposition method. The first electrode film 43 is formed in a film shape along the first wafer main surface 61, the interlayer film 36, the wall surfaces of the plurality of source openings 37, and the wall surfaces of the plurality of gate openings 38. The second electrode film 44 may be formed by either or both of a sputtering method and a vapor deposition method. The second electrode film 44 is stacked on the first electrode film 43 and is formed in a film shape along the first wafer main surface 61, the interlayer film 36, the wall surfaces of the plurality of source openings 37, and the wall surfaces of the plurality of gate openings 38.

[0283] The main electrode film 42 is formed on the lower electrode film 41. The main electrode film 42 may be formed by either or both of a sputtering method and a vapor deposition method. The main electrode film 42 is laminated on the lower electrode film 41 and is formed in a film shape along the first wafer main surface 61, the interlayer film 36, the wall surfaces of the plurality of source openings 37, and the wall surfaces of the plurality of gate openings 38.

[0284] Next, the second base electrode film 77 is divided into the source electrode 40, the gate electrode 45, and the gate wiring 46. In this process, a mask (not shown) having a predetermined layout is formed on the main electrode film 42. The mask (not shown) covers the regions where the source electrode 40, the gate electrode 45, and the gate wiring 46 are to be formed, and leaves the other regions exposed.

[0285] Next, unnecessary portions of the main electrode film 42 are removed by etching using a mask (not shown). The unnecessary portions of the main electrode film 42 are removed until the lower electrode film 41 is exposed. The etching method may be either or both of wet etching and dry etching. The mask (not shown) is removed after the etching step of the main electrode film 42.

[0286] Next, unnecessary portions of the lower electrode film 41 are removed by etching using the main electrode film 42 as a mask. The unnecessary portions of the lower electrode film 41 are removed until the interlayer film 36 is exposed. The step of removing the lower electrode film 41 includes a step of removing the second electrode film 44 by etching and a step of removing the first electrode film 43 by etching. The etching method may be either or both of wet etching and dry etching.

[0287] This forms the source electrode 40, the gate electrode 45, and the gate wiring 46. Of course, unnecessary portions of the lower electrode film 41 may be removed by etching using a mask (not shown) in the etching step of the main electrode film 42.

[0288] 10N, a drain electrode 47 is formed on the second wafer main surface 62. The drain electrode 47 may be formed by either or both of a sputtering method and a vapor deposition method. Thereafter, the wafer 60 is cut along the cutting lines 66 (see FIG. 9) to cut out a plurality of semiconductor devices 1. The semiconductor device 1 is manufactured through the steps including those described above.

[0289] 11 is an enlarged cross-sectional view showing a semiconductor device 1 according to a modified example. Referring to Fig. 11, the semiconductor device 1 includes a plurality of p-type high concentration regions 30 formed in regions along the sidewalls of the plurality of gate structures 15 in the second region 13. In this embodiment, the plurality of high concentration regions 30 are formed at intervals from one another in regions between the plurality of gate structures 15, and face one another with a portion of the second region 13 sandwiched therebetween.

[0290] The plurality of high-concentration regions 30 are formed on both sides of the plurality of gate structures 15, respectively, and face the corresponding buried electrodes 18 across the corresponding insulating films 17. The plurality of high-concentration regions 30 each extend in a strip shape in the second direction Y along the plurality of gate structures 15 in a plan view.

[0291] The multiple high-concentration regions 30 are formed in regions between the multiple source regions 20 and the multiple drift regions 25 in a cross-sectional view, respectively, and extend in the vertical direction Z along the sidewalls of the corresponding gate structures 15. That is, part or all of the channel of the transistor structure Tr is formed in the multiple high-concentration regions 30. The multiple high-concentration regions 30 are formed at intervals from adjacent gate structures 15 toward the corresponding gate structure 15, and face each other with part of the second region 13 sandwiched between them.

[0292] In this embodiment, the multiple high-concentration regions 30 are formed at intervals in the horizontal direction (first direction X) from the multiple contact regions 21, and are electrically connected to the multiple contact regions 21 via parts of the second region 13. Of course, the high-concentration regions 30 may be connected to the multiple contact regions 21.

[0293] The configuration of one high-concentration region 30 will be described below. The high-concentration region 30 has an upper end on the first surface 8 side and a lower end (bottom) on the bottom wall side of the gate structure 15. The upper end of the high-concentration region 30 may be located on the first surface 8 side relative to the depth position of the intermediate portion of the gate structure 15, or may be located on the bottom wall side of the gate structure 15 relative to the depth position of the intermediate portion of the gate structure 15.

[0294] In this embodiment, the upper end of the high concentration region 30 is connected to the source region 20. Of course, the upper end of the high concentration region 30 may be formed at a distance from the source region 20 toward the bottom wall of the gate structure 15. The lower end of the high concentration region 30 may be located on the first surface portion 8 side with respect to the depth position of the intermediate portion of the gate structure 15, or may be located on the bottom wall side of the gate structure 15 with respect to the depth position of the intermediate portion of the gate structure 15.

[0295] In this embodiment, the lower end of the high-concentration region 30 is connected to the drift region 25 (specifically, the upper end of the drift region 25). Of course, the lower end of the high-concentration region 30 may be formed at a distance from the drift region 25 (specifically, the upper end of the drift region 25) toward the first surface portion 8.

[0296] The high concentration region 30 may have an edge that protrudes outward (toward the adjacent gate structure 15) from the drift region 25. Of course, the edge of the high concentration region 30 may be located closer to the gate structure 15 than the drift region 25. The edge of the high concentration region 30 is preferably formed with a gap from the contact region 21 toward the corresponding gate structure 15. Of course, the edge of the high concentration region 30 may be connected to the contact region 21.

[0297] The above-described embodiments (including variations) can be implemented in other forms. For example, in the above-described embodiments, a structure may be adopted in which the conductivity type of an "n-type" semiconductor region is inverted to "p-type" and the conductivity type of a "p-type" semiconductor region is inverted to "n-type." A specific configuration in this case can be obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and accompanying drawings.

[0298] In the above-described embodiment, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. Similarly, the base region 6 may include a silicon single crystal. Similarly, the first region 7 may include a silicon single crystal.

[0299] In the above-described embodiment, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0300] Below, examples of features extracted from this specification and drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components of the above-mentioned embodiments, but are not intended to limit the scope of each clause to the above-mentioned embodiments. The "semiconductor device" in the following clauses may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," etc., as necessary.

[0301] [A1] A semiconductor device (1) including: a chip (2) having a main surface (3); a first region (7) of a first conductivity type (n-type) formed in the chip (2) in a surface layer portion of the main surface (3); a second region (13) of a second conductivity type (p-type) formed in a region of the chip (2) on the main surface (3) side relative to the first region (7); a trench-type gate structure (15) formed in the main surface (3) at a distance from a bottom of the second region (13); an impurity region (20) of the first conductivity type (n-type) formed in a surface layer portion of the main surface (3) along the gate structure (15); and a drift region (25) of the first conductivity type (n-type) formed in a thickness range between the bottom of the second region (13) and a bottom wall of the gate structure (15), which defines the impurity region (20) and a channel.

[0302] [A2] The semiconductor device (1) according to A1, wherein the chip (2) includes SiC.

[0303] [A3] The semiconductor device (1) according to A1 or A2, wherein the drift region (25) crosses the bottom of the second region (13) and is connected to the first region (7).

[0304] [A4] The semiconductor device (1) according to any one of A1 to A3, wherein the drift region (25) is connected to the bottom wall of the gate structure (15).

[0305] [A5] The semiconductor device (1) according to any one of A1 to A4, wherein the drift region (25) is formed wider than the gate structure (15).

[0306] [A6] The semiconductor device (1) according to any one of A1 to A5, wherein the drift region (25) has a depth less than the depth of the gate structure (15) when the depth position of the bottom wall of the gate structure (15) is used as a reference.

[0307] [A7] The semiconductor device (1) according to any one of A1 to A6, wherein the drift region (25) extends along the sidewall of the gate structure (15) toward the main surface (3) and has an extension formed at an interval from the impurity region (20) toward the bottom wall of the gate structure (15).

[0308] [A8] A semiconductor device (1) according to any one of A1 to A7, wherein a plurality of the gate structures (15) are formed on the main surface (3) at intervals, a plurality of the impurity regions (20) are formed along the plurality of the gate structures (15), and a plurality of the drift regions (25) are respectively formed in a thickness range between the bottom of the second region (13) and the bottom wall of the gate structure (15).

[0309] [A9] The semiconductor device (1) according to any one of A1 to A8, further comprising a high concentration region (30) of a second conductivity type (p-type) formed in the second region (13) on the side of the gate structure (15) and having an impurity concentration higher than the impurity concentration of the second region (13).

[0310] [A10] The semiconductor device (1) according to A9, wherein the high concentration region (30) is formed at an interval from the main surface (3) to the bottom side of the second region (13).

[0311] [A11] The semiconductor device (1) according to A9 or A10, wherein the high concentration region (30) is formed at an interval from the bottom of the second region (13) toward the main surface (3).

[0312] [A12] The semiconductor device (1) according to any one of A9 to A11, wherein the high concentration region (30) has a portion located on the main surface (3) side relative to the depth position of the bottom wall of the gate structure (15).

[0313] [A13] A semiconductor device (1) according to any one of A9 to A12, wherein the high concentration region (30) has a portion located on the bottom side of the second region (13) relative to the depth position of the bottom wall of the gate structure (15).

[0314] [A14] The semiconductor device (1) according to any one of A9 to A13, wherein the high concentration region (30) extends in the thickness direction of the chip (2) in a cross-sectional view.

[0315] [A15] The semiconductor device (1) according to any one of A9 to A14, further comprising a second conductivity type (p-type) contact region (21) formed in a surface layer portion of the second region (13) and having an impurity concentration higher than the impurity concentration of the second region (13), and the high concentration region (30) is electrically connected to the contact region (21).

[0316] [A16] The semiconductor device (1) according to A15, wherein the high concentration region (30) is formed in a region that overlaps the contact region (21) in the thickness direction of the chip (2).

[0317] [A17] The semiconductor device (1) according to A15 or A16, wherein the high concentration region (30) is formed wider than the contact region (21).

[0318] [A18] A semiconductor device (1) according to any one of A15 to A17, wherein the high concentration region (30) is formed at a distance from the contact region (21) toward the bottom side of the second region (13) and is electrically connected to the contact region (21) via a part of the second region (13).

[0319] [A19] A semiconductor device (1) comprising: a chip (2) having a main surface (3); a first region (7) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3) within the chip (2); a second region (13) of a second conductivity type (p-type) formed in a region of the chip (2) on the main surface (3) side relative to the first region (7); a trench-type gate structure (15) formed in the main surface (3) spaced from a bottom of the second region (13); a drift region (25) of the first conductivity type (n-type) formed in a thickness range between the bottom of the second region (13) and a bottom wall of the gate structure (15); and a high-concentration region (30) of a second conductivity type (p-type) formed in the second region (13) on the side of the gate structure (15) and having an impurity concentration higher than the impurity concentration of the second region (13).

[0320] [A20] The semiconductor device (1) according to A19, wherein the high concentration region (30) has a portion facing the drift region (25) in a direction along the main surface (3).

[0321] Although specific embodiments have been described in detail above, these are merely examples that clearly demonstrate the technical content. Various technical ideas extracted from this specification can be appropriately combined without being limited by the order of explanation in the specification or the order of the embodiment examples.

[0322] REFERENCE SIGNS LIST 1 semiconductor device 2 chip 3 first main surface 7 first region 13 second region 15 gate structure 20 source region 21 contact region 25 drift region 30 high concentration region

Claims

1. A chip having a main surface, A first region of a first conductivity type formed on the surface layer of the main surface within the chip, A second region of a second conductivity type formed in the region on the main surface side with respect to the first region within the chip, A trench-type gate structure formed on the main surface, spaced apart from the bottom of the second region, A first conductivity type impurity region formed on the surface layer of the main surface along the gate structure, A semiconductor device comprising: a drift region of a first conductivity type formed in a thickness range between the bottom of the second region and the bottom wall of the gate structure, which demarcates the impurity region and the channel.

2. The semiconductor device according to claim 1, wherein the chip includes SiC.

3. The semiconductor device according to claim 1, wherein the drift region crosses the bottom of the second region and is connected to the first region.

4. The semiconductor device according to claim 1, wherein the drift region is connected to the bottom wall of the gate structure.

5. The semiconductor device according to claim 1, wherein the drift region is formed to be wider than the gate structure.

6. The semiconductor device according to claim 1, wherein the drift region has a depth less than the depth of the gate structure, with reference to the depth position of the bottom wall of the gate structure.

7. The semiconductor device according to claim 1, wherein the drift region extends along the side wall of the gate structure toward the main surface and has an extension formed at a distance from the impurity region toward the bottom wall of the gate structure.

8. Multiple gate structures are formed on the main surface at intervals, Multiple impurity regions are formed along multiple gate structures, The semiconductor device according to claim 1, wherein a plurality of the drift regions are formed in the thickness range between the bottom of the second region and the bottom wall of the gate structure.

9. The semiconductor device according to any one of claims 1 to 8, further comprising a high-concentration region of a second conductivity type formed laterally to the gate structure within the second region and having an impurity concentration higher than that of the second region.

10. The semiconductor device according to claim 9, wherein the high-concentration region is formed with a gap between the main surface and the bottom side of the second region.

11. The semiconductor device according to claim 9, wherein the high-concentration region is formed with a gap between the bottom of the second region and the main surface.

12. The semiconductor device according to claim 9, wherein the high-concentration region has a portion located on the main surface side with respect to the depth position of the bottom wall of the gate structure.

13. The semiconductor device according to claim 9, wherein the high-concentration region has a portion located on the bottom side of the second region with respect to the depth position of the bottom wall of the gate structure.

14. The semiconductor device according to claim 9, wherein the high-concentration region extends in the thickness direction of the chip in a cross-sectional view.

15. The material further includes a second conductive contact region formed on the surface of the second region and having a higher impurity concentration than the impurity concentration of the second region, The semiconductor device according to claim 9, wherein the high-concentration region is electrically connected to the contact region.

16. The semiconductor device according to claim 15, wherein the high-concentration region is formed in a region that overlaps with the contact region in the thickness direction of the chip.

17. The semiconductor device according to claim 15, wherein the high-concentration region is formed to be wider than the contact region.

18. The semiconductor device according to claim 15, wherein the high-concentration region is formed with a gap between it and the bottom of the second region from the contact region and is electrically connected to the contact region via a part of the second region.

19. A chip having a main surface, A first region of a first conductivity type formed on the surface layer of the main surface within the chip, A second region of a second conductivity type formed in the region on the main surface side with respect to the first region within the chip, A trench-type gate structure formed on the main surface, spaced apart from the bottom of the second region, A drift region of the first conductivity type formed in the thickness range between the bottom of the second region and the bottom wall of the gate structure, A semiconductor device comprising: a high-concentration region of a second conductivity type formed laterally to the gate structure within the second region and having a higher impurity concentration than the impurity concentration of the second region.

20. The semiconductor device according to claim 19, wherein the high-concentration region has a portion facing the drift region in a direction along the main surface.