Semiconductor device

Abstract

This semiconductor device includes: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer part of the main surface; and a termination region of a second conductivity type formed in a surface layer part of the semiconductor region at an interval from the main surface in the thickness direction of the chip, at a peripheral edge part of the main surface.

Description

Semiconductor Devices

[0001] This application claims priority to Patent Application No. 2023-126932 filed with the Japan Patent Office on August 3, 2023, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device.

[0002] Patent Document 1 (US2008 / 0277669A1) discloses a semiconductor device having a termination structure in the peripheral region of a drift layer.

[0003] US Patent Application Publication No. 2008 / 0277669

[0004] SUMMARY The present disclosure provides a semiconductor device having a novel layout.

[0005] The present disclosure provides a semiconductor device including a chip having a main surface, a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface, and a termination region of a second conductivity type formed in the surface layer portion of the semiconductor region at a peripheral portion of the main surface and spaced apart from the main surface in a thickness direction of the chip.

[0006] The present disclosure provides a semiconductor device including a chip having a main surface, a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface, and a field region of a second conductivity type formed in the surface layer portion of the semiconductor region at a peripheral portion of the main surface and spaced apart from the main surface in the thickness direction of the chip.

[0007] The present disclosure provides a semiconductor device including a chip having a main surface, a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface, a trench formed in an inner portion of the main surface so as to be positioned within the semiconductor region, and a termination region of a second conductivity type formed in the surface layer portion of the semiconductor region at the periphery of the main surface and having a bottom positioned closer to the main surface than the depth position of the bottom wall of the trench.

[0008] The present disclosure provides a semiconductor device including a chip having a main surface, a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface, a trench formed in an inner portion of the main surface so as to be positioned within the semiconductor region, and a field region of a second conductivity type formed in the surface layer portion of the semiconductor region at the periphery of the main surface and having a bottom positioned closer to the main surface than the depth position of the bottom wall of the trench.

[0009] The present disclosure provides a semiconductor device including: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface; a trench structure formed in an inner portion of the main surface so as to be positioned within the semiconductor region; a well region of a second conductivity type formed in a surface layer portion of the semiconductor region so as to be positioned on the peripheral side of the main surface relative to the trench structure; and the termination region of the second conductivity type formed in the surface layer portion of the semiconductor region so as to be positioned on the peripheral side of the main surface relative to the well region.

[0010] The present disclosure provides a semiconductor device including a chip having a first surface portion and a second surface portion recessed in a thickness direction relative to the first surface portion, a semiconductor region of a first conductivity type formed in a surface layer portion of the second surface portion, and a termination region of a second conductivity type formed in the surface layer portion of the semiconductor region spaced apart from the second surface portion in the thickness direction of the chip.

[0011] The present disclosure provides a semiconductor device including a chip having a first surface portion and a second surface portion recessed in a thickness direction relative to the first surface portion, a semiconductor region of a first conductivity type formed in a surface layer portion of the second surface portion, and a field region of a second conductivity type formed in the surface layer portion of the semiconductor region in the second surface portion, spaced apart from the second surface portion in the thickness direction of the chip.

[0012] The above and further objects, features and advantages will become more apparent from the accompanying drawings and detailed description.

[0013] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing an example layout of a first main surface. FIG. 4 is an enlarged plan view showing a main portion of the first main surface shown in FIG. 3. FIG. 5 is an enlarged plan view showing a main portion of the first main surface shown in FIG. 3. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is an enlarged cross-sectional view of one region shown in FIG. 6. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 5. FIG. 10A is a cross-sectional view showing the cross-sectional structure of the peripheral region taken along line XX in FIG. 1, together with the peripheral structure according to the first embodiment. FIG. 10B is a cross-sectional view showing the cross-sectional structure of the peripheral region taken along line XX in FIG. 1, together with the peripheral structure according to a second embodiment. FIG. 10C is a cross-sectional view showing the cross-sectional structure of the peripheral region taken along line XX in FIG. 1, together with the peripheral structure according to a third embodiment. 10D is a cross-sectional view showing the cross-sectional structure of the outer periphery region along the X-X line shown in FIG. 1 , together with the outer periphery structure according to the fourth embodiment. FIG. 10E is a cross-sectional view showing the cross-sectional structure of the outer periphery region along the X-X line shown in FIG. 1 , together with the outer periphery structure according to the fifth embodiment. FIG. 11A is a cross-sectional view showing the first outer periphery structure according to the first modified example. FIG. 11B is a cross-sectional view showing the first outer periphery structure according to the second modified example. FIG. 11C is a cross-sectional view showing the first outer periphery structure according to the third modified example. FIG. 11D is a cross-sectional view showing the first outer periphery structure according to the fourth modified example. FIG. 11E is a cross-sectional view showing the first outer periphery structure according to the fifth modified example. FIG. 11F is a cross-sectional view showing the first outer periphery structure according to the sixth modified example. FIG. 11G is a cross-sectional view showing the first outer periphery structure according to the seventh modified example. FIG. 11H is a cross-sectional view showing the first outer periphery structure according to the eighth modified example. FIG. 11I is a cross-sectional view showing the first outer periphery structure according to the ninth modified example. FIG. 11J is a cross-sectional view showing the first outer periphery structure according to the tenth modified example. Fig. 12A is a cross-sectional view showing a second outer periphery structure according to a first modified example. Fig. 12B is a cross-sectional view showing a second outer periphery structure according to a second modified example. Fig. 12C is a cross-sectional view showing a second outer periphery structure according to a third modified example. Fig. 12D is a cross-sectional view showing a second outer periphery structure according to a fourth modified example. Fig. 12E is a cross-sectional view showing a second outer periphery structure according to a fifth modified example. Fig. 12F is a cross-sectional view showing a second outer periphery structure according to a sixth modified example.FIG. 12G is a cross-sectional view showing a second periphery structure according to a seventh modification. FIG. 12H is a cross-sectional view showing a second periphery structure according to an eighth modification. FIG. 12I is a cross-sectional view showing a second periphery structure according to a ninth modification. FIG. 12J is a cross-sectional view showing a second periphery structure according to a tenth modification. FIG. 13 is a cross-sectional view showing a main portion of an active region of a semiconductor device according to a second embodiment. FIG. 14 is a cross-sectional view showing a main portion of an active region of the semiconductor device shown in FIG. 13. FIG. 15 is a cross-sectional view showing the periphery region of the semiconductor device shown in FIG. 13 together with the periphery structure according to the first embodiment. FIG. 16 is an enlarged plan view showing a main portion of an active region of a semiconductor device according to a third embodiment. FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 16. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 16. FIG. 19 is a cross-sectional view showing a main portion of the active region of the semiconductor device shown in FIG. 16. FIG. 20 is a plan view showing a semiconductor device according to a fourth embodiment. 21 is a cross-sectional view taken along line XXI-XXI in FIG. 20 . FIG. 22 is a perspective view showing the shape of a chip. FIG. 23 is a plan view showing an example layout of the first main surface. FIG. 24 is an enlarged plan view showing a main portion of the first main surface shown in FIG. 23 . FIG. 25 is an enlarged plan view showing a main portion of the first main surface shown in FIG. 23 . FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 25 . FIG. 27 is a cross-sectional view showing the cross-sectional structure of the peripheral region taken along line XXVII-XXVII in FIG. 20 , together with the peripheral structure according to the first embodiment. FIG. 28 is a cross-sectional view showing a main portion of the active region of a semiconductor device according to the fifth embodiment. FIG. 29 is a cross-sectional view showing a main portion of the active region of the semiconductor device shown in FIG. 28 . FIG. 30 is a cross-sectional view showing the peripheral region of the semiconductor device shown in FIG. 28 , together with the peripheral structure according to the first embodiment. FIG. 31 is an enlarged plan view showing the active region of a semiconductor device according to the sixth embodiment. FIG. 32 is a cross-sectional view taken along line XXXII-XXXII in FIG. 31 . Fig. 33 is a cross-sectional view taken along line XXXIII-XXXIII shown in Fig. 31. Fig. 34 is a cross-sectional view showing a main part of the active region of the semiconductor device shown in Fig. 31. Fig. 35 is a plan view showing a semiconductor device according to a seventh embodiment. Fig. 36 is a cross-sectional view taken along line XXXVI-XXXVI shown in Fig. 35. Fig. 37 is a plan view showing an example layout of the first main surface.Fig. 38 is an enlarged plan view showing a main part of the first main surface shown in Fig. 37. Fig. 39 is a cross-sectional view taken along line XXXIX-XXXIX shown in Fig. 38. Fig. 40 is an enlarged cross-sectional view of one region shown in Fig. 39. Fig. 41 is a cross-sectional view showing the cross-sectional structure taken along line XLI-XLI shown in Fig. 35 together with the peripheral structure according to the first embodiment.

[0014] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0015] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0016] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type."

[0017] "P-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0018] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a first main surface 3. Fig. 4 is an enlarged plan view showing a main portion of the first main surface 3 shown in Fig. 3. Fig. 5 is an enlarged plan view showing a main portion of the first main surface 3 shown in Fig. 3.

[0019] Fig. 6 is a cross-sectional view taken along line VI-VI shown in Fig. 4. Fig. 7 is a cross-sectional view taken along line VII-VII shown in Fig. 4. Fig. 8 is an enlarged cross-sectional view of a region shown in Fig. 6. Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 5.

[0020] 1 to 9, a semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0021] Semiconductor device 1A includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1A is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0022] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1A is a "SiC semiconductor device."

[0023] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0024] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0025] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0026] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0027] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0028] Hereinafter, the direction extending along the first main surface 3 may be referred to as the “horizontal direction.” The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.

[0029] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle from a vertical line along the vertical direction Z toward the off-direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off-angle with respect to the horizontal plane.

[0030] The off-direction is preferably the a-axis direction of the SiC single crystal (second direction Y in this embodiment). The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0031] The off angle is preferably 5° or less. The off angle is particularly preferably 2° or more and 4.5° or less. The off angle is typically set in the range of 4°±0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0032] The semiconductor device 1A includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4. A drain potential as a first potential (high potential) is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as a "base region (layer)," a "semiconductor region (layer)," a "drain region (layer)," or the like.

[0033] The first semiconductor region 6 extends in a layered form along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has the off direction and off angle described above.

[0034] The first semiconductor region 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor region 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0035] The semiconductor device 1A includes an n-type second semiconductor region 7 formed in a surface layer portion of the first main surface 3. The second semiconductor region 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor region 7 has an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6. The second semiconductor region 7 is formed in a region closer to the first main surface 3 than the first semiconductor region 6 in a cross-sectional view, and is electrically connected to the first semiconductor region 6.

[0036] The second semiconductor region 7 extends in a layered form along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal), and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0037] The second semiconductor region 7 (epitaxial layer) has the off direction and off angle described above. The second semiconductor region 7 preferably has a thickness less than that of the first semiconductor region 6. Of course, the thickness of the second semiconductor region 7 may be greater than that of the first semiconductor region 6.

[0038] The thickness of the second semiconductor region 7 may be 5 μm or more and 15 μm or less. The thickness of the second semiconductor region 7 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0039] The semiconductor device 1A includes an active region 8 set in a chip 2. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in an inner portion of the chip 2 at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).

[0040] The active region 8 is set to a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The ratio (area ratio) of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and 0.95 or less.

[0041] The semiconductor device 1A includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include a device structure (transistor structure Tr). The peripheral region 9 is set on the periphery of the chip 2.

[0042] That is, in plan view, the peripheral region 9 is provided in the region between the periphery of the chip 2 and the active region 8. In plan view, the peripheral region 9 extends in a strip shape along the active region 8 and is set in the shape of a polygonal ring (a square ring in this embodiment) surrounding the active region 8.

[0043] The semiconductor device 1A includes a p-type body region 10 formed in a surface layer portion of the first main surface 3, in an inner portion of the first main surface 3. The body region 10 may also be referred to as an "impurity region," a "channel region," or the like.

[0044] The body region 10 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential.

[0045] The body region 10 is formed in a surface layer portion of the second semiconductor region 7. The body region 10 is formed in an inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The body region 10 is formed in the active region 8, but is not formed in the peripheral region 9. In this embodiment, the body region 10 is formed over the entire active region 8.

[0046] The body region 10 is formed at a distance from the bottom of the second semiconductor region 7 (the first semiconductor region 6) toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. In other words, the body region 10 is formed in a region on the first main surface 3 side of the second semiconductor region 7 in a cross-sectional view, and is electrically connected to the second semiconductor region 7.

[0047] In other words, the body region 10 is formed in a thickness range between the first major surface 3 and the second semiconductor region 7 in a cross-sectional view, and forms a pn junction with the second semiconductor region 7. The bottom of the body region 10 is located closer to the first major surface 3 than the depth position of the intermediate portion of the second semiconductor region 7.

[0048] The semiconductor device 1A includes an n-type source region 11 formed in a surface layer portion of the first main surface 3 in an inner portion of the first main surface 3. A source potential is applied to the source region 11. The source region 11 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The n-type impurity concentration of the source region 11 is higher than the p-type impurity concentration of the body region 10.

[0049] The source region 11 is formed in the inner part of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The source region 11 is formed in the active region 8, and is not formed in the peripheral region 9.

[0050] The source region 11 is formed in a surface layer portion of the body region 10 at a distance from the bottom of the body region 10 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the body region 10. In other words, the source region 11 is formed in a thickness range between the first main surface 3 and the body region 10 in a cross-sectional view.

[0051] That is, the source region 11 is formed in a region on the first main surface 3 side of the body region 10 in a cross-sectional view, and is electrically connected to the body region 10. The source region 11 may be formed at an interval inward from the periphery of the body region 10 in a plan view. The source region 11 extends in a layer shape along the first main surface 3.

[0052] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures 15 formed in an inner portion of the first main surface 3. The gate structures 15 may also be referred to as "trench structures," "trench gate structures," or the like. A gate potential (gate signal) serving as a control potential is applied to the plurality of gate structures 15. The plurality of gate structures 15 controls inversion and non-inversion of the channel in the body region 10 in response to the gate potential.

[0053] The plurality of gate structures 15 are formed in the inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The plurality of gate structures 15 are formed in the active region 8, and are not formed in the peripheral region 9.

[0054] The multiple gate structures 15 are arranged at intervals in a first direction X (=m-axis direction) in a plan view, and each extends in a strip shape in a second direction Y (=a-axis direction). That is, the multiple gate structures 15 are arranged in a stripe shape extending in the second direction Y in a plan view. The extending direction of the multiple gate structures 15 coincides with the off-direction of the SiC single crystal.

[0055] Of course, the multiple gate structures 15 may be arranged at intervals in the second direction Y in a plan view and may each extend in a strip shape in the first direction X. With respect to the second direction Y, both ends of the multiple gate structures 15 may be located in a region between the periphery of the body region 10 and the periphery of the source region 11.

[0056] When the gate pitch is defined as the distance in the horizontal direction (first direction X) between the centers of the plurality of gate structures 15, the gate pitch may be 1 μm or more and 5 μm or less. The gate pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0057] The plurality of gate structures 15 penetrates the body region 10 and the source region 11 to reach the second semiconductor region 7. The plurality of gate structures 15 are formed at intervals from the depth position of the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0058] In this embodiment, the plurality of gate structures 15 are formed substantially perpendicular to the first main surface 3. Of course, the plurality of gate structures 15 may also be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0059] The side walls (long sides) of the plurality of gate structures 15 are each formed by the m-plane ((1-100) plane) of the SiC single crystal. Of course, the side walls (long sides) of the plurality of gate structures 15 may each be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 15. The side walls of the plurality of gate structures 15 are formed approximately perpendicular to the first main surface 3.

[0060] The bottom walls of the gate structures 15 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the gate structures 15 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the gate structures 15 may be curved in an arc shape toward the second main surface 4.

[0061] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 15 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0062] The gate structure 15 may have a width of 0.1 μm to 2 μm, and may have a width in at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0063] The depth of the gate structure 15 may be 0.1 μm or more and 3 μm or less. The depth of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less.

[0064] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0065] Each of the plurality of gate structures 15 includes a first trench 16, a first insulating film 17, and a first buried electrode 18. The first trench 16 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 15.

[0066] The first insulating film 17 covers the wall surface of the first trench 16. The first insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 17 includes a silicon oxide film made of an oxide of the chip 2.

[0067] The first insulating film 17 includes a first film portion and a second film portion. The first film portion coats the sidewall of the first trench 16 in a film-like manner. The second film portion coats the bottom wall of the first trench 16 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to that of the first film portion.

[0068] The first insulating film 17 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0069] The first buried electrode 18 is buried in the first trench 16 with the first insulating film 17 sandwiched therebetween. The first buried electrode 18 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The first buried electrode 18 faces the second semiconductor region 7, the body region 10, and the source region 11 with the first insulating film 17 sandwiched therebetween.

[0070] The first buried electrode 18 has an electrode surface exposed from the first trench 16. The electrode surface of the first buried electrode 18 is located closer to the bottom wall of the first trench 16 with respect to the height position of the first main surface 3. The electrode surface of the first buried electrode 18 is located closer to the first main surface 3 with respect to the depth position of the bottom of the source region 11. The electrode surface of the first buried electrode 18 has a recess in an inner portion that tapers toward the bottom wall of the first trench 16.

[0071] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) source structures 20 formed in an inner portion of the first main surface 3. The source structures 20 may be referred to as "first source structures," "first trench source structures," "second trench structures," etc. A source potential is applied to the plurality of source structures 20.

[0072] The plurality of source structures 20 are formed in the inner part of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The source structures 20 are formed in the active region 8, and are not formed in the peripheral region 9.

[0073] The plurality of source structures 20 penetrate the body region 10 and the source region 11 to reach the second semiconductor region 7. The plurality of source structures 20 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0074] In this embodiment, the source structures 20 are formed substantially perpendicular to the first main surface 3. Of course, the source structures 20 may be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0075] The source structures 20 are respectively arranged in regions between the gate structures 15 at intervals from the gate structures 15 in the first direction X, and face the gate structures 15 in the first direction X.

[0076] That is, the source structures 20 are arranged alternately with the gate structures 15 in the first direction X in a plan view, and each extends in a strip shape in the second direction Y. That is, the source structures 20 are arranged in a stripe shape extending in the second direction Y. The extending direction of the source structures 20 coincides with the off-direction of the SiC single crystal.

[0077] Of course, the source structures 20 may be arranged at intervals in the second direction Y according to the extending direction of the gate structures 15, and may extend in a strip shape in the first direction X. With respect to the second direction Y, both ends of the source structures 20 may be located in a region between the peripheral edge of the body region 10 and the peripheral edge of the source region 11.

[0078] When the distance between the centers of the plurality of source structures 20 in the horizontal direction (first direction X) is defined as the source pitch, the source pitch is preferably approximately equal to the gate pitch of the plurality of gate structures 15. Of course, the source pitch may be larger than the gate pitch or smaller than the gate pitch.

[0079] The source pitch may be 1 μm or more and 5 μm or less. The source pitch may have a value belonging to at least one of the ranges of 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0080] When the horizontal distance between the center of the gate structure 15 and the center of the source structure 20 is defined as the trench pitch, the trench pitch may be 0.25 μm or more and 2.5 μm or less.

[0081] The trench pitch may have a value belonging to at least one of the ranges of 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, and 2.25 μm to 2.5 μm.

[0082] The sidewalls of the plurality of source structures 20 are each formed by the m-plane ((1-100) plane) of the SiC single crystal. Of course, the sidewalls of the plurality of source structures 20 may each be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the source structures 20. The sidewalls of the plurality of source structures 20 are formed approximately perpendicular to the first main surface 3.

[0083] The bottom walls of the source structures 20 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the source structures 20 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the source structures 20 may be curved in an arc shape toward the second main surface 4.

[0084] The inclination angle (absolute value) of the sidewall of the source structure 20 relative to the vertical line may be 85° to 95°. The inclination angle may have a value belonging to at least one of the ranges of 85° to 87.5°, 87.5° to 90°, 90° to 92.5°, and 92.5° to 95°. The inclination angle is preferably 87° to 93°.

[0085] The source structure 20 has a width that is approximately equal to the width of the gate structure 15. Of course, the width of the source structure 20 may be greater than the width of the gate structure 15 or may be less than the width of the gate structure 15.

[0086] The width of source structure 20 may be 0.1 μm to 2 μm, or may have a value belonging to at least one of the following ranges: 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0087] The depth of the source structure 20 is approximately equal to the depth of the gate structure 15. Of course, the depth of the source structure 20 may be greater than the depth of the gate structure 15 or less than the depth of the gate structure 15.

[0088] The ratio (depth ratio) of the depth of source structure 20 to the depth of gate structure 15 is preferably 0.8 to 1.2. The depth ratio may have a value belonging to at least one of the ranges of 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, 0.95 to 1, 1 to 1.05, 1.05 to 1.1, 1.1 to 1.15, and 1.15 to 1.2. The depth ratio is preferably 0.95 to 1.05.

[0089] The depth of the source structure 20 may be 0.1 μm or more and 3 μm or less. The depth of the source structure 20 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the source structure 20 is preferably 0.5 μm or more and 1.5 μm or less.

[0090] The source structure 20 may have an aspect ratio of 1 to 3, inclusive. The aspect ratio of the source structure 20 is the ratio of the depth of the source structure 20 to the width of the source structure 20. The aspect ratio may have a value belonging to at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3, inclusive. Preferably, the aspect ratio is 1.5 to 2.5, inclusive.

[0091] Each of the plurality of source structures 20 includes a second trench 21, a second insulating film 22, and a second buried electrode 23. The second trench 21 is formed in the first main surface 3 and defines the wall surfaces (sidewalls and bottom wall) of the source structure 20.

[0092] The second insulating film 22 covers the wall surface of the second trench 21. The second insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating film 22 preferably includes the same type of insulating material as the insulating material of the first insulating film 17. In this embodiment, the second insulating film 22 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 22 includes a silicon oxide film made of an oxide of the chip 2.

[0093] The second insulating film 22 includes a first film portion and a second film portion. The first film portion coats the sidewall of the second trench 21 in a film-like manner. The second film portion coats the bottom wall of the second trench 21 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.

[0094] The thickness of the first film portion of the second insulating film 22 may be approximately equal to the thickness of the first film portion of the first insulating film 17. The thickness of the second film portion of the second insulating film 22 may be approximately equal to the thickness of the second film portion of the first insulating film 17.

[0095] The second insulating film 22 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0096] The second buried electrode 23 is buried in the second trench 21 with the second insulating film 22 sandwiched therebetween. The second buried electrode 23 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The second buried electrode 23 preferably contains the same type of conductive material as the conductive material of the first buried electrode 18. The second buried electrode 23 faces the second semiconductor region 7, the body region 10, and the source region 11 with the second insulating film 22 sandwiched therebetween.

[0097] The second buried electrode 23 has an electrode surface exposed from the second trench 21. The electrode surface of the second buried electrode 23 is located on the bottom wall side of the second trench 21 with respect to the height position of the first main surface 3. The electrode surface of the second buried electrode 23 is located on the first main surface 3 side with respect to the depth position of the bottom of the source region 11.

[0098] The electrode surface of the second buried electrode 23 has a recess in an inner portion that tapers toward the bottom wall side of the second trench 21. Of course, the second buried electrode 23 may be buried on the bottom wall side of the second trench 21 with respect to the depth position of the bottom of the source region 11 so as not to face the source region 11 across the second insulating film 22.

[0099] The semiconductor device 1A includes one or more trench-type (trench electrode-type) dummy structures 25 formed in an inner portion of the first main surface 3. The dummy structures 25 may be referred to as a "second source structure," a "second trench source structure," a "third trench structure," a "dummy trench structure," a "periphery structure," or the like. The number of dummy structures 25 is arbitrary.

[0100] The number of dummy structures 25 may be 1 or more and 15 or less. The number of dummy structures 25 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. The number of dummy structures 25 is typically 1 or more and 10 or less. In this embodiment, the semiconductor device 1A includes five dummy structures 25, as an example.

[0101] One or more dummy structures 25 may be formed in an electrically floating state. One or more dummy structures 25 may be applied with a source potential. The multiple dummy structures 25 may be formed in an electrically floating state, or may be fixed to the source potential. Of course, the multiple dummy structures 25 may include one or more dummy structures 25 formed in an electrically floating state and one or more dummy structures 25 to which a source potential is applied.

[0102] The plurality of dummy structures 25 are formed in the inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The dummy structures 25 are formed in the active region 8, and are not formed in the peripheral region 9.

[0103] The plurality of dummy structures 25 are arranged on the periphery of the active region 8 at intervals from a group of structures including the plurality of gate structures 15 and the plurality of source structures 20. The plurality of dummy structures 25 are arranged at intervals from one another on the periphery of the active region 8 and are adjacent to one another in the horizontal direction.

[0104] The plurality of dummy structures 25 are each formed in a strip shape extending along the periphery of the active region 8 in a plan view. The plurality of dummy structures 25 extend in the extension direction (second direction Y) of the plurality of gate structures 15 (plurality of source structures 20).

[0105] The plurality of dummy structures 25 extend in a direction (first direction X) that intersects (specifically, is perpendicular to) the extending direction of the plurality of gate structures 15 (plurality of source structures 20). The plurality of dummy structures 25 may be formed in a polygonal ring (quadrilateral ring) that collectively surrounds a group of structures including the plurality of gate structures 15 and the plurality of source structures 20 in plan view.

[0106] In this embodiment, the plurality of dummy structures 25 are formed in a region outside the source region 11 and penetrate only the body region 10. Of course, in this embodiment, the plurality of dummy structures 25 penetrate the body region 10 and the source region 11 so as to reach the second semiconductor region 7.

[0107] The plurality of dummy structures 25 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 across a part of the second semiconductor region 7. In this embodiment, the plurality of dummy structures 25 are formed substantially perpendicular to the first main surface 3. Of course, the plurality of dummy structures 25 may be formed in a tapered shape toward the bottom of the second semiconductor region 7.

[0108] When the distance between the centers of the multiple dummy structures 25 in the horizontal direction (first direction X) is defined as the dummy pitch, the dummy pitch is preferably less than the trench pitch of the gate structures 15 and the source structures 20. Of course, the dummy pitch may be approximately equal to the trench pitch or may be greater than the trench pitch.

[0109] The dummy pitch may be 0.25 μm or more and 2.5 μm or less. The dummy pitch may have a value belonging to at least one of the ranges of 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, and 2.5 μm or more and 2.5 μm or less.

[0110] The side walls of the plurality of dummy structures 25 are formed by the m-plane ((1-100) plane) of the SiC single crystal and the a-plane ((11-20) plane) of the SiC single crystal, respectively. The side walls of the plurality of dummy structures 25 are formed substantially perpendicular to the first main surface 3.

[0111] The bottom walls of the plurality of dummy structures 25 are formed by the c-plane (Si-plane) of the SiC single crystal. The bottom walls of the plurality of dummy structures 25 preferably extend substantially flat in the horizontal direction. Of course, the bottom walls of the plurality of dummy structures 25 may be curved in an arc shape toward the second main surface 4.

[0112] The inclination angle (absolute value) of the sidewall of the dummy structure 25 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0113] The dummy structures 25 may have a width that is approximately equal to the width of the gate structures 15. The width of the dummy structures 25 may be greater than or less than the width of the gate structures 15. The width of the dummy structures 25 may be approximately equal to the width of the source structures 20. The width of the dummy structures 25 may be greater than or less than the width of the source structures 20.

[0114] The width of the dummy structure 25 may be 0.1 μm or more and 2 μm or less. The width of the dummy structure 25 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0115] The dummy structure 25 preferably has a depth that is approximately equal to the depth of either or both of the gate structure 15 and the source structure 20. The depth of the dummy structure 25 may be greater than the depth of the gate structure 15 or less than the depth of the gate structure 15. The depth of the dummy structure 25 may be greater than the depth of the source structure 20 or less than the depth of the source structure 20. In this embodiment, the depth of the dummy structure 25 is approximately equal to the depth of both the gate structure 15 and the source structure 20.

[0116] The ratio (depth ratio) of the depth of the dummy structure 25 to the depth of the gate structure 15 (source structure 20) is preferably 0.8 to 1.2. The depth ratio may have a value belonging to at least one of the ranges of 0.8 to 0.85, 0.85 to 0.9, 0.9 to 0.95, 0.95 to 1, 1 to 1.05, 1.05 to 1.1, 1.1 to 1.15, and 1.15 to 1.2. The depth ratio is preferably 0.95 to 1.05.

[0117] The depth of the dummy structure 25 may be 0.1 μm or more and 3 μm or less. The depth of the dummy structure 25 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the dummy structure 25 is preferably 0.5 μm or more and 1.5 μm or less.

[0118] The dummy structure 25 may have an aspect ratio of 1 to 3. The aspect ratio of the dummy structure 25 is the ratio of the depth of the dummy structure 25 to the width of the dummy structure 25. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0119] Each of the plurality of dummy structures 25 includes a third trench 26, a third insulating film 27, and a third buried electrode 28. The third trench 26 is formed in the first main surface 3, and defines the wall surfaces (side walls and bottom wall) of the dummy structure 25.

[0120] The third insulating film 27 covers the wall surface of the third trench 26. The third insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0121] The third insulating film 27 preferably contains the same type of insulating material as the insulating material of the first insulating film 17. In this embodiment, the third insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the third insulating film 27 contains a silicon oxide film made of an oxide of the chip 2.

[0122] The third insulating film 27 includes a first film portion and a second film portion. The first film portion coats the sidewall of the third trench 26 in a film-like manner. The second film portion coats the bottom wall of the third trench 26 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.

[0123] The thickness of the first film portion of the third insulating film 27 may be approximately equal to the thickness of the first film portion of the first insulating film 17. The thickness of the second film portion of the third insulating film 27 may be approximately equal to the thickness of the second film portion of the first insulating film 17.

[0124] The third insulating film 27 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0125] The third buried electrode 28 is buried in the third trench 26 with a third insulating film 27 sandwiched therebetween. The third buried electrode 28 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The third buried electrode 28 preferably contains the same type of conductive material as the conductive material of the first buried electrode 18.

[0126] The third buried electrode 28 faces the second semiconductor region 7 and the body region 10 with the third insulating film 27 interposed therebetween. Of course, the third buried electrode 28 may have a portion facing the source region 11.

[0127] The third buried electrode 28 has an electrode surface exposed from the third trench 26. The electrode surface of the third buried electrode 28 is located on the bottom wall side of the third trench 26 with respect to the height position of the first main surface 3. The electrode surface of the third buried electrode 28 is located on the first main surface 3 with respect to the depth position of the bottom of the source region 11.

[0128] The electrode surface of the third buried electrode 28 has a recess in an inner portion that tapers toward the bottom wall side of the third trench 26. Of course, the third buried electrode 28 may be buried on the bottom wall side of the third trench 26 with respect to the depth position of the bottom of the source region 11.

[0129] The semiconductor device 1A includes a plurality of well regions 30 formed in the chip 2 (second semiconductor region 7) in the active region 8. The plurality of well regions 30 may also be referred to as "trench well regions."

[0130] The multiple well regions 30 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the multiple well regions 30 may be higher than the p-type impurity concentration of the body region 10 or may be lower than the p-type impurity concentration of the body region 10.

[0131] The multiple well regions 30 include multiple gate well regions 30g, multiple source well regions 30s, and one or multiple (multiple in this embodiment) dummy well regions 30d. The gate well region 30g may be referred to as a "first well region" or the like, the source well region 30s may be referred to as a "second well region" or the like, and the dummy well region 30d may be referred to as a "third well region" or the like.

[0132] The multiple gate well regions 30g are formed at intervals from one another in the horizontal direction (first direction X) in regions directly below the multiple gate structures 15. The multiple gate well regions 30g are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple gate structures 15, and overlap the multiple gate structures 15 in a one-to-one correspondence in the thickness direction.

[0133] The multiple gate well regions 30g each extend in a strip shape in the second direction Y in plan view, following the extension direction of the corresponding gate structure 15. That is, the multiple gate well regions 30g are arranged in a stripe shape extending in the second direction Y in plan view. The extension direction of the multiple gate well regions 30g coincides with the off-direction of the SiC single crystal.

[0134] Of course, the multiple gate well regions 30g may extend in the first direction X in accordance with the extending direction of the multiple gate structures 15. In this case, the multiple gate well regions 30g intersect (specifically, are perpendicular to) the off direction.

[0135] The multiple gate well regions 30g are formed at intervals inward from the periphery (the multiple dummy structures 25) of the active region 8. In the second direction Y, both ends of the multiple gate well regions 30g may be located inward of both ends of the multiple gate structures 15, or may be located closer to the periphery of the active region 8 than both ends of the multiple gate structures 15.

[0136] When the distance between the centers of the plurality of gate well regions 30g in the horizontal direction (first direction X) is defined as the gate well pitch, the gate well pitch is approximately equal to the gate pitch of the plurality of gate structures 15. Of course, the gate well pitch may be larger than the gate pitch or smaller than the gate pitch.

[0137] The gate well region 30g may be approximately equal to the width of the gate structure 15. The width of the gate well region 30g may be greater than the width of the gate structure 15 or may be less than the width of the gate structure 15.

[0138] The width of the gate well region 30g may be 0.1 μm to 2 μm, or may have a value belonging to at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0139] The plurality of gate well regions 30g are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall of the plurality of gate structures 15, and face the first semiconductor region 6 across a part of the second semiconductor region 7. In this embodiment, the plurality of gate well regions 30g have a depth less than the depth of the plurality of gate structures 15 in a cross-sectional view, and are formed at intervals from a depth position at the middle of the second semiconductor region 7 toward the bottom wall of the plurality of gate structures 15.

[0140] Of course, the multiple gate well regions 30g may have a depth greater than that of the multiple gate structures 15 and may be formed in a columnar shape extending in the thickness direction of the chip 2. In this case, the multiple gate well regions 30g may cross the depth position of the intermediate portion of the second semiconductor region 7. In other words, the multiple gate well regions 30g may have bottoms located closer to the bottom of the second semiconductor region 7 (toward the second main surface 4) than the intermediate portion of the second semiconductor region 7.

[0141] The depth of the gate well region 30g is preferably greater than 0 μm and less than or equal to 5 μm. The depth of the gate well region 30g may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0142] The gate well region 30g may have an aspect ratio greater than 0 and less than or equal to 10. The aspect ratio of the gate well region 30g is the ratio of the depth of the gate well region 30g to the width of the gate well region 30g. The aspect ratio may have a value belonging to at least one of the following ranges: greater than 0 and less than or equal to 1, 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0143] The plurality of gate well regions 30g each have an upper end located on the bottom wall side of the corresponding gate structure 15. The upper ends of the plurality of gate well regions 30g may be connected to the bottom wall of the corresponding gate structure 15.

[0144] The upper ends of the plurality of gate well regions 30g may extend along the sidewalls of the corresponding gate structures 15 and be connected to the body region 10. Of course, the upper ends of the plurality of gate well regions 30g may be formed at intervals from the bottom walls of the corresponding gate structures 15 toward the bottom of the second semiconductor region 7.

[0145] The plurality of source well regions 30s are formed in the chip 2 (second semiconductor region 7) in regions directly below the plurality of source structures 20, spaced apart from the plurality of gate well regions 30g in the first direction X. The plurality of source well regions 30s are formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the plurality of source structures 20, and overlap with the plurality of source structures 20 in a one-to-one correspondence in the thickness direction.

[0146] The multiple source well regions 30s each extend in a strip shape in the second direction Y in plan view, following the extension direction of the corresponding source structure 20. That is, the multiple source well regions 30s are arranged in a stripe shape extending in the second direction Y in plan view. The extension direction of the multiple source well regions 30s coincides with the off-direction of the SiC single crystal.

[0147] Of course, the source well regions 30s may extend in the first direction X in accordance with the extending direction of the source structures 20. In this case, the source well regions 30s intersect (specifically, are perpendicular to) the off-direction.

[0148] The source well regions 30s are formed at intervals inward from the periphery (the dummy structures 25) of the active region 8. In the second direction Y, both ends of the source well regions 30s may be located inward of the source structures 20 with respect to both ends of the source structures 20, or may be located on the periphery of the active region 8 with respect to both ends of the source structures 20.

[0149] When the distance between the centers of the plurality of source well regions 30s in the horizontal direction (first direction X) is defined as the source well pitch, the source well pitch is approximately equal to the source pitch of the plurality of source structures 20. Of course, the source well pitch may be larger than the source pitch or smaller than the source pitch.

[0150] The source well pitch is preferably approximately equal to the gate well pitch, although the source well pitch may be greater than or less than the gate well pitch.

[0151] When the distance in the horizontal direction (first direction X) between the center of the gate well region 30g and the center of the source well region 30s is defined as the well pitch, the well pitch is preferably approximately equal to the trench pitch between the gate structure 15 and the source structure 20. Of course, the well pitch may be larger than the trench pitch or smaller than the trench pitch.

[0152] The source well region 30s may have a width approximately equal to the width of the source structure 20. The source well region 30s may be greater than or less than the width of the source structure 20. The width of the source well region 30s may be approximately equal to the width of the gate well region 30g. The width of the source well region 30s may be greater than or less than the width of the gate well region 30g.

[0153] The width of the source well region 30s may be 0.1 μm or more and 2 μm or less. The width of the source well region 30s may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0154] The plurality of source well regions 30s are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall of the plurality of source structures 20, and face the first semiconductor region 6 across a part of the second semiconductor region 7. In this embodiment, the plurality of source well regions 30s have a depth less than the depth of the plurality of source structures 20 in a cross-sectional view, and are formed at intervals from a depth position at the middle of the second semiconductor region 7 toward the bottom wall of the plurality of source structures 20.

[0155] Of course, the multiple source well regions 30s may have a depth greater than that of the multiple source structures 20 and may be formed in a columnar shape extending in the thickness direction of the chip 2. In this case, the multiple source well regions 30s may cross the depth position of the intermediate portion of the second semiconductor region 7. In other words, the multiple source well regions 30s may have bottoms located closer to the bottom of the second semiconductor region 7 than the intermediate portion of the second semiconductor region 7.

[0156] The source well regions 30s may form a superjunction structure with the gate well regions 30g. In the superjunction structure, when a reverse bias voltage is applied, a depletion layer extending from the gate well regions 30g and a depletion layer extending from the source well regions 30s are connected in a region (second semiconductor region 7) between the gate well regions 30g and the source well regions 30s.

[0157] The depth of the source well regions 30s may be approximately equal to the depth of the gate well regions 30g, or may be greater than or less than the depth of the gate well regions 30g.

[0158] The depth of the source well region 30s is preferably greater than 0 μm and less than or equal to 5 μm. The depth of the source well region 30s may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0159] The source well region 30s may have an aspect ratio greater than 0 and less than or equal to 10. The aspect ratio of the source well region 30s is the ratio of the depth of the source well region 30s to the width of the source well region 30s. The aspect ratio may have a value belonging to at least one of the ranges greater than 0 and less than or equal to 1, 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0160] The plurality of source well regions 30s each have an upper end portion located on the bottom wall side of the corresponding source structure 20. The upper ends of the plurality of source well regions 30s may be connected to the bottom wall of the corresponding source structure 20.

[0161] The upper ends of the plurality of source well regions 30s may extend along the sidewalls of the corresponding source structures 20 and be connected to the body region 10. Of course, the upper ends of the plurality of source well regions 30s may be formed at intervals from the bottom walls of the corresponding source structures 20 toward the bottom of the second semiconductor region 7.

[0162] The multiple dummy well regions 30d are formed in the chip 2 (second semiconductor region 7) in regions directly below the multiple dummy structures 25, spaced horizontally from the multiple gate well regions 30g and the multiple source well regions 30s.

[0163] The multiple dummy well regions 30d are each formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple dummy structures 25, and overlap the multiple dummy structures 25 in a one-to-one correspondence in the thickness direction.

[0164] The multiple dummy well regions 30d each extend in a strip shape along the corresponding dummy structure 25 in plan view. In this embodiment, the multiple dummy well regions 30d are each formed in a polygonal ring shape (a square ring in this embodiment) extending along the corresponding dummy structure 25 in plan view. The multiple dummy well regions 30d may be connected to each other in the horizontal direction. Of course, the multiple dummy well regions 30d may also be formed with intervals between them.

[0165] When the horizontal distance between the centers of the multiple dummy well regions 30d is defined as the dummy well pitch, the dummy well pitch is approximately equal to the dummy pitch of the multiple dummy structures 25. Of course, the dummy well pitch may be larger than the dummy pitch or smaller than the dummy pitch.

[0166] In this embodiment, the dummy well pitch is less than the well pitch between the gate well region 30g and the source well region 30s. Of course, the dummy well pitch may be approximately equal to the well pitch or may be greater than the well pitch.

[0167] The dummy well pitch may be approximately equal to the gate well pitch. The dummy well pitch may be greater than or less than the gate well pitch. The dummy well pitch may be approximately equal to the source well pitch. The dummy well pitch may be greater than or less than the source well pitch.

[0168] The dummy well region 30d may have a width that is approximately equal to the width of the dummy structure 25. The width of the dummy well region 30d may be greater than the width of the dummy structure 25 or may be less than the width of the dummy structure 25.

[0169] The width of the dummy well region 30d may be approximately equal to the width of the gate well region 30g, or may be greater than or less than the width of the gate well region 30g.

[0170] The width of the dummy well region 30d may be approximately equal to the width of the source well region 30s, or may be greater than or less than the width of the source well region 30s.

[0171] The width of the dummy well region 30d may be 0.1 μm or more and 2 μm or less. The width of the dummy well region 30d may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0172] The plurality of dummy well regions 30d are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall of the plurality of dummy structures 25, and face the first semiconductor region 6 across a part of the second semiconductor region 7. In this embodiment, the plurality of dummy well regions 30d have a depth less than the depth of the plurality of dummy structures 25 in a cross-sectional view, and are formed at intervals from a depth position at the middle of the second semiconductor region 7 toward the bottom wall of the plurality of dummy structures 25.

[0173] Of course, the multiple dummy well regions 30d may have a depth greater than the depth of the multiple dummy structures 25 and may be formed in a columnar shape extending in the thickness direction of the chip 2. In this case, the multiple dummy well regions 30d may cross the depth position of the intermediate portion of the second semiconductor region 7. In other words, the multiple dummy well regions 30d may have bottoms located closer to the bottom of the second semiconductor region 7 than the intermediate portion of the second semiconductor region 7.

[0174] The depth of the plurality of dummy well regions 30d may be approximately equal to the depth of the plurality of gate well regions 30g, or may be greater than or less than the depth of the plurality of gate well regions 30g.

[0175] The depth of the plurality of dummy well regions 30d may be approximately equal to the depth of the plurality of source well regions 30s, or may be greater than or less than the depth of the plurality of source well regions 30s.

[0176] The depth of the dummy well region 30d is preferably greater than 0 μm and less than 5 μm. The depth of the dummy well region 30d may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0177] The dummy well region 30d may have an aspect ratio greater than 0 and less than or equal to 10. The aspect ratio of the dummy well region 30d is the ratio of the depth of the dummy well region 30d to the width of the dummy well region 30d. The aspect ratio may have a value belonging to at least one of the ranges greater than 0 and less than or equal to 1, 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0178] The plurality of dummy well regions 30d each have an upper end portion located on the bottom wall side of the corresponding dummy structure 25. The upper ends of the plurality of dummy well regions 30d may be connected to the bottom walls of the corresponding dummy structures 25.

[0179] The upper ends of the plurality of dummy well regions 30d may extend along the sidewalls of the corresponding dummy structures 25 and be connected to the body region 10. Of course, the upper ends of the plurality of dummy well regions 30d may be formed at intervals from the bottom walls of the corresponding dummy structures 25 toward the bottom of the second semiconductor region 7.

[0180] The semiconductor device 1A includes a plurality of contact regions 31 formed in the chip 2 (second semiconductor region 7). The plurality of contact regions 31 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the plurality of contact regions 31 is higher than the p-type impurity concentration of the well region 30.

[0181] The contact regions 31 include gate contact regions 31g, source contact regions 31s, and one or more (in this embodiment, multiple) dummy contact regions 31d. The gate contact region 31g may be referred to as a "first contact region" or the like, the source contact region 31s may be referred to as a "second contact region" or the like, and the dummy contact region 31d may be referred to as a "third contact region" or the like.

[0182] The plurality of gate contact regions 31g are formed in regions along the plurality of gate structures 15, spaced apart from the plurality of source structures 20. The plurality of gate contact regions 31g are formed in a one-to-many correspondence with the plurality of gate structures 15. The plurality of gate contact regions 31g are interposed in regions between the bottom walls of the plurality of gate structures 15 and the bottoms of the plurality of gate well regions 30g, and are formed at intervals in the second direction Y.

[0183] With respect to one gate structure 15 and the other gate structure 15, the multiple gate contact regions 31g along one gate structure 15 face the multiple gate contact regions 31g along the other gate structure 15 in the first direction X in a plan view. In other words, the multiple gate contact regions 31g are generally arranged in a matrix at intervals in the first direction X and the second direction Y in a plan view.

[0184] Of course, the plurality of gate contact regions 31g along one gate structure 15 may face, in plan view, a region between the plurality of gate contact regions 31g along the other gate structure 15 in the first direction X. In other words, the plurality of gate contact regions 31g may be arranged in a staggered pattern overall in plan view with intervals in the first direction X and the second direction Y.

[0185] In this embodiment, the gate contact regions 31g extend in a strip shape along the gate structures 15 in a plan view. The lengths of the gate contact regions 31g in the second direction Y may be equal to or different from one another. The lengths of the gate contact regions 31g in the second direction Y are adjusted according to the channel area to be formed.

[0186] The channel area is the total area of ​​the portions of the source region 11 exposed from the regions between the gate structures 15 and the source structures 20. That is, the channel area increases or decreases depending on the ratio of the total planar area of ​​the gate contact regions 31g. The total planar area of ​​the gate contact regions 31g is preferably less than the channel area.

[0187] That is, in the region between one adjacent gate structure 15 and one adjacent source structure 20, the total planar area of ​​the plurality of gate contact regions 31g is preferably less than the planar area of ​​the source region 11. With this configuration, an increase in the resistance value (on-resistance) due to a short channel is suppressed.

[0188] The length of the plurality of gate contact regions 31g may be greater than or less than the width of the gate structure 15. The length of the plurality of gate contact regions 31g may be greater than or less than the gate pitch of the plurality of gate structures 15.

[0189] The spacing between the multiple gate contact regions 31g in the second direction Y is preferably larger than the width of the gate structure 15. Of course, the spacing between the multiple gate contact regions 31g in the second direction Y may be smaller than the width of the gate structure 15. The spacing between the multiple gate contact regions 31g may be larger or smaller than the gate pitch.

[0190] The plurality of gate contact regions 31g are connected to the bottom walls of the corresponding gate structures 15 and the corresponding gate well regions 30g. The gate contact regions 31g extend from the regions directly below the gate structures 15 to both sides of the gate structures 15 and have extending portions that extend in the vertical direction Z along the side walls of the gate structures 15.

[0191] It is preferable that the thickness in the horizontal direction (first direction X) of the portion (extension) of the gate contact region 31g that runs along the side wall of the gate structure 15 is less than the thickness in the vertical direction Z of the portion of the gate contact region 31g that runs along the bottom wall of the gate structure 15.

[0192] The extension of the gate contact region 31g is electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connects the corresponding gate well region 30g to the body region 10. This prevents the gate well region 30g from being electrically floating, and improves the electrical response characteristics of the gate well region 30g.

[0193] The gate contact region 31g has an upper end exposed from the first main surface 3. In this embodiment, the upper end of the gate contact region 31g is exposed from the sidewall of the first trench 16 at the opening end of the first trench 16. The upper end of the gate contact region 31g may extend horizontally in the surface layer portion of the body region 10.

[0194] The source contact regions 31s are formed in regions along the source structures 20, spaced apart from the gate structures 15. The source contact regions 31s have a planar layout that is different from the planar layout of the gate contact regions 31g. In this embodiment, the source contact regions 31s are formed in a one-to-one correspondence with the source structures 20.

[0195] The multiple source contact regions 31s are respectively interposed in regions between the bottom walls of the corresponding source structures 20 and the bottoms of the corresponding source well regions 30s, and extend in a strip shape in the second direction Y. In other words, the multiple source contact regions 31s are formed in stripes extending along the multiple source structures 20 in a plan view.

[0196] That is, the source contact regions 31s have lengths in the second direction Y that are greater than the lengths of the gate contact regions 31g, and cross the gate structures 15 in the second direction Y. The source contact regions 31s may have lengths in the second direction Y that are greater than the lengths of the source structures 20, or may have lengths that are less than the lengths of the source structures 20.

[0197] The source contact regions 31s preferably have a total planar area greater than the total planar area of ​​the gate contact regions 31g. The total planar area of ​​the source contact regions 31s may be greater than or less than the channel area.

[0198] Of course, like the multiple gate contact regions 31g, the multiple source contact regions 31s may be formed in a one-to-many correspondence with the multiple source structures 20. In this case, with respect to one source structure 20 and the other source structure 20, the multiple gate contact regions 31g along one source structure 20 may face the multiple source contact regions 31s along the other source structure 20 in the first direction X in plan view.

[0199] That is, the multiple source contact regions 31s may be generally arranged in a matrix with gaps in the first direction X and the second direction Y in a plan view. Of course, the multiple source contact regions 31s along one source structure 20 may face, in the first direction X, a region between the multiple source contact regions 31s along the other source structure 20 in a plan view. That is, the multiple source contact regions 31s may be generally arranged in a staggered manner with gaps in the first direction X and the second direction Y in a plan view.

[0200] The plurality of source contact regions 31s are respectively connected to the bottom walls of the corresponding source structures 20 and the corresponding source well regions 30s. The plurality of source contact regions 31s extend from the regions directly below the source structures 20 to both sides of the source structures 20 and have extending portions that extend along the sidewalls of the source structures 20.

[0201] It is preferable that the thickness in the horizontal direction (first direction X) of the portion (extension) of the source contact region 31s along the side wall of the source structure 20 is less than the thickness in the vertical direction Z of the portion of the source contact region 31s along the bottom wall of the source structure 20.

[0202] The extension of the source contact region 31s is electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connects the corresponding source well region 30s to the body region 10. This prevents the source well region 30s from being electrically floating, and improves the electrical response characteristics of the source well region 30s.

[0203] The source contact region 31s has an upper end exposed from the first main surface 3. In this embodiment, the upper end of the source contact region 31s is exposed from the sidewall of the second trench 21 at the opening end of the second trench 21. The upper end of the source contact region 31s may extend horizontally in the surface layer portion of the body region 10.

[0204] The upper end of the source contact region 31s is electrically connected to the upper end of the gate contact region 31g in the body region 10. In this embodiment, the upper end of the source contact region 31s is formed integrally with the upper end of the gate contact region 31g.

[0205] The plurality of dummy contact regions 31d are formed in regions along the plurality of dummy structures 25, spaced apart from the plurality of gate structures 15 and the plurality of source structures 20. The plurality of dummy contact regions 31d are formed in a one-to-one correspondence with the plurality of dummy structures 25.

[0206] The plurality of dummy contact regions 31d are respectively interposed in regions between the bottom wall of the corresponding dummy structure 25 and the bottom of the corresponding dummy well region 30d, and extend in a strip shape along the corresponding dummy structure 25. In this embodiment, the plurality of dummy contact regions 31d each extend in a polygonal ring shape (a square ring shape in this embodiment) along the corresponding dummy structure 25 in plan view.

[0207] The plurality of dummy contact regions 31d are respectively connected to the bottom walls of the corresponding dummy structures 25 and the corresponding dummy well regions 30d. The plurality of dummy contact regions 31d protrude from the region directly below the dummy structures 25 to both sides of the dummy structures 25 and have extensions that extend along the side walls of the dummy structures 25.

[0208] It is preferable that the thickness in the horizontal direction (first direction X) of the portions (extensions) of the multiple dummy contact regions 31d that extend along the side walls of the dummy structure 25 is less than the thickness in the vertical direction Z of the portions of the multiple dummy contact regions 31d that extend along the bottom walls of the dummy structure 25.

[0209] The extensions of the plurality of dummy contact regions 31d are electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connect the corresponding dummy well regions 30d to the body region 10. This prevents the plurality of dummy well regions 30d from being electrically floating, and improves the electrical response characteristics of the plurality of dummy well regions 30d.

[0210] The plurality of dummy contact regions 31d each have an upper end portion exposed from the first main surface 3. In this embodiment, the upper ends of the plurality of dummy contact regions 31d are exposed from the sidewall of the third trench 26 at the opening end of the third trench 26.

[0211] The upper ends of the multiple dummy contact regions 31 d may extend horizontally in a surface layer portion of the body region 10. The upper ends of the multiple dummy contact regions 31 d are electrically connected to each other in the body region 10. In this embodiment, the upper ends of the multiple dummy contact regions 31 d are integrally formed in the body region 10.

[0212] 10A to 10E, the configuration of the peripheral region 9 will be described. Figures 10A to 10E are cross-sectional views showing the cross-sectional structure of the peripheral region 9 taken along line XX shown in Figure 1, together with the peripheral structures 40 according to the first to fifth embodiments.

[0213] 10A , semiconductor device 1A may include a peripheral structure 40 according to the first embodiment formed in peripheral region 9. Peripheral structure 40 includes a first peripheral structure 41 on the inner side (active region 8) of first main surface 3, and a second peripheral structure 42 on the peripheral edge side of first main surface 3.

[0214] The first peripheral structure 41 includes a p-type outer well region 43 formed in a surface layer portion of the first main surface 3 in the peripheral region 9 (the peripheral portion of the first main surface 3). The outer well region 43 may also be referred to as a "well region" or the like. A source potential is applied to the outer well region 43. The outer well region 43 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.

[0215] The outer well region 43 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 31. The p-type impurity concentration of the outer well region 43 may be approximately equal to the p-type impurity concentration of the body region 10. The p-type impurity concentration of the outer well region 43 may be higher than the p-type impurity concentration of the body region 10, or may be lower than the p-type impurity concentration of the body region 10.

[0216] The p-type impurity concentration of the outer well region 43 may be approximately equal to the p-type impurity concentration of the well region 30. The p-type impurity concentration of the outer well region 43 may be higher than the p-type impurity concentration of the well region 30, or may be lower than the p-type impurity concentration of the well region 30.

[0217] The outer well region 43 is formed in a surface layer portion of the second semiconductor region 7 and is electrically connected to the second semiconductor region 7. The outer well region 43 extends in a layered manner along the first main surface 3. The outer well region 43 is formed at an interval from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) to the inward side of the first main surface 3 (toward the active region 8). The outer well region 43 extends in a band shape along the periphery of the first main surface 3 (the periphery of the active region 8) in a plan view.

[0218] In this embodiment, the outer well region 43 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner portion (active region 8) of the first main surface 3. The outer well region 43 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0219] The outer well region 43 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. In this embodiment, the inner edge portion of the outer well region 43 is connected to the outermost dummy structure 25. The inner edge portion of the outer well region 43 defines the boundary between the active region 8 and the peripheral region 9.

[0220] The outer well region 43 has a width greater than the width of the outermost dummy structure 25. The width of the outer well region 43 may be greater than the total width of the plurality of dummy structures 25.

[0221] The outer well region 43 may have a width greater than 0 μm and less than 300 μm. The width of the outer well region 43 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm. The width of the outer well region 43 is preferably greater than 10 μm and less than 200 μm.

[0222] The outer well region 43 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The outer well region 43 is preferably formed at a distance from a depth position of the middle part of the second semiconductor region 7 toward the first main surface 3.

[0223] The outer well region 43 has an upper end exposed from the first main surface 3 and a bottom located within the second semiconductor region 7. The bottom of the outer well region 43 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the body region 10. Of course, the bottom of the outer well region 43 may be located closer to the first main surface 3 than the depth position of the bottom of the body region 10.

[0224] The bottom of the outer well region 43 may be located on the first main surface 3 side relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s and the dummy well region 30d).

[0225] The bottom of the outer well region 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the at least one type of well region 30. The bottom of the outer well region 43 may be located at a depth position substantially equal to the depth of the bottom of the at least one type of well region 30.

[0226] The bottom of the outer well region 43 is located closer to the first main surface 3 than the depth position of the bottom wall of the gate structure 15. The bottom of the outer well region 43 is located closer to the first main surface 3 than the depth position of the bottom wall of the source structure 20. The bottom of the outer well region 43 is located closer to the first main surface 3 than the depth position of the bottom wall of the dummy structure 25.

[0227] The bottom of the outer well region 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the gate structure 15. The bottom of the outer well region 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the source structure 20. The bottom of the outer well region 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the dummy structure 25.

[0228] In this embodiment, the outer well region 43 is formed at a distance from the depth position of the upper end of the dummy well region 30d toward the first main surface 3, and does not have a direct connection to the dummy well region 30d.

[0229] For example, when the bottom of the outer well region 43 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the dummy structure 25, the outer well region 43 may have a portion connected to the well region 30 (dummy well region 30d). The bottom of the outer well region 43 may be connected to the upper end of the dummy well region 30d.

[0230] The depth (thickness) of the outer well region 43 may be greater than 0 μm and less than 5 μm. The depth of the outer well region 43 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The depth of the outer well region 43 is preferably greater than 0.2 μm and less than 3 μm.

[0231] The outer well region 43 forms a pn junction with the second semiconductor region 7. The outer well region 43 spreads a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer in the outer well region 43 spreads horizontally and in the thickness direction, and merges with the depletion layer spreading from the active region 8. The outer well region 43 expands the depletion layer spreading from the active region 8 toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (peripheral region 9) of the first main surface 3.

[0232] The first peripheral structure 41 includes a p-type outer contact region 44 formed in the peripheral region 9 (the peripheral edge of the first principal surface 3) in a surface layer portion of the first principal surface 3. The outer contact region 44 may also be referred to as a "contact region," a "fourth contact region," or the like.

[0233] The outer contact region 44 has a p-type impurity concentration higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the outer contact region 44 is higher than the p-type impurity concentration of the well region 30. The p-type impurity concentration of the outer contact region 44 is higher than the p-type impurity concentration of the outer well region 43.

[0234] The p-type impurity concentration of the outer contact region 44 may be approximately equal to the p-type impurity concentration of the contact region 31. The p-type impurity concentration of the outer contact region 44 may be higher than the p-type impurity concentration of the contact region 31, or may be lower than the p-type impurity concentration of the contact region 31.

[0235] The outer contact region 44 is formed in the surface layer portion of the outer well region 43. In other words, the outer contact region 44 is formed in a thickness range between the first main surface 3 and the bottom of the outer well region 43. The outer contact region 44 increases the p-type impurity concentration of the outer well region 43, and improves the electrical response speed of the outer well region 43.

[0236] The outer contact region 44 extends in a band shape along the outer well region 43 (active region 8) in a plan view. In this embodiment, the outer contact region 44 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part of the first main surface 3 (active region 8).

[0237] The outer contact region 44 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). Of course, the outer contact region 44 may have a plurality of portions that are arranged at intervals along the active region 8 so as to surround the active region 8. In this case, the plurality of portions may each extend in a strip shape along the active region 8.

[0238] The outer contact region 44 has a width less than that of the outer well region 43, and is formed within the outer well region 43. The outer contact region 44 has an inner edge portion on the inner side of the first main surface 3 (on the active region 8 side) and an outer edge portion on the peripheral side of the first main surface 3.

[0239] In this embodiment, the inner edge of the outer well region 43 is connected to the outermost dummy structure 25. In this embodiment, the inner edge of the outer well region 43 is connected to the dummy contact region 31d that is located along the outermost dummy structure 25. As a result, the outer well region 43 is electrically connected to the body region 10 via the dummy contact region 31d. Of course, the outer well region 43 may be formed at a distance from the dummy contact region 31d.

[0240] The outer edge of the outer contact region 44 is formed at a distance from the outer edge of the outer well region 43. Of course, the outer contact region 44 may cross the outer edge of the outer well region 43.

[0241] The outer contact region 44 has a width greater than the width of the outermost dummy structure 25. The width of the outer contact region 44 may be greater than the total width of the plurality of dummy structures 25.

[0242] The width of the outer contact region 44 may be greater than 0 μm and less than 300 μm. The width of the outer contact region 44 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm. The width of the outer contact region 44 is preferably greater than 10 μm and less than 50 μm.

[0243] The outer contact region 44 has an upper end located on the first main surface 3 side and a bottom located on the bottom side of the outer well region 43. The upper end of the outer contact region 44 is exposed from the first main surface 3.

[0244] The bottom of the outer contact region 44 is located on the first main surface 3 side with respect to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d).

[0245] The bottom of the outer contact region 44 is located closer to the first main surface 3 than the depth position of the bottom wall of the gate structure 15. The bottom of the outer contact region 44 is located closer to the first main surface 3 than the depth position of the bottom wall of the source structure 20. The bottom of the outer contact region 44 is located closer to the first main surface 3 than the depth position of the bottom wall of the dummy structure 25.

[0246] The bottom of the outer contact region 44 is formed at a distance from the bottom of the outer well region 43 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the outer well region 43. The bottom of the outer contact region 44 may be formed at a distance from a depth position at the middle of the outer well region 43 toward the first main surface 3.

[0247] The bottom of the outer contact region 44 may be located on the bottom side of the outer well region 43 relative to the depth position of the middle part of the outer well region 43. The bottom of the outer contact region 44 may cross the bottom of the outer well region 43 and be located within the second semiconductor region 7.

[0248] The bottom of the outer contact region 44 is located closer to the first main surface 3 than the depth position of the bottom of the body region 10. The bottom of the outer contact region 44 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the body region 10.

[0249] The depth (thickness) of the outer contact region 44 may be greater than 0 μm and less than 1 μm. The depth of the outer contact region 44 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, 0.4 μm to 0.5 μm, 0.5 μm to 0.6 μm, 0.6 μm to 0.7 μm, 0.7 μm to 0.8 μm, 0.8 μm to 0.9 μm, and 0.9 μm to 1 μm. The depth of the outer contact region 44 is preferably greater than 0.05 μm and less than 0.5 μm.

[0250] The first peripheral structure 41 includes a p-type termination region 45 formed in the surface layer of the first main surface 3 in the peripheral region 9 (the peripheral portion of the first main surface 3). The termination region 45 may also be referred to as a "termination well region" or a "JTE region (Junction Termination Extension region)." A source potential is applied to the termination region 45.

[0251] The termination region 45 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the termination region 45 is lower than the p-type impurity concentration of the contact region 31. The p-type impurity concentration of the termination region 45 is lower than the p-type impurity concentration of the outer contact region 44.

[0252] The p-type impurity concentration of the termination region 45 may be higher than the p-type impurity concentration of the body region 10 or may be lower than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the termination region 45 may be higher than the p-type impurity concentration of the well region 30 or may be lower than the p-type impurity concentration of the well region 30. The p-type impurity concentration of the termination region 45 may be higher than the p-type impurity concentration of the outer well region 43 or may be lower than the p-type impurity concentration of the outer well region 43.

[0253] The termination region 45 is formed in a region between the periphery of the first main surface 3 and the active region 8. Specifically, the termination region 45 is formed in a region between the periphery of the first main surface 3 and the outer well region 43. The termination region 45 extends in a band shape along the periphery of the first main surface 3 (the outer well region 43, the active region 8) in a plan view.

[0254] In this embodiment, termination region 45 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of chip 2 in a plan view, and surrounds the inner portion (outer well region 43, active region 8) of first main surface 3. Termination region 45 may have an edge portion that connects the portion extending in first direction X and the portion extending in second direction Y in an arc shape (preferably a quadrant arc shape).

[0255] Of course, termination region 45 may have a plurality of portions arranged at intervals along the inner portion (outer well region 43, active region 8) of first main surface 3 so as to surround the inner portion (outer well region 43, active region 8) of first main surface 3. In this case, the plurality of portions may each extend in a strip shape along the inner portion (outer well region 43, active region 8) of first main surface 3.

[0256] The termination region 45 preferably has a width greater than the width of the outer well region 43. Of course, the width of the termination region 45 may be less than the width of the outer well region 43.

[0257] The width of termination region 45 may be greater than 0 μm and less than 300 μm. The width of termination region 45 may be greater than 0 μm and less than 25 μm, greater than 25 μm and less than 50 μm, greater than 50 μm and less than 75 μm, greater than 75 μm and less than 100 μm, greater than 100 μm and less than 125 μm, greater than 125 μm and less than 150 μm, greater than 150 μm and less than 175 μm, greater than 175 μm and less than 200 μm, greater than 200 μm and less than 225 μm, greater than 225 μm and less than 250 μm, greater than 250 μm and less than 275 μm, and greater than 275 μm and less than 300 μm. The width of termination region 45 is preferably greater than 10 μm and less than 200 μm.

[0258] The width ratio of the width of termination region 45 to the width of outer well region 43 may be 0.5 or more and 5 or less. The width ratio may have a value belonging to any one of the ranges of 0.5 or more and 0.75 or less, 0.75 or more and 1 or less, 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, 2.75 or more and 3 or less, 4 or more and 4.25 or less, 4.25 or more and 4.5 or less, 4.5 or more and 4.75 or less, and 4.75 or more and 5 or less. The width ratio is preferably 1 or more and 2.5 or less.

[0259] The termination region 45 is formed in a surface layer portion of the second semiconductor region 7 and is electrically connected to the second semiconductor region 7. The termination region 45 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The termination region 45 is preferably formed at a distance from a depth position in the middle of the second semiconductor region 7 toward the first main surface 3.

[0260] The termination region 45 is formed at a distance from the first main surface 3 in the thickness direction of the chip 2. In other words, the termination region 45 is formed at a distance from the first main surface 3 to the bottom side of the second semiconductor region 7, and has a portion facing the first main surface 3 with a part of the second semiconductor region 7 in between.

[0261] The distance between first main surface 3 and termination region 45 may be greater than 0 μm and less than 3 μm. The distance may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, 2.25 μm to 2.5 μm, 2.5 μm to 2.75 μm, and 2.75 μm to 3 μm. The distance is preferably greater than 0.1 μm and less than 2 μm.

[0262] The termination region 45 has an upper end located on the first main surface 3 side and a bottom located on the bottom side of the second semiconductor region 7. The upper end of the termination region 45 extends horizontally along the first main surface 3 and forms a pn junction with the second semiconductor region 7. The upper end of the termination region 45 is located on the first main surface 3 side with respect to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d).

[0263] The upper end of the termination region 45 is located on the first main surface 3 side relative to the depth position of the bottom wall of the gate structure 15. The upper end of the termination region 45 is located on the first main surface 3 side relative to the depth position of the bottom wall of the source structure 20. The upper end of the termination region 45 is located on the first main surface 3 side relative to the depth position of the bottom wall of the dummy structure 25. The upper end of the termination region 45 is located on the first main surface 3 side relative to the depth position of the bottom of the outer well region 43.

[0264] The bottom of termination region 45 extends horizontally along first main surface 3 and forms a pn junction with second semiconductor region 7. In this embodiment, the bottom of termination region 45 is located closer to the bottom of second semiconductor region 7 than the depth position of the bottom of body region 10. The bottom of termination region 45 may also be located closer to first main surface 3 than the depth position of the bottom of body region 10.

[0265] The bottom of termination region 45 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom of outer well region 43. The bottom of termination region 45 may be located closer to first main surface 3 than the depth position of the bottom of outer well region 43. The bottom of termination region 45 may be located at a depth position substantially equal to the bottom of outer well region 43.

[0266] The bottom of the termination region 45 may be located closer to the first main surface 3 than the depth position of the bottom wall of the gate structure 15. The bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the gate structure 15. The bottom of the termination region 45 may be located closer to the first main surface 3 than the depth position of the bottom wall of the source structure 20. The bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the source structure 20.

[0267] The bottom of termination region 45 may be located closer to first main surface 3 than the depth position of the bottom wall of dummy structure 25. The bottom of termination region 45 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom wall of dummy structure 25.

[0268] The bottom of the termination region 45 may be located closer to the first main surface 3 than the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d). The bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the at least one type of well region 30. The bottom of the termination region 45 may be located at a depth position substantially equal to the depth of the bottom of the at least one type of well region 30.

[0269] Termination region 45 may have a depth (thickness) that is greater than the distance between first major surface 3 and termination region 45. The depth of termination region 45 is the distance between the top and bottom of termination region 45. The depth of termination region 45 may be less than the distance between first major surface 3 and termination region 45.

[0270] The depth of the termination region 45 may be smaller than the distance between the bottom of the second semiconductor region 7 and the termination region 45. The depth of the termination region 45 may be larger than the distance between the bottom of the second semiconductor region 7 and the termination region 45. The depth of the termination region 45 is preferably smaller than the depth of the outer well region 43. The depth of the termination region 45 may be larger than the depth of the outer well region 43.

[0271] The depth (thickness) of termination region 45 may be greater than 0 μm and equal to or less than 4 μm. The depth of termination region 45 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.25 μm, 0.25 μm or more and less than 0.5 μm, 0.5 μm or more and less than 0.75 μm, 0.75 μm or more and less than 1 μm, 1 μm or more and less than 1.25 μm, 1.25 μm or more and less than 1.5 μm, 1.5 μm or more and less than 1.75 μm, 1.75 μm or more and less than 2 μm, 2 μm or more and less than 2.25 μm, 2.25 μm or more and less than 2.5 μm, 2.5 μm or more and less than 2.75 μm, 2.75 μm or more and less than 3 μm, 3 μm or more and less than 3.25 μm, 3.25 μm or more and less than 3.5 μm, 3.5 μm or more and less than 3.75 μm, and 3.75 μm or more and less than 4 μm. The depth of the termination region 45 is preferably 0.5 μm or more and 3 μm or less.

[0272] The termination region 45 has an inner edge portion on the inner side (outer well region 43) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the termination region 45 is connected to the outer edge portion of the outer well region 43.

[0273] Specifically, the inner edge of the termination region 45 is connected to the outer edge of the outer well region 43 in a region closer to the bottom of the outer well region 43 than the depth position of the middle part of the outer well region 43. In this way, the termination region 45 is electrically connected to the body region 10 and the outer contact region 44 via the outer well region 43.

[0274] The inner edge of the termination region 45 may be located closer to the inner edge of the outer well region 43 than the outer edge of the outer contact region 44. The inner edge of the termination region 45 may be formed at a distance from the outer edge of the outer contact region 44 toward the outer edge of the outer well region 43.

[0275] The inner edge of the termination region 45 may be formed at a distance from the bottom of the outer contact region 44 toward the bottom of the outer well region 43, and may face the outer contact region 44 across a part of the outer well region 43. The inner edge of the termination region 45 may be connected to the outer contact region 44.

[0276] The inner edge of the termination region 45 may be formed at a distance from the inner edge of the outer well region 43 (the outermost dummy structure 25) toward the outer edge of the outer well region 43. The inner edge of the termination region 45 may be connected to the outermost dummy structure 25.

[0277] In this case, the inner edge of termination region 45 may have a portion connected to the outermost dummy well region 30 d. Of course, this specification does not exclude from the technical concept a configuration in which the inner edge of termination region 45 is formed at a distance from the inner edge of outer well region 43 toward the peripheral edge of first main surface 3.

[0278] The connection portion (overlap portion) between the outer edge of the outer well region 43 and the inner edge of the termination region 45 contains the p-type impurities of the outer well region 43 and the p-type impurities of the termination region 45. Therefore, the connection portion (overlap portion) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer well region 43 and the p-type impurity concentration of the termination region 45.

[0279] The termination region 45 expands the depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer in the termination region 45 expands in the horizontal and thickness directions and integrates with the depletion layer expanding from the active region 8 (outer well region 43). The termination region 45 expands the depletion layer expanding from the active region 8 toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (peripheral region 9) of the first main surface 3.

[0280] The second periphery structure 42 includes at least one p-type field region 47 formed in the surface layer portion of the first main surface 3 in the periphery region 9 (the peripheral portion of the first main surface 3). The field region 47 may also be referred to as a "guard region," a "field limit region," or the like.

[0281] The plurality of field regions 47 are formed in an electrically floating state. Of course, the plurality of field regions 47 may be fixed to the source potential. The plurality of field regions 47 relieve the electric field within the chip 2 in the peripheral region 9.

[0282] The number of field regions 47 is arbitrary. The number of field regions 47 may be 1 or more and 15 or less. The number of field regions 47 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. The number of field regions 47 is typically 1 or more and 10 or less. In this embodiment, the second peripheral structure 42 includes, for example, six field regions 47.

[0283] The plurality of field regions 47 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the plurality of field regions 47 is lower than the p-type impurity concentration of the contact region 31. The p-type impurity concentration of the plurality of field regions 47 may be higher than the p-type impurity concentration of the contact region 31.

[0284] The p-type impurity concentration of the plurality of field regions 47 is lower than the p-type impurity concentration of the outer contact region 44. The p-type impurity concentration of the plurality of field regions 47 may be higher than the p-type impurity concentration of the outer contact region 44.

[0285] The p-type impurity concentrations of the plurality of field regions 47 may be higher than the p-type impurity concentration of the body region 10 or may be lower than the p-type impurity concentration of the body region 10. The p-type impurity concentrations of the plurality of field regions 47 may be approximately equal to the p-type impurity concentration of the body region 10.

[0286] The p-type impurity concentrations of the plurality of field regions 47 may be higher than the p-type impurity concentration of the well region 30, or may be lower than the p-type impurity concentration of the well region 30. The p-type impurity concentrations of the plurality of field regions 47 may be approximately equal to the p-type impurity concentration of the well region 30.

[0287] The p-type impurity concentrations of the multiple field regions 47 may be higher than the p-type impurity concentration of the outer well region 43, or may be lower than the p-type impurity concentration of the outer well region 43. The p-type impurity concentrations of the multiple field regions 47 may be approximately equal to the p-type impurity concentration of the outer well region 43.

[0288] The p-type impurity concentrations of the plurality of field regions 47 are preferably approximately equal to the p-type impurity concentration of the termination region 45. Of course, the p-type impurity concentrations of the plurality of field regions 47 may be higher than the p-type impurity concentration of the termination region 45, or may be lower than the p-type impurity concentration of the termination region 45.

[0289] In this embodiment, the p-type impurity concentrations of the multiple field regions 47 are approximately equal to each other. The p-type impurity concentrations of the multiple field regions 47 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The p-type impurity concentrations of the multiple field regions 47 may also be different from each other.

[0290] The p-type impurity concentrations of the plurality of field regions 47 may increase sequentially toward the periphery of the first main surface 3. Of course, the p-type impurity concentrations of the plurality of field regions 47 may increase toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 47.

[0291] The p-type impurity concentrations of the plurality of field regions 47 may decrease in order toward the periphery of the first main surface 3. Of course, the p-type impurity concentrations of the plurality of field regions 47 may decrease toward the periphery of the first main surface 3 in units of two or more groups, each group including two or more field regions 47.

[0292] A plurality of field regions 47 are formed in the region between the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) and the active region 8 and spaced apart from the periphery of the first main surface 3 and the active region 8.

[0293] The plurality of field regions 47 are formed in a region between the periphery of the first main surface 3 and the outer well region 43, spaced apart from the periphery of the first main surface 3 and the outer well region 43. The plurality of field regions 47 are formed in a region between the periphery of the first main surface 3 and the termination region 45, spaced apart from the periphery of the first main surface 3 and the termination region 45.

[0294] The plurality of field regions 47 are formed at intervals from one another in the surface layer portion of the second semiconductor region 7 and are electrically connected to the second semiconductor region 7. The plurality of field regions 47 extend in a strip shape along the periphery of the first main surface 3 (the outer well region 43, the active region 8) in a plan view.

[0295] In this embodiment, the plurality of field regions 47 are formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surround the inner portion (the outer well region 43 and the active region 8) of the first main surface 3. The plurality of field regions 47 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0296] Of course, each of the multiple field regions 47 may have multiple portions arranged at intervals along the periphery (outer well region 43, active region 8) of the first main surface 3 so as to surround the inner portion (outer well region 43, active region 8) of the first main surface 3. In this case, the multiple portions may each extend in a strip shape along the periphery (outer well region 43, active region 8) of the first main surface 3. Each of the multiple field regions 47 has a width that is less than the width of the termination region 45.

[0297] The width of field region 47 may be greater than 0 μm and less than 5 μm. The width of field region 47 may be greater than 0 μm and less than 0.25 μm, greater than 0.25 μm and less than 0.5 μm, greater than 0.5 μm and less than 0.75 μm, greater than 0.75 μm and less than 1 μm, greater than 1 μm and less than 1.25 μm, greater than 1.25 μm and less than 1.5 μm, greater than 1.5 μm and less than 1.75 μm, greater than 1.75 μm and less than 2 μm, greater than 2 μm and less than 2.25 μm, greater than 2.25 μm and less than 2.5 μm, or greater than 2.5 μm. The width of the field region 47 may be in the range of 2.75 μm or less, 2.75 μm to 3 μm, 3 μm to 3.25 μm, 3.25 μm to 3.5 μm, 3.5 μm to 3.75 μm, 3.75 μm to 4 μm, 4 μm to 4.25 μm, 4.25 μm to 4.5 μm, 4.5 μm to 4.75 μm, or 4.75 μm to 5 μm. The width of the field region 47 is preferably in the range of 0.5 μm to 3 μm.

[0298] In this embodiment, the widths of the field regions 47 are approximately equal to each other. The widths of the field regions 47 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The widths of the field regions 47 may also be different from each other.

[0299] The spacing between the plurality of field regions 47 may be equal to or less than the width of the field region 47. The spacing between the plurality of field regions 47 is preferably less than the width of the field region 47. Of course, the spacing between the plurality of field regions 47 may be greater than the width of the field region 47.

[0300] The ratio of the spacing between field regions 47 to the width of field region 47 (spacing ratio) may be 0.1 or greater and 5 or less. The spacing ratio may have a value belonging to at least one of the ranges of 0.1 or greater and 0.5 or less, 0.5 or greater and 1 or less, 1 or greater and 1.5 or less, 1.5 or greater and 2 or less, 2 or greater and 2.5 or less, 2.5 or greater and 3 or less, 3 or greater and 3.5 or less, 3.5 or greater and 4 or less, 4 or greater and 4.5 or less, and 4.5 or greater and 5 or less. The spacing ratio is preferably 0.1 or greater and 2 or less.

[0301] In this embodiment, the spacing between the multiple field regions 47 is approximately equal to one another. The spacing between the multiple field regions 47 is arbitrary and can take various values ​​depending on the electric field to be relaxed. The spacing between the multiple field regions 47 may also be different from one another.

[0302] The spacing between the field regions 47 may be greater than 0 μm and less than or equal to 5 μm. The spacing may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The spacing is preferably greater than or equal to 0.5 μm and less than or equal to 3 μm.

[0303] The plurality of field regions 47 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 across a part of the second semiconductor region 7. The plurality of field regions 47 are preferably formed at intervals from a depth position at the middle of the second semiconductor region 7 toward the first main surface 3.

[0304] The plurality of field regions 47 are formed at intervals from the first main surface 3 in the thickness direction of the chip 2. In other words, the plurality of field regions 47 are formed at intervals from the first main surface 3 toward the bottom of the second semiconductor region 7, and have portions that face the first main surface 3 with part of the second semiconductor region 7 in between. The plurality of field regions 47 are each formed in a depth range between the top end and bottom of the termination region 45, and face the termination region 45 in the horizontal direction.

[0305] The distance between the first main surface 3 and the field region 47 is preferably approximately equal to the distance between the first main surface 3 and the termination region 45. Of course, the distance between the first main surface 3 and the field region 47 may be greater than the distance between the first main surface 3 and the termination region 45, or may be smaller than the distance between the first main surface 3 and the termination region 45.

[0306] The distance between the first main surface 3 and the field region 47 may be greater than 0 μm and less than 3 μm. The distance may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, 2.25 μm to 2.5 μm, 2.5 μm to 2.75 μm, and 2.75 μm to 3 μm. The distance is preferably greater than 0.1 μm and less than 2 μm.

[0307] Each of the plurality of field regions 47 has an upper end located on the first main surface 3 side and a bottom located on the bottom side of the second semiconductor region 7. The upper ends of the field regions 47 extend horizontally along the first main surface 3 and form pn junctions with the second semiconductor region 7. The upper ends of the field regions 47 are located on the first main surface 3 side with respect to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d).

[0308] The upper end of the field region 47 is located closer to the first main surface 3 than the depth position of the bottom wall of the gate structure 15. The upper end of the field region 47 is located closer to the first main surface 3 than the depth position of the bottom wall of the source structure 20. The upper end of the field region 47 is located closer to the first main surface 3 than the depth position of the bottom wall of the dummy structure 25.

[0309] The upper end of the field region 47 is located closer to the first main surface 3 than the depth position of the bottom of the outer well region 43. The upper end of the field region 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the outer well region 43.

[0310] The bottom of field region 47 extends horizontally along first main surface 3 and forms a pn junction with second semiconductor region 7. In this embodiment, the bottom of field region 47 is located closer to the bottom of second semiconductor region 7 than the depth position of the bottom of body region 10. The bottom of field region 47 may also be located closer to first main surface 3 than the depth position of the bottom of body region 10.

[0311] The bottom of field region 47 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom of outer well region 43. The bottom of field region 47 may be located closer to first main surface 3 than the depth position of the bottom of outer well region 43. The bottom of field region 47 may be located at a depth position substantially equal to the bottom of outer well region 43.

[0312] The bottom of field region 47 may be located closer to first main surface 3 than the depth position of the bottom wall of gate structure 15. The bottom of field region 47 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom wall of gate structure 15. The bottom of field region 47 may be located closer to first main surface 3 than the depth position of the bottom wall of source structure 20. The bottom of field region 47 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom wall of source structure 20.

[0313] The bottom of field region 47 may be located closer to first main surface 3 than the depth position of the bottom wall of dummy structure 25. The bottom of field region 47 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom wall of dummy structure 25.

[0314] The bottom of the field region 47 may be located on the first main surface 3 side relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d).

[0315] The bottom of the field region 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the at least one type of well region 30. The bottom of the field region 47 may be located at a depth position substantially equal to the depth of the bottom of the at least one type of well region 30.

[0316] Field region 47 may have a depth (thickness) approximately equal to the depth (thickness) of termination region 45. The depth of field region 47 is the distance between the top and bottom of field region 47. Of course, the depth of field region 47 may be greater than or less than the depth of termination region 45.

[0317] The depth of field region 47 may be greater than the distance between first main surface 3 and field region 47. The depth of field region 47 may be less than the distance between first main surface 3 and field region 47. The depth of field region 47 may be less than the distance between the bottom of second semiconductor region 7 and field region 47. The depth of field region 47 may be greater than the distance between the bottom of second semiconductor region 7 and field region 47.

[0318] The depth (thickness) of the field region 47 may be greater than 0 μm and equal to or less than 4 μm. The depth of field region 47 may have a value belonging to at least one of the following ranges: greater than 0 μm and less than 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, 1.75 μm to 2 μm, 2 μm to 2.25 μm, 2.25 μm to 2.5 μm, 2.5 μm to 2.75 μm, 2.75 μm to 3 μm, 3 μm to 3.25 μm, 3.25 μm to 3.5 μm, 3.5 μm to 3.75 μm, and 3.75 μm to 4 μm. The depth of the field region 47 is preferably 0.5 μm or more and 3 μm or less.

[0319] In this embodiment, the depths of the field regions 47 are approximately equal to one another. The depths of the field regions 47 are arbitrary and may take various values ​​depending on the electric field to be relaxed. The depths of the field regions 47 may also be different from one another.

[0320] The multiple field regions 47 expand the depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layers in the multiple field regions 47 expand horizontally and in the thickness direction, and merge with the depletion layer expanding from the active region 8 side (termination region 45 side). The multiple field regions 47 expand the depletion layer expanding from the active region 8 side (termination region 45 side) toward the peripheral edge of the first main surface 3, thereby reducing the electric field intensity (electric field concentration) in the peripheral portion (outer peripheral region 9) of the first main surface 3.

[0321] 10B , the semiconductor device 1A may include a peripheral structure 40 according to a second embodiment formed in the peripheral region 9. The peripheral structure 40 according to the second embodiment has a configuration in which the field region 47 is removed from the peripheral structure 40 (second peripheral structure 42) according to the first embodiment. In other words, the peripheral structure 40 according to the second embodiment includes an outer well region 43, an outer contact region 44, and a termination region 45, but does not include the field region 47.

[0322] 10C , the semiconductor device 1A may include a peripheral structure 40 according to a third embodiment formed in the peripheral region 9. The peripheral structure 40 according to the third embodiment has a configuration in which the termination region 45 is removed from the peripheral structure 40 (first peripheral structure 41) according to the first embodiment. In other words, the peripheral structure 40 according to the third embodiment includes an outer well region 43, an outer contact region 44, and a field region 47, but does not include the termination region 45.

[0323] 10D , the semiconductor device 1A may include a peripheral structure 40 according to a fourth embodiment formed in the peripheral region 9. The peripheral structure 40 according to the fourth embodiment includes a termination region 45 in the peripheral structure 40 (first peripheral structure 41) according to the first embodiment, the termination region 45 having an upper end exposed from the first main surface 3. Other configurations of the peripheral structure 40 according to the fourth embodiment are similar to those of the peripheral structure 40 according to the first embodiment.

[0324] 10E, the semiconductor device 1A may include a peripheral structure 40 according to a fifth embodiment formed in the peripheral region 9. The peripheral structure 40 according to the fifth embodiment includes one or more (multiple in this embodiment) field regions 47 having upper ends exposed from the first main surface 3 in the peripheral structure 40 (second peripheral structure 42) according to the first embodiment. The other configurations of the peripheral structure 40 according to the fifth embodiment are similar to those of the peripheral structure 40 according to the first embodiment.

[0325] In the peripheral structures 40 according to the first to fifth embodiments, the electric field distribution and the extension range of the depletion layer within the chip 2 (first main surface 3) are adjusted by the layout (particularly the termination region 45 and field region 47) of the first peripheral structure 41 and the second peripheral structure 42. In other words, the peripheral structures 40 according to the first to fifth embodiments have the advantage that the value of the breakdown voltage can be adjusted by the layout of the first peripheral structure 41 and the second peripheral structure 42.

[0326] Either or both of the termination region 45 and the field region 47 can be formed in the surface layer of the second semiconductor region 7 at a distance from the first major surface 3 and can have an upper end that forms a pn junction with the second semiconductor region 7.

[0327] This increases the extension range of the depletion layer and improves the breakdown voltage compared to when either or both of termination region 45 and field region 47 have upper ends exposed from first main surface 3. This configuration is also effective in adjusting the breakdown voltage in accordance with device specifications.

[0328] 1 to 10E, semiconductor device 1A includes a main surface insulating film 50 that selectively covers first main surface 3. Main surface insulating film 50 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0329] The main surface insulating film 50 preferably contains the same type of insulating material as the insulating material of the first insulating film 17. In this embodiment, the main surface insulating film 50 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 50 contains a silicon oxide film made of an oxide of the chip 2.

[0330] The main surface insulating film 50 is selectively connected to the first insulating film 17 of the plurality of gate structures 15, the second insulating film 22 of the plurality of source structures 20, and the third insulating film 27 of the plurality of dummy structures 25 in the active region 8, and exposes the first buried electrodes 18 of the plurality of gate structures 15, the second buried electrodes 23 of the plurality of source structures 20, and the third buried electrodes 28 of the plurality of dummy structures 25.

[0331] The main surface insulating film 50 covers the second semiconductor region 7, the outer well region 43, and the outer contact region 44 in the peripheral region 9. In this embodiment, the main surface insulating film 50 is continuous with the first to fourth side surfaces 5A to 5D in the peripheral portion of the first main surface 3. Of course, the main surface insulating film 50 may be formed at a distance inward from the peripheral portion of the first main surface 3, exposing the peripheral portion of the first main surface 3 (the second semiconductor region 7).

[0332] The semiconductor device 1A includes an outer wiring 51 arranged on a main surface insulating film 50 in the peripheral region 9. The outer wiring 51 may also be referred to as a "wiring," "main surface wiring," "peripheral wiring," "side wiring," or the like.

[0333] The outer wiring 51 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The outer wiring 51 preferably has the same conductive material (conductivity type) as at least one of the first buried electrode 18, the second buried electrode 23, and the third buried electrode 28.

[0334] The outer wiring 51 is arranged in the peripheral region 9 at a distance from the periphery of the first main surface 3 toward the active region 8. The outer wiring 51 is arranged on the outer well region 43 and faces the outer well region 43 with the main surface insulating film 50 interposed therebetween.

[0335] The outer wiring 51 extends in a band shape along the periphery of the first main surface 3 (the periphery of the active region 8) in plan view, following the outer well region 43. In this embodiment, the outer wiring 51 is formed in a polygonal ring shape (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view, and surrounds the inner part of the first main surface 3 (the active region 8).

[0336] The outer wiring 51 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). The outer wiring 51 may be either ended or endless.

[0337] The outer wiring 51 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the outer wiring 51 is drawn out into the active region 8, crossing the boundary between the active region 8 and the outer periphery region 9 (i.e., the inner edge portion of the outer well region 43). The inner edge portion of the outer wiring 51 covers one or more dummy structures 25.

[0338] In this embodiment, the inner edge of the outer wiring 51 covers the outermost dummy structure 25 and is connected to the third buried electrode 28 of the outermost dummy structure 25. The outer wiring 51 is formed integrally with the third buried electrode 28 of the dummy structure 25. In other words, the outer wiring 51 is formed as an extension portion of the third buried electrode 28, and is routed over the main surface insulating film 50.

[0339] The outer edge of outer wiring 51 is formed at a distance inward (toward active region 8) from the innermost field region 47 of the plurality of field regions 47. In other words, the outer edge of outer wiring 51 does not face the plurality of field regions 47 across main surface insulating film 50. With this configuration, the outer wiring 51 is prevented from blocking the electric field dispersion path in the region above the plurality of field regions 47, and the plurality of field regions 47 appropriately distributes the electric field (electric force lines).

[0340] The outer edge of the outer wiring 51 is formed at a distance inward from the outer edge of the termination region 45. In this embodiment, the outer edge of the outer wiring 51 is disposed at a distance inward from the outer edge of the outer contact region 44, and has a portion facing the outer contact region 44 across the main surface insulating film 50. The outer edge of the outer wiring 51 may have a portion facing the termination region 45 in the stacking direction.

[0341] The semiconductor device 1A includes an insulating interlayer film 52 that selectively covers the first main surface 3 with the main surface insulating film 50 sandwiched therebetween. The interlayer film 52 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 52 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 52 preferably includes a silicon oxide film.

[0342] The interlayer film 52 covers the plurality of gate structures 15 (first buried electrodes 18) and the plurality of dummy structures 25 (third buried electrodes 28) on the side of the active region 8. The interlayer film 52 may cover both ends of the source structure 20 on the side of the active region 8.

[0343] The interlayer film 52 covers the second semiconductor region 7 , the outer well region 43 and the outer contact region 44 on the peripheral region 9 side, with the main surface insulating film 50 sandwiched therebetween.

[0344] In this embodiment, the interlayer film 52 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral portion of the first main surface 3. Of course, the interlayer film 52 may be formed at a distance inward from the peripheral portion of the first main surface 3, exposing the peripheral portion of the first main surface 3 (the second semiconductor region 7).

[0345] The interlayer film 52 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer film 52 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0346] The semiconductor device 1A includes a plurality of source openings 53 formed in an interlayer film 52. The plurality of source openings 53 are formed in a region between the plurality of gate structures 15 in a one-to-one correspondence with the plurality of source structures 20. The plurality of source openings 53 each extend in a strip shape in the second direction Y along the corresponding source structure 20.

[0347] The plurality of source openings 53 penetrate the main surface insulating film 50 and the interlayer film 52, and expose a corresponding one of the source structures 20, the source region 11, the plurality of gate contact regions 31g, and the plurality of source contact regions 31s. Each of the plurality of source openings 53 may have an opening end curved in an arc shape.

[0348] The plurality of source openings 53 may be formed in a one-to-many correspondence with the corresponding one source structure 20. In this case, the plurality of source openings 53 may be formed at intervals along the corresponding one source structure 20. In this case, the plurality of source openings 53 may be formed in a quadrangular shape, a rectangular shape (strip shape), a circular shape, or the like in a plan view.

[0349] The semiconductor device 1A includes at least one outer opening 54 (one in this embodiment) formed in the interlayer film 52. The outer opening 54 penetrates the main surface insulating film 50 and the interlayer film 52, exposing the outer edge of the outer wiring 51 and the outer contact region 44. The outer opening 54 extends in a strip shape along the outer edge of the outer wiring 51 and the outer contact region 44 in a plan view.

[0350] In this embodiment, the outer opening 54 is formed in a polygonal ring shape (specifically, a square ring shape) in plan view that surrounds the inner portion (active region 8) of the first main surface 3 along the outer contact region 44 and the outer wiring 51. The outer opening 54 may have an opening end that is curved in an arc shape.

[0351] Of course, the semiconductor device 1A may have a plurality of outer openings 54. In this case, the plurality of outer openings 54 may be formed at intervals along the outer contact region 44 and the outer wiring 51 so as to surround the inner portion (active region 8) of the first main surface 3. In this case, the plurality of outer openings 54 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in plan view.

[0352] The semiconductor device 1A includes a plurality of gate openings 55 formed in an interlayer film 52 (see FIG. 3). The plurality of gate openings 55 are formed in a one-to-many correspondence with a corresponding one of the gate structures 15. In this embodiment, the plurality of gate openings 55 penetrate the interlayer film 52 and expose one end or the other end of each of the plurality of gate structures 15 (first buried electrodes 18).

[0353] The gate openings 55 may each have an opening end curved in an arc shape. The gate openings 55 may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, or the like in a plan view.

[0354] The semiconductor device 1A includes a source electrode 60 disposed on the first main surface 3. The source electrode 60 is a terminal electrode to which a source potential is applied from the outside. The source electrode 60 may also be referred to as a "source pad electrode," a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like.

[0355] The source electrode 60 is disposed on a portion of the interlayer film 52 that covers the active region 8. The source electrode 60 extends from above the interlayer film 52 into the plurality of source openings 53, and is electrically connected to the source region 11 and the plurality of contact regions 31 within the plurality of source openings 53.

[0356] In this embodiment, the source electrode 60 has a first pad portion 60a, a second pad portion 60b, and a third pad portion 60c. The first pad portion 60a has a relatively large planar area and forms the main body of the source electrode 60. In this embodiment, the first pad portion 60a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first main surface 3.

[0357] The second pad portion 60b has a planar area smaller than that of the first pad portion 60a, and is drawn out in a strip shape (rectangular) from one end of the first pad portion 60a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 60c has a planar area smaller than that of the first pad portion 60a, and is drawn out in a strip shape (rectangular) from the other end of the first pad portion 60a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 60b in the second direction Y.

[0358] The planar area of ​​the third pad portion 60c may be approximately equal to the planar area of ​​the second pad portion 60b. Of course, the planar area of ​​the third pad portion 60c may be larger than the planar area of ​​the second pad portion 60b, or may be smaller than the planar area of ​​the second pad portion 60b. Either or both of the second pad portion 60b and the third pad portion 60c may be used as a terminal portion for monitoring a current.

[0359] The source electrode 60 does not necessarily have to have both the second pad portion 60b and the third pad portion 60c at the same time. The source electrode 60 may have only one of the second pad portion 60b and the third pad portion 60c. Of course, the source electrode 60 may be composed of only the first pad portion 60a and may not have both the second pad portion 60b and the third pad portion 60c.

[0360] In this embodiment, the source electrode 60 has a layered structure including a lower electrode film 61 and a main electrode film 62, which are layered in this order from the chip 2 side. In this embodiment, the lower electrode film 61 has a layered structure including a first electrode film 63 and a second electrode film 64. In this embodiment, the first electrode film 63 includes a Ti film, and the second electrode film 64 includes a TiN film. The lower electrode film 61 does not necessarily have to have a layered structure, and may have a single-layer structure consisting of either the first electrode film 63 (Ti film) or the second electrode film 64 (TiN film).

[0361] The first electrode film 63 has a thickness less than the thickness of the interlayer film 52. The thickness of the first electrode film 63 may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 63 may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0362] The second electrode film 64 has a thickness less than that of the interlayer film 52. The thickness of the second electrode film 64 is preferably greater than that of the first electrode film 63. The thickness of the second electrode film 64 may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 64 may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0363] The first electrode film 63 collectively covers the region of the interlayer film 52 where the multiple source openings 53 are formed, and extends from above the interlayer film 52 into the multiple source openings 53. The first electrode film 63 has a portion that covers the insulating main surface of the interlayer film 52 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 53 in a film-like manner, and a portion that covers the first main surface 3 in the multiple source openings 53. The first electrode film 63 is mechanically and electrically connected to the source region 11 and the multiple contact regions 31 in the source openings 53.

[0364] The second electrode film 64 directly covers the first electrode film 63. The second electrode film 64 collectively covers the region of the interlayer film 52 where the multiple source openings 53 are formed, sandwiching the first electrode film 63 therebetween, and extends from above the interlayer film 52 into the multiple source openings 53.

[0365] The second electrode film 64 has a portion that covers the insulating main surface of the interlayer film 52 in a film-like manner with the first electrode film 63 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 53 in a film-like manner with the first electrode film 63 sandwiched therebetween, and a portion that covers the first main surface 3 in a film-like manner with the first electrode film 63 sandwiched therebetween within the plurality of source openings 53. The second electrode film 64 is electrically connected to the source region 11 and the plurality of contact regions 31 via the first electrode film 63 within the source opening 53.

[0366] The main electrode film 62 contains a different conductive material from the lower electrode film 61 (the first electrode film 63 and the second electrode film 64). The main electrode film 62 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 62 has a thickness greater than the thickness (total thickness) of the lower electrode film 61. The thickness of the main electrode film 62 is preferably greater than the thickness of the interlayer film 52.

[0367] The thickness of the main electrode film 62 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 62 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0368] The main electrode film 62 directly covers the lower electrode film 61 (second electrode film 64). The main electrode film 62 collectively covers the region of the interlayer film 52 where the plurality of source openings 53 are formed, and backfills the plurality of source openings 53.

[0369] The main electrode film 62 has a portion that covers the insulating main surface of the interlayer film 52 with the lower electrode film 61 in between, a portion that covers the wall surfaces of the plurality of source openings 53 with the lower electrode film 61 in between, and a portion that covers the first main surface 3 with the lower electrode film 61 in between. The main electrode film 62 is electrically connected to the source region 11 and the plurality of contact regions 31 via the lower electrode film 61 within the plurality of source openings 53.

[0370] The semiconductor device 1A includes a termination wiring 65 arranged around the source electrode 60 on the interlayer film 52. The termination wiring 65 is supplied with the same potential (source potential) as the potential (source potential) supplied to the source electrode 60. The termination wiring 65 may also be referred to as a "termination electrode," "wiring," "source wiring," "first wiring," "finger electrode," "source finger," or the like.

[0371] The termination wiring 65 has a wiring width less than the electrode width of the source electrode 60, and is selectively routed on the interlayer film 52. In this embodiment, the termination wiring 65 is drawn from the source electrode 60 (first pad portion 60a) to the fourth side surface 5D. The termination wiring 65 is drawn from the active region 8 to the peripheral region 9, and has a portion that faces the outer wiring 51 with the interlayer film 52 sandwiched between them. In this embodiment, the termination wiring 65 covers the outer wiring 51 over the entire periphery.

[0372] The termination wiring 65 enters the outer opening 54 from above the interlayer film 52 and is electrically connected to the outer contact region 44 and the outer wiring 51 within the outer opening 54. In other words, the termination wiring 65 is electrically connected to the termination region 45 via the outer contact region 44.

[0373] The termination wiring 65 is electrically connected to one or more (one in this embodiment) dummy structures 25 (third buried electrodes 28) via the outer wiring 51. The source potential applied to the source electrode 60 is applied to the dummy structures 25 via the termination wiring 65, and is also applied to the termination region 45 via the termination wiring 65.

[0374] In plan view, the termination wiring 65 extends in a band shape along the periphery of the first main surface 3 (the periphery of the active region 8) following the outer contact region 44. In this embodiment, the termination wiring 65 is formed in a polygonal ring shape (a square ring in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view, and surrounds the inner part of the first main surface 3 (the active region 8).

[0375] The termination wiring 65 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). The termination wiring 65 may be either terminated or endless.

[0376] The termination wiring 65 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral edge side of the first main surface 3. The inner edge portion of the termination wiring 65 is located within the active region 8 and faces one or more (multiple in this embodiment) dummy structures 25 with the interlayer film 52 interposed therebetween.

[0377] The outer edge of termination wiring 65 is formed at a distance inward (toward active region 8) from the periphery of first main surface 3. The outer edge of termination wiring 65 is formed at a distance inward from the innermost field region 47 of the multiple field regions 47. In other words, termination wiring 65 does not face the multiple field regions 47 across interlayer film 52.

[0378] With this configuration, the electric field dispersion path in the region above the plurality of field regions 47 is prevented from being blocked by the termination wiring 65, and the electric field (electric field lines) are appropriately dispersed by the plurality of field regions 47.

[0379] The outer edge of the termination wiring 65 is formed at a distance inward from the outer edge of the termination region 45, and faces the termination region 45 across the interlayer film 52. In this embodiment, the outer edge of the outer wiring 51 is disposed at a distance from the outer edge of the outer contact region 44 toward the outer edge of the termination region 45, and faces the entire outer contact region 44 across the main surface insulating film 50.

[0380] Like the source electrode 60, the termination wiring 65 has a laminated structure including a lower electrode film 61 and a main electrode film 62 laminated in this order from the chip 2 side. In this embodiment, the lower electrode film 61 has a laminated structure including a first electrode film 63 and a second electrode film 64.

[0381] The first electrode film 63 covers the entire region of the interlayer film 52 where the outer opening 54 is formed, and extends into the outer opening 54 from above the interlayer film 52. The first electrode film 63 has a portion that covers the insulating main surface of the interlayer film 52 in a film-like manner, a portion that covers the wall surface of the outer opening 54 in a film-like manner, and a portion that covers the outer wiring 51 and the first main surface 3 within the outer opening 54. The first electrode film 63 is mechanically and electrically connected to the outer contact region 44 and the outer wiring 51 within the outer opening 54.

[0382] The second electrode film 64 directly covers the first electrode film 63. The second electrode film 64 collectively covers the region of the interlayer film 52 where the outer opening 54 is formed, sandwiching the first electrode film 63 therebetween, and extends from above the interlayer film 52 into the outer opening 54.

[0383] The second electrode film 64 has a portion that covers the insulating main surface of the interlayer film 52 in a film-like manner with the first electrode film 63 in between, a portion that covers the wall surface of the outer opening 54 in a film-like manner with the first electrode film 63 in between, and a portion that covers the first main surface 3 in the outer opening 54 in a film-like manner with the first electrode film 63 in between. The second electrode film 64 is electrically connected to the outer contact region 44 and the outer wiring 51 via the first electrode film 63 in the outer opening 54.

[0384] The main electrode film 62 directly covers the lower electrode film 61 (second electrode film 64). The main electrode film 62 collectively covers the region of the interlayer film 52 where the outer opening 54 is formed, and backfills the outer opening 54.

[0385] The main electrode film 62 has a portion that covers the insulating main surface of the interlayer film 52 with the lower electrode film 61 in between, a portion that covers the wall surface of the outer opening 54 with the lower electrode film 61 in between, and a portion that covers the first main surface 3 with the lower electrode film 61 in between. The main electrode film 62 is electrically connected to the outer contact region 44 and the outer wiring 51 via the lower electrode film 61 within the outer opening 54.

[0386] The semiconductor device 1A includes a gate electrode 66 disposed on the first main surface 3. The gate electrode 66 is a terminal electrode to which a gate potential is applied from the outside. The gate electrode 66 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like. Although not shown, the gate electrode 66 includes a lower electrode film 61 and a main electrode film 62 stacked in this order from the chip 2 side, similar to the source electrode 60.

[0387] The gate electrode 66 is disposed on a portion of the interlayer film 52 that covers the active region 8, spaced apart from the source electrode 60. In this embodiment, the gate electrode 66 is disposed in a region on the third side surface 5C side of the first pad portion 60a, and faces the first pad portion 60a in the first direction X. The gate electrode 66 is interposed in a region between the second pad portion 60b and the third pad portion 60c, and faces both the second pad portion 60b and the third pad portion 60c in the second direction Y.

[0388] The gate electrode 66 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 66 has a planar area less than the planar area of ​​the source electrode 60. The gate electrode 66 has a planar area less than the planar area of ​​the first pad portion 60a. The gate electrode 66 may also have a planar area less than the planar area of ​​the second pad portion 60b (third pad portion 60c).

[0389] The gate electrode 66 partially faces the plurality of gate structures 15 and the plurality of source structures 20 across the interlayer film 52. Specifically, the gate electrode 66 is disposed inwardly from both ends of the plurality of gate structures 15 at a distance, and faces inner portions of the plurality of gate structures 15 across the interlayer film 52. In this form, the gate electrode 66 does not have any direct electrical connection points to the plurality of gate structures 15.

[0390] Of course, the gate electrode 66 may be electrically connected to the plurality of gate structures 15 through the plurality of gate openings 55. The portions of the plurality of gate structures 15 located under the gate electrode 66 may be removed.

[0391] In this case, the gate electrode 66 may face the body region 10 with the main surface insulating film 50 and the interlayer film 52 sandwiched therebetween. The gate electrode 66 may also partially face one or more dummy structures 25 with the interlayer film 52 sandwiched therebetween.

[0392] The semiconductor device 1A includes a gate wiring 67 that is drawn out from the gate electrode 66 onto the first main surface 3. The gate wiring 67 may also be referred to as a "wiring," a "second wiring," a "finger electrode," a "gate finger," or the like.

[0393] The gate wiring 67 transmits the gate potential applied to the gate electrode 66 to other regions. Although not shown, the gate wiring 67 includes a lower electrode film 61 and a main electrode film 62 stacked in this order from the chip 2 side, similar to the source electrode 60 (gate electrode 66).

[0394] The gate wiring 67 is drawn out from the gate electrode 66 onto the portion of the interlayer film 52 that covers the active region 8, and is routed to the region between the source electrode 60 and the termination wiring 65 at a distance from the source electrode 60 and the termination wiring 65.

[0395] The gate wiring 67 has a portion extending in a strip shape in the first direction X in a plan view and a portion extending in a strip shape in the second direction Y, and intersects (specifically, orthogonally) with ends (both ends in this embodiment) of the multiple gate structures 15. In this embodiment, the gate wiring 67 is formed in a strip shape with ends having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 60.

[0396] The gate wiring 67 enters the plurality of gate openings 55 from above the interlayer film 52, and is mechanically and electrically connected to the ends (both ends) of the plurality of gate structures 15 (first buried electrodes 18) within the plurality of gate openings 55. As a result, the gate potential applied to the gate electrode 66 is applied to the plurality of gate structures 15 via the gate wiring 67.

[0397] The semiconductor device 1A includes a drain electrode 68 covering the second main surface 4. The drain electrode 68 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 68 may also be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," or the like.

[0398] The drain electrode 68 is electrically connected to the first semiconductor region 6. The drain electrode 68 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 68 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0399] A breakdown voltage that can be applied between the source electrode 60 and the drain electrode 68 (between the first major surface 3 and the second major surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or less and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, 2500 V or more and 2750 V or less, and 2750 V or more and 3000 V or less.

[0400] 11A to 11J, first to tenth modified examples of the first peripheral structure 41 according to the first to fifth embodiments will be shown below. Figures 11A to 11J are cross-sectional views showing the first peripheral structure 41 according to the first to tenth modified examples.

[0401] The semiconductor device 1A may include any one of the features of the first peripheral structure 41 according to the first to fifth embodiments from the features of the first peripheral structure 41 according to the first to tenth modifications. Of course, the features of the first peripheral structure 41 according to the first to tenth modifications may be combined as appropriate.

[0402] Therefore, the semiconductor device 1A can simultaneously include at least two of the features of the first peripheral structure 41 according to the first to tenth modified examples in the same or different regions with respect to the first peripheral structure 41 according to the first to fifth embodiment examples.

[0403] At least one feature of the outer well region 43, outer contact region 44, and termination region 45 according to the first to tenth modified examples is appropriately selected depending on the configuration of the first to fifth embodiment examples, and is applied to the configuration of the first to fifth embodiment examples.

[0404] Referring to Figure 11A (first variant), the first peripheral structure 41 may include an outer well region 43 having a bottom located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s and the dummy well region 30d).

[0405] The bottom of the outer well region 43 may be connected to the well region 30 (dummy well region 30 d ), or may be formed spaced apart from the well region 30 .

[0406] The bottom of the termination region 45 may be located on the first main surface 3 side relative to the depth position of at least one of the bottom wall of the gate structure 15 , the bottom wall of the source structure 20 and the bottom wall of the dummy structure 25 .

[0407] Referring to Figure 11B (second variant), the first peripheral structure 41 may include an outer well region 43 having a bottom located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s and the dummy well region 30d).

[0408] The bottom of the outer well region 43 may be connected to the well region 30 (dummy well region 30 d ), or may be formed spaced apart from the well region 30 .

[0409] The bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of at least one of the bottom walls of the gate structure 15, the source structure 20, and the dummy structure 25. The bottom of the termination region 45 may be located closer to the first main surface 3 than the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d).

[0410] Referring to Figure 11C (third variant), the first peripheral structure 41 may include an outer well region 43 having a bottom located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s and the dummy well region 30d).

[0411] The bottom of the outer well region 43 may be connected to the well region 30 (dummy well region 30 d ), or may be formed spaced apart from the well region 30 .

[0412] The bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of at least one of the bottom wall of the gate structure 15, the bottom wall of the source structure 20, and the bottom wall of the dummy structure 25. In this embodiment, the bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of at least one type of well region 30.

[0413] The bottom of termination region 45 may be located closer to first main surface 3 than the depth position of the bottom of the intermediate portion of second semiconductor region 7. The bottom of termination region 45 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom of the intermediate portion of second semiconductor region 7.

[0414] Referring to Figure 11D (fourth variant), the first peripheral structure 41 may include an outer well region 43 having a bottom located on the first main surface 3 side relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s and the dummy well region 30d).

[0415] The bottom of the outer well region 43 may be connected to the well region 30 (dummy well region 30d), or may be formed at a distance from the well region 30. The bottom of the outer well region 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of at least one of the bottom wall of the gate structure 15, the bottom wall of the source structure 20, and the bottom wall of the dummy structure 25.

[0416] The bottom of the termination region 45 may be located on the first main surface 3 side relative to the depth position of at least one of the bottom wall of the gate structure 15 , the bottom wall of the source structure 20 and the bottom wall of the dummy structure 25 .

[0417] Referring to Figure 11E (fifth variant), the first peripheral structure 41 may include an outer well region 43 having a bottom located on the first main surface 3 side relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s and the dummy well region 30d).

[0418] The bottom of the outer well region 43 may be connected to the well region 30 (dummy well region 30d), or may be formed at a distance from the well region 30. The bottom of the outer well region 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of at least one of the bottom wall of the gate structure 15, the bottom wall of the source structure 20, and the bottom wall of the dummy structure 25.

[0419] The bottom of the termination region 45 may be located on the first main surface 3 side relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d).

[0420] The bottom of the termination region 45 may be located on the bottom side of the second semiconductor region 7 relative to the depth position of at least one of the bottom wall of the gate structure 15 , the bottom wall of the source structure 20 and the bottom wall of the dummy structure 25 .

[0421] Referring to Figure 11F (sixth variant), the first peripheral structure 41 may include an outer well region 43 having a bottom located on the first main surface 3 side relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s and the dummy well region 30d).

[0422] The bottom of the outer well region 43 may be connected to the well region 30 (dummy well region 30d), or may be formed at a distance from the well region 30. The bottom of the outer well region 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of at least one of the bottom wall of the gate structure 15, the bottom wall of the source structure 20, and the bottom wall of the dummy structure 25.

[0423] The bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s and the dummy well region 30d).

[0424] The bottom of termination region 45 may be located closer to first main surface 3 than the depth position of the bottom of the intermediate portion of second semiconductor region 7. The bottom of termination region 45 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom of the intermediate portion of second semiconductor region 7.

[0425] 11G (seventh modified example), first peripheral structure 41 may include outer well region 43 having a bottom located closer to first main surface 3 than the depth position of the bottom wall of dummy structure 25. The bottom of outer well region 43 may be connected to well region 30 (dummy well region 30d), or may be formed spaced apart from well region 30.

[0426] An upper end of the termination region 45 may be connected to the outer well region 43. The bottom of the termination region 45 may be located on the bottom side of the second semiconductor region 7 with respect to the depth position of at least one of the bottom wall of the gate structure 15, the bottom wall of the source structure 20, and the bottom wall of the dummy structure 25.

[0427] The bottom of the termination region 45 may be located on the first main surface 3 side relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d).

[0428] 11H (eighth modified example), first peripheral structure 41 may include outer well region 43 having a bottom located closer to first main surface 3 than the depth position of the bottom wall of dummy structure 25. The bottom of outer well region 43 may be connected to well region 30 (dummy well region 30d), or may be formed spaced apart from well region 30.

[0429] An upper end of the termination region 45 may be connected to the outer well region 43. The bottom of the termination region 45 may be located at a depth substantially equal to the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d).

[0430] 11I (ninth modified example), first peripheral structure 41 may include outer well region 43 having a bottom located closer to first main surface 3 than the depth position of the bottom wall of dummy structure 25. The bottom of outer well region 43 may be connected to well region 30 (dummy well region 30d), or may be formed spaced apart from well region 30.

[0431] The bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s and the dummy well region 30d).

[0432] The bottom of termination region 45 may be located closer to first main surface 3 than the depth position of the bottom of the intermediate portion of second semiconductor region 7. The bottom of termination region 45 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom of the intermediate portion of second semiconductor region 7.

[0433] Referring to Figure 11J (tenth variant), the first periphery structure 41 may include a termination region 45 formed at a distance from the bottom of the outer well region 43 toward the bottom of the second semiconductor region 7.

[0434] The bottom of termination region 45 may be located closer to first main surface 3 than the depth position of at least one of the bottom walls of gate structure 15, source structure 20, and dummy structure 25. The bottom of termination region 45 may be located closer to the bottom of second semiconductor region 7 than the depth position of at least one of the bottom walls of gate structure 15, source structure 20, and dummy structure 25.

[0435] The bottom of the termination region 45 may be located closer to the first main surface 3 than the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d). The bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of at least one type of well region 30.

[0436] The bottom of the termination region 45 may be located at a depth substantially equal to the bottom of the at least one type of well region 30. The bottom of the termination region 45 may be located closer to the first main surface 3 than the depth position of the intermediate portion of the second semiconductor region 7. The bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the intermediate portion of the second semiconductor region 7.

[0437] The upper end of the termination region 45 may be located closer to the first main surface 3 than a depth position of at least one of the bottom walls of the gate structure 15, the source structure 20, and the dummy structure 25. The upper end of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than a depth position of at least one of the bottom walls of the gate structure 15, the source structure 20, and the dummy structure 25.

[0438] The upper end of the termination region 45 may be located closer to the first main surface 3 than the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d). The upper end of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of at least one type of well region 30.

[0439] 12A to 12J, first to tenth modified examples of the second peripheral structure 42 according to the first to fifth embodiments will be shown below. Figures 12A to 12J are cross-sectional views showing the second peripheral structure 42 according to the first to tenth modified examples.

[0440] The semiconductor device 1A may include any one of the features of the second peripheral structures 42 according to the first to fifth embodiments from the features of the second peripheral structures 42 according to the first to tenth modifications. Of course, the features of the second peripheral structures 42 according to the first to tenth modifications may be combined as appropriate.

[0441] Therefore, the semiconductor device 1A can simultaneously include, in the same or different regions, at least two of the features of the second peripheral structures 42 according to the first to tenth modifications in the second peripheral structures 42 according to the first to fifth embodiments. At least one feature of the field region 47 according to the first to tenth modifications is selected appropriately depending on the configuration of the first to fifth embodiments, and is applied to the configuration of the first to fifth embodiments.

[0442] One or more of the features of the second peripheral structure 42 according to the first to tenth modified examples are applied as appropriate to any one of the configurations of the first to fifth embodiment examples together with one or more of the features of the first peripheral structure 41 according to the first to tenth modified examples.

[0443] 12A (first modified example), the second peripheral structure 42 may include a plurality of field regions 47 arranged at different intervals. The intervals between the plurality of field regions 47 may increase sequentially toward the periphery of the first main surface 3.

[0444] That is, the spacing between the field regions 47 located on the peripheral edge side of the first main surface 3 may be greater than the spacing between the field regions 47 located on the inner edge side of the first main surface 3. Of course, the spacing between the field regions 47 may increase toward the peripheral edge side of the first main surface 3 in units of two or more groups, each group including two or more field regions 47.

[0445] 12B (second modified example), the second peripheral structure 42 may include a plurality of field regions 47 arranged at different intervals. The intervals between the plurality of field regions 47 may decrease sequentially toward the periphery of the first main surface 3.

[0446] In other words, the spacing between the field regions 47 located on the peripheral edge side of the first main surface 3 may be smaller than the spacing between the field regions 47 located on the inner edge side of the first main surface 3. Of course, the spacing between the field regions 47 may decrease toward the peripheral edge side of the first main surface 3 in units of two or more groups, each group including two or more field regions 47.

[0447] 12C (third modified example), the second peripheral structure 42 may include a plurality of field regions 47 arranged with different widths. The widths of the plurality of field regions 47 may increase sequentially toward the periphery of the first main surface 3.

[0448] That is, the widths of the field regions 47 located on the peripheral edge of the first main surface 3 may be greater than the widths of the field regions 47 located on the inner edge of the first main surface 3. Of course, the widths of the field regions 47 may increase toward the peripheral edge of the first main surface 3 in groups of two or more, each group including two or more field regions 47.

[0449] 12D (fourth modified example), the second peripheral structure 42 may include a plurality of field regions 47 arranged with different widths. The widths of the plurality of field regions 47 may decrease sequentially toward the periphery of the first main surface 3.

[0450] That is, the widths of the field regions 47 located on the peripheral edge of the first main surface 3 may be smaller than the widths of the field regions 47 located on the inner edge of the first main surface 3. Of course, the widths of the field regions 47 may decrease toward the peripheral edge of the first main surface 3 in two or more groups, each group including two or more field regions 47.

[0451] 12E (fifth modified example), second perimeter structure 42 may include one or more (multiple in this embodiment) field regions 47 formed shallower than termination region 45. The bottoms of the multiple field regions 47 may be located closer to first main surface 3 than the depth position of the bottom of termination region 45.

[0452] The bottoms of the multiple field regions 47 may be located on the first main surface 3 side relative to the depth position of at least one of the bottom wall of the gate structure 15 , the bottom wall of the source structure 20 and the bottom wall of the dummy structure 25 .

[0453] The upper ends of the plurality of field regions 47 may be located closer to the first main surface 3 than the depth position of the upper end of the termination region 45. The upper ends of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the upper end of the termination region 45.

[0454] 12F (sixth modified example), second periphery structure 42 may include one or more (multiple in this embodiment) field regions 47 formed deeper than termination region 45. The bottoms of the multiple field regions 47 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom of termination region 45.

[0455] The bottoms of the multiple field regions 47 may be located on the bottom side of the second semiconductor region 7 relative to the depth position of at least one of the bottom wall of the gate structure 15, the bottom wall of the source structure 20, and the bottom wall of the dummy structure 25.

[0456] The upper ends of the plurality of field regions 47 may be located closer to the first main surface 3 than the depth position of the upper end of the termination region 45. The upper ends of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the upper end of the termination region 45. The upper ends of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the termination region 45.

[0457] 12G (seventh modified example), second periphery structure 42 may include one or more (multiple in this embodiment) field regions 47 formed deeper than termination region 45. The bottoms of the multiple field regions 47 may be located closer to the bottom of second semiconductor region 7 than the depth position of at least one of the bottom wall of gate structure 15, the bottom wall of source structure 20, and the bottom wall of dummy structure 25.

[0458] The bottoms of the multiple field regions 47 may be located on the first main surface 3 side relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d).

[0459] The bottoms of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the at least one type of well region 30. The bottoms of the plurality of field regions 47 may be located at a depth substantially equal to the depth of the bottom of the at least one type of well region 30.

[0460] The upper ends of the plurality of field regions 47 may be located closer to the first main surface 3 than the depth position of the upper end of the termination region 45. The upper ends of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the upper end of the termination region 45. The upper ends of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the termination region 45.

[0461] The upper ends of the plurality of field regions 47 may be located on the bottom side of the second semiconductor region 7 relative to a depth position of at least one of the bottom walls of the gate structure 15, the source structure 20, and the dummy structure 25. The upper ends of the plurality of field regions 47 may be located on the first main surface 3 side relative to a depth position of at least one of the bottom walls of the gate structure 15, the source structure 20, and the dummy structure 25.

[0462] 12H (eighth modified example), second periphery structure 42 may include one or more (multiple in this embodiment) field regions 47 formed deeper than termination region 45. The bottoms of the multiple field regions 47 may be located closer to the bottom of second semiconductor region 7 than the depth position of the bottom of at least one type of well region 30 (at least one of gate well region 30g, source well region 30s, and dummy well region 30d).

[0463] The bottoms of the plurality of field regions 47 may be located closer to the first main surface 3 than the depth position of the intermediate portion of the second semiconductor region 7. The bottoms of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the intermediate portion of the second semiconductor region 7.

[0464] The upper ends of the plurality of field regions 47 may be located closer to the first main surface 3 than the depth position of the upper end of the termination region 45. The upper ends of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the upper end of the termination region 45. The upper ends of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the termination region 45.

[0465] The upper ends of the plurality of field regions 47 may be located closer to the first main surface 3 than a depth position of at least one of the bottom walls of the gate structure 15, the source structure 20, and the dummy structure 25. The upper ends of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than a depth position of at least one of the bottom walls of the gate structure 15, the source structure 20, and the dummy structure 25.

[0466] The upper ends of the plurality of field regions 47 may be located closer to the first main surface 3 than the depth position of the bottom of at least one type of well region 30. The upper ends of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of at least one type of well region 30.

[0467] 12I (ninth modified example), the second peripheral structure 42 may include a plurality of field regions 47 each having a bottom located at a different depth. The depth positions of the bottoms of the plurality of field regions 47 may increase sequentially toward the periphery of the first main surface 3.

[0468] That is, the depth position of the bottom of one or more field regions 47 located on the peripheral edge side of first main surface 3 may be greater than the depth position of the bottom of one or more field regions 47 located on the inward side of first main surface 3. Of course, the depth positions of the bottoms of the multiple field regions 47 may increase toward the peripheral edge side of first main surface 3 in units of two or more groups, each group including two or more field regions 47.

[0469] The field regions 47 may have different depths (thicknesses) from one another. The depths of the field regions 47 may increase sequentially toward the periphery of the first main surface 3.

[0470] That is, the depth of one or more field regions 47 located on the peripheral side of first main surface 3 may be greater than the depth of one or more field regions 47 located on the inward side of first main surface 3. The depth of the multiple field regions 47 may increase toward the peripheral side of first main surface 3 in units of two or more groups, each group including two or more field regions 47.

[0471] The field regions 47 may have substantially the same depth (thickness). That is, the distance between the first main surface 3 and the upper ends of the field regions 47 may increase toward the periphery of the first main surface 3. As in the other modifications, the one or more field regions 47 may be formed at a distance from the first main surface 3, or may be exposed from the first main surface 3.

[0472] 12J (tenth modified example), the second periphery structure 42 may include a plurality of field regions 47 each having a bottom located at a different depth. The depth positions of the bottoms of the plurality of field regions 47 may decrease sequentially toward the periphery of the first main surface 3.

[0473] In other words, the depth position of the bottom of one or more field regions 47 located on the peripheral side of first main surface 3 may be smaller than the depth position of the bottom of one or more field regions 47 located on the inward side of first main surface 3. Of course, the depth positions of the bottoms of the multiple field regions 47 may decrease toward the peripheral side of first main surface 3 in two or more groups, each group including two or more field regions 47.

[0474] The field regions 47 may have different depths (thicknesses) from one another. The depths of the field regions 47 may decrease sequentially toward the periphery of the first main surface 3.

[0475] That is, the depth of one or more field regions 47 located on the peripheral side of first main surface 3 may be smaller than the depth of one or more field regions 47 located on the inward side of first main surface 3. The depth of the multiple field regions 47 may decrease toward the peripheral side of first main surface 3 in two or more groups, each group including two or more field regions 47.

[0476] The field regions 47 may have substantially the same depth. That is, the distance between the first main surface 3 and the upper ends of the field regions 47 may decrease toward the periphery of the first main surface 3. As in the other modifications, the one or more field regions 47 may be formed at a distance from the first main surface 3, or may be exposed from the first main surface 3.

[0477] As described above, semiconductor device 1A may include chip 2, n-type (first conductivity type) second semiconductor region 7 (semiconductor region), and p-type (second conductivity type) termination region 45. Chip 2 may have first main surface 3. Second semiconductor region 7 may be formed in a surface layer portion of first main surface 3. Termination region 45 may be formed in a surface layer portion of second semiconductor region 7 at a periphery of first main surface 3 and spaced apart from first main surface 3 in the thickness direction of chip 2.

[0478] This configuration provides a semiconductor device 1A having a novel layout. For example, in this semiconductor device 1A, the extension range of the depletion layer can be adjusted by the termination region 45 spaced apart from the first main surface 3. This layout is effective in improving the breakdown voltage of the semiconductor device 1A.

[0479] The chip 2 may include SiC. This configuration provides the semiconductor device 1A as a SiC semiconductor device having a novel layout. The physical properties of SiC further improve the breakdown voltage of the SiC semiconductor device. In particular, since SiC semiconductor devices are used in relatively high-voltage environments, the effect of improving the breakdown voltage provided by the termination region 45 is effective.

[0480] Termination region 45 may form a pn junction with second semiconductor region 7. This configuration allows the depletion layer originating from termination region 45 to expand appropriately. Termination region 45 may face first main surface 3 with part of second semiconductor region 7 interposed therebetween.

[0481] According to this configuration, termination region 45 can have an upper end portion that forms a pn junction with second semiconductor region 7. Therefore, a depletion layer originating from termination region 45 can also extend to a portion of second semiconductor region 7 that is located between first main surface 3 and termination region 45.

[0482] Termination region 45 may have a thickness (depth) greater than the distance between first main surface 3 and termination region 45. According to this configuration, termination region 45 having a thickness greater than the distance between first main surface 3 and termination region 45 can adjust the extension range of the depletion layer.

[0483] The termination region 45 may be formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3. According to this configuration, the extension range of the depletion layer can be adjusted by the termination region 45 spaced apart from the bottom of the second semiconductor region 7.

[0484] Termination region 45 may have a thickness (depth) that is less than the distance between the bottom of second semiconductor region 7 and termination region 45. According to this configuration, termination region 45 having a thickness that is less than the distance between the bottom of second semiconductor region 7 and termination region 45 can adjust the extension range of the depletion layer.

[0485] The semiconductor device 1A may include a p-type outer well region 43. The outer well region 43 may be formed in a surface layer portion of the first main surface 3 at the periphery of the first main surface 3. In this case, the termination region 45 may be formed in a region between the periphery of the first main surface 3 and the outer well region 43.

[0486] According to this configuration, the depletion layer expands from the outer well region 43 on the inner side of the first main surface 3, and at the same time, the depletion layer expands from the termination region 45 on the peripheral side of the first main surface 3. This can improve the breakdown voltage of the semiconductor device 1A.

[0487] Termination region 45 may be connected to outer well region 43. With this configuration, the depletion layer extending from termination region 45 can be integrated with the depletion layer extending from outer well region 43. This reduces discontinuity of the depletion layer within chip 2, and can improve the breakdown voltage of semiconductor device 1A.

[0488] Termination region 45 may have a bottom located below the depth position of the bottom of outer well region 43. With this configuration, the extension range of the depletion layer can be adjusted by termination region 45 having a bottom located below the bottom of outer well region 43. This layout is effective in improving the breakdown voltage of semiconductor device 1A.

[0489] The semiconductor device 1A may include a p-type outer contact region 44. The outer contact region 44 may be formed in a surface layer portion of the outer well region 43 and may have a p-type impurity concentration higher than the p-type impurity concentration of the outer well region 43. According to this configuration, the outer contact region 44 improves the electrical response speed of the outer well region 43.

[0490] Termination region 45 may have a p-type impurity concentration lower than the p-type impurity concentration of outer contact region 44. With this configuration, the extension range of the depletion layer can be adjusted by termination region 45 having a p-type impurity concentration lower than the p-type impurity concentration of outer contact region 44. This layout is effective in improving the breakdown voltage of semiconductor device 1A.

[0491] The semiconductor device 1A may include a termination wiring 65 (termination electrode) disposed on the first main surface 3 and electrically connected to the termination region 45. With this configuration, a predetermined termination potential is applied to the termination region 45 via the termination wiring 65. This allows the termination wiring 65 to improve the electrical response characteristics of the termination region 45. The termination potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be ground potential. The termination potential may be source potential.

[0492] In this case, the semiconductor device 1A may include a p-type outer well region 43. The outer well region 43 may be formed in a surface portion of the first main surface 3 at the periphery of the first main surface 3. In this case, the termination region 45 may be formed in a region between the periphery of the first main surface 3 and the outer well region 43 so as to be electrically connected to the outer well region 43. The termination wiring 65 may be electrically connected to the outer well region 43.

[0493] According to this configuration, a depletion layer expands from the outer well region 43 on the inner side of the first main surface 3, and at the same time, a depletion layer expands from the termination region 45 on the peripheral side of the first main surface 3. Furthermore, the electrical response speed of the outer well region 43 and the electrical response speed of the termination region 45 can be improved by the termination wiring 65.

[0494] The semiconductor device 1A may include a p-type outer contact region 44. The outer contact region 44 may be formed in a surface layer portion of the outer well region 43 and may have a p-type impurity concentration higher than the p-type impurity concentration of the outer well region 43. In this case, the termination wiring 65 may be electrically connected to the outer well region 43 via the outer contact region 44.

[0495] According to this configuration, the electrical response speed of the outer well region 43 can be improved by the outer contact region 44 and the termination wiring 65. Furthermore, the ohmic properties of the termination wiring 65 with respect to the outer well region 43 can be improved by the outer contact region 44.

[0496] The semiconductor device 1A may include an interlayer film 52 (insulating film) covering the first main surface 3. The semiconductor device 1A may include an outer opening 54 (contact opening) formed in the interlayer film 52 so as to expose the outer contact region 44.

[0497] In this case, the termination wiring 65 may be disposed on the interlayer film 52 and electrically connected to the outer contact region 44 through the outer opening 54. With this configuration, the termination wiring 65 can be appropriately electrically connected to the outer contact region 44.

[0498] The semiconductor device 1A may include an active region 8 provided in an inner portion of the first main surface 3, and a peripheral region 9 provided in a peripheral portion of the first main surface 3. In this case, the termination region 45 may be formed in the peripheral region 9. According to this configuration, the breakdown voltage of the semiconductor device 1A can be improved by utilizing the termination region 45 formed in the peripheral region 9 outside the active region 8.

[0499] Termination region 45 may extend in a strip shape along active region 8 in a plan view. With this configuration, the breakdown voltage of semiconductor device 1A can be improved by termination region 45 extending in a strip shape along active region 8. Termination region 45 may surround active region 8 in a plan view. With this configuration, the breakdown voltage of semiconductor device 1A can be improved by termination region 45 surrounding active region 8.

[0500] The semiconductor device 1A may include a transistor structure Tr formed in the active region 8. According to this configuration, the breakdown voltage of the semiconductor device 1A including the transistor structure Tr can be improved by the termination region 45 formed in the peripheral region 9.

[0501] The semiconductor device 1A may include a p-type field region 47. The field region 47 may be formed in a surface layer portion of the second semiconductor region 7 in a region between the periphery of the first main surface 3 and the termination region 45.

[0502] According to this configuration, the depletion layer expands from the termination region 45 on the inner side of the first main surface 3, and at the same time, the depletion layer expands from the field region 47 on the peripheral side of the first main surface 3. This can improve the breakdown voltage of the semiconductor device 1A.

[0503] From another perspective, semiconductor device 1A may include chip 2, n-type (first conductivity type) second semiconductor region 7 (semiconductor region), and p-type (second conductivity type) field region 47. Chip 2 may have a first main surface 3. Second semiconductor region 7 may be formed in a surface layer portion of first main surface 3. Field region 47 may be formed in a surface layer portion of second semiconductor region 7 at a periphery of first main surface 3 and spaced apart from first main surface 3 in the thickness direction of chip 2.

[0504] This configuration provides a semiconductor device 1A having a novel layout. For example, in this semiconductor device 1A, the extension range of the depletion layer can be adjusted by the field region 47 spaced apart from the first main surface 3. This layout is effective in improving the breakdown voltage of the semiconductor device 1A.

[0505] The chip 2 may include SiC. This configuration provides the semiconductor device 1A as a SiC semiconductor device having a novel layout. The physical properties of SiC further improve the breakdown voltage of the SiC semiconductor device. In particular, since SiC semiconductor devices are used in relatively high-voltage environments, the effect of improving the breakdown voltage provided by the field region 47 is effective.

[0506] Field region 47 may form a pn junction with second semiconductor region 7. With this configuration, the depletion layer originating from field region 47 can be appropriately expanded. Field region 47 may face first main surface 3 with part of second semiconductor region 7 interposed therebetween. With this configuration, the depletion layer originating from field region 47 also expands to a portion of second semiconductor region 7 that is located between first main surface 3 and field region 47.

[0507] Field region 47 may have a thickness (depth) greater than the distance between first main surface 3 and field region 47. According to this configuration, the extension range of the depletion layer can be adjusted by field region 47 having a thickness greater than the distance between first main surface 3 and field region 47.

[0508] The field region 47 may be formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3. According to this configuration, the extension range of the depletion layer can be adjusted by the field region 47 spaced apart from the bottom of the second semiconductor region 7.

[0509] Field region 47 may have a thickness (depth) that is less than the distance between the bottom of second semiconductor region 7 and field region 47. According to this configuration, the extension range of the depletion layer can be adjusted by field region 47 having a thickness that is less than the distance between the bottom of second semiconductor region 7 and field region 47.

[0510] Field region 47 may extend in a strip shape along the periphery of first main surface 3. With this configuration, the breakdown voltage of semiconductor device 1A can be improved by field region 47 extending in a strip shape along the periphery of first main surface 3. Field region 47 may surround an inner portion of first main surface 3 in a plan view. With this configuration, the breakdown voltage of semiconductor device 1A can be improved by field region 47 surrounding the inner portion of first main surface 3.

[0511] A plurality of field regions 47 may be formed at intervals in a surface layer portion of the second semiconductor region 7. With this configuration, the plurality of field regions 47 can improve the breakdown voltage of the semiconductor device 1A. The plurality of field regions 47 may have the same depth as one another. With this configuration, the plurality of field regions 47 having the same depth as one another can improve the breakdown voltage of the semiconductor device 1A.

[0512] Semiconductor device 1A may include an active region 8 provided in an inner portion of first main surface 3 and a peripheral region 9 provided in a peripheral portion of first main surface 3. In this case, field region 47 may be formed in peripheral region 9. According to this configuration, by utilizing field region 47 formed in peripheral region 9 outside active region 8, the breakdown voltage of semiconductor device 1A can be improved.

[0513] Field region 47 may extend in a strip shape along active region 8 in a plan view. With this configuration, the breakdown voltage of semiconductor device 1A can be improved by field region 47 extending in a strip shape along active region 8. Field region 47 may surround active region 8 in a plan view. With this configuration, the breakdown voltage of semiconductor device 1A can be improved by field region 47 surrounding active region 8.

[0514] The semiconductor device 1A may include a transistor structure Tr formed in the active region 8. According to this configuration, the breakdown voltage of the semiconductor device 1A including the transistor structure Tr can be improved by the field region 47 formed in the peripheral region 9.

[0515] The semiconductor device 1A may include a p-type termination region 45. The termination region 45 may be formed in a surface layer portion of the second semiconductor region 7 in the peripheral portion of the first main surface 3. In this case, the field region 47 may be formed in the surface layer portion of the second semiconductor region 7 in a region between the peripheral portion of the first main surface 3 and the termination region 45.

[0516] According to this configuration, the depletion layer expands from the termination region 45 on the inner side of the first main surface 3, and at the same time, the depletion layer expands from the field region 47 on the peripheral side of the first main surface 3. This can improve the breakdown voltage of the semiconductor device 1A.

[0517] The field region 47 may be formed to be narrower than the termination region 45. According to this configuration, the field region 47 being narrower than the termination region 45 can improve the breakdown voltage of the semiconductor device 1A.

[0518] The semiconductor device 1A may include a p-type outer well region 43. The outer well region 43 may be formed in a surface layer portion of the first main surface 3 at the periphery of the first main surface 3. In this case, the termination region 45 may be formed in a region between the periphery of the first main surface 3 and the outer well region 43.

[0519] According to this configuration, the depletion layer expands from the outer well region 43 on the inner side of the first main surface 3, and at the same time, the depletion layer expands from the termination region 45 on the peripheral side of the first main surface 3. This can improve the breakdown voltage of the semiconductor device 1A.

[0520] The semiconductor device 1A may include a p-type outer contact region 44. The outer contact region 44 may be formed in a surface layer portion of the outer well region 43 and may have a p-type impurity concentration higher than the p-type impurity concentration of the outer well region 43. According to this configuration, the outer contact region 44 improves the electrical response speed of the outer well region 43.

[0521] The semiconductor device 1A may include a termination wiring 65 (termination electrode) disposed on the first main surface 3 and electrically connected to the termination region 45. With this configuration, a predetermined termination potential is applied to the termination region 45 via the termination wiring 65. This allows the termination wiring 65 to improve the electrical response characteristics of the termination region 45. The termination potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be ground potential. The termination potential may be source potential.

[0522] Fig. 13 is a cross-sectional view showing a main part of the active region 8 of the semiconductor device 1B according to the second embodiment. Fig. 14 is a cross-sectional view showing a main part of the active region 8 of the semiconductor device 1B shown in Fig. 13. Fig. 15 is a cross-sectional view showing the peripheral region 9 of the semiconductor device 1B shown in Fig. 13 together with the peripheral structure 40 according to the first embodiment.

[0523] 13 to 15, semiconductor device 1B has a configuration obtained by modifying the configurations of multiple gate structures 15, multiple source structures 20, and multiple dummy structures 25 of semiconductor device 1A. Specifically, semiconductor device 1B has multiple source structures 20 having a depth greater than that of multiple gate structures 15.

[0524] The ratio (depth ratio) of the depth of the source structure 20 to the depth of the gate structure 15 may be 1.5 or more and 2.5 or less. The depth ratio may have a value belonging to at least one of the ranges of 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, and 2.25 or more and 2.5 or less.

[0525] The semiconductor device 1B has a plurality of dummy structures 25 having a depth greater than that of the plurality of gate structures 15. The depth of the plurality of dummy structures 25 is preferably approximately equal to the depth of the plurality of source structures 20. Of course, the depth of the plurality of dummy structures 25 may be greater than or less than the depth of the plurality of source structures 20.

[0526] The ratio (depth ratio) of the depth of the dummy structure 25 to the depth of the gate structure 15 may be 1.5 or more and 2.5 or less. The depth ratio may have a value belonging to at least one of the ranges of 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, and 2.25 or more and 2.5 or less.

[0527] The bottom of the outer well region 43 may be formed at a distance toward the first main surface 3 from the depth positions of the bottom walls of the plurality of source structures 20. The bottom of the outer well region 43 may be formed at a distance toward the first main surface 3 from the depth positions of the bottom walls of the plurality of dummy structures 25.

[0528] The bottom of the outer contact region 44 may be formed at a distance toward the first main surface 3 from the depth positions of the bottom walls of the plurality of source structures 20. The bottom of the outer contact region 44 may be formed at a distance toward the first main surface 3 from the depth positions of the bottom walls of the plurality of dummy structures 25.

[0529] The bottom of termination region 45 may be formed at a distance toward first main surface 3 from the depth positions of the bottom walls of the plurality of source structures 20. The bottom of termination region 45 may be formed at a distance toward first main surface 3 from the depth positions of the bottom walls of the plurality of dummy structures 25.

[0530] The bottoms of the plurality of field regions 47 may be formed at intervals toward the first main surface 3 from the depth positions of the bottom walls of the plurality of source structures 20. The bottoms of the plurality of field regions 47 may be formed at intervals toward the first main surface 3 from the depth positions of the bottom walls of the plurality of dummy structures 25.

[0531] Other configurations and descriptions of the semiconductor device 1B are the same as those of the semiconductor device 1A. Of course, like the semiconductor device 1A, the semiconductor device 1B can include any one of the peripheral structures 40 according to the first to fifth embodiments (see also FIGS. 10A to 10E).

[0532] Furthermore, the semiconductor device 1B may include any one of the features of the first peripheral structure 41 according to the first to fifth embodiments (see also FIGS. 11A to 11J). Of course, the features of the first peripheral structure 41 according to the first to tenth modifications may be combined as appropriate.

[0533] Therefore, the semiconductor device 1B can simultaneously include at least two of the features of the first peripheral structure 41 according to the first to tenth modified examples in the same or different regions with respect to the first peripheral structure 41 according to the first to fifth embodiment examples.

[0534] At least one feature of the outer well region 43, outer contact region 44, and termination region 45 according to the first to tenth modified examples is appropriately selected depending on the configuration of the first to fifth embodiment examples, and is applied to the configuration of the first to fifth embodiment examples.

[0535] The semiconductor device 1B may include any one of the features of the second peripheral structures 42 according to the first to tenth modified examples in relation to the second peripheral structures 42 according to the first to fifth embodiments (see also FIGS. 12A to 12J). Of course, the features of the second peripheral structures 42 according to the first to tenth modified examples may be combined as appropriate.

[0536] Therefore, the semiconductor device 1B can simultaneously include, in the same or different regions, at least two of the features of the second peripheral structures 42 according to the first to tenth modifications in the second peripheral structures 42 according to the first to fifth embodiments. At least one feature of the field region 47 according to the first to tenth modifications is selected appropriately depending on the configurations of the first to fifth embodiments, and is applied to the configurations of the first to fifth embodiments.

[0537] The semiconductor device 1B can include one or more of the features of the first peripheral structure 41 according to the first to tenth modified examples, and one or more of the features of the second peripheral structure 42 according to the first to tenth modified examples, together with the configuration of any one of the first to fifth embodiment examples.

[0538] Fig. 16 is an enlarged plan view showing a main portion of the active region 8 of a semiconductor device 1C according to the third embodiment. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 16. Fig. 18 is a cross-sectional view taken along line XVIII-XVIII shown in Fig. 16. Fig. 19 is a cross-sectional view showing a main portion of the active region 8 of the semiconductor device 1C shown in Fig. 16.

[0539] 16 to 19, semiconductor device 1C has a configuration in which the configurations of gate structures 15, source structures 20 and dummy structures 25 in semiconductor device 1A are modified.

[0540] Specifically, unlike the semiconductor device 1A, the semiconductor device 1C includes a plurality of gate structures 15 and a plurality of dummy structures 25, but does not include a plurality of source structures 20. In this embodiment, the plurality of gate structures 15 are arranged adjacent to each other at intervals in the first direction X (= m-axis direction), and each extends in a strip shape in the second direction Y (= a-axis direction).

[0541] The plurality of dummy structures 25 are arranged on the periphery of the active region 8 at intervals from the group of structures including the plurality of gate structures 15. The plurality of dummy structures 25 may each be formed in a polygonal ring shape (quadratic ring shape) that collectively surrounds the group of structures including the plurality of gate structures 15 in a plan view.

[0542] It is preferable that the depth of the plurality of dummy structures 25 is approximately equal to the depth of the plurality of gate structures 15. Of course, the depth of the plurality of dummy structures 25 may be greater than the depth of the plurality of gate structures 15 or may be smaller than the depth of the plurality of gate structures 15.

[0543] Unlike the semiconductor device 1A, the semiconductor device 1C includes a plurality of gate well regions 30g and a plurality of dummy well regions 30d, but does not include a plurality of source well regions 30s. The plurality of gate well regions 30g and the plurality of dummy well regions 30d have the same shapes as those in the semiconductor device 1A.

[0544] The semiconductor device 1C includes a plurality of gate contact regions 31g and a plurality of dummy contact regions 31d, but does not include a plurality of source contact regions 31s. The plurality of gate contact regions 31g and the plurality of dummy contact regions 31d have the same shapes as those in the semiconductor device 1A.

[0545] With respect to one gate structure 15 and the other gate structure 15, the multiple gate contact regions 31g along one gate structure 15 face the multiple gate contact regions 31g along the other gate structure 15 in the first direction X in a plan view.

[0546] That is, the plurality of gate contact regions 31g are generally arranged in a matrix in plan view at intervals in the first direction X and the second direction Y. In this case, the plurality of gate contact regions 31g along one gate structure 15 may be connected to the plurality of gate contact regions 31g along the other gate structure 15 in the surface layer portion of the body region 10.

[0547] Of course, the plurality of gate contact regions 31g along one gate structure 15 may face, in plan view, a region between the plurality of gate contact regions 31g along the other gate structure 15 in the first direction X. In other words, the plurality of gate contact regions 31g may be arranged in a staggered pattern overall in plan view with intervals in the first direction X and the second direction Y.

[0548] Similar to the semiconductor device 1A, the semiconductor device 1C includes a plurality of source openings 53 formed in the interlayer film 52. In this embodiment, the plurality of source openings 53 are formed in regions between adjacent gate structures 15, respectively, and expose the source region 11 and the plurality of gate contact regions 31g, respectively.

[0549] Similar to the semiconductor device 1A, the semiconductor device 1C includes a source electrode 60 disposed on the first main surface 3. The source electrode 60 has a layered structure including a lower electrode film 61 and a main electrode film 62, which are layered in this order from the chip 2 side. Similar to the semiconductor device 1A, the lower electrode film 61 has a layered structure including a first electrode film 63 and a second electrode film 64.

[0550] The first electrode film 63 collectively covers the region of the interlayer film 52 where the plurality of source openings 53 are formed, and extends into the plurality of source openings 53 from above the interlayer film 52. The first electrode film 63 is mechanically and electrically connected to the source region 11 and the plurality of gate contact regions 31g within the plurality of source openings 53.

[0551] The second electrode film 64 collectively covers the region of the interlayer film 52 where the plurality of source openings 53 are formed, sandwiching the first electrode film 63 therebetween, and extends into the plurality of source openings 53 from above the interlayer film 52. The second electrode film 64 is electrically connected to the source region 11 and the plurality of gate contact regions 31g via the first electrode film 63 within the plurality of source openings 53.

[0552] The main electrode film 62 collectively covers the region of the interlayer film 52 where the plurality of source openings 53 are formed, and backfills the plurality of source openings 53. The main electrode film 62 is electrically connected to the source region 11 and the plurality of gate contact regions 31g via the lower electrode film 61 within the plurality of source openings 53.

[0553] Other configurations and descriptions of the semiconductor device 1C are the same as those of the semiconductor device 1A. As with the semiconductor device 1A, the semiconductor device 1C can include any one of the peripheral structures 40 according to the first to fifth embodiments (see also FIGS. 10A to 10E).

[0554] Furthermore, the semiconductor device 1C may include any one of the features of the first peripheral structure 41 according to the first to fifth embodiments (see also FIGS. 11A to 11J). Of course, the features of the first peripheral structure 41 according to the first to tenth modifications may be combined as appropriate.

[0555] Therefore, the semiconductor device 1C can simultaneously include at least two of the features of the first peripheral structure 41 according to the first to tenth modified examples in the same or different regions with respect to the first peripheral structure 41 according to the first to fifth embodiment examples.

[0556] At least one feature of the outer well region 43, outer contact region 44, and termination region 45 according to the first to tenth modified examples is appropriately selected depending on the configuration of the first to fifth embodiment examples, and is applied to the configuration of the first to fifth embodiment examples.

[0557] The semiconductor device 1C may include any one of the features of the second peripheral structures 42 according to the first to tenth modified examples in relation to the second peripheral structures 42 according to the first to fifth embodiments (see also FIGS. 12A to 12J). Of course, the features of the second peripheral structures 42 according to the first to tenth modified examples may be combined as appropriate.

[0558] Therefore, the semiconductor device 1C can simultaneously include, in the same or different regions, at least two of the features of the second peripheral structures 42 according to the first to tenth modifications in the second peripheral structures 42 according to the first to fifth embodiments. At least one feature of the field region 47 according to the first to tenth modifications is selected appropriately depending on the configuration of the first to fifth embodiments, and is applied to the configuration of the first to fifth embodiments.

[0559] The semiconductor device 1C can include one or more of the features of the first peripheral structure 41 according to the first to tenth modified examples, and one or more of the features of the second peripheral structure 42 according to the first to tenth modified examples, together with the configuration of any one of the first to fifth embodiment examples.

[0560] Fig. 20 is a plan view showing a semiconductor device 1D according to a fourth embodiment. Fig. 21 is a cross-sectional view taken along line XXI-XXI shown in Fig. 20. Fig. 22 is a perspective view showing the shape of a chip 2. Fig. 23 is a plan view showing an example layout of a first main surface 3.

[0561] Fig. 24 is an enlarged plan view showing a main part of the first main surface 3 shown in Fig. 23. Fig. 25 is an enlarged plan view showing a main part of the first main surface 3 shown in Fig. 23. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI shown in Fig. 25. Fig. 27 is a cross-sectional view showing the cross-sectional structure of the outer periphery region 9 taken along line XXVII-XXVII shown in Fig. 20, together with the outer periphery structure 40 according to the first embodiment.

[0562] Similar to the semiconductor device 1A, the semiconductor device 1D includes a chip 2, a first semiconductor region 6, and a second semiconductor region 7. The semiconductor device 1D includes a first surface portion 71, a second surface portion 72, and first to fourth connection surface portions 73A to 73D formed on the first main surface 3.

[0563] The first surface 71, the second surface 72, and the first to fourth connection surface portions 73A to 73D define a mesa on the first main surface 3. The first surface 71, the second surface 72, and the first to fourth connection surface portions 73A to 73D (i.e., the mesa) may be considered to be components of the chip 2 (first main surface 3).

[0564] The first surface portion 71 may be referred to as the "active surface," the second surface portion 72 may be referred to as the "outer surface," the first to fourth connecting surface portions 73A to 73D may be referred to as "connecting surfaces," and the mesa may be referred to as the "active mesa."

[0565] The first surface portion 71 is defined in an inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The first surface portion 71 has a flat surface extending in the horizontal direction and is formed by the c-plane (Si-plane). In this embodiment, the first surface portion 71 is formed in a polygonal shape (specifically, a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0566] The ratio (area ratio) of the planar area of ​​the first surface portion 71 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may be 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and 0.95 or less.

[0567] The second surface 72 is located closer to the periphery of the first main surface 3 than the first surface 71, and is recessed from the height of the first surface 71 in the thickness direction of the chip 2 (toward the second main surface 4). The second surface 72 extends in a strip shape along the first surface 71 in a plan view, and is formed in a polygonal ring shape (specifically, a quadrangular ring) surrounding the first surface 71. The second surface 72 is continuous with the first to fourth side surfaces 5A to 5D.

[0568] The second surface 72 is formed substantially parallel to the first surface 71 and has a flat surface extending horizontally. In this embodiment, the second surface 72 is formed by the c-plane (Si-plane). The second surface 72 is formed in the second semiconductor region 7 at a distance from the first semiconductor region 6. In other words, the second surface 72 is recessed to a depth less than the thickness of the second semiconductor region 7, exposing the second semiconductor region 7.

[0569] The second surface portion 72 may have a depth of 0.1 μm to 3 μm. The depth of the second surface portion 72 may have a value belonging to at least one of the ranges of 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0570] The first to fourth connection surface portions 73A to 73D extend in the vertical direction Z and are connected to the first surface portion 71 and the second surface portion 72. The first connection surface portion 73A is located on the first side surface 5A side, the second connection surface portion 73B is located on the second side surface 5B side, the third connection surface portion 73C is located on the third side surface 5C side, and the fourth connection surface portion 73D is located on the fourth side surface 5D side.

[0571] The first connecting surface 73A and the second connecting surface 73B extend in the first direction X and face each other in the second direction Y. The third connecting surface 73C and the fourth connecting surface 73D extend in the second direction Y and face each other in the first direction X.

[0572] In this way, the mesa is defined in a protruding (convex) shape on the first main surface 3. The mesa is formed only in the second semiconductor region 7, and not in the first semiconductor region 6. The first to fourth connection surface portions 73A to 73D may extend substantially perpendicularly between the first surface portion 71 and the second surface portion 72, and define a mesa in the shape of a quadrangular pillar.

[0573] The first to fourth connection surface portions 73A to 73D may be inclined obliquely downward toward the first surface portion 71 and the second surface portion 72, and may define a mesa having a truncated quadrangular pyramid shape. The first to fourth connection surface portions 73A to 73D may be inclined at an angle greater than 90° and equal to or less than 135° with respect to the first surface portion 71.

[0574] Similar to the semiconductor device 1A, the semiconductor device 1D includes an active region 8 and a peripheral region 9. In this embodiment, the active region 8 is set on a first surface portion 71. The peripheral region 9 is set on a second surface portion 72.

[0575] That is, the active region 8 is set in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view, following the first surface portion 71. The peripheral region 9 is set in a polygonal ring shape (a square ring shape in this embodiment) that extends in a strip shape along the active region 8, following the second surface portion 72, and surrounds the active region 8.

[0576] Similar to the semiconductor device 1A, the semiconductor device 1D includes a p-type body region 10 formed in a surface layer portion of the first main surface 3 in an inner portion of the first main surface 3. In this embodiment, the body region 10 is formed in a surface layer portion of the first surface portion 71. The body region 10 is formed at an interval from the bottom of the second semiconductor region 7 toward the first surface portion 71, and faces the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0577] The body region 10 is formed at a distance from the depth position of the second surface portion 72 toward the first surface portion 71, and extends in a layered manner along the first surface portion 71. In this embodiment, the body region 10 is formed over the entire first surface portion 71 and is exposed from the first to fourth connection surface portions 73A to 73D. Of course, the body region 10 may also be formed at a distance inward from the periphery of the first surface portion 71.

[0578] Similar to the semiconductor device 1A, the semiconductor device 1D includes an n-type source region 11 formed in a surface layer portion of the first main surface 3, in an inner portion of the first main surface 3. In this embodiment, the source region 11 is formed in a surface layer portion of the body region 10 in the first surface portion 71, with a gap therebetween from a depth position of the bottom of the body region 10 toward the first surface portion 71.

[0579] The source region 11 extends in a layered manner along the first surface portion 71. In this embodiment, the source region 11 is formed over the entire first surface portion 71 and is exposed from the first to fourth connection surface portions 73A to 73D. Of course, the source region 11 may also be formed at an interval inward from the periphery of the first surface portion 71.

[0580] Similar to the semiconductor device 1A, the semiconductor device 1D includes a plurality of gate structures 15 formed on the first main surface 3 in an inner portion of the first main surface 3. In this embodiment, the plurality of gate structures 15 are formed in the inner portion of the first surface 71 at intervals from the periphery of the first surface 71.

[0581] In this embodiment, the multiple gate structures 15 are formed at intervals from the depth position of the bottom of the second semiconductor region 7 toward the first surface portion 71, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.

[0582] In this embodiment, the plurality of gate structures 15 have a depth that is approximately equal to the depth of the second surface portion 72. Of course, the depth of the plurality of gate structures 15 may be greater than the depth of the second surface portion 72, or may be less than the depth of the second surface portion 72. Additionally, the description of the gate structure 15 of the semiconductor device 1D can be obtained by replacing the "first main surface 3" with the "first surface portion 71" in the description of the gate structure 15 of the semiconductor device 1A.

[0583] Similar to the semiconductor device 1A, the semiconductor device 1D includes a plurality of source structures 20 formed on the first main surface 3 in an inner portion of the first main surface 3. In this embodiment, the plurality of source structures 20 are formed in the inner portion of the first surface 71 at intervals from the periphery of the first surface 71.

[0584] In this embodiment, the multiple source structures 20 are formed at intervals from the depth position of the bottom of the second semiconductor region 7 toward the first surface portion 71, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.

[0585] In this embodiment, the plurality of source structures 20 have a depth that is approximately equal to the depth of the second surface portion 72. Of course, the depth of the plurality of source structures 20 may be greater than the depth of the second surface portion 72, or may be less than the depth of the second surface portion 72. Additionally, the description of the source structure 20 of the semiconductor device 1D can be obtained by replacing the "first main surface 3" with the "first surface portion 71" in the description of the source structure 20 of the semiconductor device 1A.

[0586] Similar to the semiconductor device 1A, the semiconductor device 1D includes one or more (multiple in this embodiment) dummy structures 25 formed on the first main surface 3 at the periphery of the active region 8. In this embodiment, the multiple dummy structures 25 are formed on the periphery of the first surface 71 at intervals from the periphery of the first surface 71.

[0587] In this embodiment, the multiple dummy structures 25 are formed in a region on the third connection surface 73C side and a region on the fourth connection surface 73D side in the peripheral portion of the first surface 71. In this embodiment, the multiple dummy structures 25 are arranged at intervals from each other in the first direction X and are each formed in a strip shape extending in the second direction Y. Of course, the multiple dummy structures 25 may be formed in a ring shape on the first surface 71 surrounding the multiple gate structures 15 and the multiple source structures 20, as in the case of the semiconductor device 1A.

[0588] In this embodiment, the plurality of dummy structures 25 have a depth that is approximately equal to the depth of the second surface portion 72. Of course, the depth of the plurality of dummy structures 25 may be greater than the depth of the second surface portion 72, or may be less than the depth of the second surface portion 72. Additionally, the description of the dummy structures 25 of the semiconductor device 1D can be obtained by replacing the "first main surface 3" with the "first surface portion 71" in the description of the dummy structures 25 of the semiconductor device 1A.

[0589] Similar to the semiconductor device 1A, the semiconductor device 1D includes a plurality of well regions 30 formed in the chip 2 (second semiconductor region 7) in the active region 8. The plurality of well regions 30 include a plurality of gate well regions 30g, a plurality of source well regions 30s, and a plurality of dummy well regions 30d.

[0590] Similar to the semiconductor device 1A, the multiple gate well regions 30g are formed at intervals in the horizontal direction (first direction X) in regions directly below the multiple gate structures 15. In this embodiment, the bottoms of the multiple gate well regions 30g are located closer to the bottom of the second semiconductor region 7 than the depth position of the second surface portion 72.

[0591] As in the semiconductor device 1A, the plurality of source well regions 30s are formed in regions immediately below the plurality of source structures 20, spaced apart in the horizontal direction (first direction X) from the plurality of gate well regions 30g. In this embodiment, the bottoms of the plurality of source well regions 30s are located closer to the bottom of the second semiconductor region 7 than the depth position of the second surface portion 72.

[0592] Similar to the semiconductor device 1A, the plurality of dummy well regions 30d are formed in regions directly below the plurality of dummy structures 25, spaced apart in the horizontal direction from the plurality of gate well regions 30g and the plurality of source well regions 30s. In this embodiment, the bottoms of the plurality of dummy well regions 30d are located closer to the bottom of the second semiconductor region 7 than the depth position of the second surface portion 72.

[0593] Similar to the semiconductor device 1A, the semiconductor device 1D includes a plurality of contact regions 31 formed in the chip 2 (second semiconductor region 7). The plurality of contact regions 31 include a plurality of gate contact regions 31g, a plurality of source contact regions 31s, and a plurality of dummy contact regions 31d.

[0594] The description of the plurality of gate contact regions 31g, the plurality of source contact regions 31s and the plurality of dummy contact regions 31d relating to semiconductor device 1D can be obtained by replacing "first main surface 3" with "first surface portion 71" in the description of the plurality of gate contact regions 31g, the plurality of source contact regions 31s and the plurality of dummy contact regions 31d relating to semiconductor device 1A.

[0595] Similar to the semiconductor device 1A, the semiconductor device 1D includes one of the peripheral structures 40 according to the first to fifth embodiments formed in the peripheral region 9 (see also FIGS. 10A to 10E). Fig. 27 shows an example in which the semiconductor device 1D has the peripheral structure 40 according to the first embodiment. The peripheral structure 40 includes a first peripheral structure 41 on the inward (active region 8) side of the first main surface 3, and a second peripheral structure 42 on the peripheral edge side of the first main surface 3.

[0596] As in the case of the semiconductor device 1A, the first peripheral structure 41 includes a p-type outer well region 43 formed in a surface layer portion of the first main surface 3 in the peripheral region 9. In this embodiment, the outer well region 43 is formed in a surface layer portion of the second surface portion 72. Specifically, the outer well region 43 is formed in a surface layer portion of the second semiconductor region 7 in the second surface portion 72, and is electrically connected to the second semiconductor region 7.

[0597] In this embodiment, the outer well region 43 is formed at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the second surface portion 72 toward the first surface portion 71. The outer well region 43 extends in a band shape along the periphery (first to fourth connection surface portions 73A to 73D) of the first surface portion 71 in a plan view.

[0598] In this embodiment, the outer well region 43 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first surface portion 71 in a plan view, and surrounds the first surface portion 71. The outer well region 43 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0599] The outer well region 43 has an inner edge portion on the first surface portion 71 side and an outer edge portion on the peripheral side of the second surface portion 72. In this embodiment, the inner edge portion of the outer well region 43 is drawn out from the outer periphery region 9 toward the active region 8 and is connected to the dummy well region 30d.

[0600] The inner edge of the outer well region 43 may have a portion extending in the vertical direction Z along the first to fourth connection surface portions 73A to 73D and on the surface portions of the first to fourth connection surface portions 73A to 73D. In this case, the inner edge of the outer well region 43 may be connected to the body region 10 at the surface portion of the first surface portion 71. Of course, the inner edge of the outer well region 43 may be formed at a distance from the dummy well region 30d toward the peripheral edge of the second surface portion 72.

[0601] The outer well region 43 is formed at a distance from the bottom of the second semiconductor region 7 toward the second surface portion 72, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The outer well region 43 may be formed at a distance from a depth position of the middle portion of the second semiconductor region 7 toward the second surface portion 72. The outer well region 43 may cross the depth position of the middle portion of the second semiconductor region 7.

[0602] In this embodiment, the outer well region 43 is formed in a region on the second surface portion 72 side relative to the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d), and faces the at least one type of well region 30 in the horizontal direction.

[0603] The outer well region 43 has an upper end exposed from the second surface portion 72 and a bottom located within the second semiconductor region 7. The bottom of the outer well region 43 is formed at a distance from the depth position of the middle portion of the second semiconductor region 7 toward the second surface portion 72. In this embodiment, the bottom of the outer well region 43 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the body region 10.

[0604] The bottom of the outer well region 43 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the gate structure 15. The bottom of the outer well region 43 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the source structure 20. The bottom of the outer well region 43 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the dummy structure 25.

[0605] The bottom of the outer well region 43 may be formed at a distance from the depth position of the bottom of the at least one type of well region 30 toward the second surface portion 72. The bottom of the outer well region 43 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the at least one type of well region 30.

[0606] The bottom of the outer well region 43 may be located at a depth substantially equal to the bottom of the at least one type of well region 30. Other explanations of the outer well region 43 in the semiconductor device 1D are the same as those of the outer well region 43 in the semiconductor device 1A.

[0607] As in the case of the semiconductor device 1A, the first peripheral structure 41 includes a p-type outer contact region 44 formed in the surface layer portion of the first main surface 3 in the peripheral region 9. In this embodiment, the outer contact region 44 is formed in the surface layer portion of the second surface portion 72.

[0608] Specifically, the outer contact region 44 is formed in the surface layer of the outer well region 43 in the second surface portion 72. The outer contact region 44 is formed at a distance from the bottom of the outer well region 43 toward the second surface portion 72, and faces the second semiconductor region 7 with a part of the outer well region 43 in between.

[0609] In plan view, the outer contact region 44 extends in a band shape along the periphery (first to fourth connection surface portions 73A to 73D) of the first surface portion 71. In this embodiment, the outer contact region 44 is formed in a polygonal ring shape (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first surface portion 71 in plan view, and surrounds the first surface portion 71.

[0610] The outer contact region 44 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). Of course, the outer contact region 44 may have a plurality of portions that are arranged at intervals along the first surface 71 so as to surround the first surface 71. In this case, the plurality of portions may each extend in a strip shape along the first surface 71.

[0611] The outer contact region 44 has a width less than the width of the outer well region 43, and is formed within the outer well region 43. The outer contact region 44 has an inner edge portion on the first surface portion 71 side and an outer edge portion on the peripheral edge side of the second surface portion 72.

[0612] In this embodiment, the inner edge of the outer contact region 44 is formed at a distance from the periphery of the first surface 71 (first to fourth connection surface portions 73A to 73D) toward the periphery of the second surface 72. Of course, like the outer well region 43, the inner edge of the outer contact region 44 may be drawn out from the outer periphery region 9 toward the active region 8 and connected to the dummy well region 30d.

[0613] In this case, the inner edge of the outer contact region 44 may have a portion that extends in the vertical direction Z along the surface layers of the first to fourth connection surface portions 73A to 73D along the first to fourth connection surface portions 73A to 73D. In this case, the inner edge of the outer contact region 44 may be connected to the body region 10 in the surface layer portion of the first surface portion 71. Of course, the inner edge of the outer contact region 44 may be connected to the dummy contact region 31d in the surface layer portion of the first surface portion 71.

[0614] The outer edge of the outer contact region 44 is formed at a distance from the outer edge of the outer well region 43 toward the first surface portion 71. Of course, the outer contact region 44 may cross the outer edge of the outer well region 43.

[0615] The outer contact region 44 has an upper end located on the second surface portion 72 side and a bottom located on the bottom side of the outer well region 43. The upper end of the outer contact region 44 is exposed from the second surface portion 72.

[0616] The bottom of the outer contact region 44 may be formed at a distance from the depth position of the intermediate portion of the outer well region 43 toward the second surface portion 72. The bottom of the outer contact region 44 may be located closer to the bottom of the outer well region 43 than the depth position of the intermediate portion of the outer well region 43.

[0617] The bottom of the outer contact region 44 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the gate structure 15. The bottom of the outer contact region 44 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the source structure 20. The bottom of the outer contact region 44 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the dummy structure 25.

[0618] The bottom of the outer contact region 44 is formed at a distance from the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d) toward the second surface portion 72.

[0619] The bottom of the outer contact region 44 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the at least one type of well region 30. The bottom of the outer contact region 44 may be located at a depth position substantially equal to the depth of the bottom of the at least one type of well region 30.

[0620] The bottom of the outer contact region 44 may be located on the bottom side of the second semiconductor region 7 from the depth position of the bottom of at least one type of contact region 31 (at least one of the gate contact region 31g, the source contact region 31s and the dummy contact region 31d).

[0621] The bottom of the outer contact region 44 may be formed at a distance toward the second surface portion 72 from the depth position of the bottom of at least one type of contact region 31. Other explanations of the outer contact region 44 of the semiconductor device 1D are the same as those of the outer contact region 44 of the semiconductor device 1A.

[0622] As in the case of semiconductor device 1A, first peripheral structure 41 includes a p-type termination region 45 formed in the surface layer portion of first main surface 3 in peripheral region 9. In this embodiment, termination region 45 is formed in the surface layer portion of second surface portion 72.

[0623] Specifically, termination region 45 is formed in a region on the surface layer of second surface 72 between the periphery of first surface 71 (first to fourth connection surface portions 73A to 73D) and the periphery of second surface 72 (first to fourth side surfaces 5A to 5D). More specifically, termination region 45 is formed in a region between the periphery of first surface 71 and outer well region 43.

[0624] In plan view, the termination region 45 extends in a band shape along the periphery of the first surface portion 71. In this embodiment, the termination region 45 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first surface portion 71 in plan view, and surrounds the first surface portion 71. The termination region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0625] Of course, termination region 45 may have a plurality of portions arranged at intervals along first surface 71 so as to surround first surface 71. In this case, the plurality of portions may each extend in a strip shape along first surface 71. Termination region 45 preferably has a width greater than the width of outer well region 43. Of course, the width of termination region 45 may be less than the width of outer well region 43.

[0626] The termination region 45 is formed in a surface layer portion of the second semiconductor region 7 in the second surface portion 72, and is electrically connected to the second semiconductor region 7. The termination region 45 is formed at a distance from the bottom of the second semiconductor region 7 toward the second surface portion 72, and faces the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0627] The termination region 45 is formed at a distance from the second surface 72 in the thickness direction of the chip 2. In other words, the termination region 45 is formed at a distance from the second surface 72 on the bottom side of the second semiconductor region 7, and has a portion facing the second surface 72 with a part of the second semiconductor region 7 in between.

[0628] The termination region 45 has an upper end located on the second surface portion 72 side and a bottom located on the bottom side of the second semiconductor region 7. The upper end of the termination region 45 extends horizontally along the second surface portion 72 and forms a pn junction with the second semiconductor region 7.

[0629] The upper end of the termination region 45 may be located closer to the second surface portion 72 than the depth position of the bottom of the outer well region 43. The upper end of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the outer well region 43.

[0630] The upper end of the termination region 45 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the gate structure 15. The upper end of the termination region 45 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the source structure 20. The upper end of the termination region 45 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the dummy structure 25.

[0631] The upper end of the termination region 45 may be located closer to the second surface portion 72 than the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d). The upper end of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of at least one type of well region 30.

[0632] The bottom of the termination region 45 extends horizontally along the second surface portion 72 and forms a pn junction with the second semiconductor region 7. The bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 or closer to the second surface portion 72 relative to the depth position of the bottom of the outer well region 43. Of course, the bottom of the termination region 45 may be located at a depth position substantially equal to the bottom of the outer well region 43.

[0633] The bottom of the termination region 45 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the gate structure 15. The bottom of the termination region 45 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the source structure 20. The bottom of the termination region 45 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the dummy structure 25.

[0634] The bottom of the termination region 45 may be located closer to the second surface portion 72 than the depth position of the bottom of the at least one type of well region 30. The bottom of the termination region 45 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the at least one type of well region 30.

[0635] The termination region 45 may have a depth (thickness) greater than the distance between the second surface portion 72 and the termination region 45. The depth of the termination region 45 is the distance between the top end and the bottom of the termination region 45. The depth of the termination region 45 may be less than the distance between the second surface portion 72 and the termination region 45.

[0636] The depth of the termination region 45 may be smaller than the distance between the bottom of the second semiconductor region 7 and the termination region 45. The depth of the termination region 45 may be larger than the distance between the bottom of the second semiconductor region 7 and the termination region 45. The depth of the termination region 45 is preferably smaller than the depth of the outer well region 43. The depth of the termination region 45 may be larger than the depth of the outer well region 43.

[0637] The termination region 45 has an inner edge on the first surface 71 side and an outer edge on the peripheral side of the second surface 72. The inner edge of the termination region 45 is connected to the outer edge of the outer well region 43. Specifically, the inner edge of the termination region 45 is connected to the outer edge of the outer well region 43 in a region on the bottom side of the outer well region 43. In this embodiment, the termination region 45 is electrically connected to the body region 10 and the outer contact region 44 via the outer well region 43 and the dummy well region 30d.

[0638] The inner edge of the termination region 45 may be formed at a distance from the outer edge of the outer contact region 44 toward the outer edge of the outer well region 43. The inner edge of the termination region 45 may be located closer to the inner edge of the outer well region 43 than the outer edge of the outer contact region 44.

[0639] The inner edge of the termination region 45 may be formed at a distance from the bottom of the outer contact region 44 toward the bottom of the outer well region 43, and may face the outer contact region 44 across a part of the outer well region 43. The inner edge of the termination region 45 may be connected to the outer contact region 44.

[0640] The inner edge of the termination region 45 may be formed at a distance from the inner edge of the outer well region 43 toward the outer edge of the outer well region 43. The inner edge of the termination region 45 may be formed at a distance from the periphery of the first surface 71 (first to fourth connection surfaces 73A to 73D) toward the outer edge of the outer well region 43.

[0641] Of course, the inner edge of the termination region 45 may be connected to the dummy well region 30d, similar to the outer well region 43. Other explanations of the termination region 45 of the semiconductor device 1D are the same as those of the termination region 45 of the semiconductor device 1A.

[0642] The second peripheral structure 42 includes at least one (in this embodiment, multiple) p-type field region 47 formed in the surface layer portion of the first main surface 3 in the peripheral region 9, similar to the case of the semiconductor device 1A.

[0643] In this embodiment, the plurality of field regions 47 are formed on the surface layer of the second surface 72. The plurality of field regions 47 are formed on the surface layer of the second surface 72 in a region between the periphery of the first surface 71 (first to fourth connecting surface portions 73A to 73D) and the periphery of the second surface 72 (first to fourth side surfaces 5A to 5D).

[0644] Specifically, the plurality of field regions 47 are formed in a region between the periphery of the second surface portion 72 and the outer well region 43, with a gap therebetween. More specifically, the plurality of field regions 47 are formed in a region between the periphery of the second surface portion 72 and the termination region 45, with a gap therebetween.

[0645] The plurality of field regions 47 are formed at intervals from one another in the surface layer portion of the second semiconductor region 7 and are electrically connected to the second semiconductor region 7. The plurality of field regions 47 are formed at intervals from the bottom of the second semiconductor region 7 toward the second surface portion 72, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0646] The plurality of field regions 47 are formed at intervals from the second surface portion 72 in the thickness direction of the chip 2. In other words, the plurality of field regions 47 are formed at intervals from the second surface portion 72 toward the bottom of the second semiconductor region 7, and have portions that face the second surface portion 72 across part of the second semiconductor region 7. The plurality of field regions 47 are each formed in a depth range between the top end and bottom of the termination region 45, and face the termination region 45 in the horizontal direction.

[0647] It is preferable that the distance between the second surface portion 72 and the field region 47 be approximately equal to the distance between the second surface portion 72 and the termination region 45. Of course, the distance between the second surface portion 72 and the field region 47 may be greater than the distance between the second surface portion 72 and the termination region 45, or may be smaller than the distance between the second surface portion 72 and the termination region 45.

[0648] In a plan view, the plurality of field regions 47 extend in a band shape along the periphery of the first surface portion 71. In this embodiment, the plurality of field regions 47 are formed in a polygonal ring shape (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the first surface portion 71 in a plan view, and surround the first surface portion 71.

[0649] The field regions 47 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). Of course, the field regions 47 may each have a plurality of portions arranged at intervals along the periphery of the first surface 71 so as to surround the first surface 71. In this case, the plurality of portions may each extend in a strip shape along the periphery of the first surface 71. The field regions 47 each have a width that is less than the width of the termination region 45.

[0650] Each of the field regions 47 has an upper end located on the second surface 72 side and a bottom located on the bottom side of the second semiconductor region 7. The upper ends of the field regions 47 extend horizontally along the second surface 72 and form pn junctions with the second semiconductor region 7.

[0651] The upper ends of the plurality of field regions 47 may be located closer to the second surface portion 72 than the depth position of the bottom of the outer well region 43. The upper ends of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the outer well region 43.

[0652] The upper ends of the plurality of field regions 47 are located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the gate structure 15. The upper ends of the plurality of field regions 47 are located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the source structure 20. The upper ends of the plurality of field regions 47 are located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the dummy structure 25.

[0653] The upper ends of the plurality of field regions 47 may be located closer to the second surface portion 72 than the depth position of the bottom of at least one type of well region 30 (at least one of the gate well region 30g, the source well region 30s, and the dummy well region 30d). The upper ends of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of at least one type of well region 30.

[0654] The bottoms of the plurality of field regions 47 extend horizontally along the second surface portion 72 and form pn junctions with the second semiconductor region 7. The bottoms of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the outer well region 43, or may be located closer to the second surface portion 72. Of course, the bottoms of the plurality of field regions 47 may also be located at a depth position substantially equal to the depth of the bottom of the outer well region 43.

[0655] The bottoms of the plurality of field regions 47 are located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the gate structure 15. The bottoms of the plurality of field regions 47 are located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the source structure 20. The bottoms of the plurality of field regions 47 are located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall of the dummy structure 25.

[0656] The bottoms of the plurality of field regions 47 may be located closer to the second surface portion 72 than the depth position of the bottoms of at least one type of well region 30. The bottoms of the plurality of field regions 47 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottoms of at least one type of well region 30.

[0657] Field region 47 may have a depth (thickness) approximately equal to the depth (thickness) of termination region 45. The depth of field region 47 is the distance between the top and bottom of field region 47. Of course, the depth of field region 47 may be greater than or less than the depth of termination region 45.

[0658] The depth of the field region 47 may be greater than the distance between the second surface portion 72 and the field region 47. The depth of the field region 47 may be less than the distance between the second surface portion 72 and the field region 47.

[0659] The depth of field region 47 may be smaller than the distance between the bottom of second semiconductor region 7 and field region 47. The depth of field region 47 may be larger than the distance between the bottom of second semiconductor region 7 and field region 47. Other descriptions of field region 47 in semiconductor device 1D are the same as those for field region 47 in semiconductor device 1A.

[0660] Similar to the semiconductor device 1A, the semiconductor device 1D includes a main surface insulating film 50 that selectively covers the first main surface 3. In this embodiment, the main surface insulating film 50 selectively covers the first surface portion 71, the second surface portion 72, and the first to fourth connection surface portions 73A to 73D.

[0661] The main surface insulating film 50 is selectively connected to the first insulating film 17 of the plurality of gate structures 15, the second insulating film 22 of the plurality of source structures 20, and the third insulating film 27 of the plurality of dummy structures 25 in the first surface portion 71, and exposes the first buried electrodes 18 of the plurality of gate structures 15, the second buried electrodes 23 of the plurality of source structures 20, and the third buried electrodes 28 of the plurality of dummy structures 25.

[0662] The main surface insulating film 50 covers the second semiconductor region 7, the outer well region 43, and the outer contact region 44 in the second surface portion 72. In this embodiment, the main surface insulating film 50 is continuous with the first to fourth side surfaces 5A to 5D in the peripheral portion of the second surface portion 72.

[0663] Of course, the main surface insulating film 50 may be formed at a distance inward from the periphery of the second surface portion 72, exposing the periphery (second semiconductor region 7) of the second surface portion 72. The main surface insulating film 50 covers the inner edges of the body region 10, the source region 11, and the outer well region 43 in the first to fourth connection surface portions 73A to 73D.

[0664] Similar to the semiconductor device 1A, the semiconductor device 1D includes an outer wiring 51 disposed on the main surface insulating film 50 in the peripheral region 9. In this embodiment, the outer wiring 51 is formed as a sidewall wiring that covers at least one (in this embodiment, all) of the first to fourth connection surface portions 73A to 73D on the second surface portion 72.

[0665] The outer wiring 51 is arranged at a distance from the periphery of the second surface 72 toward the first surface 71. Specifically, the outer wiring 51 is arranged at a distance from the outer edge of the termination region 45 toward the first surface 71.

[0666] More specifically, the outer wiring 51 is disposed at a distance from the outer edge of the outer well region 43 toward the first surface 71, and faces the outer well region 43 across the main surface insulating film 50. In this embodiment, the outer wiring 51 faces the outer contact region 44 across the main surface insulating film 50. The outer wiring 51 may have a portion facing the termination region 45 in the stacking direction.

[0667] In this embodiment, the outer wiring 51 is formed in a polygonal ring shape (specifically, a square ring shape) that extends along the periphery of the first surface portion 71 (first to fourth connection surface portions 73A to 73D) in a planar view, imitating the outer contact region 44, and surrounds the first surface portion 71.

[0668] The outer wiring 51 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). The outer wiring 51 may be either ended or endless.

[0669] The outer wiring 51 includes an outer edge portion extending in a film-like manner along the second surface portion 72, an intermediate portion extending in a film-like manner along the first to fourth connection surface portions 73A to 73D, and an inner edge portion extending in a film-like manner along the first surface portion 71. The outer edge portion of the outer wiring 51 may have a thickness less than the depth of the second surface portion 72, and may cover the second surface portion 72 in a film-like manner in an area on the second surface portion 72 side relative to the height position of the first surface portion 71.

[0670] The outer edge of the outer wiring 51 is formed at a distance from the innermost field region 47 of the plurality of field regions 47 toward the first surface portion 71. In other words, the outer edge of the outer wiring 51 does not face the plurality of field regions 47 across the main surface insulating film 50. The outer edge of the outer wiring 51 is formed at a distance from the outer edge of the termination region 45 toward the first surface portion 71.

[0671] In this embodiment, the outer wiring 51 is disposed at a distance from the outer edge of the outer contact region 44 toward the first surface 71, and has a portion facing the outer contact region 44 across the main surface insulating film 50. The outer wiring 51 may have a portion facing the termination region 45 in the stacking direction.

[0672] The middle portion of the outer wiring 51 covers the first to fourth connection surface portions 73A to 73D, so that the outer wiring 51 functions as a "sidewall structure (sidewall wiring)" that reduces the step between the first surface portion 71 and the second surface portion 72.

[0673] The intermediate portion of the outer wiring 51 may cover the first to fourth connection surface portions 73A to 73D in a film-like manner in accordance with the inclination angles of the first to fourth connection surface portions 73A to 73D. The intermediate portion of the outer wiring 51 covers the inner edges of the body region 10, the source region 11, and the outer well region 43 with the main surface insulating film 50 sandwiched therebetween.

[0674] The inner edge of the outer wiring 51 rides up onto the first surface 71 from at least one (all in this embodiment) of the first to fourth connection surfaces 73A to 73D, and extends in a band shape along the edge of the first surface 71. In this embodiment, the inner edge of the outer wiring 51 is formed in a polygonal ring shape (specifically, a square ring shape) that surrounds the inner part of the first surface 71.

[0675] The inner edge of the outer wiring 51 covers one or more (one in this embodiment) of the multiple dummy structures 25. The inner edge of the outer wiring 51 is connected to the third buried electrode 28 of the dummy structure 25. Specifically, the outer wiring 51 is formed integrally with the third buried electrode 28 of the dummy structure 25. In other words, the outer wiring 51 is formed as an extension portion in which a portion of the third buried electrode 28 is extended onto the main surface insulating film 50.

[0676] Similar to the semiconductor device 1A, the semiconductor device 1D includes an interlayer film 52 that selectively covers the first main surface 3 with a main surface insulating film 50 sandwiched therebetween. The interlayer film 52 covers the plurality of gate structures 15 (first buried electrodes 18) and the plurality of dummy structures 25 (third buried electrodes 28) on the first surface portion 71 side. The interlayer film 52 covers the second semiconductor region 7, the outer well region 43, and the outer contact region 44 on the second surface portion 72 side with the main surface insulating film 50 sandwiched therebetween.

[0677] In this embodiment, the interlayer film 52 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral portion of the second surface portion 72. Of course, the interlayer film 52 may be formed at a distance inward from the peripheral portion of the second surface portion 72, exposing the peripheral portion of the second surface portion 72 (the second semiconductor region 7). The interlayer film 52 covers the first to fourth connection surface portions 73A to 73D with the outer wiring 51 sandwiched therebetween.

[0678] As in the case of the semiconductor device 1A, the semiconductor device 1D includes a plurality of source openings 53 formed in the interlayer film 52, at least one (one in this embodiment) outer opening 54, and at least one (multiple in this embodiment) gate openings 55.

[0679] The plurality of source openings 53 are formed on the first surface 71 side in the same manner as in the semiconductor device 1A, exposing the source region 11 and the plurality of contact regions 31. The outer opening 54 is formed on the second surface 72 side in the same manner as in the semiconductor device 1A, exposing the outer edge of the outer wiring 51 and the outer contact region 44.

[0680] The plurality of gate openings 55 are formed on the first surface 71 side in the same manner as in the semiconductor device 1A, exposing one end or the other end of the plurality of gate structures 15 (first buried electrodes 18).

[0681] Similar to the semiconductor device 1A, the semiconductor device 1D includes a source electrode 60 disposed on the first main surface 3. The source electrode 60 is disposed on a portion of the interlayer film 52 that covers the first surface portion 71. The source electrode 60 extends from above the interlayer film 52 into the plurality of source openings 53, and is electrically connected to the source region 11 and the plurality of contact regions 31 within the plurality of source openings 53.

[0682] Similar to the case of the semiconductor device 1A, the source electrode 60 has a laminated structure including a lower electrode film 61 and a main electrode film 62 laminated in this order from the chip 2 side. The lower electrode film 61 has a laminated structure including a first electrode film 63 and a second electrode film 64. Other descriptions of the source electrode 60 of the semiconductor device 1D are similar to those of the source electrode 60 of the semiconductor device 1A.

[0683] Similar to the semiconductor device 1A, the semiconductor device 1D includes a termination wiring 65 arranged around the source electrode 60 on the interlayer film 52. Similar to the semiconductor device 1A, the termination wiring 65 has a laminated structure including a lower electrode film 61 and a main electrode film 62 laminated in this order from the chip 2 side. The lower electrode film 61 has a laminated structure including a first electrode film 63 and a second electrode film 64.

[0684] In this embodiment, the termination wiring 65 is drawn from the source electrode 60 (first pad portion 60a) to the fourth connection surface portion 73D side and selectively routed on the interlayer film 52. The termination wiring 65 has a wiring width less than the electrode width of the source electrode 60. In this embodiment, the termination wiring 65 covers the peripheral edge portion of the first surface portion 71 at a distance from the source electrode 60 and extends in a strip shape along at least one (all in this embodiment) of the first to fourth connection surfaces 73A to 73D.

[0685] In this embodiment, the termination wiring 65 is formed in a polygonal ring shape (specifically, a square ring shape) extending along the first to fourth connection surface portions 73A to 73D in a plan view, and surrounds the source electrode 60. The termination wiring 65 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The outer wiring 51 may be either terminated or endless.

[0686] The termination wiring 65 is drawn out from the first surface 71 (active region 8) side across at least one (all in this embodiment) of the first to fourth connection surface portions 73A to 73D to the second surface 72 (peripheral region 9) side, and has a portion facing the outer wiring 51 across the interlayer film 52. In this embodiment, the termination wiring 65 covers the outer wiring 51 over the entire periphery.

[0687] The termination wiring 65 enters the outer opening 54 from above the interlayer film 52 and is electrically connected to the outer contact region 44 and the outer wiring 51 within the outer opening 54 .

[0688] That is, the termination wiring 65 is electrically connected to the termination region 45 via the outer contact region 44, and is electrically connected to one or more (one in this embodiment) dummy structures 25 (third buried electrodes 28) via the outer wiring 51. The source potential applied to the source electrode 60 is applied to the termination region 45 via the termination wiring 65, and at the same time, is applied to the dummy structures 25 via the termination wiring 65.

[0689] The termination wiring 65 has an inner edge on the first surface 71 side and an outer edge on the second surface 72 side. The inner edge of the termination wiring 65 is located on the first surface 71 and faces the multiple dummy structures 25 with the interlayer film 52 in between.

[0690] The outer edge of the termination wiring 65 is formed at a distance inward from the periphery of the second surface portion 72. The outer edge of the termination wiring 65 is formed at a distance inward from the innermost field region 47 of the multiple field regions 47. In other words, the termination wiring 65 does not face the multiple field regions 47 across the interlayer film 52. The outer edge of the termination wiring 65 is formed at a distance inward from the outer edge of the termination region 45, and faces the termination region 45 across the interlayer film 52.

[0691] The outer edge of the termination wiring 65 is formed at a distance from the outer edge of the outer well region 43 toward the periphery of the second surface 72. In other words, the termination wiring 65 covers the entire outer well region 43. Other explanations of the termination wiring 65 of the semiconductor device 1D are the same as those of the termination wiring 65 of the semiconductor device 1A.

[0692] Similar to the semiconductor device 1A, the semiconductor device 1D includes a gate electrode 66 disposed on the first main surface 3. The source electrode 60 is disposed on a portion of the interlayer film 52 that covers the first surface portion 71.

[0693] As in the case of the semiconductor device 1A, the gate electrode 66 has a laminated structure including a lower electrode film 61 and a main electrode film 62 laminated in this order from the chip 2 side. The lower electrode film 61 has a laminated structure including a first electrode film 63 and a second electrode film 64. Other descriptions of the gate electrode 66 in the semiconductor device 1D are the same as those of the gate electrode 66 in the semiconductor device 1A.

[0694] Similar to the semiconductor device 1A, the semiconductor device 1D includes a gate wiring 67 extending from the gate electrode 66 onto the first main surface 3. In this embodiment, the gate wiring 67 is disposed on the first surface 71 at a distance inward from the periphery of the first surface 71. Therefore, the gate wiring 67 is not positioned on the second surface 72.

[0695] As in the case of the semiconductor device 1A, the gate wiring 67 enters the plurality of gate openings 55 from above the interlayer film 52 and is mechanically and electrically connected to the ends (both ends) of the plurality of gate structures 15 (first buried electrodes 18) within the plurality of gate openings 55. Other explanations of the gate wiring 67 in the semiconductor device 1D are the same as those for the gate wiring 67 in the semiconductor device 1A.

[0696] Similar to the semiconductor device 1A, the semiconductor device 1D includes a drain electrode 68 covering the second main surface 4. The drain electrode 68 is electrically connected to the first semiconductor region 6. Other details of the drain electrode 68 in the semiconductor device 1D are similar to those of the drain electrode 68 in the semiconductor device 1A.

[0697] A breakdown voltage that can be applied between the source electrode 60 and the drain electrode 68 (between the first major surface 3 and the second major surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or less and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, 2500 V or more and 2750 V or less, and 2750 V or more and 3000 V or less.

[0698] As in the case of semiconductor device 1A, semiconductor device 1D can include any one of the features of the first peripheral structure 41 relating to the first to fifth embodiment examples (see also Figures 11A to 11J).

[0699] A specific configuration in this case can be obtained by replacing "the inner portion of the first main surface 3 (active region 8)" with "the first surface portion 71 (active region 8)" and "the peripheral portion of the first main surface 3 (outer peripheral region 9)" with "the second surface portion 72 (outer peripheral region 9)" in the description of the first outer peripheral structure 41 according to the first to tenth modifications. Of course, the features of the first outer peripheral structure 41 according to the first to tenth modifications can be combined as appropriate.

[0700] Therefore, the semiconductor device 1D can simultaneously include at least two of the features of the first peripheral structure 41 according to the first to tenth modified examples in the same or different regions with respect to the first peripheral structure 41 according to the first to fifth embodiment examples.

[0701] At least one feature of the outer well region 43, outer contact region 44, and termination region 45 according to the first to tenth modified examples is appropriately selected depending on the configuration of the first to fifth embodiment examples, and is applied to the configuration of the first to fifth embodiment examples.

[0702] The semiconductor device 1D may include any one of the features of the second peripheral structure 42 relating to the first to fifth embodiment examples, as well as the features of the second peripheral structure 42 relating to the first to tenth modified examples (see also Figures 12A to 12J).

[0703] A specific configuration in this case can be obtained by replacing "the inner portion of the first main surface 3 (active region 8)" with "the first surface portion 71 (active region 8)" and "the peripheral portion of the first main surface 3 (outer peripheral region 9)" with "the second surface portion 72 (outer peripheral region 9)" in the description of the second outer peripheral structure 42 according to the first to tenth modifications. Of course, the features of the second outer peripheral structure 42 according to the first to tenth modifications can be combined as appropriate.

[0704] Therefore, the semiconductor device 1D can simultaneously include at least two of the features of the second peripheral structure 42 according to the first to tenth modified examples in the same or different regions with respect to the second peripheral structure 42 according to the first to fifth embodiment examples.

[0705] At least one feature of the field region 47 according to the first to tenth modifications is selected appropriately according to the configurations of the first to fifth embodiments, and is applied to the configurations of the first to fifth embodiments.

[0706] The semiconductor...

Claims

1. A chip having a main surface, A first conductivity type semiconductor region formed on the surface layer of the main surface, A semiconductor device comprising: a second conductivity type termination region formed on the surface layer of the semiconductor region at a distance from the main surface in the thickness direction of the chip, at the peripheral edge of the main surface.

2. The semiconductor device according to claim 1, wherein the chip includes SiC.

3. The semiconductor device according to claim 1, wherein the termination region faces the main surface with a portion of the semiconductor region in between.

4. The semiconductor device according to claim 1, wherein the termination region has a thickness greater than the distance between the main surface and the termination region.

5. The peripheral edge of the main surface further includes a second conductivity type well region formed on the surface layer of the main surface, The semiconductor device according to any one of claims 1 to 4, wherein the termination region is formed in the surface layer of the semiconductor region in the region between the periphery of the main surface and the well region.

6. The semiconductor device according to claim 5, wherein the termination region is connected to the well region.

7. The semiconductor device according to claim 5, wherein the termination region has a bottom located below the depth position of the bottom of the well region.

8. The system further includes a second conductive contact region formed on the surface of the well region and having an impurity concentration higher than that of the well region. The semiconductor device according to claim 5, wherein the termination region has an impurity concentration less than the impurity concentration of the contact region.

9. The semiconductor device according to any one of claims 1 to 4, further comprising a termination electrode disposed on the main surface and electrically connected to the termination region.

10. The semiconductor device according to any one of claims 1 to 4, further comprising a field region of a second conductivity type formed on the surface layer of the semiconductor region in the region between the periphery of the main surface and the terminal region.

11. A chip having a main surface, A first conductivity type semiconductor region formed on the surface layer of the main surface, A semiconductor device comprising: a second conductivity type field region formed on the surface layer of the semiconductor region at a distance from the main surface in the thickness direction of the chip, at the periphery of the main surface.

12. The semiconductor device according to claim 11, wherein the chip includes SiC.

13. The semiconductor device according to claim 11, wherein the field region faces the main surface with a portion of the semiconductor region in between.

14. The semiconductor device according to claim 11, wherein the field region has a thickness greater than the distance between the main surface and the field region.

15. The semiconductor device according to claim 11, wherein a plurality of the field regions are formed at intervals on the surface layer of the semiconductor region.

16. The peripheral edge of the main surface further includes a second conductivity type termination region formed on the surface layer of the semiconductor region, The semiconductor device according to any one of claims 11 to 15, wherein the field region is formed in the surface layer of the semiconductor region in the region between the periphery of the main surface and the terminal region.

17. The peripheral edge of the main surface further includes a second conductivity type well region formed on the surface layer of the main surface, The semiconductor device according to claim 16, wherein the termination region is formed in the surface layer of the semiconductor region in the region between the periphery of the main surface and the well region.

18. The semiconductor device according to claim 17, further comprising a second conductivity type contact region formed on the surface of the well region and having an impurity concentration higher than that of the well region.

19. The semiconductor device according to claim 16, further comprising a termination electrode disposed on the main surface at a distance from the field region toward the inner part of the main surface and electrically connected to the termination region.

20. An active region provided in the inner part of the main surface, An outer peripheral region provided at the periphery of the main surface, The device structure formed in the active region further includes, The semiconductor device according to any one of claims 11 to 15, wherein the field region is formed in the outer peripheral region.