Semiconductor device

Abstract

Provided is a semiconductor device (100) comprising a floating region (202) of a second conductivity type which is disposed under a lower end (43) of a first gate trench part (40) on the upper surface side of a semiconductor substrate (10) and does not extend under a lower end (33) of a first dummy trench part. A first mesa part is provided in contact with the first gate trench part and includes: an emitter region (12) of a first conductivity type having a higher concentration than in a drift region (18); and a base region (14) of the second conductivity type provided between the emitter region and the drift region and being in contact with the first gate trench part. The lower end of the first dummy trench part is in contact with the region of the first conductivity type.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Conventionally, semiconductor devices provided with transistors such as insulated gate bipolar transistors (IGBTs) have been known (see, for example, Patent Documents 1 to 4). [Prior art documents] [Patent Document 1] Japanese Patent No. 6472714 [Patent Document 2] Japanese Patent No. 4456013 [Patent Document 3] Japanese Patent Laid-Open No. 2020-21941 [Patent Document 4] Japanese Patent Laid-Open No. 2010-232627 General disclosure

[0003] (Problem to be Solved) In a semiconductor device, it is preferable to suppress the snapback phenomenon.

[0004] To solve the above problem, one aspect of the present invention provides a semiconductor device including an IGBT. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface and including a first conductivity type drift region. Any of the semiconductor devices may include a first gate trench portion provided on the upper surface of the semiconductor substrate. Any of the semiconductor devices may include a first dummy trench portion provided on the upper surface of the semiconductor substrate and arranged alongside the first gate trench portion on the upper surface. Any of the semiconductor devices may include a first mesa portion within the semiconductor substrate, sandwiched between the first gate trench portion and the first dummy trench portion. Any of the semiconductor devices may include a second conductivity type floating region on the upper surface of the semiconductor substrate, arranged below a lower end of the first gate trench portion and not extending below a lower end of the first dummy trench portion. The first mesa portion of any of the above semiconductor devices may be provided in contact with the first gate trench portion and may have an emitter region of a first conductivity type having a higher concentration than the drift region. The first mesa portion of any of the above semiconductor devices may be provided between the emitter region and the drift region and may have a base region of a second conductivity type in contact with the first gate trench portion. In any of the above semiconductor devices, a lower end of the first dummy trench portion may be in contact with a region of the first conductivity type.

[0005] In any of the above semiconductor devices, the floating region may not be in contact with the lower end of the gate trench portion.

[0006] In any of the above semiconductor devices, the floating region may be in contact with a lower end of the gate trench portion.

[0007] In any of the above semiconductor devices, the first mesa portion may further include an accumulation region of the first conductivity type that is provided between the base region and the drift region and has a higher concentration than the drift region.

[0008] In any of the above semiconductor devices, the accumulation region may be in contact with the floating region.

[0009] In any of the above semiconductor devices, the lower end of the accumulation region may be located lower than the lower end of the floating region.

[0010] In any of the above semiconductor devices, the lower end of the accumulation region may be located higher than the lower end of the floating region.

[0011] In any of the above semiconductor devices, the first mesa portion may have a second conductivity type contact region in contact with the upper surface of the semiconductor substrate and having a higher concentration than the base region.

[0012] In any of the above semiconductor devices, the first mesa portion may have a contact portion that is provided from the upper surface of the semiconductor substrate to the inside of the first mesa portion and is filled with a conductive material.

[0013] In any of the above semiconductor devices, a lower end of the contact portion may be in contact with the contact region.

[0014] In any of the above semiconductor devices, the first dummy trench portion may be provided on both sides of the first gate trench portion.

[0015] In any of the above semiconductor devices, the floating region may be in contact with a sidewall of the first dummy trench portion.

[0016] In any of the above semiconductor devices, the first dummy trench portion may have an electrode made of polysilicon doped with an impurity of a first conductivity type.

[0017] Any of the above semiconductor devices may include a lower end region of the first conductivity type that is provided in contact with a lower end of the first dummy trench portion and has a higher concentration than the drift region.

[0018] Any of the above semiconductor devices may include two dummy trenches provided on the top surface of the semiconductor substrate and arranged side by side on the top surface. In any of the above semiconductor devices, a distance between the first gate trench and the first dummy trench may be the same as a distance between the two dummy trenches.

[0019] Any of the above semiconductor devices may include diode sections arranged alternately with the IGBTs in a first direction. In any of the above semiconductor devices, the IGBTs arranged between the diode sections may have a plurality of trench sections arranged side by side in the first direction, each trench section including the first gate trench section and the first dummy trench section. In any of the above semiconductor devices, the intervals between each of the plurality of trench sections may be the same.

[0020] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions.

[0021] 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. It is an enlarged view of region D in FIG. 1. It is a view showing an example of an e-e cross section in FIG. 2. It is a view showing an example of an f-f cross section in FIG. 2. It is a view showing collector voltage-collector current characteristics in an example and a reference example. It is a view showing collector voltage-collector current characteristics in an example and a reference example. It is a view showing an example of measurement of voltage and current of a semiconductor device of an example. It is a view showing another example of measurement of voltage and current of a semiconductor device of a reference example. It is a view showing another example of measurement of voltage and current of a semiconductor device of an example. It is a view showing trade-off characteristics of turn-on loss and reverse recovery dV / dt in a reference example and an example. It is a view showing another example of an f-f cross section. It is a view showing another example of an f-f cross section. It is a view showing another example of an f-f cross section. It is a view showing another example of an f-f cross section. It is a view showing another example of an f-f cross section. It is a view showing another example of an ee cross section.

[0022] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0023] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0024] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0025] In this specification, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0026] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0027] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0028] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0029] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0030] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is described in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0031] In this specification, chemical concentration refers to the atomic density of an impurity measured regardless of its state of electrical activation. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as a value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is sufficiently greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0032] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. ３ , or / cm ３ This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atoms notation may be omitted.

[0033] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects or the like.

[0034] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0035] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0036] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two pairs of end edges 162 that face each other in a top view. In FIG. 1 , the X-axis and Y-axis are parallel to either of the end edges 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0037] An active portion 160 is provided in the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted from FIG. 1 . The active portion 160 may refer to a region that overlaps with the emitter electrode in a top view. The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0038] The active section 160 is provided with a transistor section 70 including a transistor element such as an insulated gate bipolar transistor (IGBT). The active section 160 may further be provided with a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1 , the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the top surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0039] In FIG. 1 , the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1 ). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0040] The diode section 80 has an N+ type cathode region in a region that contacts the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 that extends the diode section 80 in the Y-axis direction to the gate wiring described below may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0041] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 also has a gate structure, which has an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the upper surface side of the semiconductor substrate 10.

[0042] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 162. The vicinity of the edge 162 refers to the region between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0043] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is hatched with diagonal lines.

[0044] The gate wiring in this example has a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The region surrounded by the well region in a top view may be the active portion 160.

[0045] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0046] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, it is possible to reduce variations in wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0047] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The peripheral gate wiring 130 and the active side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0048] The active side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active side gate wiring 131 extends in the X axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 that sandwich the active section 160, crossing the active section 160 at approximately the center in the Y axis direction. When the active section 160 is divided by the active side gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X axis direction in each divided region.

[0049] The semiconductor device 100 may include a temperature sensing section (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting section (not shown) which simulates the operation of a transistor section provided in the active section 160.

[0050] In the present example, the semiconductor device 100 includes an edge termination structure 90 between the active section 160 and the edge 162 when viewed from above. The edge termination structure 90 in the present example is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 90 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active section 160.

[0051] 2 is an enlarged view of region D in FIG. 1 . Region D includes a transistor section 70, a diode section 80, and an active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0052] An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is not shown in FIG. 2 . In this example, a contact portion 54 is provided in the interlayer insulating film so as to penetrate the interlayer insulating film. The contact portion 54 may include a contact hole provided in the interlayer insulating film and a conductive member filled in the contact hole. In FIG. 2 , each contact portion 54 is hatched with diagonal lines.

[0053] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is connected to the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 via a contact portion 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction.

[0054] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0055] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the area where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as a metal alloy such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. Furthermore, the contact hole may have a plug formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0056] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the active side gate wiring 131. In this example, the well region 11 is provided away from the end of the contact portion 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of a second conductivity type having a doping concentration higher than that of the base region 14. In this example, the base region 14 is P- type, and the well region 11 is P+ type.

[0057] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0058] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench that are straight along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0059] At least a portion of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0060] In the transistor section 70, the dummy trench section 30 is provided between each of the straight line sections 39 of the gate trench section 40. One or more dummy trench sections 30 may be provided between each of the straight line sections 39. The dummy trench section 30 may have a linear shape extending in the extension direction, and may have a straight line section 29 and a tip section 31, similar to the gate trench section 40.

[0061] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0062] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the mesa portion simply referred to as a mesa portion refers to both the mesa portion 60 and the mesa portion 61.

[0063] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active-side gate wiring 131 is referred to as the base region 14-e. While FIG. 2 shows the base region 14-e located at one end of each mesa portion in the extension direction, a base region 14-e is also located at the other end of each mesa portion. Each mesa portion may be provided with at least one of a first-conductivity-type emitter region 12 and a second-conductivity-type contact region 15 in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type with a higher concentration than the base region 14. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0064] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0065] The emitter region 12 in the mesa portion 60 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 is also provided in a region overlapping with the contact portion 54.

[0066] The contact region 15 in the mesa portion 60 is provided in a region overlapping with the contact portion 54. The contact region 15 may or may not be in contact with the gate trench portion 40. The contact region 15 may or may not be in contact with the dummy trench portion 30.

[0067] 2 , the emitter region 12 in the mesa portion 60 is provided from one trench portion to the other trench portion in the X-axis direction. The contact region 15 in the mesa portion 60 may also be provided from one trench portion to the other trench portion in the X-axis direction. The contact region 15 does not have to be in contact with either of the two trench portions that sandwich the mesa portion 60. In this case, a base region 14 may be provided between the contact region 15 and the trench portion.

[0068] 2, the contact regions 15 and emitter regions 12 of the mesa portion 60 are alternately arranged along the extension direction (Y-axis direction) of the trench portion. In another example, the contact regions 15 and emitter regions 12 of the mesa portion 60 may be provided in stripes along the extension direction (Y-axis direction) of the trench portion. For example, the emitter regions 12 are provided in regions in contact with the trench portion, and the contact regions 15 are provided in regions sandwiched between the emitter regions 12. Alternatively, the mesa portion 60 may be provided with emitter regions 12 instead of contact regions 15. For example, the emitter regions 12 may be provided in the entire region sandwiched between the base regions 14-e in the Y-axis direction.

[0069] The mesa portion 61 of the diode section 80 does not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region sandwiched between the base regions 14-e on the upper surface of the mesa portion 61, a contact region 15 may be provided in contact with each of the base regions 14-e. In the region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61, a base region 14 may be provided. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15.

[0070] A contact portion 54 is provided above each mesa portion. The contact portion 54 is arranged in a region sandwiched between the base regions 14-e. In this example, the contact portion 54 is provided above each of the contact region 15, the base region 14, and the emitter region 12. The contact portion 54 is not provided in a region corresponding to the base region 14-e and the well region 11. The contact portion 54 may be arranged in the center of the arrangement direction (X-axis direction) of the mesa portions 60.

[0071] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2 , the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0072] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact portion 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact portion 54.

[0073] Fig. 3 is a diagram showing an example of the e-e cross section in Fig. 2. The e-e cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0074] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact portion 54 described with reference to FIG. 2 .

[0075] The contact portion 54 penetrates the interlayer insulating film 38. The contact portion 54 may be formed of a metal different from that of the emitter electrode 52. The contact portion 54 may contain tungsten. A barrier metal layer including at least one of a titanium film and a titanium nitride film may be provided at the bottom of the contact portion 54. The contact portion 54 may be provided up to the upper surface 21 of the semiconductor substrate 10, or may be provided up to the interior of the semiconductor substrate 10. In the example of FIG. 3 , the contact portion 54 is a contact trench provided from the upper surface 21 of the semiconductor substrate 10 to the interior of each mesa portion. This increases the contact area between the contact portion 54 and the semiconductor substrate 10. In the cross section, the lower end of the contact portion 54 of the transistor portion 70 contacts the emitter region 12. In the cross section, the lower end of the contact portion 54 of the diode portion 80 contacts the base region 14.

[0076] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is connected to the semiconductor substrate 10 via a contact portion 54. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0077] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70 and the diode section 80.

[0078] In the mesa portion 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0079] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18.

[0080] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0081] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. That is, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0082] A P-type base region 14 is provided in the mesa portion 61 of the diode section 80 in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided below the base region 14 in the mesa portion 61.

[0083] In each of the transistor section 70 and the diode section 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Furthermore, the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0084] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 may be located at the same depth as the chemical concentration peak of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0085] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0086] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors in each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0087] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed in the order of forming the doped regions and then the trenches. The trenches penetrating the doped regions also include trenches formed in the order of forming the trenches and then forming the doped regions.

[0088] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. The diode section 80 is provided with the dummy trench section 30, but is not provided with the gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0089] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and further inside than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0090] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0091] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0092] In this example, the gate trench 40 and the dummy trench 30 are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may have a downwardly convex curved shape (a curved shape in cross section). In this specification, the depth position of the lower end 43 of the gate trench 40 is designated Zt.

[0093] The semiconductor device 100 of this example includes a P-type floating region 202 provided below the lower end 43 of the gate trench portion 40. The lower end 43 of the gate trench portion 40 refers to the portion of the gate trench portion 40 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of FIG. 3, the lower end 43 of the gate trench portion 40 is located at the center of the gate trench portion 40 in the X-axis direction. Furthermore, the lower end 33 of the dummy trench portion 30 refers to the portion of the dummy trench portion 30 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of FIG. 3, the lower end 33 of the dummy trench portion 30 is located at the center of the dummy trench portion 30 in the X-axis direction.

[0094] At least a portion of the floating region 202 is provided at a position overlapping with the lower end 43 in a top view and is disposed below the lower end 43 in the Z-axis direction. The floating region 202 may include a portion that does not overlap with the lower end 43 in a top view. The floating region 202 may include a portion that is provided above the lower end 43. The floating region 202 may be in contact with the lower end 43 or may be separated from the lower end 43. In the example of FIG. 3 , the floating region 202 is in contact with the entire curved portion of the gate trench portion 40, including the lower end 43. The floating region 202 may be formed by implanting a P-type dopant near the lower end of the trench structure after forming the trench structure of the gate trench portion 40 and before forming the gate conductive portion 44.

[0095] The floating region 202 is electrically floating relative to an electrode such as a metal or polysilicon electrode. At least one of an N-type region and an insulating film is disposed between the floating region 202 and the electrode. In other words, the floating region 202 and the electrode are not connected by a P-type region or a conductive material. The doping concentration of the floating region 202 may be equal to or lower than the doping concentration of the base region 14, or may be higher than the doping concentration of the base region 14. In this example, the doping concentration of the floating region 202 is higher than the doping concentration of the base region 14. The doping concentration is 1×10 １５ cm －３ That's it, 1 x 10 １７ cm －３ It may be the following:

[0096] The floating region 202 is disposed apart from the base region 14. An N-type region (at least one of the accumulation region 16 and the drift region 18 in this example) is provided between the floating region 202 and the base region 14.

[0097] In this specification, the gate trench portion 40 below which the floating region 202 is disposed is referred to as the first gate trench portion 40-1. Furthermore, the dummy trench portion 30 disposed alongside the first gate trench portion 40-1 in the X-axis direction on the upper surface 21 is referred to as the first dummy trench portion 30-1. The first gate trench portion 40-1 and the first dummy trench portion 30-1 are two trench portions adjacent to each other in the X-axis direction. In this example, the first dummy trench portions 30-1 are disposed on both sides of the first gate trench portion 40-1 in the X-axis direction. Furthermore, the mesa portion 60 sandwiched between the first gate trench portion 40-1 and the first dummy trench portion 30-1 is referred to as the first mesa portion 60-1. Of the mesa portions 60, the portion sandwiched between the two dummy trench portions 30 is referred to as a second mesa portion 60-2. The second mesa portion 60-2 may have the same structure as the first mesa portion 60-1.

[0098] Each transistor portion 70 has one or more first gate trench portions 40-1. Each transistor portion 70 may have multiple first gate trench portions 40-1. In each transistor portion 70, 50% or more of the gate trench portions 40 may be first gate trench portions 40-1, 80% or more of the gate trench portions 40 may be first gate trench portions 40-1, or all of the gate trench portions 40 may be first gate trench portions 40-1.

[0099] The floating region 202 is disposed below the lower end 43 of the first gate trench portion 40-1, and does not extend below the lower end 33 of the adjacent first dummy trench portion 30-1. The lower end 33 is in contact with an N-type region (drift region 18 in this example). Furthermore, on the upper surface 21 side of the semiconductor substrate 10, no P-type region is provided below the lower end 33, but an N-type region (drift region 18 in this example) is provided.

[0100] By providing the floating region 202, when the transistor section 70 is turned on, electrons are prevented from flowing to the lower end 43 of the first gate trench section 40-1, and a depletion layer can be left near the lower end 43. This reduces the reverse recovery dV / dt. The reverse recovery dV / dt is the slope of the time waveform of the anode-cathode voltage during reverse recovery of the diode section 80. Furthermore, when the semiconductor device 100 is used in a circuit such as a three-phase inverter, the tail of the voltage waveform of the IGBT provided in the opposing arm can be reduced. This improves the trade-off characteristics between turn-on loss and reverse recovery dV / dt.

[0101] On the other hand, if the floating region 202 extends below the lower end 33 of the first dummy trench portion 30-1, when a channel is formed in the base region 14 of the first mesa portion 60-1 and an electron current flows, the electron current is less likely to flow to the collector region 22. This may result in snapback when the transistor portion 70 is turned on. This may also result in a longer turn-on time for the transistor portion 70. In the semiconductor device 100 of this example, the floating region 202 does not extend below the lower end 33 of the first dummy trench portion 30-1. This may result in a channel being formed in the base region 14 of the first mesa portion 60-1 and an electron current flowing, making it easier for the electron current to flow to the collector region 22. This makes it possible to suppress the occurrence of snapback and reduce the turn-on delay.

[0102] In this example, the floating region 202 is arranged so as not to overlap with the first dummy trench portion 30-1 in a top view. The floating region 202 may be arranged so as not to contact the first dummy trench portion 30-1. In this example, an N-type region is arranged between the floating region 202 and the first dummy trench portion 30-1. The floating region 202 may be arranged so as to overlap with the first mesa portion 60-1 in a top view. The first mesa portion 60-1 may have a region that does not overlap with the floating region 202 in a top view. In this example, the region of the first mesa portion 60-1 that contacts the first dummy trench portion 30-1 does not overlap with the floating region 202. The floating region 202 may extend to a position that overlaps with the contact portion 54 of the first mesa portion 60-1, or may be arranged so as not to overlap.

[0103] The floating region 202 extends in the Y-axis direction when viewed from above. The length of the floating region 202 in the Y-axis direction may be 50% or more, 70% or more, or 90% or more of the length of the straight portion 39 of the first gate trench portion 40-1 in the Y-axis direction. When the floating region 202 is provided over the entire first gate trench portion 40-1, the end of the floating region 202 in the Y-axis direction is located below the base region 14-e.

[0104] The distance in the X-axis direction between the first gate trench portion 40-1 and the first dummy trench portion 30-1 is defined as X1. The distance between the trench portions is the distance between the centers of the trench portions in the X-axis direction. The distance in the X-axis direction between the two dummy trench portions 30 in the transistor portion 70 is defined as X2. In this example, the distance between the two first dummy trench portions 30-1 is X2. The distance X1 and the distance X2 may be the same. The distance in the X-axis direction between the two dummy trench portions 30 in the diode portion 80 is defined as X3. The distance X1, the distance X2, and the distance X3 may be the same.

[0105] The intervals between all trench portions in at least one transistor portion 70 sandwiched between two diode portions 80 in the X-axis direction may be the same. Also, the intervals between all trench portions in the semiconductor device 100 may be the same.

[0106] 4 is a diagram showing an example of the ff cross section in FIG. 2. The ff cross section is an XZ plane passing through the contact region 15 and the cathode region 82. The semiconductor device 100 in the ff cross section has a contact region 15 instead of the emitter region 12 in the mesa portion 60 in the structure of the semiconductor device 100 in the ee cross section. A contact region 15 is also provided in the mesa portion 61. The other structures are similar to those of the semiconductor device 100 in the ee cross section.

[0107] The contact region 15 is exposed on the upper surface 21 of the semiconductor substrate 10. The contact region 15 is provided between the upper surface 21 and the base region 14. In this example, the contact region 15 does not contact the trench portions on either side of each mesa portion. In the example of FIG. 4, the base region 14 is provided between the contact region 15 and each trench portion. The contact region 15 in this example is connected to the emitter electrode 52 via a contact portion 54. The contact region 15 may be provided with a groove into which the contact portion 54 is inserted. In this cross section, the lower ends of the contact portions 54 of the transistor portion 70 and the diode portion 80 contact the contact region 15.

[0108] 5 is a diagram showing collector voltage-collector current characteristics in an example and a reference example. The reference example is an example in which the floating region 202 is extended to below the lower end 33 of the first dummy trench portion 30-1. The example is the semiconductor device 100 described with reference to FIGS. 1 to 4.

[0109] In the reference example, the floating region 202 makes it difficult for the electron current in the first mesa portion 60-1 to flow to the collector region 22. For this reason, in the reference example, snapback occurs, in which almost no collector current flows until the collector voltage exceeds a predetermined voltage, as shown in FIG. 5. In contrast, in the semiconductor device 100 according to the example, the electron current in the first mesa portion 60-1 easily flows to the collector region 22. For this reason, snapback does not occur.

[0110] Fig. 6 is a diagram showing an example of measuring the voltage and current of a semiconductor device of a reference example. The semiconductor device of the reference example of Fig. 6 has a structure similar to that of the semiconductor device of the reference example of Fig. 5. Fig. 6 shows the time waveforms of the collector voltage Vce, collector current Ic, and gate voltage Vge of the semiconductor device. In Fig. 6, Vbus represents the voltage of the bus wiring connected to the collector of the semiconductor device, Ic represents the steady-state value of the collector current, Rg represents the gate resistance, and Tj represents the temperature of the measurement environment.

[0111] 6, the timing when a predetermined on-voltage is applied to the gate of the semiconductor device is set as reference time 0. The time required for the collector voltage Vce to decrease to 10% of the voltage value (600 V) in the off state is set as the turn-on time of the semiconductor device.

[0112] As the gate capacitance is charged, the gate voltage Vge increases. In this example, when the gate voltage Vge reaches approximately 440 V, a channel is formed in the base region 14. However, in the reference example, the electron current in the first mesa portion 60-1 does not easily flow to the collector region 22, so the rise of the collector current Ic is delayed and the fall of the collector voltage Vce is also delayed. This results in a relatively long turn-on time and increases the loss during turn-on.

[0113] FIG. 7 is a diagram showing an example of measuring the voltage and current of a semiconductor device according to an embodiment. The semiconductor device according to the embodiment shown in FIG. 7 is the semiconductor device 100 described with reference to FIGS. 1 to 4. In this embodiment, the electron current of the first mesa portion 60-1 easily flows to the collector region 22. Therefore, the delay in the rise of the collector current Ic and the fall of the collector voltage Vce is small. This results in a relatively short turn-on time, reducing loss during turn-on.

[0114] FIG. 8 is a diagram showing another example of measuring the voltage and current of the semiconductor device of the reference example. In this example, the steady-state value of the collector current Ic (150 A) is different from the steady-state value of the collector current Ic (15 A) of the reference example of FIG. 6. Other conditions are the same as those of the reference example of FIG. 6. In the reference example of FIG. 8, the rise of the collector current Ic is delayed, and the fall of the collector voltage Vce is also delayed. This results in a relatively long turn-on time, which increases the loss during turn-on.

[0115] FIG. 9 is a diagram showing another example of measuring the voltage and current of the semiconductor device of the embodiment. In this example, the steady-state value of the collector current Ic (150 A) is different from the steady-state value of the collector current Ic (15 A) of the embodiment of FIG. 7. Other conditions are the same as those of the embodiment of FIG. 7. In the embodiment of FIG. 9, the delay in the rise of the collector current Ic and the fall of the collector voltage Vce is also small. This results in a relatively short turn-on time, reducing loss during turn-on.

[0116] 10 is a diagram showing the trade-off characteristics between turn-on loss and reverse recovery dV / dt in the reference example and the working example, showing the trade-off relationship in which the turn-on loss increases when the reverse recovery dV / dv is reduced.

[0117] The reference example in Fig. 10 is a semiconductor device that does not have a floating region 202. The semiconductor device of the example is the semiconductor device 100 described with reference to Figs. 1 to 4. The semiconductor device 100 of the example has an improved trade-off characteristic by having the floating region 202. For example, when the reverse recovery dV / dt is the same, the turn-on loss of the example is smaller than that of the reference example.

[0118] As described in Fig. 10, the semiconductor device 100 can improve the trade-off characteristics between turn-on loss and reverse recovery dV / dt. As described in Fig. 5, the semiconductor device 100 can suppress snapback. As described in Figs. 6 to 9, the semiconductor device 100 can reduce the turn-on delay in the transistor portion 70.

[0119] 11 is a diagram showing another example of the ff cross section. The semiconductor device 100 of this example differs from the semiconductor device 100 of FIGS. 3 and 4 in the structure of the accumulation region 16. The other structures are similar to those of the semiconductor device 100 of any aspect described in this specification.

[0120] The accumulation region 16 in this example is in contact with the floating region 202. The accumulation region 16 may or may not be in contact with the base region 14. In each mesa portion, the lower ends of the accumulation regions 16 may be located at the same depth. The lower ends of the accumulation regions 16 may be located closer to the upper surface 21 than the lower end 43 of the first gate trench portion 40-1, or may be located closer to the lower surface 23 than the lower end 43, or may be located at the same depth as the lower end 43. The lower end of the accumulation region 16 in this example is located higher than the lower end of the floating region 202.

[0121] According to this example, since the high-concentration accumulation region 16 is disposed near the floating region 202, excessive diffusion of the P-type dopant in the floating region 202 can be suppressed, and the entire first mesa portion 60-1 can be suppressed from being covered with the floating region 202. For example, an N-type region is more likely to remain near the first dummy trench portion 30-1. This further facilitates suppressing the occurrence of snapback and the like.

[0122] 12 is a diagram showing another example of the ff cross section. The semiconductor device 100 of this example differs from the semiconductor device 100 in FIG. 11 in the structure of the accumulation region 16. The other structures are similar to those of the semiconductor device 100 of any aspect described in this specification.

[0123] In this example, the lower end of the accumulation region 16 is located lower than the lower end of the floating region 202. In this example, the floating region 202 is surrounded by the accumulation region 16 except for the portion that contacts the trench portion. The lower end of the accumulation region 16 may be located on the upper surface 21 side of the semiconductor substrate 10. The distance in the Z-axis direction between the lower end of the floating region 202 and the lower end of the accumulation region 16 may be 10 μm or less, 5 μm or less, or 3 μm or less.

[0124] According to this example, the floating region 202 is surrounded by the accumulation region 16. This prevents the P-type dopant in the floating region 202 from diffusing too much, which would otherwise cause the entire first mesa portion 60-1 to be covered by the floating region 202. For example, an N-type region is more likely to remain in the vicinity of the first dummy trench portion 30-1. This further facilitates preventing the occurrence of snapback and the like.

[0125] 13 is a diagram showing another example of the ff cross section. The semiconductor device 100 of this example differs from the semiconductor device 100 of the other examples in the arrangement of the floating region 202. The other structures are similar to those of the semiconductor device 100 of any of the aspects described in this specification.

[0126] The floating region 202 in this example is not in contact with the first gate trench portion 40-1. The floating region 202 is disposed below the lower end 43 of the first gate trench portion 40-1 and spaced apart from the lower end 43. In this example, the floating region 202 is also disposed on the upper surface 21 side of the semiconductor substrate 10. The distance in the Z-axis direction between the floating region 202 and the lower end 43 may be 10 μm or less, 5 μm or less, or 3 μm or less. This example makes it easier to ensure a path for electron current to flow from the first mesa portion 60-1 to the collector region 22. This makes it possible to further suppress the occurrence of snapback, etc.

[0127] 14 is a diagram showing another example of the ff cross section. The semiconductor device 100 of this example differs from the semiconductor device 100 of the other examples in the arrangement of the floating region 202. The other structures are similar to those of the semiconductor device 100 of any of the aspects described in this specification.

[0128] In this example, the floating region 202 is in contact with the first dummy trench portion 30-1. When the first dummy trench portions 30-1 are arranged on both sides of the first gate trench portion 40-1 in the X-axis direction, the floating region 202 may be in contact with both of the first dummy trench portions 30-1.

[0129] In this example, the floating region 202 does not extend below the lower end 33 of the first dummy trench portion 30-1. The floating region 202 may be in contact with the sidewall of the first dummy trench portion 30-1. The sidewall is the portion of the outer wall of the first dummy trench portion 30-1 other than the lower end 33. The sidewall of the first dummy trench portion 30-1 may be a flat portion of the outer wall of the first dummy trench portion 30-1. This example also makes it possible to improve the trade-off characteristics described above.

[0130] In this example, the dummy conductive portion 34 of the first dummy trench portion 30-1 may be a polysilicon electrode doped with N-type impurities. If the dummy conductive portion 34 is P-type polysilicon, the sidewall of the first dummy trench portion 30-1 and the floating region 202 will be at the same potential. In this case, the path through which the electron current flows from the channel is divided by the equipotential region, making it difficult for the electron current to flow. By making the dummy conductive portion 34 N-type, the sidewall of the first dummy trench portion 30-1 and the floating region 202 will be at different potentials. In this case, a path through which the electron current flows remains near the sidewall of the first dummy trench portion 30-1. This makes it possible to improve the trade-off characteristics of the semiconductor device 100 while suppressing the occurrence of snapback, etc.

[0131] The conductive portions of the trench portions other than the first dummy trench portion 30-1 may also be N-type polysilicon. The doping concentration of the N-type impurity in the dummy conductive portion 34 of the first dummy trench portion 30-1 may be higher than the doping concentration of the N-type impurity in the gate conductive portion 44 of the first gate trench portion 40-1. This makes it easier to ensure a path for electron current to flow near the sidewall of the first dummy trench portion 30-1. In another example, the conductive portions of at least some of the trench portions other than the first dummy trench portion 30-1 may be P-type polysilicon. For example, the conductive portion of the first gate trench portion 40-1 may be P-type polysilicon.

[0132] 15 is a diagram showing another example of the ff cross section. The semiconductor device 100 of this example differs from the semiconductor device 100 of the other examples in the arrangement pattern of the trench portions in the X-axis direction of the transistor portion 70. The structure other than the arrangement pattern of the trench portions is the same as that of the semiconductor device 100 of any of the aspects described in this specification.

[0133] The transistor section 70 in this example has two first gate trench sections 40-1 arranged adjacent to each other in the X-axis direction. As an example, the transistor section 70 has two first gate trench sections 40-1 and two first dummy trench sections 30-1 arranged alternately in the X-axis direction.

[0134] A floating region 202 is disposed below the lower end 43 of each first gate trench portion 40-1. The floating regions 202 below two first gate trench portions 40-1 adjacent to each other in the X-axis direction may be separated from each other as shown in FIG. 15 or may be connected to each other.

[0135] The mesa portion 60 sandwiched between two first gate trench portions 40-1 is referred to as the third mesa portion 60-3. The third mesa portion 60-3 may have the same structure as the first mesa portion 60-1. In another example, the third mesa portion 60-3 may have a structure different from that of the first mesa portion 60-1. The third mesa portion 60-3 may be sandwiched between the first mesa portions 60-1 in the X-axis direction. In this example, three or more first gate trench portions 40-1 are not arranged consecutively in the X-axis direction.

[0136] 16 is a diagram showing another example of the ff cross section. The semiconductor device 100 of this example differs from the semiconductor device 100 of the other examples in that it includes a bottom end region 204. The structure other than the bottom end region 204 is similar to that of the semiconductor device 100 of any of the aspects described in this specification.

[0137] The lower end region 204 is an N-type region provided below the lower end 33 of the first dummy trench portion 30-1. The doping concentration of the lower end region 204 is higher than the doping concentration of the drift region 18. The doping concentration of the lower end region 204 may be at least twice, at least five times, or at least ten times the doping concentration of the drift region 18. The doping concentration of the lower end region 204 may be higher or lower than the doping concentration of the floating region 202. By providing the lower end region 204, it is possible to prevent the vicinity of the lower end 33 of the first dummy trench portion 30-1 from becoming P-type, making it easier to ensure a path for electron current.

[0138] The lower end region 204 may be in contact with or spaced apart from the lower end 33 of the first dummy trench portion 30-1. The lower end of the lower end region 204 may be located above or below the lower end of the floating region 202. The lower end region 204 may be located away from or in contact with the accumulation region 16.

[0139] 17 is a diagram showing another example of the e-e cross section. The semiconductor device 100 of this example further includes a contact region 19 compared to the example shown in FIG. 3. The arrangement of the contact portion 54 is also different. The other structures are similar to those of the example shown in FIG.

[0140] The contact region 19 is provided in contact with the lower end of the contact portion 54, and is a P+ type region with a higher doping concentration than the base region 14. The doping concentration of the contact region 19 may be the same as that of the contact region 15. At least a part of the contact region 19 may be provided inside the base region 14. The contact portion 54 in the transistor section 70 may or may not be provided so as to penetrate the emitter region 12. In this example, the contact region 19 in the transistor section 70 is provided below the emitter region 12. Furthermore, the entire contact region 19 in the diode section 80 is provided inside the base region 14.

[0141] In each mesa portion in the ff cross section, the contact region 19 may be provided at the same depth as in the ee cross section. Moreover, when the emitter region 12 is provided instead of the contact region 15, the ff cross section has the same structure as in FIG.

[0142] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0143] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0144] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 18...Drift region, 19...Contact region, 20...Buffer region, 21...Upper surface, 22...Collector region, 23...Lower surface, 24...Collector electrode, 29...Straight portion, 30...Dummy trench portion, 30-1...First dummy trench portion, 31...Tip portion, 32...Dummy insulating film, 33...Lower end, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Straight portion, 40...Gate trench portion, 40-1...First gate trench portion, 41... ..tip portion, 42...gate insulating film, 43...bottom end, 44...gate conductive portion, 45...trench, 52...emitter electrode, 54...contact portion, 60, 61...mesa portion, 60-1...first mesa portion, 60-2...second mesa portion, 60-3...third mesa portion, 70...transistor portion, 80...diode portion, 81...extension region, 82...cathode region, 90...edge termination structure portion, 100...semiconductor device, 130...periphery gate wiring, 131...active side gate wiring, 160...active portion, 162...edge, 164...gate pad, 202...floating region, 204...bottom end region

Claims

1. A semiconductor device including an IGBT, a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; a first gate trench portion provided on the upper surface of the semiconductor substrate; a first dummy trench portion provided on the upper surface of the semiconductor substrate and arranged alongside the first gate trench portion on the upper surface; a first mesa portion sandwiched between the first gate trench portion and the first dummy trench portion within the semiconductor substrate; a second conductivity type floating region that is disposed below a lower end of the first gate trench portion on the upper surface side of the semiconductor substrate and does not extend below a lower end of the first dummy trench portion; Equipped with The first mesa portion includes: an emitter region of a first conductivity type provided in contact with the first gate trench portion and having a higher concentration than the drift region; a second conductivity type base region provided between the emitter region and the drift region and in contact with the first gate trench portion; and The lower end of the first dummy trench portion is in contact with a region of a first conductivity type.

2. The floating region is not in contact with the lower end of the first gate trench portion. The semiconductor device according to claim 1 .

3. The floating region is in contact with the lower end of the first gate trench portion. The semiconductor device according to claim 1 .

4. The first mesa portion is provided between the base region and the drift region and further includes an accumulation region of a first conductivity type having a higher concentration than the drift region. The semiconductor device according to claim 1 .

5. The accumulation region is in contact with the floating region. The semiconductor device according to claim 4 .

6. The lower end of the accumulation region is located lower than the lower end of the floating region. The semiconductor device according to claim 5 .

7. The lower end of the accumulation region is located above the lower end of the floating region. The semiconductor device according to claim 5 .

8. The first mesa portion is in contact with the upper surface of the semiconductor substrate and further includes a contact region of a second conductivity type having a higher concentration than the base region. The semiconductor device according to claim 1 .

9. The first mesa portion further includes a contact portion that is provided from the upper surface of the semiconductor substrate to the inside of the first mesa portion and is filled with a conductive material. The semiconductor device according to claim 8 .

10. The lower end of the contact portion is in contact with the contact region. The semiconductor device according to claim 9 .

11. The first dummy trench portion is provided on both sides of the first gate trench portion. The semiconductor device according to claim 1 .

12. The floating region is in contact with a sidewall of the first dummy trench portion. The semiconductor device according to claim 1 .

13. The first dummy trench portion has a polysilicon electrode doped with a first conductivity type impurity. The semiconductor device according to claim 12.

14. a lower end region of the first conductivity type provided in contact with a lower end of the first dummy trench portion and having a higher concentration than the drift region; The semiconductor device according to claim 1 .

15. The semiconductor substrate further includes two dummy trench portions provided on the upper surface thereof and arranged side by side on the upper surface. The semiconductor device according to claim 1 .

16. The interval between the first gate trench portion and the first dummy trench portion is the same as the interval between the two dummy trench portions. The semiconductor device according to claim 15.

17. Further comprising diode portions arranged alternately with the IGBTs in a first direction; the IGBT disposed between the diode portions has a plurality of trench portions including the first gate trench portion and the first dummy trench portion and arranged side by side in the first direction; The intervals between the trench portions in the plurality of trench portions are the same. The semiconductor device according to claim 1 .

18. A lower end of the first dummy trench portion is located at the same depth as a part of the floating region. The semiconductor device according to claim 1 .

19. The depth position of the lower end of the first gate trench portion is equal to the depth position of the lower end of the first dummy trench portion. The semiconductor device according to claim 1 .

20. At least a portion of the gate conductive portion to which the gate voltage of the first gate trench portion is applied is located at the same depth as at least a portion of the floating region. The semiconductor device according to claim 1 .

21. The width of the contact portion is smaller than the width of the first mesa portion. The semiconductor device according to claim 9 .