Input circuit
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2023-08-23
- Publication Date
- 2026-05-21
Abstract
Description
Input circuit
[0001] The present disclosure relates to an input circuit (hereinafter simply referred to as "input circuit") that receives a signal from outside an LSI.
[0002] As transistors constituting LSIs become smaller, the voltage stress that the transistors can withstand (hereinafter simply referred to as "voltage resistance") is decreasing. As a result, an input circuit may receive a signal from outside the LSI whose voltage exceeds the transistor's voltage resistance. To address this issue, an input circuit is known that includes a conversion circuit that converts the voltage of an input signal received from outside the LSI into a voltage that does not exceed the transistor's voltage resistance.
[0003] For example, Patent Document 1 discloses an input circuit provided with the above-mentioned conversion circuit.
[0004] U.S. Patent No. 1,119,0187
[0005] However, as semiconductor devices become increasingly miniaturized, and the breakdown voltage of transistors further decreases, a voltage exceeding the breakdown voltage may be input, causing deterioration of the transistors over time.
[0006] Therefore, an input circuit is needed that can convert the input signal into an appropriate voltage and prevent the transistor from deteriorating over time, even if the withstand voltage of the transistor continues to decrease.
[0007] The present invention aims to solve the above problems.
[0008] An input circuit according to one aspect of the present disclosure includes an input buffer, a first voltage conversion circuit, a second voltage conversion circuit, and a third voltage conversion circuit. The input buffer includes a first transistor of a first conductivity type having a source connected to a first power supply, a drain connected to a first node, and a gate connected to a second node, a second transistor of the first conductivity type having a source connected to the first node, a drain connected to an output terminal, and a gate connected to a third node, a third transistor of a second conductivity type having a source connected to the second power supply, a drain connected to a fourth node, and a gate connected to a fifth node, and a fourth transistor of the second conductivity type having a source connected to the fourth node, a drain connected to the output terminal, and a gate connected to the third node. The first voltage conversion circuit includes a fifth transistor of the first conductivity type provided between the input terminal and the second node and having a gate connected to a first bias power supply, and a sixth transistor of the first conductivity type provided between the first bias power supply and the second node and having a gate connected to the input terminal. The second voltage conversion circuit includes a seventh transistor of a second conductivity type that is provided between the input terminal and the fifth node and has a gate connected to a second bias power supply, and an eighth transistor of a second conductivity type that is provided between the second bias power supply and the fifth node and has a gate connected to the input terminal. The third voltage conversion circuit includes a ninth transistor of a second conductivity type that is provided between the second node and the third node and has a gate connected to the second bias power supply, and a tenth transistor of a second conductivity type that is provided between the second bias power supply and the third node and has a gate connected to the second node.
[0009] According to the present disclosure, it is possible to prevent the transistor from deteriorating over time.
[0010] 1. Circuit diagram showing an example of the configuration of an input circuit according to a first embodiment. 2. Circuit diagram showing an example of the configuration of an input circuit according to a second embodiment. 3. Circuit diagram showing an example of the configuration of an input circuit according to a third embodiment. 4. Circuit diagram showing an example of the configuration of an input circuit according to a fifth embodiment. 5. Circuit diagram showing an example of the configuration of an input circuit according to a sixth embodiment. 6. Circuit diagram showing an example of the configuration of an input circuit according to a seventh embodiment. 7. Circuit diagram showing an example of the configuration of an input circuit according to an eighth embodiment.
[0011] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same reference numerals may be used to refer to power supply nodes and power supply voltages supplied to the power supply nodes. Also, the same reference numerals may be used to refer to terminals and signals passing through the terminals, and to nodes and signals passing through the nodes.
[0012] LSIs are broadly classified into internal circuits that drive transistors with relatively low voltage resistance at low voltages, and interface circuits that drive transistors with relatively high voltage resistance at high voltages for transmitting and receiving signals to and from the outside of the LSI. The input circuit according to the present disclosure is mainly included in the interface circuit.
[0013] First Embodiment An input circuit 10 according to this embodiment will be described with reference to FIG.
[0014] The input circuit 10 according to this embodiment includes an input buffer 4, a first voltage conversion circuit 1, a second voltage conversion circuit 2, and a third voltage conversion circuit 3.
[0015] -Input Buffer- The input buffer 4 includes a P-type (corresponding to a first conductivity type) transistor P1 and a P-type transistor P2 connected in series between a power supply VDD (corresponding to a first power supply) and an output terminal OUT, and an N-type (corresponding to a second conductivity type) transistor N2 and an N-type transistor N1 connected in series between the output terminal OUT and a ground VSS (corresponding to a second power supply).
[0016] In the input buffer 4 of the present disclosure, the gates of the transistors P1 and P2 are independent, and the gates of the transistors N1 and N2 are independent. The gates of the transistors P2 and N2 are connected to a node Ld (corresponding to a third node).
[0017] The transistor P1 (corresponding to the first transistor) has a source connected to the power supply VDD, a drain connected to a node Le (corresponding to the first node), and a gate connected to a node La (corresponding to the second node). The transistor P2 (corresponding to the second transistor) has a source connected to the node Le, a drain connected to the output terminal OUT, and a gate connected to a node Ld. The transistor N1 (corresponding to the third transistor) has a source connected to the ground VSS, a drain connected to a node Lf (corresponding to the fourth node), and a gate connected to a node Lb (corresponding to the fifth node). The transistor N2 (corresponding to the fourth transistor) has a source connected to the node Lf, a drain connected to the output terminal OUT, and a gate connected to the node Ld.
[0018] -First Voltage Conversion Circuit- The first voltage conversion circuit 1 is provided between the input terminal IN and a node La, and includes a P-type transistor P3 and a P-type transistor P4. The voltage of the input signal IN input to the input terminal IN varies between the voltage VSS and the voltage VDD.
[0019] The transistor P3 (corresponding to the fifth transistor) is provided between the input terminal IN and the node La, and has its gate connected to the bias power supply VbiasP (corresponding to the first bias power supply). The transistor P4 (corresponding to the sixth transistor) is provided between the bias power supply VbiasP and the node La, and has its gate connected to the input terminal IN.
[0020] The power supply voltage of the bias power supply VbiasP is higher than the power supply voltage of the ground VSS and is equal to or lower than the power supply voltage of a bias power supply VbiasN (described later). The power supply voltage of the bias power supply VbiasN is lower than the power supply voltage of the power supply VDD. That is, the relationship between the power supply voltages is VSS<VbiasP≦VbiasN<VDD.
[0021] - Second Voltage Conversion Circuit - The second voltage conversion circuit 2 is provided between the input terminal IN and the node Lb, and includes an N-type transistor N3 and an N-type transistor N4.
[0022] The transistor N3 (corresponding to the seventh transistor) is provided between the input terminal IN and the node Lb, and has its gate connected to the bias power supply VbiasN (corresponding to the second bias power supply). The transistor N4 (corresponding to the eighth transistor) is provided between the bias power supply VbiasN and the node Lb, and has its gate connected to the input terminal IN.
[0023] The third voltage conversion circuit 3 is provided between the node La and the node Ld, and includes an N-type transistor N5 and an N-type transistor N6. The configuration of the third voltage conversion circuit 3 is the same as that of the second voltage conversion circuit 2.
[0024] The transistor N5 (corresponding to the ninth transistor) is provided between the node La and the node Ld, and has its gate connected to the bias power supply VbiasN. The transistor N6 (corresponding to the tenth transistor) is provided between the bias power supply VbiasN and the node Ld, and has its gate connected to the node La.
[0025] - Operation of Input Circuit - Next, the operation of the input circuit 10 will be described. In the following description, the voltage of each terminal and each node will be expressed as "(terminal name or node name) = (symbol indicating voltage)". Specifically, when the voltage of the input terminal IN is VDD (the voltage of the power supply VDD), it will be expressed as IN = VDD. Similarly, when the voltage of the node La is VbiasP (the voltage of the first bias power supply), it will be expressed as La = VbiasP. The same applies to the other embodiments.
[0026] When IN=VSS, transistor P3 turns off and transistor P4 turns on, resulting in La=VbiasP. Then, transistor N5 turns on and transistor N6 turns off, resulting in Ld=VbiasP. Furthermore, transistor N3 turns on and transistor N4 turns off, resulting in Lb=VSS. As a result, transistors P1 and P2 turn on, transistor N1 turns off, and OUT=VDD.
[0027] When IN=VDD, transistor P3 turns on and transistor P4 turns off, resulting in La=VDD. Then, transistor N5 turns off and transistor N6 turns on, resulting in Ld=VbiasN. Also, transistor N3 turns off and transistor N4 turns on, resulting in Lb=VbiasN. This turns transistor P1 off, transistors N1 and N2 turn on, resulting in OUT=VSS.
[0028] Table 1 below shows the voltages of each node when IN=VSS and IN=VDD. Also, Figure 2 shows the transition of the voltage of each node when the input signal IN changes linearly from VSS to VDD from time t1 to time t2, and then changes linearly from VDD to VSS from time t3 to time t4.
[0029]
[0030] As shown in Table 1, the terminal voltage of each transistor depends on VDD, VbiasP, and VbiasN. Specifically, when IN=VDD, the gate-drain voltage of transistor P2, i.e., the potential difference between node Ld and output terminal OUT, is VbiasN. Furthermore, when IN=VSS, the gate-drain voltage of transistor N2, i.e., the potential difference between node Ld and output terminal OUT, is "VDD-VbiasP." Furthermore, as shown in FIG. 2, the voltage of node Ld, which corresponds to the voltage range of the gates (X, Y) of transistors M2 and M3 in Patent Document 1, transitions between VbiasP and VbiasN.
[0031] As a result, for example, by determining the values of VbiasP and VbiasN (bias power supply voltage values) so as not to exceed the breakdown voltages of transistors P2 and N2, it is possible to prevent deterioration of the transistors over time. Furthermore, even if the breakdown voltages of transistors further decrease in semiconductor devices that are becoming increasingly miniaturized, it is possible to similarly prevent deterioration over time.
[0032] In this embodiment, VbiasP can be equal to VbiasN as long as the voltage resistance of each transistor is not exceeded. Furthermore, the bias power supply VbiasP and / or the bias power supply VbiasN can be replaced with the voltage of the internal circuit. This allows for a reduction in the number of power supplies. Furthermore, the input circuit 10 according to this embodiment can be configured using the same low-voltage transistors as the internal circuit, making it applicable to semiconductor devices that do not have high-voltage transistors. This also applies to the embodiments described below.
[0033] Second Embodiment Next, an input circuit 10 according to this embodiment will be described with reference to FIG. 3. In FIG. 3, components corresponding to those in FIG. 1 are denoted by the same reference numerals. However, this embodiment (FIG. 3) is not intended to limit the components denoted by the same reference numerals as those in the first embodiment (FIG. 1). In other words, the voltages, characteristics, etc. of components denoted by the same reference numerals in this embodiment and the first embodiment may differ from each other. The same applies to the relationship between this embodiment and other embodiments, and to the relationship between the other embodiments.
[0034] In the following description, differences from the first embodiment will be mainly described, and overlapping descriptions may be omitted.
[0035] In this embodiment, as shown in FIG. 3 , the configuration of the third voltage conversion circuit 3 differs from that of the first embodiment ( FIG. 1 ). In this embodiment, with regard to transistors, an N-type transistor corresponds to a first conductivity type transistor, and a P-type transistor corresponds to a second conductivity type transistor. With regard to power supplies, the ground VSS corresponds to the first power supply, the power supply VDD corresponds to the second power supply, the bias power supply VbiasN corresponds to the first bias power supply, and the bias power supply VbiasP corresponds to the second bias power supply. With regard to nodes, the node Lf corresponds to the first node, the node Lb corresponds to the second node, the node Ld corresponds to the third node, the node Le corresponds to the fourth node, and the node La corresponds to the fifth node.
[0036] The third voltage conversion circuit 3 is provided between the node Lb and the node Ld, and includes a P-type transistor P5 and a P-type transistor P6. The configuration of the third voltage conversion circuit 3 is the same as that of the first voltage conversion circuit 1.
[0037] The transistor P5 (corresponding to the ninth transistor) is provided between the node Lb and the node Ld, and has its gate connected to the bias power supply VbiasP. The transistor P6 (corresponding to the tenth transistor) is provided between the bias power supply VbiasP and the node Ld, and has its gate connected to the node Lb.
[0038] In this embodiment, in the input buffer 4, the transistor N1 corresponds to a first transistor of a first conductivity type, the transistor N2 corresponds to a second transistor of the first conductivity type, the transistor P1 corresponds to a third transistor of a second conductivity type, and the transistor P2 corresponds to a fourth transistor of the second conductivity type.
[0039] In the first voltage conversion circuit 1 (corresponding to the second voltage conversion circuit), the transistor P3 corresponds to a seventh transistor of the second conductivity type, and the transistor P4 corresponds to an eighth transistor of the second conductivity type.
[0040] In the second voltage conversion circuit 2 (corresponding to the first voltage conversion circuit), the transistor N3 corresponds to a fifth transistor of the first conductivity type, and the transistor N4 corresponds to a sixth transistor of the first conductivity type.
[0041] --Operation of Input Circuit-- Next, the operation of the input circuit 10 will be described.
[0042] When IN=VSS, transistor N3 turns on and transistor N4 turns off, resulting in Lb=VSS. Then, transistor P5 turns off and transistor P6 turns on, resulting in Ld=VbiasP. Also, transistor P3 turns off and transistor P4 turns on, resulting in La=VbiasP. This causes transistors P1 and P2 to turn on, transistor N1 to turn off, and OUT=VDD.
[0043] When IN=VDD, transistor N3 turns off and transistor N4 turns on, resulting in Lb=VbiasN. Then, transistor P5 turns on and transistor P6 turns off, resulting in Ld=VbiasN. Also, transistor P3 turns on and transistor P4 turns off, resulting in La=VDD. This turns transistor P1 off, transistors N1 and N2 turn on, resulting in OUT=VSS.
[0044] Table 2 below shows the voltages at each node when IN=VSS and IN=VDD.
[0045]
[0046] As shown in Table 2, the voltage at each node relative to the input voltage IN is the same as in the first embodiment. Although not shown, the voltage transition at each node is also the same as the waveform in FIG. 2, and the same effects as in the first embodiment can be obtained.
[0047] That is, according to this embodiment, as in the first embodiment, the inter-terminal voltage of each transistor depends on VDD, VbiasP, and VbiasN. Specifically, when IN=VDD, the gate-drain voltage of transistor P2, i.e., the potential difference between node Ld and output terminal OUT, is VbiasN. Furthermore, when IN=VSS, the gate-drain voltage of transistor N2, i.e., the potential difference between node Ld and output terminal OUT, is "VDD-VbiasP."
[0048] As a result, for example, by determining the values of VbiasP and VbiasN (bias power supply voltage values) so as not to exceed the breakdown voltages of transistors P2 and N2, it is possible to prevent deterioration of the transistors over time. Furthermore, even if the breakdown voltages of transistors further decrease in semiconductor devices that are becoming increasingly miniaturized, it is possible to similarly prevent deterioration over time.
[0049] Third Embodiment Next, an input circuit 10 according to this embodiment will be described with reference to Fig. 4. In Fig. 4, components corresponding to those in Fig. 1 are denoted by the same reference numerals. In the following description, differences from the first embodiment will be mainly described, and overlapping descriptions may be omitted.
[0050] In the first embodiment, since the third voltage conversion circuit 3 is connected to node La, the load of the first voltage conversion circuit 1 that drives node La is greater than the load of the second voltage conversion circuit 2 that drives node Lb. As a result, a delay may occur in the signal propagating through node La relative to the signal at node Lb. Therefore, this embodiment is configured to solve the above problem.
[0051] Specifically, as shown in FIG. 4, the configuration and connection destination of the third voltage conversion circuit 3 differ from those of the first embodiment (FIG. 1).
[0052] -Third voltage conversion circuit- The third voltage conversion circuit 3 is provided between the input terminal IN and node Ld, and is configured by connecting in series a second conversion circuit 32 having the same circuit configuration as the third voltage conversion circuit 3 of the second embodiment and a first conversion circuit 31 having the same circuit configuration as the third voltage conversion circuit 3 of the first embodiment.
[0053] The second conversion circuit 32 is provided between the input terminal IN and a node Lc (corresponding to the sixth node) and includes a P-type transistor P5 and a P-type transistor P6. The transistor P5 (corresponding to the ninth transistor) is provided between the input terminal IN and the node Lc, and its gate is connected to a bias power supply VbiasP. The transistor P6 (corresponding to the tenth transistor) is provided between the bias power supply VbiasP and the node Lc, and its gate is connected to the input terminal IN.
[0054] The first conversion circuit 31 is provided between the node Lc and the node Ld and includes an N-type transistor N5 and an N-type transistor N6. The transistor N5 (corresponding to the eleventh transistor) is provided between the node Lc and the node Ld and has a gate connected to a bias power supply VbiasN. The transistor N6 (corresponding to the twelfth transistor) is provided between the bias power supply VbiasN and the node Ld and has a gate connected to the node Lc.
[0055] -Operation of Input Circuit- Next, we will explain the operation of the input circuit 10. Here, since the circuit configurations of the first voltage conversion circuit 1, the second voltage conversion circuit 2, and the input buffer 4 are the same as in the first embodiment, the states of the nodes La and Lb are the same as in the first embodiment.
[0056] In addition, since the configuration of the second conversion circuit 32 is the same as that of the first voltage conversion circuit 1, the state of node La and the state of node Lc are the same. Furthermore, the series circuit of the second conversion circuit 32 and the first conversion circuit 31 has the same circuit configuration as the series circuit of the first voltage conversion circuit 1 and the third voltage conversion circuit 3 in Fig. 1. Therefore, the state of node Ld in this embodiment is the same as the state of node Ld in the first embodiment.
[0057] Table 3 below shows the voltages at each node when IN=VSS and IN=VDD.
[0058]
[0059] As described above, according to this embodiment, as in the first embodiment, the terminal voltage of each transistor depends on VDD, VbiasP, and VbiasN. Specifically, when IN=VDD, the gate-drain voltage of transistor P2, i.e., the potential difference between node Ld and output terminal OUT, is VbiasN. Furthermore, when IN=VSS, the gate-drain voltage of transistor N2, i.e., the potential difference between node Ld and output terminal OUT, is "VDD-VbiasP."
[0060] As a result, for example, by determining the values of VbiasP and VbiasN (bias power supply voltage values) so as not to exceed the breakdown voltages of transistors P2 and N2, it is possible to prevent deterioration of the transistors over time. Furthermore, even if the breakdown voltages of transistors further decrease in semiconductor devices that are becoming increasingly miniaturized, it is possible to similarly prevent deterioration over time.
[0061] Furthermore, by connecting the third voltage conversion circuit 3 between the input terminal IN and node Ld, it is possible to reduce the load on the first voltage conversion circuit 1 and reduce the signal delay at node La relative to the signal at node Lb, thereby shortening the delay time of signals propagating through the circuit and increasing the operating speed of the input circuit 10.
[0062] Fourth Embodiment Next, an input circuit 10 according to this embodiment will be described with reference to Fig. 5. In Fig. 5, components corresponding to those in Fig. 3 are denoted by the same reference numerals. In the following description, differences from the second embodiment will be mainly described, and overlapping descriptions may be omitted.
[0063] In the second embodiment, since the third voltage conversion circuit 3 is connected to node Lb, the load of the second voltage conversion circuit 2 that drives node Lb is greater than the load of the first voltage conversion circuit 1 that drives node La. As a result, a delay may occur in the signal propagating through node Lb relative to the signal at node La. Therefore, this embodiment is configured to solve the above problem.
[0064] Specifically, as shown in FIG. 5, the configuration and connection destination of the third voltage conversion circuit 3 differ from those of the second embodiment (FIG. 3).
[0065] -Third voltage conversion circuit- The third voltage conversion circuit 3 is provided between the input terminal IN and the node Ld, and is configured by connecting in series a first conversion circuit 31 having the same circuit configuration as the third voltage conversion circuit 3 of the first embodiment and a second conversion circuit 32 having the same circuit configuration as the third voltage conversion circuit 3 of the second embodiment.
[0066] The first conversion circuit 31 is provided between the input terminal IN and a node Lc (corresponding to the sixth node) and includes an N-type transistor N5 and an N-type transistor N6. The transistor N5 (corresponding to the ninth transistor) is provided between the input terminal IN and the node Lc, with its gate connected to a bias power supply VbiasN. The transistor N6 (corresponding to the tenth transistor) is provided between the bias power supply VbiasN and the node Lc, with its gate connected to the input terminal IN.
[0067] The second conversion circuit 32 is provided between the nodes Lc and Ld and includes a P-type transistor P5 and a P-type transistor P6. The transistor P5 (corresponding to the eleventh transistor) is provided between the nodes Lc and Ld, and its gate is connected to the bias power supply VbiasP. The transistor P6 (corresponding to the twelfth transistor) is provided between the bias power supply VbiasP and the node Ld, and its gate is connected to the node Lc.
[0068] -Operation of Input Circuit- Next, we will explain the operation of the input circuit 10. Here, since the circuit configurations of the first voltage conversion circuit 1, the second voltage conversion circuit 2, and the input buffer 4 are the same as in the second embodiment, the states of the nodes La and Lb are the same as in the second embodiment.
[0069] Furthermore, since the configuration of the first conversion circuit 31 is the same as that of the second voltage conversion circuit 2, the state of node Lb and the state of node Lc are the same. Furthermore, the series circuit of the first conversion circuit 31 and the second conversion circuit 32 has the same circuit configuration as the series circuit of the second voltage conversion circuit 2 and the third voltage conversion circuit 3 in Fig. 3. Therefore, the state of node Ld in this embodiment is the same as the state of node Ld in the second embodiment.
[0070] Table 4 below shows the voltages at each node when IN=VSS and IN=VDD.
[0071]
[0072] As described above, according to this embodiment, as in the second embodiment, the inter-terminal voltage of each transistor depends on VDD, VbiasP, and VbiasN. Specifically, when IN=VDD, the gate-drain voltage of transistor P2, i.e., the potential difference between node Ld and output terminal OUT, is VbiasN. Furthermore, when IN=VSS, the gate-drain voltage of transistor N2, i.e., the potential difference between node Ld and output terminal OUT, is "VDD-VbiasP."
[0073] Fifth Embodiment Next, an input circuit 10 according to this embodiment will be described with reference to Fig. 6. In Fig. 6, components corresponding to those in Fig. 1 are denoted by the same reference numerals. In the following description, differences from the first embodiment will be mainly described, and overlapping descriptions may be omitted.
[0074] In the first embodiment, while the input voltage IN is transitioning from VSS to VDD, the transistor P4 is turned on when "IN≦VbiasP−Vthp (Vthp=threshold value of a P-type transistor)" and, when turned on, conducts between the bias power supply VbiasP and node La. The transistor P3 is turned on when "IN≧VbiasP+Vthp" and, when turned on, conducts between the input terminal IN and node La. Furthermore, during the period "VbiasP−Vthp<IN<VbiasP+Vthp", both the transistors P3 and P4 are turned off. The transistor N3 is turned on when "IN≦VbiasN−Vthn (Vthn=threshold value of an N-type transistor)" and, when turned on, conducts between the input terminal IN and node Lb. Transistor N4 turns on when "IN≧VbiasN+Vthn." When turned on, the bias power supply VbiasN and node Lb are electrically connected. Furthermore, during the period "VbiasN-Vthn<IN<VbiasN+Vthn," transistors N3 and N4 are both off. Similarly, transistors N5 and N6 are both off during the period "VbiasN-Vthn<La<VbiasN+Vthn." In each of the voltage conversion circuits 1 to 3, signals are not transmitted during the period when the transistors are off. This can cause the transitions at nodes La, Lb, and Ld to stagnate or become unstable, as indicated by the dashed circles in FIG. 2 . As a result, the signal change at the output terminal OUT can be delayed. Therefore, this embodiment is configured to solve the above problem.
[0075] 1, a first buffer circuit B1 and a second buffer circuit B2 are added, and transistors are added to the first voltage conversion circuit 1, the second voltage conversion circuit 2, and the third voltage conversion circuit 3.
[0076] -First Buffer Circuit- The first buffer circuit B1 includes a P-type transistor P11 and a first inverter INV1. The transistor P11 (corresponding to the eleventh transistor) has a source connected to a node Le, a drain connected to a bias power supply VbiasP, and a gate connected to an output terminal OUT. The first inverter INV1 is provided between the node Le and a node Lg (corresponding to the sixth node). The first inverter INV1 has a first power supply terminal T11 connected to the power supply VDD and a second power supply terminal T12 connected to the bias power supply VbiasP.
[0077] - Second Buffer Circuit - The second buffer circuit B2 includes an N-type transistor N13 and a second inverter INV2. The transistor N13 (corresponding to the twelfth transistor) has a source connected to node Lf, a drain connected to a bias power supply VbiasN, and a gate connected to the output terminal OUT. The second inverter INV2 is provided between node Lf and node Lh (corresponding to the seventh node). The second inverter INV2 has a first power supply terminal T21 connected to the bias power supply VbiasN and a second power supply terminal T22 connected to ground VSS.
[0078] In addition to the circuit configuration of the first embodiment, the first voltage conversion circuit 1 further includes an N-type transistor N7 (corresponding to a thirteenth transistor) provided between the input terminal IN and a node La and having its gate connected to a node Lh. The second voltage conversion circuit 2 further includes a P-type transistor P7 (corresponding to a fourteenth transistor) provided between the input terminal IN and a node Lb and having its gate connected to a node Lg. The third voltage conversion circuit 3 further includes a P-type transistor P8 (corresponding to a fifteenth transistor) provided between the nodes La and Ld and having its gate connected to a node Lg.
[0079] - Operation of Input Circuit - Next, the operation of the input circuit 10 will be described with reference to Fig. 7. Here, the differences from the first embodiment will be mainly described.
[0080] First, at time t1, when IN=VSS, transistors P1 and P2 are turned on, Le=VDD, Lg=VbiasP, and transistors P7 and P8 are turned off. Also, transistors N1 and N2 are turned off, transistor N13 is turned on, Lf=VbiasN, Lh=VSS, and transistor N7 is turned off.
[0081] During the transition from IN=VSS to IN=VDD between time t1 and time t2, transistor N3 turns on, causing the voltage at node Lb to rise, which in turn causes transistor N1 to turn on, causing the voltages at output terminal OUT and node Lf to fall. During this transition, transistor N13 turns off, the second inverter INV2 inverts, and Lh becomes VbiasN. Therefore, transistor N7 turns on during the period "IN≦VbiasN−Vthn." This turns on transistor N7 during the period "VbiasP−Vthp<IN≦VbiasN−Vthn," which corresponds to the period when transistors P3 and P4 are off in the first embodiment, establishing electrical continuity between input terminal IN and node La. Therefore, the voltage at node La rises as the voltage at input terminal IN rises (see FIG. 7).
[0082] Furthermore, during the transition from IN=VSS to IN=VDD, transistor P7 is turned on during the period "IN≧VbiasP+Vthp." As a result, transistor P7 is turned on during the period "VbiasP+Vthp≦IN<VbiasN+Vthn," which corresponds to the period during which transistors N3 and N4 are off in the first embodiment, and the input terminal IN and node Lb are electrically connected. Therefore, the voltage at node Lb rises as the voltage at input terminal IN rises (see FIG. 7).
[0083] Similarly, transistor P8 is turned on during the period "La≧VbiasP+Vthp." As a result, transistor P8 is turned on during the period "VbiasP+Vthp≦La<VbiasN+Vthn," which corresponds to the period when transistors N5 and N6 are off, and node La and node Ld are conductive. Therefore, the voltage at node Ld rises in accordance with the transition of the voltage at node La, that is, with the rise in the voltage at input terminal IN.
[0084] Between time t2 and time t3, when IN=VDD, transistors P1 and P2 are turned off, transistor P11 is turned on, Le=VbiasP, Lg=VDD, transistors P7 and P8 are turned off, transistors N1 and N2 are turned on, transistor N13 is turned off, Lf=VSS, Lh=VbiasN, and transistor N7 is turned off.
[0085] During the transition from IN=VDD to IN=VSS between time t3 and time t4, transistors P7, P8, and N7 are turned on for the same period as the transition from IN=VSS to IN=VDD, and the voltages of the nodes decrease as the voltage at the input terminal IN decreases (see Figure 7).
[0086] As described above, according to this embodiment, the transistors N7, P7, and P8 are turned on during the period when the common circuits of the voltage conversion circuits 1 to 3 with the first embodiment are turned off. This makes it possible to prevent the transition of each node from becoming stagnant or unstable, and to speed up the signal change at the output terminal OUT.
[0087] Sixth Embodiment Next, an input circuit 10 according to this embodiment will be described with reference to Fig. 8. In Fig. 8, components corresponding to those in Fig. 6 are denoted by the same reference numerals. The following description will focus on differences from the fifth embodiment, and redundant description may be omitted.
[0088] In this embodiment, as shown in Fig. 8, the configuration of the third voltage conversion circuit 3 differs from that of the fifth embodiment (Fig. 6). In this embodiment, with regard to transistors, N-type transistors correspond to first conductivity type transistors, and P-type transistors correspond to second conductivity type transistors. With regard to power supplies, the ground VSS corresponds to the first power supply, the power supply VDD corresponds to the second power supply, the bias power supply VbiasN corresponds to the first bias power supply, and the bias power supply VbiasP corresponds to the second bias power supply. With regard to nodes, the node Lf corresponds to the first node, the node Lb corresponds to the second node, the node Ld corresponds to the third node, the node Le corresponds to the fourth node, and the node La corresponds to the fifth node.
[0089] Similar to the problem with the first embodiment described in the fifth embodiment, in the second embodiment, signals are not propagated in each of the voltage conversion circuits 1 to 3 while the transistors are off. This may cause the transitions at the nodes La, Lb, and Ld to stagnate or become unstable. As a result, the signal change at the output terminal OUT may be delayed. Therefore, this embodiment is configured to solve the above problem.
[0090] The third voltage conversion circuit 3 is provided between the node Lb and the node Ld, and includes a P-type transistor P5, a P-type transistor P6, and an N-type transistor N8. The configuration of the third voltage conversion circuit 3 is the same as that of the first voltage conversion circuit 1.
[0091] Transistor P5 (corresponding to the ninth transistor) is provided between node Lb and node Ld, and has its gate connected to bias power supply VbiasP. Transistor P6 (corresponding to the tenth transistor) is provided between bias power supply VbiasP and node Ld, and has its gate connected to node Lb. Transistor N8 (corresponding to the fifteenth transistor) is provided between node Lb and node Ld, and has its gate connected to node Lh.
[0092] - Operation of Input Circuit - Next, the operation of the input circuit 10 will be described, focusing on the differences from the fifth embodiment.
[0093] First, when IN=VSS at time t1, Lb=VSS and Lh=VSS, and the transistor N8 is turned off.
[0094] During the transition from IN=VSS to IN=VDD between time t1 and time t2, when Lh=VbiasN, transistor N8 turns on for the period "Lb≦VbiasN−Vthn". As a result, transistor N8 turns on for the period "VbiasP−Vthp<Lb≦VbiasN−Vthn", which corresponds to the period when transistors P5 and P6 are off (the same as transistors P3 and P4), and nodes Lb and Ld become conductive. Therefore, node Ld rises as node Lb rises, i.e., as the input terminal IN rises.
[0095] When IN=VDD between time t2 and time t3, Lb=VbiasN and Lh=VbiasN, and transistor N8 is turned off.
[0096] During the transition from IN=VDD to IN=VSS between time t3 and time t4, transistor N8 is turned on for the same period as during the transition from IN=VSS to IN=VDD. Therefore, node Ld falls as node Lb falls, i.e., as the voltage at input terminal IN falls.
[0097] This embodiment also provides the same effects as the fifth embodiment. Specifically, during the period when the common circuits of the voltage conversion circuits 1 to 3 with the second embodiment are off, the transistors N7, N8, and P7 are on. This makes it possible to prevent the transition of each node from becoming stagnant or unstable, and to speed up the signal change at the output terminal OUT.
[0098] Seventh Embodiment Next, an input circuit 10 according to this embodiment will be described with reference to FIG.
[0099] In the third embodiment described above, the configuration of the second conversion circuit 32 of the third voltage conversion circuit 3 is the same as the configuration of the first voltage conversion circuit 1. Therefore, the transition state of node Lc accompanying the transition of the input terminal IN is the same as that of node La. Furthermore, in the third embodiment, the circuit configuration other than the third voltage conversion circuit 3 is the same as in the first embodiment. Therefore, the configuration of the third embodiment (see FIG. 4 ) has a problem common to the description of the fifth embodiment, namely, there is a case where the signal change at the output terminal OUT is delayed. Therefore, this embodiment is configured to solve the above problem.
[0100] The input circuit 10 according to this embodiment has a configuration that combines the third embodiment and the fifth embodiment. Specifically, the input circuit 10 according to this embodiment includes a first buffer circuit B1 and a second buffer circuit B2, similar to the fifth embodiment, in addition to the circuit configuration of the third embodiment. Furthermore, transistors are added to the first voltage conversion circuit 1, the second voltage conversion circuit 2, and the third voltage conversion circuit 3 according to the third embodiment.
[0101] Specifically, in addition to the circuit configuration of the third embodiment, the first voltage conversion circuit 1 further includes an N-type transistor N7 (corresponding to the fifteenth transistor) provided between the input terminal IN and node La and having its gate connected to node Lh. The second voltage conversion circuit 2 further includes a P-type transistor P7 (corresponding to the sixteenth transistor) provided between the input terminal IN and node Lb and having its gate connected to node Lg. The third voltage conversion circuit 3 includes an N-type transistor N8 (corresponding to the seventeenth transistor) provided between the input terminal IN and node Lc and having its gate connected to node Lh, and a P-type transistor P8 (corresponding to the eighteenth transistor) provided between nodes Lc and Ld and having its gate connected to node Lg.
[0102] - Operation of Input Circuit - Regarding the operation of the input circuit 10, the operation of the transistor N8 is the same as that of the transistor N7 according to the fifth embodiment. Furthermore, other additional components are the same as those of the fifth embodiment. Therefore, detailed description thereof will be omitted here.
[0103] As described above, according to this embodiment, transistors P7, P8, N7, and N8 are turned on during the period when the common circuits of the voltage conversion circuits 1 to 3 with the third embodiment are turned off. This makes it possible to prevent the transition of each node from becoming stagnant or unstable, and to speed up the signal change at the output terminal OUT.
[0104] Eighth Embodiment Next, an input circuit 10 according to this embodiment will be described with reference to FIG.
[0105] In the fourth embodiment described above, the configuration of the first conversion circuit 31 of the third voltage conversion circuit 3 is the same as the configuration of the second voltage conversion circuit 2. Therefore, the transition state of node Lc accompanying the transition of the input terminal IN is the same as that of node Lb. Furthermore, in the fourth embodiment, the circuit configuration other than that of the third voltage conversion circuit 3 is the same as that of the second embodiment. Therefore, the configuration of the fourth embodiment (see FIG. 5 ) has a problem common to that described in the sixth embodiment, namely, there is a case where the signal change at the output terminal OUT is delayed. Therefore, this embodiment is configured to solve the above problem.
[0106] The input circuit 10 according to this embodiment has a configuration that combines the fourth and sixth embodiments. Specifically, the input circuit 10 according to this embodiment includes a first buffer circuit B1 and a second buffer circuit B2 in addition to the circuit configuration of the fourth embodiment. Furthermore, transistors are added to the first voltage conversion circuit 1, second voltage conversion circuit 2, and third voltage conversion circuit 3 according to the third embodiment.
[0107] Specifically, in addition to the circuit configuration of the fourth embodiment, the first voltage conversion circuit 1 further includes an N-type transistor N7 (corresponding to the fifteenth transistor) provided between the input terminal IN and node La and having its gate connected to node Lh. The second voltage conversion circuit 2 further includes a P-type transistor P7 (corresponding to the sixteenth transistor) provided between the input terminal IN and node Lb and having its gate connected to node Lg. The third voltage conversion circuit 3 includes a P-type transistor P8 (corresponding to the seventeenth transistor) provided between the input terminal IN and node Lc and having its gate connected to node Lg, and an N-type transistor N8 (corresponding to the eighteenth transistor) provided between nodes Lc and Ld and having its gate connected to node Lh.
[0108] - Operation of Input Circuit - Regarding the operation of the input circuit 10, the operation of the transistor P8 is the same as that of the transistor P7 according to the sixth embodiment. Furthermore, other additional components are the same as those of the sixth embodiment. Therefore, detailed description thereof will be omitted here.
[0109] As described above, according to this embodiment, transistors P7, P8, N7, and N8 are turned on during the period when the common circuits of the voltage conversion circuits 1 to 3 with the fourth embodiment are turned off. This makes it possible to prevent the transition of each node from becoming stagnant or unstable, and to speed up the signal change at the output terminal OUT.
[0110] INDUSTRIAL APPLICABILITY The input circuit according to the present disclosure is extremely useful in semiconductor devices that are becoming increasingly miniaturized, because it can prevent deterioration of transistors over time even if the breakdown voltage of the transistors further decreases.
[0111] 1 First voltage conversion circuit 2 Second voltage conversion circuit 3 Third voltage conversion circuit 4 Input buffer 10 Input circuit IN Input terminal La Node (second node) Lb Node (fifth node) Ld Node (third node) Le Node (first node) Lf Node (fourth node) N1 Transistor (third transistor) N2 Transistor (fourth transistor) N3 Transistor (seventh transistor) N4 Transistor (eighth transistor) N5 Transistor (ninth transistor) N6 Transistor (tenth transistor) OUT Output terminal P1 Transistor (first transistor) P2 Transistor (second transistor) P3 Transistor (fifth transistor) P4 Transistor (sixth transistor) VDD Power supply (first power supply) VSS Ground (second power supply) VbiasN Bias power supply (second bias power supply) VbiasP Bias power supply (first bias power supply)
Claims
1. A semiconductor device comprising an input buffer, a first voltage conversion circuit, a second voltage conversion circuit, and a third voltage conversion circuit, wherein the input buffer comprises: a first transistor of a first conductivity type having a source connected to a first power supply, a drain connected to a first node, and a gate connected to a second node; a second transistor of the first conductivity type having a source connected to the first node, a drain connected to an output terminal, and a gate connected to a third node; a third transistor of a second conductivity type having a source connected to a second power supply, a drain connected to a fourth node, and a gate connected to a fifth node; and a fourth transistor of a second conductivity type having a source connected to the fourth node, a drain connected to the output terminal, and a gate connected to the third node; the first voltage conversion circuit comprises: a fifth transistor of a first conductivity type provided between an input terminal and the second node, and having a gate connected to a first bias power supply; and a sixth transistor of a first conductivity type provided between the first bias power supply and the second node, and having a gate connected to the input terminal; an eighth transistor of a second conductivity type provided between the input terminal and the fifth node, the gate of which is connected to a second bias power supply; and an eighth transistor of a second conductivity type provided between the second bias power supply and the fifth node, the gate of which is connected to the input terminal; and the third voltage conversion circuit comprises: a ninth transistor of a second conductivity type provided between the second node and the third node, the gate of which is connected to the second bias power supply; and a tenth transistor of a second conductivity type provided between the second bias power supply and the third node, the gate of which is connected to the second node.
2. An input circuit according to claim 1, further comprising: a first buffer circuit comprising an eleventh transistor of a first conductivity type having a source connected to the first node, a drain connected to the first bias power supply, and a gate connected to the output terminal; and a first inverter provided between the first node and a sixth node, with a first power supply terminal connected to the first power supply and a second power supply terminal connected to the first bias power supply; and a second buffer circuit comprising a twelfth transistor of a second conductivity type having a source connected to the fourth node, a drain connected to the second bias power supply, and a gate connected to the output terminal; and a second inverter provided between the fourth node and a seventh node, with a first power supply terminal connected to the second bias power supply and a second power supply terminal connected to the second power supply; the first voltage conversion circuit comprising a thirteenth transistor of a second conductivity type provided between the input terminal and the second node, with a gate connected to the seventh node; and the second voltage conversion circuit comprising a fourteenth transistor of a first conductivity type provided between the input terminal and the fifth node, with a gate connected to the sixth node; the third voltage conversion circuit comprises a fifteenth transistor of a first conductivity type provided between the second node and the third node, the fifteenth transistor having a gate connected to the sixth node.
3. An input circuit as claimed in claim 1 or 2, characterized in that: the first conductivity type is P-type, the second conductivity type is N-type, the power supply voltage of the first bias power supply is higher than the power supply voltage of the second power supply and is equal to or lower than the power supply voltage of the second bias power supply, and the power supply voltage of the second bias power supply is lower than the power supply voltage of the first power supply.
4. An input circuit as claimed in claim 1 or 2, characterized in that: the first conductivity type is N-type, the second conductivity type is P-type, the power supply voltage of the second bias power supply is higher than the power supply voltage of the first power supply and is equal to or lower than the power supply voltage of the first bias power supply, and the power supply voltage of the first bias power supply is lower than the power supply voltage of the second power supply.
5. A semiconductor device comprising an input buffer, a first voltage conversion circuit, a second voltage conversion circuit, and a third voltage conversion circuit, wherein the input buffer comprises: a first transistor of a first conductivity type having a source connected to a first power supply, a drain connected to a first node, and a gate connected to a second node; a second transistor of a first conductivity type having a source connected to the first node, a drain connected to an output terminal, and a gate connected to a third node; a third transistor of a second conductivity type having a source connected to a second power supply, a drain connected to a fourth node, and a gate connected to a fifth node; and a fourth transistor of a second conductivity type having a source connected to the fourth node, a drain connected to the output terminal, and a gate connected to the third node; the first voltage conversion circuit comprises: a fifth transistor of a first conductivity type provided between an input terminal and the second node, and having a gate connected to a first bias power supply; and a sixth transistor of a first conductivity type provided between the first bias power supply and the second node, and having a gate connected to the input terminal; an eighth transistor of a second conductivity type provided between the input terminal and the fifth node, the gate of which is connected to a second bias power supply; and an eighth transistor of a second conductivity type provided between the second bias power supply and the fifth node, the gate of which is connected to the input terminal; and the third voltage conversion circuit comprises: a ninth transistor of a first conductivity type provided between the input terminal and a sixth node, the gate of which is connected to the first bias power supply; a tenth transistor of a first conductivity type provided between the first bias power supply and the sixth node, the gate of which is connected to the input terminal; an eleventh transistor of a second conductivity type provided between the sixth node and the third node, the gate of which is connected to the second bias power supply; and a twelfth transistor of a second conductivity type provided between the second bias power supply and the third node, the gate of which is connected to the sixth node.
6. An input circuit according to claim 5, further comprising: a first buffer circuit comprising a thirteenth transistor of a first conductivity type having a source connected to the first node, a drain connected to the first bias power supply, and a gate connected to the output terminal; and a first inverter provided between the first node and a seventh node, with a first power supply terminal connected to the first power supply and a second power supply terminal connected to the first bias power supply; and a second buffer circuit comprising a fourteenth transistor of a second conductivity type having a source connected to the fourth node, a drain connected to the second bias power supply, and a gate connected to the output terminal; and a second inverter provided between the fourth node and an eighth node, with a first power supply terminal connected to the second bias power supply and a second power supply terminal connected to the second power supply; the first voltage conversion circuit comprising a fifteenth transistor of a second conductivity type provided between the input terminal and the second node, with a gate connected to the eighth node; and the second voltage conversion circuit comprising a sixteenth transistor of a first conductivity type provided between the input terminal and the fifth node, with a gate connected to the seventh node; the third voltage conversion circuit comprises: a 17th transistor of a second conductivity type provided between the input terminal and the sixth node, the 17th transistor having a gate connected to the eighth node, and an 18th transistor of a first conductivity type provided between the sixth node and the third node, the 18th transistor having a gate connected to the seventh node.
7. An input circuit as claimed in claim 5 or 6, characterized in that: the first conductivity type is P-type, the second conductivity type is N-type, the power supply voltage of the first bias power supply is higher than the power supply voltage of the second power supply and is equal to or lower than the power supply voltage of the second bias power supply, and the power supply voltage of the second bias power supply is lower than the power supply voltage of the first power supply.
8. An input circuit as claimed in claim 5 or 6, characterized in that: the first conductivity type is N-type, the second conductivity type is P-type, the power supply voltage of the second bias power supply is higher than the power supply voltage of the first power supply and is equal to or lower than the power supply voltage of the first bias power supply, and the power supply voltage of the first bias power supply is lower than the power supply voltage of the second power supply.