Field effect transistor, integrated circuit, electronic device, method for switching polarity of field effect transistor, and method for changing integrated circuit

Abstract

A field effect transistor according to the present invention includes: a semiconductor substrate composed of a single crystal semiconductor having a resistivity of 0.01 kΩ cm or more at an arbitrary temperature or an impurity concentration of 1×1016 / cm3 or less; a gate insulating layer in contact with the semiconductor substrate; a control gate electrode in contact with the gate insulating layer; one or a plurality of storage gate electrodes in contact with the gate insulating layer and arranged side by side with the control gate electrode; and a terminal electrode in contact with the semiconductor substrate.

Description

Field effect transistor, integrated circuit, electronic device, method for switching polarity of field effect transistor, and method for modifying integrated circuit

[0001] An embodiment of the present invention relates to a field effect transistor, an integrated circuit, an electronic device, a method for switching the polarity of a field effect transistor, and a method for modifying an integrated circuit.

[0002] Semiconductor technology has become indispensable in modern society, with CMOS logic gates being a particularly important technology. A logic gate is a circuit that performs logical operations on input digital signals consisting of "0" and "1." Logical operations based on logic gates enable a variety of information processing functions, such as controlling electronic devices and computers, and image processing. CMOS technology is the technology that realizes logic gates, which function as the basic elements of such various electronic circuits. CMOS technology uses field-effect transistors (hereinafter referred to as "MOS-FETs") with a MOS (Metal-Oxide-Semiconductor) structure as the basic element. Specifically, CMOS technology refers to the technology that realizes logic gates by complementarily combining n-type MOS-FETs and p-type MOS-FETs.

[0003] Typically, MOS-FETs are manufactured through a process in which an impurity that imparts n-type conductivity (e.g., phosphorus) or an impurity that imparts p-type conductivity (e.g., boron) is implanted into a semiconductor substrate containing a predetermined impurity (e.g., boron). This impurity implantation process forms n-type MOS-FETs and p-type MOS-FETs at predetermined positions on the semiconductor substrate. These MOS-FETs are then electrically connected by wiring to form logic gates using CMOS technology.

[0004] US Patent Application Publication No. 2011 / 0121400

[0005] In the conventional CMOS technology described above, n-type or p-type MOS-FETs are manufactured by implanting predetermined impurities into a semiconductor substrate, so the polarity of the MOS-FET cannot be changed after manufacture. In other words, the function (circuit configuration) of the CMOS logic gates formed on the semiconductor substrate cannot be changed afterward. Therefore, the product specifications of integrated circuits manufactured by combining CMOS logic gates cannot be physically changed.

[0006] The present invention has been made in view of the above problems, and aims to provide a technology for realizing a CMOS logic gate whose specifications can be physically changed. In particular, the present invention aims to provide a field-effect transistor whose polarity can be changed after the fact.

[0007] In one embodiment of the present invention, the field effect transistor has a resistivity of 0.01 kΩ·cm or more at any temperature or an impurity concentration of 1×10 １６ / cm ３ The semiconductor device includes a semiconductor substrate made of the following single crystal semiconductor, a gate insulating layer in contact with the semiconductor substrate, a control gate electrode in contact with the gate insulating layer, one or more storage gate electrodes in contact with the gate insulating layer and arranged side by side with the control gate electrode, and a terminal electrode in contact with the semiconductor substrate.

[0008] In a plan view, the plurality of storage gate electrodes may be arranged with the control gate electrode sandwiched therebetween.

[0009] The gate insulating layer may be in contact with a first surface of the semiconductor substrate, and the terminal electrode may be in contact with a second surface of the semiconductor substrate that is continuous with the first surface and has a normal direction different from that of the first surface.

[0010] The one or more storage gate electrodes may be switchably connected to a first power supply line providing a positive voltage and a second power supply line providing a negative voltage.

[0011] The field effect transistor may operate as an N-type transistor when the positive voltage is applied to the one or more storage gate electrodes, and may operate as a P-type transistor when the negative voltage is applied to the one or more storage gate electrodes.

[0012] A programmable integrated circuit according to one embodiment of the present invention includes any of the field effect transistors having the above-described configurations.

[0013] An electronic device according to one embodiment of the present invention includes a programmable integrated circuit including any of the field-effect transistors having the above-described configurations, and a light-shielding housing that surrounds the programmable integrated circuit.

[0014] In the electronic device, a light emitting unit capable of irradiating the semiconductor substrate with light may be disposed inside the housing, and the housing may have an opening (specifically, an opening for irradiating light).

[0015] In the electronic device, a heat supply unit capable of supplying heat to the semiconductor substrate may be disposed inside the housing. The heat supply unit may be a thermoelectric element.

[0016] In one embodiment of the present invention, a method for switching polarity of a field effect transistor is provided, wherein the field effect transistor has a resistivity of 0.01 kΩ cm or more at any temperature or an impurity concentration of 1×10 １６ / cm ３ The device comprises a semiconductor substrate made of the following single-crystal semiconductor, a gate insulating layer in contact with the semiconductor substrate, a control gate electrode in contact with the gate insulating layer, one or more storage gate electrodes in contact with the gate insulating layer and arranged side by side with the control gate electrode, and a terminal electrode in contact with the semiconductor substrate: The method includes supplying light or heat to the semiconductor substrate while applying a positive or negative voltage to the one or more storage gate electrodes, or applying a positive or negative voltage to the one or more storage gate electrodes while supplying light or heat to the semiconductor substrate.

[0017] In the method, the positive voltage may be applied to the one or more storage gate electrodes of the field effect transistor operated as an N-type transistor, and the negative voltage may be applied to the one or more storage gate electrodes of the field effect transistor operated as a P-type transistor.

[0018] A method for modifying an integrated circuit according to one embodiment of the present invention includes modifying the configuration of a logic circuit using the field effect transistors by the method described above.

[0019] FIG. 1 is a perspective view showing a schematic structure of a MOS-FET according to one embodiment of the present invention. FIG. 2 is a cross-sectional view showing a schematic structure of a MOS-FET according to one embodiment of the present invention. FIG. 3 is a diagram for explaining the function of a storage gate electrode in a MOS-FET according to one embodiment of the present invention. FIG. 4 is a diagram for explaining the function of a storage gate electrode in a MOS-FET according to one embodiment of the present invention. FIG. 5 is a diagram for explaining the operation of a MOS-FET according to one embodiment of the present invention when it is in an off state. FIG. 6 is a diagram for explaining the operation of a MOS-FET according to one embodiment of the present invention when it is in an on state. FIG. 7 is a schematic diagram showing the energy band state of a semiconductor substrate when the MOS-FET is in an off state. FIG. 8 is a schematic diagram of an experimental sample used in an experiment to verify the function of the storage gate electrode. FIG. 9 is a diagram showing the resistance value (R ２ｔ ) back gate voltage (V ＢＧ 4B is an enlarged view of the range of back gate voltages from −20 V to 20 V in FIG. 4B. The dependence of capacitance (C) on back gate voltage (V ＢＧ ) is a graph showing the dependence of the resistance (R ２ｔ13B is a diagram showing a change in the capacitance of a MOS-FET according to an embodiment of the present invention. FIG. 13C is a perspective view showing a schematic structure of a MOS-FET according to an embodiment of the present invention. FIG. 13D is a cross-sectional view showing a schematic structure of a MOS-FET according to an embodiment of the present invention. FIG. 13E is a cross-sectional view showing a schematic structure of a MOS-FET according to an embodiment of the present invention. FIG. 13F is a cross-sectional view showing a schematic structure of a MOS-FET according to an embodiment of the present invention. FIG. 13G is a cross-sectional view showing a schematic structure of a MOS-FET according to an embodiment of the present invention. FIG. 13H is a cross-sectional view showing a schematic structure of a MOS-FET according to an embodiment of the present invention. FIG. 13I is a cross-sectional view showing a schematic structure of a MOS-FET according to an embodiment of the present invention. FIG. 13J is a cross-sectional view showing a schematic structure of a MOS-FET according to an embodiment of the present invention. FIG. 13J is a cross-sectional view showing a schematic structure of a MOS-FET according to an embodiment of the present invention. While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments and is not to be construed as limiting the scope of the invention.

[0020] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be embodied in various forms without departing from the spirit of the present invention, and should not be construed as being limited to the description of the embodiments exemplified below. To clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part more schematically than the actual form, but these are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those described with reference to the previous drawings may be assigned the same reference numerals, and redundant explanations may be omitted.

[0021] In each embodiment of the present invention, for convenience of explanation, the direction from the semiconductor substrate toward the control gate electrode will be referred to as "up" or "upper," and the opposite direction will be referred to as "lower" or "lower." However, these terms are merely expressions for explaining the relative positional relationship of each element. In the drawings, if the up-down relationship between the semiconductor substrate and the control gate electrode is reversed, the control gate electrode may be located below or below the semiconductor substrate. Note that an expression that another element is located above (or below) a certain element does not preclude the presence of another element between the certain element and the other element, unless otherwise specified.

[0022] In each embodiment of the present invention, when a plurality of elements having the same function are provided, the elements may be described by adding an alphabet (a, b, c, etc.) to the reference numerals indicating the individual elements to distinguish between them. However, even when the reference numerals of the elements are added with an alphabet in the drawings, when there is no particular need to distinguish between the elements, the elements may be described by using only the reference numerals.

[0023] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0024] First Embodiment A MOS-FET according to one embodiment of the present invention will be described. In this embodiment, an n-type MOS-FET will be described as an example of the MOS-FET, but the same explanation can be given for a p-type MOS-FET, except that the polarity is reversed.

[0025] [MOS-FET Structure] Fig. 1A is a perspective view showing a schematic structure of a MOS-FET 100 according to one embodiment of the present invention. Fig. 1B is a cross-sectional view showing a schematic structure of a MOS-FET 100 according to one embodiment of the present invention. As shown in Fig. 1A, the MOS-FET 100 includes a semiconductor substrate 110, a gate insulating layer 120, a control gate electrode 130, storage gate electrodes 140a and 140b, and terminal electrodes 150a and 150b.

[0026] The semiconductor substrate 110 is a substrate made of, for example, silicon (Si) or silicon-germanium (SiGe). In this embodiment, a single-crystal silicon substrate is used as the semiconductor substrate 110. However, the semiconductor material is not limited to these examples, and other compound semiconductors having a heterostructure may also be used. There are no particular restrictions on the thickness of the semiconductor substrate 110 in this embodiment, but it may be selected, for example, from the range of 200 μm to 800 μm. In this embodiment, the thickness of the semiconductor substrate 110 (strictly speaking, the thickness directly below the control gate electrode 130) is set to 500 μm.

[0027] In the MOS-FET 100 of this embodiment, an intrinsic or substantially intrinsic semiconductor substrate (a so-called non-doped semiconductor substrate) is used as the semiconductor substrate 110. Specifically, a semiconductor substrate having a resistivity of 0.01 kΩ cm or more (preferably 0.1 kΩ cm or more, and more preferably 1 kΩ cm or more) in a given temperature range is used as the semiconductor substrate 110. In other words, the semiconductor substrate 110 used in this embodiment has an impurity concentration of 1×10 １６ / cm ３ or less (preferably 1 × 10 １５ / cm ３ More preferably, 1×10 １４ / cm ３ (See below).

[0028] When a semiconductor substrate 110 that satisfies the above conditions is used, the carrier concentration present in the semiconductor substrate 110 at room temperature, for example, is very small, and the semiconductor substrate 110 can be said to be substantially intrinsic. In other words, the semiconductor substrate 110 can be said to be a semiconductor substrate to which substantially no impurities have been added (i.e., non-doped). When such a semiconductor is used as the channel of a MOS-FET, it is difficult to induce carriers by applying a gate voltage. However, in this embodiment, a semiconductor substrate with a higher resistivity than conventional semiconductor substrates (i.e., a semiconductor substrate with a low impurity concentration) is intentionally used.

[0029] In the semiconductor substrate 110 of this embodiment, the portions where the terminal electrodes 150a and 150b are provided are relatively lower than the portions where the control gate electrode 130 and the storage gate electrode 140 are provided. That is, in the MOS-FET 100 of this embodiment, the semiconductor substrate 110 is processed to have a convex shape in cross section, the reason for which will be described later.

[0030] The gate insulating layer 120 is provided on the semiconductor substrate 110 so as to be in contact with the semiconductor substrate 110. Specifically, the gate insulating layer 120 of this embodiment is provided on the convex portion of the semiconductor substrate 110.

[0031] The gate insulating layer 120 may be an insulating layer made of silicon oxide (SiOx), silicon nitride (SixNy), or silicon oxynitride (SixOyNz). When silicon oxide is used as the material, the gate insulating layer 120 may be a silicon oxide layer formed by subjecting the semiconductor substrate 110 to a thermal oxidation treatment. However, instead of or in addition to the silicon-based insulating material, other insulating layers made of aluminum oxide (AlOx), hafnium oxide (HfOx), or the like may be used as the gate insulating layer 120. There are no particular limitations on the film thickness of the gate insulating layer 120, and it may be selected from the range of 5 nm to 100 nm, for example.

[0032] The control gate electrode 130 is provided on the gate insulating layer 120. That is, the control gate electrode 130 faces the semiconductor substrate 110 via the gate insulating layer 120. This structure is a so-called MOS structure. In the MOS-FET 100 of this embodiment, the width of the control gate electrode 130 in the direction connecting the terminal electrodes 150a and 150b is called the "effective channel length." As shown in FIG. 1B, the control gate electrode 130 has a gate voltage (V ＣＧ ) is supplied.

[0033] A metal electrode made of a metal such as aluminum (Al), tantalum (Ta), molybdenum (Mo), tungsten (W), titanium (Ti), or copper (Cu), or a metal compound containing these metals, can be used as the control gate electrode 130. Alternatively, a silicon electrode made conductive by adding impurities to a silicon pattern can also be used as the control gate electrode 130.

[0034] A predetermined gate voltage (V ＣＧ 1B, in order to show that different voltages can be supplied, a variable power supply 215 is electrically connected via a power supply line 210. However, the method of supplying the gate voltage is not limited to this example. For example, a predetermined gate voltage may be supplied by appropriately switching between a power supply line connected to a high-potential power supply and a power supply line connected to a low-potential power supply.

[0035] The storage gate electrodes 140a and 140b are provided on the gate insulating layer 120, similar to the control gate electrode 130. That is, the storage gate electrodes 140a and 140b each constitute a MOS structure facing the semiconductor substrate 110 via the gate insulating layer 120. In this embodiment, the control gate electrode 130 and the storage gate electrode 140 are formed in the same process. That is, the storage gate electrode 140 is formed using the same material as the control gate electrode 130. However, this is not limiting, and the control gate electrode 130 and the storage gate electrode 140 can also be formed using different materials.

[0036] In the MOS-FET 100 of this embodiment, the storage gate electrode 140 has a function of storing carriers (electrons or holes) in a portion of the semiconductor substrate 110 that faces the storage gate electrode 140 via the gate insulating layer 120. As shown in FIG. 1B, the storage gate electrode 140 is applied with a storage voltage (V ＡＧ ) is supplied. ＡＧ ) is a voltage for attracting the above-mentioned carriers, and a voltage of opposite polarity to the polarity of the carriers is supplied. For example, a positive accumulation voltage is supplied to attract electrons as carriers, and a negative accumulation voltage is supplied to attract holes. The accumulation voltage may be a fixed voltage or a pulsed voltage. For example, a high-speed pulsed voltage (a high-frequency pulsed voltage) may be supplied as the accumulation voltage, thereby making it possible to supply a substantially positive or negative voltage.

[0037] As described above, the storage gate electrode 140 has the function of attracting carriers of a desired polarity and storing the carriers of the desired polarity via the gate insulating layer 120. The specific role of the storage gate electrode 140 will be described later.

[0038] 1B, in order to show that a positive or negative storage voltage can be supplied, a variable power supply 225 is electrically connected via a power supply line 220. However, the method of supplying the storage voltage is not limited to this example, and for example, a predetermined storage voltage may be supplied by appropriately switching between a power supply line connected to a power supply that outputs a positive voltage and a power supply line connected to a power supply that outputs a negative voltage.

[0039] The terminal electrodes 150a and 150b function as source and drain electrodes of the MOS-FET 100. As shown in FIGS. 1A and 1B , the terminal electrodes 150a and 150b of this embodiment are arranged to face each other with a portion of the semiconductor substrate 110 sandwiched therebetween. Here, the surface of the semiconductor substrate 110 that contacts the gate insulating layer 120 is referred to as the first surface 111. The first surface 111 of the semiconductor substrate 110 can also be said to be the surface where carriers accumulate. Next, the surface that is continuous with the first surface 111 and has a different normal direction from the first surface 111 is referred to as the second surface 112. In the example of FIGS. 1A and 1B , the top surface of the convex portion of the convex-shaped semiconductor substrate 110 is the first surface 111, and the side surface is the second surface 112. The terminal electrodes 150a and 150b contact the second surface 112.

[0040] As will be described in detail later, the MOS-FET 100 of this embodiment forms a current path (hereinafter referred to as a "channel") using carriers accumulated below the storage gate electrode 140. Therefore, in order to reduce the resistance component between the terminal electrodes 150a and 150b and the channel as much as possible, it is desirable to position the terminal electrodes 150a and 150b as close as possible to the channel formed below the storage gate electrode 140. For this reason, this embodiment is structured so that current is extracted from the second surface 112 of the semiconductor substrate 110, which has a normal direction different from that of the first surface 111 where the channel is formed.

[0041] In this embodiment, the terminal electrodes 150a and 150b are formed by a process different from that of the control gate electrode 130 and the storage gate electrode 140. That is, the terminal electrodes 150a and 150b are formed of a material different from that of the control gate electrode 130 and the storage gate electrode 140. For example, the terminal electrodes 150a and 150b are preferably formed using a metal material with a relatively low resistance, such as a metal compound containing aluminum or copper as a main component.

[0042] The element structure of the MOS-FET 100 of this embodiment has been described so far, but the MOS-FET 100 can be manufactured using known semiconductor manufacturing processes. The gate insulating layer 120 can be formed using a chemical vapor deposition (CVD) method. The control gate electrode 130, storage gate electrode 140, and terminal electrode 150 can be formed by forming a metal layer by a sputtering method and then patterning it using an etching technique using photolithography.

[0043] Furthermore, etching techniques using photolithography can also be used when processing the semiconductor substrate 110 into a convex pattern. In this embodiment, after the gate insulating layer 120, the control gate electrode 130, and the storage gate electrode 140 are formed on the semiconductor substrate 110, photoresist is formed by photolithography so as to cover the control gate electrode 130 and the storage gate electrode 140. Then, using the photoresist as a mask, dry etching is performed on the gate insulating layer 120 and the semiconductor substrate 110 in that order, and the semiconductor substrate 110 is etched to a desired depth. However, the method of patterning the semiconductor substrate 110 is not limited to this example, and various known methods can be used.

[0044] 1A and 1B, the device structure of the MOS-FET 100 of this embodiment has been described. Next, the operation of the MOS-FET 100 of this embodiment will be described. Before describing the operation of the MOS-FET 100, the function of the storage gate electrode 140 in the MOS-FET 100 will first be described.

[0045] 2A and 2B are diagrams illustrating the function of storage gate electrode 140 in MOS-FET 100 according to one embodiment of the present invention. Specifically, Fig. 2A is an example of forming an n-type MOS-FET 100, and Fig. 2B is an example of forming a p-type MOS-FET 100. Figs. 2A and 2B correspond to schematic diagrams of a portion of MOS-FET 100 shown in Fig. 1 that is composed of semiconductor substrate 110, gate insulating layer 120, and storage gate electrode 140.

[0046] In FIG. 2A, the left diagram shows a state where no voltage is applied to the storage gate electrode 140 (i.e., storage voltage V ＡＧ =0), and the diagram on the right shows a state where a positive voltage is applied to the storage gate electrode 140 (i.e., storage voltage V ＡＧ The semiconductor substrate 110 is assumed to be grounded in both the left and right figures.

[0047] As described above, the semiconductor substrate 110 of this embodiment is substantially an intrinsic semiconductor. Therefore, in the state shown in the left diagram, almost no carriers (electrons) exist inside the semiconductor substrate 110. Therefore, even if a positive voltage (a positive voltage of 10 V in this embodiment) is supplied to the storage gate electrode 140 in the left diagram, no carriers (electrons) are attracted.

[0048] In contrast, as shown in the right diagram, when the semiconductor substrate 110 is irradiated with light, the energy of the absorbed light generates electron-hole pairs inside the semiconductor substrate 110 (internal photoelectric effect). At this time, when a positive voltage (the aforementioned 10 V positive voltage) is supplied to the storage gate electrode 140, electrons generated inside the semiconductor substrate 110 are attracted to the storage gate electrode 140 and stored near the interface of the semiconductor substrate 110 with the gate insulating layer 120. That is, the MOS-FET 100 of this embodiment can accumulate electrons below the storage gate electrode 140 by simultaneously irradiating the semiconductor substrate 110 with light and supplying a positive voltage to the storage gate electrode 140. However, "simultaneously" does not mean that the timing of light irradiation and voltage supply are synchronized, but rather means that the periods during which light irradiation and voltage supply are overlapped. Therefore, either the timing of light irradiation or the timing of voltage supply can occur first.

[0049] 2B shows how carriers (holes) are accumulated below the storage gate electrode 140 through the same operation as described above. In FIG. 2B, in order to attract holes generated inside the semiconductor substrate 110, a negative voltage is supplied to the storage gate electrode 140 while irradiating the semiconductor substrate 110 with light. As a result, holes are attracted below the storage gate electrode 140, and the holes are accumulated as carriers near the interface between the semiconductor substrate 110 and the gate insulating layer 120.

[0050] In the light irradiation process of the semiconductor substrate 110 described above, light having a wavelength shorter than the wavelength corresponding to the bandgap of the semiconductor (single crystal silicon in this embodiment) that is the material of the semiconductor substrate 110 is irradiated. For example, when the semiconductor substrate 110 is made of single crystal silicon, the wavelength corresponding to the energy bandgap (1.1 eV) of single crystal silicon is 1127 nm. Therefore, light in the visible light range or ultraviolet light range irradiated onto the semiconductor substrate 110 is absorbed by the semiconductor substrate 110, and electron-hole pairs are generated by the energy imparted to the semiconductor substrate 110 during this absorption. In this way, when single crystal silicon is used as the semiconductor substrate 110, the light irradiation process can be performed using a small, low-power light source such as an LED.

[0051] Even if light irradiation is stopped, the carriers attracted by the storage gate electrode 140 to the vicinity of the first surface 111 of the semiconductor substrate 110 will not disappear as long as an accumulation voltage is continuously supplied to the storage gate electrode 140. That is, after the above-described voltage supply to the storage gate electrode 140 and the light irradiation process on the semiconductor substrate 110 are performed, the state in which the carriers are accumulated below the storage gate electrode 140 can be maintained by stopping the light irradiation process and continuing to supply voltage to the storage gate electrode 140.

[0052] As described above, the storage gate electrode 140 included in the MOS-FET 100 of this embodiment can retain desired carriers (electrons or holes) near the first surface 111 of the semiconductor substrate 110 (i.e., near the interface between the semiconductor substrate 110 and the gate insulating layer 120) by controlling the polarity of the voltage supplied to the storage gate electrode 140. Specifically, by irradiating the semiconductor substrate 110 with light while supplying a positive voltage to the storage gate electrode 140, electrons can be induced below the storage gate electrode 140, making the polarity of the MOS-FET 100 n-type. Conversely, by irradiating the semiconductor substrate 110 with light while supplying a negative voltage to the storage gate electrode 140, holes can be induced below the storage gate electrode 140, making the polarity of the MOS-FET 100 p-type.

[0053] The operation of the MOS-FET 100 of this embodiment will be described below, taking into account the above-described function of the storage gate electrode 140. The MOS-FET 100 described below is in a state in which electrons are stored below the storage gate electrode 140 due to the above-described operation, i.e., in a state in which n-type polarity is imparted.

[0054] FIG. 3A is a diagram illustrating the operation of MOS-FET 100 according to one embodiment of the present invention when it is in an off state. FIG. 3B is a diagram illustrating the operation of MOS-FET 100 according to one embodiment of the present invention when it is in an on state. FIG. 3C is a schematic diagram illustrating the energy band state of semiconductor substrate 110 when MOS-FET 100 is in an off state. FIG. 3D is a schematic diagram illustrating the energy band state of semiconductor substrate 110 when MOS-FET 100 is in an on state. As described above, all of the MOS-FETs 100 described using FIGS. 3A to 3D are examples in which the polarity is n-type.

[0055] As shown in FIG. 3A, when MOS-FET 100 is in the off state, a positive voltage (V ＡＧ>0) is supplied to the control gate electrode 130, and electrons are stored below the storage gate electrode 140. As described above, in this embodiment, a current path formed by carriers stored below the storage gate electrode 140 is called a channel. The channel 10 shown in FIG. 3A is a current path formed by electrons being stored near the first surface 111 of the semiconductor substrate 110. However, in the off state shown in FIG. 3A, a gate voltage (V ＣＧ ) is not supplied, there is no channel directly below the control gate electrode 130.

[0056] 3C shows the energy band state when the n-type MOS-FET 100 is in the off state (the state shown in FIG. 3A). The horizontal axis represents the distance from the second surface 112 in contact with the terminal electrode 150a, and the vertical axis represents energy. EC represents the conduction band, EF represents the Fermi level, and EV represents the valence band. In FIG. 3C, regions I and III correspond to regions overlapping with the storage gate electrodes 140a and 140b, respectively. Region II corresponds to the region overlapping with the control gate electrode 130.

[0057] 3C, in region II of the semiconductor substrate 110, which corresponds to a region directly below the control gate electrode 130, a sufficiently high energy barrier 20 is formed in the conduction band, preventing electrons from moving between regions I and III. In other words, the channel 10 formed in region I and the channel 10 formed in region III are separated from each other by region II. Therefore, as shown in FIG. 3A, even if a voltage is applied between the terminal electrodes 150a and 150b, no current flows between the terminal electrodes 150a and 150b because the channel 10, which serves as a current path, is separated.

[0058] On the other hand, as shown in FIG. 3B, when MOS-FET 100 is in the on state, a positive voltage (V ＡＧ >0) is supplied to the control gate electrode 130, and a positive gate voltage (V ＣＧ>0) is supplied to the control gate electrode 130. At this time, supplying a positive gate voltage to the control gate electrode 130 changes the state of the energy band in region II, lowering the energy barrier 20, as shown in FIG. 3D. As a result, electrons stored in regions I and III become able to move toward region II, and a continuous channel 10 is formed from region I to region III, as shown in FIG. 3A. In this way, by controlling the voltage supplied to the control gate electrode 130 to change the energy band of the semiconductor substrate 110 located directly below the control gate electrode 130, a current path electrically connecting the terminal electrode 150a and the terminal electrode 150b can be formed.

[0059] In this embodiment, an n-type MOS-FET 100 has been described as an example, but the operation is similar even when a p-type MOS-FET 100 is used. In the case of a p-type MOS-FET 100, a channel 10 is formed below the storage gate electrode 140 by holes attracted by a negative storage voltage. In this case, in a p-type MOS-FET in the off state, holes stored in the valence band remain in regions I and III due to a barrier that protrudes in the opposite direction to that shown in FIG. 3D. In a p-type MOS-FET in the on state, the barrier in region II is lowered by the supply of a negative gate voltage, and a channel composed of holes is formed from regions I to III.

[0060] As described above, the MOS-FET 100 of this embodiment can set the polarity according to the polarity of the supplied voltage by irradiating the semiconductor substrate 110 with light and supplying a voltage to the storage gate electrode 140 during overlapping periods. Specifically, by supplying a positive voltage to the storage gate electrode 140, the MOS-FET 100 can accumulate electrons directly below the storage gate electrode 140 via the gate insulating layer 120, thereby forming a channel 10 for the n-type MOS-FET 100. Furthermore, by supplying a negative voltage to the storage gate electrode 140, the MOS-FET 100 can accumulate holes directly below the storage gate electrode 140 via the gate insulating layer 120, thereby forming a channel 10 for the p-type MOS-FET 100. Thus, this embodiment can provide a field-effect transistor whose polarity can be changed subsequently (in other words, reversibly).

[0061] (Function of storage gate electrode) As described above, the storage gate electrode 140 has the function of attracting any carrier of the electron-hole pairs generated due to light irradiation on the semiconductor substrate 110 to directly below the storage gate electrode 140 (specifically, the interface between the semiconductor substrate 110 and the gate insulating layer 120), and retaining the attracted carrier even after the light irradiation is stopped.

[0062] In the course of the invention, the inventors conducted a verification experiment to verify the feasibility of the storage gate electrode function. Specifically, in a MOS structure consisting of a semiconductor substrate, an insulating layer, and a storage gate electrode, the inventors verified whether the storage gate electrode can retain carriers on the surface of the semiconductor substrate. The verification experiment is described below.

[0063] When carriers accumulate at the interface between the semiconductor and insulating layer in the MOS structure described above, the carrier concentration of the storage gate electrode changes due to electrostatic coupling. Therefore, by measuring the change in carrier concentration (change in conductivity) of the storage gate electrode, it is possible to verify whether carriers are accumulating at the interface between the semiconductor and insulating layer. However, metal materials generally have extremely high carrier concentrations, making them unsuitable for the purpose of this experiment, which is to measure minute changes in conductivity. Therefore, the inventors focused on graphene, which has a low carrier concentration, as a material for the storage gate electrode.

[0064] Graphene is a two-dimensional material with a thickness of one atomic layer, in which carbon atoms are bonded in a hexagonal pattern. Graphene is known for its linear and gapless band dispersion in electrical conduction. In a MOS structure in which semiconductors, insulating layers, and graphene are stacked, when carriers accumulate at the interface between the semiconductor and insulating layer, the carrier concentration in the graphene changes due to electrostatic bonding. By measuring this change in carrier concentration as a change in resistance using the Drude model, it is possible to verify whether carriers are accumulating at the interface between the semiconductor and insulating layer.

[0065] 4A is a schematic diagram of an experimental sample 800 used in an experiment to verify the function of the storage gate electrode. As shown in FIG. 4A, the experimental sample 800 includes a semiconductor substrate 160, an insulating layer 170, a storage gate electrode 180, a terminal electrode 190a, and a terminal electrode 190b. The experimental sample 800 has a MOS structure composed of the semiconductor substrate 160, the insulating layer 170, and the storage gate electrode 180. A variable power supply 230 is disposed between the semiconductor substrate 160 and the terminal electrode 190b, and a back gate voltage (V ＢＧ The back gate voltage is based on the potential of the terminal electrode 190b. That is, the back gate voltage when the semiconductor substrate 160 has a relatively high potential is a positive voltage, and the back gate voltage when the semiconductor substrate 160 has a relatively low potential is a negative voltage.

[0066] In this experiment, a p-type single-crystal silicon substrate doped with a low concentration of impurity (boron) was used as the semiconductor substrate 160. Therefore, carriers (holes) exist within the semiconductor substrate 160 at room temperature. Since this experiment measures changes in the resistance value of the storage gate electrode 180, it is convenient for carriers to exist in the semiconductor substrate 160 due to thermal excitation at room temperature. However, in experiments involving carrier generation by light irradiation, as described below, it is necessary to achieve a state in which no carriers exist within the semiconductor substrate 160. Therefore, the inventors prepared the semiconductor substrate 160 so that experiments could be performed in a low-temperature environment cooled with liquid helium. When the semiconductor substrate 160 is placed in a low-temperature environment, the carriers within the semiconductor substrate 160 are almost completely eliminated due to suppression of thermal excitation. In other words, the semiconductor substrate 160 can be considered a substantially intrinsic semiconductor substrate.

[0067] The insulating layer 170 is made of silicon dioxide (SiO ２ ). The storage gate electrode 180 was made of graphene, as described above. The storage gate electrode 180 made of graphene was obtained by transferring graphene formed on a transfer substrate by chemical vapor deposition (CVD) onto the insulating layer 170, and then patterning the transferred graphene by electron beam (EB) lithography. The terminal electrodes 190a and 190b were obtained by patterning a metal material by electron beam lithography. In this experiment, the resistance value of the storage gate electrode 180 was measured by a two-terminal method using the two terminal electrodes 190a and 190b.

[0068] Although not shown, in this experiment, the experimental sample 800 shown in Fig. 4A and an LED light source were placed inside a light-shielding shield to provide an environment in which carriers would not be generated in the semiconductor substrate 160 due to unintentional light irradiation. As the LED light source, an LED light source using GaAs (gallium arsenide) with a wavelength of 940 nm was placed.

[0069] FIG. 4B shows the resistance (R ２ｔ ) back gate voltage (V ＢＧ) is shown. FIG. 4C is an enlarged view of the back gate voltage range of −20 V to 20 V in FIG. 4B. FIG. 4B shows the measurement results at room temperature (RT). In FIG. 4C, the measurement results at room temperature (RT) are shown by a solid line, and the measurement results at a low temperature (4.2 K) are shown by a dotted line.

[0070] As shown in Figure 4B, when the back gate voltage was swept from -20 V to 40 V, a peak in the resistance value was observed around 27 V. The back gate voltage at which this peak was observed is considered to be the state where the Fermi level of graphene is located at the contact point between the valence band and the conductor, and is the charge neutrality point (V ＮＰ In this experiment, the change in the resistance value in the voltage range lower than the charge neutral point is measured as the change in the carrier concentration of the storage gate electrode 180.

[0071] 4C , according to the results of the low-temperature measurement (dotted line), the resistance value of the storage gate electrode 180 is constant regardless of the back gate voltage. This means that carriers are not accumulated at the interface between the semiconductor substrate 160 and the insulating layer 170. In other words, in a low-temperature environment, carriers inside the semiconductor substrate 160 disappear, and the semiconductor substrate 160 is in a state substantially equivalent to that of an undoped single-crystal silicon substrate.

[0072] In addition, in FIG. 4C, the results of the room temperature measurement (solid line) show that, with the back gate voltage at 0 V as the reference point, a decrease in resistance value was observed when a negative voltage of -10 V was applied, and an increase in resistance value was observed when a positive voltage of 10 V was applied. From the results of FIG. 4C, it can be seen that the back gate voltage (V ＢＧ ) can be used to verify the change in the resistance value (i.e., the change in the carrier concentration) of the storage gate electrode 180. In other words, it was confirmed that the carrier storage function of the storage gate electrode 180 can be verified using the experimental sample 800.

[0073] FIG. 4D shows the relationship between the capacitance (C) and the back gate voltage (V) in the experimental sample 800. ＢＧSpecifically, the capacitance was measured when the back gate voltage was swept from −10 V to 10 V. The measurement was carried out at room temperature.

[0074] The CV shown in solid line in FIG. 4D ＢＧ The curve can be divided into three regions representing different band bending states. Region I corresponds to a state in which the energy band of the semiconductor substrate 160 is bent toward the conductor side at the interface with the insulating layer 170. This state corresponds to a state in which holes are accumulated at the interface between the semiconductor substrate 160 and the insulating layer 170. Regions II and III correspond to a state in which the energy band of the semiconductor substrate 160 is bent toward the valence band side at the interface with the insulating layer 170. This state corresponds to a state in which electrons are accumulated at the interface between the semiconductor substrate 160 and the insulating layer 170.

[0075] In region II, a depletion layer is formed at the interface between the semiconductor substrate 160 and the insulating layer 170, which increases the apparent inter-electrode distance (the distance between the semiconductor substrate 160 and the storage gate electrode 180), and a decrease in capacitance is observed. ＢＧ = approximately 5 V) corresponds to the flat band voltage, and it is expected that the energy band of the semiconductor substrate 160 is flat.

[0076] 4B to 4D, the inventors considered that if a positive voltage of 10 V or a negative voltage of −10 V is supplied as the back gate voltage in experimental sample 800 shown in FIG. 4A, the carriers can be kept sufficiently trapped by band bending. In other words, by setting the back gate voltage as described above, it is possible to verify the presence or absence of carrier accumulation by the change in the resistance value of storage gate electrode 180.

[0077] FIG. 4E shows the resistance (R ２ｔ4E shows the change in resistance. In this experiment, as shown in FIG. 4E, a back gate voltage of −10 V or 10 V was supplied to the experimental sample 800, and the resistance value was measured. 10 seconds after the start of the measurement, the semiconductor substrate 160 was irradiated with light, and after 10 seconds of light irradiation, the light irradiation was stopped. In FIG. 4E, the solid line shows the resistance value when a back gate voltage of 10 V was supplied, and the dotted line shows the resistance value when a back gate voltage of −10 V was supplied. The measurement was performed in the low-temperature environment described above.

[0078] According to the measurement results shown in FIG. 4E , a change in resistance was observed at the start of light irradiation. Specifically, when a back gate voltage of 10 V was applied, the resistance increased, and when a back gate voltage of −10 V was applied, the resistance decreased. In light of the results shown in FIGS. 4C and 4D , the measurement results shown in FIG. 4E indicate that carriers generated by light irradiation were attracted by the storage gate electrode 180 to the interface between the semiconductor substrate 160 and the insulating layer 170, resulting in a change in the resistance of the storage gate electrode 180. That is, the results shown in FIG. 4E verify that (1) carriers are generated within the semiconductor substrate 160 by irradiating a substantially intrinsic (having a sufficiently low carrier concentration) semiconductor substrate 160 with light, and (2) electrons or holes are attracted to the interface between the semiconductor substrate 160 and the insulating layer 170 by a positive or negative voltage applied to the storage gate electrode 180.

[0079] Furthermore, as shown in Fig. 4E, no change in the resistance value of storage gate electrode 180 was observed even when light irradiation was stopped. This result means that even if carriers inside semiconductor substrate 160 are annihilated when light irradiation is stopped, carriers are retained at the interface between semiconductor substrate 160 and insulating layer 170 due to the voltage supplied to storage gate electrode 180. In other words, the result of Fig. 4E verified that storage gate electrode 180 has the function of retaining carriers even after light irradiation is stopped.

[0080] (Variation 1 of First Embodiment) Fig. 5A is a perspective view showing a schematic structure of a MOS-FET 100a according to one embodiment of the present invention. Fig. 5B is a cross-sectional view showing a schematic structure of a MOS-FET 100a according to one embodiment of the present invention. The MOS-FET 100a shown in Variation 1 has a different terminal electrode structure from the MOS-FET 100 described in the first embodiment. In the following description using the drawings, parts common to the first embodiment are denoted by the same reference numerals as in the first embodiment, and detailed description thereof may be omitted.

[0081] 5A and 5B, in MOS-FET 100a shown in Modification 1, terminal electrodes 152a and 152b have curved surfaces CS. When MOS-FET 100a is covered with a passivation layer (not shown) made of an insulating layer to protect the entire device from external moisture and the like, providing terminal electrodes 152a and 152b with curved surfaces CS can improve the coverage rate of the passivation layer.

[0082] The method for forming the curved surfaces of the terminal electrodes 152a and 152b is not particularly limited, but for example, the curved surfaces CS may be formed by forming the terminal electrodes 152a and 152b by anisotropic dry etching, and then performing isotropic wet etching using the same photoresist.

[0083] 6A and 6B are cross-sectional views showing a schematic structure of a MOS-FET 100b according to one embodiment of the present invention. Specifically, FIG. 6A shows the MOS-FET 100b in an off state, and FIG. 6B shows the MOS-FET 100b in an on state. The MOS-FET 100b shown in this modification 2 differs from the MOS-FET 100 described in the first embodiment in the structure of the gate insulating layer. In the following description using the drawings, parts common to the first embodiment are denoted by the same reference numerals as in the first embodiment, and detailed description thereof may be omitted.

[0084] 6A and 6B, in the MOS-FET 100b shown in Modification 2, the gate insulating layer 120a is processed to have a convex shape. Specifically, the gate insulating layer 120a has a first portion that overlaps with the control gate electrode 130 and is thicker than a second portion that overlaps with the storage gate electrode 140. The gate insulating layer 120a can be formed by forming an insulating layer using a CVD method or the like, and then thinning only the portion that overlaps with the storage gate electrode 140 using a half-etching technique in advance.

[0085] 6A and 6B, the process of forming the channel 10 is the same as the process described with reference to FIGS. 3A and 3B. That is, as shown in FIG. 6A, when the MOS-FET 100b is in the off state, the channel 10 is formed below the storage gate electrodes 140a and 140b by the attraction of electrons or holes. When a gate voltage is applied to the control gate electrode 130, the energy barrier of the semiconductor substrate 110 below the control gate electrode 130 is lowered, as shown in FIG. 6B, and the channel 10 continues from the terminal electrode 150a to the terminal electrode 150b.

[0086] According to the present modification 2, the gate insulating layer 120a directly below the control gate electrode 130 is thickened, thereby increasing the breakdown voltage characteristics against the gate voltage and improving the reliability of the MOS-FET 100b. Furthermore, because the gate insulating layer 120a directly below the storage gate electrode 140 is relatively thin, a sufficient number of carriers can be stored even if the voltage supplied to the storage gate electrode 140 is low, thereby reducing the power consumption of the MOS-FET 100b.

[0087] 7A and 7B are cross-sectional views showing a schematic structure of a MOS-FET 100c according to one embodiment of the present invention. Specifically, FIG. 7A shows the MOS-FET 100c in an off state, and FIG. 7B shows the MOS-FET 100c in an on state. The MOS-FET 100c shown in this modification 3 differs from the MOS-FET 100 described in the first embodiment in the structure of the semiconductor substrate. In the following description using the drawings, parts common to the first embodiment are denoted by the same reference numerals as in the first embodiment, and detailed description thereof may be omitted.

[0088] As shown in FIGS. 7A and 7B , the MOS-FET 100c shown in Modification 3 has a recess 115 formed in a portion of the semiconductor substrate 110a. Specifically, the recess 115 is formed in a portion of the semiconductor substrate 110a that overlaps with the control gate electrode 130. The recess 115 may be formed by providing a photoresist with an opening where the recess 115 is to be formed, and then half-etching a portion of the semiconductor substrate 110a, before forming the gate insulating layer 120. There is no particular limitation on the depth of the recess 115, but in Modification 3, the inner wall of the recess 115 forms the region where the channel is to be formed. That is, the length along the inner wall of the recess 115 in a cross-sectional view (the sum of twice the length of the sidewall of the recess 115 and the length of the bottom) corresponds to the effective channel length.

[0089] 7A and 7B, the process of forming the channel 10 is the same as the process described with reference to FIGS. 3A and 3B. That is, as shown in FIG. 7A, when the MOS-FET 100c is in the off state, the channel 10 is formed below the storage gate electrodes 140a and 140b by the attraction of electrons or holes. Then, when a gate voltage is supplied to the control gate electrode 130, the energy barrier of the semiconductor substrate 110 below the control gate electrode 130 is lowered, and a channel is formed along the inner wall of the recess 115, as shown in FIG. 7B. As a result, the channel 10 continues from the terminal electrode 150a to the terminal electrode 150b.

[0090] According to the third modification, by forming a recess 115 in the semiconductor substrate 110a directly below the control gate electrode 130, a channel can be formed in the depth direction of the semiconductor substrate 110a. That is, the width of the control gate electrode 130 can be narrowed without changing the effective channel length, thereby realizing a miniaturized MOS-FET 100c (and a high density of an integrated circuit using the MOS-FET 100c). Furthermore, since the effective channel length can be increased without changing the size of the MOS-FET 100c, the off-current of the MOS-FET 100c can be reduced.

[0091] 8A and 8B are cross-sectional views showing a schematic structure of a MOS-FET 100d according to one embodiment of the present invention. Specifically, FIG. 8A shows the MOS-FET 100d in an off state, and FIG. 8B shows the MOS-FET 100d in an on state. The MOS-FET 100d shown in this fourth modification has a different semiconductor substrate structure from the MOS-FET 100 described in the first embodiment. In the following description using the drawings, parts common to the first embodiment are denoted by the same reference numerals as in the first embodiment, and detailed description thereof may be omitted.

[0092] As shown in FIGS. 8A and 8B , the MOS-FET 100d shown in Modification 4 has a protrusion 117 formed in a portion of the semiconductor substrate 110b. Specifically, the protrusion 117 is formed in a portion of the semiconductor substrate 110b that overlaps with the control gate electrode 130. The protrusion 117 may be formed by applying photoresist to the location where the protrusion 117 is to be formed and then performing half-etching on a portion of the semiconductor substrate 110b (specifically, the portion that overlaps with the storage gate electrode 140) before forming the gate insulating layer 120. There is no particular limitation on the height of the protrusion 117, but in Modification 4, the outer wall of the protrusion 117 forms a region where a channel is to be formed. That is, the length along the outer wall of the protrusion 117 in a cross-sectional view (the sum of twice the length of the sidewall of the protrusion 117 and the length of the top) corresponds to the effective channel length.

[0093] 8A and 8B, the process of forming the channel 10 is the same as the process described with reference to FIGS. 3A and 3B. That is, as shown in FIG. 8A, when the MOS-FET 100d is in the off state, the channel 10 is formed by attraction of electrons or holes below the storage gate electrodes 140a and 140b and on the sidewall of the convex portion 117. Then, when a gate voltage is supplied to the control gate electrode 130, the energy barrier of the semiconductor substrate 110b below the control gate electrode 130 is lowered, and a channel is formed at the top of the convex portion 117, as shown in FIG. 8B. As a result, the channel 10 continues from the terminal electrode 150a to the terminal electrode 150b.

[0094] According to the fourth modification, by forming a convex portion 117 in the semiconductor substrate 110b directly below the control gate electrode 130, a channel can be formed in a direction perpendicular to the semiconductor substrate 110b. That is, the width of the control gate electrode 130 can be narrowed without changing the effective channel length, thereby realizing a miniaturized MOS-FET 100d (and a high density of an integrated circuit using the MOS-FET 100d). Furthermore, since the effective channel length can be increased without changing the size of the MOS-FET 100d, the off-current of the MOS-FET 100d can be reduced.

[0095] Second Embodiment In the first embodiment, the semiconductor in which the channel is formed is an intrinsic or substantially intrinsic semiconductor (i.e., a semiconductor having a resistivity of 0.01 kΩ·cm or more or an impurity concentration of 1×10 in any temperature range). １６ / cm ３ An example has been described in which carriers are induced in a semiconductor by light irradiation using a semiconductor (hereinafter referred to as a semiconductor). However, embodiments of the present invention are not limited to this example. For example, in order to induce carriers in an intrinsic or substantially intrinsic semiconductor, it is sufficient to supply some energy sufficient to generate electron-hole pairs in the semiconductor. Such energy may be not only light energy but also thermal energy.

[0096] When thermal energy is used to induce carriers, for example, the MOS-FET 100 described in the first embodiment may be operated at room temperature, and carriers may be generated by applying heat to the semiconductor substrate 110 instead of light when changing polarity. When applying heat to the semiconductor substrate 110, it is preferable that the rate of temperature rise or fall be as fast as possible. Furthermore, in order to minimize degradation of the device characteristics, a means capable of selectively heating the semiconductor substrate 110 is desirable. For these reasons, it is preferable to use a thermoelectric element such as a Peltier element that utilizes the Peltier effect as the heating means. Such a heating means may be disposed in the MOS-FET 100 shown in FIG. 1A so that the heat-generating surface is in contact with or close to the back side of the semiconductor substrate 110 (the side on which the device structure is not formed).

[0097] Third Embodiment In this embodiment, a programmable integrated circuit in which a logic gate is configured using the MOS-FETs described in the first embodiment (including the modifications) will be described.

[0098] 9 is a circuit diagram showing an example of a logic gate using MOS-FETs. Specifically, FIG. 9 shows an example of a "NAND gate" and a "NOR gate."

[0099] 9, the NAND gate is configured by combining two n-type MOS-FETs 31n and 32n and two p-type MOS-FETs 31p and 32p. The n-type MOS-FET 31n and the p-type MOS-FET 31p share a gate and are connected in series to configure a CMOS circuit 35. An input A is input to the gates of the n-type MOS-FET 31n and the p-type MOS-FET 31p, respectively. An input B is input to the gates of the n-type MOS-FET 32n and the p-type MOS-FET 32p, respectively. The output of the CMOS circuit 35 is connected to the drain of the p-type MOS-FET 32p and is output as output Z of the NAND gate.

[0100] A NAND gate is a logic gate for negative logical product. Specifically, output Z is low only when inputs A and B are both high, and output Z is high when either input A or B is low.

[0101] 9, the NOR gate is configured by combining two n-type MOS-FETs 41n and 42n and two p-type MOS-FETs 41p and 42p. The n-type MOS-FET 41n and the p-type MOS-FET 41p share a gate and are connected in series to configure a CMOS circuit 45. An input A is input to the gates of the p-type MOS-FET 42p and the n-type MOS-FET 42n, respectively. An input B is input to the gates of the n-type MOS-FET 41n and the p-type MOS-FET 41p, respectively. The output of the CMOS circuit 45 is connected to the drain of the n-type MOS-FET 42n and is output as output Z of the NOR gate.

[0102] A NOR gate is a NOR logic gate. Specifically, the output Z is high only when both inputs A and B are low, and the output Z is low when either input A or B is high.

[0103] Fig. 10 is a circuit diagram showing an example of a logic gate 300 used in a programmable integrated circuit according to one embodiment of the present invention. The logic gate 300 shown in Fig. 10 has the carrier-storage MOS-FETs 61 and 62 described in the first or second embodiment, in addition to an n-type MOS-FET 51n and a p-type MOS-FET 51p. In the circuit diagram of the logic gate shown in Fig. 10, the circuit symbols representing the carrier-storage MOS-FETs 61 and 62 mean that the carrier-storage MOS-FETs 61 and 62 can be either n-type or p-type.

[0104] 10, the n-type MOS-FET 51n, the carrier storage MOS-FET 61, and the p-type MOS-FET 51p are connected in series with each other. The carrier storage MOS-FET 61 is connected between the n-type MOS-FET 51n and the p-type MOS-FET 51p. The source of the n-type MOS-FET 51n is connected to the power supply line on the low potential side. The source of the p-type MOS-FET 51p is connected to the power supply line on the high potential side.

[0105] Input A is input to the gate of p-type MOS-FET 51p, switch 71, and switch 72. Input B is input to the gate of n-type MOS-FET 51n, switch 71, and switch 72. Switch 71 selects either input A or input B and inputs it to the gate of carrier storage MOS-FET 61. Switch 72 selects either input A or input B and inputs it to the gate of carrier storage MOS-FET 62.

[0106] A node 81 located between the n-type MOS-FET 51n and the carrier storage MOS-FET 61 is connected to the output Z １ The node 82 located between the p-type MOS-FET 51p and the carrier storage MOS-FET 61 outputs the output Z ２ is output as

[0107] The carrier storage MOS-FET 62 is connected to a power supply line or node 81 on the high potential side via a switch 73. The carrier storage MOS-FET 62 is also connected to a power supply line or node 82 on the low potential side via a switch 74.

[0108] The logic gate 300 having the above configuration can realize either the NAND gate or the NOR gate shown in Fig. 9 by setting the carrier storage MOS-FETs 61 and 62 to n-type or p-type MOS-FETs and appropriately switching the wiring using the switches 71 to 74. In other words, the logic gate 300 of this embodiment can function as a programmable logic gate.

[0109] 11A is a circuit diagram showing an example in which logic gate 300 used in a programmable integrated circuit according to an embodiment of the present invention is switched to a NAND gate. Note that the portion shown by the dotted line indicates the portion of the wiring and contacts that make up logic gate 300 that is not used in the NAND gate.

[0110] 11A, when the logic gate 300 is set as a NAND gate, the carrier storage MOS-FETs 61 and 62 are set as n-type and p-type MOS-FETs, respectively. As a result, a CMOS circuit is formed by the p-type MOS-FET 51p and the carrier storage MOS-FET 61. Furthermore, the switches 71 and 72 select inputs A and B, respectively. The switch 73 selects the high-potential power supply line. The switch 74 selects the wiring connected to node 82.

[0111] With the above configuration, the logic gate 300 can perform the same arithmetic processing as the NAND gate shown in FIG.

[0112] 11B is a circuit diagram showing an example in which logic gate 300 used in a programmable integrated circuit according to an embodiment of the present invention is switched to a NOR gate. Note that the portion shown by the dotted line indicates the wiring and contacts that make up logic gate 300 that are not used in the NOR gate.

[0113] 11B, when logic gate 300 is set as a NOR gate, carrier-storage MOS-FETs 61 and 62 are set as p-type and n-type MOS-FETs, respectively. Switches 71 and 72 select input B and input A, respectively. Switch 73 selects the wiring connected to node 81. Switch 74 selects the power supply line on the low potential side. With the above configuration, logic gate 300 can perform the same arithmetic processing as the NOR gate shown in FIG. 9.

[0114] 12 is a flowchart showing the procedure for changing the logic gate 300 to a NAND gate or a NOR gate. An example of switching a NAND gate to a NOR gate will be described below with reference to the flowchart shown in FIG.

[0115] 10, the contacts of the switches 71 to 74 are switched to change the connected wiring (step S101). Specifically, the switch 71 is switched to connect the gate of the carrier-storage MOS-FET 61 to input B. The switch 72 is switched to connect the gate of the carrier-storage MOS-FET 62 to input A. The switch 73 is switched to connect the drain of the carrier-storage MOS-FET 62 to node 81. The switch 74 is switched to connect the source of the carrier-storage MOS-FET 62 to the low-potential power supply line.

[0116] Next, the voltage supplied to the storage gate electrode 140 is inverted (step S102). Specifically, the storage voltage supplied to the storage gate electrode 140 of the carrier-storage MOS-FET 61 is inverted from positive to negative, and the storage voltage supplied to the storage gate electrode 140 of the carrier-storage MOS-FET 62 is inverted from negative to positive. At this time, the carrier-storage MOS-FETs 61 and 62 constituting the NAND gate have a voltage of the same polarity as the accumulated carriers supplied to their storage gate electrodes 140, thereby releasing the accumulation of carriers.

[0117] Next, the semiconductor substrate 110 is irradiated with light to generate carriers (electrons and holes) inside the semiconductor substrate 110 (step S103). However, in step S103, instead of irradiating with light, energy can also be supplied to the semiconductor substrate 110 by a method such as heat treatment.

[0118] In step S103, when the semiconductor substrate 110 is irradiated with light, the storage gate electrode 140 is already supplied with a positive or negative voltage, and thus the generated carriers are attracted to the area below the storage gate electrode 140 to which a voltage of the opposite polarity has been supplied. Specifically, holes are accumulated below the storage gate electrode 140 in the carrier-storage MOS-FET 61, and electrons are accumulated below the storage gate electrode 140 in the carrier-storage MOS-FET 62. That is, at this point, the carrier-storage MOS-FET 61 is set as a p-type MOS-FET, and the carrier-storage MOS-FET 62 is set as an n-type MOS-FET.

[0119] Finally, the light irradiation to the semiconductor substrate 110 is stopped (step S104). By stopping the light irradiation, most of the carriers generated inside the semiconductor substrate 110 disappear, but the carriers accumulated below the storage gate electrode 140 are retained.

[0120] The above procedure completes the process of changing the logic gate 300 from a NAND gate to a NOR gate. The process of changing the logic gate 300 from a NOR gate to a NAND gate can also be carried out according to the flowchart shown in Figure 12. At this time, the switching destinations of the switches 71 to 74 and the polarities of the carrier storage MOS-FETs 61 and 62 are set to the opposite.

[0121] (Variation 1 of the Third Embodiment) The switches 71 to 74 included in the logic gate 300 shown in Fig. 10 can be well-known switching circuits such as multiplexers. The multiplexer is a circuit in which CMOS transmission gates are connected in parallel, and is controlled by a selection control signal S. The selection control signal S is a signal input to select an output from the multiplexer, and signifies a predetermined voltage.

[0122] FIG. 13A is a circuit diagram showing an example of a logic gate 300a used in a programmable integrated circuit according to one embodiment of the present invention. The basic configuration of FIG. 13A is the same as that of the logic gate 300 shown in FIG. 10. However, in the logic gate 300a, the switches 71 to 74 are replaced with multiplexers 71m to 74m. Furthermore, in the logic gate 300a, selection control signals S and S bar (the inverted signal of the selection control signal S) are input to the storage gate electrodes 140 of the carrier storage MOSFETs 61 and 62, respectively. By inputting the selection control signals S and S bar to the storage gate electrodes 140, steps S101 and S102 shown in FIG. 12 can be executed simultaneously. Note that in FIG. 13A, the voltage on the high potential side is a positive voltage (V ＤＤ ) and the voltage on the low potential side is the ground voltage.

[0123] 13A is used as a NAND gate, the multiplexer 71m is controlled to output input A, and the carrier-storage MOS-FET 61 is set to operate as an n-type MOS-FET. In this case, when the selection control signal S input to the multiplexer 71m and the storage gate electrode 140 of the carrier-storage MOS-FET 61 is set to High (positive voltage), the multiplexer 71m selects input A, and the carrier-storage MOS-FET 61 accumulates electrons below the storage gate electrode 140 to form an n-type MOS-FET.

[0124] FIG. 13B is a diagram showing the configurations of the multiplexers 71m to 74m and the carrier-storage MOS-FET 61 shown in FIG. 13A. The carrier-storage MOS-FET 61 is assumed to have the same structure as the MOS-FET 100 shown in FIG. 1B. The multiplexers 71m to 74m shown in FIGS. 13A and 13B can be formed using a known CMOS process. However, in this embodiment, an intrinsic or substantially intrinsic semiconductor substrate is used as the semiconductor substrate 110 used as the base substrate. Therefore, it is not appropriate to use the semiconductor substrate 110 as the channel of a conventional MOS-FET. It is desirable to add n-type or p-type impurities to the regions where the multiplexers 71m to 74m are to be formed in advance by ion implantation or the like so that the MOS-FETs can be formed using a known CMOS process.

[0125] 13B, each of the multiplexers 71m to 74m has a configuration in which a CMOS transmission gate 75 consisting of an n-type MOS-FET 75n and a p-type MOS-FET 75p is connected in parallel with a CMOS transmission gate 76 consisting of an n-type MOS-FET 76n and a p-type MOS-FET 76p. If the input of the CMOS transmission gate 75 is A and the input of the CMOS transmission gate 76 is B, either the input A or B is selected according to the selection control signal S, and is output as the output Y.

[0126] In the carrier storage MOS-FET 61, a selection control signal S is input to the storage gate electrodes 140a and 140b, and an inverted version of the selection control signal S, S bar, is input to the semiconductor substrate 110. In other words, a positive storage voltage is supplied to the storage gate electrodes 140a and 140b of the carrier storage MOS-FET 61 shown in FIG. 13B. Note that while only the carrier storage MOS-FET 61 is shown in FIG. 13B, the configuration of the carrier storage MOS-FET 62 is basically the same. However, in the carrier storage MOS-FET 62, an inverted version of the selection control signal S, S bar, is input to the storage gate electrodes 140a and 140b, and the selection control signal S is input to the semiconductor substrate 110.

[0127] 13A and 13B functions as a NAND gate after light irradiation when, for example, High (positive voltage) is input to the selection control signal S, and functions as a NOR gate after light irradiation when Low (negative voltage) is input to the selection control signal S. In this way, the logic gate 300a can realize logic gates with different physical configurations and functions by the simple method of controlling the selection control signal S input to each switch (multiplexers 71m to 74m) and the storage gate electrodes 140 of the carrier storage MOS-FETs 61 and 62.

[0128] (Variation 2 of the Third Embodiment) The multiplexer shown in FIG. 13B can also be configured using a carrier storage element that forms a channel with carriers attracted below the storage gate electrode, similar to a carrier storage MOS-FET.

[0129] 14 is a diagram showing an example of a multiplexer 400 using carrier storage elements according to one embodiment of the present invention. The basic circuit configuration is similar to that of the multiplexer shown in FIG. 13B. The multiplexer 400 shown in FIG. 14 has a configuration in which a transmission gate 410 composed of carrier storage elements 411 and 412 and a transmission gate 420 composed of carrier storage elements 421 and 422 are connected in parallel. If the input to the transmission gate 410 is A and the input to the transmission gate 420 is B, either the input A or B is selected in accordance with a selection control signal S, and output as an output Y.

[0130] The carrier storage type elements 411, 412, 421, and 422 shown in Fig. 14 have the same structure. As shown in Fig. 14, the carrier storage type element 411 includes a semiconductor substrate 91, an insulating layer 92, a storage gate electrode 93, and terminal electrodes 94a and 94b. The semiconductor substrate 91, the insulating layer 92, and the storage gate electrode 93 form a MOS structure. Note that although the specific structure has been explained using the carrier storage type element 411 as an example here, the structures of the other carrier storage type elements 412, 421, and 422 are similar.

[0131] In the carrier accumulation element 411, the semiconductor substrate 91 is grounded, and a selection control signal S is input to the storage gate electrode 93. Therefore, when the semiconductor substrate 91 is irradiated with light and carriers (electrons and holes) are generated inside the semiconductor substrate 91, and a high (positive voltage) selection control signal S is input to the storage gate electrode 93, electrons are accumulated at the interface between the semiconductor substrate 91 and the insulating layer 92. In other words, a current path (channel) made up of electrons is formed between the terminal electrodes 94a and 94b. Therefore, the carrier accumulation element 411 outputs the input A as the output Y.

[0132] The carrier accumulation element 412 applies a positive voltage (V ＤＤ ) is supplied to the semiconductor substrate 91, and an inverted signal S bar of the selection control signal S is input to the storage gate electrode 93. Therefore, when carriers are generated inside the semiconductor substrate 91 and a low (negative voltage) signal is input to the storage gate electrode 93 as an inverted signal of the selection control signal S, holes are accumulated at the interface between the semiconductor substrate 91 and the insulating layer 92. In other words, a current path made up of holes is formed between the terminal electrodes 94a and 94b. Therefore, the carrier accumulation element 412 outputs the input A as the output Y.

[0133] As described above, when a high (positive voltage) is input as the selection control signal S, the transmission gate 410 outputs the input A as the output Y.

[0134] On the other hand, in the carrier accumulation element 421, a Low signal is input to the storage gate electrode 93 as an inverted signal of the selection control signal S. However, because the semiconductor substrate 91 is grounded, carriers are not accumulated at the interface between the semiconductor substrate 91 and the insulating layer 92. In other words, no current path is formed between the terminal electrodes 94a and 94b, and the input B is not output. It is assumed here that a voltage equal to the ground voltage or a voltage with a very small difference from the ground voltage is supplied as the inverted signal (Low) of the selection control signal S.

[0135] In addition, in the carrier storage element 422, a high level is input as a selection control signal S to the storage gate electrode 93. However, when a positive voltage (V ＤＤ) is supplied, carriers are not accumulated at the interface between the semiconductor substrate 91 and the insulating layer 92. In other words, no current path is formed between the terminal electrodes 94a and 94b, and the input B is not output. ＤＤ ) is supplied with a voltage that is the same potential as the selection control signal S(High) or has a very small difference from the selection control signal S.

[0136] As described above, when High (positive voltage) is input as the selection control signal S, the input B is not output from the transmission gate 420 .

[0137] The above explanation is an example in which High is input as the selection control signal S, but if Low is input as the selection control signal S, the transmission gate 410 will not output the input A, and the transmission gate 420 will output the input B as the output Y.

[0138] 14 uses carrier storage elements 411, 412, 421, and 422 as elements that form current paths. The multiplexer 400 functions as a selection circuit that outputs either input A or input B according to the combination of the selection control signal S or S input to the storage gate electrodes 140 of the carrier storage elements 411, 412, 421, and 422 and the voltage supplied to the semiconductor substrate 91.

[0139] Fourth Embodiment In this embodiment, an electronic device including a programmable integrated circuit including the carrier accumulation type MOS-FET described in the first or second embodiment will be described.

[0140] FIG. 15A is a schematic diagram showing the overall configuration of an electronic device 900 according to one embodiment of the present invention. Specifically, FIG. 15A shows an example using a programmable integrated circuit 925 including a carrier-storage MOS-FET that generates carriers inside a semiconductor when irradiated with light. As shown in FIG. 15A, the electronic device 900 includes a housing 910, a printed circuit board 920, and a light source 930. Although not shown, the electronic device 900 may have an internal power supply for driving the printed circuit board 920 or the light source 930, or may have a transformer circuit or the like that transforms an external power supply.

[0141] The housing 910 is a protective member for protecting the programmable integrated circuit 925 included in the printed circuit board 920 from external moisture, dust, and the like. The housing 910 also has a light-shielding property. In this embodiment, since the programmable integrated circuit 925 includes a carrier-storage MOS-FET (not shown), the housing 910 is configured so that light does not hit the carrier-storage MOS-FET except when changing the polarity of the carrier-storage MOS-FET.

[0142] The printed circuit board 920 is supported inside the housing 910, and electronic components 922 and an integrated circuit 923 are mounted on the printed circuit board 921. In this embodiment, the logic gate 300 and logic gate 300a described in the third embodiment are used as the programmable integrated circuit 925 included in the printed circuit board 920. The printed circuit board 921 supporting the printed circuit board 920 has an opening 921a formed therein so as to expose the back side (i.e., the semiconductor substrate side) of the programmable integrated circuit 925. The light source 930 is a member for irradiating light onto a plurality of carrier accumulation MOS-FETs (e.g., the MOS-FETs 100 shown in FIGS. 1A and 1B) included in the programmable integrated circuit 925. In this embodiment, an LED light source that emits light in the visible light range is used as the light source 930. The light source 930 faces the programmable integrated circuit 925 via the opening 921a in the printed circuit board 921.

[0143] 15A, light emitted from the light source 930 is irradiated through the opening 921a onto the programmable integrated circuit 925. In practice, the light emitted from the light source 930 is configured to be irradiated onto the semiconductor substrate (semiconductor substrate 110 shown in FIGS. 1A and 1B) included in the programmable integrated circuit 925.

[0144] 15A has a light source 930 disposed as a light emitting unit inside a light-shielding housing 910. Therefore, when changing the function of a logic gate included in a programmable integrated circuit 925, a polarity change process for a carrier-storage MOS-FET can be performed simply by irradiating light from the light source 930. Note that the integrated circuit 923 may include an arithmetic circuit or memory that processes information required to set the logic gate of the programmable integrated circuit 925 (for example, information specifying the selection control signal S depending on the type of logic gate).

[0145] Fig. 15B is a schematic diagram showing the overall configuration of an electronic device 900a according to one embodiment of the present invention. Fig. 15B differs from the electronic device 900 shown in Fig. 15A in that it does not include a light source 930 inside a housing 910, but instead takes in light from the outside. In Fig. 15B, parts having the same functions as those in Fig. 15A are given the same reference numerals, and their description may be omitted.

[0146] 15B , a housing 910a of an electronic device 900a has an opening 911 for allowing light to enter from outside the housing. Furthermore, in the example shown in Fig. 15B , a sliding lid 912 is provided for opening and closing the opening 911. However, the example is not limited to this, and the lid 912 may have a structure that allows it to be opened and closed by other methods, or may be omitted.

[0147] 15B is configured such that during normal operation, opening 911 is closed by lid 912 to prevent light from entering from the outside. When changing the function of a logic gate included in programmable integrated circuit 925, lid 912 is opened to irradiate light from an external light source (not shown) or to let in sunlight, thereby changing the polarity of the carrier-accumulation MOS-FET.

[0148] Fig. 16 is a schematic diagram showing the overall configuration of an electronic device 900b according to one embodiment of the present invention. Fig. 16 differs from the electronic device 900 shown in Fig. 15A in that the change process of the logic gate in the programmable integrated circuit 925 is performed by heating (supply of thermal energy) rather than by light irradiation. In Fig. 16, parts having the same functions as those in Fig. 15A are given the same reference numerals, and their description may be omitted.

[0149] 16 , in an electronic device 900b, a metal member 921b is filled inside an opening 921a of a printed circuit board 921. The metal member 921b is made of a material with high thermal conductivity. For example, the metal member 921b is made of aluminum or copper. The metal member 921b serves to efficiently transfer heat emitted from a thermoelectric element 926 to a programmable integrated circuit 925.

[0150] The thermoelectric element 926 is a heat supply unit configured, for example, by a Peltier element utilizing the Peltier effect. In the example shown in FIG. 16 , as described in the second embodiment, carriers are generated inside the semiconductor substrate by supplying thermal energy to the semiconductor substrate of a carrier storage MOS-FET. The thermoelectric element 926 supplies thermal energy to the programmable integrated circuit 925 (specifically, the semiconductor substrate of the carrier storage MOS-FET included in the programmable integrated circuit 925) via the metal member 921b. Note that, although the example shown in FIG. 16 illustrates an example in which heat is supplied via the metal member 921b, the present invention is not limited to this example. The heat supply method is not limited as long as sufficient thermal energy can be supplied to the programmable integrated circuit 925.

[0151] Based on the above-described embodiments (including modifications of the embodiments below), those skilled in the art may add or remove components or modify designs, or add or omit steps or modify conditions, as appropriate, and these modifications are within the scope of the present invention as long as they incorporate the gist of the present invention. Furthermore, the above-described embodiments may be combined as appropriate as long as they are not mutually inconsistent.

[0152] Furthermore, even if there are other effects and advantages different from those brought about by the aspects of the above-mentioned embodiments, if they are clear from the description in this specification or can be easily predicted by a person skilled in the art, they are naturally understood to be brought about by the present invention.

[0153] 10...channel, 20...energy barrier, 31n, 32n...n-type MOS-FET, 31p, 32p...p-type MOS-FET, 35...CMOS circuit, 41n, 42n...n-type MOS-FET, 41p, 42p...p-type MOS-FET, 51n...n-type MOS-FET, 51p...p-type MOS-FET, 61, 62...carrier storage type MOS-FET, 71 to 74...switch, 71m to 74m...multiplexer, 75, 76...transistor transmission gate, 75n, 76n... n-type MOS-FET, 75p, 76p... p-type MOS-FET, 81, 82... node, 91... semiconductor substrate, 92... insulating layer, 93... storage gate electrode, 94a, 94b... terminal electrode, 100, 100a to 100d... MOS-FET, 110, 110a, 110b... semiconductor substrate, 111... first surface, 112... second surface, 115... recess, 117... protrusion, 120, 120a... gate insulating layer, 130...control gate electrode, 140, 140a, 140b...storage gate electrode, 150, 150a, 150b...terminal electrode, 152a, 152b...terminal electrode, 160...semiconductor substrate, 170...insulating layer, 180...storage gate electrode, 190, 190a, 190b...terminal electrode, 210, 220...power supply line, 215, 225, 230...variable power supply, 300, 300a...logic gate, 400...multiplexer, 410, 420...transistor Transmission gate, 411, 412, 421, 422...Carrier accumulation type element, 800...Experimental sample, 900, 900a, 900b...Electronic device, 910, 910a...Housing, 911...Opening, 912...Cover, 920...Printed circuit board, 921...Printed board, 921a...Opening, 921b...Metal member, 922...Electronic component, 923...Integrated circuit, 925...Programmable integrated circuit, 926...Thermoelectric element, 930...Light source

Claims

1. At any given temperature, the resistivity is 0.01 kΩ·cm or higher, or the impurity concentration is 1 × 10⁻⁶ １６ / cm ３ A semiconductor substrate composed of the following single-crystal semiconductors, A gate insulating layer in contact with the semiconductor substrate, A control gate electrode in contact with the gate insulating layer, One or more storage gate electrodes are arranged in contact with the gate insulating layer and alongside the control gate electrode, A terminal electrode in contact with the semiconductor substrate, Equipped with, A field-effect transistor in which the one or more storage gate electrodes are switchably connected to a first power supply line that supplies a positive voltage and a second power supply line that supplies a negative voltage.

2. At any given temperature, the resistivity is 0.01 kΩ·cm or higher, or the impurity concentration is 1 × 10⁻⁶ １６ / cm ３ A semiconductor substrate composed of the following single-crystal semiconductors, A gate insulating layer in contact with the semiconductor substrate, A control gate electrode in contact with the gate insulating layer, One or more storage gate electrodes are arranged in contact with the gate insulating layer and alongside the control gate electrode, A terminal electrode in contact with the semiconductor substrate, Equipped with, When a positive voltage is applied to the one or more storage gate electrodes, it operates as an N-type transistor. A transistor that operates as a P-type transistor when a negative voltage is applied to one or more of the storage gate electrodes.

3. The field-effect transistor according to claim 1 or 2, wherein, in a plan view, the plurality of storage gate electrodes are arranged with the control gate electrode in between.

4. The gate insulating layer is in contact with the first surface of the semiconductor substrate, The field-effect transistor according to claim 1 or 2, wherein the terminal electrode is continuous with the first surface of the semiconductor substrate and in contact with a second surface having a different normal direction from the first surface.

5. The field-effect transistor according to claim 2, wherein the one or more storage gate electrodes are switchably connected to a first power supply line that supplies a positive voltage and a second power supply line that supplies a negative voltage.

6. A programmable integrated circuit comprising a field-effect transistor according to claim 1 or 2.

7. A programmable integrated circuit including a field-effect transistor according to claim 1 or 2, A light-shielding housing surrounding the aforementioned programmable integrated circuit, Electronic devices, including those mentioned above.

8. A programmable integrated circuit including a field-effect transistor, A light-shielding housing surrounding the aforementioned programmable integrated circuit, Includes, The aforementioned field-effect transistor is A semiconductor substrate composed of a single-crystal semiconductor with a resistivity of 0.01 kΩ·cm or more or an impurity concentration of 1 × 10¹⁶ / cm³ or less at any temperature, A gate insulating layer in contact with the semiconductor substrate, A control gate electrode in contact with the gate insulating layer, One or more storage gate electrodes are arranged in contact with the gate insulating layer and alongside the control gate electrode, A terminal electrode in contact with the semiconductor substrate, Equipped with, An electronic device having a light irradiation unit arranged inside the housing that can irradiate light onto the semiconductor substrate.

9. A programmable integrated circuit including a field-effect transistor, A light-shielding housing surrounding the aforementioned programmable integrated circuit, Includes, The aforementioned field-effect transistor is A semiconductor substrate composed of a single-crystal semiconductor with a resistivity of 0.01 kΩ·cm or more or an impurity concentration of 1 × 10¹⁶ / cm³ or less at any temperature, A gate insulating layer in contact with the semiconductor substrate, A control gate electrode in contact with the gate insulating layer, One or more storage gate electrodes are arranged in contact with the gate insulating layer and alongside the control gate electrode, A terminal electrode in contact with the semiconductor substrate, Equipped with, An electronic device in which a heat supply unit capable of supplying heat to the semiconductor substrate is arranged inside the aforementioned housing.

10. The electronic device according to claim 7, wherein a light irradiation unit capable of irradiating light onto the semiconductor substrate is arranged inside the housing.

11. The electronic device according to claim 7, wherein the housing has an opening.

12. The electronic device according to claim 7, wherein a heat supply unit capable of supplying heat to the semiconductor substrate is arranged inside the housing.

13. The electronic device according to claim 9, wherein the heat supply unit is a thermoelectric element.

14. The electronic device according to claim 12, wherein the heat supply unit is a thermoelectric element.

15. A method for switching the polarity of a field-effect transistor, The aforementioned field-effect transistor is At any given temperature, the resistivity is 0.01 kΩ·cm or higher, or the impurity concentration is 1 × 10⁻⁶ １６ / cm ３ A semiconductor substrate composed of the following single-crystal semiconductors, A gate insulating layer in contact with the semiconductor substrate, A control gate electrode in contact with the gate insulating layer, One or more storage gate electrodes are arranged in contact with the gate insulating layer and alongside the control gate electrode, A terminal electrode in contact with the semiconductor substrate, Equipped with, A method comprising applying a positive or negative voltage to one or more storage gate electrodes while supplying light or heat to the semiconductor substrate, or supplying light or heat to the semiconductor substrate while applying a positive or negative voltage to one or more storage gate electrodes.

16. The positive voltage is applied to the one or more storage gate electrodes of the field-effect transistor that is operated as an N-type transistor. The method according to claim 15, wherein the negative voltage is applied to the one or more storage gate electrodes of the field-effect transistor that is operated as a P-type transistor.

17. A method for modifying an integrated circuit, comprising changing the configuration of a logic circuit using the field-effect transistor by the method described in claim 15 or 16.