Semiconductor device

Abstract

A semiconductor device (1) includes: a substrate (10); a regrowth layer (22) provided so as to cover gate openings (20); a gate electrode (32) provided over the regrowth layer (22) so as to cover the gate openings (20); source electrodes (34) disposed away from the gate electrode (32); and a drain electrode (36) provided under the substrate (10). The regrowth layer (22) has a normal region (23c) having a substantially even thickness and abnormal growth regions (23a, 23b) having smaller thicknesses than the normal region (23c), outside the gate openings (20) in a plan view of the substrate (10). Neither the gate electrode (32) nor the source electrodes (34) overlap with the abnormal growth regions (23a, 23b) in the plan view of the substrate (10).

Description

semiconductor devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Nitride semiconductors, typified by GaN, are wide-gap semiconductors with a large band gap, and are characterized by a large breakdown field and a high electron saturation drift velocity compared to compound semiconductors such as GaAs or Si semiconductors. For example, the band gaps of GaN and AlN are 3.4 eV and 6.2 eV, respectively, at room temperature. For this reason, research and development of power transistors using nitride semiconductors, which are advantageous for achieving high output and / or high breakdown voltage, is currently being actively conducted.

[0003] Patent Document 1 discloses a vertical field effect transistor (FET). Patent Document 1 discloses that when a regrowth layer is provided so as to cover a gate opening, abnormal growth of the regrowth layer occurs. Patent Document 1 suppresses abnormal growth by making at least a portion of the outline of the gate opening follow a circular arc or an elliptical arc.

[0004] Patent No. 7017579

[0005] The vertical field effect transistor disclosed in Patent Document 1 has problems such as an increase in leakage current and a decrease in breakdown voltage.

[0006] Therefore, the present disclosure provides a semiconductor device having a low leakage current and a high breakdown voltage.

[0007] A semiconductor device according to one aspect of the present disclosure comprises a substrate, a first semiconductor layer of a first conductivity type provided above the substrate, a second semiconductor layer of a second conductivity type provided above the first semiconductor layer and having a polarity different from that of the first conductivity type, a third semiconductor layer provided so as to cover a first opening that penetrates the second semiconductor layer and reaches the first semiconductor layer, a gate electrode provided above the third semiconductor layer so as to cover the first opening, a source electrode provided at a distance from the gate electrode, and a drain electrode provided below the substrate, wherein the third semiconductor layer includes, outside the first opening in a planar view of the substrate, a first region having a substantially uniform thickness and a second region having a thickness thinner than the first region, and neither the gate electrode nor the source electrode overlaps the second region in a planar view of the substrate.

[0008] According to the present disclosure, it is possible to provide a semiconductor device having a low leakage current and a high breakdown voltage.

[0009] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. FIG. 2 is a plan view of the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view schematically showing an off-angle of a substrate. FIG. 4 is a plan view schematically showing an abnormal growth region of a regrowth layer. FIG. 5 is a cross-sectional view schematically showing an abnormal growth region of a regrowth layer. FIG. 6 is an enlarged plan view of a semiconductor device according to the first embodiment. FIG. 7 is a graph showing the off-characteristics of the semiconductor device according to the first embodiment. FIG. 8 is a plan view of a semiconductor device according to a second embodiment. FIG. 9 is an enlarged plan view of a semiconductor device according to the second embodiment.

[0010] (Summary of the Present Disclosure) A semiconductor device according to a first aspect of the present disclosure includes a substrate, a first semiconductor layer of a first conductivity type provided above the substrate, a second semiconductor layer of a second conductivity type provided above the first semiconductor layer and having a polarity different from that of the first conductivity type, a third semiconductor layer provided so as to cover a first opening that penetrates the second semiconductor layer and reaches the first semiconductor layer, a gate electrode provided above the third semiconductor layer so as to cover the first opening, a source electrode provided apart from the gate electrode, and a drain electrode provided below the substrate, wherein the third semiconductor layer includes, outside the first opening in a planar view of the substrate, a first region having a substantially uniform thickness and a second region having a thickness thinner than the first region, and neither the gate electrode nor the source electrode overlaps the second region in a planar view of the substrate.

[0011] The phrase "substantially uniform thickness (or film thickness)" means, for example, that when the thickness of a target film is measured at multiple locations within a target region, the difference between each measured value and the average thickness measurement is 10% or less of the average. The number of measurement locations can be, for example, 2 to 10. Alternatively, the thickness can be considered to be "substantially uniform" when the angle between the upper and lower surfaces of the film in a cross section cut along the thickness direction is 2° or less.

[0012] The third semiconductor layer can be formed, for example, by a crystal regrowth process performed after the first opening is formed. In a plan view of the substrate, the third semiconductor layer includes a second region as an abnormally grown region due to abnormal growth during the crystal regrowth process. The second region is thinner than the first region, which can increase leakage current. For example, if a gate electrode or a source electrode is provided so as to overlap the second region in a plan view of the substrate, leakage current can occur between the drain electrode provided below the substrate and the gate electrode or source electrode, which can lead to a decrease in breakdown voltage.

[0013] In contrast, in the semiconductor device according to the present embodiment, as described above, neither the gate electrode nor the source electrode is provided in the second region in plan view, which makes it possible to suppress an increase in leakage current and achieve high breakdown voltage characteristics.

[0014] A semiconductor device according to a second aspect of the present disclosure is the semiconductor device according to the first aspect, wherein the third semiconductor layer includes a fourth semiconductor layer including a channel region, and a fifth semiconductor layer of the second conductivity type provided between the fourth semiconductor layer and the gate electrode.

[0015] This allows the fifth semiconductor layer of the second conductivity type to raise the potential of the channel, making it possible to operate the semiconductor device with normally-off characteristics.

[0016] A semiconductor device according to a third aspect of the present disclosure is the semiconductor device according to the second aspect, wherein the source electrode has an elongated shape in a first direction in a planar view of the substrate, and the first opening includes, in a planar view of the substrate, two straight portions extending along the first direction with the source electrode sandwiched therebetween, a first connection portion connecting first ends of each of the two straight portions in the first direction in an arch shape, and a second connection portion connecting second ends of each of the two straight portions opposite the first ends in an arch shape.

[0017] This allows the curvature of each of the first and second connecting portions to be small, significantly suppressing the occurrence of growth singularities, thereby suppressing an increase in leakage current through the growth singularities and achieving high breakdown voltage characteristics.

[0018] The growth singularity is a position that can be the starting point for abnormal growth, and specifically corresponds to a bending point in the contour of the opening. The larger the angle between the two line segments at the bending point, the less likely abnormal growth will occur. Therefore, by connecting the ends of the straight lines in an arch shape, it is possible to make the contour of the opening smoothly curved like an arc, for example, and thereby suppress abnormal growth.

[0019] A semiconductor device according to a fourth aspect of the present disclosure is a semiconductor device according to the third aspect, which comprises three or more source electrodes, and two or more first openings arranged side by side in a second direction perpendicular to the first direction, the three or more source electrodes arranged side by side in the second direction, and the source electrodes arranged between adjacent first openings.

[0020] This allows for a larger current, i.e., a higher output. Furthermore, for the source electrode disposed between adjacent first openings, the first connection portion and the second connection portion can be avoided in the first direction. This reduces the abnormal growth region caused by the first connection portion and the second connection portion, thereby further reducing the leakage current and achieving even higher breakdown voltage characteristics.

[0021] A semiconductor device according to a fifth aspect of the present disclosure is the semiconductor device according to the second aspect, and includes a plurality of source electrodes, each of which has an elongated shape in a first direction in a planar view of the substrate, and which is arranged side by side in a second direction perpendicular to the first direction in a planar view of the substrate, and the first opening is provided between each of adjacent source electrodes in the second direction in a planar view of the substrate, and includes a plurality of straight portions extending along the first direction, a first connection portion that connects first ends of each of the straight portions in the first direction in a continuous arch shape along the second direction, and a second connection portion that connects second ends of each of the straight portions opposite the first ends in a continuous arch shape along the second direction.

[0022] This allows the curvature of each of the first and second connecting portions to be small, significantly suppressing the occurrence of growth singularities, thereby suppressing an increase in leakage current through the growth singularities and achieving high breakdown voltage characteristics.

[0023] A semiconductor device according to a sixth aspect of the present disclosure is a semiconductor device according to any one of the third to fifth aspects, further comprising source electrodes arranged along the first direction, and each of the multiple linear portions extends continuously across the multiple source electrodes arranged along the first direction.

[0024] This makes it possible to achieve a larger current, that is, a higher output characteristic.

[0025] A semiconductor device according to a seventh aspect of the present disclosure is the semiconductor device according to any one of the third to sixth aspects, wherein, in a plan view of the substrate, a first virtual line is a virtual line that passes through a center of the source electrode and is parallel to the first direction, and a second virtual line is a virtual line that passes through the center of the source electrode and is orthogonal to the first direction, where: (a) a first distance is a distance on the second virtual line between an outline of the line portion on the source electrode side and an outline of the fifth semiconductor layer on the source electrode side; (b) a second distance is the distance on the first virtual straight line between the outer edge contour of the fifth semiconductor layer on the first connection portion side and the contour of the first connection portion on the side opposite the source electrode; and (c) a third distance is the distance on the first virtual straight line between the contour of the second connection portion on the source electrode side and the contour of the fifth semiconductor layer on the source electrode side of the portion located between the source electrode and the second connection portion, both of the second distance and the third distance are longer than the first distance.

[0026] When the third semiconductor layer is formed by a crystal regrowth process so as to cover the first opening, a one-sided abnormal growth region is likely to occur along the off-axis direction of the substrate. Furthermore, to achieve good transistor operation in a semiconductor device, it is desirable that the gate electrode surrounding and adjacent to the source electrode be a normal gate electrode free from abnormal growth. Therefore, to avoid the abnormal growth region, the second distance and the third distance are made longer than the first distance at the longitudinal end (i.e., the first direction) of the source electrode. This suppresses an increase in leakage current through the abnormal growth region, thereby achieving high breakdown voltage characteristics.

[0027] A semiconductor device according to an eighth aspect of the present disclosure is the semiconductor device according to the seventh aspect, wherein, in a planar view of the substrate, (a) a fourth distance is defined as the distance on the first virtual straight line between the outline of the first connection portion on the source electrode side and the outline of the fifth semiconductor layer on the source electrode side of a portion of the fifth semiconductor layer located between the source electrode and the first connection portion, and (b) a fifth distance is defined as the distance on the first virtual straight line between the outer edge outline of the fifth semiconductor layer on the second connection portion side and the outline of the second connection portion on the side opposite the source electrode, and both the fourth distance and the fifth distance are longer than the first distance.

[0028] This allows a normal gate electrode that does not include an abnormal growth region to be formed regardless of whether the off-direction of the substrate is to the positive or negative side of the first direction, thereby suppressing an increase in leakage current through the abnormal growth region and achieving high breakdown voltage characteristics.

[0029] A semiconductor device according to a ninth aspect of the present disclosure is a semiconductor device according to any one of the first to eighth aspects, in which a second opening is provided at a position away from the first opening in a planar view of the substrate, penetrating the third semiconductor layer and reaching the second semiconductor layer, and at least a portion of the source electrode is provided within the second opening.

[0030] This allows the second semiconductor layer and the source electrode to be in contact with each other within the second opening, so that the potential of the second semiconductor layer can be fixed to the source potential. This allows for stable transistor operation and improved breakdown voltage. Furthermore, the source electrode and the channel can be in contact with each other within the second opening, so that the source contact resistance can be reduced.

[0031] A semiconductor device according to a tenth aspect of the present disclosure is a semiconductor device according to any one of the first to ninth aspects, wherein the source electrode has an elongated shape in a first direction when viewed in a plan view of the substrate, and the upper surface of the substrate has an off-angle inclined along the first direction.

[0032] This makes it possible to prevent the generation of an abnormally grown region in the short direction of the first opening, which may affect the operation of the device, and therefore to suppress deterioration of the characteristics of the semiconductor device.

[0033] A semiconductor device according to an eleventh aspect of the present disclosure is the semiconductor device according to the tenth aspect, wherein the substrate includes gallium nitride, and the first direction is the a-axis direction of gallium nitride.

[0034] This makes it easier to reduce the ohmic contact resistance of the source electrode, thereby reducing the on-resistance.

[0035] A semiconductor device according to a twelfth aspect of the present disclosure is the semiconductor device according to the tenth aspect, wherein the substrate includes gallium nitride, and the first direction is the m-axis direction of gallium nitride.

[0036] This improves the flatness of the surface of the semiconductor layer grown on the substrate, which increases the stability of processes such as exposure, enabling the provision of high-quality semiconductor devices and an improved yield.

[0037] A semiconductor device according to a thirteenth aspect of the present disclosure is a semiconductor device according to any one of the first to twelfth aspects, wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer all contain a nitride semiconductor as a main component.

[0038] By using nitride semiconductors with a large band gap, high output and high breakdown voltage can be achieved.

[0039] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0040] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement positions, and connection configurations shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in independent claims are described as optional components.

[0041] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0042] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, such as circle or ellipse, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0043] In this specification and the drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional Cartesian coordinate system. When the planar shape of the substrate is rectangular, the x-axis and y-axis are directions parallel to a first side of the rectangle and a second side perpendicular to the first side, respectively. The z-axis is the thickness direction of the substrate. In this specification, the "thickness direction" of the substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may also be referred to as the "lateral direction."

[0044] Furthermore, the side of the substrate on which the gate electrode and source electrode are provided is considered to be "upper" or "upper side", and the side of the substrate on which the drain electrode is provided is considered to be "lower" or "lower side".

[0045] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0046] In this specification, unless otherwise specified, the term "plan view" refers to a view perpendicular to the main surface of the substrate of the nitride semiconductor device, that is, a view of the main surface of the substrate from the front.

[0047] Furthermore, in this specification, the distance between A and B in a planar view refers to the shortest distance between A and B in a planar view. When A and B have a certain size, the distance is the length of the shortest line segment among the countless line segments connecting any point on the contour line representing the outer shape of A in a planar view with any point on the contour line representing the outer shape of B.

[0048] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0049] In this specification, AlGaN refers to a ternary mixed crystal Al ｘ Ga １－ｘ Hereinafter, multi-element mixed crystals are abbreviated by the arrangement of the symbols of the respective constituent elements, such as AlInN, GaInN, etc. For example, AlInN, which is an example of a nitride semiconductor, ｘ Ga １－ｘ－ｙ In ｙ N (0<x<1, 0<y<1, and 0<x+y<1) is abbreviated as AlGaInN.

[0050] First Embodiment [Configuration] First, the configuration of a semiconductor device according to a first embodiment will be described with reference to FIGS. 1 and 2. FIG.

[0051] Fig. 1 is a cross-sectional view of a semiconductor device 1 according to this embodiment. In Fig. 1, each component, such as a semiconductor layer and an electrode, is shaded with diagonal lines to indicate a cross section. Fig. 1 shows a cross section taken along line II in Fig. 2.

[0052] Fig. 2 is a plan view of the semiconductor device 1 according to this embodiment. Fig. 2(b) is an enlarged view of Fig. 2(a), and the source electrode pad 44 is not shown.

[0053] 1, the semiconductor device 1 according to this embodiment is a so-called vertical field-effect transistor (FET). Specifically, in the semiconductor device 1, a current flows between the drain electrode 36 and the source electrode 34 in a direction perpendicular to the main surface of the substrate 10.

[0054] The semiconductor device 1 is a device having a stacked structure of nitride semiconductor layers containing nitride semiconductors such as GaN and AlGaN as the main components. Note that "A contains B as the main component" means that the content of B in A is 50% or more.

[0055] The semiconductor device 1 has a heterostructure of an AlGaN film and a GaN film. In the heterostructure of the AlGaN film and the GaN film, spontaneous polarization or piezoelectric polarization on the C-plane represented by the (0001) plane generates a high concentration of two-dimensional electron gas (2DEG) 25 at the heterointerface. Therefore, even in an undoped state, a high concentration of 1×10 １３ cm －２ The sheet carrier concentration can be obtained as above.

[0056] The semiconductor device 1 according to this embodiment is a normally-off FET. In the semiconductor device 1, for example, the source electrode 34 is grounded (i.e., the potential is 0 V), and a positive potential is applied to the drain electrode 36. The potential applied to the drain electrode 36 is, for example, not limited to, 100 V or more and 1200 V or less. When the semiconductor device 1 is in the off state, 0 V or a negative potential (e.g., −5 V) is applied to the gate electrode 32. When the semiconductor device 1 is in the on state, a positive potential (e.g., +5 V) is applied to the gate electrode 32. The semiconductor device 1 may be a normally-on FET.

[0057] As shown in FIGS. 1 and 2 , the semiconductor device 1 includes a substrate 10, a drift layer 12, a first underlayer 14, a second underlayer 16, a third underlayer 18, a regrown layer 22, a gate electrode 32, a source electrode 34, a drain electrode 36, an interlayer insulating film 40, a gate electrode pad 42, and a source electrode pad 44. The semiconductor device 1 also includes a gate opening 20 and a source opening 30. In FIG. 2 , the outline of the gate opening 20 in a plan view is indicated by a dashed line. The outline of the gate opening 20 corresponds to the upper end of the side surface 20b of the gate opening 20. A specific planar layout will be described later, and the following description will first focus on the cross-sectional configuration of the semiconductor device 1.

[0058] The substrate 10 includes a nitride semiconductor. Specifically, the substrate 10 includes gallium nitride (GaN). The shape of the substrate 10 in plan view is, for example, rectangular, but is not limited to this.

[0059] The substrate 10 has a thickness of, for example, 300 μm and a carrier concentration of 1×10 １８ cm －３ n ＋ The substrate is made of n-type GaN. Note that n-type and p-type indicate the conductivity type of the semiconductor. ＋ The n-type indicates a state in which a semiconductor is doped with a high concentration of n-type dopants, i.e., a heavily doped semiconductor. －The term "type" refers to a state in which a semiconductor is doped with a low concentration of n-type dopant, i.e., lightly doped. ＋ Type and n － Both types are examples of the first conductivity type, and may be referred to as n-type without distinction. ＋ Type and p － Both types are examples of a second conductivity type that has a polarity different from that of the first conductivity type, and may be referred to as p-type without distinction.

[0060] The upper surface of the substrate 10 has an off-angle inclined along the y-axis direction. The y-axis direction is an example of a first direction, and refers to the positive or negative y-axis direction, or both.

[0061] FIG. 3 is a cross-sectional view schematically illustrating the off-angle θ of the substrate 10. In FIG. 3, the oblique lines in the substrate 10 represent the crystal planes of GaN. The off-angle θ can be expressed as the angle between the GaN crystal plane and the upper surface 10a or lower surface 10b of the substrate 10. The off-angle θ is, for example, greater than 0° and not greater than 5°. The off-angle θ may be 0.1° or greater. The off-angle θ may be 1° or less, or may be 0.5° or less. The upper surface 10a and the lower surface 10b are each the main surface of the substrate 10.

[0062] The crystal structure of a GaN crystal can be expressed by three directions: the a-axis direction, the m-axis direction, and the c-axis direction. The a-axis direction is the [11-20] direction. The m-axis direction is the [1-100] direction. The c-axis direction is the

[0001] direction. The GaN crystal plane shown in Figure 3 is the C-plane, also called the (0001) plane. The tilt direction of the crystal plane is called the off-direction, and is, for example, the a-axis direction or the m-axis direction.

[0063] The substrate 10 does not have to be a nitride semiconductor substrate, but may be, for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a zinc oxide (ZnO) substrate.

[0064] The drift layer 12 is an example of a first semiconductor layer of a first conductivity type provided above the substrate 10. The drift layer 12 contains a nitride semiconductor as a main component. The drift layer 12 is, for example, an n-type semiconductor layer having a thickness of 8 μm. － The drift layer 12 is a film made of GaN of the type. The donor concentration of the drift layer 12 is, for example, 1×10 １５ cm －３ 1x10 or more １７ cm －３ As an example, １６ cm －３ The carbon concentration (C concentration) of the drift layer 12 is, for example, 1×10 １５ cm －３ 2x10 or more １７ cm －３ The following is the result.

[0065] The drift layer 12 is provided, for example, in contact with the upper surface (main surface) 10 a of the substrate 10. The drift layer 12 is formed on the upper surface 10 a of the substrate 10 by crystal growth, for example, by a metal organic vapor phase epitaxy (MOVPE) method, a hydride vapor phase epitaxy (HVPE) method, or the like.

[0066] The first underlayer 14 is an example of a nitride semiconductor layer provided above the drift layer 12. In this embodiment, the first underlayer 14 is provided between the drift layer 12 and the second underlayer 16. The first underlayer 14 is a high-resistance layer having a higher resistance than the second underlayer 16. The first underlayer 14 is, for example, a 200 nm-thick film made of GaN doped with carbon (C). The first underlayer 14 is provided in contact with the upper surface of the drift layer 12. The first underlayer 14 is formed on the drift layer 12 by crystal growth using, for example, MOVPE, HVPE, or the like.

[0067] For example, the carbon concentration of the first underlayer 14 is 3×10 １７ cm －３ That's all, but 1 x 10 １８ cm －３In this case, the concentration of silicon (Si) or oxygen (O) as an n-type impurity is lower than the carbon concentration. For example, the silicon concentration or oxygen concentration of the first underlayer 14 is 5×10 １６ cm －３ The following is 2 x 10 １６ cm －３ The following may also be used: As for the type of ions implanted into the first underlayer 14, ion species other than those mentioned above can also provide the same effect as long as they are capable of increasing the resistance of the semiconductor layer.

[0068] The second underlayer 16 is an example of a second semiconductor layer of a second conductivity type provided above the drift layer 12. The second underlayer 16 contains a nitride semiconductor as a main component. The second underlayer 16 has a thickness of 400 nm and a carrier concentration of 1×10 １７ cm －３ The second underlayer 16 is a film made of p-type GaN, where p is a p-type GaN film. The second underlayer 16 is provided in contact with the upper surface of the first underlayer 14. The second underlayer 16 is formed on the first underlayer 14 by crystal growth using, for example, MOVPE, HVPE, or the like.

[0069] The second underlayer 16 is formed by crystal growth, but may also be formed by, for example, implanting magnesium (Mg) into the deposited i-GaN. Furthermore, the second underlayer 16 may not be a p-type nitride semiconductor layer, but may be an insulating layer obtained by implanting iron (Fe) or boron (B).

[0070] The second underlayer 16 suppresses leakage current between the source electrode 34 and the drain electrode 36. For example, when a reverse voltage is applied to the pn junction formed between the second underlayer 16 and the drift layer 12, specifically when the drain electrode 36 has a higher potential than the source electrode 34, a depletion layer extends to the drift layer 12. This enables the semiconductor device 1 to have a high breakdown voltage. In this embodiment, the drain electrode 36 has a higher potential than the source electrode 34 in both the off state and the on state, except in the case of reverse conduction. This allows the semiconductor device 1 to have a high breakdown voltage.

[0071] 1, in this embodiment, the second underlayer 16 is in contact with the source electrode 34. Therefore, the second underlayer 16 is fixed to the source potential applied to the source electrode 34. This stabilizes the potential of the second underlayer 16, thereby achieving effects such as stable transistor operation and improved breakdown voltage.

[0072] The third underlayer 18 is an example of a semiconductor layer provided above the second underlayer 16. The third underlayer 18 is a high-resistance layer having a higher resistance than the second underlayer 16. The third underlayer 18 is, for example, a 200 nm-thick film made of GaN (i-GaN). The third underlayer 18 is provided in contact with the upper surface of the second underlayer 16. The third underlayer 18 is formed on the second underlayer 16 by crystal growth using, for example, MOVPE, HVPE, or the like.

[0073] The third underlayer 18 is an undoped semiconductor layer, but may also be an insulating or semi-insulating layer. Here, "undoped" means that it is not doped with a dopant such as Si or Mg that changes the polarity of GaN to n-type or p-type. For example, the third underlayer 18 may be doped with carbon (C), similar to the first underlayer 14. For example, the carbon concentration of the third underlayer 18 is higher than the carbon concentration of the second underlayer 16.

[0074] For example, the carbon concentration of the third underlayer 18 is 3×10 １７ cm －３ That's all, but 1 x 10 １８ cm －３ In this case, the concentration of silicon (Si) or oxygen (O) as an n-type impurity is lower than the carbon concentration. For example, the silicon concentration or oxygen concentration of the third underlayer 18 is 5×10 １６ cm －３ The following is 2 x 10 １６ cm －３ The following may also be used: As for the type of ions implanted into the third underlayer 18, ion species other than those mentioned above can also provide the same effect as long as they are capable of increasing the resistance of the semiconductor layer.

[0075] A layer for suppressing the diffusion of p-type impurities such as Mg from the second underlayer 16 may be provided on the upper surface of the third underlayer 18. For example, a 20-nm-thick AlGaN layer may be provided as a diffusion suppression layer between the upper surface of the third underlayer 18 and the regrowth layer 22. For example, an InAlGaN layer may also be used as the diffusion suppression layer. If Mg diffuses to the vicinity of the channel, the carrier concentration of the two-dimensional electron gas 25 decreases, increasing the on-resistance. By providing a diffusion suppression layer, the increase in on-resistance can be suppressed. However, because the degree of Mg diffusion varies depending on the crystal growth conditions, a diffusion suppression layer is not necessarily required. Furthermore, at least one of the first underlayer 14 and the third underlayer 18 may not be provided.

[0076] In the semiconductor device 1, the drift layer 12, the first underlayer 14, the second underlayer 16, and the third underlayer 18 are successively formed on the upper surface 10a of the substrate 10 (see FIG. 3 ) by a crystal growth process. After crystal growth of the semiconductor films corresponding to each layer is performed, the layers are partially removed by patterning to form the gate opening 20. Specifically, the gate opening 20 is formed by removing a portion of each of the third underlayer 18, the second underlayer 16, and the first underlayer 14 so as to partially expose the drift layer 12. At this time, by removing a surface portion of the drift layer 12 by a predetermined thickness (e.g., 300 nm), the bottom surface 20a of the gate opening 20 is formed below the lower surface of the first underlayer 14.

[0077] The third underlayer 18, the second underlayer 16, and the first underlayer 14 are often removed using dry etching such as inductively coupled plasma etching (ICP), with a chlorine-based gas used as the process gas.

[0078] The gate opening 20 is an example of a first opening that penetrates the second underlayer 16 and reaches the drift layer 12. Specifically, the gate opening 20 penetrates the third underlayer 18, the second underlayer 16, and the first underlayer 14, in this order. A bottom surface 20a of the gate opening 20 is part of the upper surface of the drift layer 12. As shown in FIG. 1 , the bottom surface 20a is located below the lower surface of the first underlayer 14. The lower surface of the first underlayer 14 corresponds to the interface between the first underlayer 14 and the drift layer 12. The bottom surface 20a is, for example, parallel to the major surface of the substrate 10. When the semiconductor device 1 is on, a drain current flows between the drain electrode 36 and the source electrode 34 through the bottom surface 20a of the gate opening 20.

[0079] In this embodiment, the gate opening 20 is formed so that the opening area increases with increasing distance from the substrate 10. Specifically, the side surface 20b of the gate opening 20 is inclined obliquely. As shown in FIG. 1 , the cross-sectional shape of the gate opening 20 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid.

[0080] The inclination angle of the side surface 20b with respect to the bottom surface 20a is, for example, 20° to 80°, but may be 30° to 45°. The smaller the inclination angle, the closer the side surface 20b is to the C-plane, which improves the film quality of the regrowth layer 22 formed along the side surface 20b by crystal regrowth. On the other hand, the larger the inclination angle, the more the gate opening 20 is prevented from becoming too large, which enables the miniaturization of the semiconductor device 1.

[0081] The regrowth layer 22 is an example of a third semiconductor layer provided to cover the gate opening 20. The regrowth layer 22 contains a nitride semiconductor as a main component. As shown in FIG. 1 , the regrowth layer 22 includes an electron transit layer 24, an electron supply layer 26, and a threshold adjustment layer 28.

[0082] The electron transit layer 24 is an example of a first regrown layer provided to cover the upper surface of the third underlayer 18 and the side surface 20 b and bottom surface 20 a of the gate opening 20. Specifically, a portion of the electron transit layer 24 is provided along the bottom surface 20 a and side surface 20 b of the gate opening 20, and another portion of the electron transit layer 24 is provided on the upper surface of the third underlayer 18. The electron transit layer 24 is, for example, a 150 nm-thick film made of undoped GaN. Note that although the electron transit layer 24 is assumed to be undoped, a portion of it may be made n-type by, for example, doping with Si.

[0083] The electron transit layer 24 is in contact with the drift layer 12 at the bottom surface 20 a and the side surface 20 b of the gate opening 20. The electron transit layer 24 is in contact with each of the first underlying layer 14, the second underlying layer 16, and the third underlying layer 18 at the side surface 20 b of the gate opening 20. Furthermore, the electron transit layer 24 is in contact with the top surface of the third underlying layer 18.

[0084] The electron transit layer 24 is an example of a fourth semiconductor layer including a channel region. Specifically, a two-dimensional electron gas 25, which serves as a channel, is generated near the interface between the electron transit layer 24 and the electron supply layer 26. In FIG. 1 , the two-dimensional electron gas 25 is schematically illustrated by a dotted line. The two-dimensional electron gas 25 bends along the interface between the electron transit layer 24 and the electron supply layer 26, i.e., along the inner surface of the gate opening 20.

[0085] 1, an AlN layer having a thickness of about 1 nm is provided as a second regrown layer between the electron transit layer 24 and the electron supply layer 26. This suppresses alloy scattering, improves channel mobility, and makes it possible to reduce on-resistance. However, the AlN layer is not necessarily required.

[0086] The electron supply layer 26 is an example of a third regrown layer provided to cover the upper surface of the second underlayer 16 and the side surface 20 b and bottom surface 20 a of the gate opening 20. The electron transit layer 24 and the electron supply layer 26 are provided in this order from the substrate 10 side. The electron supply layer 26 is, for example, a film made of undoped AlGaN with a thickness of 20 nm. The electron supply layer 26 is formed to a shape that conforms to the upper surface of the electron transit layer 24 and to a substantially uniform thickness.

[0087] The electron supply layer 26 has a larger band gap than the electron transit layer 24. Therefore, an AlGaN / GaN heterointerface is formed between the electron supply layer 26 and the electron transit layer 24. The electron supply layer 26 supplies electrons to a channel region (two-dimensional electron gas 25) formed in the electron transit layer 24.

[0088] The threshold adjustment layer 28 is an example of a fifth semiconductor layer of the second conductivity type provided between the electron transit layer 24 and the gate electrode 32. Specifically, the threshold adjustment layer 28 is provided between the electron supply layer 26 and the gate electrode 32, and is in contact with the upper surface of the electron supply layer 26. The threshold adjustment layer 28 has a thickness of 100 nm and a carrier concentration of 1×10 １７ cm －３ The film is made of p-type AlGaN.

[0089] The provision of the threshold adjustment layer 28 increases the potential of the channel portion, thereby increasing the threshold of the transistor and realizing a normally-off state.

[0090] The threshold adjustment layer 28 may not be provided, and the gate electrode 32 may be provided in contact with the electron supply layer 26. Alternatively, for example, a layer made of SiN or SiO ２ may be provided between the gate electrode 32 and the electron supply layer 26. This makes it possible to suppress the gate current and shift the threshold voltage in the positive direction to achieve normally-off operation.

[0091] The electron transit layer 24, the electron supply layer 26, and the threshold adjustment layer 28 are formed by successively depositing nitride semiconductor films by a crystal regrowth process after forming the gate opening 20 and patterning them into a predetermined shape. Specifically, an undoped GaN film that will form the electron transit layer 24, an undoped AlGaN film that will form the electron supply layer 26, and a p-type AlGaN film that will form the threshold adjustment layer 28 are successively deposited by MOVPE, HVPE, or the like. After deposition, a portion of the p-type AlGaN film is etched away until the undoped AlGaN film is exposed, thereby forming the threshold adjustment layer 28. Furthermore, portions of the undoped AlGaN film and the undoped GaN film, as well as a portion of the third underlayer 18, are successively etched away until the second underlayer 16 is exposed. As a result, a source opening 30 is formed that reaches the second underlayer 16, and the electron supply layer 26 and the electron transit layer 24 are patterned into a predetermined shape.

[0092] The source opening 30 is an example of a second opening that penetrates the regrown layer 22 and reaches the second underlayer 16 at a position away from the gate opening 20 in a plan view of the substrate 10. In the present embodiment, the source opening 30 is provided at a position away from both the gate electrode 32 and the threshold adjustment layer 28 in a plan view of the substrate 10.

[0093] A bottom surface 30a of the source opening 30 is part of the upper surface of the second underlayer 16. As shown in FIG. 1 , the bottom surface 30a is located below the interface between the third underlayer 18 and the second underlayer 16. That is, the source opening 30 is formed by removing a surface portion of the second underlayer 16. Alternatively, the bottom surface 30a may be flush with the interface between the third underlayer 18 and the second underlayer 16. The bottom surface 30a is, for example, parallel to the major surface of the substrate 10.

[0094] 1, the source opening 30 is formed so that the opening area is constant regardless of the distance from the substrate 10. Specifically, the side surface 30b of the source opening 30 is perpendicular to the bottom surface 30a. In other words, the cross-sectional shape of the source opening 30 is rectangular.

[0095] Alternatively, the source opening 30 may be formed so that the opening area increases with increasing distance from the substrate 10. Specifically, the side surface 30b of the source opening 30 may be obliquely inclined. For example, the cross-sectional shape of the source opening 30 may be an inverted trapezoid, more specifically, an inverted isosceles trapezoid. In this case, the inclination angle of the side surface 30b relative to the bottom surface 30a may be, for example, in the range of 30° to 60°. The oblique inclination of the side surface 30b increases the contact area between the source electrode 34 and the electron transit layer 24 (two-dimensional electron gas 25), making it easier to achieve ohmic contact. The two-dimensional electron gas 25 is exposed at the side surface 30b of the source opening 30 and connected to the source electrode 34 at the exposed portion.

[0096] The source opening 30 is not necessarily required. The provision of the source opening 30 can reduce the ohmic contact resistance between the two-dimensional electron gas 25 functioning as a channel and the source electrode 34. Furthermore, the second underlayer 16 and the source electrode 34 can be electrically connected, which stabilizes the potential of the second underlayer 16 and provides effects such as stable transistor operation and improved breakdown voltage.

[0097] The gate electrode 32 is provided above the regrown layer 22 so as to cover the gate opening 20. Specifically, the gate electrode 32 is provided in contact with the upper surface of the threshold adjustment layer .

[0098] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 can be made of a material that makes ohmic contact with the p-type GaN layer. For example, palladium (Pd), nickel (Ni)-based material, tungsten silicide (WSi), gold (Au), etc. can be used.

[0099] The gate electrode 32 is formed by forming a conductive film by sputtering or vapor deposition after the formation of the threshold adjustment layer 28, the formation of the source opening 30, or the formation of the source electrode 34, and then patterning the formed conductive film.

[0100] The source electrode 34 is provided at a position away from the gate electrode 32. In this embodiment, at least a portion of the source electrode 34 is provided within the source opening 30. Specifically, the source electrode 34 is provided in contact with the bottom surface 30a and the side surface 30b of the source opening 30 so as to fill the source opening 30. The source electrode 34 is in direct contact with the two-dimensional electron gas 25 at the side surface 30b of the source opening 30. This makes it possible to reduce the contact resistance between the source electrode 34 and the two-dimensional electron gas 25. Note that a portion of the source electrode 34 may be provided on the upper surface of the electron supply layer 26.

[0101] The source electrode 34 is formed using a conductive material such as metal. Examples of the material for the source electrode 34 include Ti / Al (a laminated structure of a Ti layer and an Al layer), which can be ohmically connected to the n-type GaN layer by heat treatment. The source electrode 34 is formed by patterning a conductive film formed by sputtering or vapor deposition, for example.

[0102] The source electrode 34 forms a Schottky contact with p-type GaN. Therefore, in order to obtain better contact between the source electrode 34 and the second underlayer 16 containing p-type GaN as a main component, a metal material with a large work function, such as Pd or Ni, that can obtain a lower contact with p-type GaN may be inserted. This makes it possible to further stabilize the potential of the second underlayer 16.

[0103] The drain electrode 36 is provided below the substrate 10. Specifically, the drain electrode 36 is provided in contact with the lower surface 10b of the substrate 10.

[0104] The drain electrode 36 is formed using a conductive material such as a metal. For example, a material that makes ohmic contact with n-type GaN, such as Ti / Al, can be used as the material for the drain electrode 36. The drain electrode 36 is formed by, for example, sputtering or vapor deposition.

[0105] The interlayer insulating film 40 is provided to electrically insulate the gate electrode 32 and the threshold adjustment layer 28 from the source electrode pad 44. Specifically, the interlayer insulating film 40 is provided so as to cover at least the entire gate electrode 32 and the threshold adjustment layer 28, but not a part of the source electrode 34. The interlayer insulating film 40 contains, for example, a silicon oxide film or a silicon nitride film as its main component. The thickness of the interlayer insulating film 40 is not particularly limited, but is, for example, thicker than the gate electrode 32.

[0106] The gate electrode pad 42 is electrically connected to the gate electrode 32. A power supply, a drive circuit, or the like for controlling the gate electrode 32 is connected to the gate electrode pad 42 outside the semiconductor device 1. The gate electrode pad 42 is formed using a conductive material such as a metal.

[0107] The source electrode pad 44 is electrically connected to the source electrode 34. A power supply, a drive circuit, or the like that supplies a source potential to the source electrode 34 is connected to the source electrode pad 44 outside the semiconductor device 1. The source electrode pad 44 is formed using a conductive material such as a metal.

[0108] 2, the source electrode pad 44 is provided at a distance from the gate electrode pad 42 so as not to come into contact with the gate electrode pad 42. The source electrode pad 44 is provided so as to cover almost the entire area of ​​the semiconductor device 1 except for the gate electrode pad 42 in a plan view, and is in contact with each of the plurality of source electrodes 34 arranged in an island shape.

[0109] [Planar Layout] Next, the planar layout of the semiconductor device 1 according to this embodiment will be described with reference to FIG.

[0110] 2 can be called a finger-type layout in which a plurality of source electrodes 34 are arranged in a comb shape. Note that source electrode pads 44 are not shown in FIG. 2B.

[0111] Specifically, the semiconductor device 1 includes a plurality of source electrodes 34 each having an elongated shape in the y-axis direction. The plurality of source electrodes 34 are arranged side by side in each of the x-axis direction and the y-axis direction. The number of source electrodes 34 arranged side by side in the x-axis direction and the y-axis direction is not particularly limited. For example, the number of source electrodes 34 arranged side by side in the y-axis direction may be one, i.e., there may be no plurality of source electrodes 34 arranged side by side in the y-axis direction. Although not shown in FIG. 2 , a plurality of source openings 30 are provided in one-to-one correspondence with the plurality of source electrodes 34.

[0112] In this embodiment, the longitudinal direction of the source electrode 34 is the a-axis direction of GaN. This allows most of the side surface 20b of the gate opening 20 and the side surface 30b of the source opening 30 to be aligned with the m-axis direction. As a result, substantially no GaN crystal facets are generated on the side surfaces 20b and 30b, thereby achieving good electrode contact and low channel resistance.

[0113] The longitudinal direction of the source electrode 34 is not particularly limited. For example, the longitudinal direction of the source electrode 34 may be the m-axis direction of GaN. In this case, the flatness of the surface of each semiconductor layer crystal-grown on the substrate 10 is improved. This increases the stability of processes such as exposure, making it possible to provide semiconductor devices 1 with excellent quality and improve yield.

[0114] As shown in FIG. 1 , the gate electrode 32 and the threshold adjustment layer 28 are provided between adjacent source electrodes 34. Specifically, the gate electrode 32 is a flat electrode in plan view having a first through-hole that exposes the source electrode 34 at a position corresponding to the source electrode 34. The threshold adjustment layer 28 is a flat layer in plan view having a second through-hole that exposes the source electrode 34 at a position corresponding to the source electrode 34. A plurality of first through-holes and a plurality of second through-holes are provided so as to correspond one-to-one with the plurality of source electrodes 34. A portion of the threshold adjustment layer 28 and the second through-hole are exposed in the first through-hole provided in the gate electrode 32. Specifically, a portion of the threshold adjustment layer 28 surrounding the source electrode 34, and an edge portion of the second through-hole are exposed in the first through-hole. The shape of this edge portion in plan view is the same as the shape of the gate opening 20 in plan view, and is a ring shape with the number "0" extending vertically. In this specification, this ring shape may be referred to as a zero pattern shape.

[0115] The semiconductor device 1 has a plurality of gate openings 20. The plurality of gate openings 20 are arranged side by side in the x-axis direction. Each of the plurality of gate openings 20 has a zero pattern shape in plan view. In plan view, one source electrode 34 or a plurality of source electrodes 34 arranged side by side in the y-axis direction is arranged on the inner periphery of the ring of the gate openings 20. Furthermore, one source electrode 34 or a plurality of source electrodes 34 arranged side by side in the y-axis direction is also arranged between adjacent gate openings 20.

[0116] As shown in FIG. 2, the gate opening 20 includes, in plan view, two linear portions 21a and 21b and two connecting portions 21c and 21d.

[0117] The two linear portions 21a and 21b are portions that extend along the y-axis direction with the source electrode 34 sandwiched therebetween. In the present embodiment, the two linear portions 21a and 21b each extend continuously across the multiple source electrodes 34 that are lined up along the y-axis direction.

[0118] The connecting portion 21c is an example of a first connecting portion, and is a portion that connects the first ends of the two straight portions 21a and 21b on the positive side in the y-axis direction in an arch shape. The connecting portion 21d is an example of a second connecting portion, and is a portion that connects the second ends of the two straight portions 21a and 21b on the negative side in the y-axis direction in an arch shape.

[0119] Here, "arch-shaped" refers to a shape that is convex toward either the positive or negative side in the y-axis direction. For example, the connecting portion 21c has a smoothly curved shape with a substantially constant width. Specifically, the contour of the connecting portion 21c is a semicircular arc on both the inner and outer circumferential sides.

[0120] By connecting the first ends of the two linear portions 21 a and 21 b in an arch shape, the curvature of the connecting portion 21 c can be made smaller than when each first end is individually terminated in a semicircular arc shape, thereby effectively suppressing the occurrence of growth singularities during regrowth.

[0121] The connecting portion 21d has an inverted shape of the connecting portion 21c. The modifications applicable to the connecting portion 21c are also applicable to the connecting portion 21d. Note that the connecting portion 21d may have a different shape from the connecting portion 21c.

[0122] For example, the outline of the connection portion 21c may be an elliptical arc or a quadratic function shape. Furthermore, the outline of the connection portion 21c does not have to be a curve. For example, the outline of the connection portion 21c may be a broken line that is convex toward the positive side of the y-axis. The angle between adjacent line segments that make up the broken line is greater than 90°. For example, each bending point of the broken line may be positioned on a virtual circular or elliptical arc. The use of a broken line can improve the accuracy of patterning when forming the connection portion 21c. The outline of the connection portion 21c may be formed by combining straight lines (line segments) and curves.

[0123] 2, in the semiconductor device 1, two source electrodes 34 aligned in the y-axis direction are arranged on the inner periphery of the zero-pattern shaped gate opening 20. In addition, two source electrodes 34 aligned in the y-axis direction are also arranged in the space between adjacent gate openings 20 in the x-axis direction.

[0124] In this embodiment, gate electrode 32 overlaps, in plan view, linear portions 21 a and 21 b of gate opening 20. On the other hand, gate electrode 32 does not overlap, in plan view, either connecting portions 21 c or 21 d of gate opening 20. This allows gate electrode 32 to be provided so as not to overlap, in plan view, abnormally grown regions 23 a and 23 b that may occur in regrown layer 22 formed after gate opening 20 is formed.

[0125] [Abnormal Growth Region] Next, the abnormal growth region will be described with reference to Figures 4 and 5. Figures 4 and 5 are a plan view and a cross-sectional view, respectively, that schematically show abnormal growth regions 23a and 23b of regrowth layer 22. Figure 5 shows a cross section taken along line V-V in Figure 4.

[0126] As described above, after the gate opening 20 is formed, the regrowth layer 22 is formed by crystal growth so as to cover the gate opening 20. At this time, abnormal growth occurs in the regrowth layer 22 due to the off-angle of the upper surface of the substrate 10. Specifically, unilateral abnormal growth regions 23a and 23b are formed along the direction of the off-angle of the GaN crystal. The larger the off-angle, the more pronounced the abnormal growth.

[0127] In the abnormal growth regions 23a and 23b, the thickness of each layer of the regrowth layer 22 is thinner than the design value. Specifically, as shown in FIG. 5 , the regrowth layer 22 includes a normal region 23c and abnormal growth regions 23a and 23b outside the gate opening 20 in a plan view. The normal region 23c is an example of a first region having a substantially uniform thickness. The abnormal growth regions 23a and 23b are an example of a second region and are thinner than the normal region 23c. In this embodiment, the abnormal growth regions 23a and 23b are considered to have a thickness that is 80% or less of the thickness of a region where abnormal growth does not occur (specifically, the normal region 23c). For example, as shown in FIG. 5 , the thickness T2 of the threshold adjustment layer 28 in the abnormal growth region 23b is smaller than the thickness T1 of the threshold adjustment layer 28 in the normal region 23c. The same applies to the electron transit layer 24 and the electron supply layer 26.

[0128] Note that "outside the gate opening 20 in plan view" refers to the range outside the upper end of the side surface 20b of the gate opening 20, in other words, the range that does not overlap with either the bottom surface 20a or the side surface 20b in plan view. Because the gate opening 20 has a zero pattern shape in plan view, the "outside the gate opening 20" exists on both the inner and outer circumferential sides of the zero pattern shape.

[0129] In a plan view, the ranges in which the abnormal growth regions 23a and 23b are formed are in the same direction relative to the gate opening 20. That is, abnormal growth of GaN crystal occurs from a portion of the outline of the gate opening 20 located in the off-direction (specifically, on the positive side of the y-axis direction) to extend toward the off-direction. The off-direction is the direction in which the crystal plane faces diagonally downward. In this embodiment, the off-direction is substantially aligned with the longitudinal direction of the source electrode 34, i.e., the y-axis direction. Specifically, the angle between the off-direction and the y-axis direction is within ±10°. By substantially aligning the off-direction and the y-axis direction, the formation of abnormal growth regions in the active region can be suppressed, thereby improving device characteristics. Therefore, the smaller the angle between the off-direction and the y-axis direction, the more the device characteristics can be improved. Therefore, the angle may be within ±5° or ±2°.

[0130] In this embodiment, as shown in Figure 4, abnormal growth region 23a is an abnormal growth region that occurs on the outer periphery of the zero pattern shape. It is formed so as to extend from the outer periphery of the outline of connection portion 21c toward the positive side in the y-axis direction. Abnormal growth region 23b is an abnormal growth region that occurs on the inner periphery of the zero pattern shape. It is formed so as to extend from the inner periphery of the outline of connection portion 21d toward the positive side in the y-axis direction.

[0131] It is expected that the region where the film thickness is reduced due to abnormal crystal growth will not substantially exist in the portion surrounding the source electrode 34. This is because a reduction in the film thickness of the threshold adjustment layer 28 will change the threshold voltage of the transistor. Specifically, the distance between the gate opening 20 and the source electrode 34 in the longitudinal direction (y-axis direction) of the source electrode 34 is ensured to be greater than a predetermined value.

[0132] 6 is an enlarged plan view of the semiconductor device 1 according to this embodiment. Two imaginary lines VL1 and VL2 are shown in FIG. The imaginary line VL1 is an example of a first imaginary line, which is an imaginary line that passes through the center of the source electrode 34 and is parallel to the y-axis direction in a planar view. The imaginary line VL2 is an example of a second imaginary line, which is an imaginary line that passes through the center of the source electrode 34 and is perpendicular to the y-axis direction (i.e., parallel to the x-axis direction) in a planar view.

[0133] 6 are both longer than the distance Lg1. In addition, the distances Lg4 and Lg5 are both longer than the distance Lg1. That is, the following relationships are satisfied:

[0134] (1) Lg1<Lg2 (2) Lg1<Lg3 (3) Lg1<Lg4 (4) Lg1<Lg5

[0135] The distance Lg1 is an example of a first distance and is the distance on the virtual line VL2. The distance Lg1 is the distance between the outline of the straight line portion 21a on the source electrode 34 side and the outline of the threshold adjustment layer 28 on the source electrode 34 side.

[0136] The distance Lg2 is an example of a second distance, and is the distance on the virtual line VL1. The distance Lg2 is the distance between the outer edge contour of the threshold adjustment layer 28 on the connection portion 21c side (the contour on the positive side in the y-axis direction) and the contour of the connection portion 21c on the side opposite to the source electrode 34.

[0137] The distance Lg3 is an example of a third distance and is the distance on the virtual line VL1. The distance Lg3 is the distance between the outline of the connection portion 21 d on the source electrode 34 side and the outline of the portion of the threshold adjustment layer 28 located between the source electrode 34 and the connection portion 21 d on the source electrode 34 side.

[0138] The distance Lg4 is an example of the fourth distance and is the distance on the virtual line VL1. The distance Lg4 is the distance between the outline of the connection portion 21c on the source electrode 34 side and the outline of the portion of the threshold adjustment layer 28 located between the source electrode 34 and the connection portion 21c on the source electrode 34 side.

[0139] The distance Lg5 is an example of a fifth distance and is a distance on the virtual line VL1. The distance Lg5 is the distance between the outer edge contour of the threshold adjustment layer 28 on the connection portion 21d side (the contour on the negative side in the y-axis direction) and the contour of the connection portion 21d on the side opposite to the source electrode 34.

[0140] As described above, by ensuring that the distance between the abnormal growth regions 23a and 23b and the source electrode 34 is longer than a predetermined value at the longitudinal ends of the source electrode 34, it is possible to suppress deterioration of the transistor characteristics.

[0141] 2 and 6, in the semiconductor device 1 according to the present embodiment, the gate electrode 32 does not overlap the abnormal growth regions 23 a and 23 b in plan view. Similarly, none of the multiple source electrodes 34 overlap the abnormal growth regions 23 a and 23 b in plan view.

[0142] In the abnormal growth regions 23 a and 23 b, the thicknesses of the threshold adjustment layer 28, the electron supply layer 26, and the electron transit layer 24 may be smaller than those in the normal region 23 c. Depending on the growth conditions, the thickness may become substantially zero. Therefore, when the gate electrode 32 overlaps the abnormal growth region 23 a or 23 b, the leakage current flowing through the gate electrode 32 increases.

[0143] 7 is a graph showing the off characteristics of the semiconductor device 1 according to this embodiment, in which the horizontal axis represents the drain voltage Vd and the vertical axis represents the drain current Id.

[0144] The example shown in Fig. 7 corresponds to semiconductor device 1 according to the present embodiment, and as shown in Fig. 2, gate electrode 32 does not overlap abnormal growth regions 23a and 23b in plan view. The comparative example shown in Fig. 7 is a semiconductor device in which the gate electrode is provided so as to overlap abnormal growth regions 23a and 23b in plan view. The example and comparative example have the same configuration except for the gate electrode.

[0145] 7, in the range of drain voltage Vd above 200 V, the drain current Id flows at a large level in the comparative example, whereas the drain current Id can be suppressed in the example. In the range of drain voltage above approximately 350 V, the leakage current can be suppressed by approximately two orders of magnitude compared to the comparative example.

[0146] The same applies to a case where a gate insulating film is provided as the threshold adjustment layer 28, such as in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). That is, by providing the gate electrode 32 and the source electrode 34 so as not to overlap the abnormal growth regions 23 a and 23 b in a plan view, it is possible to reduce the leakage current.

[0147] In the semiconductor device 1, a source electrode pad 44 is provided above the abnormal growth regions 23a and 23b via an interlayer insulating film 40. Because the interlayer insulating film 40 can suppress leakage current, the presence of the source electrode pad 44 or other wiring metals or the like does not pose a problem.

[0148] As described above, in the semiconductor device 1 according to this embodiment, an increase in leakage current can be suppressed, and high breakdown voltage characteristics can be achieved.

[0149] Second Embodiment Next, a second embodiment will be described.

[0150] The main difference between the second embodiment and the first embodiment is the shape of the gate opening in plan view. The following description will focus on the differences from the first embodiment, and description of the commonalities will be omitted or simplified.

[0151] Fig. 8 is a plan view of the semiconductor device 2 according to this embodiment. Fig. 9 is an enlarged plan view of the semiconductor device 2 according to this embodiment.

[0152] 8, the semiconductor device 2 differs from the semiconductor device 1 according to the first embodiment in that it includes a gate opening 120 instead of the gate opening 20. The gate opening 120 has a different shape in plan view from the gate opening 20. The gate opening 120 has a structure in which the multiple gate openings 20 shown in FIG. 2 are connected in the x-axis direction on both the positive and negative sides in the y-axis direction.

[0153] Specifically, the gate opening 120 includes, in plan view, a plurality of linear portions 121a and connecting portions 121c and 121d.

[0154] The plurality of straight line portions 121a are provided between adjacent source electrodes 34 in the x-axis direction. Each of the plurality of straight line portions 121a extends along the y-axis direction. In the present embodiment, each of the plurality of straight line portions 121a extends continuously across the plurality of source electrodes 34 aligned along the y-axis direction.

[0155] The connecting portion 121c is an example of a first connecting portion, and is a portion that connects first ends of the straight portions 121a on the positive side in the y-axis direction to each other in a continuous arch shape along the x-axis direction. The connecting portion 121d is an example of a second connecting portion, and is a portion that connects second ends of the straight portions 121a on the negative side in the y-axis direction to each other in a continuous arch shape along the x-axis direction.

[0156] For example, the contour of the outer periphery of the connecting portion 121c is curved at both ends on the positive and negative sides in the x-axis direction, and these curved portions are connected by straight lines (line segments). The contour of the inner periphery of the connecting portion 121c is made up of multiple semicircular arcs connecting adjacent straight line segments 121a. The specific shape of the contour of the connecting portion 121c is not particularly limited, and may be an elliptical arc, a broken line, or a combination of line segments and curves.

[0157] The connecting portion 121d has a shape obtained by inverting the connecting portion 121c. The modifications applicable to the connecting portion 121c are also applicable to the connecting portion 121d. Note that the connecting portion 121d may have a different shape from the connecting portion 121c.

[0158] In semiconductor device 2 according to the present embodiment, abnormal growth regions 123a and 23b are formed, as in embodiment 1. Abnormal growth regions 123a and 23b are formed so as to extend from the portion of the outline of gate opening 120 on the positive side in the y-axis direction to the positive side in the y-axis direction. In this embodiment, because the outline on the outer periphery of connection portion 121c includes a line segment, abnormal growth region 123a is also formed so as to extend along the line segment in the x-axis direction.

[0159] In the semiconductor device 2, the distances Lg2 and Lg3 shown in FIG. 9 are both longer than the distance Lg1. Furthermore, the distances Lg4 and Lg5 are both longer than the distance Lg1. In other words, the above-described inequalities (1) to (4) are satisfied. Note that the distances Lg1, Lg2, Lg3, Lg4, and Lg5 shown in FIG. 9 are each defined in the same manner as in the first embodiment.

[0160] In this embodiment, too, none of the gate electrode 32 and the plurality of source electrodes 34 overlap the abnormal growth regions 123 a and 23 b in plan view, which makes it possible to suppress an increase in leakage current and achieve high breakdown voltage characteristics in the semiconductor device 2 according to this embodiment.

[0161] In the present embodiment, an example has been shown in which all of the straight portions 121a of the gate opening 120 are connected by the connecting portion 121c and the connecting portion 121d, respectively, but this is not limiting. A plurality of gate openings may be provided, each of which connects a plurality of straight portions 121a. Furthermore, instead of one of the connecting portion 121c and the connecting portion 121d, the connecting portion 21c or 21d shown in the first embodiment may be provided.

[0162] While the semiconductor device according to one or more aspects has been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0163] For example, in the above embodiment, the shape of each of the source electrodes in plan view is elongated in one direction, but this is not limited to this. For example, the shape of each of the source electrodes in plan view may be a regular hexagon. Furthermore, the number of source electrodes included in the semiconductor device may be only one.

[0164] For example, each semiconductor layer may contain a semiconductor other than a nitride semiconductor as a main component. For example, each semiconductor layer may contain a compound semiconductor such as GaAs or SiGe, or a Si semiconductor as a main component. Even in this case, leakage current can be reduced in the same way as in the semiconductor devices including nitride semiconductors according to the above-described embodiments.

[0165] Furthermore, the semiconductor device is not limited to a vertical transistor. For example, a semiconductor device according to one aspect of the present disclosure may include a substrate, a first semiconductor layer of a first conductivity type provided above the substrate, a second semiconductor layer of a second conductivity type different in polarity from the first conductivity type provided above the first semiconductor layer, a third semiconductor layer provided to cover a first opening that penetrates the second semiconductor layer and reaches the first semiconductor layer, a first electrode provided above the third semiconductor layer to cover the first opening, and a second electrode provided below the substrate. In the semiconductor device according to this aspect, the third semiconductor layer includes, outside the first opening in a plan view of the substrate, a first region having a substantially uniform thickness and a second region having a thickness thinner than the first region, and the first electrode does not overlap the second region in a plan view of the substrate. Even with this configuration, leakage current through the second region can be suppressed, thereby achieving high breakdown voltage characteristics. Such a semiconductor device is, for example, a vertical diode. The modifications and combinations applicable to the transistor configurations described above can also be applied to diodes, provided there is no contradiction.

[0166] Furthermore, for example, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0167] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to each of the above-described embodiments within the scope of the claims or their equivalents.

[0168] The present disclosure can be used, for example, in power devices used in power supply circuits of consumer devices.

[0169] REFERENCE SIGNS LIST 1, 2 Semiconductor device 10 Substrate 10a Upper surface 10b Lower surface 12 Drift layer 14 First underlayer 16 Second underlayer 18 Third underlayer 20, 120 Gate opening 20a, 30a Bottom surface 20b, 30b Side surface 21a, 21b, 121a Linear portion 21c, 21d, 121c, 121d Connection portion 22 Regrowth layer 23a, 23b, 123a Abnormal growth region 23c Normal region 24 Electron transit layer 25 Two-dimensional electron gas 26 Electron supply layer 28 Threshold adjustment layer 30 Source opening 32 Gate electrode 34 Source electrode 36 Drain electrode 40 Interlayer insulating film 42 Gate electrode pad 44 Source electrode pad

Claims

1. A semiconductor device comprising: a substrate; a first semiconductor layer of a first conductivity type provided above the substrate; a second semiconductor layer of a second conductivity type, the second conductivity type being different in polarity from the first conductivity type, provided above the first semiconductor layer; a third semiconductor layer provided so as to cover a first opening which penetrates the second semiconductor layer to reach the first semiconductor layer; a gate electrode provided above the third semiconductor layer so as to cover the first opening; a source electrode provided at a distance from the gate electrode; and a drain electrode provided below the substrate, wherein the third semiconductor layer includes, outside the first opening in a planar view of the substrate, a first region having a substantially uniform thickness and a second region having a thickness thinner than the first region, and neither the gate electrode nor the source electrode overlaps the second region in a planar view of the substrate.

2. The semiconductor device according to claim 1, wherein the third semiconductor layer includes: a fourth semiconductor layer including a channel region; and a fifth semiconductor layer of the second conductivity type provided between the fourth semiconductor layer and the gate electrode.

3. The semiconductor device of claim 2, wherein the source electrode has an elongated shape in a first direction in a plan view of the substrate, and the first opening includes, in a plan view of the substrate, two straight line portions extending along the first direction with the source electrode between them, a first connection portion connecting first ends of the two straight line portions in the first direction in an arch shape, and a second connection portion connecting second ends of the two straight line portions opposite the first ends in an arch shape.

4. The semiconductor device of claim 3, comprising three or more of the source electrodes, two or more of the first openings arranged side by side in a second direction perpendicular to the first direction, the three or more source electrodes being arranged side by side in the second direction, and the source electrodes being arranged between adjacent ones of the first openings.

5. The semiconductor device of claim 2, comprising a plurality of source electrodes, each of which has an elongated shape in a first direction in a planar view of the substrate, the plurality of source electrodes being arranged side by side in a second direction perpendicular to the first direction in a planar view of the substrate, and the first opening being provided between each of the source electrodes adjacent to each other in the second direction in a planar view of the substrate, the first opening including: a plurality of straight line portions extending along the first direction; a first connection portion connecting first ends of each of the plurality of straight line portions in the first direction in a continuous arch shape along the second direction; and a second connection portion connecting second ends of each of the plurality of straight line portions opposite the first ends in a continuous arch shape along the second direction.

6. The semiconductor device according to any one of claims 3 to 5, further comprising source electrodes aligned along the first direction, and each of the multiple straight portions extends continuously across the multiple source electrodes aligned along the first direction.

7. In a plan view of the substrate, a first virtual line is a virtual line that passes through the center of the source electrode and is parallel to the first direction, and a second virtual line is a virtual line that passes through the center of the source electrode and is perpendicular to the first direction; (a) a first distance is a distance on the second virtual line between an outline of the line portion on the source electrode side and an outline of the fifth semiconductor layer on the source electrode side; (b) a second distance is a distance on the first virtual line between an outer edge outline of the fifth semiconductor layer on the first connection portion side and an outline of the first connection portion on the side opposite to the source electrode; and (c) a third distance is a distance on the first virtual line between an outline of the second connection portion on the source electrode side and an outline of the fifth semiconductor layer on the source electrode side of a portion of the fifth semiconductor layer that is located between the source electrode and the second connection portion, both of the second distance and the third distance are longer than the first distance. The semiconductor device according to any one of claims 3 to 5.

8. The semiconductor device of claim 7, wherein, in a planar view of the substrate, (a) a fourth distance is a distance on the first virtual straight line between an outline of the first connection portion on the source electrode side and an outline of the fifth semiconductor layer on the source electrode side of a portion of the fifth semiconductor layer located between the source electrode and the first connection portion, and (b) a fifth distance is a distance on the first virtual straight line between an outer edge outline of the fifth semiconductor layer on the second connection portion side and an outline of the second connection portion on the side opposite to the source electrode, both of the fourth distance and the fifth distance are longer than the first distance.

9. A semiconductor device as claimed in any one of claims 1 to 5, wherein a second opening is provided at a position away from the first opening in a planar view of the substrate, the second opening penetrating the third semiconductor layer to reach the second semiconductor layer, and at least a portion of the source electrode is provided within the second opening.

10. A semiconductor device according to any one of claims 1 to 5, wherein the source electrode has an elongated shape in a first direction in a planar view of the substrate, and an upper surface of the substrate has an off-angle inclined along the first direction.

11. The semiconductor device according to claim 8, wherein the substrate comprises gallium nitride, and the first direction is an a-axis direction of gallium nitride.

12. The semiconductor device according to claim 10, wherein the substrate comprises gallium nitride, and the first direction is an m-axis direction of gallium nitride.

13. The semiconductor device according to any one of claims 1 to 5, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer all contain a nitride semiconductor as a main component.