Semiconductor device and method for manufacturing semiconductor device
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2026-02-20
- Publication Date
- 2026-06-01
Abstract
Description
Semiconductor device and method for manufacturing the same
[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.
[0002] Patent Document 1 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in this document includes a support substrate and a semiconductor element. The semiconductor element is bonded by solid-state diffusion bonding via an intermediate metal layer.
[0003] JP 2022-63488 A
[0004] [Summary] If the bonding of a semiconductor element is insufficient, the semiconductor device may not be able to fully function.
[0005] An object of the present disclosure is to provide an improved semiconductor device and a manufacturing method thereof. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof that are capable of more appropriately bonding semiconductor elements.
[0006] A semiconductor device provided by a first aspect of the present disclosure includes a support, a first semiconductor element supported by the support, and a first bonding sheet interposed between the support and the first semiconductor element, wherein the first bonding sheet has a first portion including a portion overlapping with the first semiconductor element when viewed in a first direction that is a thickness direction of the support, and a second portion including a portion not overlapping with the first semiconductor element when viewed in the first direction and having a thickness in the first direction smaller than that of the first portion.
[0007] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: temporarily bonding a first bonding sheet to a support; and bonding a first semiconductor element to the support via the first bonding sheet. In the temporarily bonding step, a portion of the first bonding sheet is pressed toward the support in a first direction to form a first portion on the first bonding sheet that is not pressed on the first bonding sheet, and a second portion that is pressed and has a thickness in the first direction smaller than that of the first portion. In the bonding step, the first semiconductor element and at least a portion of the first portion overlap, but the first semiconductor element and at least a portion of the second portion do not overlap, when viewed in the first direction.
[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
[0009] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 is a partial enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 5 is a partial enlarged cross-sectional view taken along line V-V in FIG. 4. FIG. 6 is a partial enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 7 is a partial enlarged cross-sectional view taken along line VII-VII in FIG. 6. FIG. 8 is a system configuration diagram showing a vehicle equipped with a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a perspective view showing a holder used in the method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a bottom view showing a holder used in the method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10. FIG. 12 is a cross-sectional view taken along line XI-XI in FIG. 10. FIG. 13 is a partial enlarged cross-sectional view showing a holder used in the method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. FIG. 14 is a plan view showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14. FIG. 16 is a partially enlarged plan view showing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 17 is a partially enlarged plan view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 18 is a partially enlarged plan view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 19 is a partially enlarged plan view showing a semiconductor device according to the second embodiment of the present disclosure. FIG. 20 is a partially enlarged plan view showing a first modified example of the semiconductor device according to the second embodiment of the present disclosure. FIG. 21 is a partially enlarged plan view showing a semiconductor device according to the third embodiment of the present disclosure. FIG. 22 is a partially enlarged cross-sectional view taken along line XXII-XXII in FIG. 21. FIG. 23 is a partially enlarged plan view showing a first modified example of the semiconductor device according to the third embodiment of the present disclosure. FIG. 24 is a partially enlarged cross-sectional view taken along line XXIV-XXIV in FIG. 23. FIG. 25 is a perspective view showing another example of a holder used in the method for manufacturing a semiconductor device according to the present disclosure. FIG. 26 is a cross-sectional view showing another example of a holder used in the method for manufacturing a semiconductor device according to the present disclosure.
[0010] DETAILED DESCRIPTION Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.
[0011] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.
[0012] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." In the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.
[0013] 1 to 7 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a support 1, one or more first semiconductor elements 5A, and one or more first bonding sheets 6A. In this embodiment, the semiconductor device A1 further includes one or more second semiconductor elements 5B, one or more second bonding sheets 6B, a positive input terminal 7A, an output terminal 7B, a negative input terminal 7C, a plurality of control terminals 7D, a plurality of control terminals 7E, a plurality of first wires 8A, a plurality of second wires 8B, a plurality of third wires 8C, a plurality of fourth wires 8D, and a sealing resin 9.
[0014] There is no limitation on the number of one or more first semiconductor elements 5A and one or more second semiconductor elements 5B. In this embodiment, the semiconductor device A1 includes a plurality of first semiconductor elements 5A and a plurality of second semiconductor elements 5B. There is no limitation on the number of one or more first bonding sheets 6A and one or more second bonding sheets 6B. In this embodiment, the semiconductor device A1 includes a plurality of first bonding sheets 6A and a plurality of second bonding sheets 6B.
[0015] In FIGS. 1 to 7 , the thickness direction of the support is defined as the first direction z in the present disclosure. The first side of the first direction z is referred to as the z1 side, and the second side opposite the first side in the z direction is referred to as the z2 side. A direction perpendicular to the first direction z is defined as the second direction x. The first side of the second direction x is referred to as the x1 side, and the second side opposite the x1 side is referred to as the x2 side. A direction perpendicular to the first direction z and the second direction x is defined as the third direction y. The first side of the third direction y is referred to as the y1 side, and the second side opposite the y1 side is referred to as the y2 side. For ease of understanding, the positive input terminal 7A, the output terminal 7B, the negative input terminal 7C, the plurality of control terminals 7E and 7D, the plurality of first wires 8A, the plurality of second wires 8B, the plurality of third wires 8C, the plurality of fourth wires 8D, and the sealing resin 9 are omitted in FIGS. 2 to 7 .
[0016] The specific use of the semiconductor device A1 is not limited in any way. In the semiconductor device A1, a plurality of first semiconductor elements 5A form an upper arm circuit, and a plurality of second semiconductor elements 5B form a lower arm circuit, thereby forming a half-bridge circuit. The semiconductor device A1 forms, for example, an inverter that converts DC power to AC power and supplies power to a drive source such as a motor. Although the semiconductor device A1 of this embodiment will be described using an example in which it has one half-bridge circuit, it may also be configured to have, for example, three half-bridge circuits, thereby supplying power to a three-phase AC motor.
[0017] Each of the multiple first semiconductor elements 5A and the multiple second semiconductor elements 5B is configured using a semiconductor material primarily composed of SiC (silicon carbide). The semiconductor material is not limited to SiC and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like. In this embodiment, the first semiconductor elements 5A and the second semiconductor elements 5B are MOSFETs (metal-oxide-semiconductor field effect transistors). The first semiconductor elements 5A and the second semiconductor elements 5B are not limited to the first semiconductor elements 5A and the second semiconductor elements 5B, but may be field-effect transistors including MISFETs (metal-insulator-semiconductor FETs), bipolar transistors such as IGBTs (insulated gate bipolar transistors), IC chips such as LSIs, diodes, capacitors, or the like.
[0018] 4 to 7 , the first semiconductor element 5A and the second semiconductor element 5B of this embodiment have an element body 50, a drain electrode 51, a source electrode 52, a gate electrode 53, and a source sense electrode 54. The element body 50 is made of the semiconductor material described above. The drain electrode 51 is disposed on the z1 side of the element body 50 in the first direction z. The source electrode 52, the gate electrode 53, and the source sense electrode 54 are disposed on the z2 side of the element body 50 in the first direction z.
[0019] As shown in Figure 3, the support 1 has an insulating layer 10, a back surface metal layer 11, a first main surface metal layer 2A, a second main surface metal layer 2B, a third main surface metal layer 3A, a fourth main surface metal layer 3B, a bonding layer 4A and a bonding layer 4B.
[0020] The insulating layer 10 is an insulating plate-like member containing, for example, ceramic. The back surface metal layer 11 is laminated on the z1 side of the insulating layer 10 in the first direction z. The back surface metal layer 11 contains, for example, a metal such as Cu (copper). The first main surface metal layer 2A is laminated on the z2 side of the insulating layer 10 in the first direction z, on the x1 side of the second direction x. The second main surface metal layer 2B is laminated on the z2 side of the insulating layer 10 in the first direction z, on the x2 side of the second direction x. The first main surface metal layer 2A and the second main surface metal layer 2B are separated from each other and each contains, for example, a metal such as Cu (copper). The insulating layer 10, the back surface metal layer 11, the first main surface metal layer 2A, and the second main surface metal layer 2B may form, for example, a DBC (Direct Bonded Copper) substrate or an AMB (Active Metal Brazing) substrate.
[0021] The third main surface metal layer 3A is bonded to the first main surface metal layer 2A via a bonding layer 4A. The third main surface metal layer 3A contains a metal such as Cu (copper). The bonding layer 4A is intended to bond the first main surface metal layer 2A and the bonding layer 4A, for example, by solid-state diffusion bonding. The specific configuration of the bonding layer 4A is not limited in any way, and may be, for example, a configuration in which a metal layer containing Ag (silver) is formed on both sides of a base layer containing Al (aluminum). In this case, a metal layer containing Ag (silver) may be formed on the surfaces of the first main surface metal layer 2A and the third main surface metal layer 3A.
[0022] The fourth main surface metal layer 3B is bonded to the second main surface metal layer 2B via a bonding layer 4B. The fourth main surface metal layer 3B contains a metal such as Cu (copper). The bonding layer 4B is intended to bond the second main surface metal layer 2B and the bonding layer 4B, for example, by solid-state diffusion bonding. The specific configuration of the bonding layer 4B is not limited in any way, and may be, for example, a configuration in which a metal layer containing Ag (silver) is formed on both sides of a base layer containing Al (aluminum). In this case, a metal layer containing Ag (silver) may be formed on the surfaces of the second main surface metal layer 2B and the fourth main surface metal layer 3B.
[0023] The multiple first semiconductor elements 5A are conductively bonded to the third main surface metal layer 3A via multiple first bonding sheets 6A. In this embodiment, the drain electrodes 51 of the first semiconductor elements 5A are conductively bonded to the third main surface metal layer 3A via the first bonding sheet 6A. The first bonding sheet 6A is used to conductively bond the first semiconductor elements 5A to the third main surface metal layer 3A, for example, by solid-state diffusion bonding. The specific configuration of the first bonding sheet 6A is not limited. When solid-state diffusion bonding is used, the first bonding sheet 6A is configured such that metal layers containing, for example, Ag (silver) are formed on both sides of a base layer containing, for example, Al (aluminum). In this case, metal layers containing, for example, Ag (silver) may be formed on the surfaces of the first semiconductor elements 5A and the third main surface metal layer 3A. This allows, for example, the drain electrodes 51 of the multiple first semiconductor elements 5A to be conductively connected to the third main surface metal layer 3A. The specific shape of the first bonding sheet 6A is not limited; in the illustrated example, it is rectangular.
[0024] As shown in Figures 4 and 5, the first bonding sheet 6A includes a first portion 60 and a second portion 61. In Figure 4, the second portion 61 is hatched for ease of understanding, and this also applies to subsequent figures. The first portion 60 has a portion that overlaps with the first semiconductor element 5A when viewed in the first direction z. The second portion 61 includes a portion that does not overlap with the first semiconductor element 5A when viewed in the first direction z, and is thinner in the first direction z than the first portion 60. The second portion 61 is a pressure mark formed when the first bonding sheet 6A is temporarily bonded to the third main surface metal layer 3A (support 1) in the manufacturing method of the semiconductor device A1 described below.
[0025] The specific configurations of the first portion 60 and the second portion 61 are not limited in any way. In the illustrated example, the second portion 61 does not entirely overlap the first semiconductor element 5A when viewed in the first direction z, and is disposed on the outside in the second direction x and the third direction y. The second portion 61 contacts four edges of the first bonding sheet 6A. The second portion 61 contacts four corners of the first bonding sheet 6A. The second portion 61 has a rectangular ring shape when viewed in the first direction z. The first portion 60 is separated from all edges of the first bonding sheet 6A.
[0026] The second semiconductor elements 5B are electrically connected to the fourth main surface metal layer 3B via the second bonding sheets 6B. In this embodiment, the drain electrodes 51 of the second semiconductor elements 5B are electrically connected to the fourth main surface metal layer 3B via the second bonding sheets 6B. The second bonding sheets 6B are used to electrically connect the second semiconductor elements 5B to the fourth main surface metal layer 3B, for example, by solid-state diffusion bonding. The specific configuration of the second bonding sheet 6B is not limited in any way. When solid-state diffusion bonding is used, the second bonding sheet 6B is configured such that metal layers containing, for example, Ag (silver) are formed on both sides of a base layer containing, for example, Al (aluminum). In this case, metal layers containing, for example, Ag (silver) may be formed on the surfaces of the second semiconductor elements 5B and the fourth main surface metal layer 3B. This allows, for example, the drain electrodes 51 of the second semiconductor elements 5B to be electrically connected to the fourth main surface metal layer 3B. The specific shape of the second bonding sheet 6B is not limited in any way, and in the illustrated example, it is rectangular. The second bonding sheet 6B may have the same configuration as the first bonding sheet 6A, or may have a different configuration.
[0027] 6 and 7 , the second bonding sheet 6B includes a first portion 60 and a second portion 61. The first portion 60 has a portion that overlaps with the second semiconductor element 5B when viewed in the first direction z. The second portion 61 includes a portion that does not overlap with the second semiconductor element 5B when viewed in the first direction z, and is thinner in the first direction z than the first portion 60. The second portion 61 is a pressure mark formed when the second bonding sheet 6B is temporarily bonded to the fourth main surface metal layer 3B (support 1) in a manufacturing method of the semiconductor device A1 described below.
[0028] The specific configurations of the first portion 60 and the second portion 61 are not limited in any way. In the illustrated example, the second portion 61 does not entirely overlap the second semiconductor element 5B when viewed in the first direction z, and is disposed on the outside in the second direction x and the third direction y. The second portion 61 contacts four edges of the second bonding sheet 6B. The second portion 61 contacts four corners of the second bonding sheet 6B. The second portion 61 has a rectangular ring shape when viewed in the first direction z. The first portion 60 is separated from all edges of the second bonding sheet 6B.
[0029] The positive input terminal 7A is a terminal connected to the positive side of a DC power supply and is conductively joined to the third main surface metal layer 3A.
[0030] The output terminal 7B is a terminal connected to the load side of a motor, etc. The output terminal 7B is conductively joined to the fourth main surface metal layer 3B.
[0031] The negative input terminal 7C is connected to the negative side of the DC power supply and is electrically connected to, for example, the source electrodes 52 of the second semiconductor elements 5B via second wires 8B. The second wires 8B include a metal such as copper (Cu), aluminum (Al), or gold (Au).
[0032] For example, the source electrodes 52 of the plurality of first semiconductor elements 5A are electrically connected to the fourth main surface metal layer 3B via a plurality of first wires 8A. The first wires 8A include a metal such as copper (Cu), aluminum (Al), or gold (Au).
[0033] The plurality of control terminals 7D are terminals for controlling the plurality of first semiconductor elements 5A. The plurality of control terminals 7D are electrically connected to, for example, the gate electrodes 53, source sense electrodes 54, etc. of the plurality of first semiconductor elements 5A via a plurality of third wires 8C. The third wires 8C include a metal such as copper (Cu), aluminum (Al), or gold (Au).
[0034] The plurality of control terminals 7E are terminals for controlling the plurality of second semiconductor elements 5B. The plurality of control terminals 7E are electrically connected to, for example, the gate electrodes 53, source sense electrodes 54, etc. of the plurality of second semiconductor elements 5B via the plurality of fourth wires 8D. The fourth wires 8D include a metal such as copper (Cu), aluminum (Al), or gold (Au).
[0035] The sealing resin 9 covers a part of the support 1, the plurality of first semiconductor elements 5A, the plurality of second semiconductor elements 5B, etc. The positive input terminal 7A, the output terminal 7B, the negative input terminal 7C, the plurality of control terminals 7D, and the plurality of control terminals 7E each have a portion protruding from the sealing resin 9.
[0036] Next, a vehicle C1 equipped with the semiconductor device A1 will be described with reference to Fig. 8. The vehicle C1 is, for example, an electric vehicle (EV).
[0037] As shown in Fig. 8, vehicle C1 includes an on-board charger 910, a storage battery 920, and a drive system 930. Power is supplied to the on-board charger 910 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 910 via a wired connection. The on-board charger 910 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 910 is stepped up by the converter and then supplied to the storage battery 920. The stepped-up voltage is, for example, 600 V.
[0038] The drive system 930 drives the vehicle C1. The drive system 930 has an inverter 931 and a drive source 932. The semiconductor device A1 constitutes part of the inverter 931. The power stored in the storage battery 920 is supplied to the inverter 931. The power supplied from the storage battery 920 to the inverter 931 is DC power. In addition, unlike the power system shown in FIG. 8 , a step-up DC-DC converter may be further provided between the storage battery 920 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931 including the semiconductor device A1 is electrically connected to the drive source 932.
[0039] The drive source 932 includes an AC motor and a transmission. When AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle C1. This drives the vehicle C1. To drive the vehicle C1, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. The semiconductor device A1 in the inverter 931 is required to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.
[0040] Next, a method for manufacturing the semiconductor device A1 will be described.
[0041] 9 to 13 show a holder B1 used in the manufacturing method of the semiconductor device A1. The holder B1 is used to hold and temporarily bond the first bonding sheet 6A or the second bonding sheet 6B in the manufacturing method of the semiconductor device A1. There are no limitations on the material of the holder B1, and it may be, for example, metal, resin, or the like.
[0042] The holder B1 has, for example, a main surface 91, a protrusion 92, and a suction hole 93.
[0043] The main surface 91 faces the z1 side in the first direction z. The protrusions 92 protrude from the main surface 91 toward the z1 side in the first direction z. The number and shape of the protrusions 92 are not limited in any way. In the illustrated example, the holder B1 has one protrusion 92. The protrusion 92 has a rectangular ring shape when viewed in the first direction z. The number and shape of the protrusions 92 correspond to the configuration of the second parts 61 of the first bonding sheet 6A and the second bonding sheet 6B, which will be described below.
[0044] The protrusion 92 has an abutment surface 921. The abutment surface 921 faces the z1 side in the first direction z. The abutment surface 921 is located on the z1 side in the first direction z with respect to the main surface 91. The shape and size of the abutment surface 921 are not limited in any way, and various shapes such as a rectangular shape, a circular shape, an elliptical shape, or a polygonal shape can be selected. In the example shown in FIGS. 9 and 10 , the abutment surface 921 is rectangular and annular. In the illustrated example, the width of the abutment surface 921 is, for example, 0.1 mm or more and 2 mm or less.
[0045] The suction hole 93 opens in the main surface 91. There are no particular limitations on the specific shape of the suction hole 93, and in the example shown, the suction hole 93 is circular when viewed in the first direction z. There are no particular limitations on the number of suction holes 93. The holder B1 may have one suction hole 93 or multiple suction holes 93.
[0046] 11 and 12 , in the illustrated example, the holder B1 is attached to, for example, a base 98. The base 98 functions to apply a suction force necessary for holding the holder B1 and to move the holder B1 to a desired position. In the illustrated example, the base 98 has a suction hole 981. The suction hole 981 communicates with the suction hole 93. When gas is sucked through the suction hole 981, a negative pressure is generated near the suction hole 93. This negative pressure holds the first bonding sheet 6A or the second bonding sheet 6B on the abutment surface 921.
[0047] In the method for manufacturing the semiconductor device A1, a plurality of first semiconductor elements 5A are conductively bonded to the third principal surface metal layer 3A, and a plurality of second semiconductor elements 5B are conductively bonded to the fourth principal surface metal layer 3B. In this embodiment, solid-state diffusion bonding is used for these conductive bondings. The plurality of first bonding sheets 6A and second bonding sheets 6B are used to more appropriately realize solid-state diffusion bonding.
[0048] 14 and 15 , a support body 1 is prepared. Next, a holder B1 is used to temporarily bond a plurality of first bonding sheets 6A to the third main surface metal layer 3A, and a plurality of second bonding sheets 6B to the fourth main surface metal layer 3B. The first bonding sheet 6A and the second bonding sheet 6B are formed in a metal foil-like state, and, for example, their size in a plan view as viewed in the first direction z is, for example, approximately 2 mm to 15 mm square, and their thickness in the first direction z (thickness t0 in FIG. 13 ) is, for example, 0.05 mm to 0.3 mm, for example, approximately 0.11 mm.
[0049] The first bonding sheet 6A or the second bonding sheet 6B, which is prepared at a predetermined position not shown in the figure, is held by a holder B1 as shown in Fig. 11. The first bonding sheet 6A or the second bonding sheet 6B is in contact with the contact surface 921 due to the negative pressure of the suction holes 93.
[0050] Next, the holder B1 is moved above the third or fourth main surface metal layer 3A or 3B to which the first or second bonding sheet 6A or 6B is to be temporarily bonded. The holder B1 is then moved toward the z1 side in the first direction z. As a result of this downward movement, the first or second bonding sheet 6A or 6B comes into contact with the third or fourth main surface metal layer 3A or 3B, as shown in FIG.
[0051] When the holder B1 is further pressed toward the z1 side in the first direction z by the base 98, a portion of the first bonding sheet 6A or the second bonding sheet 6B is crushed by the pressing force from the contact surface 921, as shown in Fig. 13. This crushed portion is a pressure mark and becomes the second portion 61. The thickness t1 of the second portion 61 is thinner than the above-mentioned thickness t0 by a height dz.
[0052] The pressing force of the contact surface 921 causes the first bonding sheet 6A or the second bonding sheet 6B to be temporarily bonded to the third principal surface metal layer 3A or the fourth principal surface metal layer 3B. Although this bonding has a lower bonding strength than bonding by, for example, solid-state diffusion bonding, it prevents the plurality of first bonding sheets 6A and the plurality of second bonding sheets 6B from moving during subsequent transportation of the support body 1. In addition to the pressing force of the contact surface 921, temporary bonding may be achieved by, for example, applying ultrasonic waves or heating.
[0053] After the first bonding sheets 6A and the second bonding sheets 6B are temporarily bonded, the first semiconductor elements 5A and the second semiconductor elements 5B are placed on or temporarily bonded to the first bonding sheets 6A and the second bonding sheets 6B, as shown in FIGS. 1 and 2 . At this time, the first semiconductor elements 5A and the second semiconductor elements 5B are placed on or temporarily bonded to the first portions 60 of the corresponding first bonding sheets 6A and the corresponding second bonding sheets 6B. That is, the first semiconductor elements 5A and the second semiconductor elements 5B overlap with at least a portion of the first portions 60 of the corresponding first bonding sheets 6A and the corresponding second bonding sheets 6B in the first direction z. The first semiconductor elements 5A and the second semiconductor elements 5B do not overlap with at least a portion of the second portions 61 of the corresponding first bonding sheets 6A and the corresponding second bonding sheets 6B in the first direction z. In the illustrated example, when viewed in the first direction z, all of the first semiconductor elements 5A and the second semiconductor elements 5B overlap with the first portion 60, but do not overlap with all of the second portion 61.
[0054] 1 and 2 , the integrated product of the support 1, the plurality of first bonding sheets 6A and second bonding sheets 6B, and the plurality of first semiconductor elements 5A and second semiconductor elements 5B is then subjected to, for example, solid-state diffusion bonding. As a result, the plurality of first semiconductor elements 5A and the plurality of second semiconductor elements 5B are conductively bonded to the third main surface metal layer 3A and the fourth main surface metal layer 3B via the plurality of first bonding sheets 6A and the plurality of second bonding sheets 6B. The semiconductor device A1 is then manufactured through processes such as fixing the positive input terminal 7A, the output terminal 7B, the negative input terminal 7C, the plurality of control terminals 7D and 7E, connecting the plurality of first wires 8A, the plurality of second wires 8B, the plurality of third wires 8C and the plurality of fourth wires 8D, and forming the sealing resin 9.
[0055] Next, the operation of the semiconductor device A1 and the method for manufacturing the semiconductor device A1 will be described.
[0056] As shown in FIG. 13 , the second portion 61 of the first bonding sheet 6A is a pressure mark formed by, for example, pressure applied by the contact surface 921 of the holder B1. On the other hand, the first portion 60 is a non-pressurized portion that is not subjected to pressure by, for example, the contact surface 921. The thickness t1 of the second portion 61 in the first direction z is thinner than the thickness t0 of the first portion 60. Therefore, if solid-phase diffusion bonding is performed with the first semiconductor element 5A superimposed on the second portion 61, for example, bonding defects may occur. If ultrasonic waves or heating are applied during the temporary bonding of the first bonding sheet 6A, scratches may be formed on the surface of the second portion 61 or the crystalline structure may change. In such cases, the second portion 61 may also cause bonding defects. In this embodiment, the second portion 61 has a portion separated from the first semiconductor element 5A when viewed in the first direction z. This makes it possible to suppress bonding defects caused by the second portion 61 and more appropriately bond the first semiconductor element 5A.
[0057] In this embodiment, the entire second portion 61 is separated from the first semiconductor element 5A. As a result, the entire first semiconductor element 5A overlaps with the first portion 60, but does not overlap with the second portion 61. This is preferable for bonding the first semiconductor element 5A.
[0058] The second portion 61 contacts the edge of the first bonding sheet 6A and is arranged along the edge. As a result, when the first bonding sheet 6A is temporarily bonded to the third main surface metal layer 3A, the edge and the portion near the edge of the first bonding sheet 6A are temporarily bonded to the third main surface metal layer 3A. This prevents the temporarily bonded first bonding sheet 6A from peeling off from the third main surface metal layer 3A due to insufficient bonding. The second portion 61 contacts the corner of the first bonding sheet 6A. This further prevents the first bonding sheet 6A from peeling off.
[0059] Similar to the improved bonding of the first semiconductor element 5A due to the configuration of the first part 60 and second part 61 of the first bonding sheet 6A, the improved bonding of the second semiconductor element 5B can be expected due to the configuration of the first part 60 and second part 61 of the second bonding sheet 6B.
[0060] 16 to 26 show modified examples and other embodiments of the present invention. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. The configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.
[0061] 16 shows a first modification of the semiconductor device A1. While the figure shows a portion where a first semiconductor element 5A is bonded to a third principal surface metal layer 3A via a first bonding sheet 6A, the illustrated configuration may also be applied to a portion where a second semiconductor element 5B is bonded to a fourth principal surface metal layer 3B via a second bonding sheet 6B, and the same applies to subsequent modifications.
[0062] In the semiconductor device A11 of this modified example, the first bonding sheet 6A has a plurality of second portions 61. The plurality of second portions 61 are arranged along the edge of the first bonding sheet 6A and are in contact with the edge of the first bonding sheet 6A. Four of the second portions 61 are in contact with four corners of the first bonding sheet 6A. A portion of the first portion 60 is interposed between adjacent second portions 61. The first portions 60 are in contact with the edge of the first bonding sheet 6A. In other words, the plurality of second portions 61 of this modified example correspond to the second portions 61 of the semiconductor device A1 formed in a dotted line shape.
[0063] This modification also allows the first semiconductor element 5A to be bonded more appropriately. As can be understood from this modification, the first bonding sheet 6A may have a configuration including a plurality of second portions 61.
[0064] Second Modification of First Embodiment: Figure 17 shows a second modification of the semiconductor device A1. In this modification, the semiconductor device A12 has four second portions 61 in the first bonding sheet 6A. The four second portions 61 are in contact with four corners of the first bonding sheet 6A, respectively. A portion of the first portion 60 is interposed between adjacent second portions 61.
[0065] This modification also allows the first semiconductor element 5A to be bonded more appropriately. As can be understood from this modification, the first bonding sheet 6A may have a configuration including a plurality of second portions 61.
[0066] Third Modification of First Embodiment: Figure 18 shows a third modification of the semiconductor device A1. In the semiconductor device A13 of this modification, the first bonding sheet 6A has a plurality of second portions 61. The second portions 61 contact the edges of the first bonding sheet 6A. However, the second portions 61 are spaced apart from the corners of the first bonding sheet 6A. In this example, four second portions 61 are arranged so as to individually contact the center portions of the four edges of the first bonding sheet 6A.
[0067] This modification also allows the first semiconductor element 5A to be more appropriately bonded. As can be understood from this modification, the second portion 61 may be configured away from the corner of the first bonding sheet 6A.
[0068] Second Embodiment: Figure 19 shows a semiconductor device according to a second embodiment of the present disclosure. In a semiconductor device A2 of this embodiment, a first bonding sheet 6A has two second portions 61. The two second portions 61 are spaced apart from each other in the second direction x and each contacts two parallel edges of the first bonding sheet 6A extending in the third direction y. The two second portions 61 contact four corners of the first bonding sheet 6A.
[0069] This embodiment also allows the first semiconductor element 5A to be more appropriately bonded. As can be understood from this embodiment, there is no limitation on the number of the second portions 61. By disposing the two second portions 61 separately on both sides of the first bonding sheet 6A in the second direction x, the first bonding sheet 6A can be temporarily bonded in a more balanced manner.
[0070] 20 shows a first modification of the semiconductor device A2. In the semiconductor device A21 of this modification, the first bonding sheet 6A has two second portions 61. The two second portions 61 are spaced apart from each other in the second direction x and are respectively in contact with two parallel edges of the first bonding sheet 6A extending in the third direction y. Meanwhile, the two second portions 61 are spaced apart from the four corners of the first bonding sheet 6A.
[0071] This modification also allows the first semiconductor element 5A to be more appropriately bonded. As can be understood from this modification, the second portion 61 may be configured away from the corner of the first bonding sheet 6A.
[0072] 21 and 22 show a semiconductor device according to a third embodiment of the present disclosure. In a semiconductor device A3 of this embodiment, a second portion 61 has a portion that overlaps with a first semiconductor element 5A and a portion that does not overlap with the first semiconductor element 5A when viewed in the first direction z.
[0073] In the illustrated example, the second portion 61 has a rectangular ring shape as viewed in the first direction z. Two portions of the second portion 61 extending along the second direction x each partially overlap with the first semiconductor element 5A as viewed in the first direction z. Unlike the illustrated example, only one of the two portions of the second portion 61 extending along the second direction x may overlap with the first semiconductor element 5A as viewed in the first direction z.
[0074] This embodiment also allows the first semiconductor element 5A to be bonded more appropriately. As can be understood from this embodiment, the second portion 61 may partially overlap the first semiconductor element 5A. By limiting the portion of the second portion 61 that overlaps with the first semiconductor element 5A to a small area, the first semiconductor element 5A can be bonded appropriately.
[0075] 23 and 24 show a first modified example of the semiconductor device A3. In the semiconductor device A31 of this modified example, the first bonding sheet 6A has two second portions 61. One of the second portions 61 has a configuration similar to that of the second portion 61 of the semiconductor device A3. The other second portion 61 entirely overlaps the first semiconductor element 5A when viewed in the first direction z. This second portion 61 is smaller in size than the rectangular-annular second portion 61. This second portion 61 may overlap the center of the first semiconductor element 5A when viewed in the first direction z.
[0076] This modification also makes it possible to more appropriately bond the first semiconductor element 5A. As can be understood from this embodiment, the configuration in which the second portion 61 and the first semiconductor element 5A overlap can be set in various ways.
[0077] 25 and 26 show another example of a holder used in the method for manufacturing a semiconductor device according to the present disclosure. The holder B2 in this example has four protrusions 92. The holder B2 is configured to enable temporary bonding of the first bonding sheet 6A of the semiconductor device A13 shown in FIG. 18, for example.
[0078] The protrusion 92 of this modified example has an abutment surface 921 and an inclined surface 922. The abutment surface 921 has the configuration described above. The inclined surface 922 is located outward from the abutment surface 921 in the second direction x or the third direction y. The inclined surface 922 is inclined so that the more it extends outward in the second direction x or the third direction y, the closer it is to the z2 side in the first direction z.
[0079] The holder B2 can temporarily bond, for example, the first bonding sheet 6A of the semiconductor device A13 shown in Fig. 18. As shown in Fig. 26, when holding the first bonding sheet 6A or the second bonding sheet 6B placed in the recess of the tray Tr, the provision of the inclined surface 922 can prevent the holder B2 from interfering with the tray Tr.
[0080] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are not limited to the above-described embodiment. The specific configurations of the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure can be freely modified in various ways.
[0081] Supplementary Note 1. A semiconductor device (A1) comprising: a support (1); a first semiconductor element (5A) supported by the support (1); and a first bonding sheet (6A) interposed between the support (1) and the first semiconductor element (5A), wherein the first bonding sheet (6A) has: a first portion (60) including a portion overlapping with the first semiconductor element (5A) when viewed in a first direction (z) that is the thickness direction of the support (1); and a second portion (61) including a portion not overlapping with the first semiconductor element (5A) when viewed in the first direction (z) and having a thickness in the first direction (z) smaller than that of the first portion (60). Supplementary Note 2. The semiconductor device (A1) according to Supplementary Note 1, wherein the second portion (61) does not entirely overlap with the first semiconductor element (5A) when viewed in the first direction (z). Supplementary Note 3. The semiconductor device (A1) according to Appendix 1 or 2, wherein the first bonding sheet (6A) is rectangular when viewed in the first direction (z). Appendix 4. The semiconductor device (A2) according to Appendix 3, wherein the second portion (61) is in contact with two parallel edges of the first bonding sheet (6A). Appendix 5. The semiconductor device (A1) according to Appendix 3, wherein the second portion (61) is in contact with all edges of the first bonding sheet (6A). Appendix 6. The semiconductor device (A1) according to Appendix 5, wherein the second portion (61) is rectangular and annular when viewed in the first direction (z). Appendix 7. The semiconductor device (A1) according to Appendix 3, wherein the second portion (61) is in contact with a corner of the first bonding sheet (6A). Appendix 8. The semiconductor device (A11) according to Appendix 3, wherein the second portion (61) is spaced from the corner of the first bonding sheet (6A). Appendix 9. The semiconductor device (A1) according to Appendix 1, wherein the second portion (61) has a portion overlapping with the first semiconductor element (5A) when viewed in the first direction (z). Appendix 10. The semiconductor device (A1) according to any one of Appendixes 1 to 9, wherein the first portion (60) contacts an edge of the first bonding sheet (6A). Appendix 11. The semiconductor device (A1) according to any one of Appendixes 1 to 10, wherein the first bonding sheet (6A) has a metal layer containing Ag (silver). Appendix 12. The semiconductor device (A1) according to Appendix 11, wherein the first bonding sheet (6A) has a base layer containing aluminum (Al).Appendix 13. The semiconductor device (A1) according to any one of Appendixes 1 to 12, wherein the support (1) has a third main surface metal layer (3A), and the first semiconductor element (5A) is bonded to the third main surface metal layer (3A) via the first bonding sheet (6A). Appendix 14. A method for manufacturing a semiconductor device (A1), comprising: a step of temporarily bonding a first bonding sheet (6A) to a support (1); and a step of bonding a first semiconductor element (5A) to the support (1) via the first bonding sheet (6A), wherein in the step of temporarily bonding the first bonding sheet (6A), a portion of the first bonding sheet (6A) is pressed toward the support (1) in a first direction (z) to form a first portion (60) that is a non-pressurized portion of the first bonding sheet (6A) and a second portion (61) that is pressed and has a thickness in the first direction (z) smaller than that of the first portion (60), and in the step of bonding the first semiconductor element (5A), at least a portion of the first semiconductor element (5A) and the first portion (60) overlap with each other, and at least a portion of the first semiconductor element (5A) and the second portion (61) do not overlap with each other, as viewed in the first direction (z). Supplementary Note 15. A method for manufacturing a semiconductor device (A1) according to Supplementary Note 14, wherein solid-state diffusion bonding is used in the step of bonding the first semiconductor element (5A). Supplementary Note 16. A vehicle (C1) comprising: a drive source (932); and the semiconductor device (A1) according to any one of Supplements 1 to 13, wherein the semiconductor device (A1) is electrically connected to the drive source (932).
[0082] A1, A11, A12, A13, A2, A21, A3, A31: semiconductor device 1: support 2A: first main surface metal layer 2B: second main surface metal layer 3A: third main surface metal layer 3B: fourth main surface metal layer 4A: bonding layer 4B: bonding layer 5A: first semiconductor element 5B: second semiconductor element 6A: first bonding sheet 6B: second bonding sheet 7A: positive electrode input terminal 7B: output terminal 7C: negative electrode input terminal 7D: control terminal 7E: control terminal 8A: first wire 8B: second wire 8C: third wire 8D: fourth wire 9: sealing resin 10: insulating layer 11: back surface metal layer 50: element body 51: drain electrode 52: source electrode 53: gate electrode 54: source sense electrode 60: first part 61: second part 91: Main surface 92: Convex portion 93: Suction hole 98: Base 910: On-board charger 920: Storage battery 921: Contact surface 922: Inclined surface 930: Drive system 931: Inverter 932: Drive source 981: Suction hole B1, B2: Holder C1: Vehicle Tr: Tray dz: Height t0, t1: Thickness x: Second direction y: Third direction z: First direction
Claims
1. Support and A first semiconductor element supported on the aforementioned support, The system comprises a first bonding sheet interposed between the support and the first semiconductor element, A semiconductor device comprising: a first bonding sheet having a first portion that overlaps with the first semiconductor element when viewed in a first direction which is the thickness direction of the support; and a second portion that does not overlap with the first semiconductor element when viewed in a first direction and is thinner in the first direction than the first portion.
2. The semiconductor device according to claim 1, wherein the second part, when viewed in the first direction, does not overlap entirely with the first semiconductor element.
3. The semiconductor device according to claim 1 or 2, wherein the first bonding sheet is rectangular in shape when viewed in the first direction.
4. The semiconductor device according to claim 3, wherein the second part is in contact with two mutually parallel edges of the first bonding sheet.
5. The semiconductor device according to claim 3, wherein the second part is in contact with all edges of the first bonding sheet.
6. The semiconductor device according to claim 5, wherein the second part is rectangular and annular when viewed in the first direction.
7. The semiconductor device according to claim 3, wherein the second part is in contact with the corner of the first bonding sheet.
8. The semiconductor device according to claim 3, wherein the second part is separated from the corner of the first bonding sheet.
9. The semiconductor device according to claim 1, wherein the second part has a portion that overlaps with the first semiconductor element when viewed in the first direction.
10. The semiconductor device according to claim 1 or 2, wherein the first part is in contact with the edge of the first bonding sheet.
11. The semiconductor device according to claim 1 or 2, wherein the first bonding sheet has a metal layer containing Ag.
12. The semiconductor device according to claim 11, wherein the first bonding sheet has a substrate layer containing Al.
13. The support has a third main surface metal layer, The semiconductor device according to claim 1 or 2, wherein the first semiconductor element is bonded to the third main surface metal layer via a first bonding sheet.
14. The process involves temporarily bonding the first bonding sheet to the support, The process includes the step of bonding a first semiconductor element to the support via the first bonding sheet, In the step of temporarily joining the first bonding sheet, a portion of the first bonding sheet is pressed toward the support in a first direction, thereby forming a first portion which is an unpressurized portion and a second portion which is thinner in the first direction than the first portion due to the pressurization. A method for manufacturing a semiconductor device, wherein, in the step of joining the first semiconductor element, at least a portion of the first semiconductor element and the first part overlap when viewed in the first direction, and at least a portion of the first semiconductor element and the second part do not overlap.
15. The method for manufacturing a semiconductor device according to claim 14, wherein a solid-phase diffusion bonding is used in the step of bonding the first semiconductor element.