Semiconductor device

Abstract

This semiconductor device comprises: a main transistor that has a main surface on which a main source electrode and a main gate electrode are formed; and a sub-transistor at least a part of which is disposed over the main gate electrode. The sub-transistor has a sub-drain electrode electrically connected to the main gate electrode, and a sub-source electrode electrically connected to the main source electrode.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a switch control device connected to the gate of a high-side switch. This switch control device has an active Miller clamp function that suppresses an increase in the gate potential of the high-side switch when the low-side switch is turned on.

[0003] JP 2012-257421 A

[0004] [Summary] However, if the conductive path between the gate of the high-side switch and the switch control device becomes long, there is a risk that the active Miller clamp function will be degraded due to the inductance caused by the length of the conductive path.

[0005] A semiconductor device according to one embodiment of the present disclosure includes a main transistor having a main surface on which a main source electrode and a main gate electrode are formed, and a sub-transistor at least a portion of which is arranged above the main gate electrode, the sub-transistor having a sub-drain electrode electrically connected to the main gate electrode and a sub-source electrode electrically connected to the main source electrode.

[0006] FIG. 1 is a schematic perspective view of a semiconductor device of a first embodiment. FIG. 2 is a schematic plan view of the semiconductor device of FIG. 1. FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. 2. FIG. 4 is a schematic plan view of a main transistor and a sub-transistor in the semiconductor device of FIG. 2. FIG. 5 is a schematic cross-sectional view of the main transistor and the sub-transistor taken along line F5-F5 in FIG. 4. FIG. 6 is a schematic circuit diagram of the semiconductor device of FIG. 1. FIG. 7 is a schematic plan view of a semiconductor device of a second embodiment. FIG. 8 is a schematic plan view of a main transistor, a sub-transistor, and a clip in the semiconductor device of FIG. 7. FIG. 9 is a schematic cross-sectional view of the main transistor, the sub-transistor, and the clip taken along line F9-F9 in FIG. 8. FIG. 10 is a schematic cross-sectional view of the main transistor, the sub-transistor, and the clip taken along line F10-F10 in FIG. 8. FIG. 11 is a schematic perspective view of a main transistor and a sub-transistor unit in a semiconductor device of a third embodiment. FIG. 12 is a schematic plan view of the main transistor and the sub-transistor unit of FIG. 11. FIG. 13 is a schematic side view of the main transistor and sub-transistor unit of FIG. 11 . FIG. 14 is a schematic plan view of the sub-transistor unit. FIG. 15 is a schematic cross-sectional view of the sub-transistor unit taken along line F15-F15 in FIG. 14 . FIG. 16 is a schematic plan view of a semiconductor device of a third embodiment. FIG. 17 is a schematic perspective view of a semiconductor device of a fourth embodiment. FIG. 18 is a schematic perspective view of the semiconductor device of FIG. 17 with the sealing member omitted. FIG. 19 is a schematic perspective view of the semiconductor device of FIG. 18 with the first to third connection wirings and source connection wiring omitted. FIG. 20 is a schematic plan view of the semiconductor device of FIG. 18 . FIG. 21 is a schematic plan view of an enlarged view of the main transistor and its periphery in the semiconductor device of FIG. 20 . FIG. 22 is a schematic cross-sectional view of the semiconductor device taken along line F22-F22 in FIG. 20 . FIG. 23 is a schematic cross-sectional view of the semiconductor device taken along line F23-F23 in FIG. 20 . Fig. 24 is a schematic cross-sectional view of the semiconductor device taken along line F24-F24 in Fig. 20. Fig. 25 is a schematic plan view showing an enlarged view of one sub-transistor and its periphery in the semiconductor device of Fig. 20.26 is a schematic plan view showing an enlarged view of another sub-transistor and its periphery in the semiconductor device of FIG. 20. FIG. 27 is a schematic circuit diagram of the semiconductor device of FIG. 17. FIG. 28 is a schematic plan view of a semiconductor device of a fifth embodiment. FIG. 29 is a schematic plan view showing the internal structure of the semiconductor device of FIG. 28. FIG. 30 is a schematic rear view of the semiconductor device of FIG. 28. FIG. 31 is a schematic plan view showing the internal structure of the semiconductor device of FIG. 30. FIG. 32 is a schematic cross-sectional view of the semiconductor device taken along line F32-F32 in FIG. 28. FIG. 33 is a schematic cross-sectional view of the semiconductor device taken along line F33-F33 in FIG. 28. FIG. 34 is a schematic plan view of a semiconductor device of a modified example. FIG. 35 is a schematic plan view showing an enlarged view of a sub-transistor and its periphery in the semiconductor device of the modified example. FIG. 36 is a schematic plan view of a main transistor and a sub-transistor unit in the semiconductor device of the modified example. FIG. 37 is a schematic plan view showing an enlarged view of a main transistor and its periphery in the semiconductor device of the modified example. FIG. 38 is a schematic cross-sectional view of the semiconductor device of the modified example.

[0007] DETAILED DESCRIPTION Hereinafter, several embodiments of semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] First Embodiment A semiconductor device 10 according to a first embodiment will be described with reference to Figures 1 to 6. The semiconductor device 10 according to the first embodiment is a discrete semiconductor.

[0010] [Overall Structure of Semiconductor Device] The overall structure of the semiconductor device 10 will be described with reference to Figures 1 to 3. Figure 1 shows a schematic perspective structure of the semiconductor device 10. Figure 2 shows a schematic planar structure of the semiconductor device 10. In Figures 1 and 2, a sealing member 60, which will be described later, is shown by a two-dot chain line to show the internal structure of the semiconductor device 10. Figure 3 shows a schematic cross-sectional structure of the semiconductor device 10 taken along line F3-F3 in Figure 2. Note that the term "planar view" used in this disclosure refers to viewing the semiconductor device 10 in the Z direction of the X, Y and Z axes, which are orthogonal to each other, in Figure 1.

[0011] 1, the semiconductor device 10 includes a main transistor 20, a sub-transistor 40, first to fifth frames 51 to 55 that form external terminals, and a sealing member 60. The sealing member 60 seals the main transistor 20 and the sub-transistor 40 and also partially seals the first to fifth frames 51 to 55. The first to fifth frames 51 to 55 protrude from the sealing member 60 to the outside.

[0012] The sealing member 60 is formed in a rectangular flat plate shape with its thickness direction in the Z direction. The sealing member 60 includes a sealing front surface 61 and a sealing back surface 62 facing opposite each other in the Z direction, and first to fourth sealing side surfaces 63 to 66 as four sealing side surfaces connecting the sealing front surface 61 and the sealing back surface 62. The first sealing side surface 63 and the second sealing side surface 64 constitute both end surfaces of the sealing member 60 in the X direction. The third sealing side surface 65 and the fourth sealing side surface 66 constitute both end surfaces of the sealing member 60 in the Y direction. The sealing member 60 is formed from an insulating material. In one example, a black epoxy resin is used as the insulating material. In this disclosure, the direction from the sealing back surface 62 toward the sealing front surface 61 in the Z direction is referred to as "upward," and the direction from the sealing front surface 61 toward the sealing back surface 62 is referred to as "downward."

[0013] The first to fifth frames 51 to 55 protrude from the third sealing side surface 65 to the outside of the sealing member 60. The first to fifth frames 51 to 55 are formed of a conductive material. In one example, the conductive material is a material containing at least one of aluminum (Al), copper (Cu), titanium (Ti), and nickel (Ni).

[0014] The first frame 51 includes a die pad 51A supporting the main transistor 20 and a first lead 51B. In one example, the die pad 51A and the first lead 51B are integrated. The die pad 51A is electrically connected to a main drain electrode 33 (described later) of the main transistor 20. The die pad 51A is formed in a rectangular flat plate shape with its thickness direction in the Z direction. As shown in FIG. 3 , the die pad 51A is exposed from the sealing back surface 62. As shown in FIG. 2 , the first lead 51B extends from an end of the die pad 51A closer to the first sealing side surface 63 in the X direction and an end of the die pad 51A closer to the third sealing side surface 65 in the Y direction toward the third sealing side surface 65. In other words, the first lead 51B is formed across the third sealing side surface 65. Therefore, the first lead 51B includes a first inner lead portion sealed in the sealing member 60 and a first outer lead portion protruding from the sealing member 60. The first lead 51B constitutes an external terminal. Since the die pad 51A is electrically connected to the main drain electrode 33 of the main transistor 20, the first lead 51B forms a main drain terminal.

[0015] The second to fifth frames 52 to 55 are arranged closer to the third sealing side surface 65 than the die pad 51A in a plan view. The second to fifth frames 52 to 55 are arranged closer to the second sealing side surface 64 than the first lead 51B. The second to fifth frames 52 to 55 are arranged side by side in the X direction. In one example, the second frame 52, the third frame 53, the fourth frame 54, and the fifth frame 55 are arranged in this order from the first sealing side surface 63 toward the second sealing side surface 64.

[0016] The second frame 52 is electrically connected to a main source electrode 31 (described later) of the main transistor 20. The second frame 52 includes a second pad 52A and a second lead 52B. In one example, the second pad 52A and the second lead 52B are integrated. The second pad 52A is provided within the sealing member 60. The second lead 52B is formed across the third sealing side surface 65. Therefore, the second lead 52B includes a second inner lead portion sealed in the sealing member 60 and a second outer lead portion protruding from the sealing member 60. The second lead 52B constitutes a main source terminal as an external terminal.

[0017] The third frame 53 is electrically connected to a sub-gate electrode 44 (described later) of the sub-transistor 40. The third frame 53 includes a third pad 53A and a third lead 53B. In one example, the third pad 53A and the third lead 53B are integrated. The third pad 53A is provided within the sealing member 60. The third lead 53B is formed across the third sealing side surface 65. Therefore, the third lead 53B includes a third inner lead portion sealed in the sealing member 60 and a third outer lead portion protruding from the sealing member 60. The third lead 53B constitutes a sub-gate terminal as an external terminal.

[0018] The fourth frame 54 is electrically connected to a second main gate electrode 32B (described later) of the main transistor 20. The fourth frame 54 includes a fourth pad 54A and a fourth lead 54B. In one example, the fourth pad 54A and the fourth lead 54B are integrated. The fourth pad 54A is provided within the sealing member 60. The fourth lead 54B is formed across the third sealing side surface 65. Therefore, the fourth lead 54B includes a fourth inner lead portion sealed in the sealing member 60 and a fourth outer lead portion protruding from the sealing member 60. The fourth lead 54B constitutes a main gate terminal as an external terminal.

[0019] The fifth frame 55 is electrically connected to a second sense / source electrode 34B (described later) of the main transistor 20. The fifth frame 55 includes a fifth pad 55A and a fifth lead 55B. In one example, the fifth pad 55A and the fifth lead 55B are integrated. The fifth pad 55A is provided within the sealing member 60. The fifth lead 55B is formed across the third sealing side surface 65. Therefore, the fifth lead 55B includes a fifth inner lead portion sealed in the sealing member 60 and a fifth outer lead portion protruding from the sealing member 60. The fifth lead 55B constitutes a sense / source terminal as an external terminal.

[0020] 3, the main transistor 20 is bonded to the die pad 51A by a conductive bonding material SD, which may be, for example, a solder paste or an Ag (silver) paste.

[0021] As shown in FIGS. 2 and 3 , the main transistor 20 is formed in a rectangular plate shape with its thickness direction aligned in the Z direction. The main transistor 20 has a main front surface 21, a main back surface 22 facing the opposite side from the main front surface 21 in the Z direction, and first to fourth main side surfaces 23 to 26 as four side surfaces connecting the main front surface 21 and the main back surface 22. The main front surface 21 faces the same side as the sealing front surface 61. The main back surface 22 faces the same side as the sealing back surface 62. The first main side surface 23 and the second main side surface 24 constitute both end surfaces of the main transistor 20 in the X direction. The first main side surface 23 faces the same side as the first sealing side surface 63, and the second main side surface 24 faces the same side as the second sealing side surface 64. The third main side surface 25 and the fourth main side surface 26 constitute both end surfaces of the main transistor 20 in the Y direction. The third main side surface 25 faces the same side as the third sealing side surface 65 , and the fourth main side surface 26 faces the same side as the fourth sealing side surface 66 .

[0022] The main transistor 20 is configured as, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In one example, the main transistor 20 is a SiC (Silicon Carbide) MOSFET. However, the main transistor 20 may be a Si (Silicon) MOSFET. The main transistor 20 is formed in a rectangular plate shape with the thickness direction in the Z direction. In one example, the main transistor 20 is formed in a rectangular shape with the longitudinal direction in the Y direction and the lateral direction in the X direction in a plan view.

[0023] 2 and 3, the main transistor 20 includes a main source electrode 31 and a main gate electrode 32 formed on the main front surface 21, and a main drain electrode 33 formed on the main back surface 22. Also, as shown in FIG. 2, the main transistor 20 includes a first sense source electrode 34A and a second sense source electrode 34B formed on the main front surface 21.

[0024] The main source electrode 31 is formed over most of the main surface 21. In one example, the main source electrode 31 is formed in a rectangular shape in a plan view. The main gate electrode 32, the first sense source electrode 34A, and the second sense source electrode 34B are arranged closer to the third main side surface 25 than the main source electrode 31. The main gate electrode 32, the first sense source electrode 34A, and the second sense source electrode 34B are arranged at the same position as each other in the Y direction and spaced apart from each other in the X direction. The main gate electrode 32 is arranged between the first sense source electrode 34A and the second sense source electrode 34B in the X direction. The first sense source electrode 34A is arranged closer to the first main side surface 23 than the main gate electrode 32. The second sense source electrode 34B is arranged closer to the second main side surface 24 than the main gate electrode 32. Both the first sense source electrode 34A and the second sense source electrode 34B are formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view.

[0025] The main gate electrode 32 includes a first main gate electrode 32A and a second main gate electrode 32B. The first main gate electrode 32A and the second main gate electrode 32B are arranged in alignment with each other in the Y direction and spaced apart from each other in the X direction. The first main gate electrode 32A is arranged closer to the first sense source electrode 34A, and the second main gate electrode 32B is arranged closer to the second sense source electrode 34B. In one example, both the first main gate electrode 32A and the second main gate electrode 32B are formed in a square shape in a plan view.

[0026] The shapes of the first main gate electrode 32A, the second main gate electrode 32B, the first sense source electrode 34A, and the second sense source electrode 34B in a planar view can be changed as desired. In one example, the shapes of both the first main gate electrode 32A and the second main gate electrode 32B in a planar view may be rectangular.

[0027] 2 and 3, a passivation layer 35 is formed on the main surface 21. The passivation layer 35 is a layer that protects the main surface 21. The passivation layer 35 is made of, for example, silicon nitride (SiN), silicon oxide (SiO ２ ), and polyimide (PI).

[0028] As shown in FIG. 4 , the passivation layer 35 includes first to third source openings 35A to 35C, a first gate opening 35D, and a second gate opening 35E. The first to third source openings 35A to 35C are spaced apart from one another in a plan view. The portions exposed by the first to third source openings 35A to 35C respectively constitute the main source electrode 31, the first sense source electrode 34A, and the second sense source electrode 34B. More specifically, a source electrode layer 36 is formed on the main surface 21. The passivation layer 35 is formed on the source electrode layer 36, and the first to third source openings 35A to 35C are formed thereon. The portion of the source electrode layer 36 exposed by the first source opening 35A constitutes the main source electrode 31. The portion of the source electrode layer 36 exposed by the second source opening 35B constitutes the first sense source electrode 34A. A portion of the source electrode layer 36 exposed by the third source opening 35C constitutes the second sense source electrode 34B. In other words, the passivation layer 35 includes a first source partition portion 35F that separates the first source opening 35A and the second source opening 35B, and a second source partition portion 35G that separates the first source opening 35A and the third source opening 35C.

[0029] The first gate opening 35D and the second gate opening 35E are spaced apart from each other in a plan view. The portions exposed by the first gate opening 35D and the second gate opening 35E constitute the first main gate electrode 32A and the second main gate electrode 32B, respectively. More specifically, a gate electrode layer 37 is formed on the main surface 21. A passivation layer 35 is formed on the gate electrode layer 37, and the first gate opening 35D and the second gate opening 35E are formed thereon. The portion of the gate electrode layer 37 exposed by the first gate opening 35D constitutes the first main gate electrode 32A. The portion of the gate electrode layer 37 exposed by the second gate opening 35E constitutes the second main gate electrode 32B. The first gate opening 35D and the second gate opening 35E are spaced apart from each other in the X direction. In other words, the passivation layer 35 includes a gate partition portion 35H that separates the first gate opening 35D and the second gate opening 35E.

[0030] 3, the main drain electrode 33 of the main transistor 20 is formed over the entire main back surface 22. The main drain electrode 33 is bonded to the die pad 51A by a conductive bonding material SD. Therefore, the main drain electrode 33 is electrically connected to the die pad 51A. In other words, the first lead 51B integrated with the die pad 51A is electrically connected to the main drain electrode 33. Therefore, the first lead 51B constitutes a main drain terminal.

[0031] 2, the main source electrode 31 and the second pad 52A of the second frame 52 are connected by a main source clip CP. This electrically connects the main source electrode 31 and the second pad 52A. Therefore, the second lead 52B integrated with the second pad 52A is electrically connected to the main source electrode 31. Therefore, the second lead 52B constitutes a main source terminal.

[0032] The main source clip CP is formed of a metal plate in an L-shape in plan view, and is made of a metal material such as Cu or Al. The main source clip CP is joined to the main source electrode 31 and the second pad 52A by, for example, ultrasonic welding or a conductive bonding material SD.

[0033] The second main gate electrode 32B and the fourth pad 54A of the fourth frame 54 are connected by a wire W1. This electrically connects the second main gate electrode 32B and the fourth pad 54A. Therefore, the fourth lead 54B integrated with the fourth pad 54A is electrically connected to the second main gate electrode 32B. Therefore, the fourth lead 54B constitutes a main gate terminal.

[0034] The second sense source electrode 34B and the fifth pad 55A of the fifth frame 55 are connected by a wire W2. This electrically connects the second sense source electrode 34B and the fifth pad 55A. Therefore, the fifth lead 55B integrated with the fifth pad 55A is electrically connected to the second sense source electrode 34B. Therefore, the fifth lead 55B constitutes a sense source terminal.

[0035] A sub-transistor 40 is disposed on the first main gate electrode 32A. The sub-transistor 40 is bonded to the first main gate electrode 32A by a conductive bonding material SD. The sub-transistor 40 is an active clamp transistor. The sub-transistor 40 is configured as, for example, a MOSFET. In one example, the sub-transistor 40 is configured as a SiMOSFET. The sub-transistor 40 is formed in a rectangular plate shape with the thickness direction in the Z direction. In one example, the sub-transistor 40 is formed in a square shape in a plan view. The sub-transistor 40 may be formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. Alternatively, the sub-transistor 40 may be formed in a rectangular shape with the Y direction as the longitudinal direction and the X direction as the lateral direction in a plan view.

[0036] 5 , the sub-transistor 40 has a sub-surface 41 and a sub-back surface 42 that face opposite to each other in the Z direction. The sub-surface 41 faces the same side as the main surface 21 of the main transistor 20. The sub-back surface 42 faces the same side as the main back surface 22 of the main transistor 20. The sub-transistor 40 includes a sub-source electrode 43 and a sub-gate electrode 44 formed on the sub-surface 41, and a sub-drain electrode 45 formed on the sub-back surface 42.

[0037] 4, the sub-source electrode 43 is formed over most of the sub-surface 41. The sub-gate electrode 44 is formed at one of the four corners of the sub-surface 41. The sub-gate electrode 44 is disposed on the sub-surface 41 closer to the third frame 53 (see FIG. 2). As shown in FIG. 5, the sub-drain electrode 45 is formed over the entire surface of the sub-back surface 42.

[0038] The sub-drain electrode 45 is joined to the first main gate electrode 32A by a conductive bonding material SD, thereby electrically connecting the sub-drain electrode 45 to the first main gate electrode 32A. The gate partition wall 35H prevents the conductive bonding material SD from penetrating into the second main gate electrode 32B.

[0039] The sub-source electrode 43 and the first sense source electrode 34A are connected by a wire W3. This electrically connects the sub-source electrode 43 to the first sense source electrode 34A. Because the first sense source electrode 34A is electrically connected to the main source electrode 31 by the common source electrode layer 36, it can be said that the sub-source electrode 43 is electrically connected to the main source electrode 31. Therefore, it can be said that the main source electrode 31 and the sub-source electrode 43 are electrically connected by the wire W3. Here, the wire W3 is an example of a "connecting member".

[0040] 2, the sub-gate electrode 44 and the third pad 53A of the third frame 53 are connected by a wire W4. This electrically connects the sub-gate electrode 44 to the third pad 53A. Therefore, the third lead 53B integrated with the third pad 53A is electrically connected to the sub-gate electrode 44. Therefore, the third lead 53B forms a sub-gate terminal.

[0041] The wires W1 to W4 are made of a conductive material such as gold (Au), Cu, Al, etc. The wires W1 to W4 are bonding wires formed by, for example, a wire bonding device.

[0042] [Circuit Configuration of Semiconductor Device] The circuit configuration of the semiconductor device 10 described above is shown in Figure 6. As shown in Figure 6, the main transistor 20 and the sub-transistor 40 are electrically connected within the semiconductor device 10. More specifically, the sub-drain electrode 45 of the sub-transistor 40 is electrically connected to the main gate electrode 32 of the main transistor 20. The sub-source electrode 43 of the sub-transistor 40 is electrically connected to the main source electrode 31 of the main transistor 20.

[0043] The main drain electrode 33 of the main transistor 20 is electrically connected to the first lead 51B, which serves as the main drain terminal. The main source electrode 31 is electrically connected to the second lead 52B, which serves as the main source terminal. The second sense source electrode 34B is electrically connected to the fifth lead 55B, which serves as the sense source terminal. Therefore, the sub-source electrode 43 is electrically connected to the fifth lead 55B. The main gate electrode 32 is electrically connected to the fourth lead 54B, which serves as the main gate terminal. Therefore, the sub-drain electrode 45 is electrically connected to the fourth lead 54B. The sub-gate electrode 44 of the sub-transistor 40 is electrically connected to the third lead 53B, which serves as the sub-gate terminal.

[0044] According to the semiconductor device 10, by turning on the sub-transistor 40 when the main transistor 20 is in an off state, the gate-source voltage Vgs of the main transistor 20 is forcibly set to approximately 0 V. This makes it possible to suppress the gate-source voltage Vgs of the main transistor 20 from rising.

[0045] [Operation] The operation of the semiconductor device 10 of the first embodiment will be described. The sub-transistor 40 is disposed on the first main gate electrode 32A of the main transistor 20. The sub-drain electrode 45 of the sub-transistor 40 is disposed opposite the first main gate electrode 32A in the Z direction. The sub-drain electrode 45 is bonded to the first main gate electrode 32A by a conductive bonding material SD. This electrically connects the sub-drain electrode 45 and the first main gate electrode 32A. Because the sub-drain electrode 45 and the first main gate electrode 32A are disposed opposite each other in the Z direction, the conduction path between the sub-drain electrode 45 and the first main gate electrode 32A can be shortened compared to a configuration in which the sub-transistor 40 is disposed outside the main transistor 20.

[0046] [Effects] The semiconductor device 10 of the first embodiment has the following effects: (1-1) The semiconductor device 10 includes a main transistor 20 having a main surface 21 on which a main source electrode 31 and a main gate electrode 32 are formed, and a sub-transistor 40 at least a portion of which is disposed above the main gate electrode 32, the sub-transistor 40 having a sub-drain electrode 45 electrically connected to the main gate electrode 32 and a sub-source electrode 43 electrically connected to the main source electrode 31.

[0047] With this configuration, the conduction path between the main gate electrode 32 of the main transistor 20 and the sub-drain electrode 45 of the sub-transistor 40 can be shortened, thereby reducing the inductance caused by the length of this conduction path. This enhances the effect of the sub-transistor 40 in suppressing the rise in the gate-source voltage Vgs of the main gate electrode 32, i.e., enhances the active Miller clamp function. This makes it possible to suppress the occurrence of false turn-on of the main transistor 20.

[0048] (1-2) The sub-transistor 40 includes a sub-surface 41 on which a sub-source electrode 43 is formed, and a sub-back surface 42 facing the opposite side to the sub-surface 41 and on which a sub-drain electrode 45 is formed. The main gate electrode 32 of the main transistor 20 and the sub-drain electrode 45 are joined by a conductive joining material SD.

[0049] According to this configuration, the conductive path between the main gate electrode 32 of the main transistor 20 and the sub-drain electrode 45 of the sub-transistor 40 can be further shortened, thereby further reducing the inductance caused by the length of this conductive path.

[0050] (1-3) The main gate electrode 32 of the main transistor 20 includes a first main gate electrode 32A and a second main gate electrode 32B that are spaced apart from each other in a plan view. The sub-drain electrode 45 of the sub-transistor 40 is joined to the first main gate electrode 32A by a conductive bonding material SD.

[0051] According to this configuration, the main gate electrode 32 can be configured so that it serves as a gate electrode electrically connected to the sub-drain electrode 45 of the sub-transistor 40 and a gate electrode that applies a gate voltage to the main transistor 20. Therefore, the gate voltage can be applied directly to the main transistor 20 via the second main gate electrode 32B without passing through the sub-transistor 40.

[0052] (1-4) The sub-transistor 40 includes a sub-source electrode 43 formed on the sub-surface 41. The first sense source electrode 34A of the main transistor 20 and the sub-source electrode 43 are electrically connected via a wire W3 serving as a connecting member.

[0053] According to this configuration, the conduction path between the sub-source electrode 43 and the first sense source electrode 34A can be made shorter than in a configuration in which the sub-transistor 40 is disposed outside the main transistor 20.

[0054] (1-5) The main transistor 20 includes a passivation layer 35 formed on the main surface 21. The passivation layer 35 includes a first gate opening 35D exposing the first main gate electrode 32A, a second gate opening 35E exposing the second main gate electrode 32B, and a gate partition portion 35H formed between the first gate opening 35D and the second gate opening 35E.

[0055] According to this configuration, the gate partition wall 35H can prevent the conductive bonding material SD that bonds the first main gate electrode 32A and the sub-drain electrode 45 of the sub-transistor 40 from penetrating into the second gate opening 35E. Therefore, it is possible to prevent the conductive bonding material SD from adhering to the second main gate electrode 32B, making it difficult to connect the second main gate electrode 32B and the wire W1.

[0056] 7 to 10, a semiconductor device 10 according to a second embodiment will be described. The semiconductor device 10 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment mainly in the connection structure between the main transistor 20 and the sub-transistor 40. Differences from the first embodiment will be described in detail below, and components common to the first embodiment will be denoted by the same reference numerals and will not be described again.

[0057] FIG. 7 shows a schematic planar structure of the semiconductor device 10. In FIG. 7, the sealing member 60 is indicated by a two-dot chain line to show the internal structure of the semiconductor device 10. FIG. 8 shows a schematic planar structure of the main transistor 20 and the sub-transistor 40. FIG. 9 shows a schematic cross-sectional structure of the semiconductor device 10 taken along line F9-F9 in FIG. 8. FIG. 10 shows a schematic cross-sectional structure of the main transistor 20 and the sub-transistor 40 taken along line F10-F10 in FIG. 8.

[0058] 7 , in the second embodiment, the main gate electrode 32 of the main transistor 20 and the fourth frame 54 are connected by a conductive clip 70. In other words, the semiconductor device 10 includes the conductive clip 70 joined to the main gate electrode 32. The sub-transistor 40 is disposed above the clip 70.

[0059] As described above, the arrangement of the sub-transistors 40 differs from that of the first embodiment, and therefore the configuration of the main gate electrode 32 of the main transistor 20 differs from that of the first embodiment. More specifically, in the main transistor 20 of the second embodiment, the passivation layer 35 does not divide the main gate electrode 32 into a first main gate electrode 32A and a second main gate electrode 32B (both see FIG. 4 ). That is, the main transistor 20 of the second embodiment includes a single main gate electrode 32. As shown in FIG. 8 , the passivation layer 35 includes a gate opening 35J that exposes the main gate electrode 32. In plan view, the opening area of ​​the gate opening 35J is larger than the opening areas of the first gate opening 35D and the second gate opening 35E (both see FIG. 4 ).

[0060] A plate-shaped clip 70 is bonded onto the main gate electrode 32. The clip 70 is made of a metal material such as Cu or Al. In one example, the clip 70 is formed by pressing a metal plate. The clip 70 includes a gate junction portion 71 and a wiring portion 72. In one example, the gate junction portion 71 and the wiring portion 72 are integrated.

[0061] 9 , the gate bond portion 71 is a portion of the clip 70 that bonds to the main gate electrode 32. The gate bond portion 71 is formed, for example, in a flat plate shape that is perpendicular to the Z direction. The gate bond portion 71 is bonded to the main gate electrode 32 by, for example, a conductive bonding material SD. As shown in FIGS. 9 and 10 , the conductive bonding material SD that bonds the gate bond portion 71 to the main gate electrode 32 is prevented from protruding from the gate opening 35J by the passivation layer 35.

[0062] 7 and 9, the wiring portion 72 is a portion that bends and extends upward from the gate bonding portion 71 and is bonded to the fourth pad 54A of the fourth frame 54. As shown in Fig. 7, the wiring portion 72 is formed in a stepped shape in a plan view. Note that the shape of the wiring portion 72 in a plan view can be changed as desired.

[0063] 9 and 10 , the sub-transistor 40 is disposed at the gate junction portion 71 of the clip 70. In other words, the sub-transistor 40 is disposed at a portion of the clip 70 that overlaps with the main gate electrode 32 in a plan view. The sub-transistor 40 is bonded to the gate junction portion 71 by a conductive bonding material SD. As a result, the clip 70 and the sub-drain electrode 45 of the sub-transistor 40 are bonded to each other by the conductive bonding material SD.

[0064] 10, the sub-source electrode 43 of the sub-transistor 40 and the first sense source electrode 34A are electrically connected by a wire W3, as in the first embodiment. Also, as shown in Fig. 7, the sub-gate electrode 44 of the sub-transistor 40 (see Fig. 9) and the third pad 53A of the third frame 53 are electrically connected by a wire W4, as in the first embodiment.

[0065] [Effects] The semiconductor device 10 of the second embodiment has the following effects: (2-1) The semiconductor device 10 includes a conductive clip 70 joined to the main gate electrode 32. The sub-transistor 40 is disposed above the clip 70 with the sub-drain electrode 45 joined to the clip 70.

[0066] With this configuration, both the clip 70 and the sub-drain electrode 45 of the sub-transistor 40 can be electrically connected to one main gate electrode 32. Therefore, for example, there is no need to form two main gate electrodes 32, and the total area of ​​the main source electrode 31, the first sense source electrode 34A, and the second sense source electrode 34B can be increased. In other words, the area of ​​the source electrode layer 36 that constitutes the main source electrode 31, the first sense source electrode 34A, and the second sense source electrode 34B can be increased. In other words, the active area of ​​the main transistor 20 is increased, and the on-resistance can be reduced.

[0067] (2-2) The sub-transistor 40 includes a sub-surface 41 on which a sub-source electrode 43 is formed, and a sub-back surface 42 facing the opposite side to the sub-surface 41 and on which a sub-drain electrode 45 is formed. The clip 70 and the sub-drain electrode 45 are bonded together by a conductive bonding material SD.

[0068] According to this configuration, the conductive path between the sub-drain electrode 45 and the clip 70 can be made shorter than in a configuration in which the sub-drain electrode 45 is formed on the sub-surface 41. Therefore, the conductive path between the sub-drain electrode 45 and the main gate electrode 32 can be made shorter, and the inductance caused by this conductive path can be reduced.

[0069] (2-3) The sub-transistor 40 is disposed in a position of the clip 70 that overlaps with the main gate electrode 32 in plan view. This configuration can further shorten the conductive path between the sub-drain electrode 45 and the main gate electrode 32, thereby further reducing the inductance caused by this conductive path.

[0070] 11 to 16, a semiconductor device 10 according to a third embodiment will be described. The semiconductor device 10 according to the third embodiment differs from the semiconductor device 10 according to the first embodiment mainly in the configurations of the main transistor 20 and the sub-transistor 40 and the connection structure between the main transistor 20 and the sub-transistor 40.

[0071] FIG. 11 shows a schematic perspective structure of the main transistor 20 and a sub-transistor unit 80 (described later) of the semiconductor device 10 of the third embodiment. FIG. 12 shows a schematic planar structure of FIG. 11. FIG. 13 shows a schematic side view structure of FIG. 11. FIG. 14 shows a schematic internal structure of the sub-transistor unit 80. FIG. 15 shows a schematic cross-sectional structure of the sub-transistor unit 80 taken along line F15-F15 in FIG. 14. FIG. 16 shows a schematic planar structure of the semiconductor device 10 of the third embodiment. Note that in FIG. 16, the sealing member 60 is indicated by a two-dot chain line to show the internal structure of the semiconductor device 10.

[0072] As shown in FIG. 11 , the main gate electrode 32, first sense source electrode 34A, and second sense source electrode 34B formed on the main surface 21 of the main transistor 20 of the third embodiment are disposed closer to the third main side surface 25 than the main source electrode 31 in the Y direction. The main gate electrode 32 is disposed at the center of the main surface 21 in the X direction. The first sense source electrode 34A is disposed closer to the first main side surface 23 than the main gate electrode 32. The second sense source electrode 34B is disposed closer to the second main side surface 24 than the main gate electrode 32. In the third embodiment, the first sense source electrode 34A is formed in a square shape in a plan view. Both the main gate electrode 32 and the second sense source electrode 34B are formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. Note that the shapes of the main gate electrode 32, the first sense source electrode 34A, and the second sense source electrode 34B in a plan view can be changed as desired.

[0073] The semiconductor device 10 includes a sub-transistor unit 80 including a sub-transistor 40 (see FIG. 14). The sub-transistor unit 80 is disposed above the main transistor 20. The configuration of the sub-transistor unit 80 will be described below.

[0074] 13 , the sub-transistor unit 80 includes a first drain wiring 81, a second drain wiring 82, a source wiring 83, and a gate wiring 84, and a sub-sealing member 90 that seals the sub-transistor 40 without sealing the main transistor 20. The first drain wiring 81, the second drain wiring 82, the source wiring 83, and the gate wiring 84 include portions that are exposed from the sub-sealing member 90. The first drain wiring 81, the second drain wiring 82, the source wiring 83, and the gate wiring 84 include one or more appropriately selected from the group consisting of Ti (titanium), TiN (titanium nitride), Au, Ag, Cu, Al, and W (tungsten), for example.

[0075] The sub-sealing member 90 is made of an insulating material, such as epoxy resin. That is, the sub-sealing member 90 may be made of the same material as the sealing member 60. The sub-sealing member 90 is formed in a rectangular flat plate shape with the thickness direction aligned in the Z direction. As shown in FIG. 12 , the sub-sealing member 90 is formed in a rectangular shape with the longitudinal direction aligned in the X direction and the lateral direction aligned in the Y direction in a plan view.

[0076] 12 and 13 , the sub sealing member 90 includes a sub sealing surface 91 and a sub sealing back surface 92 facing opposite each other in the Z direction, and first to fourth sub sealing side surfaces 93 to 96 as four side surfaces connecting the sub sealing surface 91 and the sub sealing back surface 92. The sub sealing surface 91 faces the same side as the main surface 21 of the main transistor 20, and the sub sealing back surface 92 faces the same side as the main back surface 22 of the main transistor 20. The first sub sealing side surface 93 and the second sub sealing side surface 94 constitute both end surfaces of the sub sealing member 90 in the X direction. The first sub sealing side surface 93 faces the same side as the second main side surface 24 of the main transistor 20, and the second sub sealing side surface 94 faces the same side as the first main side surface 23 of the main transistor 20. The third sub sealing side surface 95 and the fourth sub sealing side surface 96 constitute both end surfaces of the sub sealing member 90 in the Y direction. The third sub-encapsulation side surface 95 faces the same side as the third main side surface 25 of the main transistor 20 , and the fourth sub-encapsulation side surface 96 faces the same side as the fourth main side surface 26 of the main transistor 20 .

[0077] 15 , both the first drain wiring 81 and the source wiring 83 are exposed from the sub-sealing back surface 92. The first drain wiring 81 and the source wiring 83 are arranged at the same position as each other in the Z direction. The first drain wiring 81 and the source wiring 83 are also arranged at the same position as each other in the Y direction and spaced apart from each other in the X direction. The first drain wiring 81 is arranged closer to the first sub-sealing side surface 93 than the source wiring 83.

[0078] 14 , the first drain wiring 81 is a wiring on which the sub-transistor 40 is disposed. In one example, the first drain wiring 81 is formed in a rectangular shape with the X direction as the longitudinal direction and the Y direction as the lateral direction in a plan view. As shown in FIG. 15 , the sub-transistor 40 is bonded to the first drain wiring 81 by, for example, a conductive bonding material SD. More specifically, the sub-drain electrode 45 of the sub-transistor 40 is bonded to the first drain wiring 81 by the conductive bonding material SD. Therefore, the sub-drain electrode 45 is electrically connected to the first drain wiring 81.

[0079] In the third embodiment, the shapes and arrangement of the sub-source electrode 43 and the sub-gate electrode 44 formed on the sub-surface 41 of the sub-transistor 40 differ from those in the first embodiment. More specifically, the sub-source electrode 43 is formed over most of the sub-surface 41. The sub-source electrode 43 includes a recess that opens toward the source wiring 83 at one of both ends of the sub-surface 41 in the X direction, which is closer to the source wiring 83, in a plan view. The recess is located at the center of the sub-source electrode 43 in the Y direction. The sub-gate electrode 44 is located within the recess of the sub-source electrode 43 in a plan view. The sub-gate electrode 44 is formed in a rectangular shape in a plan view.

[0080] The source wiring 83 is a wiring that is electrically connected to the sub-source electrode 43 of the sub-transistor 40. The source wiring 83 and the sub-source electrode 43 are connected by a conductive sub-clip 85. This electrically connects the sub-source electrode 43 and the source wiring 83. The sub-clip 85 is made of a metal material such as Cu or Al. The sub-clip 85 is formed by pressing a metal plate.

[0081] 14, the sub-clip 85 includes a first connection portion 85A connected to the sub-source electrode 43 and a pair of second connection portions 85B connected to the source wiring 83. In one example, the first connection portion 85A and the pair of second connection portions 85B are integrated.

[0082] The first connection portion 85A is formed in a rectangular shape with its longitudinal direction in the X direction and its lateral direction in the Y direction. As shown in Fig. 15, the first connection portion 85A is joined to the sub-source electrode 43 by, for example, a conductive bonding material SD.

[0083] 14 , the pair of second connection portions 85B extend from the first connection portion 85A toward the source wiring 83 in a plan view. The pair of second connection portions 85B are arranged spaced apart from each other in the Y direction. Each second connection portion 85B is connected to the source wiring 83 by bending at a position overlapping the source wiring 83 in a plan view.

[0084] As shown in FIG. 13 , the second drain wiring 82 and the gate wiring 84 are exposed from the sub-sealing surface 91 of the sub-sealing member 90. The second drain wiring 82 and the gate wiring 84 are arranged at the same position in the Z direction. The second drain wiring 82 and the gate wiring 84 are also arranged at the same position in the Y direction and spaced apart from each other in the X direction. The second drain wiring 82 is arranged closer to the first sub-sealing side surface 93 than the gate wiring 84. The second drain wiring 82 is arranged opposite the first drain wiring 81 in the Z direction. The gate wiring 84 is arranged opposite the source wiring 83 in the Z direction. The dimension of the second drain wiring 82 in the X direction is smaller than the dimension of the first drain wiring 81 in the X direction. The dimension of the gate wiring 84 in the X direction is larger than the dimension of the source wiring 83 in the X direction. Of both X-direction ends of the gate wiring 84, the end closer to the first sub-sealing side surface 93 faces the first drain wiring 81 in a plan view.

[0085] 15 , the second drain wiring 82 is connected to the first drain wiring 81 by a first via 86. That is, the second drain wiring 82 is electrically connected to the first drain wiring 81. The first via 86 is disposed closer to the first sub sealing side surface 93 than the sub transistor 40 in the X direction. The first via 86 penetrates the sub sealing member 90 in the Z direction, for example.

[0086] The gate wiring 84 is connected to the sub-gate electrode 44 of the sub-transistor 40 by a second via 87. That is, the gate wiring 84 is electrically connected to the sub-gate electrode 44. The second via 87 is arranged at a position overlapping the sub-gate electrode 44 in a plan view. The second via 87 penetrates in the Z direction through a portion of the sub-sealing member 90 between the sub-surface 41 of the sub-transistor 40 and the sub-sealing surface 91 in the Z direction. Both the first via 86 and the second via 87 contain one or more appropriately selected from, for example, Ti, TiN, Au, Ag, Cu, Al, and W.

[0087] 13 , the sub-transistor unit 80 is disposed on the main transistor 20. More specifically, the sub-transistor unit 80 is bonded to the main transistor 20 by a conductive bonding material SD. The first drain wiring 81 is bonded to the main gate electrode 32 by a conductive bonding material SD. The source wiring 83 is bonded to the first sense source electrode 34A by a conductive bonding material SD.

[0088] The positions of the first drain wiring 81 and the source wiring 83 in the X direction are set so that, when the sub-transistor unit 80 is mounted on the main gate electrode 32 and the first sense source electrode 34A, the main gate electrode 32 and the first drain wiring 81 face each other, and the first sense source electrode 34A and the source wiring 83 face each other. In other words, the positions of the first drain wiring 81 and the source wiring 83 in the X direction are set according to the positions of the main gate electrode 32 and the first sense source electrode 34A in the X direction. In one example, the pitch in the X direction between the first drain wiring 81 and the source wiring 83 is equal to the pitch in the X direction between the main gate electrode 32 and the first sense source electrode 34A of the main transistor 20. Here, if the difference between the X-direction pitch between the first drain wiring 81 and the source wiring 83 and the X-direction pitch between the main gate electrode 32 and the first sense source electrode 34A of the main transistor 20 is, for example, within 10% of the X-direction pitch between the first drain wiring 81 and the source wiring 83, it can be said that the X-direction pitch between the first drain wiring 81 and the source wiring 83 is equal to the X-direction pitch between the main gate electrode 32 and the first sense source electrode 34A of the main transistor 20. Furthermore, the X-direction pitch between the first drain wiring 81 and the source wiring 83 is defined by the distance between the X-direction center of the first drain wiring 81 and the X-direction center of the source wiring 83. The X-direction pitch between the main gate electrode 32 and the first sense source electrode 34A of the main transistor 20 is defined by the distance between the X-direction center of the main gate electrode 32 and the X-direction center of the first sense source electrode 34A.

[0089] As shown in FIG. 16 , the main transistor 20 and the sub-transistor unit 80 are encapsulated by a encapsulating member 60. The main transistor 20 is connected to a die pad 51A by a conductive bonding material SD. The main source electrode 31 is electrically connected to the second frame 52 by a main source clip CP. The second sense source electrode 34B is electrically connected to the fifth frame 55 by a wire W2. The second drain wiring 82 of the sub-transistor unit 80 is electrically connected to the fourth frame 54 by a wire W1. Therefore, the fourth lead 54B constitutes a main gate terminal. The gate wiring 84 is electrically connected to the third frame 53 by a wire W4. Therefore, the third lead 53B constitutes a sub-gate terminal.

[0090] [Effects] The semiconductor device 10 of the third embodiment has the following effects. (3-1) The sub-transistor 40 includes a sub-surface 41 on which the sub-gate electrode 44 and the sub-source electrode 43 are formed, and a sub-back surface 42 facing the opposite side to the sub-surface 41 and on which the sub-drain electrode 45 is formed. The sub-transistor unit 80 includes a sub-sealing member 90 that seals the sub-transistor 40 without sealing the main transistor 20. The sub-sealing member 90 includes a sub-sealing surface 91 and a sub-sealing back surface 92 that face opposite each other in a plan view. The sub-sealing member 90 has insulating properties. The sub-transistor unit 80 includes: a first drain wiring 81 provided on the sub-sealing back surface 92 and electrically connected to the sub-drain electrode 45; a source wiring 83 arranged on the sub-sealing back surface 92 at a distance from the first drain wiring 81 in the X-direction and electrically connected to the sub-source electrode 43; a gate wiring 84 provided on the sub-sealing surface 91 and electrically connected to the sub-gate electrode 44; and a second drain wiring 82 arranged on the sub-sealing surface 91 at a distance from the gate wiring 84 in the X-direction and electrically connected to the sub-drain electrode 45.

[0091] According to this configuration, the first drain wiring 81 and the source wiring 83 are formed on the sub-sealing back surface 92 of the sub-sealing member 90, so the size and pitch of the first drain wiring 81 and the source wiring 83 can be adjusted as desired regardless of the size of the sub-transistor 40. Therefore, the size and pitch of the first drain wiring 81 and the source wiring 83 are determined in accordance with the electrode configuration of the main transistor 20, so there is no need to change the electrode configuration of the main transistor 20. In other words, an existing transistor can be used as the main transistor 20.

[0092] In addition, since the second drain wiring 82 electrically connected to the first drain wiring 81 is formed on the sub-sealing surface 91, in a main transistor 20 including one main gate electrode 32, even if the first drain wiring 81 is connected to the main gate electrode 32, a signal (gate signal) for driving and controlling the main transistor 20 can be supplied to the main gate electrode 32 of the main transistor 20 via the second drain wiring 82.

[0093] (3-2) The first drain wiring 81 is connected to the main gate electrode 32 of the main transistor 20 by a conductive bonding material SD. The source wiring 83 is connected to the first sense source electrode 34A of the main transistor 20 by a conductive bonding material SD.

[0094] According to this configuration, by mounting the sub-transistor unit 80 on the main transistor 20, the sub-drain electrode 45 and the main gate electrode 32 are electrically connected via the first drain wiring 81, and the sub-source electrode 43 and the first sense source electrode 34A are electrically connected via the source wiring 83. This makes it possible to shorten both the length of the conductive path between the sub-drain electrode 45 and the main gate electrode 32 and the length of the conductive path between the sub-source electrode 43 and the first sense source electrode 34A, compared to a configuration in which the sub-drain electrode 45 and the main gate electrode 32 are connected and the sub-source electrode 43 and the first sense source electrode 34A are connected via wires. Therefore, the inductance caused by the lengths of these conductive paths can be reduced.

[0095] (3-3) In plan view, the second drain wiring 82 is arranged at a position overlapping the first drain wiring 81. With this configuration, a gate signal can be supplied to the main gate electrode 32 of the main transistor 20 on which the sub-transistor unit 80 is mounted, without changing the connection of a wire or the like to the main gate electrode 32 of the main transistor 20. In addition, the sub-transistor unit 80 can be made smaller than in a configuration in which the second drain wiring 82 is arranged at a position different from the first drain wiring 81 in plan view.

[0096] (3-4) In a plan view, the gate wiring 84 is disposed at a position overlapping the source wiring 83. With this configuration, the sub-transistor unit 80 can be made smaller than in a configuration in which the gate wiring 84 is disposed at a position different from the source wiring 83 in a plan view.

[0097] (3-5) The pitch in the X direction between the first drain wiring 81 and the source wiring 83 is equal to the pitch in the X direction between the main gate electrode 32 of the main transistor 20 and the first sense source electrode 34A.

[0098] According to this configuration, the pitch in the X direction between the first drain wiring 81 and the source wiring 83 is set to match the pitch in the X direction between the main gate electrode 32 and the first sense source electrode 34A of the main transistor 20. Therefore, the first drain wiring 81 and the main gate electrode 32 can be electrically connected, and the source wiring 83 and the first sense source electrode 34A can be electrically connected, without changing the arrangement of the main gate electrode 32 and the first sense source electrode 34A of the main transistor 20.

[0099] (3-6) The area of ​​the first drain wiring 81 is smaller than that of the main gate electrode 32. The area of ​​the source wiring 83 is smaller than that of the first sense source electrode 34A. This configuration allows for favorable junction between the first drain wiring 81 and the main gate electrode 32 and between the source wiring 83 and the first sense source electrode 34A.

[0100] 17 to 27, a semiconductor device 10 according to a fourth embodiment will be described. The semiconductor device 10 according to the fourth embodiment differs from the semiconductor device 10 according to the third embodiment mainly in that the discrete semiconductor has been replaced with a module including a plurality of semiconductor elements. Below, differences from the third embodiment will be described in detail, and components common to the third embodiment will be denoted by the same reference numerals and will not be described again.

[0101] FIG. 17 shows a schematic perspective view of the semiconductor device 10 of the fourth embodiment. FIG. 18 shows a schematic perspective view of the semiconductor device 10 of FIG. 17 , omitting the sealing member 160 described later to show the internal structure of the semiconductor device 10. FIG. 19 shows a schematic perspective view of the semiconductor device 10 of FIG. 17 , omitting the first to third connection wirings 151 to 153 and the source connection wiring 154 described later to show a further internal structure of the semiconductor device 10. FIG. 20 shows a schematic planar view of the semiconductor device 10 of FIG. 18 . FIG. 21 shows an enlarged schematic planar view of the six main transistors 20 and their surroundings in FIG. 20 . FIG. 22 shows a schematic cross-sectional view of the semiconductor device 10 taken along line F22-F22 in FIG. 20 . FIG. 23 shows a schematic cross-sectional view of the semiconductor device 10 taken along line F23-F23 in FIG. 20 . FIG. 24 shows a schematic cross-sectional view of the semiconductor device 10 taken along line F24-F24 in FIG. 20 . Fig. 25 shows a schematic enlarged planar structure of a first main transistor 20A (described later) and its periphery. Fig. 26 shows a schematic enlarged planar structure of a third main transistor 20C (described later) and its periphery. Fig. 27 schematically shows the circuit configuration of the semiconductor device 10.

[0102] 17 to 21 , the semiconductor device 10 includes a plurality of (six in the fourth embodiment) main transistors 20, a plurality of (six in the fourth embodiment) sub-transistor units 80, a plurality of (two in the fourth embodiment) conductive substrates 100, a support substrate 110, a plurality of (five in the fourth embodiment) power terminals 120, a plurality of (eleven in the fourth embodiment) control terminals 130, and a sealing member 160. In the following description, for convenience, the six main transistors 20 will be referred to as "first to sixth main transistors 20A to 20F," and the six sub-transistor units 80 will be referred to as "first to sixth sub-transistor units 80A to 80F." The two conductive substrates 100 will be referred to as "first conductive substrate 100A and second conductive substrate 100B." The five power terminals 120 will be referred to as "first to third input terminals 121 to 123, first output terminal 124, and second output terminal 125." The eleven control terminals 130 are referred to as "first to fifth control terminals 131A to 135A, 131B to 135B, and sixth control terminal 136."

[0103] The semiconductor device 10 of the fourth embodiment is configured to convert DC power supplied to first to third input terminals 121 to 123 of the multiple power terminals 120 into AC power using first to sixth main transistors 20A to 20F. The converted AC power is input to a power supply target such as a motor from a first output terminal 124 and a second output terminal 125. In this manner, the semiconductor device 10 constitutes part of a power conversion circuit such as an inverter. In one example, the first to third main transistors 20A to 20C in the semiconductor device 10 constitute an upper arm of the inverter, and the fourth to sixth main transistors 20D to 20F constitute a lower arm of the inverter.

[0104] As shown in FIG. 17 , the sealing member 160 is formed in a rectangular plate shape with its thickness aligned in the Z direction. The sealing member 160 is formed in a rectangular shape with its longitudinal direction aligned in the X direction and its lateral direction aligned in the Y direction in a plan view. The sealing member 160 is made of an insulating material. For example, black epoxy resin may be used as the insulating material. The sealing member 160 seals the first to sixth main transistors 20A to 20F, the first to sixth sub-transistor units 80A to 80F, the first conductive substrate 100A, and the second conductive substrate 100B (see FIGS. 19 to 21 ). The sealing member 160 also partially seals the support substrate 110, the first to third input terminals 121 to 123, the first output terminal 124, the second output terminal 125, the first to fifth control terminals 131A to 135A and 131B to 135B, and the sixth control terminal 136.

[0105] The sealing member 160 includes a sealing front surface 161 and a sealing back surface 162 that face opposite each other in the Z direction, and first to fourth sealing side surfaces 163 to 166 that serve as four side surfaces connecting the sealing front surface 161 and the sealing back surface 162. The first sealing side surface 163 and the second sealing side surface 164 constitute both end surfaces of the sealing member 160 in the X direction. The third sealing side surface 165 and the fourth sealing side surface 166 constitute both end surfaces of the sealing member 160 in the Y direction.

[0106] The sealing surface 161 is provided with a plurality of (four in the fourth embodiment) first protrusions 167 and a plurality of (eleven in the fourth embodiment) second protrusions 168. Each of the first protrusions 167 and each of the second protrusions 168 protrudes from the sealing surface 161 in the Z direction.

[0107] The multiple first protrusions 167 are provided in a dispersed manner near the four corners of the sealing surface 161. The tip surface of each first protrusion 167 is approximately parallel to the sealing surface 161. Each first protrusion 167 is formed, for example, in the shape of a hollow truncated cone with a bottom. The multiple first protrusions 167 can be used as spacers when the semiconductor device 10 is mounted on a control circuit board or the like of an apparatus that uses power generated by the semiconductor device 10. The shape of each first protrusion 167 can be changed as desired. For example, each first protrusion 167 may be in the shape of a cylinder, a truncated pyramid, a prism, or the like.

[0108] The multiple second protrusions 168 are configured to support the first to fifth control terminals 131A to 135A, 131B to 135B, and the sixth control terminal 136. The first to fifth control terminals 131A to 135A, 131B to 135B, and the sixth control terminal 136 are provided to protrude in the Z direction from the eleven second protrusions 168. In other words, each of the first to fifth control terminals 131A to 135A, 131B to 135B, and the sixth control terminal 136 protrudes in the Z direction from the sealing surface 161. Six of the eleven second protrusions 168 are arranged near the first protrusion 167 closer to the first sealing side surface 163. The six second protrusions 168 are arranged at the same positions as each other in the X direction and spaced apart from each other in the Y direction. The remaining five second protrusions 168 are arranged near the first protrusion 167 closer to the second sealing side surface 164. The five second protrusions 168 are arranged at the same positions in the X direction and spaced apart from one another in the Y direction. Each second protrusion 168 is formed in a truncated cone shape. The shape of each second protrusion 168 can be changed as desired. In one example, each second protrusion 168 may be cylindrical, truncated pyramid, square tube, or the like.

[0109] The first to third input terminals 121 to 123 protrude from the first sealing side surface 163 in the X direction. The first to third input terminals 121 to 123 are arranged at the same position as one another in the Z direction. The first to third input terminals 121 to 123 are arranged spaced apart from one another in the Y direction. The first input terminal 121 is arranged between the second input terminal 122 and the third input terminal 123 in the Y direction. The second input terminal 122 is arranged closer to the third sealing side surface 165 than the first input terminal 121. The third input terminal 123 is arranged closer to the fourth sealing side surface 166 than the first input terminal 121.

[0110] The first output terminal 124 and the second output terminal 125 protrude in the X direction from the second sealing side surface 164. The first output terminal 124 and the second output terminal 125 are arranged at the same position as each other in the Z direction. The first output terminal 124 and the second output terminal 125 are arranged at a distance from each other in the Y direction. The first to third input terminals 121 to 123, the first output terminal 124, and the second output terminal 125 are formed from a metal material such as Cu or Al. The first to third input terminals 121 to 123, the first output terminal 124, and the second output terminal 125 are formed, for example, by pressing a metal plate.

[0111] Next, the internal structure of the semiconductor device 10 will be described. As shown in FIG. 19 , the support substrate 110 is formed in a sheet shape with the thickness direction in the Z direction. The support substrate 110 is formed in a rectangular shape with the longitudinal direction in the X direction and the lateral direction in the Y direction in a plan view. As shown in FIG. 22 , the support substrate 110 is formed, for example, by a DBC (Direct Bonded Copper) substrate. In one example, the support substrate 110 includes a first metal layer 111, a second metal layer 112, and an insulating layer 113. The insulating layer 113 is sandwiched between the first metal layer 111 and the second metal layer 112 in the Z direction.

[0112] The insulating layer 113 is made of, for example, ceramics with excellent thermal conductivity. For example, AlN (aluminum nitride) is used as the ceramic. The insulating layer 113 is not limited to ceramics and may be an insulating resin sheet.

[0113] The first metal layer 111 is formed on the surface of the insulating layer 113. As shown in FIG. 19 , a plurality of first metal layers 111 (two in the fourth embodiment) are provided. For convenience, the two first metal layers 111 are referred to as "first metal layers 111A, 111B." The two first metal layers 111A, 111B are arranged at the same position in the Y direction and spaced apart from each other in the X direction. Each of the first metal layers 111A, 111B is formed, for example, in a rectangular shape with the X direction as the short side direction and the Y direction as the long side direction. In a plan view, the first metal layers 111A, 111B have the same shape and size.

[0114] The second metal layer 112 is formed on the back surface of the insulating layer 113. The second metal layer 112 is formed, for example, in a rectangular shape that is slightly smaller than the insulating layer 113 in a plan view. The first metal layer 111 and the second metal layer 112 are formed of Cu or a Cu alloy. Note that the first metal layer 111 and the second metal layer 112 may also be formed of other conductive materials such as Al or Fe.

[0115] The support substrate 110 supports both the first conductive substrate 100A and the second conductive substrate 100B. Both the first conductive substrate 100A and the second conductive substrate 100B are disposed on the support substrate 110. The first conductive substrate 100A and the second conductive substrate 100B are arranged at the same position in the Y direction and spaced apart from each other in the X direction.

[0116] The first conductive substrate 100A is bonded to the first metal layer 111A. In one example, the first conductive substrate 100A and the first metal layer 111A are bonded by solid-state diffusion of a conductive bonding material. For example, Ag plating may be formed on the first metal layer 111A. This Ag plating can improve bonding with the conductive bonding material by solid-state diffusion.

[0117] The first conductive substrate 100A is made of a metal plate material. In one example, the first conductive substrate 100A may be configured as a lead frame. The first conductive substrate 100A supports the first to third main transistors 20A to 20C. The first conductive substrate 100A is formed in the shape of a rectangular flat plate with the thickness direction in the Z direction. The first conductive substrate 100A is formed in a rectangular shape with the longitudinal direction in the Y direction and the lateral direction in the X direction in a plan view. In one example, the first conductive substrate 100A is formed in a rectangular shape that is one size smaller than the first metal layer 111 in a plan view.

[0118] The second conductive substrate 100B is bonded to the first metal layer 111B. In one example, the second conductive substrate 100B and the first metal layer 111B are bonded by solid-state diffusion of a conductive bonding material. For example, Ag plating may be formed on the first metal layer 111B.

[0119] The second conductive substrate 100B is made of a metal plate material. In one example, the second conductive substrate 100B may be configured as a lead frame. The second conductive substrate 100B supports the fourth to sixth main transistors 20D to 20F. The second conductive substrate 100B is formed in the shape of a rectangular flat plate with its thickness direction aligned in the Z direction. The shape and size of the second conductive substrate 100B are, for example, the same as those of the first conductive substrate 100A.

[0120] Both the first conductive substrate 100A and the second conductive substrate 100B include a base material, a front surface bonding layer, and a back surface bonding layer stacked on top of each other. The base material is a plate-shaped member formed from a metal material. For example, Cu or a Cu alloy is used as the metal material. The front surface bonding layer is formed on the front surface of the base material. The front surface of the base material is the surface opposite the support substrate 110 in the Z direction. The back surface bonding layer is formed on the back surface of the base material. The back surface of the base material is the surface facing the opposite side to the front surface of the base material in the Z direction. Both the front surface bonding layer and the back surface bonding layer are formed by, for example, Ag plating.

[0121] The first to third main transistors 20A to 20C arranged on the first conductive substrate 100A are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. The first to third main transistors 20A to 20C are arranged closer to the second conductive substrate 100B on the first conductive substrate 100A in the X direction. The first main transistor 20A, the second main transistor 20B, and the third main transistor 20C are arranged in this order from the third sealing side surface 165 toward the fourth sealing side surface 166 (see FIG. 17 for both).

[0122] 25 and 26 , similar to the first embodiment, the first to third main transistors 20A to 20C have a main source electrode 31 and a main gate electrode 32 formed on the main front surface 21, and a main drain electrode 33 (see FIG. 5 ) formed on the main back surface 22. Therefore, the main drain electrodes 33 of the first to third main transistors 20A to 20C are joined to the first conductive substrate 100A by a conductive bonding material SD. As a result, the main drain electrodes 33 of the first to third main transistors 20A to 20C are electrically connected to the first conductive substrate 100A. In other words, the main drain electrodes 33 of the first to third main transistors 20A to 20C are electrically connected to each other via the first conductive substrate 100A.

[0123] 20 and 21 , first to sixth intermediate wirings 141A to 146A are provided on the first conductive substrate 100A closer to the first sealing side surface 163 than the first to third main transistors 20A to 20C. The first intermediate wiring 141A is connected to the first control terminal 131A, the second intermediate wiring 142A is connected to the second control terminal 132A, the third intermediate wiring 143A is connected to the third control terminal 133A, the fourth intermediate wiring 144A is connected to the fourth control terminal 134A, and the fifth intermediate wiring 145A is connected to the fifth control terminal 135A. The sixth intermediate wiring 146A is connected to the sixth control terminal 136. The sixth intermediate wiring 146A is arranged closer to the fourth sealing side surface 166 than the first to fifth intermediate wirings 141A to 145A. The first to sixth intermediate wirings 141A to 146A are provided on an insulating layer 147A. That is, the insulating layer 147A is interposed between the first to sixth intermediate wirings 141A to 146A and the first conductive substrate 100A in the Z direction. Therefore, the first to sixth intermediate wirings 141A to 146A and the first conductive substrate 100A are insulated by the insulating layer 147A. Details of the first to fifth intermediate wirings 141A to 145A will be described later.

[0124] The first to third input terminals 121 to 123 are arranged on the opposite side of the first conductive substrate 100A from the second conductive substrate 100B in the X direction. The first to third input terminals 121 to 123 are arranged at positions adjacent to the first conductive substrate 100A in the X direction.

[0125] The first input terminal 121 is electrically connected to the first conductive substrate 100A. In one example, as shown in FIG. 24 , the first input terminal 121 is integrated with the first conductive substrate 100A. That is, the first input terminal 121 is electrically connected to the main drain electrodes 33 of the first to third main transistors 20A to 20C. The first input terminal 121 includes a first inner lead portion sealed by the sealing member 160 and a first outer lead portion protruding from the sealing member 160.

[0126] 20 , the second input terminal 122 and the third input terminal 123 are insulated from the first conductive substrate 100A. The second input terminal 122 and the third input terminal 123 are disposed at a distance from the first conductive substrate 100A in the X direction. The second input terminal 122 includes a second inner lead portion sealed by the sealing member 160 and a second outer lead portion protruding from the sealing member 160. The third input terminal 123 includes a third inner lead portion sealed by the sealing member 160 and a third outer lead portion protruding from the sealing member 160.

[0127] 19 , the fourth to sixth main transistors 20D to 20F arranged on the second conductive substrate 100B are arranged at the same positions in the X direction and spaced apart from one another in the Y direction. The pitch of the fourth to sixth main transistors 20D to 20F in the Y direction is the same as the pitch of the first to third main transistors 20A to 20C in the Y direction. The fourth to sixth main transistors 20D to 20F are arranged on the second conductive substrate 100B closer to the first conductive substrate 100A in the X direction. The fourth main transistor 20D, the fifth main transistor 20E, and the sixth main transistor 20F are arranged in this order from the third sealing side surface 165 toward the fourth sealing side surface 166 (both see FIG. 18 ). Therefore, the fourth main transistor 20D is positioned so as to overlap the first main transistor 20A when viewed from the X direction, the fifth main transistor 20E is positioned so as to overlap the second main transistor 20B when viewed from the X direction, and the sixth main transistor 20F is positioned so as to overlap the third main transistor 20C when viewed from the X direction.

[0128] The fourth to sixth main transistors 20D to 20F have the same configuration as the first to third main transistors 20A to 20C. Therefore, the main drain electrodes 33 of the fourth to sixth main transistors 20D to 20F are joined to the second conductive substrate 100B by a conductive bonding material SD. As a result, the main drain electrodes 33 of the fourth to sixth main transistors 20D to 20F are electrically connected to each other via the second conductive substrate 100B.

[0129] First to sixth intermediate wirings 141B to 146B are provided in a portion of the second conductive substrate 100B closer to the second sealing side surface 164 than the fourth to sixth main transistors 20D to 20F. The first intermediate wiring 141B is connected to the first control terminal 131B, the second intermediate wiring 142B is connected to the second control terminal 132B, the third intermediate wiring 143B is connected to the third control terminal 133B, the fourth intermediate wiring 144B is connected to the fourth control terminal 134B, and the fifth intermediate wiring 145B is connected to the fifth control terminal 135B. On the other hand, no control terminal is connected to the sixth intermediate wiring 146B. The first to sixth intermediate wirings 141B to 146B are provided on an insulating layer 147B. In other words, the insulating layer 147B is interposed between the first to sixth intermediate wirings 141B to 146B and the second conductive substrate 100B in the Z direction. Therefore, the first to sixth intermediate wirings 141B to 146B and the second conductive substrate 100B are insulated from each other by the insulating layer 147B. Details of the first to fifth intermediate wirings 141B to 145B will be described later.

[0130] The first output terminal 124 and the second output terminal 125 are arranged on the opposite side of the second conductive substrate 100B from the first conductive substrate 100A in the X direction. The first output terminal 124 and the second output terminal 125 are arranged at positions adjacent to the second conductive substrate 100B in the X direction.

[0131] Both the first output terminal 124 and the second output terminal 125 are electrically connected to the second conductive substrate 100B. In one example, as shown in FIG. 24 , the first output terminal 124 (second output terminal 125) is integrated with the second conductive substrate 100B. That is, the first output terminal 124 and the second output terminal 125 are electrically connected to the main drain electrodes 33 of the fourth to sixth main transistors 20D to 20F. The first output terminal 124 includes a first inner lead portion sealed by the sealing member 160 and a first outer lead portion protruding from the sealing member 160. The second output terminal 125 includes a second inner lead portion sealed by the sealing member 160 and a second outer lead portion protruding from the sealing member 160.

[0132] 18 and 20, the semiconductor device 10 includes first to third connection wirings 151 to 153 and a source connection wiring 154. The first to third connection wirings 151 to 153 are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. The first to third connection wirings 151 to 153 are arranged so as to straddle the X-direction between the first conductive substrate 100A and the second conductive substrate 100B in a plan view. Each of the first to third connection wirings 151 to 153 has a strip shape extending in the X direction in a plan view. The first to third connection wirings 151 to 153 are formed of a conductive material such as Cu or Al.

[0133] 21, 22, and 24, the first connection wiring 151 connects the main source electrode 31 of the first main transistor 20A and the second conductive substrate 100B, thereby electrically connecting the main source electrode 31 of the first main transistor 20A and the second conductive substrate 100B.

[0134] The second connection wiring 152 connects the main source electrode 31 of the second main transistor 20B and the second conductive substrate 100B, thereby electrically connecting the main source electrode 31 of the second main transistor 20B and the second conductive substrate 100B.

[0135] The third connection wiring 153 connects the main source electrode 31 of the third main transistor 20C and the second conductive substrate 100B, thereby electrically connecting the main source electrode 31 of the second main transistor 20B and the second conductive substrate 100B.

[0136] Since the second conductive substrate 100B is electrically connected to the main drain electrodes 33 of the fourth to sixth main transistors 20D to 20F, the main source electrodes 31 of the first to third main transistors 20A to 20C are electrically connected to the main drain electrodes 33 of the fourth to sixth main transistors 20D to 20F.

[0137] 21 to 23, the source connection wiring 154 connects the main source electrodes 31 of the fourth to sixth main transistors 20D to 20F to the second input terminal 122 and the third input terminal 123. This electrically connects the main source electrodes 31 of the fourth to sixth main transistors 20D to 20F to the second input terminal 122 and the third input terminal 123. The source connection wiring 154 is made of a conductive material such as Cu or Al. In one example, the source connection wiring 154 is formed by pressing a metal plate, for example.

[0138] The source connection wiring 154 is formed to cover substantially the entire first conductive substrate 100A and a portion of the second conductive substrate 100B closer to the first conductive substrate 100A in a plan view. Therefore, the source connection wiring 154 includes portions that overlap with the first to third connection wirings 151 to 153 and the first to third main transistors 20A to 20C in a plan view. As shown in FIG. 22 , the source connection wiring 154 is disposed at a position spaced apart in the Z direction from the first to third connection wirings 151 to 153 and the first to third main transistors 20A to 20C. As shown in FIG. 21 , the source connection wiring 154 is formed so that the first to sixth sub-transistor units 80A to 80F are exposed in a plan view. In other words, the first to sixth sub-transistor units 80A to 80F are disposed at positions exposed from the source connection wiring 154 in a plan view. In addition, the source connection wiring 154 can be said to be formed so that the first to sixth sub-transistors 40A to 40F (see FIG. 27) are exposed in a plan view. In other words, the first to sixth sub-transistors 40A to 40F are arranged at positions exposed from the source connection wiring 154 in a plan view.

[0139] [Main Transistors and Sub-Transistor Units] Next, the first to sixth main transistors 20A to 20F and the first to sixth sub-transistor units 80A to 80F will be described.

[0140] 21 , first to third sub-transistor units 80A to 80C are arranged above the first to third main transistors 20A to 20C. Fourth to sixth sub-transistor units 80D to 80F are arranged above the fourth to sixth main transistors 20D to 20F. The first to sixth sub-transistor units 80A to 80F have the same structure, and use the sub-transistor unit 80 of the third embodiment.

[0141] 21, the first main transistor 20A and the sixth main transistor 20F have the same structure, and the second to fifth main transistors 20B to 20E have the same structure. Therefore, the following will describe the first main transistor 20A and the third main transistor 20C, and will omit a description of the second, fourth to sixth main transistors 20B, and 20D to 20F.

[0142] As shown in FIG. 25 , the first main transistor 20A includes a main source electrode 31, a main gate electrode 32, a first sense source electrode 34A, and a second sense source electrode 34B formed on the main surface 21. The first main transistor 20A also includes a first sense electrode 38 and a second sense electrode 39 formed on the main surface 21. Both the first sense electrode 38 and the second sense electrode 39 are electrically connected to a diode D1 (see FIG. 27 ) provided within the first main transistor 20A. This diode D1 is, for example, a parasitic diode of the first main transistor 20A and can be used, for example, as a temperature detection diode. The first sense electrode 38 is electrically connected to the anode of the diode D1, and the second sense electrode 39 is electrically connected to the cathode of the diode D1.

[0143] The main gate electrode 32, the first sense source electrode 34A, the second sense source electrode 34B, the first sense electrode 38, and the second sense electrode 39 are arranged closer to the first main side surface 23 in the X direction than the main source electrode 31. The main source electrode 31 is formed in a rectangular shape with its longitudinal direction in the X direction and its transverse direction in the Y direction. The main source electrode 31 is formed over most of the main surface 21. The main gate electrode 32, the first sense source electrode 34A, the first sense electrode 38, and the second sense electrode 39 are arranged spaced apart from each other in the Y direction. The first sense electrode 38 and the second sense electrode 39 are arranged closer to the third main side surface 25 than the first sense source electrode 34A and the main gate electrode 32. The second sense source electrode 34B is arranged at a position overlapping with the first sense electrode 38 and the second sense electrode 39 when viewed from the X direction. The second sense source electrode 34B is disposed closer to the main source electrode 31 than the first sense electrode 38 and the second sense electrode 39 .

[0144] The first sub-transistor unit 80A is joined to the first sense source electrode 34A and the main gate electrode 32. The connection between the first sub-transistor unit 80A and the first sense source electrode 34A and the main gate electrode 32 is the same as in the third embodiment. Therefore, the first sense source electrode 34A is electrically connected to the sub-source electrode 43 (see FIG. 14) of the first sub-transistor 40A (see FIG. 27) in the first sub-transistor unit 80A. The main gate electrode 32 is electrically connected to the sub-drain electrode 45 (see FIG. 14) of the first sub-transistor 40A in the first sub-transistor unit 80A.

[0145] 21, a sixth sub-transistor unit 80F is joined to the first sense source electrode 34A and the main gate electrode 32 of the sixth main transistor 20F. Therefore, the first sense source electrode 34A is electrically connected to the sub-source electrode 43 of the sixth sub-transistor 40F (see FIG. 27) in the sixth sub-transistor unit 80F. The main gate electrode 32 is electrically connected to the sub-drain electrode 45 of the sixth sub-transistor 40F.

[0146] 26 , the third main transistor 20C includes a main source electrode 31, a main gate electrode 32, a first sense source electrode 34A, and a second sense source electrode 34B formed on the main surface 21. On the other hand, the third main transistor 20C does not include a first sense electrode 38 or a second sense electrode 39.

[0147] The main source electrode 31 is formed over most of the main surface 21 of the third main transistor 20C. The main gate electrode 32, the first sense source electrode 34A, and the second sense source electrode 34B are arranged closer to the first main side surface 23 than the main source electrode 31.

[0148] The third sub-transistor unit 80C is joined to the first sense source electrode 34A and the main gate electrode 32. The connection between the third sub-transistor unit 80C and the first sense source electrode 34A and the main gate electrode 32 is the same as in the third embodiment. Therefore, the main source electrode 31 is electrically connected to the sub-source electrode 43 of the sub-transistor 40 in the third sub-transistor unit 80C (see FIG. 14 for both). The main gate electrode 32 is electrically connected to the sub-drain electrode 45 of the sub-transistor 40 in the third sub-transistor unit 80C (see FIG. 14 for both).

[0149] 21, the second, fourth, and sixth sub-transistor units 80B, 80D, and 80F are joined to the first sense source electrodes 34A and the main gate electrodes 32 of the second, fourth, and sixth main transistors 20B, 20D, and 20F. Therefore, the first sense source electrodes 34A of the second, fourth, and sixth main transistors 20B, 20D, and 20F are electrically connected to the sub-source electrodes 43 of the second, fourth, and sixth sub-transistors 40B, 40D, and 40F (see FIG. 27) in the second, fourth, and sixth sub-transistor units 80B, 80D, and 80F. The main gate electrodes 32 of the second and fourth to sixth main transistors 20B, 20D to 20F are electrically connected to the sub-drain electrodes 45 of the second and fourth to sixth sub-transistors 40B, 40D to 40F (see FIG. 27).

[0150] As shown in FIG. 21 , the first to third intermediate wirings 141A to 143A are wirings extending in the Y direction. The first intermediate wiring 141A is a wiring electrically connected to the second drain wirings 82 of the first to third sub-transistor units 80A to 80C. The second drain wirings 82 of the first to third sub-transistor units 80A to 80C and the first intermediate wiring 141A are connected by a wire W. Therefore, the second drain wirings 82 of the first to third sub-transistor units 80A to 80C are electrically connected to each other via the first intermediate wiring 141A. The first control terminal 131A connected to the first intermediate wiring 141A is electrically connected to the second drain wirings 82 of the first to third sub-transistor units 80A to 80C. The second drain wirings 82 of the first to third sub-transistor units 80A to 80C are electrically connected to the main gate electrodes 32 of the first to third main transistors 20A to 20C. Therefore, the first control terminal 131A constitutes a first main gate terminal (first sub-drain terminal). Here, the first intermediate wiring 141A is an example of an "upper main gate connecting wiring," and the first control terminal 131A is an example of an "upper main gate terminal."

[0151] The second intermediate wiring 142A is arranged closer to the first sealing side surface 163 in the X direction than the first intermediate wiring 141A. The second intermediate wiring 142A is arranged at a position adjacent to the first intermediate wiring 141A in the X direction. The second intermediate wiring 142A is a wiring that is electrically connected to the second sense and source electrode 34B of the first main transistor 20A, the second sense and source electrode 34B of the second main transistor 20B, and the second sense and source electrode 34B of the third main transistor 20C. The second sense and source electrodes 34B of the first to third main transistors 20A to 20C and the second intermediate wiring 142A are connected by a wire W. Therefore, the second sense and source electrodes 34B of the first to third main transistors 20A to 20C are electrically connected to each other via the second intermediate wiring 142A. The second control terminal 132A connected to the second intermediate wiring 142A is electrically connected to the second sense source electrodes 34B of the first to third main transistors 20A to 20C. Therefore, the second control terminal 132A constitutes a first sense source terminal. Here, the second intermediate wiring 142A is an example of an "upper sense source connecting wiring," and the second control terminal 132A is an example of an "upper sense source terminal."

[0152] The third intermediate wiring 143A is disposed closer to the first sealing side surface 163 (see FIG. 20 ) than the second intermediate wiring 142A in the X direction. The third intermediate wiring 143A is disposed adjacent to the second intermediate wiring 142A in the X direction. The third intermediate wiring 143A is a wiring electrically connected to the gate wiring 84 of the first to third sub-transistor units 80A to 80C. The gate wiring 84 of the first to third sub-transistor units 80A to 80C and the third intermediate wiring 143A are connected by wires W. Therefore, the gate wiring 84 of the first to third sub-transistor units 80A to 80C are electrically connected to each other via the third intermediate wiring 143A. The third control terminal 133A connected to the third intermediate wiring 143A is electrically connected to the gate wiring 84 of the first to third sub-transistor units 80A to 80C. Therefore, the third control terminal 133A constitutes a first sub-gate terminal. Here, the third intermediate wiring 143A is an example of an "upper sub-gate connection wiring", and the third control terminal 133A is an example of an "upper sub-gate terminal".

[0153] The fourth middle wiring 144A and the fifth middle wiring 145A are arranged closer to the third sealing side surface 165 (see FIG. 20) in the Y direction than the first to third middle wirings 141A to 143A.

[0154] The fourth intermediate wiring 144A is a wiring that is electrically connected to the first sense electrode 38 of the first main transistor 20A. The first sense electrode 38 of the first main transistor 20A and the fourth intermediate wiring 144A are connected by a wire W. The fourth control terminal 134A connected to the fourth intermediate wiring 144A is electrically connected to the first sense electrode 38. Therefore, the fourth control terminal 134A constitutes a first sense terminal.

[0155] The fifth intermediate wiring 145A is a wiring that is electrically connected to the second sense electrode 39 of the first main transistor 20A. The second sense electrode 39 of the first main transistor 20A and the fifth intermediate wiring 145A are connected by a wire W. The fifth control terminal 135A connected to the fifth intermediate wiring 145A is electrically connected to the second sense electrode 39. Therefore, the fifth control terminal 135A constitutes a second sense terminal.

[0156] 20 , the connection mode by wires W between the fourth to sixth main transistors 20D to 20F and the fourth to sixth sub-transistor units 80D to 80F and the first intermediate wirings 141B to 145B is the same as the connection mode by wires W between the first to third main transistors 20A to 20C and the first to third sub-transistor units 80A to 80C and the first to fifth intermediate wirings 141A to 145A, and therefore a detailed description thereof will be omitted. Here, the first intermediate wiring 141B is an example of a "lower main gate connecting wiring," and the first control terminal 131B is an example of a "lower main gate terminal." The second intermediate wiring 142B is an example of a "lower sense source connecting wiring," and the second control terminal 132B is an example of a "lower sense source terminal." The third intermediate wiring 143B is an example of a "lower sub-gate connecting wiring," and the third control terminal 133B is an example of a "lower sub-gate terminal."

[0157] [Circuit Configuration of Semiconductor Device] The semiconductor device 10 described above includes a circuit configuration as shown in FIG. 27. The semiconductor device 10 includes an upper arm transistor QU configured by first to third main transistors 20A to 20C connected in parallel with each other, and a lower arm transistor QL configured by fourth to sixth main transistors 20D to 20F connected in parallel with each other. The upper arm transistor QU and the lower arm transistor QL are connected in series. More specifically, the source of the upper arm transistor QU is electrically connected to the drain of the lower arm transistor QL. A node between these sources and drains is electrically connected to the first output terminal 124 and the second output terminal 125. The drain of the upper arm transistor QU is electrically connected to the first input terminal 121 and the sixth control terminal 136. The source of the lower arm transistor QL is electrically connected to the second input terminal 122 and the third input terminal 123. Here, the first to third main transistors 20A to 20C are an example of "plurality of upper main transistors", and the fourth to sixth main transistors 20D to 20F are an example of "plurality of lower main transistors".

[0158] The semiconductor device 10 includes an upper active clamp transistor QAU configured by first to third sub-transistors 40A to 40C connected in parallel to each other, and a lower active clamp transistor QAL configured by fourth to sixth sub-transistors 40D to 40F connected in parallel to each other. Here, the first to third sub-transistors 40A to 40C are an example of "plurality of upper sub-transistors," and the fourth to sixth sub-transistors 40D to 40F are an example of "plurality of lower sub-transistors."

[0159] The drain of the upper active clamp transistor QAU is electrically connected to the gate of the upper arm transistor QU, and the source of the upper active clamp transistor QAU is electrically connected to the source of the upper arm transistor QU. The gate of the upper active clamp transistor QAU is electrically connected to the third control terminal 133A. Both the source of the upper active clamp transistor QAU and the source of the upper arm transistor QU are electrically connected to the second control terminal 132A.

[0160] The drain of the lower active clamp transistor QAL is electrically connected to the gate of the lower arm transistor QL, and the source of the lower active clamp transistor QAL is electrically connected to the source of the lower arm transistor QL. The gate of the lower active clamp transistor QAL is electrically connected to the third control terminal 133B. Both the source of the lower active clamp transistor QAL and the source of the lower arm transistor QL are electrically connected to the second control terminal 132B.

[0161] The semiconductor device 10 includes a diode D1 electrically connected to the fourth control terminal 134A and the fifth control terminal 135A, and a diode D2 electrically connected to the fourth control terminal 134B and the fifth control terminal 135B. The diode D1 is configured to detect the temperature of, for example, the upper-arm transistor QU. The cathode of the diode D1 is electrically connected to both the source of the upper-arm transistor QU and the source of the upper active clamp transistor QAU. The diode D2 is configured to detect the temperature of, for example, the lower-arm transistor QL. The cathode of the diode D2 is electrically connected to both the source of the lower-arm transistor QL and the source of the lower active clamp transistor QAL.

[0162] [Effects] The semiconductor device 10 of the fourth embodiment has the following effects. (4-1) The semiconductor device 10 includes an upper arm transistor QU configured by first to third main transistors 20A to 20C connected in parallel to each other, a lower arm transistor QL configured by fourth to sixth main transistors 20D to 20F connected in parallel to each other and including a drain electrically connected to the source of the upper arm transistor QU, first to third sub-transistor units 80A to 80C individually arranged on the main surface 21 of each of the first to third main transistors 20A to 20C, and fourth to sixth sub-transistor units 80D to 80F individually arranged on the main surface 21 of each of the fourth to sixth main transistors 20D to 20F. Furthermore, in the semiconductor device 10, each of the first to sixth main transistors 20A to 20F includes a main gate electrode 32 and a first sense source electrode 34A formed on the main surface 21. Each of the first to sixth sub-transistor units 80A to 80F includes a sub-drain electrode 45 and a sub-source electrode 43. The sub-drain electrodes 45 of the first to third sub-transistor units 80A to 80C are electrically connected to the main gate electrodes 32 of the first to third main transistors 20A to 20C, respectively.

[0163] The sub-source electrodes 43 of the first to third sub-transistors 40A to 40C are individually electrically connected to the first sense source electrodes 34A of the first to third main transistors 20A to 20C. The sub-drain electrodes 45 of the fourth to sixth sub-transistor units 80D to 80F are individually electrically connected to the main gate electrodes 32 of the fourth to sixth main transistors 20D to 20F. The sub-source electrodes 43 of the fourth to sixth sub-transistor units 80D to 80F are individually electrically connected to the first sense source electrodes 34A of the fourth to sixth main transistors 20D to 20F.

[0164] According to this configuration, the conductive paths between the sub-drain electrodes 45 of the first to sixth sub-transistor units 80A to 80F and the main gate electrodes 32 of the first to sixth main transistors 20A to 20F can be shortened, respectively. This reduces the inductance caused by the length of these conductive paths. Furthermore, the conductive paths between the sub-source electrodes 43 of the first to sixth sub-transistor units 80A to 80F and the first sense-source electrodes 34A of the first to sixth main transistors 20A to 20F can be shortened, respectively. This reduces the inductance caused by the length of these conductive paths.

[0165] (4-2) The first to sixth sub-transistor units 80A to 80F individually seal the first to sixth sub-transistors 40A to 40F, and include an insulating sub-sealing member 90 including a sub-sealing surface 91 facing the same side as the sub-surface 41 and a sub-sealing back surface 92 facing the same side as the sub-back surface 42, a first drain wiring 81 provided on the sub-sealing back surface 92 and electrically connected to the sub-drain electrode 45, a source wiring 83 arranged on the sub-sealing back surface 92 at a distance from the first drain wiring 81 in the Y direction and electrically connected to the sub-source electrode 43, a gate wiring 84 provided on the sub-sealing surface 91 and electrically connected to the sub-gate electrode 44, and a second drain wiring 82 arranged on the sub-sealing surface 91 at a distance from the gate wiring 84 in the Y direction and electrically connected to the sub-drain electrode 45.

[0166] According to this configuration, the first drain wiring 81 and the source wiring 83 are formed on the sub sealing back surface 92 of the sub sealing member 90, so the size and pitch of the first drain wiring 81 and the source wiring 83 can be adjusted as desired regardless of the size of the sub transistor 40. Therefore, the size and pitch of the first drain wiring 81 and the source wiring 83 are determined in accordance with the configuration of the electrodes of the first to sixth main transistors 20A to 20F, so there is no need to change the configuration of the electrodes of the first to sixth main transistors 20A to 20F. In other words, existing transistors can be used as the first to sixth main transistors 20A to 20F.

[0167] (4-3) The first to sixth sub-transistor units 80A to 80F are arranged in positions exposed from the source connection wiring 154 in a plan view. This configuration makes it possible to avoid interference between the source connection wiring 154 and the wires W that connect the first to sixth sub-transistor units 80A to 80F to the first to third intermediate wirings 141A to 143A, 141B to 143B.

[0168] Fifth Embodiment A semiconductor device 10 according to a fifth embodiment will be described with reference to Figures 28 to 33. The semiconductor device 10 according to the fifth embodiment is not a discrete semiconductor, as in the fourth embodiment, but is a module.

[0169] FIG. 28 shows a schematic planar structure of the semiconductor device 10 of the fifth embodiment. FIG. 29 shows a schematic planar structure in which a sealing member 200, which will be described later, is indicated by a two-dot chain line to show the internal structure of the semiconductor device 10 of FIG. 28. FIG. 30 shows a schematic rear surface structure of the semiconductor device 10. FIG. 31 shows a schematic rear surface structure in which the sealing member 200 is indicated by a two-dot chain line to show the internal structure of the semiconductor device 10 of FIG. 30. FIG. 32 shows a schematic cross-sectional structure of the semiconductor device 10 taken along line F32-F32 in FIG. 28. FIG. 33 shows a schematic cross-sectional structure of the semiconductor device 10 taken along line F33-F33 in FIG. 28.

[0170] 28 to 33 , the semiconductor device 10 includes a plurality of (eight in the fifth embodiment) main transistors 20, a plurality of (eight in the fifth embodiment) sub-transistors 40, a plurality of (two in the fifth embodiment) substrates 170, a plurality of (five in the fifth embodiment) power terminals 180, a plurality of (eight in the fifth embodiment) control terminals 190, and a sealing member 200. In the following description, for convenience, the eight main transistors 20 will be referred to as "first to eighth main transistors 20A to 20H," and the eight sub-transistors 40 will be referred to as "first to eighth sub-transistors 40A to 40H." The two substrates 170 will be referred to as "first substrate 170A and second substrate 170B." The five power terminals 180 will be referred to as "first to third input terminals 181 to 183, first output terminal 184, and second output terminal 185." The eight control terminals 190 are referred to as "first to eighth control terminals 191 to 198."

[0171] The semiconductor device 10 of the fifth embodiment is configured to convert DC power supplied to first to third input terminals 181 to 183 of a plurality of power terminals 180 into AC power using first to eighth main transistors 20A to 20H. The converted AC power is input to a power supply target such as a motor from a first output terminal 184 and a second output terminal 185. In this manner, the semiconductor device 10 constitutes part of a power conversion circuit such as an inverter. In one example, the first to fourth main transistors 20A to 20D in the semiconductor device 10 constitute an upper arm of the inverter, and the fifth to eighth main transistors 20E to 20H constitute a lower arm of the inverter.

[0172] As shown in FIGS. 28 and 30 , the sealing member 200 is formed in a rectangular plate shape with its thickness aligned in the Z direction. The sealing member 200 is formed in a rectangular shape with its longitudinal direction aligned in the X direction and its lateral direction aligned in the Y direction in a plan view. The sealing member 200 is made of an insulating material. For example, black epoxy resin may be used as the insulating material. The sealing member 200 seals the first to eighth main transistors 20A to 20H and the first to eighth sub-transistors 40A to 40H (see FIGS. 29 and 31 ). The sealing member 200 also partially seals the first substrate 170A, the second substrate 170B, the first to third input terminals 181 to 183, the first output terminal 184, the second output terminal 185, and the first to eighth control terminals 191 to 198.

[0173] The sealing member 200 includes a sealing front surface 201 and a sealing back surface 202 that face opposite each other in the Z direction, and first to fourth sealing side surfaces 203 to 206 that serve as four side surfaces connecting the sealing front surface 201 and the sealing back surface 202. The first sealing side surface 203 and the second sealing side surface 204 constitute both end surfaces of the sealing member 200 in the X direction. The third sealing side surface 205 and the fourth sealing side surface 206 constitute both end surfaces of the sealing member 200 in the Y direction.

[0174] The first to third input terminals 181 to 183 protrude from the second sealing side surface 204 in the X direction. The first to third input terminals 181 to 183 are arranged at the same position as one another in the Z direction. The first to third input terminals 181 to 183 are arranged spaced apart from one another in the Y direction. The first input terminal 181 is arranged between the second input terminal 182 and the third input terminal 183 in the Y direction. The second input terminal 182 is arranged closer to the third sealing side surface 205 than the first input terminal 181. The third input terminal 183 is arranged closer to the fourth sealing side surface 206 than the first input terminal 181.

[0175] The first output terminal 184 and the second output terminal 185 protrude from the first sealing side surface 203 in the X direction. The first output terminal 184 and the second output terminal 185 are arranged at the same position in the Z direction. The first output terminal 184 and the second output terminal 185 are arranged spaced apart from each other in the Y direction. The first to third input terminals 181 to 183, the first output terminal 184, and the second output terminal 185 are formed from a metal material such as Cu or Al. The first to third input terminals 181 to 183, the first output terminal 184, and the second output terminal 185 are formed by pressing a metal plate. Note that the first to third input terminals 181 to 183, the first output terminal 184, and the second output terminal 185 may be formed by plating, such as Sn (tin) plating.

[0176] The first to fifth control terminals 191 to 195 protrude from the first sealed side surface 203 in the X direction. The first to fifth control terminals 191 to 195 are arranged at the same positions as one another in the Z direction. The first to fifth control terminals 191 to 195 are arranged to be spaced apart from one another in the Y direction. The first to fifth control terminals 191 to 195 are arranged between the first output terminal 184 and the second output terminal 185 in the Y direction. The first to fifth control terminals 191 to 195 are arranged at the same positions as the first output terminal 184 and the second output terminal 185 in the Z direction.

[0177] The sixth to eighth control terminals 196 to 198 protrude in the X direction from the second sealed side surface 204. The sixth to eighth control terminals 196 to 198 are arranged at the same positions as one another in the Z direction. The sixth to eighth control terminals 196 to 198 are arranged between the first input terminal 181 and the third input terminal 183 in the Y direction. The sixth to eighth control terminals 196 to 198 are arranged at the same positions as the first to third input terminals 181 to 183 in the Z direction.

[0178] Next, the internal structure of the semiconductor device 10 will be described. As shown in FIGS. 29, 32, and 33, the first substrate 170A is a substrate on which the first to fourth main transistors 20A to 20D and the fifth to eighth sub-transistors 40E to 40H are mounted. The first substrate 170A is configured, for example, by a DBC substrate. In one example, the first substrate 170A includes a first metal layer 171, a second metal layer 172, and an insulating layer 173. The insulating layer 173 is sandwiched in the Z direction between the first metal layer 171 and the second metal layer 172.

[0179] The insulating layer 173 is made of, for example, ceramics with excellent thermal conductivity. For example, AlN (aluminum nitride) is used as the ceramic. The insulating layer 173 is not limited to ceramics and may be an insulating resin sheet.

[0180] The first metal layer 171 is formed on the surface of the insulating layer 173. A plurality of first metal layers 171 (three in the fifth embodiment) are provided. For convenience, the three first metal layers 171 are referred to as "first metal layers 171A, 171B, and 171C." The three first metal layers 171A to 171C are arranged spaced apart from one another in the X direction. Each of the first metal layers 171A and 171B is formed, for example, in a rectangular shape with the X direction as its short side and the Y direction as its long side. The first metal layer 171C is, for example, in a strip shape extending in the Y direction. The first metal layer 171C is disposed between the first metal layer 171A and the first metal layer 171B in the X direction.

[0181] As shown in Figures 30, 32, and 33, the second metal layer 172 is formed on the back surface of the insulating layer 173. The second metal layer 172 is formed, for example, in a rectangular shape that is slightly smaller than the insulating layer 173 in a plan view. The first metal layer 171 and the second metal layer 172 are formed, for example, from Cu or a Cu alloy. The first metal layer 171 and the second metal layer 172 may also be formed from a conductive material such as Al. In one example, the first metal layer 171 and the second metal layer 172 may be formed by plating. In this case, the first metal layer 171 and the second metal layer 172 may also be formed, for example, from a material containing Ni.

[0182] 29, the first metal layer 171A has first to fourth main transistors 20A to 20D mounted thereon. The first to fourth main transistors 20A to 20D are arranged at the same positions in the X direction and spaced apart from each other in the Y direction.

[0183] The first to fourth main transistors 20A to 20D have a main source electrode 31, a main gate electrode 32, and two sense source electrodes 34 formed on the main surface 21, and a main drain electrode 33 (see Figure 33) formed on the main back surface 22.

[0184] The first to fourth main transistors 20A to 20D are joined to the first metal layer 171A by a conductive bonding material SD (see FIG. 33). Therefore, the main drain electrodes 33 of the first to fourth main transistors 20A to 20D are electrically connected to the first metal layer 171A. In other words, it can be said that the main drain electrodes 33 of the first to fourth main transistors 20A to 20D are electrically connected to each other via the first metal layer 171A.

[0185] The first to fifth connection wirings 211 to 215 and an insulating layer 216 are provided in a portion of the first metal layer 171A that is closer to the first sealing side surface 203 than the first to fourth main transistors 20A to 20D. The insulating layer 216 is interposed between the first to fifth connection wirings 211 to 215 and the first metal layer 171A in the Z direction. Therefore, the first to fifth connection wirings 211 to 215 are insulated from the first metal layer 171A.

[0186] The first connection wiring 211 is a wiring that is electrically connected to the main gate electrodes 32 of the first to fourth main transistors 20A to 20D. The first connection wiring 211 is formed in a strip shape extending in the Y direction. The main gate electrodes 32 of the first to fourth main transistors 20A to 20D and the first connection wiring 211 are connected by wires W. A first control terminal 191 is also connected to the first connection wiring 211. In one example, the first control terminal 191 is joined to the first connection wiring 211 by ultrasonic welding. The first control terminal 191 may also be joined to the first connection wiring 211 by a conductive bonding material. In this way, the first control terminal 191 is electrically connected to the main gate electrodes 32 of the first to fourth main transistors 20A to 20D. Therefore, the first control terminal 191 constitutes a first main gate terminal.

[0187] The second connection wiring 212 is a wiring that is electrically connected to one of the two sense source electrodes 34 of the first to fourth main transistors 20A to 20D. The second connection wiring 212 is disposed adjacent to the first connection wiring 211 in the X direction. The second connection wiring 212 is formed in a strip shape extending in the Y direction. The sense source electrodes 34 of the first to fourth main transistors 20A to 20D are connected to the second connection wiring 212 by wires W. A second control terminal 192 is also connected to the second connection wiring 212. The second control terminal 192 is connected to the second connection wiring 212 in the same manner as the first control terminal 191. In this way, the second control terminal 192 is electrically connected to the sense source electrodes 34 of the first to fourth main transistors 20A to 20D. Therefore, the second control terminal 192 constitutes a first sense source terminal.

[0188] The third connection wiring 213 is arranged closer to the third sealing side surface 205 than the first connection wiring 211 and the second connection wiring 212. The third connection wiring 213 is formed in an L shape extending in the X direction and the Y direction. The third control terminal 193 is connected to the third connection wiring 213. The method of connecting the third control terminal 193 to the third connection wiring 213 is the same as that of the first control terminal 191.

[0189] The fourth connection wiring 214 and the fifth connection wiring 215 are arranged closer to the third sealing side surface 205 than the first to third connection wirings 211 to 213. The fourth connection wiring 214 and the fifth connection wiring 215 are arranged at a distance from each other in the Y direction. The fourth connection wiring 214 and the fifth connection wiring 215 are wirings that are electrically connected to a thermistor 230 that detects the temperature inside the semiconductor device 10. The thermistor 230 includes a first terminal and a second terminal. The first terminal is joined to the fourth connection wiring 214 by a conductive bonding material, and the second terminal is joined to the fifth connection wiring 215 by a conductive bonding material.

[0190] The fourth connection wiring 214 is connected to the fourth control terminal 194. The fifth connection wiring 215 is connected to the fifth control terminal 195. The method of connecting the fourth connection wiring 214 and the fourth control terminal 194 and the method of connecting the fifth connection wiring 215 and the fifth control terminal 195 are the same as those of the first control terminal 191. In this way, the fourth control terminal 194 and the fifth control terminal 195 are electrically connected to the thermistor 230. Therefore, both the fourth control terminal 194 and the fifth control terminal 195 constitute temperature detection terminals.

[0191] The fifth to eighth sub-transistors 40E to 40H are mounted on the first metal layer 171B. The fifth to eighth sub-transistors 40E to 40H are arranged at the same positions in the X direction and spaced apart from each other in the Y direction.

[0192] The fifth to eighth sub-transistors 40E to 40H have a sub-source electrode 43 and a sub-gate electrode 44 formed on a sub-surface 41, and a sub-drain electrode 45 (see FIG. 32) formed on a sub-rear surface 42.

[0193] The fifth to eighth sub-transistors 40E to 40H are bonded to the first metal layer 171B by a conductive bonding material SD. Therefore, the sub-drain electrodes 45 of the fifth to eighth sub-transistors 40E to 40H are electrically connected to the first metal layer 171B. In other words, it can be said that the sub-drain electrodes 45 of the fifth to eighth sub-transistors 40E to 40H are electrically connected to each other via the first metal layer 171B.

[0194] A connection wiring 221 and an insulating layer 222 are provided in a portion of the first metal layer 171B that is closer to the second sealing side surface 204 than the fifth to eighth sub-transistors 40E to 40H. The insulating layer 222 is interposed between the connection wiring 221 and the first metal layer 171B in the Z direction. Therefore, the connection wiring 221 is insulated from the first metal layer 171B.

[0195] The connection wiring 221 is a wiring that is electrically connected to the sub-gate electrodes 44 of the fifth to eighth sub-transistors 40E to 40H. The connection wiring 221 is formed in a strip shape extending in the Y direction. The sub-gate electrodes 44 of the fifth to eighth sub-transistors 40E to 40H and the connection wiring 221 are connected by wires W.

[0196] 31 to 33, the second substrate 170B is a substrate on which the fifth to eighth main transistors 20E to 20H and the first to fourth sub-transistors 40A to 40D are mounted. The second substrate 170B is configured, for example, by a DBC substrate. In one example, the second substrate 170B includes a first metal layer 174, a second metal layer 175, and an insulating layer 176. As shown in FIG. 33, the second substrate 170B is disposed opposite the first substrate 170A in the Z direction.

[0197] The insulating layer 176 is made of, for example, ceramics with excellent thermal conductivity. For example, AlN is used as the ceramic. The insulating layer 176 is not limited to ceramics and may be an insulating resin sheet.

[0198] The first metal layer 174 is formed on the surface of the insulating layer 176. A plurality of first metal layers 174 (four in the fifth embodiment) are provided. For convenience, the four first metal layers 174 are referred to as "first metal layers 174A to 174D." The four first metal layers 174A to 174D are arranged at a distance from one another.

[0199] 30 , 32 , and 33 , the second metal layer 175 is formed on the back surface of the insulating layer 176. The second metal layer 175 is formed, for example, in a rectangular shape that is slightly smaller than the insulating layer 176 in a plan view. The first metal layer 174 and the second metal layer 175 are formed, for example, from Cu or a Cu alloy. The first metal layer 174 and the second metal layer 175 may also be formed from a conductive material such as Al.

[0200] 31, the fifth to eighth main transistors 20E to 20H are mounted on the first metal layer 174A. The fifth to eighth main transistors 20E to 20H are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. The fifth to eighth main transistors 20E to 20H have the same configuration as the first main transistor 20A.

[0201] 32 and 33 , the fifth to eighth main transistors 20E to 20H are arranged opposite the fifth to eighth sub-transistors 40E to 40H in the Z direction. More specifically, the fifth sub-transistor 40E is arranged at a position overlapping the main gate electrode 32 of the fifth main transistor 20E in a plan view. Therefore, it can be said that at least a portion of the fifth sub-transistor 40E is arranged below the main gate electrode 32 of the fifth main transistor 20E. Similarly, the sixth to eighth sub-transistors 40F to 40H are arranged at a position overlapping the main gate electrodes 32 of the sixth to eighth main transistors 20F to 20H in a plan view. Therefore, it can be said that at least a portion of the sixth to eighth sub-transistors 40F to 40H is arranged below the main gate electrodes 32 of the sixth to eighth main transistors 20F to 20H.

[0202] 31 and 32, the fifth to eighth main transistors 20E to 20H are joined to the first metal layer 174A by a conductive bonding material SD. Therefore, the main drain electrodes 33 of the fifth to eighth main transistors 20E to 20H are electrically connected to the first metal layer 174A. In other words, it can be said that the main drain electrodes 33 of the fifth to eighth main transistors 20E to 20H are electrically connected to each other via the first metal layer 174A.

[0203] First to third connection wirings 241 to 243 and an insulating layer 244 are provided in portions of the first metal layer 174A that are closer to the second sealing side surface 204 than the fifth to eighth main transistors 20E to 20H. The insulating layer 244 is interposed between the first to third connection wirings 241 to 243 and the first metal layer 174A in the Z direction. Therefore, the first to third connection wirings 241 to 243 are insulated from the first metal layer 174A.

[0204] Each of the main source electrodes 31 of the fifth main transistor 20E and the sixth main transistor 20F is electrically connected to the first metal layer 174C by a wire W. A second input terminal 182 is connected to the first metal layer 174C. As a result, each of the main source electrodes 31 of the fifth main transistor 20E and the sixth main transistor 20F is electrically connected to the second input terminal 182.

[0205] Each of the main source electrodes 31 of the seventh main transistor 20G and the eighth main transistor 20H is electrically connected to the first metal layer 174D by a wire W. A third input terminal 183 is connected to the first metal layer 174D. As a result, each of the main source electrodes 31 of the seventh main transistor 20G and the eighth main transistor 20H is electrically connected to the third input terminal 183.

[0206] The first connection wiring 241 is a wiring that is electrically connected to the main gate electrodes 32 of the fifth to eighth main transistors 20E to 20H. The first connection wiring 241 is formed in a strip shape extending in the Y direction. The main gate electrodes 32 of the fifth to eighth main transistors 20E to 20H and the first connection wiring 241 are connected by wires W. The first connection wiring 241 is electrically connected to the sixth control terminal 196. The connection structure between the first connection wiring 241 and the sixth control terminal 196 is the same as that of the first control terminal 191. As a result, the sixth control terminal 196 is electrically connected to the main gate electrodes 32 of the fifth to eighth main transistors 20E to 20H. Therefore, it can be said that the sixth control terminal 196 constitutes a second main gate terminal.

[0207] The first connection wiring 241 is also electrically connected to the first metal layer 171B (see FIG. 29 ). In one example, the first connection wiring 241 and the first metal layer 171B are connected by a first pillar 261. The first pillar 261 is formed in a columnar shape extending in the Z direction. The first pillar 261 is formed of a conductive material such as Cu or Al. The first connection wiring 241 and the first metal layer 171B include portions that are arranged opposite each other in the Z direction. The first pillar 261 connects the opposing portions of the first connection wiring 241 and the first metal layer 171B. In this way, it can be said that the first connection wiring 241 is electrically connected to the sub-drain electrodes 45 of the fifth to eighth sub-transistors 40E to 40H. Therefore, it can be said that the sixth control terminal 196 is electrically connected to the sub-drain electrodes 45 of the fifth to eighth sub-transistors 40E to 40H. Here, the first pillar 261 is an example of a "second connecting member."

[0208] The second connection wiring 242 is a wiring that is electrically connected to one of the two sense source electrodes 34 of the fifth to eighth main transistors 20E to 20H. The second connection wiring 242 is disposed adjacent to the first connection wiring 241 in the Y direction. The second connection wiring 242 is formed in a strip shape extending in the Y direction. The sense source electrodes 34 of the fifth to eighth main transistors 20E to 20H are connected to the second connection wiring 242 by wires W. A seventh control terminal 197 is electrically connected to the second connection wiring 242. The connection structure between the second connection wiring 242 and the seventh control terminal 197 is the same as that of the first control terminal 191. In this way, the seventh control terminal 197 is electrically connected to the sense source electrodes 34 of the fifth to eighth main transistors 20E to 20H. Therefore, it can be said that the seventh control terminal 197 constitutes a second sense source terminal.

[0209] The third connection wiring 243 is disposed at a position overlapping the fifth main transistor 20E when viewed from the X direction. The third connection wiring 243 is formed in an L-shape extending in the X and Y directions. The eighth control terminal 198 is electrically connected to the third connection wiring 243. The connection structure between the third connection wiring 243 and the eighth control terminal 198 is the same as that of the first control terminal 191. The third connection wiring 243 is electrically connected to the connection wiring 221 (see FIG. 29 ) by a second pillar 262. The second pillar 262 is formed in a columnar shape extending in the Z direction. The second pillar 262 is formed of a conductive material such as Cu or Al. The third connection wiring 243 and the connection wiring 221 include portions arranged opposite each other in the Z direction. The second pillar 262 connects the opposing portions of the third connection wiring 243 and the connection wiring 221. In this way, the third connection wiring 243 is electrically connected to the sub-gate electrodes 44 of the fifth to eighth sub-transistors 40E to 40H. Therefore, it can be said that the eighth control terminal 198 is electrically connected to the sub-gate electrodes 44 of the fifth to eighth sub-transistors 40E to 40H. In other words, it can be said that the eighth control terminal 198 constitutes a second sub-gate terminal.

[0210] The first metal layer 174B is provided with the first to fourth sub-transistors 40A to 40D. The first to fourth sub-transistors 40A to 40D are arranged at the same positions in the X direction and spaced apart from each other in the Y direction. The first to fourth sub-transistors 40A to 40D have the same configuration as the fifth sub-transistor 40E.

[0211] 32 and 33 , the first to fourth main transistors 20A to 20D are arranged opposite the first to fourth sub-transistors 40A to 40D in the Z direction. More specifically, the first sub-transistor 40A is arranged at a position overlapping the main gate electrode 32 of the first main transistor 20A in a plan view. Therefore, it can be said that at least a portion of the first sub-transistor 40A is arranged above the main gate electrode 32 of the first main transistor 20A. Similarly, the second to fourth sub-transistors 40B to 40D are arranged at positions overlapping the main gate electrodes 32 of the second to fourth main transistors 20B to 20D in a plan view. Therefore, it can be said that at least a portion of the second to fourth sub-transistors 40B to 40D is arranged above the main gate electrodes 32 of the second to fourth main transistors 20B to 20D.

[0212] The first to fourth sub-transistors 40A to 40D are bonded to the first metal layer 174B by a conductive bonding material SD. Therefore, the sub-drain electrodes 45 of the first to fourth sub-transistors 40A to 40D are electrically connected to the first metal layer 174B. In other words, it can be said that the sub-drain electrodes 45 of the first to fourth sub-transistors 40A to 40D are electrically connected to each other via the first metal layer 174B.

[0213] The first metal layer 174B is electrically connected to the first connection wiring 211. In one example, the first metal layer 174B and the first connection wiring 211 are connected by a third pillar 263. The third pillar 263 is formed in a columnar shape extending in the Z direction. The third pillar 263 is formed of a conductive material such as Cu or Al. The first metal layer 174B and the first connection wiring 211 include portions that are arranged opposite each other in the Z direction. The third pillar 263 connects the opposing portions of the first metal layer 174B and the first connection wiring 211. As a result, the first connection wiring 211 is electrically connected to the sub-drain electrodes 45 of the first to fourth sub-transistors 40A to 40D. Therefore, it can be said that the first control terminal 191 is electrically connected to the sub-drain electrodes 45 of the first to fourth sub-transistors 40A to 40D. Here, the third pillar 263 is an example of a "first connection member."

[0214] A connection wiring 251 and an insulating layer 252 are provided in a portion of the first metal layer 174B that is closer to the first sealing side surface 203 than the first to fourth sub-transistors 40A to 40D. The insulating layer 252 is interposed between the connection wiring 251 and the first metal layer 174B in the Z direction. Therefore, the connection wiring 251 is insulated from the first metal layer 174B.

[0215] The connection wiring 251 is a wiring electrically connected to the sub-gate electrodes 44 of the first to fourth sub-transistors 40A to 40D. The connection wiring 251 is formed in a strip shape extending in the Y direction. The sub-gate electrodes 44 of the first to fourth sub-transistors 40A to 40D and the connection wiring 251 are connected by wires W. The connection wiring 251 is also electrically connected to the third connection wiring 213 (see FIG. 29 ). In one example, the connection wiring 251 and the third connection wiring 213 are connected by a fourth pillar 264. The fourth pillar 264 is formed in a columnar shape extending in the Z direction. The fourth pillar 264 is made of a conductive material such as Cu or Al. The connection wiring 251 and the third connection wiring 213 include portions arranged opposite each other in the Z direction. The fourth pillar 264 connects the opposing portions of the connection wiring 251 and the third connection wiring 213. In this way, the third control terminal 193 is electrically connected to the sub-gate electrodes 44 of the first to fourth sub-transistors 40A to 40D. Therefore, it can be said that the third control terminal 193 constitutes a first sub-gate terminal.

[0216] 29, 31, and 33, the main source electrodes 31 of the first to fourth main transistors 20A to 20D and the sub-source electrodes 43 of the first to fourth sub-transistors 40A to 40D are individually electrically connected by first source connection pillars 271. The main source electrodes 31 of the fifth to eighth main transistors 20E to 20H and the sub-source electrodes 43 of the fifth to eighth sub-transistors 40E to 40H are individually electrically connected by second source connection pillars 272. The first source connection pillars 271 and the second source connection pillars 272 extend in the Z direction. The first source connection pillars 271 and the second source connection pillars 272 are formed of a conductive material such as Cu or Al.

[0217] As shown in FIG. 33 , the first metal layer 171C and the first metal layer 174A are electrically connected. In one example, the first metal layer 171C and the first metal layer 174A are connected by a fifth pillar 265. The first metal layer 171C and the first metal layer 174A include portions that are arranged opposite each other in the Z direction. The fifth pillar 265 connects the opposing portions of the first metal layer 171C and the first metal layer 174A. This electrically connects the main source electrodes 31 of the first to fourth main transistors 20A to 20D and the main drain electrodes 33 of the fourth to eighth main transistors 20E to 20H. Here, the first metal layer 171C is an example of a "first surface electrode," and the first metal layer 174A is an example of a "second surface electrode." The fifth pillar 265 is an example of a "third connection member." Therefore, it can be said that the third connection member includes a pillar. The circuit configuration of the semiconductor device 10 of the fifth embodiment is the same as the circuit configuration of the semiconductor device 10 of the fourth embodiment.

[0218] [Effects] The semiconductor device 10 of the fifth embodiment has the following effects: (5-1) The semiconductor device 10 includes a first substrate 170A on which the first to eighth main transistors 20A to 20H, the first to eighth sub-transistors 40A to 40H, the first to fourth main transistors 20A to 20D, and the fifth to eighth sub-transistors 40E to 40H are mounted, and a second substrate 170B disposed opposite the first substrate 170A in the Z direction and on which the fifth to eighth main transistors 20E to 20F and the first to fourth sub-transistors 40A to 40D are mounted. a third pillar 263 that electrically connects the main gate electrodes 32 of the first to fourth main transistors 20A to 20D to the sub-drain electrodes 45 of the first to fourth sub-transistors 40A to 40D, and a first pillar 261 that electrically connects the main gate electrodes 32 of the fifth to eighth main transistors 20E to 20H to the sub-drain electrodes 45 of the fifth to eighth sub-transistors 40E to 40H.

[0219] According to this configuration, the first substrate 170A and the second substrate 170B are arranged opposite each other in the Z direction, and therefore the semiconductor device 10 can be made smaller than in a configuration in which the first substrate 170A and the second substrate 170B are arranged in a direction intersecting the Z direction.

[0220] (5-2) The first substrate 170A includes a first metal layer 171C electrically connected to the main source electrodes 31 of the first to fourth main transistors 20A to 20D. The second substrate 170B includes a first metal layer 174A electrically connected to the main drain electrodes 33 of the fifth to eighth main transistors 20E to 20H. The semiconductor device 10 includes a fifth pillar 265 electrically connecting the first metal layer 171C and the first metal layer 174A.

[0221] According to this configuration, the main source electrodes 31 of the first to fourth main transistors 20A to 20D and the main drain electrodes 33 of the fifth to eighth main transistors 20E to 20H can be electrically connected inside the semiconductor device 10. Therefore, compared to a configuration in which the main source electrodes 31 of the first to fourth main transistors 20A to 20D and the main drain electrodes 33 of the fifth to eighth main transistors 20E to 20H are electrically connected outside the semiconductor device 10, the conduction paths between the main source electrodes 31 of the first to fourth main transistors 20A to 20D and the main drain electrodes 33 of the fifth to eighth main transistors 20E to 20H can be made shorter.

[0222] <Modifications> The above embodiment can be modified as follows: The following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0223] In the first embodiment, instead of the sub-transistor 40, the sub-transistor unit 80 of the third embodiment may be disposed on the main transistor 20. In this case, the first drain wiring 81 of the sub-transistor unit 80 may be electrically connected to the main gate electrode 32 of the main transistor 20, and the source wiring 83 may be electrically connected to the first sense-source electrode 34A of the main transistor 20. The gate wiring 84 may be electrically connected to the third frame 53 by a wire W1. In this case, the wire W3 is omitted. When multiple main gate electrodes such as the first main gate electrode 32A and the second main gate electrode 32B are provided as in the main transistor 20 of the first embodiment, the second drain wiring 82 may be omitted from the sub-transistor unit 80. In this case, the gate wiring 84 may be disposed in a position overlapping with the first drain wiring 81 in a plan view.

[0224] In the first embodiment, the relationship between the area of ​​the first main gate electrode 32A and the area of ​​the second main gate electrode 32B in a plan view can be changed as desired. For example, the area of ​​the first main gate electrode 32A may be larger than the area of ​​the second main gate electrode 32B. This configuration allows a larger-sized sub-transistor 40 to be disposed on the first main gate electrode 32A.

[0225] In the first embodiment, it is possible to arbitrarily change the arrangement of the main transistor 20 with respect to the die pad 51A of the first frame 51. In one example, as shown in Fig. 34 , the main transistor 20 may be arranged on the die pad 51A so that the first main gate electrode 32A, the second main gate electrode 32B, the first sense source electrode 34A, and the second sense source electrode 34B are aligned along the Y direction.

[0226] In the first and second embodiments, the configuration of the sub-transistor 40 can be changed as desired. For example, a lateral transistor in which a sub-source electrode 43, a sub-gate electrode 44, and a sub-drain electrode 45 are formed on a sub-surface 41 may be used as the sub-transistor 40. In this case, for example, in the first embodiment, the sub-drain electrode 45 and the first main gate electrode 32A may be connected by a wire. Also, for example, in the second embodiment, the sub-drain electrode 45 and the clip 70 may be connected by a wire.

[0227] In the first and second embodiments, the configuration of the main transistor 20 can be changed as desired. For example, at least one of the first sense source electrode 34A and the second sense source electrode 34B may be formed integrally with the main source electrode 31. That is, the passivation layer 35 may have one source opening that opens areas of the source electrode layer 36 where the first sense source electrode 34A, the second sense source electrode 34B, and the main source electrode 31 are to be formed.

[0228] In the second embodiment, the size relationship between the main gate electrode 32 and the sub-transistor 40 in a plan view can be changed arbitrarily. For example, as shown in Fig. 35 , the size of the sub-transistor 40 in a plan view may be changed to include a portion that protrudes from the main gate electrode 32. In the example shown in Fig. 35 , the sub-transistor 40 includes a portion that protrudes from the main gate electrode 32 toward the third main side surface 25.

[0229] In the second embodiment, the position of the sub-transistor 40 is not limited to a position overlapping the main gate electrode 32 in a plan view, and can be changed as desired. In one example, the sub-transistor 40 may be arranged closer to the third sealing side surface 65 (see FIG. 7 ) than the main gate electrode 32, provided that it is on the clip 70. Furthermore, the sub-transistor 40 may be arranged closer to the third sealing side surface 65 than the main transistor 20, provided that it is on the clip 70.

[0230] In the first and second embodiments, the connecting member that connects the sub-source electrode 43 of the sub-transistor 40 and the first sense source electrode 34A is not limited to the wire W3 and can be changed as desired. For example, a conductive clip may be used as the connecting member.

[0231] In the third embodiment, the size of the first drain wiring 81 is larger than the size of the source wiring 83, but this is not limitative. The first drain wiring 81 and the source wiring 83 may be the same size in plan view.

[0232] In the third embodiment, the area of ​​the first drain wiring 81 may be equal to or larger than the area of ​​the main gate electrode 32. The area of ​​the source wiring 83 may be equal to or larger than the area of ​​the first sense source electrode 34A.

[0233] In the third embodiment, the arrangement of the main gate electrode 32, the first sense source electrode 34A, and the second sense source electrode 34B in the main transistor 20 can be changed as desired. For example, as shown in FIG. 36 , the main gate electrode 32 may be arranged closer to the first main side surface 23 in the X direction than both the first sense source electrode 34A and the second sense source electrode 34B. In this case, the first sense source electrode 34A is arranged, for example, between the second sense source electrode 34B and the main gate electrode 32 in the X direction. The sub-transistor unit 80 is electrically connected to, for example, the main gate electrode 32 and the first sense source electrode 34A.

[0234] In the first to third embodiments, the fifth frame 55 may be omitted. In the fourth embodiment, the arrangement of the first to sixth main transistors 20A to 20F may be changed as desired. For example, the first to third main transistors 20A to 20C may be arranged with a shift in the X direction. For example, the fourth to sixth main transistors 20D to 20F may be arranged with a shift in the X direction.

[0235] In the fourth embodiment, the first to sixth sub-transistors 40A to 40F may be arranged on the main gate electrodes 32 of the first to sixth main transistors 20A to 20F. As a result, the main gate electrodes 32 of the first to sixth main transistors 20A to 20F and the sub-drain electrodes 45 of the first to sixth sub-transistors 40A to 40F are individually and electrically connected to each other.

[0236] In the fourth embodiment, the electrode configuration of the first main transistor 20A and the sixth main transistor 20F can be changed as desired. As an example, as shown in FIG. 37 , both the first main transistor 20A and the sixth main transistor 20F may have the same electrode configuration as the second to fifth main transistors 20B to 20E. In this case, the fourth intermediate wirings 144A and 144B, the fourth control terminals 134A and 134B, the fifth intermediate wirings 145A and 145B, and the fifth control terminals 135A and 135B (all see FIG. 20 ) may be omitted.

[0237] In the fifth embodiment, the configuration of the first substrate 170A and the second substrate 170B is not limited to DBC substrates and can be changed as desired. In one example, the first substrate 170A and the second substrate 170B may be made of ceramic. In this case, a wiring layer corresponding to the first metal layers 171A to 171C may be formed on the first substrate 170A. A wiring layer corresponding to the first metal layers 174A to 174D may be formed on the second substrate 170B.

[0238] In the fifth embodiment, there may be only one main transistor 20 and one sub-transistor 40. In one example, as shown in FIG. 38 , the semiconductor device 10 includes a first substrate 170A on which the main transistor 20 is mounted, and a second substrate 170B on which the sub-transistor 40 is mounted, the second substrate 170B being spaced apart from the first substrate 170A in a plan view. The main transistor 20 is bonded to a first metal layer 171A with a conductive bonding material SD. This electrically connects the main drain electrode 33 to the first metal layer 171A. The sub-transistor 40 is bonded to a first metal layer 174 with a conductive bonding material SD. This electrically connects the sub-drain electrode 45 to the first metal layer 174. The main transistor 20 and the sub-transistor 40 are disposed opposite each other in the Z direction.

[0239] The main source electrode 31 of the main transistor 20 and the sub-source electrode 43 of the sub-transistor 40 are electrically connected. In one example, the main source electrode 31 and the sub-source electrode 43 are connected by a conductive first pillar 291. The main gate electrode 32 of the main transistor 20 is electrically connected to the first metal layer 171B. In one example, the main gate electrode 32 and the first metal layer 171B are connected by a conductive wire W. The first metal layer 171B and the first metal layer 174 are electrically connected. In one example, the first metal layer 171B and the first metal layer 174 are connected by a conductive second pillar 292. As a result, the main gate electrode 32 is electrically connected to the sub-drain electrode 45 of the sub-transistor 40. Here, the second pillar 292 is an example of a "connecting member that electrically connects the main gate electrode 32 of the main transistor 20 and the sub-drain electrode 45 of the sub-transistor 40."

[0240] The semiconductor device 10 includes an insulating layer 282 formed on the second substrate 170B and a connection wiring 281 formed on the insulating layer 282. The insulating layer 282 is formed on the first metal layer 174. Therefore, the connection wiring 281 is insulated from the first metal layer 174.

[0241] The sub-gate electrode 44 of the sub-transistor 40 is electrically connected to the connection wiring 281. In one example, the sub-gate electrode 44 and the connection wiring 281 are connected by a conductive wire W. The connection wiring 281 and the first metal layer 171C are electrically connected. In one example, the connection wiring 281 and the first metal layer 171C are connected by a conductive third pillar 293. A third control terminal 193 is electrically connected to the first metal layer 171C. Therefore, it can be said that the third control terminal 193 constitutes a sub-gate terminal.

[0242] Although not shown, the semiconductor device 10 includes an input terminal electrically connected to the main drain electrode 33 of the main transistor 20, and an output terminal electrically connected to the main source electrode 31 of the main transistor 20.

[0243] One or more of the various examples described herein can be combined to the extent that they are not technically inconsistent. In this specification, "at least one of A and B" should be understood to mean "only A, or only B, or both A and B."

[0244] The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended to mean that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0245] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z direction described herein being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0246] <Supplementary Notes> The technical ideas that can be understood from this disclosure are described below. Note that the reference numerals of the components of the embodiments corresponding to the components described in each supplementary note are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0247] [Appendix A1] A semiconductor device (10) comprising: a main transistor (20) having a main surface (21) on which a main source electrode (31) and a main gate electrode (32) are formed; and a sub-transistor (40) at least a portion of which is arranged above the main gate electrode (32), the sub-transistor (40) having a sub-drain electrode (45) electrically connected to the main gate electrode (32) and a sub-source electrode (43) electrically connected to the main source electrode (31).

[0248] [Appendix A2] The semiconductor device according to Appendix A1, wherein the sub-transistor (40) includes a sub-surface (41) on which the sub-source electrode (43) is formed, and a sub-backside (42) facing the opposite side of the sub-surface (41) and on which the sub-drain electrode (45) is formed, and the main gate electrode (32A) and the sub-drain electrode (45) are joined by a conductive bonding material (SD).

[0249] [Appendix A3] The semiconductor device according to Appendix A2, wherein the main gate electrode (32) includes a first main gate electrode (32A) and a second main gate electrode (32B) that are spaced apart from each other when viewed in the thickness direction (Z direction) of the main transistor (20), and the sub-drain electrode (45) is joined to the first main gate electrode (32A) by the conductive joining material (SD).

[0250] [Appendix A4] The semiconductor device according to Appendix A1 or A2, further comprising a conductive clip (70) joined to the main gate electrode (32), wherein the sub-transistor (40) is arranged above the clip (70) with the sub-drain electrode (45) joined to the clip (70).

[0251] [Appendix A5] The semiconductor device according to Appendix A4, wherein the sub-transistor (40) is arranged in a portion of the clip (70) that overlaps with the main gate electrode (32) when viewed in the thickness direction (Z direction) of the main transistor (20).

[0252] [Appendix A6] The semiconductor device according to Appendix A4 or A5, wherein the sub-transistor (40) includes a sub-surface (41) on which the sub-source electrode (43) is formed, and a sub-backside (42) facing the opposite side of the sub-surface (41) and on which the sub-drain electrode (45) is formed, and the clip (70) and the sub-drain electrode (45) are joined by a conductive joining material (SD).

[0253] [Appendix A7] The semiconductor device according to any one of Appendices A1 to A6, wherein the main transistor (20) includes a sense source electrode (34A) formed on the main surface (21), and the sense source electrode (34A) and the sub-source electrode (43) are electrically connected via a connecting member (W3).

[0254] [Appendix A8] The sub-transistor (40) has a sub-surface (41) on which a sub-gate electrode (44) and the sub-source electrode (43) are formed, and a sub-back surface (42) facing the opposite side of the sub-surface (41) and on which the sub-drain electrode (45) is formed; an insulating sub-sealing member (90) that encapsulates the sub-transistor (40) without encapsulating the main transistor (20), and includes a sub-sealing surface (91) and a sub-sealing back surface (92) facing opposite sides in a thickness direction (Z direction) of the sub-transistor (40); a first drain wiring (81) provided on the sub-sealing back surface (92) and electrically connected to the sub-drain electrode (45); and a source wiring (83) disposed on the sub-sealing back surface (92) at a distance from the first drain wiring (81) in a first direction (X direction) intersecting the thickness direction (Z direction), and electrically connected to the sub-source electrode (43). The semiconductor device according to Appendix A1, comprising: a gate wiring (84) provided on the sub-encapsulating surface (91) and electrically connected to the sub-gate electrode (44); and a second drain wiring (82) arranged on the sub-encapsulating surface (91) at a distance from the gate wiring (84) in the first direction (X direction) and electrically connected to the sub-drain electrode (45).

[0255] [Appendix A9] The semiconductor device according to Appendix A8, wherein the main transistor (20) includes a sense source electrode (34) formed on the main surface (21), and a pitch in the first direction (X direction) between the first drain wiring (81) and the source wiring (83) is equal to a pitch in the first direction (X direction) between the main gate electrode (32) and the sense source electrode (34A) of the main transistor (20).

[0256] [Appendix A10] The semiconductor device according to Appendix A9, wherein the sub-transistor (40) is disposed above the main transistor (20), and the main gate electrode (32) and the first drain wiring (81) are joined by a conductive bonding material (SD).

[0257] [Appendix A11] The semiconductor device according to appendix A9 or A10, wherein the sense source electrode (34A) and the source wiring (83) are joined together by a conductive bonding material (SD).

[0258] [Appendix A12] The semiconductor device according to Appendix A3, comprising: a main source terminal (52B) electrically connected to the main source electrode (31); a main gate terminal (54B) electrically connected to the second main gate electrode (32B); and a sealing member (60) that seals both the main transistor (20) and the sub-transistor (40), wherein the main source terminal (52B) and the main gate terminal (54B) are exposed from the sealing member.

[0259] [Appendix A13] The semiconductor device according to Appendix A12, wherein the sub-transistor (40) includes a sub-gate electrode (44), and a sub-gate terminal (53B) electrically connected to the sub-gate electrode (44), and the sub-gate terminal (53B) is exposed from the sealing member (60).

[0260] [Appendix A14] The semiconductor device according to Appendix A1, comprising: a first substrate (170A) on which the main transistor (20) is mounted; a second substrate (170B) on which the sub-transistor (40) is mounted, the second substrate (170B) being spaced apart from the first substrate (170A) in the thickness direction (Z direction) of the first substrate (170A); and a connecting member (292) that electrically connects the main gate electrode (32) of the main transistor (20) and the sub-drain electrode (45) of the sub-transistor (40).

[0261] [Appendix A15] The semiconductor device according to Appendix A14, wherein the main transistor (20) and the sub-transistor (40) are arranged opposite to each other in the thickness direction (Z direction).

[0262] [Appendix A16] The semiconductor device according to Appendix A15, wherein the connection member (292) includes a pillar.

[0263] [Appendix A17] The main transistor (20) includes a first main transistor (20A) and a second main transistor (20E), the sub-transistor (40) includes a first sub-transistor (40A) and a second sub-transistor (40E), a first substrate (170A) on which the first main transistor (20A) and the second sub-transistor (40E) are mounted, a second substrate (170B) disposed opposite the first substrate (170A) in the thickness direction (Z direction) of the first substrate (170A) and on which the second main transistor (20E) and the first sub-transistor (20A) are mounted, a first connection member (263) electrically connecting the main gate electrode (32) of the first main transistor (20A) and the sub-drain electrode (45) of the first sub-transistor (40A), The semiconductor device according to Appendix A1, further comprising: a second connection member (261) that electrically connects the main gate electrode (32) of the second main transistor (20E) and the sub-drain electrode (45) of the second sub-transistor (40E).

[0264] [Appendix A18] The semiconductor device according to Appendix A17, wherein the first main transistor (20A) and the first sub-transistor (40A) are arranged opposite each other in the thickness direction (Z direction), and the second main transistor (20E) and the second sub-transistor (40E) are arranged opposite each other in the thickness direction (Z direction).

[0265] [Appendix A19] The semiconductor device according to Appendix A18, wherein the first main transistor (20A) includes a main source electrode (31) electrically connected to a main drain electrode (33) of the second main transistor (20E), the first substrate (170A) includes a first surface electrode (171C) electrically connected to the main source electrode (31) of the first main transistor (20A), the second substrate (170B) includes a second surface electrode (174A) electrically connected to the main drain electrode (33) of the second main transistor (20E), and a third connection member (265) electrically connecting the first surface electrode (171C) and the second surface electrode (174A).

[0266] [Appendix A20] The semiconductor device according to Appendix A19, wherein the first main transistor (20A) and the second sub-transistor (40E) are arranged spaced apart in a first direction (X direction) intersecting the thickness direction (Z direction), the second main transistor (20E) and the first sub-transistor (40A) are arranged spaced apart in the first direction (X direction), the first surface electrode (171C) is arranged between the first main transistor (20A) and the second sub-transistor (40E) in the first direction (X direction), and the third connection member (265) is provided between the first main transistor (20A) and the second sub-transistor (40E) in the first direction (X direction) and between the second main transistor (20E) and the first sub-transistor (40A) in the first direction (X direction).

[0267] [Appendix A21] The semiconductor device according to any one of Appendices A8 to A11, wherein the second drain wiring (82) is arranged at a position overlapping the first drain wiring (81) when viewed from the thickness direction (Z direction).

[0268] [Appendix A22] The semiconductor device according to any one of Appendices A8 to A11, wherein the gate wiring (84) is arranged at a position overlapping the source wiring (83) when viewed from the thickness direction (Z direction).

[0269] [Appendix A23] The semiconductor device according to any one of Appendices A9 to A11, wherein an area of ​​the first drain wiring (81) is smaller than an area of ​​the main gate electrode (32), and an area of ​​the source wiring (83) is smaller than an area of ​​the sense source electrode (34A).

[0270] [Appendix A24] The semiconductor device according to Appendix A12 or A13, wherein the main transistor (20) includes a sense source electrode (34B), and a sense source terminal (55B) electrically connected to the sense source electrode (34B), and the sense source terminal (55B) is exposed from the sealing member (60).

[0271] [Appendix A25] The semiconductor device according to Appendix A12 or A13, wherein the main transistor (20) includes a main drain electrode (33), a main drain terminal (51B) electrically connected to the main drain electrode (33), and a die pad (51A) integrated with the main drain terminal (51B), and the main transistor (20) is disposed on the die pad (51A).

[0272] [Appendix A26] The semiconductor device according to any one of Appendices A8 to A11, wherein the main transistor (20) includes a main drain electrode (33), a main source terminal (52B) electrically connected to the main source electrode (31), a main drain terminal (51B) electrically connected to the main drain electrode (33), a main gate terminal (54B) electrically connected to the second drain wiring (82), and a sub-gate terminal (53B) electrically connected to the gate wiring (84), and a sealing member (60) that seals both the main transistor (20) and the sub-transistor (40), wherein the main source terminal (52B), the main drain terminal (51B), the main gate terminal (54B), and the sub-gate terminal (53B) are exposed from the sealing member (60).

[0273] [Appendix A27] A semiconductor device comprising: a first substrate (170A) on which a main transistor (20) is mounted; and a second substrate (170B) on which a sub-transistor (40) is mounted, the second substrate (170B) being disposed apart from the first substrate (170A) in a thickness direction (Z direction) of the first substrate (170A), ...), the main transistor (20) and the sub-transistor (40) being disposed so as to face each other in the thickness direction (Z direction), the main transistor (20) comprising a main surface (21) on which a main gate electrode (32) and a main source electrode (31) are formed, the sub-transistor (40) comprising a sub-surface (41) facing the main surface (21), a sub-back surface (42) facing the opposite side to the sub-surface (41), and a sub-drain electrode (45) formed on the sub-back surface (42), and a connecting member (292) electrically connecting the main gate electrode (32) and the sub-drain electrode (45).

[0274] [Appendix A28] The semiconductor device according to any one of Appendices A1 to A27, wherein the main transistor (20) has a main back surface (22) facing the opposite side to the main front surface (21), and a main drain electrode (33) is formed on the main back surface (22).

[0275] [Appendix A29] The semiconductor device according to any one of Appendices A1 to A28, wherein the main transistor (20) is a SiC MOSFET.

[0276] [Appendix B1] A sub-transistor (40) including a sub-surface (41) and a sub-back surface (42) facing the opposite side to the sub-surface (41), a sub-gate electrode (44) and a sub-source electrode (43) provided on the sub-surface (41), and a sub-drain electrode (45) provided on the sub-back surface (42); an insulating sub-sealing member (90) that encapsulates the sub-transistor (40) and includes a sub-sealing surface (91) and a sub-sealing back surface (92) facing opposite sides in a thickness direction (Z direction) perpendicular to the sub-surface (41); a first drain wiring (81) provided on the sub-sealing back surface (92) and electrically connected to the sub-drain electrode (45); and a source wiring (83) disposed on the sub-sealing back surface (92) at a distance from the first drain wiring (81) in a first direction (X direction) intersecting the thickness direction (Z direction), and electrically connected to the sub-source electrode (43). A sub-transistor unit (80) including: a gate wiring (84) provided on the sub-encapsulating surface (91) and electrically connected to the sub-gate electrode (44); and a second drain wiring (82) arranged on the sub-encapsulating surface (91) at a distance from the gate wiring (84) in the first direction (X direction) and electrically connected to the sub-drain electrode (45).

[0277] [Appendix B2] The sub-transistor unit according to Appendix B1, wherein the first drain wiring (81) and the sub-drain electrode (45) are joined together by a conductive joining material (SD).

[0278] [Appendix B3] The sub-transistor unit according to Appendix B1 or Appendix B2, wherein the second drain wiring (82) is arranged at a position overlapping the first drain wiring (81) when viewed from the thickness direction (Z direction).

[0279] [Appendix B4] The sub-transistor unit according to any one of Appendices B1 to B3, wherein the gate wiring (84) is arranged at a position overlapping the source wiring (83) when viewed from the thickness direction (Z direction).

[0280] [Appendix B5] The sub-transistor unit according to any one of Appendices B1 to B4, wherein the sub-source electrode (43) and the source wiring (83) are connected by a conductive clip (85).

[0281] [Appendix B6] The sub-transistor unit according to any one of Appendices B1 to B5, wherein the sub-transistor (40) is a SiMOSFET.

[0282] [Appendix C1] An upper arm transistor (QU) constituted by a plurality of upper main transistors (20A to 20C) connected in parallel with each other; a lower arm transistor (QL) constituted by a plurality of lower main transistors (20D to 20F) connected in parallel with each other and including a drain electrically connected to the source of the upper arm transistor (QU); a plurality of upper sub-transistors (40A to 40C) individually arranged on the main surface (21) of each of the plurality of upper main transistors (20A to 20C); and a plurality of lower sub-transistors (40D to 40F) individually arranged on the main surface (21) of each of the plurality of lower main transistors (20D to 20F), each of the plurality of upper main transistors (20A to 20C) and the plurality of lower main transistors (20D to 20F) including a main gate electrode (32) and a sense source electrode (34) formed on the main surface (21), Each of the plurality of upper sub-transistors (40A to 40C) and the plurality of lower sub-transistors (40D to 40F) includes a sub-drain electrode (45) and a sub-source electrode (43), the sub-drain electrodes (45) of the plurality of upper sub-transistors (40A to 40C) are individually electrically connected to the main gate electrodes (32) of the plurality of upper main transistors (20A to 20C), the sub-source electrodes (43) of the plurality of upper sub-transistors (40A to 40C) are individually electrically connected to the sense source electrodes (34) of the plurality of upper main transistors (20A to 20C), and the sub-drain electrodes (45) of the plurality of lower sub-transistors (40D to 40F) are individually electrically connected to the main gate electrodes (32) of the plurality of lower main transistors (40D to 40F), The sub-source electrodes (43) of the plurality of lower sub-transistors (40D to 40F) are individually electrically connected to the sense source electrodes (34) of the plurality of lower main transistors (20D to 20F).

[0283] [Appendix C2] Each of the plurality of upper sub-transistors (40A to 40C) and the plurality of lower sub-transistors (40D to 40F) has a sub-surface (41) on which a sub-gate electrode (44) and the sub-source electrode (43) are formed, and a sub-back surface (42) facing the opposite side to the sub-surface (41) and on which the sub-drain electrode (45) is formed; a sub-sealing member (90) that individually encapsulates the plurality of upper sub-transistors (40A to 40C) and the plurality of lower sub-transistors (40D to 40F) and includes a sub-sealing surface (91) facing the same side as the sub-surface (41) and a sub-sealing back surface (92) facing the same side as the sub-back surface (42), and has insulating properties; a first drain wiring (81) provided on the sub-sealing back surface (92) and electrically connected to the sub-drain electrode (45); The semiconductor device according to Appendix C1, comprising: a source wiring (83) disposed on the sub-sealing back surface (92) at a distance from the first drain wiring (81) in a first direction (X direction) intersecting a thickness direction (Z direction) of the sub-sealing member (90), and electrically connected to the sub-source electrode (43); a gate wiring (84) provided on the sub-sealing surface (91) and electrically connected to the sub-gate electrode (44); and a second drain wiring (82) disposed on the sub-sealing surface (91) at a distance from the gate wiring (84) in the first direction (X direction), and electrically connected to the sub-drain electrode (45).

[0284] [Appendix C3] A semiconductor device comprising: a first conductive substrate (100A) and a second conductive substrate (100B) spaced apart from each other in a second direction (Y direction); a first input terminal (121) electrically connected to the first conductive substrate (100A); and an output terminal (124, 125) electrically connected to the second conductive substrate (100B); each of the plurality of upper main transistors (20A-20C) and the plurality of lower main transistors (20D-20F) comprises a main source electrode (31); and the plurality of upper main transistors (20A-20C) are disposed on the first conductive substrate (100A) such that the main drain electrode (33) is electrically connected to the first conductive substrate (100A); the plurality of lower main transistors (20D to 20F) are arranged on the second conductive substrate (100B) such that the main drain electrodes (33) are electrically connected to the second conductive substrate (100B); connection wirings (151 to 153) electrically connecting each of the main source electrodes (31) of the plurality of upper main transistors (20A to 20C) to the second conductive substrate (100B); source connection wirings (154) electrically connecting each of the main source electrodes (31) of the plurality of lower main transistors (20D to 20F); second input terminals (122, 123) electrically connected to the source connection wirings (154); and a sealing member (160) that seals the first conductive substrate (100A), the second conductive substrate (100B), the plurality of upper main transistors (20A to 20C), the plurality of lower main transistors (20D to 20F), the connection wiring (151 to 153), and the source connection wiring (154), and also partially seals the first input terminal (121), the second input terminal (122, 123), and the output terminal (124, 125).

[0285] [Appendix C4] Each of the plurality of upper sub-transistors (40A to 40C) and the plurality of lower sub-transistors (40D to 40F) includes a sub-gate electrode (44), a first insulating layer (147A) formed on the first conductive substrate (100A), an upper main gate connection wiring (141A) formed on the first insulating layer (147A) and electrically connected to each of the main gate electrodes (32) of the plurality of upper main transistors (20A to 20C), and an upper sense source connection wiring (142A) formed on the first insulating layer (147A) and electrically connected to each of the sense source electrodes (34B) of the plurality of upper main transistors (20A to 20C), an upper sub-gate connection wiring (143A) formed in the first insulating layer (147A) and electrically connected to each of the sub-gate electrodes (44) of the plurality of upper sub-transistors (40A to 40C); an upper main gate terminal (131A) electrically connected to the upper main gate connection wiring (141A); an upper sense source terminal (132A) electrically connected to the upper sense source connection wiring (142A); and an upper sub-gate terminal (133A) electrically connected to the upper sub-gate connection wiring (143A), The semiconductor device described in Appendix C3, wherein the sealing member (160) seals the first insulating layer (147A), the upper main gate connection wiring (141A), the upper sense source connection wiring (142A), and the upper sub-gate connection wiring (143A), and also partially seals the upper main gate terminal (131A), the upper sense source terminal (132A), and the upper sub-gate terminal (133A).

[0286] [Appendix C5] A second insulating layer (147B) formed on the second conductive substrate (100B); A lower main gate connection wiring (141B) formed on the second insulating layer (147B) and electrically connected to each of the main gate electrodes (32) of the plurality of lower main transistors (20D to 20F); A lower sense source connection wiring (142B) formed on the second insulating layer (147B) and electrically connected to each of the sense source electrodes (34B) of the plurality of lower main transistors (20D to 20F); A lower sub-gate connection wiring (143B) formed on the second insulating layer (147B) and electrically connected to each of the sub-gate electrodes (45) of the plurality of lower sub-transistors (40D to 40F); A lower main gate terminal (131B) electrically connected to the lower main gate connection wiring (141B); a lower sense source terminal (132B) electrically connected to the lower sense source connection wiring (142B); and a lower sub-gate terminal (133B) electrically connected to the lower sub-gate connection wiring (143B), wherein the sealing member (160) seals the second insulating layer (147B), the lower main gate connection wiring (141B), the lower sense source connection wiring (142B), and the lower sub-gate connection wiring (143B), and also partially seals the lower main gate terminal (131B), the lower sense source terminal (132B), and the lower sub-gate terminal (133B).

[0287] [Appendix C6] A semiconductor device described in any one of Appendices C3 to C5, wherein each of the plurality of upper sub-transistors (40A to 40C) and the plurality of lower sub-transistors (40D to 40F) is arranged at a position exposed from the source connection wiring (154) when viewed from the thickness direction (Z direction) of the first conductive substrate (100A).

[0288] [Appendix C7] The semiconductor device according to any one of Appendices C3 to C6, including a support substrate (110) that supports the first conductive substrate (100A) and the second conductive substrate (100B), wherein the support substrate (110) is composed of a DBC substrate.

[0289] [Appendix C8] The semiconductor device according to any one of Appendices C3 to C7, wherein both the first conductive substrate (100A) and the second conductive substrate (100B) are made of metal plate material.

[0290] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0291] REFERENCE SIGNS LIST 10...Semiconductor device 20...Main transistor 20A to 20H...1st to 8th main transistors 21...Main surface 22...Main back surface 23 to 26...1st to 4th main side surfaces 31...Main source electrode 32...Main gate electrode 32A...First main gate electrode 32B...Second main gate electrode 33...Main drain electrode 34...Sense source electrode 34A...First sense source electrode 34B...Second sense source electrode 35...Passivation layer 35A to 35C...1st to 3rd source openings 35D...First gate opening 35E...Second gate opening 35F...First source partition 35G...Second source partition 35H...Gate partition 35J...Gate opening 36...Source electrode layer 37...Gate electrode layer 38...First sense electrode 39...Second sense electrode 40...Sub-transistor 40A to 40H...first to eighth sub-transistors 41...sub-surface 42...sub-back surface 43...sub-source electrode 44...sub-gate electrode 45...sub-drain electrode 51...first frame 51A...die pad 51B...first lead 52...second frame 52A...second pad 52B...second lead 53...third frame 53A...third pad 53B...third lead 54...fourth frame 54A...fourth pad 54B...fourth lead 55...fifth frame 55A...fifth pad 55B...fifth lead 60...encapsulating member 61...encapsulating surface 62...encapsulating back surface 63 to 66...first to fourth encapsulating side surfaces 70...clip 71...gate junction portion 72...wiring portion 80...sub-transistor unit 80A to 80F...first to sixth sub-transistor units 81...first drain wiring 82... Second drain wiring 83... Source wiring 84... Gate wiring 85... Sub-clip 85A... First connection portion 85B... Second connection portion 86... First via 87... Second via 90... Sub-sealing member 91... Sub-sealing surface 92... Sub-sealing back surface 93 to 96... First to fourth sub-sealing side surfaces 100... Conductive substrate 100A... First conductive substrate 100B... Second conductive substrate 110... Support substrate 111, 111A,111B...First metal layer 112...Second metal layer 113...Insulating layer 120...Power terminal 121-123...First to third input terminals 124...First output terminal 125...Second output terminal 130...Control terminal 131A-135A, 131B-135B...First to fifth control terminals 136...Sixth control terminal 141A-146A, 141B-146B...First to sixth intermediate wiring 147A, 147B...Insulating layer 151-153...First to third connection wiring 154...Source connection wiring 160...Sealing member 161...Sealing surface 162...Sealing back surface 163-166...First to fourth sealing side surfaces 167...First protrusion 168...Second protrusion 170...Substrate 170A...First substrate 170B...Second substrate 171, 171A to 171C...First metal layer 172...Second metal layer 173...Insulating layer 174, 174A to 174D...First metal layer 175...Second metal layer 176...Insulating layer 180...Power terminal 181 to 183...First to third input terminals 184...First output terminal 185...Second output terminal 190...Control terminal 191 to 198...First to eighth control terminals 200...Sealing member 201...Sealing surface 202...Sealing back surface 203 to 206...First to fourth sealing side surfaces 211 to 215...First to fifth connecting wirings 216...Insulating layer 221...Connecting wiring 222...Insulating layer 230...Thermistor 241 to 243...First to third connecting wirings 244...insulating layer 251...connecting wiring 252...insulating layer 261-265...first to fifth pillars 271...first source connecting pillar 272...second source connecting pillar 281...connecting wiring 282...insulating layer 291-293...first to third pillars QU...upper arm transistor QL...lower arm transistor QAU...upper active clamp transistor QAL...lower active clamp transistor SD...conductive bonding material W, W1 to W4...wires CP...main source clip D1, D2...diode,

Claims

1. A main transistor having a main surface on which a main source electrode and a main integrated circuit are formed, A subtransistor, at least a portion of which is positioned above the main gate electrode, having a sub-drain electrode electrically connected to the main gate electrode and a sub-source electrode electrically connected to the main source electrode, Semiconductor equipment, including

2. The subtransistor includes a subsurface on which the subsource electrode is formed, and a subback surface facing the opposite side from the subsurface on which the subdrain electrode is formed. The main gate electrode and the sub-drain electrode are joined together by a conductive bonding material. The semiconductor device according to claim 1.

3. The main gate electrode includes a first main gate electrode and a second main gate electrode, which are arranged spaced apart from each other when viewed in the thickness direction of the main transistor. The sub-drain electrode is bonded to the first main gate electrode by the conductive bonding material. The semiconductor device according to claim 2.

4. The present invention further includes a conductive clip joined to the main gate electrode, The subtransistor is positioned above the clip with the subdrain electrode joined to the clip. The semiconductor device according to claim 1.

5. Viewed from the thickness direction of the main transistor, the subtransistor is positioned in the portion of the clip that overlaps with the main gate electrode. The semiconductor device according to claim 4.

6. The subtransistor includes a subsurface on which the subsource electrode is formed, and a subback surface facing the opposite side from the subsurface on which the subdrain electrode is formed. The clip and the sub-drain electrode are joined together by a conductive bonding material. The semiconductor device according to claim 4.

7. The main transistor includes a sense source electrode formed on the main surface, The sense source electrode and the sub-source electrode are electrically connected via a connecting member. The semiconductor device according to claim 1.

8. The subtransistor has a subsurface on which the subgate electrode and the subsource electrode are formed, and a subback surface facing the opposite side from the subsurface on which the subdrain electrode is formed. The sub-transistor is sealed without sealing the main transistor, and the sub-sealing member includes a sub-sealing surface and a sub-sealing back surface that face opposite each other in the thickness direction of the sub-transistor, and is insulating. A first drain wiring is provided on the back surface of the sub-seal and is electrically connected to the sub-drain electrode, On the back surface of the sub-sealing, a source wiring is arranged at a distance from the first drain wiring in a first direction intersecting the thickness direction, and is electrically connected to the sub-source electrode, A gate wiring provided on the sub-sealing surface and electrically connected to the sub-gate electrode, On the sub-sealing surface, a second drain wiring is arranged at a distance from the gate wiring in the first direction and is electrically connected to the sub-drain electrode, including The semiconductor device according to claim 1.

9. The main transistor includes a sense source electrode formed on the main surface, The pitch of the first drain wiring and the source wiring in the first direction is equal to the pitch of the main gate electrode and the sense source electrode of the main transistor in the first direction. The semiconductor device according to claim 8.

10. The sub-transistor is positioned above the main transistor. The main gate electrode and the first drain wiring are joined together by a conductive bonding material. The semiconductor device according to claim 9.

11. The sense source electrode and the source wiring are joined together by a conductive bonding material. The semiconductor device according to claim 9.

12. A main source terminal electrically connected to the main source electrode, The main gate terminal electrically connected to the second main gate electrode, A sealing member that seals both the main transistor and the sub-transistor, Includes, The main source terminal and the main gate terminal are exposed from the sealing member. The semiconductor device according to claim 3.

13. The subtransistor includes a subgate electrode, Includes a subgate terminal electrically connected to the subgate electrode, The subgate terminal is exposed from the sealing member. The semiconductor device according to claim 12.

14. The first substrate on which the main transistor is mounted, A second substrate is positioned at a distance from the first substrate in the thickness direction of the first substrate, and the subtransistor is mounted on it. A connecting member that electrically connects the main gate electrode of the main transistor and the sub-drain electrode of the sub-transistor, including The semiconductor device according to claim 1.

15. In the thickness direction, the main transistor and the sub-transistor are arranged facing each other. The semiconductor device according to claim 14.

16. The connecting member includes a pillar. The semiconductor device according to claim 15.

17. The main transistor includes a first main transistor and a second main transistor. The subtransistor includes a first subtransistor and a second subtransistor, A first substrate on which the first main transistor and the second subtransistor are mounted, A second substrate is positioned opposite to the first substrate in the thickness direction of the first substrate, and on which the second main transistor and the first subtransistor are mounted, A first connecting member that electrically connects the main gate electrode of the first main transistor and the sub-drain electrode of the first sub-transistor, A second connecting member that electrically connects the main gate electrode of the second main transistor and the sub-drain electrode of the second sub-transistor, including The semiconductor device according to claim 1.

18. In the thickness direction, the first main transistor and the first sub-transistor are arranged facing each other. In the thickness direction, the second main transistor and the second sub-transistor are arranged facing each other. The semiconductor device according to claim 17.

19. The first main transistor includes a main source electrode that is electrically connected to the main drain electrode of the second main transistor. The first substrate includes a first surface electrode electrically connected to the main source electrode of the first main transistor. The second substrate includes a second surface electrode electrically connected to the main drain electrode of the second main transistor. Includes a third connecting member that electrically connects the first surface electrode and the second surface electrode. The semiconductor device according to claim 18.

20. The first main transistor and the second subtransistor are arranged spaced apart in a first direction intersecting the thickness direction. The second main transistor and the first subtransistor are arranged to be spaced apart in the first direction. The first surface electrode is positioned between the first main transistor and the second subtransistor in the first direction. The third connecting member is provided between the first main transistor and the second subtransistor in the first direction, and between the second main transistor and the first subtransistor in the first direction. The semiconductor device according to claim 19.