Semiconductor device and electronic device

Abstract

A semiconductor device according to one embodiment of the present disclosure is provided with: a first substrate which is obtained by stacking a first semiconductor layer and a first wiring layer; a second substrate which is obtained by stacking a second semiconductor layer and a second wiring layer, the second wiring layer forming a bonding surface together with the first wiring layer; a plurality of first bonding electrodes which are formed on the bonding surface of the first wiring layer, and which each have a first bonding surface; a plurality of second bonding electrodes which are formed on the bonding surface of the second wiring layer, and which each have second bonding surfaces that are bonded to the first bonding surfaces of the plurality of first bonding electrodes; one or a plurality of first metal layers which are formed between first bonding electrodes adjacent to each other on the bonding surface of the first wiring layer, and which have a first facing surface that recedes toward the first semiconductor layer side relative to the first bonding surface and faces the second substrate; and one or a plurality of second metal layers which are formed between second bonding electrodes adjacent to each other on the bonding surface of the second wiring layer, and which have a second facing surface that faces the first substrate.

Description

Semiconductor devices and electronic devices

[0001] The present disclosure relates to a semiconductor device and an electronic device having a plurality of semiconductor layers stacked on top of each other.

[0002] For example, Patent Document 1 discloses an imaging device in which a first substrate including a plurality of sensor pixels and a second substrate having a plurality of readout circuits are electrically connected to each other by bonding bonding electrodes provided on the opposing surfaces of the first substrate and the second substrate.

[0003] Japanese Patent Application Laid-Open No. 2020-088380

[0004] In such semiconductor devices, there is a demand for relaxed alignment accuracy.

[0005] Therefore, it is desirable to provide a semiconductor device and an electronic device that can relax the alignment precision requirement.

[0006] A semiconductor device according to one embodiment of the present disclosure includes a first substrate formed by stacking a first semiconductor layer and a first wiring layer; a second substrate formed by stacking a second semiconductor layer and a second wiring layer, the second wiring layer forming a bonding surface together with the first wiring layer; a plurality of first bonding electrodes formed on the bonding surface of the first wiring layer, each having a first bonding surface; a plurality of second bonding electrodes formed on the bonding surface of the second wiring layer, each having a second bonding surface bonded to the first bonding surfaces of the plurality of first bonding electrodes; one or more first metal layers formed between adjacent first bonding electrodes on the bonding surface of the first wiring layer, the first metal layers being recessed toward the first semiconductor layer from the first bonding surface and having a first opposing surface opposing the second substrate; and one or more second metal layers formed between adjacent second bonding electrodes on the bonding surface of the second wiring layer, the second metal layers having a second opposing surface opposing the first substrate.

[0007] An electronic device according to an embodiment of the present disclosure includes the semiconductor device according to the embodiment described above as a semiconductor device.

[0008] In a semiconductor device and an electronic device according to an embodiment of the present disclosure, a plurality of first bonding electrodes and a plurality of second bonding electrodes are provided on the respective bonding surfaces of a first wiring layer and a second wiring layer that form the bonding surface between a first substrate and a second substrate, and one or more first metal layers and one or more second metal layers are provided between adjacent first bonding electrodes and adjacent second bonding electrodes, respectively. Of the one or more first metal layers and one or more second metal layers, the one or more first metal layers have opposing surfaces that are recessed toward the semiconductor layer (first semiconductor layer) from the bonding surfaces of the plurality of first bonding electrodes. This prevents contact between the opposing bonding electrodes and a shield electrode at the bonding surface between the first substrate and the second substrate.

[0009] FIG. 1 is a block diagram illustrating an example of a functional configuration of an imaging device according to an embodiment of the present disclosure. FIG. 2 is a schematic plan view illustrating a general configuration of the imaging device illustrated in FIG. 1. FIG. 3 is a schematic view illustrating a cross-sectional configuration along line AA′ illustrated in FIG. 2. FIG. 4 is an equivalent circuit diagram of the pixel sharing unit illustrated in FIG. 1. FIG. 5 is a diagram illustrating an example of a connection mode between a plurality of pixel sharing units and a plurality of vertical signal lines. FIG. 6 is a schematic cross-sectional view illustrating an example of a specific configuration of the imaging device illustrated in FIG. 3. FIG. 7A is a schematic view illustrating an example of a planar configuration of a main portion of the first substrate illustrated in FIG. 6. FIG. 7B is a schematic view illustrating a planar configuration of a pad portion together with a main portion of the first substrate illustrated in FIG. 7A. FIG. 8 is a schematic view illustrating an example of a planar configuration in a horizontal direction relative to the main surface of the second substrate (semiconductor layer) illustrated in FIG. 6. FIG. 9 is a schematic view illustrating an example of a planar configuration of a pixel circuit and a main portion of the first substrate together with the first wiring layer illustrated in FIG. 6. FIG. 10A is a schematic cross-sectional view illustrating a detailed configuration of the bonding surface between the first substrate and the second substrate illustrated in FIG. 6. FIG. 10B is a cross-sectional schematic diagram illustrating misalignment at the bonding surfaces of the first substrate and the second substrate. FIG. 11A is a cross-sectional schematic diagram illustrating the configuration of the bonding surfaces of two substrates as a comparative example. FIG. 11B is a cross-sectional schematic diagram illustrating misalignment between the two substrates in the configuration shown in FIG. 11A. FIG. 12A is a cross-sectional schematic diagram illustrating the configuration of the bonding surfaces of two substrates as a comparative example. FIG. 12B is a cross-sectional schematic diagram illustrating misalignment between the two substrates in the configuration shown in FIG. 12A. FIG. 13A is a plan view schematic diagram illustrating an example of the layout of a plurality of bonding electrodes and a shield electrode on the bonding surfaces of each of the first substrate and the second substrate. FIG. 13B is a plan view schematic diagram illustrating another example of the layout of a plurality of bonding electrodes and a shield electrode on the bonding surfaces of each of the first substrate and the second substrate. FIG. 13C is a plan view schematic diagram illustrating another example of the layout of a plurality of bonding electrodes and a shield electrode on the bonding surfaces of each of the first substrate and the second substrate. Fig. 14A is a cross-sectional view illustrating a manufacturing process of a plurality of bonding electrodes and a shield electrode on the bonding surfaces of the first substrate and the second substrate shown in Fig. 10A. Fig. 14B is a cross-sectional view illustrating a process subsequent to Fig. 14A. Fig. 14C is a cross-sectional view illustrating a process subsequent to Fig. 14B. Fig. 14D is a cross-sectional view illustrating a process subsequent to Fig. 14C.14E is a schematic cross-sectional view illustrating a step subsequent to FIG. 14D . FIG. 14F is a schematic cross-sectional view illustrating a step subsequent to FIG. 14E . FIG. 14G is a schematic cross-sectional view illustrating a step subsequent to FIG. 14F . FIG. 14H is a schematic cross-sectional view illustrating a step subsequent to FIG. 14G . FIG. 15 is a schematic diagram for explaining paths of input signals and the like to the imaging device illustrated in FIG. 3 . FIG. 16 is a schematic diagram for explaining signal paths of pixel signals in the imaging device illustrated in FIG. 3 . FIG. 17A is a schematic cross-sectional view illustrating a manufacturing process of a plurality of bonding electrodes and a shield electrode according to Modification 1 of the present disclosure. FIG. 17B is a schematic cross-sectional view illustrating a step subsequent to FIG. 17A . FIG. 17C is a schematic cross-sectional view illustrating a step subsequent to FIG. 17B . FIG. 17D is a schematic cross-sectional view illustrating a step subsequent to FIG. 17C . FIG. 18 is a schematic cross-sectional view illustrating a detailed configuration of a plurality of bonding electrodes and a shield electrode according to Modification 1 of the present disclosure. FIG. 19A is a schematic cross-sectional view illustrating a manufacturing process of a plurality of bonding electrodes and a shield electrode according to Modification 2 of the present disclosure. 19B is a schematic cross-sectional view illustrating a step subsequent to FIG. 19A . FIG. 19C is a schematic cross-sectional view illustrating a step subsequent to FIG. 19B . FIG. 19D is a schematic cross-sectional view illustrating a step subsequent to FIG. 19C . FIG. 19E is a schematic cross-sectional view illustrating a step subsequent to FIG. 19D . FIG. 19F is a schematic cross-sectional view illustrating a step subsequent to FIG. 19E . FIG. 20A is a schematic cross-sectional view illustrating a manufacturing step of a plurality of bonding electrodes and a shield electrode according to Modification 3 of the present disclosure. FIG. 20B is a schematic cross-sectional view illustrating a step subsequent to FIG. 20A . FIG. 20C is a schematic cross-sectional view illustrating a step subsequent to FIG. 20B . FIG. 20D is a schematic cross-sectional view illustrating a step subsequent to FIG. 20C . FIG. 20E is a schematic cross-sectional view illustrating a step subsequent to FIG. 20D . FIG. 20F is a schematic cross-sectional view illustrating a step subsequent to FIG. 20E . FIG. 21A is a schematic cross-sectional view illustrating a manufacturing step of a plurality of bonding electrodes and a shield electrode according to Modification 4 of the present disclosure. Fig. 21B is a schematic cross-sectional view illustrating a step subsequent to Fig. 21A. Fig. 21C is a schematic cross-sectional view illustrating a step subsequent to Fig. 21B. Fig. 21D is a schematic cross-sectional view illustrating a step subsequent to Fig. 21C. Fig. 21E is a schematic cross-sectional view illustrating a step subsequent to Fig. 21D. Fig. 22A is a schematic cross-sectional view illustrating a manufacturing process of a plurality of bonding electrodes and a shield electrode according to Modification 5 of the present disclosure. Fig. 22B is a schematic cross-sectional view illustrating a step subsequent to Fig. 22A.22C is a schematic cross-sectional view showing a step subsequent to FIG. 22B. FIG. 22D is a schematic cross-sectional view showing a step subsequent to FIG. 22C. FIG. 22E is a schematic cross-sectional view showing a step subsequent to FIG. 22D. FIG. 22F is a schematic cross-sectional view showing a step subsequent to FIG. 22E. FIG. 22G is a schematic cross-sectional view showing a step subsequent to FIG. 22F. FIG. 22H is a schematic cross-sectional view showing a step subsequent to FIG. 22G. FIG. 23 is a block diagram showing an example of the configuration of an electronic device having the imaging device shown in FIG. 1. FIG. 24A is a schematic diagram showing an example of the overall configuration of a light detection system using the imaging device shown in FIG. 1 etc. FIG. 24B is a diagram showing an example of the circuit configuration of the light detection system shown in FIG. 24A. FIG. 25 is a block diagram showing an example of the general configuration of a vehicle control system. FIG. 26 is an explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit. FIG. 27 is a diagram showing an example of the general configuration of an endoscopic surgery system. FIG. 28 is a block diagram showing an example of the functional configuration of a camera head and a CCU.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order: 1. Embodiment (an example of an imaging device in which a shield electrode having an opposing surface recessed from the bonding surface of the bonding electrodes is provided between adjacent bonding electrodes on the bonding surface of a first substrate and a second substrate) 2. Modifications 2-1. Modification 1 (another example of a structure and manufacturing method of a plurality of bonding electrodes and a shield electrode) 2-2. Modification 2 (another example of a structure and manufacturing method of a plurality of bonding electrodes and a shield electrode) 2-3. Modification 3 (another example of a structure and manufacturing method of a plurality of bonding electrodes and a shield electrode) 2-4. Modification 4 (another example of a structure and manufacturing method of a plurality of bonding electrodes and a shield electrode) 2-5. Modification 5 (another example of a structure and manufacturing method of a plurality of bonding electrodes and a shield electrode) 3. Application Examples 4. Application Examples

[0011] 1. Embodiment Functional Configuration of Imaging Device FIG. 1 is a block diagram showing an example of the functional configuration of an imaging device 1 as a semiconductor device according to an embodiment of the present disclosure.

[0012] The imaging device 1 in FIG. 1 includes, for example, an input section 510A, a row driver section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.

[0013] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, pixel-sharing units 539 each including a plurality of pixels are repeated in an array having a row direction and a column direction. For convenience, the row direction may be referred to as the H direction and the column direction perpendicular to the row direction as the V direction in this specification. In the example of FIG. 1 , one pixel-sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Each of the pixels 541A, 541B, 541C, and 541D has a photodiode PD (shown in FIG. 6 , etc., described below). The pixel-sharing unit 539 is a unit that shares one pixel circuit (the pixel circuit 210 in FIG. 3 , described below). In other words, each of the four pixels (pixels 541A, 541B, 541C, and 541D) has one pixel circuit (the pixel circuit 210, described below). By operating this pixel circuit in a time-division manner, pixel signals from each of the pixels 541A, 541B, 541C, and 541D are sequentially read out. The pixels 541A, 541B, 541C, and 541D are arranged, for example, in two rows and two columns. The pixel array section 540 is provided with the pixels 541A, 541B, 541C, and 541D, as well as multiple row drive signal lines 542 and multiple vertical signal lines (column readout lines) 543. The row drive signal line 542 drives the pixels 541 included in each of multiple pixel-sharing units 539 arranged side by side in the row direction in the pixel array section 540. The row drive signal line 542 drives each pixel arranged side by side in the row direction within the pixel-sharing unit 539. As will be described in detail later with reference to FIG. 4 , the pixel-sharing unit 539 is provided with multiple transistors. To drive each of these multiple transistors, multiple row drive signal lines 542 are connected to one pixel-sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal line (column readout line) 543. Pixel signals are read out via the vertical signal line (column readout line) 543 from each of the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539.

[0014] The row driving unit 520 includes, for example, a row address control unit that determines the position of the row for pixel driving, in other words, a row decoder unit, and a row driving circuit unit that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0015] The column signal processing unit 550 includes, for example, a load circuit unit that is connected to the vertical signal line 543 and forms a source follower circuit together with the pixels 541A, 541B, 541C, and 541D (pixel-sharing units 539). The column signal processing unit 550 may include an amplifier circuit unit that amplifies the signal read out from the pixel-sharing units 539 via the vertical signal line 543. The column signal processing unit 550 may include a noise processing unit. The noise processing unit removes the system noise level from the signal read out from the pixel-sharing units 539 as a result of photoelectric conversion, for example.

[0016] The column signal processing unit 550 includes, for example, an analog-to-digital converter (ADC). The analog-to-digital converter converts the signal read from the pixel sharing unit 539 or the analog signal that has undergone the noise processing into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. The comparator unit compares the analog signal to be converted with a reference signal to be compared with the analog signal. The counter unit measures the time until the comparison result of the comparator unit is inverted. The column signal processing unit 550 may also include a horizontal scanning circuit unit that controls scanning of the readout columns.

[0017] The timing control section 530 supplies signals for controlling timing to the row driving section 520 and the column signal processing section 550 based on the reference clock signal and timing control signal input to the device.

[0018] The image signal processing unit 560 is a circuit that performs various types of signal processing on data obtained as a result of photoelectric conversion, in other words, data obtained as a result of the imaging operation in the imaging device 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0019] One example of signal processing executed by the image signal processing unit 560 is tone curve correction processing, which increases the gradation of the AD converted image data when the data is of a dark subject, and decreases the gradation when the data is of a bright subject. In this case, it is desirable to store in advance in the data storage unit of the image signal processing unit 560 characteristic data of the tone curve based on which the gradation of the image data is corrected.

[0020] The input unit 510A is for inputting, for example, the reference clock signal, timing control signal, and characteristic data from outside the device to the imaging device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, for storage in a data storage unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0021] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is for inputting a signal input to the input terminal 511 into the imaging device 1. The input amplitude change unit 513 changes the amplitude of the signal input by the input circuit unit 512 to an amplitude that is easily usable inside the imaging device 1. The input data conversion circuit unit 514 changes the arrangement of the data string of the input data. The input data conversion circuit unit 514 is configured, for example, by a serial-parallel conversion circuit. This serial-parallel conversion circuit converts a serial signal received as input data into a parallel signal. Note that the input amplitude change unit 513 and the input data conversion circuit unit 514 may be omitted from the input unit 510A. The power supply unit supplies power set to various voltages required inside the imaging device 1 based on power supplied from an external source to the imaging device 1.

[0022] When the imaging device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit that receives data from the external memory device, such as a flash memory, an SRAM, or a DRAM.

[0023] The output unit 510B outputs image data to the outside of the device. This image data may be, for example, image data captured by the imaging device 1 or image data that has been signal-processed by the image signal processing unit 560. The output unit 510B includes, for example, an output data conversion circuit unit 515, an output amplitude change unit 516, an output circuit unit 517, and an output terminal 518.

[0024] The output data conversion circuit unit 515 is configured, for example, by a parallel-serial conversion circuit, and converts parallel signals used inside the imaging device 1 into serial signals. The output amplitude change unit 516 changes the amplitude of the signals used inside the imaging device 1. Signals with changed amplitudes are easier to use in external devices connected to the outside of the imaging device 1. The output circuit unit 517 is a circuit that outputs data from inside the imaging device 1 to outside the device, and the output circuit unit 517 drives wiring outside the imaging device 1 connected to an output terminal 518. Data is output from the imaging device 1 to outside the device through the output terminal 518. The output data conversion circuit unit 515 and the output amplitude change unit 516 may be omitted from the output unit 510B.

[0025] When the imaging device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit that outputs data to the external memory device, such as a flash memory, an SRAM, or a DRAM.

[0026] [Schematic Configuration of Image Capturing Device 1] FIGS. 2 and 3 show an example of the schematic configuration of the image capturing device 1. The image capturing device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). FIG. 2 shows a schematic planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300, while FIG. 3 shows a schematic cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 stacked one on top of the other. FIG. 3 corresponds to the cross-sectional configuration taken along line A-A' in FIG. 2. The image capturing device 1 is a three-dimensional image capturing device configured by bonding together three substrates (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the surrounding interlayer insulating film is referred to as the wiring layer (100T, 200T, 300T) provided on each substrate (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, with the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S arranged in this order along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrows in FIG. 3 indicate the direction of incidence of light L into the imaging device 1. For convenience, in the following cross-sectional views, the light incident side of the imaging device 1 may be referred to as "bottom," "lower side," or "bottom," and the side opposite the light incident side may be referred to as "top," "upper side," or "upper." Furthermore, for convenience, in the present specification, with respect to a substrate having a semiconductor layer and a wiring layer, the wiring layer side may be referred to as the front surface, and the semiconductor layer side may be referred to as the back surface. The descriptions in the specification are not limited to the above-mentioned terms. The imaging device 1 is, for example, a back-illuminated imaging device in which light is incident from the back surface side of the first substrate 100 having a photodiode.

[0027] The pixel array section 540 and the pixel-sharing unit 539 included in the pixel array section 540 are both configured using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel-sharing unit 539. Each of these pixels 541A, 541B, 541C, and 541D has a photodiode (a photodiode PD, described below) and a transfer transistor (a transfer transistor TR, described below). The second substrate 200 is provided with a pixel circuit (a pixel circuit 210, described below) included in the pixel-sharing unit 539. The pixel circuit reads pixel signals transferred from the photodiodes of the pixels 541A, 541B, 541C, and 541D via the transfer transistors or resets the photodiodes. In addition to these pixel circuits, the second substrate 200 also has a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further includes a power supply line 544 (such as a power supply line VDD described below) extending in the row direction. The third substrate 300 includes, for example, an input unit 510A, a row driver 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. The row driver 520 is provided, for example, in a region that partially overlaps with the pixel array unit 540 in the stacking direction (hereinafter simply referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driver 520 is provided, in the stacking direction, in a region that overlaps with the vicinity of an end of the pixel array unit 540 in the H direction. The column signal processing unit 550 is provided, for example, in a region that partially overlaps with the pixel array unit 540 in the stacking direction. More specifically, the column signal processing unit 550 is provided in a region that overlaps with the vicinity of the end of the pixel array unit 540 in the V direction in the stacking direction. Although not shown, the input unit 510A and the output unit 510B may be provided in a portion other than the third substrate 300, for example, on the second substrate 200. Alternatively, the input unit 510A and the output unit 510B may be provided on the back surface (light incident surface) side of the first substrate 100.The pixel circuits provided on the second substrate 200 may also be called pixel transistor circuits, pixel transistor groups, pixel transistors, pixel readout circuits, or readout circuits. In this specification, the term pixel circuits will be used.

[0028] The first substrate 100 and the second substrate 200 are electrically connected, for example, via a plurality of contact portions (a plurality of bonding electrodes 124, 215 described below) (see, for example, FIG. 8A ), as will be described in detail later. The second substrate 200 and the third substrate 300 are electrically connected, for example, via contact portions 201, 202, 301, and 302. The second substrate 200 is provided with contact portions 201 and 202, and the third substrate 300 is provided with contact portions 301 and 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R in which the plurality of contact portions 201 are provided, and a contact region 202R in which the plurality of contact portions 202 are provided. The third substrate 300 has a contact region 301R in which a plurality of contact portions 301 are provided and a contact region 302R in which a plurality of contact portions 302 are provided. The contact regions 201R and 301R are provided between the pixel array section 540 and the row driver section 520 in the stacking direction, as shown in FIG. 3 , for example. In other words, the contact regions 201R and 301R are provided, for example, in a region where the row driver section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region adjacent thereto. The contact regions 201R and 301R are disposed, for example, at the end of such a region in the H direction. In the third substrate 300, the contact region 301R is provided, for example, at a position overlapping with a part of the row driver section 520, specifically, the end of the row driver section 520 in the H direction. The contact units 201 and 301 connect, for example, a row drive unit 520 provided on the third substrate 300 and a row drive signal line 542 provided on the second substrate 200. The contact units 201 and 301 may connect, for example, an input unit 510A provided on the third substrate 300 to a power supply line 544 and a reference potential line (a reference potential line VSS described below). The contact regions 202R and 302R are provided between the pixel array unit 540 and the column signal processing unit 550 in the stacking direction.In other words, the contact regions 202R and 302R are provided, for example, in a region where the column signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, or in a region adjacent thereto. The contact regions 202R and 302R are disposed, for example, at the end of such a region in the V direction. On the third substrate 300, for example, the contact region 301R is provided in a position overlapping with a part of the column signal processing unit 550, specifically, the end of the column signal processing unit 550 in the V direction. The contact regions 202 and 302 are used to connect pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion in the photodiodes) output from each of the multiple pixel sharing units 539 included in the pixel array unit 540 to the column signal processing unit 550 provided on the third substrate 300. The pixel signals are sent from the second substrate 200 to the third substrate 300.

[0029] As described above, FIG. 3 is an example cross-sectional view of the imaging device 1. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, the contact portions 201, 202, 301, and 302 are formed using electrodes made of a conductive material. The conductive material is formed, for example, of a metal material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate 200 and the third substrate 300 by directly bonding wiring formed as electrodes, for example, thereby enabling input and / or output of signals between the second substrate 200 and the third substrate 300.

[0030] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided in a desired location. For example, as described as the contact regions 201R, 202R, 301R, and 302R in FIG. 3 , the electrical connection portion may be provided in a region that overlaps with the pixel array section 540 in the stacking direction. The electrical connection portion may also be provided in a region that does not overlap with the pixel array section 540 in the stacking direction. Specifically, the electrical connection portion may be provided in a region that overlaps with a peripheral portion disposed outside the pixel array section 540 in the stacking direction.

[0031] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200. The connection holes H1 and H2 are provided outside the pixel array section 540 (or the portion overlapping the pixel array section 540). For example, the connection hole H1 is disposed outside the pixel array section 540 in the H direction, and the connection hole H2 is disposed outside the pixel array section 540 in the V direction. For example, the connection hole H1 reaches the input section 510A provided on the third substrate 300, and the connection hole H2 reaches the output section 510B provided on the third substrate 300. The connection holes H1 and H2 may be hollow or may at least partially contain a conductive material. For example, a configuration is possible in which bonding wires are connected to electrodes formed as the input section 510A and / or the output section 510B. Alternatively, the electrodes formed as the input portion 510A and / or the output portion 510B may be connected to the conductive material provided in the connection holes H1 and H2. The conductive material provided in the connection holes H1 and H2 may be embedded in part or all of the connection holes H1 and H2, or the conductive material may be formed on the side walls of the connection holes H1 and H2.

[0032] 3 shows a structure in which the input unit 510A and the output unit 510B are provided on the third substrate 300, but this is not limiting. For example, the input unit 510A and / or the output unit 510B can be provided on the second substrate 200 by sending signals from the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T. Similarly, the input unit 510A and / or the output unit 510B can be provided on the first substrate 100 by sending signals from the second substrate 200 to the first substrate 100 via the wiring layers 100T and 200T.

[0033] 4 is an equivalent circuit diagram showing an example of the configuration of the pixel-shared unit 539. The pixel-shared unit 539 includes a plurality of pixels 541 (four pixels 541A, 541B, 541C, and 541D are shown in FIG. 4 ), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 543 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. As described above, the pixel-shared unit 539 operates one pixel circuit 210 in a time-division manner to sequentially output pixel signals of each of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel-shared unit 539 to the vertical signal line 543. A state in which one pixel circuit 210 is connected to multiple pixels 541 and the pixel signals of these multiple pixels 541 are output in a time-division manner by one pixel circuit 210 is said to be "multiple pixels 541 sharing one pixel circuit 210."

[0034] The pixels 541A, 541B, 541C, and 541D have common components. Hereinafter, in order to distinguish the components of the pixels 541A, 541B, 541C, and 541D from one another, the identification number 1 is added to the end of the reference numeral for the component of pixel 541A, the identification number 2 is added to the end of the reference numeral for the component of pixel 541B, the identification number 3 is added to the end of the reference numeral for the component of pixel 541C, and the identification number 4 is added to the end of the reference numeral for the component of pixel 541D. When it is not necessary to distinguish the components of the pixels 541A, 541B, 541C, and 541D from one another, the identification numbers added to the end of the reference numerals for the components of pixels 541A, 541B, 541C, and 541D are omitted.

[0035] Each of the pixels 541A, 541B, 541C, and 541D includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. The cathode of each of the photodiodes PD (PD1, PD2, PD3, and PD4) is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD photoelectrically converts incident light and generates a charge corresponding to the amount of light received. The transfer transistors TR (transfer transistors TR1, TR2, TR3, and TR4) are, for example, n-type complementary metal oxide semiconductor (CMOS) transistors. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate is electrically connected to a drive signal line. This drive signal line is one of multiple row drive signal lines 542 (see FIG. 1 ) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusions FD1, FD2, FD3, and FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-to-voltage conversion means that generates a voltage corresponding to the amount of charge.

[0036] The four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in one pixel-shared unit 539 are electrically connected to each other and to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is one of the multiple row drive signal lines 542 connected to one pixel-shared unit 539. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. This drive signal line is one of the multiple row drive signal lines 542 connected to one pixel-shared unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 543, and the gate of the selection transistor SEL is connected to a drive signal line. This drive signal line is one of the multiple row drive signal lines 542 connected to one pixel sharing unit 539.

[0037] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and as shown in FIG. 6 (described later), extends from the surface of the semiconductor layer (semiconductor layer 100S in FIG. 6 (described later)) to a depth reaching the PD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplification transistor AMP is connected to a vertical signal line 543 via the selection transistor SEL. In the column signal processing unit 550, the amplification transistor AMP forms a source follower together with a load circuit unit connected to the vertical signal line 543. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.

[0038] The FD conversion gain switching transistor FDG is used to change the gain of charge-to-voltage conversion in the floating diffusion FD. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, when performing charge-to-voltage conversion, if the capacitance (FD capacitance C) of the floating diffusion FD is large, the V when converted to a voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, pixel signals are large, so if the FD capacitance C is not large, the floating diffusion FD cannot fully absorb the charge from the photodiode PD. Furthermore, the FD capacitance C must be large so that the V when converted to a voltage by the amplifier transistor AMP does not become too large (in other words, so that it becomes small). Taking these factors into consideration, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, increasing the overall FD capacitance C. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the FD conversion gain switching transistor FDG on and off, it is possible to change the FD capacitance C and switch the conversion efficiency. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0039] It is also possible to configure the pixel circuit 210 without the FD conversion gain switching transistor FDG. In this case, for example, the pixel circuit 210 is configured with three transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one pixel transistor, for example, the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0040] The select transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the select transistor SEL. The source of the select transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the select transistor SEL is electrically connected to a row drive signal line 542. The source of the amplifier transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to a vertical signal line 543, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. Although not shown, the number of pixels 541 sharing one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0041] FIG. 5 shows an example of a connection between multiple pixel-sharing units 539 and vertical signal lines 543. For example, four pixel-sharing units 539 arranged in a column direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups. For simplicity of explanation, FIG. 5 shows an example in which each of the four groups includes one pixel-sharing unit 539. However, each of the four groups may include multiple pixel-sharing units 539. In this way, in the imaging device 1, the multiple pixel-sharing units 539 arranged in the column direction may be divided into groups including one or more pixel-sharing units 539. For example, the vertical signal line 543 and the column signal processing unit 550 are connected to each of these groups, so that pixel signals can be simultaneously read out from each group. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to multiple pixel-sharing units 539 arranged in a column direction. In this case, pixel signals are sequentially read out in a time-division manner from the multiple pixel-sharing units 539 connected to one vertical signal line 543.

[0042] [Specific Configuration of Imaging Device] FIG. 6 shows an example of a cross-sectional configuration perpendicular to the main surfaces of the first substrate 100, second substrate 200, and third substrate 300 of the imaging device 1. FIG. 6 is a schematic representation to facilitate understanding of the positional relationships of the components, and may differ from the actual cross section. In the imaging device 1, the first substrate 100, second substrate 200, and third substrate 300 are stacked in this order. The imaging device 1 further includes a light-receiving lens 401 on the back side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the light-receiving lens 401 and the first substrate 100. The light-receiving lens 401 is provided for each of the pixels 541A, 541B, 541C, and 541D, for example. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 has a pixel array section 540 arranged in the center and a peripheral section 540B arranged outside the pixel array section 540.

[0043] The first substrate 100 has, in order from the light receiving lens 401 side, an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in and near a portion of the surface (the surface on the wiring layer 100T side), and an n-type semiconductor region 114 in the remaining region (a region deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 form a pn junction photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0044] 7A shows an example of the planar configuration of the first substrate 100. Fig. 7A mainly shows the planar configuration of the pixel isolation portion 117, photodiode PD, floating diffusion FD, VSS contact region 118, and transfer transistor TR of the first substrate 100. The configuration of the first substrate 100 will be described using Fig. 7A together with Fig. 6.

[0045] A floating diffusion FD and a VSS contact region 118 are provided near the surface of the semiconductor layer 100S. The floating diffusion FD is configured by an n-type semiconductor region provided in the p-well layer 115. The floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D are provided close to each other in the center of the pixel-sharing unit 539, for example, as shown in FIG. 7A . As will be described in detail later, the four floating diffusions (floating diffusions FD1, FD2, FD3, and FD4) included in this pixel-sharing unit 539 are electrically connected to each other via electrical connection means (pad portions 120, described later) within the first substrate 100 (more specifically, within the wiring layer 100T). Furthermore, the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via an electrical means. In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion FD is electrically connected to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG by this electrical means.

[0046] The VSS contact region 118 is a region electrically connected to the reference potential line VSS and is disposed apart from the floating diffusion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion FD is disposed at one end of each pixel in the V direction, and the VSS contact region 118 is disposed at the other end. The VSS contact region 118 is formed of, for example, a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. This allows a reference potential to be supplied to the semiconductor layer 100S.

[0047] The first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a VSS contact region 118, and a transfer transistor TR. The photodiode PD, floating diffusion FD, VSS contact region 118, and transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front surface side of the semiconductor layer 100S (the side opposite the light incident surface, the second substrate 200 side). The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front surface of the semiconductor layer 100S and a vertical portion TGa provided within the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided within the n-type semiconductor region 114. By configuring the transfer transistor TR using such a vertical transistor, transfer failure of pixel signals is less likely to occur, and the readout efficiency of pixel signals can be improved.

[0048] The horizontal portion TGb of the transfer gate TG extends, for example, in the H direction from a position facing the vertical portion TGa toward the center of the pixel sharing unit 539. This allows the H direction position of the through electrode (the through electrode TGV described below) that reaches the transfer gate TG to be closer to the H direction positions of the through electrodes (the through electrodes 120E and 121E described below) that are connected to the floating diffusion FD and the VSS contact region 118. For example, the multiple pixel sharing units 539 provided on the first substrate 100 have the same configuration.

[0049] The transfer transistor TR may be configured as a planar transistor. In this case, for example, a transfer gate TG is provided on the surface of the semiconductor layer 100S. For example, the side surfaces of the transfer gate TG are covered with sidewalls SW. The sidewalls SW include, for example, silicon nitride (SiN). A gate insulating film is provided between the semiconductor layer 100S and the transfer gate TG. The transfer gates TG (transfer gates TG1, TG2, TG3, and TG4) of the pixels 541A, 541B, 541C, and 541D are provided, for example, so as to surround the floating diffusion FD in a planar view (see, for example, FIG. 6, which will be described later).

[0050] The semiconductor layer 100S is provided with a pixel separator 117 that separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 is formed to extend in the normal direction of the semiconductor layer 100S (a direction perpendicular to the surface of the semiconductor layer 100S). As shown in FIGS. 7A and 7B , the pixel separator 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from one another, and has, for example, a lattice-like planar shape. The pixel separator 117 electrically and optically separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 includes, for example, a light-shielding film 117A and an insulating film 117B. The light-shielding film 117A is made of, for example, tungsten (W) or the like. The insulating film 117B is provided between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is made of, for example, silicon oxide (SiO). The pixel separating portion 117 has, for example, a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separating portion 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may have a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S. The pixel separating portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

[0051] The semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S, and is disposed between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on a side surface of the pixel separating section 117, specifically, between the pixel separating section 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are formed of, for example, a p-type semiconductor region.

[0052] A fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. An electric field induced by the fixed charge film 112 forms a first pinning region 113 of the hole accumulation layer at the interface on the light-receiving surface (back surface) side of the semiconductor layer 100S. This suppresses the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor layer 100S. The fixed charge film 112 is formed, for example, from an insulating film having a negative fixed charge. Examples of materials for this insulating film having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0053] A light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. This light-shielding film 117A may be provided continuously with the light-shielding film 117A that constitutes the pixel separating section 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separating section 117 in the semiconductor layer 100S. The insulating film 111 is provided so as to cover this light-shielding film 117A. The insulating film 111 is made of, for example, silicon oxide.

[0054] The wiring layer 100T, which is provided between the semiconductor layer 100S and the second substrate 200, includes, in this order from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, and an interlayer insulating film 123. Wirings 120D and 121D extending in the thickness direction are provided within the interlayer insulating film 123. The lower ends of the wirings 120D and 121R are connected to the pad portions 120 and 121, respectively, and the upper ends are connected to a plurality of bonding electrodes 124 provided on the surface 123S of the interlayer insulating film 123, which is bonded to the second substrate 200. The horizontal portion TGb of the transfer gate TG is provided, for example, in this wiring layer 100T. The interlayer insulating film 119 is provided over the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is made of, for example, a silicon oxide film. The configuration of the wiring layer 100T is not limited to the above, and may be any configuration having wiring and an insulating film.

[0055] 7B shows the configuration of the pad portions 120 and 121 along with the planar configuration shown in FIG. 7A. The pad portions 120 and 121 are provided in selective regions on the interlayer insulating film 119. The pad portion 120 is used to connect the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to one another. The pad portion 120 is disposed, for example, for each pixel sharing unit 539 in the center of the pixel sharing unit 539 in a planar view. The pad portion 120 is disposed so as to straddle the pixel separating portion 117 and overlap at least a portion of each of the floating diffusions FD1, FD2, FD3, and FD4. Specifically, the pad section 120 is formed in a region that overlaps, in a direction perpendicular to the surface of the semiconductor layer 100S, at least a portion of each of the plurality of floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) that share the pixel circuit 210 and at least a portion of the pixel isolation section 117 formed between the plurality of photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) that share the pixel circuit 210. Connection vias 120C are provided in the interlayer insulating film 119 to electrically connect the pad section 120 to the floating diffusions FD1, FD2, FD3, and FD4. The connection vias 120C are provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a portion of the pad section 120 is embedded in the connection vias 120C, thereby electrically connecting the pad section 120 to the floating diffusions FD1, FD2, FD3, and FD4.

[0056] The pad portion 121 is used to connect the multiple VSS contact regions 118 to each other. For example, the pad portion 121 electrically connects the VSS contact regions 118 provided in pixels 541C and 541D of one pixel sharing unit 539 adjacent to each other in the V direction with the VSS contact regions 118 provided in pixels 541A and 541B of the other pixel sharing unit 539. The pad portion 121 is provided, for example, to straddle the pixel isolation portion 117 and is arranged to overlap at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps, in a direction perpendicular to the surface of the semiconductor layer 100S, with at least a portion of each of the multiple VSS contact regions 118 and at least a portion of the pixel isolation portion 117 formed between the multiple VSS contact regions 118. The interlayer insulating film 119 is provided with a connection via 121C for electrically connecting the pad portion 121 and the VSS contact region 118. The connection via 121C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a portion of the pad portion 121 is embedded in the connection via 121C, thereby electrically connecting the pad portion 121 and the VSS contact region 118. For example, the pad portion 120 and the pad portion 121 of each of the multiple pixel sharing units 539 aligned in the V direction are arranged at approximately the same position in the H direction.

[0057] By providing the pad section 120, it is possible to reduce the amount of wiring for connecting each floating diffusion FD to the pixel circuit 210 (for example, the gate electrode of the amplification transistor AMP) across the entire chip. Similarly, by providing the pad section 121, it is possible to reduce the amount of wiring for supplying potential to each VSS contact region 118 across the entire chip. This makes it possible to reduce the area of ​​the entire chip, suppress electrical interference between wiring in miniaturized pixels, and / or reduce costs by reducing the number of components.

[0058] The pad portions 120, 121 can be provided at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pad portions 120, 121 can be provided on either the wiring layer 100T or the insulating region 212 of the semiconductor layer 200S. When provided on the wiring layer 100T, the pad portions 120, 121 may be in direct contact with the semiconductor layer 100S. Specifically, the pad portions 120, 121 may be configured to be directly connected to at least a portion of each of the floating diffusion FD and / or VSS contact region 118. Alternatively, connection vias 120C, 121C may be provided from each of the floating diffusion FD and / or VSS contact region 118 connected to the pad portions 120, 121, and the pad portions 120, 121 may be provided at desired positions in the insulating region 212 of the wiring layer 100T and the semiconductor layer 200S.

[0059] In particular, when the pad portions 120, 121 are provided in the wiring layer 100T, it is possible to reduce the wiring connected to the floating diffusion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S. This makes it possible to reduce, for example, the area of ​​the insulating region 212 in the second substrate 200 on which the pixel circuit 210 is formed, for forming the through electrode 120E for connecting the floating diffusion FD to the pixel circuit 210. This makes it possible to ensure a large area for the second substrate 200 on which the pixel circuit 210 is formed. By ensuring the area for the pixel circuit 210, it is possible to form a large pixel transistor, which can contribute to improving image quality by reducing noise, etc.

[0060] In particular, when an FTI structure is used for the pixel separation section 117, it is preferable to provide a floating diffusion FD and / or a VSS contact region 118 in each pixel 541, and therefore, by using the configuration of the pad sections 120, 121, the wiring connecting the first substrate 100 and the second substrate 200 can be significantly reduced.

[0061] 7B , for example, pad portions 120 connected to multiple floating diffusions FD and pad portions 121 connected to multiple VSS contact regions 118 are alternately arranged linearly in the V direction. Furthermore, the pad portions 120 and 121 are formed in positions surrounded by multiple photodiodes PD, multiple transfer gates TG, and multiple floating diffusions FD. This allows elements other than the floating diffusions FD and VSS contact regions 118 to be freely arranged on the first substrate 100 on which multiple elements are formed, thereby improving the efficiency of the layout of the entire chip. Furthermore, symmetry is ensured in the layout of elements formed in each pixel sharing unit 539, thereby suppressing variations in the characteristics of each pixel 541.

[0062] The pad portions 120 and 121 are made of, for example, polysilicon (Poly Si), more specifically, doped polysilicon to which impurities are added. The pad portions 120 and 121 are preferably made of a highly heat-resistant conductive material such as polysilicon, tungsten (W), titanium (Ti), or titanium nitride (TiN). This makes it possible to form the pixel circuit 210 after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100.

[0063] The pad portions 120 and 121 may be made of a metal material such as tantalum nitride (TaN), aluminum (Al), or copper (Cu).

[0064] The passivation film 122 is provided over the entire surface of the semiconductor layer 100S so as to cover the pad portions 120 and 121. The passivation film 122 is made of, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 with the passivation film 122 in between. This interlayer insulating film 123 is provided over the entire surface of the semiconductor layer 100S. The interlayer insulating film 123 is made of, for example, a silicon oxide (SiO) film.

[0065] The light-receiving lens 401 faces the semiconductor layer 100S, for example, with the fixed charge film 112 and the insulating film 111 therebetween. The light-receiving lens 401 is provided at a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D, for example.

[0066] As shown in FIG. 6 , the second substrate 200 includes, in this order from the first substrate 100 side, a wiring layer 200T-1, a semiconductor layer 200S, and a wiring layer 200T-2. The semiconductor layer 200S is made of a silicon substrate. A well region 211 is provided in the semiconductor layer 200S across its thickness. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 includes a pixel circuit 210 arranged for each pixel sharing unit 539. The pixel circuit 210 is provided, for example, on the front surface side (the wiring layer 200T-2 side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 such that the back surface side (the semiconductor layer 200S side) of the second substrate 200 faces the front surface side (the wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is attached to the first substrate 100 face-to-back.

[0067] The second substrate 200 is provided with an insulating region 212 that divides the semiconductor layer 200S, and an element isolation region 213 that is provided in a part of the semiconductor layer 200S in the thickness direction. For example, in the insulating region 212 that is provided between two pixel circuits 210 adjacent to each other in the H direction, the through electrodes 120E and 121E and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) of two pixel sharing units 539 connected to the two pixel circuits 210 are arranged.

[0068] The insulating region 212 has approximately the same thickness as the semiconductor layer 200S. The semiconductor layer 200S is divided by this insulating region 212. The through electrodes 120E, 121E and the through electrode TGV are arranged in this insulating region 212. The insulating region 212 is made of, for example, silicon oxide.

[0069] The through electrodes 120E and 121E are provided so as to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wiring (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4) of the wiring layer 200T-2. The through electrodes 120E and 121E are provided so as to penetrate the insulating region 212 and the interlayer insulating film 221, and their lower ends are connected to a plurality of bonding electrodes 215 provided on the bonding surface (surface 221S of the interlayer insulating film 221) of the wiring layer 200T-1 that is bonded to the first substrate 100. The through electrodes 120E, together with the wiring 120D and the bonding electrodes 124 and 215, are intended to electrically connect the pad section 120 and the pixel circuit 210. That is, the floating diffusion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 by the wiring 120D, the through electrode 120E, and the bonding electrodes 124 and 215. The through electrode 121E, together with the wiring 121D and the bonding electrodes 124 and 215, is intended to electrically connect the pad portion 121 to the reference potential line VSS of the wiring layer 200T. That is, the wiring 121D, the through electrode 121E, and the bonding electrodes 124 and 215 electrically connect the VSS contact region 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

[0070] The through electrode TGV is provided to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring layer 200T. Like the through electrodes 120E and 121E, this through electrode TGV is provided to penetrate the insulating region 212, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119 via bonding electrodes 124 and 215 provided on the bonding surface between the first substrate 100 and the second substrate 200, and its lower end is connected to the transfer gate TG. Such through electrodes TGV are intended to electrically connect the transfer gates TG (transfer gates TG1, TG2, TG3, TG4) of the pixels 541A, 541B, 541C, 541D to the wiring of the wiring layer 200T (part of the row drive signal line 542, specifically, the wiring TRG1, TRG2, TRG3, TRG4 in FIG. 11 described later). That is, the through electrodes TGV electrically connect the transfer gates TG of the first substrate 100 to the wiring TRG of the second substrate 200, and a drive signal is sent to each of the transfer transistors TR (transfer transistors TR1, TR2, TR3, TR4).

[0071] The insulating region 212 is a region in which the through electrodes 120E, 121E and the through electrodes TGV for electrically connecting the first substrate 100 and the second substrate 200 are provided insulated from the semiconductor layer 200S. For example, in the insulating region 212 provided between two pixel circuits 210 (pixel sharing units 539) adjacent to each other in the H direction, the through electrodes 120E, 121E and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) connected to the two pixel circuits 210 are arranged.

[0072] The element isolation region 213 is provided on the surface side of the semiconductor layer 200S. The element isolation region 213 has an STI (Shallow Trench Isolation) structure. In this element isolation region 213, the semiconductor layer 200S is dug in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is buried in this dug portion. This insulating film is made of, for example, silicon oxide. The element isolation region 213 separates the multiple transistors that make up the pixel circuit 210 according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (deep in the semiconductor layer 200S).

[0073] Here, with reference to Figures 7A, 7B, and 10, the difference between the outer shape (outer shape in the substrate planar direction) of the pixel sharing unit 539 on the first substrate 100 and the outer shape of the pixel sharing unit 539 on the second substrate 200 will be described.

[0074] In the imaging device 1, pixel-sharing units 539 are provided across both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel-sharing unit 539 provided on the first substrate 100 and the outer shape of the pixel-sharing unit 539 provided on the second substrate 200 are different from each other.

[0075] 7A and 7B , the outlines of the pixels 541A, 541B, 541C, and 541D are represented by dashed dotted lines, and the outline shape of the pixel-sharing unit 539 is represented by a thick line. For example, the pixel-sharing unit 539 of the first substrate 100 is configured with two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to each other in the V direction. In other words, the pixel-sharing unit 539 of the first substrate 100 is configured with four adjacent pixels 541 arranged in two rows and two columns, and the pixel-sharing unit 539 of the first substrate 100 has a substantially square outline shape. In the pixel array section 540, such pixel sharing units 539 are arranged adjacent to each other at a pitch of two pixels in the H direction (a pitch equivalent to two pixels 541) and at a pitch of two pixels in the V direction (a pitch equivalent to two pixels 541).

[0076] 10 and 11 , the outlines of the pixels 541A, 541B, 541C, and 541D are represented by dashed-dotted lines, and the outline shape of the pixel-sharing unit 539 is represented by a thick line. For example, the outline shape of the pixel-sharing unit 539 of the second substrate 200 is smaller in the H direction than the pixel-sharing unit 539 of the first substrate 100 and larger in the V direction than the pixel-sharing unit 539 of the first substrate 100. For example, the pixel-sharing unit 539 of the second substrate 200 is formed to have a size (area) equivalent to one pixel in the H direction, and is formed to have a size equivalent to four pixels in the V direction. In other words, the pixel-sharing unit 539 of the second substrate 200 is formed to have a size equivalent to adjacent pixels arranged in one row and four columns, and the pixel-sharing unit 539 of the second substrate 200 has a substantially rectangular outline shape.

[0077] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged side by side in this order in the V direction. By providing each pixel circuit 210 with a substantially rectangular outer shape as described above, it is possible to arrange four transistors (the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG) side by side in one direction (the V direction in FIG. 10 ). This allows the drain of the amplification transistor AMP and the drain of the reset transistor RST to share a single diffusion region (a diffusion region connected to the power supply line VDD). For example, it is also possible to provide the formation region of each pixel circuit 210 in a substantially square shape. In this case, two transistors are arranged along one direction, making it difficult to share a single diffusion region for the drain of the amplification transistor AMP and the drain of the reset transistor RST. Therefore, providing the formation region of the pixel circuit 210 in a substantially rectangular shape makes it easier to arrange the four transistors closely together, thereby reducing the formation region of the pixel circuit 210. In other words, the pixels can be miniaturized. Also, when it is not necessary to reduce the area in which the pixel circuit 210 is formed, the area in which the amplifier transistor AMP is formed can be increased, thereby making it possible to suppress noise.

[0078] The amplifier transistor AMP preferably has a three-dimensional structure, such as a fin type. For example, a fin type amplifier transistor AMP has a fin formed from a portion of the semiconductor layer 200S, a gate electrode having three planes surrounding the fin, and a gate insulating film provided between the gate electrode and the fin. A three-dimensional transistor refers to a transistor having multiple planes of the gate electrode facing the channel, or a transistor having a curved surface of the gate electrode surrounding the channel. Such a three-dimensional transistor can have a larger effective gate width than a planar transistor when it has the same footprint as a planar transistor. Therefore, a larger current flows through the three-dimensional transistor, resulting in a higher transconductance gm. This allows for a higher operating speed than a planar transistor. In addition, it is also possible to reduce random noise (RN). Furthermore, a three-dimensional transistor has a larger gate area than a planar transistor, thereby reducing random telegraph signal (RTS) noise.

[0079] By using such a transistor with a three-dimensional structure for at least one of the amplifier transistor AMP, the select transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG, the transistor characteristics can be improved, and image quality, for example, can be improved. In particular, by configuring the amplifier transistor AMP using a transistor with a three-dimensional structure, noise can be effectively reduced, making it possible to improve image quality. Furthermore, all of the amplifier transistor AMP, the select transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG may be configured using transistors with a three-dimensional structure. In this case, manufacturing of the pixel circuit 210 becomes easier.

[0080] For example, near the surface of the semiconductor layer 200S, in addition to the select transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided. The VSS contact region 218 is configured, for example, by a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through-electrode 121E. This VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switching transistor FDG, with the element isolation region 213 interposed therebetween.

[0081] Next, with reference to Figures 7B and 10, a description will be given of the positional relationship between the pixel-sharing units 539 provided on the first substrate 100 and the pixel-sharing units 539 provided on the second substrate 200. For example, of two pixel-sharing units 539 aligned in the V direction on the first substrate 100, one pixel-sharing unit 539 (e.g., the upper side of the paper in Figure 7B) is connected to one pixel-sharing unit 539 (e.g., the left side of the paper in Figure 10) of two pixel-sharing units 539 aligned in the H direction on the second substrate 200. For example, of the two pixel-sharing units 539 aligned in the V direction on the first substrate 100, the other pixel-sharing unit 539 (e.g., the lower side of the paper in Figure 7B) is connected to the other pixel-sharing unit 539 (e.g., the right side of the paper in Figure 10) of two pixel-sharing units 539 aligned in the H direction on the second substrate 200.

[0082] For example, in two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is approximately equal to the internal layout of the other pixel sharing unit 539 inverted in the V and H directions.

[0083] The wiring layer 200T-1 is provided on the back surface side of the semiconductor layer 200S facing the first substrate 100, and includes, for example, an interlayer insulating film 221 and a plurality of bonding electrodes 215. The plurality of bonding electrodes 215, together with a plurality of bonding electrodes 124 provided on the surface 123S of the interlayer insulating film 123 constituting the wiring layer 100T, are used to electrically connect the first substrate 100 and the second substrate 200 and to bond the first substrate 100 and the second substrate 200 together. The plurality of bonding electrodes 124 are connected to the through electrodes 120E, 121E, and TGVs, respectively. The interlayer insulating film 221 is made of, for example, silicon oxide.

[0084] The wiring layer 200T-2 is provided on the surface side of the semiconductor layer 200S facing the third substrate 300, and includes, for example, a passivation film 222, an interlayer insulating film 223, and multiple wirings (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4). The passivation film 222 is in contact with, for example, the surface of the semiconductor layer 200S, and covers the entire surface of the semiconductor layer 200S. This passivation film 222 covers the gate electrodes of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 223 is provided between the passivation film 222 and the third substrate 300. This interlayer insulating film 223 separates the multiple wirings (first wiring layer W1, second wiring layer W2, third wiring layer W3, and fourth wiring layer W4). The interlayer insulating film 223 is made of, for example, silicon oxide.

[0085] In the wiring layer 200T-2, for example, from the semiconductor layer 200S side, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact portions 201 and 202 are provided in this order, and these are insulated from each other by an interlayer insulating film 223. The interlayer insulating film 223 is provided with a plurality of connection portions that connect the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 with the layers below them. The connection portions are portions in which a conductive material is embedded in connection holes provided in the interlayer insulating film 223. For example, the interlayer insulating film 223 is provided with a connection portion 218V that connects the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. The connection portion 218V is provided in a position facing the semiconductor layer 200S.

[0086] For example, the first wiring layer W1 connects the through electrode 120E to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, a connection hole reaching the source of the FD conversion gain switching transistor FDG). The first wiring layer W1 connects the through electrode 121E to the connection portion 218V, for example, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S to the VSS contact region 118 of the semiconductor layer 100S.

[0087] The contact portions 201 and 202 may be provided at positions overlapping the pixel array portion 540 in a plan view, or may be provided in a peripheral portion 540B outside the pixel array portion 540. The contact portions 201 and 202 are provided on the surface of the second substrate 200 (the surface on the wiring layer 200T-1 side). The contact portions 201 and 202 are made of a metal such as Cu (copper) or Al (aluminum). The contact portions 201 and 202 are exposed on the surface of the wiring layer 200-1T (the surface on the third substrate 300 side). The contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding the second substrate 200 and the third substrate 300 together.

[0088] 6 shows an example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 200. This peripheral circuit may include a part of the row driving section 520 or a part of the column signal processing section 550. Alternatively, as shown in FIG. 3, the peripheral circuit may not be provided in the peripheral portion 540B of the second substrate 200, and the connection holes H1 and H2 may be provided near the pixel array section 540.

[0089] The third substrate 300 includes, for example, a wiring layer 300T and a semiconductor layer 300S, in this order, from the second substrate 200 side. For example, the surface of the semiconductor layer 300S is provided on the second substrate 200 side. The semiconductor layer 300S is made of a silicon substrate. Circuits are provided on the surface side of the semiconductor layer 300S. Specifically, at least some of the input unit 510A, row driver unit 520, timing control unit 530, column signal processing unit 550, image signal processing unit 560, and output unit 510B are provided on the surface side of the semiconductor layer 300S. The wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, multiple wiring layers separated by this interlayer insulating film, and contact units 301 and 302. The contact portions 301 and 302 are exposed on the surface of the wiring layer 300T (the surface facing the second substrate 200). The contact portion 301 is in contact with the contact portion 201 of the second substrate 200, and the contact portion 302 is in contact with the contact portion 202 of the second substrate 200. The contact portions 301 and 302 are electrically connected to circuits formed in the semiconductor layer 300S (e.g., at least one of the input portion 510A, the row driver portion 520, the timing control portion 530, the column signal processing portion 550, the image signal processing portion 560, and the output portion 510B). The contact portions 301 and 302 are made of metal such as Cu (copper) and aluminum (Al). For example, an external terminal TA is connected to the input portion 510A via a connection hole H1, and an external terminal TB is connected to the output portion 510B via a connection hole H2.

[0090] [Bonding Structure Between Substrates] Fig. 10A is a schematic diagram illustrating a detailed cross-sectional configuration of the bonding surface between the first substrate 100 and the second substrate 200 of the imaging device 1, for example. A plurality of bonding electrodes 124, 215 are provided on the bonding surfaces of the first substrate 100 and the second substrate 200, respectively, and are used for electrically connecting the first substrate 100 and the second substrate 200 and bonding the first substrate 100 and the second substrate 200 together. As shown in Fig. 10A, shield electrodes 125, 216 are further provided between adjacent bonding electrodes 124, 215 on the bonding surfaces of the first substrate 100 and the second substrate 200, respectively. Specifically, the plurality of bonding electrodes 124 and the shield electrode 125 are embedded in an interlayer insulating film 123 constituting a wiring layer 100T that forms the bonding surface of the first substrate 100 with the second substrate 200, and are exposed on the surface of the wiring layer 100T. The plurality of bonding electrodes 215 and the shield electrode 216 are each embedded in an interlayer insulating film 221 constituting the wiring layer 200T-1 that forms the bonding surface of the second substrate 200 with the first substrate 100, and are exposed on the surface of the wiring layer 200T-1. Here, the plurality of bonding electrodes 124 correspond to a specific example of "plurality of first bonding electrodes" in an embodiment of the present disclosure, and the plurality of bonding electrodes 215 correspond to a specific example of "plurality of second bonding electrodes" in an embodiment of the present disclosure. The shield electrode 125 corresponds to a specific example of "first metal layer" in an embodiment of the present disclosure, and the shield electrode 216 corresponds to a specific example of "second metal layer" in an embodiment of the present disclosure.

[0091] 10A illustrates the detailed configuration of the multiple bonding electrodes 124, 215 that bond the first substrate 100 and the second substrate 200 and the shield electrodes 125, 216 provided between adjacent bonding electrodes 124, 215, and does not illustrate wiring connected to each bonding electrode 124, 215 (e.g., wiring 120D, 121D and through electrodes 120E, 121E). Also, although not shown, it is assumed that semiconductor layers 100S, 200S are provided on the opposite side of the bonding surfaces, as shown in FIG. 6. The same applies to the subsequent figures.

[0092] The multiple bonding electrodes 124 include an electrode layer 124A embedded in the interlayer insulating film 123 and a barrier metal film 124B provided between the interlayer insulating film 123 and the electrode layer 124A. The electrode layer 124A is used to electrically connect the first substrate 100 and the second substrate 200 and to bond the first substrate 100 and the second substrate 200 together, and its surface 124SA, together with the interlayer insulating film 123, forms a flat bonding surface with the second substrate 200. The electrode layer 124A is made of a metal such as Cu (copper) or aluminum (Al). The barrier metal film 124B prevents diffusion of the electrode layer 124A into the interlayer insulating film 123, and its surface 124SB is recessed toward the semiconductor layer 100S from the surface 124SA of the electrode layer 124A, which, together with the interlayer insulating film 123, forms the bonding surface with the second substrate 200. The barrier metal film 124B is made of, for example, a single film of Ti (titanium) or Ta (tantalum), or a laminated film of, for example, titanium (Ti) and a metal nitride film such as titanium nitride (TiN).

[0093] The shield electrode 125 reduces signal interference between adjacent bonding electrodes 124. The shield electrode 125 is embedded in the interlayer insulating film 123, and its surface (the surface facing the second substrate 200) 125S, like the barrier metal film 124B of the bonding electrode 124, is recessed toward the semiconductor layer 100S from the surface 124SA of the electrode layer 124A, which forms the bonding surface with the second substrate 200 together with the interlayer insulating film 123. A fixed potential (e.g., GND) is applied to the shield electrode 125. Alternatively, the shield electrode 125 may be electrically floating. Like the barrier metal film 124B, the shield electrode 125 is formed of, for example, a single film of Ti (titanium) or Ta (tantalum), or a laminated film of, for example, titanium (Ti) and a metal nitride film such as titanium nitride (TiN).

[0094] The multiple bonding electrodes 215 include an electrode layer 215A embedded in an interlayer insulating film 221 and a barrier metal film 215B provided between the interlayer insulating film 221 and the electrode layer 215A. The electrode layer 215A is used to electrically connect the first substrate 100 and the second substrate 200 and to bond the first substrate 100 and the second substrate 200 together, and its surface 215SA, together with the interlayer insulating film 221, forms a flat bonding surface with the first substrate 100. The electrode layer 215A is made of a metal such as Cu (copper) or aluminum (Al). The barrier metal film 215B prevents diffusion of the electrode layer 215A into the interlayer insulating film 221, and its surface 215SB is recessed toward the semiconductor layer 200S from the surface 215SA of the electrode layer 215A, which, together with the interlayer insulating film 221, forms the bonding surface with the first substrate 100. The barrier metal film 215B is made of, for example, a single film of Ti (titanium) or Ta (tantalum), or a laminated film of, for example, titanium (Ti) and a metal nitride film such as titanium nitride (TiN).

[0095] The shield electrode 216 reduces signal interference between adjacent bonding electrodes 215. The shield electrode 216 is embedded in the interlayer insulating film 221, and its surface (surface facing the first substrate 100) 216S, like the barrier metal film 215B of the bonding electrode 215, is recessed toward the semiconductor layer 200S from the surface 215SA of the electrode layer 215A, which forms the bonding surface with the first substrate 100 together with the interlayer insulating film 221. A fixed potential (e.g., GND) is applied to the shield electrode 216. Alternatively, the shield electrode 216 may be electrically floating. Like the barrier metal film 215B, the shield electrode 216 is formed of, for example, a single film of Ti (titanium) or Ta (tantalum), or a laminated film of, for example, titanium (Ti) and a metal nitride film such as titanium nitride (TiN).

[0096] 11A and 12A are schematic diagrams illustrating an example of the configuration of the bonding surfaces of two hybrid-bonded substrates as a comparative example of the present embodiment. FIGS. 11B and 12B are schematic diagrams illustrating misalignment at the bonding surfaces of the two substrates shown in FIGS. 11A and 12A, respectively. Multiple bonding electrodes and shield electrodes provided on each of the two substrates, together with the surrounding interlayer insulating film, form a flat bonding surface. Here, the spacing between adjacent bonding electrodes is L1, the width of the multiple bonding electrodes is W1, the width of shield electrodes 1125 and 1216 is W2, and the spacing between the bonding electrodes and the shield electrode is L2.

[0097] If the distance between adjacent bonding electrodes 1124, 1215 is set larger than the width of the bonding electrodes 1124, 1215 (for example, L1 = 600 nm, W1 = 200 nm), the width W2 of the shield electrodes 1125, 1216 is set to 100 nm, and the distance L2 between the bonding electrodes 1124, 1215 and the shield electrodes 1125, 1216 is set to 250 nm, when the misalignment between the two substrates is about 50 nm, the electrode layers 1124A, 1215B formed on the respective bonding surfaces are bonded without any problems as shown in Fig. 11A. However, when the misalignment is, for example, 150 nm, the electrode layers 1124A, 1215B formed on the respective bonding surfaces are no longer bonded as shown in Fig. 11B.

[0098] On the other hand, if the bonding electrodes are enlarged and the distance between the bonding electrodes and the shield electrode is narrowed so that the bonding electrodes can be bonded over the entire bonding surface, for example, if the distance between adjacent bonding electrodes 2124, 2215 is equal to the width of the bonding electrodes 2124, 2215 (e.g., L1 = W1 = 400 nm), the width W2 of the shield electrodes 2125, 2216 is 100 nm, and the distance L2 between the bonding electrodes 2124, 2215 and the shield electrodes 2125, 2216 is 150 nm, when the misalignment between the two substrates is about 50 nm, the electrode layers 2124A, 2215B formed on each bonding surface are bonded without any problems as shown in Figure 12A. However, when a misalignment of, for example, 150 nm occurs, the shield electrodes 2125, 2216 come into contact with the electrode layers 2124A, 2215B formed on each bonding surface as shown in Figure 12B.

[0099] 10B is a schematic diagram illustrating misalignment at the bonding surfaces of the first substrate 100 and the second substrate 200 according to the present embodiment. In this embodiment, a surface 124SB of the barrier metal film 124B and a surface 125S of the shield electrode 125 constituting the bonding electrode 124 are recessed toward the semiconductor layer 100S relative to a surface 124SA of the electrode layer 124A constituting the bonding electrode 124. Similarly, a surface 215SB of the barrier metal film 215B and a surface 216S of the shield electrode 216 constituting the bonding electrode 215 are recessed toward the semiconductor layer 200S relative to a surface 215SA of the electrode layer 215A constituting the bonding electrode 215. As a result, similar to the configuration of the bonding electrodes 2124, 2215 and the shield electrodes 2125, 2216 at the bonding surfaces of the two substrates shown in FIG. 12A , even when L1=W1=400 nm, W2=100 nm, and L2=150 nm, the electrode layers 124A, 215A and the shield electrodes 125, 216 do not come into contact with each other, and bonding between the bonding electrode 124 and the bonding electrode 215 is possible over the entire bonding surface.

[0100] 13A to 13C are schematic diagrams illustrating an example of a planar layout of the bonding electrodes 124, 215 and the shield electrodes 125, 216 on the respective bonding surfaces of the first substrate 100 and the second substrate 200. For example, as shown in FIG. 13A , the shield electrodes 125, 216 are provided on the respective bonding surfaces in a grid pattern so as to continuously surround the bonding electrodes 124, 215 adjacent in the X-axis direction and the Y-axis direction. Alternatively, for example, as shown in FIG. 13B , the shield electrodes 125, 216 may be provided intermittently so as to extend between the bonding electrodes 124, 215 adjacent in the X-axis direction and the Y-axis direction. Alternatively, for example, as shown in FIG. 13C , the shield electrodes 125, 216 may be provided in a dot pattern between the bonding electrodes 124, 215 adjacent in the X-axis direction and the Y-axis direction.

[0101] The above-described configuration of the multiple bonding electrodes 124 , 215 and shield electrodes 125 , 216 on the bonding surface between the first substrate 100 and the second substrate 200 can also be applied to the bonding surface between the second substrate 200 and the third substrate 300 .

[0102] [Method for Manufacturing the Multiple Bonding Electrodes and the Shielding Electrode] Next, an example of a method for manufacturing the multiple bonding electrodes 124, 215 and the shielding electrodes 125, 216 will be described with reference to FIGS. 14A to 14H.

[0103] 14A, a resist film 131 is patterned on a surface 123S of the interlayer insulating film 123. Next, as shown in Fig. 14B, openings H3 and H4 are formed by, for example, dry etching or wet etching, and then the resist film 131 is removed. At this time, the width of the opening H4 in which the shield electrode 125 is formed is set to be narrower than twice the film thickness of a barrier metal film M1, which will be described later.

[0104] Next, as shown in FIG. 14C , a continuous barrier metal film M1 is formed on the surface of the interlayer insulating film 123 and on the side and bottom surfaces of the openings H3 and H4 by, for example, sputtering. At this time, the opening H4 is filled with the barrier metal film M1. Next, as shown in FIG. 14D , a conductive film M2 is formed by, for example, sputtering so as to fill the opening H3. The conductive film M2 may be formed by, for example, electrochemical deposition (ECD). Next, as shown in FIG. 14E , the conductive film M2 formed on the interlayer insulating film 123 is removed by, for example, chemical polishing (CMP), and then CMP is performed again as shown in FIG. 14F . This removes the barrier metal film M1 formed outside the openings H3 and H4, forming a plurality of bonding electrodes 124 and shield electrodes 125, each made of an electrode layer 124A and a barrier metal film 124B, in the openings H3 and H4, and planarizing the surfaces.

[0105] 14G , the barrier metal film 124B made of the barrier metal film M1 and the shield electrode 125 are selectively etched by, for example, dry etching or wet etching. As a result, the surfaces 124SB and 125S of the barrier metal film 124B and the shield electrode 125 are recessed toward the semiconductor layer 100S. Thereafter, CMP is performed again depending on the surface condition of the interlayer insulating film 123 to flatten the surfaces 123S and 124SA of the interlayer insulating film 123 and the electrode layer 124A, which serve as bonding surfaces.

[0106] Using a similar method, a bonding electrode 215 in which the surface 215SB of the barrier metal film 215B is recessed toward the semiconductor layer 200S side and a shield electrode 216 in which the surface 216S is recessed toward the semiconductor layer 200S side are formed on the surface 221S of the interlayer insulating film 221.

[0107] 14H , the interlayer insulating film 123 provided with the plurality of bonding electrodes 124 and the shield electrode 125 and the interlayer insulating film 221 provided with the plurality of bonding electrodes 215 and the shield electrode 216 are arranged facing each other, and the plurality of bonding electrodes 124 are bonded to the plurality of bonding electrodes 215. This electrically connects the first substrate 100 and the second substrate 200 to each other.

[0108] [Operation of Image Capturing Device 1] Next, the operation of the image capturing device 1 will be described using FIGS. 15 and 16. FIGS. 15 and 16 are diagrams similar to FIG. 3, with arrows added to indicate the paths of each signal. FIG. 15 uses arrows to indicate the paths of input signals input to the image capturing device 1 from the outside, as well as the paths of the power supply potential and the reference potential. FIG. 16 uses arrows to indicate the signal paths of pixel signals output from the image capturing device 1 to the outside. For example, an input signal (e.g., a pixel clock and a synchronization signal) input to the image capturing device 1 via the input unit 510A is transmitted to the row driver 520 of the third substrate 300, which generates a row drive signal. This row drive signal is sent to the second substrate 200 via the contact units 301 and 201. Furthermore, this row drive signal reaches each pixel sharing unit 539 of the pixel array unit 540 via a row drive signal line 542 in the wiring layer 200T. Of the row drive signals that reach the pixel sharing unit 539 on the second substrate 200, the drive signals other than those for the transfer gate TG are input to the pixel circuit 210, thereby driving each transistor included in the pixel circuit 210. The drive signal for the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 on the first substrate 100 via the through-electrodes TGV, thereby driving the pixels 541A, 541B, 541C, and 541D. Furthermore, a power supply potential and a reference potential supplied from the outside of the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are sent to the second substrate 200 via the contact sections 301 and 201, and are supplied to the pixel circuits 210 of each pixel sharing unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to pixels 541A, 541B, 541C, and 541D on the first substrate 100 via the through-hole electrode 121E, bonding electrodes 124 and 215, and wiring 121D. Meanwhile, pixel signals photoelectrically converted in the pixels 541A, 541B, 541C, and 541D on the first substrate 100 are sent to the pixel circuit 210 on the second substrate 200 for each pixel sharing unit 539 via wiring 120D, bonding electrodes 124 and 215, and through-hole electrode 120E. Pixel signals based on these pixel signals are sent from the pixel circuit 210 to the third substrate 300 via vertical signal lines 543 and contact units 202 and 302. These pixel signals are processed by the column signal processing unit 550 and image signal processing unit 560 on the third substrate 300, and then output to the outside via the output unit 510B.

[0109] [Functions and Effects] In the imaging device 1 of the present embodiment, shield electrodes 125, 216 are formed between adjacent bonding electrodes 124, 215 provided on the surfaces of the wiring layers 100T, 200T-1 that form the bonding surfaces of the first substrate 100 and the second substrate 200, respectively. The shield electrodes 125, 216 have surfaces 125S, 216S that are recessed toward the semiconductor layers 100S, 200S from the surfaces of the bonding electrodes 124, 215 (specifically, the surfaces 124SA, 215SA of the electrode layers 124A, 215A that form the bonding electrodes 124, 215). This prevents contact between the shield electrodes 125, 216 and the multiple bonding electrodes 124, 215 that face each other at the bonding surface between the first substrate 100 and the second substrate 200. This is described below.

[0110] As mentioned above, imaging devices have been considered in which multiple sensor pixels and multiple readout circuits are formed on different substrates (first and second substrates), and the first and second substrates are electrically connected to each other by bonding electrodes provided on the opposing surfaces of the substrates. In such imaging devices, as pixel size becomes smaller, the spacing between the bonding electrodes also becomes smaller, requiring the formation of a shield electrode between adjacent bonding electrodes. However, when a shield electrode is formed between adjacent bonding electrodes, the minimum space on the bonding surface is the space between the bonding electrode and the shield electrode. This significantly reduces the allowable amount of misalignment compared to when a shield electrode is not provided, resulting in the challenge of requiring significantly higher alignment accuracy.

[0111] In contrast to this, in the present embodiment, a shield electrode 125 is provided between adjacent bonding electrodes 124 on a surface (specifically, a surface 123S of the interlayer insulating film 123) of the wiring layer 100T that forms the bonding surface with the second substrate 200, and the shield electrode 125 has a surface 125S that is recessed toward the semiconductor layer 100S relative to the surface (specifically, a surface 124SA of the electrode layer 124A) of the bonding electrode 124 that forms the bonding surface with the second substrate 200 together with the interlayer insulating film 123. Similarly, a shield electrode 216 is provided between adjacent bonding electrodes 215 on a surface (specifically, a surface 221S of the interlayer insulating film 221) of the wiring layer 200T-1 that forms the bonding surface with the first substrate 100, and the shield electrode 216 has a surface 216S that is recessed toward the semiconductor layer 200S relative to the surface (specifically, a surface 215SA of the electrode layer 215A) of the bonding electrode 215 that forms the bonding surface with the first substrate 100 together with the interlayer insulating film 221. This prevents contact between the bonding electrodes 124 and the shield electrode 216 and between the bonding electrodes 215 and the shield electrode 125 on the bonding surfaces of the opposing first substrate 100 and second substrate 200 .

[0112] As a result, in the imaging device 1 of this embodiment, it is possible to increase the areas of the multiple bonding electrodes 124, 215 formed on the respective bonding surfaces of the first substrate 100 and the second substrate 200. This makes it possible to relax the required alignment accuracy.

[0113] In this embodiment, the example in which both surfaces 125S and 216S of the shield electrodes 125 and 216 are recessed toward the semiconductor layers 100S and 200S has been shown, but only one of them may be recessed. Even in this case, contact between the multiple bonding electrodes 124 and the shield electrode 216 and between the multiple bonding electrodes 215 and the shield electrode 125 at the bonding surfaces of the opposing first and second substrates 100 and 200 can be reduced.

[0114] Modifications 1 to 5 of the present disclosure will be described below. In the following modifications, the same reference numerals will be used to designate components common to the above embodiment.

[0115] 17A to 17D show an example of a method for manufacturing the plurality of bonding electrodes 124, 215 and the shield electrodes 125, 216 according to Modification 1 of the present disclosure. The plurality of bonding electrodes 124, 215 and the shield electrodes 125, 216 described in the above embodiment can also be manufactured by the following method.

[0116] First, as shown in FIG. 17A, in the same manner as in the above embodiment, openings H3 and H4 are formed in the interlayer insulating film 123, a barrier metal film M1 and a conductive film M2 are formed in that order, and then the conductive film M2 formed outside the openings H3 and H4 is removed by CMP.

[0117] 17B, ​​the barrier metal film M1 is selectively etched by, for example, dry etching or wet etching, and then, as shown in FIG. 17C, surfaces 123S and 124SA of the interlayer insulating film 123 and the electrode layer 124A, which serve as bonding surfaces, are planarized by CMP.

[0118] Using a similar method, a bonding electrode 215 in which the surface 215SB of the barrier metal film 215B is recessed toward the semiconductor layer 200S side and a shield electrode 216 in which the surface 216S is recessed toward the semiconductor layer 200S side are formed on the surface 221S of the interlayer insulating film 221.

[0119] 17D , the interlayer insulating film 123 provided with the plurality of bonding electrodes 124 and the shield electrode 125 and the interlayer insulating film 221 provided with the plurality of bonding electrodes 215 and the shield electrode 216 are arranged to face each other, and the plurality of bonding electrodes 124 are bonded to the plurality of bonding electrodes 215. In this way, the first substrate 100 and the second substrate 200 are electrically connected to each other.

[0120] 17C shows an example in which the surface 124SA of the electrode layer 124A and the surface 123S of the interlayer insulating film 123 are planarized, but the present invention is not limited to this. For example, as shown in FIG. 18 , only the surfaces 124SA and 215SA of the electrode layers 124A and 215A may be planarized by CMP, and only the plurality of electrode layers 124A and the plurality of electrode layers 215A that protrude from the respective surfaces of the interlayer insulating films 123 and 221 may be joined to electrically connect the first substrate 100 and the second substrate 200.

[0121] In the multiple bonding electrodes 124, 215 and the shield electrodes 125, 216 formed using the manufacturing method of this modified example, the heights of the electrode layers 124A, 215A that constitute the multiple bonding electrodes 124, 215 can be easily controlled.

[0122] 19A to 19D show an example of a method for manufacturing the plurality of bonding electrodes 124, 215 and the shield electrodes 125, 216 according to Modification 2 of the present disclosure. In the above embodiment, the barrier metal films 124B, 215B constituting the plurality of bonding electrodes 124, 215, as well as the shield electrodes 125, 216, are set back toward the respective semiconductor layers 100S, 200S, but the present disclosure is not limited to this.

[0123] 19A, similarly to the above embodiment, openings H3 and H4 are formed in the interlayer insulating film 123, a barrier metal film M1 and a conductive film M2 are sequentially formed, and then the conductive film M2 formed on the interlayer insulating film 123 is removed by CMP. Next, as shown in FIG. 19B, CMP is again performed to remove the barrier metal film M1 formed outside the openings H3 and H4, and a plurality of bonding electrodes 124 and shield electrodes 125 each made of an electrode layer 124A and a barrier metal film 124B are formed in the openings H3 and H4, and the surface is planarized.

[0124] 19C, a resist film 132 is patterned continuously on the interlayer insulating film 123 and the plurality of bonding electrodes 124, excluding the area on the shield electrode 125. Next, as shown in Fig. 19D, the barrier metal film M1 constituting the shield electrode 125 exposed from the resist film 132 is selectively etched by, for example, dry etching or wet etching, and then the resist film 132 is removed as shown in Fig. 19E. This allows the surface 125S of the shield electrode 125 to be selectively recessed.

[0125] Using a similar method, multiple bonding electrodes 215 having flat surfaces where the electrode layer 215A and the barrier metal film 215B are continuous, and a shield electrode 216 whose surface 216S is recessed toward the semiconductor layer 200S are formed on the surface 221S of the interlayer insulating film 221.

[0126] 19D , the interlayer insulating film 123 provided with the plurality of bonding electrodes 124 and the shield electrode 125 and the interlayer insulating film 221 provided with the plurality of bonding electrodes 215 and the shield electrode 216 are arranged to face each other, and the plurality of bonding electrodes 124 are bonded to the plurality of bonding electrodes 215. This electrically connects the first substrate 100 and the second substrate 200 to each other.

[0127] In the multiple joining electrodes 124, 215 and the shield electrodes 125, 216 formed using the manufacturing method of this modification, only the surfaces 125S, 216S of the shield electrodes 125, 216 can be selectively recessed.

[0128] 20A to 20D show an example of a method for manufacturing a plurality of bonding electrodes 124, 215 and shield electrodes 125, 216 according to Modification 3 of the present disclosure. In the above embodiment, an example has been shown in which the opening H4 in which the shield electrode 125 (216) is formed is filled with the barrier metal film M1, but the present invention is not limited to this.

[0129] 20A, openings H3 and H4 are formed in the interlayer insulating film 123 in the same manner as in the above embodiment. Next, as shown in FIG. 20B, a continuous barrier metal film M1 is formed on the surface of the interlayer insulating film 123 and on the side and bottom surfaces of the openings H3 and H4 by, for example, sputtering. At this time, by controlling the film formation conditions, the barrier metal film M1 is formed in the opening H4 and a gap G is also formed.

[0130] 20C, a conductive film M2 is formed by, for example, sputtering so as to fill the opening H3. Next, as shown in FIG. 20D, the conductive film M2 formed outside the openings H3 and H4 is removed by, for example, CMP, and then CMP is performed again. As a result, a plurality of bonding electrodes 124 and shield electrodes 125 each made of an electrode layer 124A and a barrier metal film 124B are formed in the openings H3 and H4.

[0131] 20E , the barrier metal film 124B made of the barrier metal film M1 and the shield electrode 125 are selectively etched by, for example, dry etching or wet etching, so that the surfaces 124SB and 125S of the barrier metal film 124B and the shield electrode 125, respectively, are recessed toward the semiconductor layer 100S.

[0132] Using a similar method, a bonding electrode 215 in which the surface 215SB of the barrier metal film 215B is recessed toward the semiconductor layer 200S side and a shield electrode 216 in which the surface 216S is recessed toward the semiconductor layer 200S side are formed on the surface 221S of the interlayer insulating film 221.

[0133] 20F , the interlayer insulating film 123 provided with the plurality of bonding electrodes 124 and the shield electrode 125 and the interlayer insulating film 221 provided with the plurality of bonding electrodes 215 and the shield electrode 216 are arranged facing each other, and the plurality of bonding electrodes 124 are bonded to the plurality of bonding electrodes 215. This electrically connects the first substrate 100 and the second substrate 200 to each other.

[0134] In the multiple bonding electrodes 124, 215 and the shield electrodes 125, 216 formed using the manufacturing method of this modified example, a gap G can be formed in the shield electrodes 125, 216. This makes it possible to relieve stress generated in the in-plane direction of the wiring layers 100T, 200T-1, for example.

[0135] 21A to 21D show an example of a method for manufacturing a plurality of bonding electrodes 124, 215 and shield electrodes 125, 216 according to Variation 4 of the present disclosure. In the above embodiment, the example has been shown in which the first substrate 100 and the second substrate 200 are bonded together in a state in which the recesses on the barrier metal films 124B, 215B and on the shield electrodes 125, 216 formed by recessing the surfaces are hollow, but the respective recesses may be filled with, for example, insulating films 126, 217.

[0136] 21A, similarly to the above embodiment, openings H3 and H4 are formed in the interlayer insulating film 123, a barrier metal film M1 and a conductive film M2 are formed in that order, and then the conductive film M2 formed on the interlayer insulating film 123 is removed by CMP. Next, as shown in FIG. 21B, CMP is again performed to remove the barrier metal film M1 formed on the interlayer insulating film 123, and a plurality of bonding electrodes 124 and shield electrodes 125 each made of an electrode layer 124A and a barrier metal film 124B are formed in the openings H3 and H4, and the surface is planarized.

[0137] 21C , the barrier metal film 124B made of the barrier metal film M1 and the shield electrode 125 are selectively etched by, for example, dry etching or wet etching. As a result, the surfaces 124SB and 125S of the barrier metal film 124B and the shield electrode 125 are recessed toward the semiconductor layer 100S. Next, as shown in FIG. 21C , an insulating film 126 is formed on the interlayer insulating film 123 by, for example, sputtering so as to fill the recesses on the barrier metal film 124B and the shield electrode 125.

[0138] Subsequently, as shown in FIG. 21D, the insulating film 126 formed outside the openings H3 and H4 is polished by, for example, CMP to expose the interlayer insulating film 123 and the electrode layer 124A and to flatten the surface.

[0139] Using a similar method, a plurality of bonding electrodes 215 and shield electrodes 216 are formed on the surface 221S of the interlayer insulating film 221, with an insulating film 217 stacked on a barrier metal film 215B and a shield electrode 216 whose respective surfaces 215SB, 216S are recessed toward the semiconductor layer 200S side.

[0140] 21E , the interlayer insulating film 123 provided with the plurality of bonding electrodes 124 and the shield electrode 125 and the interlayer insulating film 221 provided with the plurality of bonding electrodes 215 and the shield electrode 216 are arranged to face each other, and the plurality of bonding electrodes 124 are bonded to the plurality of bonding electrodes 215. This electrically connects the first substrate 100 and the second substrate 200 to each other.

[0141] In the multiple bonding electrodes 124, 215 and shield electrodes 125, 216 formed using the manufacturing method of this modified example, insulating films 126, 217 are laminated on the barrier metal films 124B, 215B and the shield electrodes 125, 216 whose surfaces 124SB, 215SB, 125S, 216S have recessed, and the recesses created by the recession are filled, thereby improving the mechanical strength of the bonding surface between the first substrate 100 and the second substrate 200.

[0142] 22A to 22D show an example of a method for manufacturing a plurality of bonding electrodes 124, 215 and shield electrodes 125, 216 according to Modification 5 of the present disclosure. In the above embodiment, the barrier metal films 124B, 215B and the shield electrodes 125, 216 are formed from the same material (barrier metal film M1), but the present disclosure is not limited to this.

[0143] 22A, a resist film 133 is patterned on a surface 123S of the interlayer insulating film 123. Next, as shown in Fig. 22B, an opening H4 is formed by, for example, dry etching or wet etching, and then the resist film 133 is removed.

[0144] 22C , a barrier metal film M3 is formed on the interlayer insulating film 123 by, for example, sputtering, and the opening H4 is filled in. Next, as shown in FIG. 22D , the barrier metal film M3 formed on the interlayer insulating film 123 is removed by, for example, dry etching or wet etching, and a portion of the barrier metal film M3 filled in the opening H4 is etched. This forms a shield electrode 127 made of the barrier metal film M3 and having a surface 127S recessed toward the semiconductor layer 100S.

[0145] 22E , an insulating film 126 is formed on the interlayer insulating film 123 so as to fill the recess formed on the shield electrode 127 due to the recession of the surface 127S, and then a plurality of bonding electrodes 124 each made of an electrode layer 124A and a barrier metal film 124B are formed in the same manner as in the above-described embodiment, etc. Thereafter, the barrier metal film 124B made of the barrier metal film M1 is selectively etched by, for example, dry etching or wet etching.

[0146] Using a similar method, a shield electrode 219 is formed on the surface 221S of the interlayer insulating film 221, the shield electrode 219 consisting of a plurality of bonding electrodes 215 and a barrier metal film M3, with the surface 215SB of the barrier metal film 215B recessed toward the semiconductor layer 200S, and the surface of which is buried in an insulating film 217.

[0147] 22H , the interlayer insulating film 123 provided with the plurality of bonding electrodes 124 and the shield electrode 127 and the interlayer insulating film 221 provided with the plurality of bonding electrodes 215 and the shield electrode 219 are arranged facing each other, and the plurality of bonding electrodes 124 are bonded to the plurality of bonding electrodes 215. This electrically connects the first substrate 100 and the second substrate 200 to each other.

[0148] In the multiple bonding electrodes 124, 215 and the shield electrodes 127, 219 formed using the manufacturing method of this modification, the barrier metal films 124B, 215B constituting the multiple bonding electrodes 124, 215 and the shield electrodes 127, 219 are formed in different processes, so they can be formed using different materials, thereby improving the degree of freedom in material selection.

[0149] 3. Application Examples Application Example 1 The imaging device 1 and the like can be applied to any type of electronic device equipped with an imaging function, for example, a camera system such as a digital still camera or a video camera, a mobile phone with an imaging function, etc. Fig. 23 shows a schematic configuration of an electronic device 1000.

[0150] The electronic device 1000 includes, for example, a lens group 1001, an imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007, which are interconnected via a bus line 1008.

[0151] The lens group 1001 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal on a pixel-by-pixel basis and supplies the signal as a pixel signal to the DSP circuit 1002.

[0152] The DSP circuit 1002 is a signal processing circuit that processes signals supplied from the imaging device 1. The DSP circuit 1002 outputs image data obtained by processing the signals from the imaging device 1. The frame memory 1003 temporarily stores the image data processed by the DSP circuit 1002 on a frame-by-frame basis.

[0153] The display unit 1004 is composed of a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and records image data of moving images or still images captured by the imaging device 1 on a recording medium such as a semiconductor memory or a hard disk.

[0154] The operation unit 1006, in response to a user's operation, outputs operation signals for various functions of the electronic device 1000. The power supply unit 1007 supplies various types of power to the DSP circuit 1002, frame memory 1003, display unit 1004, recording unit 1005, and operation unit 1006 as needed.

[0155] 24A is a schematic diagram illustrating an example of the overall configuration of a light detection system 2000 including an imaging device 1. FIG. 24B is a diagram illustrating an example of the circuit configuration of the light detection system 2000. The light detection system 2000 includes a light emitting device 2001 serving as a light source unit that emits infrared light L2, and a light detecting device 2002 serving as a light receiving unit having a photoelectric conversion element. The imaging device 1 described above can be used as the light detecting device 2002. The light detection system 2000 may further include a system control unit 2003, a light source driving unit 2004, a sensor control unit 2005, a light source side optical system 2006, and a camera side optical system 2007.

[0156] The photodetector 2002 can detect light L1 and light L2. Light L1 is external ambient light reflected by the object (measurement target) 2100 ( FIG. 24A ). Light L2 is light emitted by the light-emitting device 2001 and then reflected by the object 2100. Light L1 is, for example, visible light, and light L2 is, for example, infrared light. Light L1 can be detected by a photoelectric conversion unit in the photodetector 2002, and light L2 can be detected by a photoelectric conversion region in the photodetector 2002. Image information of the object 2100 can be obtained from light L1, and distance information between the object 2100 and the photodetector system 2000 can be obtained from light L2. The photodetector system 2000 can be installed in, for example, an electronic device such as a smartphone or a mobile object such as a car. The light-emitting device 2001 can be configured, for example, by a semiconductor laser, a surface-emitting semiconductor laser, or a vertical-cavity surface-emitting laser (VCSEL). The method of detecting the light L2 emitted from the light-emitting device 2001 by the photodetector 2002 can be, for example, an iTOF method, but is not limited to this. In the iTOF method, the photoelectric conversion unit can measure the distance to the subject 2100, for example, by using the time-of-flight (TOF) of light. The method of detecting the light L2 emitted from the light-emitting device 2001 by the photodetector 2002 can also be, for example, a structured light method or a stereo vision method. For example, in the structured light method, a predetermined pattern of light is projected onto the subject 2100, and the distance between the photodetector system 2000 and the subject 2100 can be measured by analyzing the distortion of the pattern. In addition, in the stereo vision method, for example, two or more cameras are used to acquire two or more images of the subject 2100 viewed from two or more different viewpoints, thereby measuring the distance between the photodetector system 2000 and the subject. The light emitting device 2001 and the light detecting device 2002 can be controlled synchronously by a system control unit 2003 .

[0157] 4. Application Example Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0158] FIG. 25 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0159] 25 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0160] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0161] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0162] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0163] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0164] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0165] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical site, etc.

[0166] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0167] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0168] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0169] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0170] The light source device 11203 may also be configured to provide light in a predetermined wavelength range compatible with special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light onto the body tissue. Fluorescence observation can involve irradiating excitation light onto the body tissue and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to provide narrow-band light and / or excitation light compatible with such special light observation.

[0171] FIG. 26 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0172] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0173] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0174] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0175] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0176] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0177] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0178] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0179] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0180] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0181] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0182] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0183] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0184] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0185] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0186] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0187] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0188] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 11402 among the components described above. By applying the technology according to the present disclosure to the imaging unit 11402, detection accuracy is improved.

[0189] Although an endoscopic surgery system has been described as an example here, the technology according to the present disclosure may also be applied to other systems, such as a microsurgery system.

[0190] (Application Example to Mobile Object) The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile object, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor).

[0191] FIG. 27 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0192] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 27, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0193] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0194] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0195] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0196] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0197] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0198] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0199] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0200] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0201] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 27, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0202] FIG. 28 is a diagram showing an example of the installation position of the imaging unit 12031.

[0203] In FIG. 28, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0204] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0205] 28 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0206] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0207] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0208] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0209] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0210] The foregoing has described an example of a mobile object control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging devices according to the above-described embodiment and its variants 1 to 4 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain high-resolution captured images with little noise, thereby enabling high-precision control using the captured images in the mobile object control system.

[0211] The present disclosure has been described above by way of the embodiment and its modifications 1 to 5, application examples, and applied examples. However, the present disclosure is not limited to the above-described embodiment, etc., and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0212] Furthermore, for example, the present disclosure can be configured as follows: In an imaging device having the following configuration, contact between a plurality of bonding electrodes and a shield electrode facing each other on the bonding surface can be prevented, thereby increasing the area of ​​the plurality of bonding electrodes, thereby making it possible to relax alignment accuracy requirements. a second substrate formed by laminating a second semiconductor layer and a second wiring layer, the second wiring layer forming a bonding surface together with the first wiring layer; a plurality of first bonding electrodes formed on the bonding surface of the first wiring layer, each having a first bonding surface; a plurality of second bonding electrodes formed on the bonding surface of the second wiring layer, each having a second bonding surface bonded to the first bonding surfaces of the plurality of first bonding electrodes; one or more first metal layers formed between adjacent first bonding electrodes on the bonding surface of the first wiring layer, the first metal layers being recessed toward the first semiconductor layer from the first bonding surface and having a first opposing surface opposing the second substrate; and one or more second metal layers formed between adjacent second bonding electrodes on the bonding surface of the second wiring layer, the second metal layers having a second opposing surface opposing the first substrate. (2) The semiconductor device according to (1), wherein the first substrate and the second substrate are electrically connected to each other by bonding between the plurality of first bonding electrodes and the plurality of second bonding electrodes. (3) The semiconductor device according to (1) or (2), wherein the same potential is applied to the first metal layer and the second metal layer. (4) The semiconductor device according to any one of (1) to (3), wherein a fixed potential is applied to the first metal layer and the second metal layer. (5) The semiconductor device according to any one of (1) to (4), wherein the first metal layer is provided continuously so as to surround each of the plurality of first bonding electrodes. (6) The semiconductor device according to any one of (1) to (4), wherein the first metal layer is provided intermittently so as to surround each of the plurality of first bonding electrodes. (7) The semiconductor device according to any one of (1) to (6), wherein the second metal layer is provided continuously so as to surround each of the plurality of second bonding electrodes.(8) The semiconductor device according to any one of (1) to (6), wherein the second metal layer is provided intermittently to surround each of the plurality of second bonding electrodes. (9) The semiconductor device according to any one of (1) to (8), wherein the first bonding electrode includes a first electrode layer embedded in the bonding surface of the first wiring layer and a first barrier metal layer provided between the first electrode layer and the first wiring layer, and the second bonding electrode includes a second electrode layer embedded in the bonding surface of the second wiring layer and a second barrier metal layer provided between the second electrode layer and the second wiring layer. (10) The semiconductor device according to (9), wherein the first metal layer, the second metal layer, the first barrier metal layer, and the second barrier metal layer are formed using the same material. (11) The semiconductor device according to (9), wherein the first metal layer, the second metal layer, the first barrier metal layer, and the second barrier metal layer are each formed using a metal material or a metal nitride material. (12) The semiconductor device according to any one of (1) to (11), wherein the second opposing surfaces of the one or more second metal layers are recessed toward the second semiconductor layer from the second bonding surface. (13) The semiconductor device according to any one of (9) to (12), wherein the second opposing surfaces of the one or more second metal layers are recessed toward the second semiconductor layer from the second bonding surface, the opposing surface of the first barrier metal layer facing the second substrate is recessed toward the first semiconductor layer from the first bonding surface of the first bonding electrode, and the opposing surface of the second barrier metal layer facing the first substrate is recessed toward the second semiconductor layer from the second bonding surface of the second bonding electrode. (14) The semiconductor device according to (12) or (13), wherein an insulating film is stacked on each of the first opposing surface of the first metal layer and the second opposing surface of the second metal layer.(15) The semiconductor device according to (14), wherein the first bonding electrode has a first electrode layer embedded in the bonding surface of the first wiring layer and a first barrier metal layer provided between the first electrode layer and the first wiring layer, the second bonding electrode has a second electrode layer embedded in the bonding surface of the second wiring layer and a second barrier metal layer provided between the second electrode layer and the second wiring layer, an opposing surface of the first barrier metal layer facing the second substrate is recessed toward the first semiconductor layer from the first bonding surface of the first bonding electrode, an opposing surface of the second barrier metal layer facing the first substrate is recessed toward the second semiconductor layer from the second bonding surface of the second bonding electrode, and the insulating film is stacked on the opposing surfaces of the first barrier metal layer and the second barrier metal layer. (16) The semiconductor device according to any one of (1) to (15), wherein the first semiconductor layer is provided with a photoelectric conversion unit and a floating diffusion for accumulating signal charge generated in the photoelectric conversion unit for each pixel, and the second semiconductor layer is provided with a pixel transistor for reading out the signal charge of the floating diffusion. (17) The semiconductor device according to (16), wherein the first junction electrode is electrically connected to the floating diffusion.(18) An electronic device comprising a semiconductor device, the semiconductor device including: a first substrate formed by laminating a first semiconductor layer and a first wiring layer; a second substrate formed by laminating a second semiconductor layer and a second wiring layer, the second wiring layer forming a bonding surface together with the first wiring layer; a plurality of first bonding electrodes formed on the bonding surface of the first wiring layer, each having a first bonding surface; a plurality of second bonding electrodes formed on the bonding surface of the second wiring layer, each having a second bonding surface bonded to the first bonding surfaces of the plurality of first bonding electrodes; one or more first metal layers formed between the plurality of first bonding electrodes adjacent to each other on the bonding surface of the first wiring layer, the first metal layers being recessed toward the first semiconductor layer from the first bonding surface and having a first opposing surface opposing the second substrate; and one or more second metal layers formed between the plurality of second bonding electrodes adjacent to each other on the bonding surface of the second wiring layer, the second metal layers having a second opposing surface opposing the first substrate. (19) A semiconductor device comprising: a first substrate formed by laminating a first semiconductor layer and a first wiring layer; a second substrate formed by laminating a second semiconductor layer and a second wiring layer, the second wiring layer forming a bonding surface together with the first wiring layer; a plurality of first bonding electrodes formed on the bonding surface of the first wiring layer; a plurality of second bonding electrodes formed on the bonding surface of the second wiring layer; one or more first metal layers formed between the plurality of first bonding electrodes adjacent to each other on the bonding surface of the first wiring layer and made of a material having a higher electrical resistance than the plurality of first bonding electrodes; and one or more second metal layers formed between the plurality of second bonding electrodes adjacent to each other on the bonding surface of the second wiring layer and made of a material having a higher electrical resistance than the plurality of second bonding electrodes.

[0213] This application claims priority based on Japanese Patent Application No. 2023-142943, filed on September 4, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0214] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

a first substrate formed by laminating a first semiconductor layer and a first wiring layer; a second substrate formed by laminating a second semiconductor layer and a second wiring layer, the second wiring layer forming a bonding surface together with the first wiring layer; a plurality of first bonding electrodes formed on the bonding surface of the first wiring layer, each having a first bonding surface; a plurality of second bonding electrodes formed on the bonding surface of the second wiring layer, each having a second bonding surface bonded to the first bonding surfaces of the plurality of first bonding electrodes; one or a plurality of first metal layers formed between adjacent ones of the plurality of first bonding electrodes on the bonding surface of the first wiring layer, the first bonding surface being recessed toward the first semiconductor layer from the first bonding surface and having a first opposing surface opposing the second substrate; and one or a plurality of second metal layers formed between adjacent ones of the plurality of second bonding electrodes on the bonding surface of the second wiring layer, the second bonding surface being opposed to the first substrate.

2. The semiconductor device according to claim 1, wherein the first substrate and the second substrate are electrically connected to each other by bonding between the plurality of first bonding electrodes and the plurality of second bonding electrodes.

3. The semiconductor device according to claim 1, wherein the first metal layer and the second metal layer are applied with the same potential.

4. The semiconductor device according to claim 1, wherein a fixed potential is applied to said first metal layer and said second metal layer.

5. The semiconductor device according to claim 1, wherein said first metal layer is provided continuously so as to surround each of said plurality of first bonding electrodes.

6. The semiconductor device according to claim 1, wherein the first metal layer is provided discontinuously so as to surround each of the plurality of first bonding electrodes.

7. The semiconductor device according to claim 1, wherein the second metal layer is provided continuously so as to surround each of the plurality of second bonding electrodes.

8. The semiconductor device according to claim 1, wherein the second metal layer is provided discontinuously so as to surround each of the plurality of second bonding electrodes.

9. The semiconductor device described in claim 1, wherein the first bonding electrode has a first electrode layer embedded in the bonding surface of the first wiring layer and a first barrier metal layer provided between the first electrode layer and the first wiring layer, and the second bonding electrode has a second electrode layer embedded in the bonding surface of the second wiring layer and a second barrier metal layer provided between the second electrode layer and the second wiring layer.

10. The semiconductor device according to claim 9, wherein the first metal layer, the second metal layer, the first barrier metal layer and the second barrier metal layer are formed using the same material.

11. The semiconductor device according to claim 9, wherein the first metal layer, the second metal layer, the first barrier metal layer and the second barrier metal layer are each formed using a metal material or a metal nitride material.

12. The semiconductor device according to claim 1, wherein the second opposing surfaces of the one or more second metal layers are recessed toward the second semiconductor layer from the second junction surface.

13. The semiconductor device described in claim 9, wherein the second opposing surfaces of the one or more second metal layers are recessed toward the second semiconductor layer from the second bonding surface, the opposing surface of the first barrier metal layer facing the second substrate is recessed toward the first semiconductor layer from the first bonding surface of the first bonding electrode, and the opposing surface of the second barrier metal layer facing the first substrate is recessed toward the second semiconductor layer from the second bonding surface of the second bonding electrode.

14. The semiconductor device according to claim 12, wherein an insulating film is laminated on each of the first opposing surface of the first metal layer and the second opposing surface of the second metal layer.

15. The semiconductor device described in claim 14, wherein the first bonding electrode has a first electrode layer embedded in the bonding surface of the first wiring layer and a first barrier metal layer provided between the first electrode layer and the first wiring layer, the second bonding electrode has a second electrode layer embedded in the bonding surface of the second wiring layer and a second barrier metal layer provided between the second electrode layer and the second wiring layer, an opposing surface of the first barrier metal layer facing the second substrate is recessed toward the first semiconductor layer from the first bonding surface of the first bonding electrode, an opposing surface of the second barrier metal layer facing the first substrate is recessed toward the second semiconductor layer from the second bonding surface of the second bonding electrode, and the insulating film is laminated on the opposing surfaces of each of the first barrier metal layer and the second barrier metal layer.

16. The semiconductor device according to claim 1, wherein the first semiconductor layer is provided for each pixel with a photoelectric conversion section and a floating diffusion in which signal charge generated in the photoelectric conversion section is accumulated, and the second semiconductor layer is provided with a pixel transistor that reads out the signal charge of the floating diffusion.

17. The semiconductor device according to claim 16, wherein the first junction electrode is electrically connected to the floating diffusion.

18. An electronic device comprising a semiconductor device, the semiconductor device having: a first substrate formed by laminating a first semiconductor layer and a first wiring layer; a second substrate formed by laminating a second semiconductor layer and a second wiring layer, the second wiring layer forming a bonding surface together with the first wiring layer; a plurality of first bonding electrodes formed on the bonding surface of the first wiring layer, each having a first bonding surface; a plurality of second bonding electrodes formed on the bonding surface of the second wiring layer, each having a second bonding surface bonded to the first bonding surfaces of the plurality of first bonding electrodes; one or a plurality of first metal layers formed between the plurality of first bonding electrodes adjacent to each other on the bonding surface of the first wiring layer, the first metal layers being recessed toward the first semiconductor layer from the first bonding surface and having a first opposing surface opposing the second substrate; and one or a plurality of second metal layers formed between the plurality of second bonding electrodes adjacent to each other on the bonding surface of the second wiring layer, the second metal layers having a second opposing surface opposing the first substrate.