Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a method for manufacturing a semiconductor device, the method comprising: a step for forming a plurality of trenches on a front surface of a semiconductor substrate; a step for forming an injection mask in a first trench among the plurality of trenches; and a step for injecting a second conductivity-type dopant into a second trench, in which the injection mask is not formed, among the plurality of trenches, in order to form a trench bottom part in a bottom part of the second trench. In the step of injecting the dopant, the second conductivity-type dopant is also injected into a first mesa part adjacent to the first trench and a second mesa part adjacent to the second trench.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Patent Document 1 describes a semiconductor device in which a barrier region of a second conductivity type is provided at the bottom of a trench. [Prior art documents] [Patent documents] [Patent document 1] JP 2019-110288 A General disclosure

[0003] (Problem to be Solved) The step of forming a barrier region of the second conductivity type at the bottom of the trench may cause variations in threshold voltage.

[0004] (Means for solving the problem) A first aspect of the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: forming a plurality of trenches on a front surface of a semiconductor substrate; forming an implantation mask in a first trench of the plurality of trenches; and implanting a dopant of a second conductivity type into the second trench to form a trench bottom portion at the bottom of a second trench of the plurality of trenches in which the implantation mask is not formed, wherein in the step of implanting the dopant, the dopant of the second conductivity type is also implanted into a first mesa portion adjacent to the first trench and a second mesa portion adjacent to the second trench.

[0005] The method for manufacturing a semiconductor device may further include forming a trench bottom portion at a bottom of the third trench, the step of forming an implantation mask further including forming the implantation mask in the third trench, and the step of implanting the dopant further including implanting the second conductivity type dopant into the first mesa portion adjacent to the third trench.

[0006] The upper surface of the implantation mask may be provided at the same position as the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate, or at a position deeper than the front surface of the semiconductor substrate.

[0007] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of forming a plurality of trenches on a front surface of a semiconductor substrate, forming an implantation mask in a first trench of the plurality of trenches, and implanting a dopant of a second conductivity type into the second trench to form a trench bottom portion at the bottom of a second trench of the plurality of trenches in which the implantation mask is not formed, wherein in the step of forming the implantation mask, a mask is also formed on an upper surface of a first mesa portion adjacent to the first trench and an upper surface of a second mesa portion adjacent to the second trench.

[0008] The method for manufacturing a semiconductor device may further include forming a trench bottom portion at a bottom of the third trench, the trench bottom portion being formed in the third trench and on an upper surface of the first mesa portion adjacent to the third trench, the method further including forming a third trench between the first trench and the second trench, and the method for forming an implantation mask further including forming the implantation mask in the third trench and on an upper surface of the first mesa portion adjacent to the third trench.

[0009] In the forming of the implantation mask, the implantation mask may be formed such that an end of the implantation mask in a trench arrangement direction is aligned with a sidewall of the second trench.

[0010] In a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the steps of: forming a trench etch mask on a front surface of a semiconductor substrate; forming a plurality of trenches in the front surface of the semiconductor substrate using the trench etch mask; forming an implantation mask in a first trench of the plurality of trenches; and implanting a dopant of a second conductivity type into the second trench using the trench etch mask and the implantation mask to form a trench bottom portion at the bottom of a second trench where the implantation mask is not formed.

[0011] The step of forming the plurality of trenches may further include forming a third trench between the first trench and the second trench, and the step of forming the implantation mask may further include forming the implantation mask in the third trench. The method for manufacturing a semiconductor device may further include a step of diffusing the dopant, and may further include forming the trench bottom portion at a bottom of the third trench.

[0012] The trench etch mask may have a thickness of 0.3 μm or more and 1 μm or less.

[0013] In a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method comprising: forming a plurality of trenches on a front surface of a semiconductor substrate; forming an implantation mask in a first region where a first trench of the plurality of trenches is formed; a trench bottom implantation step of implanting a second conductivity type dopant into a second trench of the plurality of trenches and a second mesa portion adjacent to the second trench in a second region where the implantation mask is not formed, to form a trench bottom portion at a bottom of the second trench; removing the implantation mask from the first region, and then implanting the second conductivity type dopant to form a base region in a first mesa portion adjacent to the first trench in the first region; and a second base implantation step of implanting the second conductivity type dopant to form a base region in the second mesa portion.

[0014] The method for manufacturing a semiconductor device may further include forming a trench bottom portion at a bottom of the third trench, forming a third trench between the first trench and the second trench, forming an implantation mask in the implantation mask, and implanting the first base with the second conductivity type dopant into the first mesa portion adjacent to the third trench.

[0015] The dose of the second base implant step may be less than the dose of the first base implant step.

[0016] The dose of the dopant implanted into the second mesa may be equal to the dose of the dopant implanted into the first mesa.

[0017] A fifth aspect of the present invention provides a semiconductor device comprising a plurality of trench portions including a first trench portion and a second trench portion, and a trench bottom portion of a second conductivity type provided at the bottom of the second trench portion, wherein the first trench portion not provided with the trench bottom portion is a dummy trench portion or a dummy gate trench portion.

[0018] In a sixth aspect of the present invention, there is provided a semiconductor device comprising: a plurality of trench portions including a first trench portion and a second trench portion; a trench bottom portion of a second conductivity type provided at the bottom of the second trench portion; a first gate runner connected to the first trench portion not provided with the trench bottom portion; and a second gate runner different from the first gate runner connected to the second trench portion.

[0019] Furthermore, a third trench portion may be provided between the first trench portion and the second trench portion, and the trench bottom portion may be provided at the bottom of the third trench portion, and the third trench portion may be the dummy trench portion or the dummy gate trench portion.

[0020] Furthermore, a third trench portion may be provided between the first trench portion and the second trench portion, and the trench bottom portion may be provided at the bottom of the third trench portion, connecting the third trench portion and the first gate runner.

[0021] The semiconductor device may further include a third trench portion between the first trench portion and the second trench portion, and the trench bottom portion may be provided at a bottom of the third trench portion. The semiconductor device may further include a first gate runner connected to the third trench portion, and a second gate runner connected to the second trench portion, the second gate runner being different from the first gate runner.

[0022] The first gate runner and the second gate runner may be connected to different gate pads.

[0023] The first gate runner and the second gate runner may have different gate wiring resistances.

[0024] The second trench portion adjacent to the first trench portion may be the dummy trench portion or the dummy gate trench portion.

[0025] The first trench portion adjacent to the second trench portion may be a dummy trench portion or a dummy gate trench portion.

[0026] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0027] 2A is a diagram showing an example of a top surface of the semiconductor device 100 according to the first embodiment. FIG. 2B is a diagram showing an example of an a-a' cross section in FIG. 1 . FIG. 2C is an enlarged view of region A in FIG. 2A . FIG. 2D is a diagram showing an example of a method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 2E is a diagram showing another example of a method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 2F is a diagram showing another example of a method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 2G is a diagram showing another example of a method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 2H is a diagram showing another example of a method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 2I is a diagram showing another example of a method for manufacturing the semiconductor device 100 according to the first embodiment. FIG. 2J is a diagram showing another example of a method for manufacturing the semiconductor device 100 according to the first embodiment. 1 is a diagram illustrating another example of a method for manufacturing the semiconductor device 100 according to Example 1. FIG. 2 is a diagram illustrating another example of a cross section of the semiconductor device 200 according to Example 2. FIG. 3 is a diagram illustrating another example of a cross section of the semiconductor device 300 according to Example 3. FIG. 4 is a diagram illustrating another example of a cross section of the semiconductor device 400 according to Example 4.

[0028] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0029] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as the "top" or "front" and the other side as the "bottom" or "back." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the front surface and the other surface is referred to as the back surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0030] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0031] In this specification, orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the front and back surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the front and back surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0032] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0033] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0034] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N Ｄ , acceptor concentration is N Ａ Then, the net doping concentration at any position is N Ｄ -N Ａ This becomes:

[0035] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons.

[0036] In this specification, the terms P+ type and N+ type refer to a doping concentration higher than that of P type or N type, and the terms P- type and N- type refer to a doping concentration lower than that of P type or N type. In addition, in this specification, the terms P++ type and N++ type refer to a doping concentration higher than that of P+ type or N+ type.

[0037] In this specification, chemical concentration refers to the concentration of an impurity measured regardless of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as a value in a thermal equilibrium state. In addition, in an N-type region, the donor concentration is sufficiently greater than the acceptor concentration, so the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration.

[0038] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the donor, acceptor, or net doping concentration in the region. In cases where the donor, acceptor, or net doping concentration is approximately uniform, the average value of the donor, acceptor, or net doping concentration in the region may be taken as the donor, acceptor, or net doping concentration.

[0039] The carrier concentration measured by the SR method may be lower than the concentration of donors or acceptors. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects or the like.

[0040] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element representing the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0041] 1 is a diagram illustrating an example of the top surface of a semiconductor device 100 according to a first embodiment. In FIG. 1, the positions of the components are shown as projected onto the front surface of a semiconductor substrate. In FIG. 1, only some of the components of the semiconductor device 100 are shown, and some components are omitted.

[0042] The semiconductor device 100 includes a semiconductor substrate. In this specification, the term "top view" simply refers to a view from the front surface side of the semiconductor substrate. The semiconductor substrate in this example has two pairs of edges that face each other when viewed from the top. In FIG. 1, the X-axis and Y-axis are parallel to one of the edges. The Z-axis is perpendicular to the front surface of the semiconductor substrate.

[0043] The semiconductor substrate is provided with an active portion 160. The active portion 160 is a region through which a main current flows in the depth direction between the front and back surfaces of the semiconductor substrate when the semiconductor device 100 operates.

[0044] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT. The active section 160 may further be provided with a diode section including a diode element such as a free wheel diode (FWD). The transistor section 70 has gate structures periodically arranged on the front surface side of the semiconductor substrate, each having an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film.

[0045] The semiconductor device 100 may have one or more pads above the semiconductor substrate. The semiconductor device 100 may have pads such as a gate pad, an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge. The vicinity of an edge refers to the region between the edge and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0046] A gate potential is applied to the gate pad, which is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate runner 47 that electrically connects the gate pad and the gate trench portion.

[0047] The gate runner 47 is disposed between the active portion 160 and the edge of the semiconductor substrate in a top view. The gate runner 47 in this example surrounds the active portion 160 in a top view. The area surrounded by the gate runner 47 in a top view may be the active portion 160.

[0048] The gate runner 47 is made up of either or both of a semiconductor gate runner 48 and a gate metal layer 50. In this example, the gate runner 47 includes the semiconductor gate runner 48 and the gate metal layer 50. The semiconductor gate runner 48 is disposed above a semiconductor substrate. In this example, the semiconductor gate runner 48 may be formed of a polycrystalline semiconductor such as polysilicon doped with impurities. The semiconductor gate runner 48 is electrically connected to a gate conductive portion provided inside the gate trench portion via a gate insulating film.

[0049] The semiconductor device 100 of this example includes a breakdown voltage structure portion 190 provided on the outer periphery of the active portion 160. The breakdown voltage structure portion 190 of this example is disposed between the gate runner 47 and the edge. The breakdown voltage structure portion 190 relieves electric field concentration on the front surface side of the semiconductor substrate.

[0050] The breakdown voltage structure 190 may further include at least one of a field plate 94 and a resurf, which are provided in an annular shape surrounding the active portion 160. The field plate 94 in this example may be made of the same material as the gate metal layer 50 or the emitter electrode 52 and / or polysilicon doped with impurities. In this example, description of the structures in the breakdown voltage structure 190 other than the field plate 94 will be omitted.

[0051] The semiconductor device 100 may also include a temperature sensing section (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detection section (not shown) which operates in the same manner as the transistor section provided in the active section 160.

[0052] The semiconductor device 100 includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, which are provided on the front surface side of a semiconductor substrate. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0053] The semiconductor device 100 of this example also includes a gate metal layer 50 and an emitter electrode 52 provided above the front surface of the semiconductor substrate. The gate metal layer 50 and the emitter electrode 52 are provided separately from each other. The gate metal layer 50 and the emitter electrode 52 are electrically insulated from each other.

[0054] An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50 and the front surface of the semiconductor substrate, but is not shown in Fig. 1. In this example, contact holes 49, 54, and 56 are provided through the interlayer insulating film. In Fig. 1, each contact hole is hatched with diagonal lines.

[0055] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate via contact holes 54.

[0056] The emitter electrode 52 is connected to a dummy conductive portion in the dummy trench portion 30 via a contact hole 56. A connection portion made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion may be provided on the front surface of the semiconductor substrate via an insulating film such as a dummy insulating film in the dummy trench portion 30.

[0057] The gate metal layer 50 is electrically connected to the semiconductor gate runner 48 via a contact hole 49. The semiconductor gate runner 48 may be formed of impurity-doped polysilicon or the like. The semiconductor gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate. The semiconductor gate runner 48 is not electrically connected to the dummy conductive portion in the dummy trench portion 30 or the emitter electrode 52. If the semiconductor gate runner 48 and the gate conductive portion are not connected, or if the semiconductor gate runner 48 is not provided, the gate metal layer 50 may be directly connected to the gate conductive portion via the contact hole 49.

[0058] The semiconductor gate runner 48 and the emitter electrode 52 are electrically isolated by an insulating material such as an interlayer insulating film and an oxide film. The semiconductor gate runner 48 in this example is provided from below the contact hole 49 to the tip 41 of the gate trench portion 40. At the tip 41 of the gate trench portion 40, the gate conductive portion is exposed on the front surface of the semiconductor substrate and is connected to the semiconductor gate runner 48.

[0059] The emitter electrode 52 and the gate metal layer 50 are made of a conductive material containing metal. For example, they are made of aluminum or an alloy containing aluminum as a main component (e.g., an aluminum-silicon alloy). Each electrode may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. In this example, the electrodes are the emitter electrode 52 and the gate metal layer 50.

[0060] Each electrode may have a plug formed of tungsten or the like in the contact hole. The plug may have a barrier metal on the side in contact with the semiconductor substrate, with tungsten buried so as to be in contact with the barrier metal, and may be formed of aluminum or the like on the tungsten.

[0061] The well region 11 overlaps with the gate runner 47, extends around the periphery of the active portion 160, and is provided in a ring shape in top view. The well region 11 also extends with a predetermined width in an area where it does not overlap with the gate runner 47, and is provided in a ring shape in top view. In this example, the well region 11 is provided away from the end of the contact hole 54 in the Y-axis direction toward the gate runner 47. The well region 11 is a region of the second conductivity type that has a higher doping concentration than the base region 14. The gate runner 47 is electrically insulated from the well region 11.

[0062] In this example, the base region 14 is P-type, and the well region 11 is P+-type. The well region 11 is formed from the front surface of the semiconductor substrate to a position deeper than the bottom end of the base region 14. The base region 14 is provided in contact with the well region 11. Therefore, the well region 11 is electrically connected to the emitter electrode 52.

[0063] The transistor section 70 has a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 are provided along the arrangement direction.

[0064] The gate trench portion 40 in this example may have two straight portions 39 (portions of the trench that are straight along the extension direction) extending along an extension direction perpendicular to the arrangement direction, and a tip portion 41 connecting the two straight portions 39.

[0065] At least a portion of the tip 41 may be curved in top view. The tip 41 connects the ends of the two straight portions 39 in the Y-axis direction to the semiconductor gate runner 48, thereby functioning as a gate electrode to the gate trench portion 40. On the other hand, by making the tip 41 curved, electric field concentration at the end can be alleviated more effectively than if the tip 41 were completed at the straight portion 39.

[0066] In another example, the transistor section 70 may have one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the arrangement direction. In the transistor section 70, the dummy trench sections 30 are provided between the respective straight line sections 39 of the gate trench sections 40. One dummy trench section 30 may be provided between each straight line section 39, or multiple dummy trench sections 30 may be provided between each straight line section 39. In FIG. 1 , two dummy trench sections 30 are provided between the straight line sections 39, but this is merely an example and is not limiting.

[0067] Furthermore, the dummy trench portion 30 does not have to be provided between the respective straight portions 39, and the gate trench portion 40 may be provided instead. With such a structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-voltage.

[0068] The dummy trench portion 30 may have a linear shape extending in the extension direction, and may have a linear portion 29 and a tip portion 31, similar to the gate trench portion 40. The semiconductor device 100 shown in FIG. 1 has only dummy trench portions 30 having tip portions 31 arranged therein, but in other examples, the semiconductor device 100 may include linear dummy trench portions 30 that do not have tip portions 31.

[0069] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. That is, at the ends of each trench portion in the Y-axis direction, the bottoms of each trench portion in the depth direction are covered by the well region 11. Furthermore, trench portions provided at the ends in the X-axis direction may be covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottoms of each trench portion.

[0070] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate that is sandwiched between the trench portions. As an example, the depth position of the mesa portion is from the front surface of the semiconductor substrate to the bottom of the trench portion. In this example, the mesa portion is sandwiched between adjacent trench portions in the X-axis direction and is provided on the front surface of the semiconductor substrate, extending in the extension direction (Y-axis direction) along the trench.

[0071] Each mesa portion has a base region 14. In each mesa portion, at least one of an emitter region 12 of a first conductivity type and a contact region 15 of a second conductivity type may be provided in a region sandwiched between the base regions 14 in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate in the depth direction.

[0072] The mesa portion has an emitter region 12 exposed on the front surface of the semiconductor substrate. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion in contact with the gate trench portion 40 has a contact region 15 exposed on the front surface of the semiconductor substrate.

[0073] The contact regions 15 and the emitter regions 12 in the mesa portion are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion are alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0074] In another example, the contact region 15 and the emitter region 12 of the mesa portion may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0075] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in a region sandwiched between the base regions 14 in the extension direction (Y-axis direction). In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 may be arranged in the center in the arrangement direction (X-axis direction) of the mesa portions.

[0076] 2A is a diagram showing an example of the aa' cross section in FIG. 1. Fig. 2B is an enlarged view of region A in Fig. 2A. The aa' cross section is an XZ plane passing through the emitter region 12, the contact region 15, the base region 14, the gate trench portion 40, and the dummy trench portion 30. In the aa' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0077] The breakdown voltage structure 190 may include a guard ring 92. The guard ring 92 is a P-type region that contacts the front surface 21 of the semiconductor substrate 10. The guard ring 92 is electrically connected to a field plate 94. Note that although the breakdown voltage structure 190 of this example includes multiple guard rings, only one guard ring 92 is shown in FIG. 2A for brevity's sake. By providing multiple guard rings 92, the depletion layer on the upper surface side of the active section 160 can be extended outward, thereby improving the breakdown voltage of the semiconductor device 100. Note that in this example, contact holes are drawn in the interlayer insulating film 38 to show the electrical connection between the guard ring 92 and the field plate 94, but this does not necessarily mean that the contact holes exist on the a-a' cross section.

[0078] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is an insulating film such as silicate glass doped with impurities such as boron or phosphorus. The interlayer insulating film 38 may be in contact with the front surface 21, or another film such as an oxide film may be provided between the interlayer insulating film 38 and the front surface 21. The interlayer insulating film 38 has a contact hole 54, as described with reference to FIG. 1 .

[0079] The emitter electrode 52 is provided on the front surface 21 of the semiconductor substrate 10 and on the upper surface of the interlayer insulating film 38. The emitter electrode 52 is electrically connected to the front surface 21 via a contact hole 54 in the interlayer insulating film 38. A plug and / or barrier metal made of tungsten (W) or the like may be provided inside the contact hole 54. A P++-type plug region (not shown) having a higher doping concentration than the contact region 15 may be provided below the contact hole in which the plug and / or barrier metal is provided. The plug region improves the contact resistance between the barrier metal and P-type regions including the well region 11, the base region 14, and the contact region 15. Improving the contact resistance between the barrier metal and the contact region 15 improves latch-up resistance.

[0080] The collector electrode 24 is provided on the rear surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a material containing a metal or a laminated film of such a material.

[0081] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0082] The semiconductor substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a remaining region of the semiconductor substrate 10 without other doped regions being provided therein.

[0083] One or more accumulation regions 16 may be provided above the drift region 18 in the Z-axis direction. The accumulation region 16 is a region in which the same dopant as the drift region 18 is accumulated at a higher concentration than the drift region 18. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. In this example, the accumulation region 16 is N-type. Examples of dopants for the accumulation region 16 include arsenic (As), phosphorus (P), and antimony (Sb). By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, thereby reducing the on-voltage.

[0084] The accumulation region 16 in this example may be provided between the base region 14 and a trench bottom portion 75, which will be described later. The upper end of the accumulation region 16 in this example contacts the base region 14, and the lower end contacts the trench bottom portion 75. In another example, the drift region 18 may be interposed between the lower end of the accumulation region 16 and the upper end of the trench bottom portion 75.

[0085] An emitter region 12 is provided above the base region 14 in contact with the front surface 21 of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).

[0086] A buffer region 20 of a first conductivity type may be provided below the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. A collector region 22 is provided below the buffer region 20. In this example, the collector region 22 is P+ type, for example. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22.

[0087] The semiconductor substrate 10 is provided with a gate trench portion 40 and a dummy trench portion 30. The gate trench portion 40 and the dummy trench portion 30 are provided so as to pass from the front surface 21 through the base region 14 and the accumulation region 16 to reach the drift region 18. The trench portion passing through the doped region is not limited to a case where the trench portion is formed after the doped region is formed. A case where the doped region is formed between the trench portions after the trench portions are formed is also included in the case where the trench portion passes through the doped region.

[0088] The gate trench portion 40 has a gate trench provided in the front surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed of an oxide film or a nitride film. The gate conductive portion 44 is provided so as to fill the inside of the gate trench more inward than the gate insulating film 42. The upper surface of the gate conductive portion 44 may be in the same XY plane as the front surface 21. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of impurity-doped polysilicon or the like.

[0089] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the base region 14 at the interface that contacts the gate trench.

[0090] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the XZ cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the front surface 21 of the semiconductor substrate 10. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy insulating film 32 may be formed of an oxide film or a nitride film. The dummy conductive portion 34 is provided so as to fill the inside of the dummy trench more inward than the dummy insulating film 32. The top surface of the dummy conductive portion 34 may be located in the same XY plane as the front surface 21. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0091] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in the XZ cross section).

[0092] A P-type trench bottom portion 75 is provided at the bottom of the trench portion. In this example, the trench bottom portion 75 is provided below the accumulation region 16. In the depth direction of the semiconductor substrate 10, the lower end of the trench bottom portion 75 may be located below the bottom of the gate trench portion 40. In other words, the trench bottom portion 75 may cover the bottom of the gate trench portion 40.

[0093] The trench bottom portion 75 may be an electrically floating layer. In this specification, a floating layer refers to a layer that is not electrically connected to any electrode, such as the emitter electrode 52. Providing the trench bottom portion 75 improves the turn-on characteristics of the transistor portion 70. Furthermore, providing the trench bottom portion 75 alleviates electric field concentration at the bottom of the gate trench portion 40, improving avalanche resistance.

[0094] The transistor section 70 may have an electron passing region 76 in which no trench bottom section 75 is provided when viewed from above. The electron passing region 76 may have an accumulation region 16. In another example, the accumulation region 16 may not be provided. The trench bottom section 75 may be an electrically floating layer provided closer to the center of the active section 160 than the electron passing region 76. In another example, the transistor section 70 may also have a region in contact with the well region 11 provided closer to the breakdown voltage structure section 190 than the electron passing region 76.

[0095] The electron passing region 76 separates the trench bottom portion 75 on the central side of the active portion 160 from the well region 11 fixed at the emitter potential and electrically floats it, so that when the transistor portion 70 is conductive, electrons can flow through the trench bottom portion 75 on the central side of the active portion 160. Furthermore, when the transistor portion 70 is conductive, electrons can flow through the electron passing region 76.

[0096] 3A and 3B are diagrams illustrating an example of a manufacturing method of the semiconductor device 100 according to the first embodiment. Here, the process related to the formation of the trench bottom portion 75 will be mainly described, and a description of other processes will be omitted.

[0097] In step S100, a trench etch mask 60 is formed on the front surface 21 of the semiconductor substrate 10, and multiple trenches are formed by etching using the trench etch mask 60. The trenches are formed by etching to a depth that reaches the region that will become the drift region 18 (a region that will remain without other doped regions being formed in a later doped region formation step).

[0098] In step S130, an oxide film having a thickness of 50 nm to 200 nm is formed. The trench etch mask 60 may be removed before the oxide film is formed. Furthermore, an implantation mask 62 is formed in those trenches among the plurality of trenches that do not have a trench bottom portion 75 formed at their bottom. In this example, the implantation mask 62 is a resist mask. For convenience, in this example, among the plurality of trenches, those trenches that do not have a trench bottom portion 75 formed at their bottom may be referred to as first trenches, and those trenches that have a trench bottom portion 75 formed at their bottom may be referred to as second trenches.

[0099] The upper surface of the implantation mask 62 is provided in the Z-axis direction at the same position as the front surface 21 of the semiconductor substrate 10 or at a position deeper than the front surface 21 of the semiconductor substrate 10. In other words, the implantation mask 62 of this example is not provided on the mesa portion, but is provided only in the first trench.

[0100] In step S140, a P-type dopant is ion-implanted to form the trench bottom portion 75. In this example, the dopant is ion-implanted vertically from above the multiple trenches toward the bottom of the trench portion. The dose amount may be adjusted appropriately to achieve a predetermined doping concentration. An example of the P-type dopant is boron (B).

[0101] The P-type dopant is implanted into the second trench where the implantation mask 62 is not formed. Furthermore, the P-type dopant is also implanted into the mesa portion where the implantation mask 62 is not formed. In this example, for convenience, the mesa portion adjacent to the first trench may be referred to as the first mesa portion, and the mesa portion adjacent to the second trench may be referred to as the second mesa portion. In the mesa portion sandwiched between the first trench and the second trench, the side of the first trench may be considered the first mesa portion, and the side of the second trench may be considered the second mesa portion. The P-type dopant is also implanted into the first mesa portion and the second mesa portion. In FIG. 3B , the implantation depth of the P-type dopant in the first mesa portion and the second mesa portion is indicated by a dashed line.

[0102] In step S150, the oxide film is removed from the sidewalls and mesa portions of the plurality of trenches. Then, in step S160, an oxide film is formed on the sidewalls of the plurality of trenches. This removes damage caused by ion implantation along with the old oxide film, and the new oxide film prevents leakage from the trenches. This oxide film becomes the dummy insulating film 32 and the gate insulating film 42. Furthermore, the plurality of trenches whose sidewalls are covered with the dummy insulating film 32 and the gate insulating film 42 are filled with impurity-doped polysilicon or the like to form the dummy conductive portion 34 and the gate conductive portion 44, respectively. Excess polysilicon or the like deposited on the front surface 21 of the semiconductor substrate 10 is removed by etching, thereby forming the dummy trench portion 30 and the gate trench portion 40.

[0103] In step S170, dopants for forming the base regions 14 and the like are ion-implanted into the front surface 21 of the semiconductor substrate 10, and then doped regions are formed by thermal diffusion. As a result, the P-type dopants implanted into the bottoms of the second trenches in step S140 diffuse in the trench arrangement direction (X-axis direction), forming trench bottom portions 75 that extend across multiple second trenches in the trench arrangement direction (X-axis direction). In addition to the trench bottom portions 75, doped regions such as the base regions 14, emitter regions 12, contact regions 15, and accumulation regions 16 are also formed.

[0104] In this example, a P-type dopant is implanted into the mesa portion in step S140. However, as shown in FIG. 3B , the P-type dopant is implanted uniformly into the first mesa portion and the second mesa portion. Therefore, even after the doping region formation process in step S170, the dose of the P-type dopant implanted into the first mesa portion and the second mesa portion is uniform, and the doping concentration of the base region 14 is uniform. Therefore, the threshold voltages of the mesa portions in contact with the gate trench portion 40 can be made uniform, regardless of whether a trench bottom portion 75 is provided at the bottom.

[0105] 4A and 4B are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment. This example differs from the example illustrated in FIGS. 3A and 3B in the process of forming the implantation mask 62. Here, the differences from the example illustrated in FIGS. 3A and 3B will be mainly described, and a description of the common processes will be omitted.

[0106] 3A. In step S230, an implantation mask 62 is formed in the trenches that do not have a trench bottom portion 75 formed at the bottom (i.e., the first trenches), on the top surface of the mesa portion adjacent to the first trench (i.e., the first mesa portion), and on the top surface of the mesa portion adjacent to the trench that has a trench bottom portion 75 formed at the bottom (i.e., the second trenches) (i.e., the second mesa portion).

[0107] The implantation mask 62 is formed so that its end in the trench arrangement direction (X-axis direction) is aligned with the sidewall of the second trench. In this specification, the upper end of the trench sidewall is defined as the point where it intersects with the front surface 21 of the semiconductor substrate 10, and "the implantation mask 62 is aligned with the trench sidewall" means that the end of the implantation mask 62 is located at the upper end of the trench sidewall in the trench arrangement direction (X-axis direction). In other words, the implantation mask 62 in this example is provided so as to cover not only the inside of the first trench but also both the first mesa portion and the second mesa portion.

[0108] In step S240, a P-type dopant is ion-implanted to form trench bottom portions 75. In this example, the dopant is ion-implanted vertically from above the multiple trenches toward the bottoms of the trench portions. The dose amount may be adjusted appropriately to achieve a predetermined doping concentration. An example of the P-type dopant is boron (B).

[0109] The P-type dopant is implanted into the second trench where the implantation mask 62 is not formed. However, the P-type dopant is not implanted into the mesa portion where the implantation mask 62 is formed. That is, in this example, the P-type dopant is implanted only into the second trench.

[0110] In steps S250 to S270, after removing the oxide film from the sidewalls of the trenches, the dummy trench portions 30, the gate trench portions 40, and the doping regions are formed. However, since these steps are common to steps S150 to S170, the description thereof will be omitted.

[0111] In this example, in step S240, the P-type dopant is implanted only into the second trench, but not into either the first or second mesa portion. Therefore, no P-type dopant is implanted into either mesa portion prior to the doping region formation process of step S270. In the doping region formation process of step S270, the P-type dopant is uniformly implanted into the first and second mesa portions. Therefore, the doping concentration of the base region 14 is uniform in both mesas, and therefore the threshold voltages of the mesa portions in contact with the gate trench portion 40 can be made uniform regardless of whether the trench bottom portion 75 is provided at the bottom.

[0112] 5A and 5B are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment. This example differs from the example illustrated in FIGS. 3A and 3B in the process of forming the trench etch mask 60. Here, the differences from the example illustrated in FIGS. 3A and 3B will be mainly described, and a description of the common processes will be omitted.

[0113] In step S300, a trench etch mask 60 is formed on front surface 21 of semiconductor substrate 10, and multiple trenches are formed by etching using trench etch mask 60. Thickness T of trench etch mask 60 is 0.3 μm or more and 1 μm or less. Thickness T of trench etch mask 60 in this example is greater than the thickness of trench etch mask 60 used in the example shown in FIGS. 3A and 3B .

[0114] In step S340, P-type dopants are ion-implanted to form trench bottom portions 75 using trench etch mask 60 and implantation mask 62. The P-type dopants are implanted into the second trenches where implantation mask 62 is not formed. However, the P-type dopants are not implanted into the mesa portions where trench etch mask 60 remains. That is, in this example, the P-type dopants are implanted only into the second trenches.

[0115] In step S350, the trench etch mask 60 provided on the top surface of the mesa and the oxide film provided on the sidewalls of the trenches are removed. In steps S350 to S370, the dummy trenches 30, the gate trenches 40, and the doping regions are formed. These steps are common to steps S160 to S170, so their description will be omitted.

[0116] In this example, the trench etch mask 60 formed thick in step S300 is also used in the step of forming the trench bottom portion 75 in step S340, so the P-type dopant is implanted only into the second trench, not into the mesa portion. Therefore, no P-type dopant is implanted into any of the mesa portions prior to the doping region formation step in step S370, and the P-type dopant is uniformly implanted into the mesa portions in the doping region formation step in step S370. Therefore, the doping concentration of the base region 14 is uniform in all mesa portions, and therefore the threshold voltages of the mesa portions adjacent to the gate trench portion 40 can be made uniform regardless of whether the trench bottom portion 75 is provided at the bottom.

[0117] In this example, by setting the thickness T of trench etch mask 60 to 0.3 μm or more and 1 μm or less, trench etch mask 60 can have a sufficient thickness to be usable as an implantation mask even after etching.

[0118] 6A to 6C are diagrams illustrating another example of the method for manufacturing the semiconductor device 100 according to the first embodiment. This example differs from the example illustrated in FIGS. 3A and 3B in the process of forming the doping region. Here, the differences from the example illustrated in FIGS. 3A and 3B will be mainly described, and a description of the common processes will be omitted.

[0119] 3A , step S400 is the same as step S100. In step S430, an implantation mask 62 is formed in a first region R1 in which a trench (i.e., a first trench) that does not have a trench bottom portion 75 formed at its bottom is formed. The implantation mask 62 in this example may be provided only in the first trench, or may be provided in the first trench and on a mesa portion (i.e., a first mesa portion) adjacent to the first trench in the first region R1.

[0120] In step S440, a P-type dopant is ion-implanted into the second region R2 where the implantation mask 62 is not formed to form the trench bottom portion 75. The P-type dopant is implanted into the second trench and the mesa portion adjacent to the second trench (i.e., the second mesa portion) where the implantation mask 62 is not formed in the second region R2. In FIG. 6B, the implantation depth of the P-type dopant into the first mesa portion and the second mesa portion is indicated by a dashed line. In steps S450 to S460, the oxide film is removed from the sidewalls of the multiple trenches, and then the dummy trench portion 30, the gate trench portion 40, and the doping region are formed. However, since these steps are common to steps S160 to S170, their description will be omitted.

[0121] In step S462, a P-type dopant is implanted into the first mesa portion adjacent to the first trench in the first region R1 to form the base region 14. In step S464, a P-type dopant is implanted into the second mesa portion to form the base region 14.

[0122] In step S464, the dose of P-type dopant implanted into the second mesa portion of the second region R2 is smaller than the dose of P-type dopant implanted into the first mesa portion of the first region R1 in step S462. The dose of P-type dopant implanted into the second mesa portion, i.e., the total dose of P-type dopant implanted into the second mesa portion in steps S440 and S464, is equal to the dose of P-type dopant implanted into the first mesa portion. Note that either the P-type dopant implantation process in step S462 or step S464 may be performed first.

[0123] In step S470, dopants for forming the emitter regions 12 and the like are ion-implanted into the front surface 21 of the semiconductor substrate 10, and then doped regions are formed by thermal diffusion. As a result, the P-type dopants implanted into the bottoms of the second trenches in step S440 diffuse in the trench arrangement direction (X-axis direction), forming trench bottom portions 75 that extend across multiple second trenches in the trench arrangement direction (X-axis direction). In addition to the trench bottom portions 75, doped regions such as the base regions 14, emitter regions 12, contact regions 15, and accumulation regions 16 are also formed.

[0124] In this example, a P-type dopant is implanted into the second mesa portion of the second region R2 in step S440. However, by implanting a larger amount of P-type dopant in step S462 than in step S464, the dose of P-type dopant implanted into the first mesa portion and the second mesa portion becomes uniform, and the doping concentration of the base region 14 becomes uniform. Therefore, the threshold voltages of the mesa portions in contact with the gate trench portion 40 can be made uniform regardless of whether the trench bottom portion 75 is provided at the bottom.

[0125] 7A is a diagram showing an example of a cross section of a semiconductor device 200 according to Example 2. Here, common reference numerals are used to designate components common to the semiconductor device 100, and differences from the semiconductor device 100 will be mainly described.

[0126] The semiconductor device 200 of this example includes a plurality of trench portions including a gate trench portion 40 and a dummy trench portion 30. For convenience, in this example, among the plurality of trench portions, a trench portion that does not have a trench bottom portion 75 at its bottom may be referred to as a first trench portion, and a trench portion that has a trench bottom portion 75 at its bottom may be referred to as a second trench portion.

[0127] 7A schematically illustrates the connection between the trench portions and electrodes of the semiconductor device 200 of this example. In this example, a region in which a plurality of first trench portions without trench bottom portions 75 are continuously arranged and a region in which a plurality of second trench portions with trench bottom portions 75 are continuously arranged are alternately arranged in the trench arrangement direction (X-axis direction). The region in which a plurality of first trench portions are continuously arranged constitutes an electron passage region 76. The trench bottom portions 75 are provided extending in the trench arrangement direction (X-axis direction) across the plurality of continuously arranged second trench portions.

[0128] In this example, the first trench portions arranged continuously are dummy trench portions 30 set to the emitter potential.

[0129] As described in relation to Example 1, if the process of forming the trench bottom portion 75 does not follow the method described in Example 1, the mesa portion (i.e., the second mesa portion) adjacent to the trench in which the trench bottom portion 75 is to be formed (i.e., the second trench) is implanted with P-type dopant, while the mesa portion (i.e., the first mesa portion) adjacent to the trench in which the trench bottom portion 75 is not to be formed (i.e., the first trench) is covered with the implantation mask 62. In other words, the dose of P-type dopant implanted into the first mesa portion is smaller than the dose of P-type dopant implanted into the second mesa portion, and there is a possibility that the threshold voltage of the first mesa portion is lower than that of the second mesa portion.

[0130] In the semiconductor device 200 of this example, the first trench portion is a dummy trench portion 30 that is not connected to the gate pad G. In other words, by making only the trench portion that is not in contact with the first mesa portion the gate trench portion 40, the threshold voltages of the mesa portions in contact with the gate trench portion 40 can be made uniform.

[0131] In this example, the second trench is a gate trench 40 set to the gate potential or a dummy trench 30 set to the emitter potential. The second trench may also include a dummy gate trench 45 shown in FIG. 7C . The dummy gate trench 45 is a trench set to the gate potential and not in contact with the emitter region 12. The gate trench 40 is electrically connected to the gate pad G via a gate runner 47 or the like. By designating only the trench not in contact with the first mesa as the gate trench 40, the threshold voltages of the mesa in contact with the gate trench 40 can be made uniform. Furthermore, in the mesa between the first and second trenches, the P-type dopant implanted in the second trench (second mesa) may diffuse to the first trench (first mesa) where the P-type dopant is not implanted, potentially reducing the doping concentration of the base region 14 of the second mesa. Therefore, the threshold voltage of the second mesa portion between the first trench portion and the second trench portion may be lower than that of the second mesa portion between the second trench portions. Therefore, the second trench portion adjacent to the first trench portion may be a dummy trench portion 30 or a dummy gate trench portion 45. When the second trench portion adjacent to the first trench portion is a dummy gate trench portion 45, an emitter region 12 may be provided in the second mesa portion on the side of the adjacent second trench portion to operate as a gate trench portion 40, and an emitter region 12 may not be provided in the second mesa portion on the side of the adjacent first trench portion. Furthermore, if the concentration difference in the base region 14 between the second mesa portions on both sides of the second trench portion adjacent to the first trench portion is small and the difference in threshold voltage is small enough to not be a problem, the second trench portion may be a gate trench portion 40 having emitter regions 12 in the second mesa portions on both sides.

[0132] 7B is a diagram showing an example of a cross section of a semiconductor device 300 according to Example 3. Here, common reference numerals are used to designate members common to the semiconductor device 100, and differences will be mainly described.

[0133] 7B schematically shows the connection between the trench portions and electrodes of the semiconductor device 300 of this example. Of the multiple trench portions in this example, the multiple first trench portions arranged continuously in the trench arrangement direction (X-axis direction) have their gate trench portions 40 connected to gate pad G1 via gate runners 47-1, and the multiple second trench portions arranged continuously in the trench arrangement direction (X-axis direction) have their gate trench portions 40 connected to gate pad G2 via gate runners 47-2. The dummy trench portions 30 are connected to the emitter electrode 52 and are set to the emitter potential.

[0134] As described above, in the process of forming the trench bottom portion 75, the dose of P-type dopant implanted into the mesa portion (i.e., the first mesa portion) adjacent to the trench in which the trench bottom portion 75 is not formed (i.e., the first trench) is different from the dose of P-type dopant implanted into the mesa portion (i.e., the second mesa portion) adjacent to the trench in which the trench bottom portion 75 is formed (i.e., the second trench).

[0135] In the semiconductor device 300 of this example, the gate trenches 40 of the multiple first trenches and the multiple second trenches are connected to different gate pads via different gate runners. This allows the gate pads G1 and G2 to send signals at different timings depending on the difference in threshold voltage, thereby aligning the on / off timing of the first trenches and the multiple second trenches.

[0136] Alternatively, the first gate runner 47-1 and the second gate runner 47-2 may have different gate wiring resistances. For example, the first gate runner 47-1 and the second gate runner 47-2 may have resistors with different resistance values ​​inserted along their paths, be made of materials with different resistances, or have different cross-sectional areas. In this case, even if the gate pads G1 and G2 are the same gate pad, the signal transmission speed to the first trench portion and the second trench portion differs depending on the gate wiring resistance of the gate runner 47-1 and the second gate runner 47-2, thereby allowing the on / off timing of the first trench portion and the multiple second trench portions to be synchronized. In this example, as in the semiconductor device 200 shown in FIG. 7A , the second trench portion adjacent to the first trench portion may be a dummy trench portion 30 or a dummy gate trench portion 45, or may be a gate trench portion 40 if the concentration difference between adjacent base regions 14 is small. Other second trench portions may include a dummy gate trench portion 45. Furthermore, in the mesa portion of the first trench adjacent to the second trench, the P-type dopant implanted into the second trench side (second mesa portion) may diffuse to the first trench side (first mesa portion) where the P-type dopant is not implanted, increasing the concentration of the base region 14 of the first mesa. Therefore, the threshold voltage may be higher in the first mesa portion between the first trench and the second trench than in the first mesa portion between the first trenches. Therefore, the first trench adjacent to the second trench may be a dummy trench portion 30 or a dummy gate trench portion 45. When the first trench adjacent to the second trench is a dummy gate trench portion 45, an emitter region 12 may be provided in the first mesa portion on the adjacent first trench side to operate as a gate trench portion 40, and the emitter region 12 may not be provided in the first mesa portion on the adjacent second trench side. Furthermore, in the first mesa portions on both sides of the first trench portion adjacent to the second trench portion, if the concentration difference in the base region 14 is small and the difference in threshold voltage is small and not a problem, the first trench portion may be a gate trench portion 40 having emitter regions 12 in the first mesa portions on both sides.The other first trench portions may include dummy gate trench portions 45 .

[0137] 7C is a diagram showing an example of a cross section of a semiconductor device 400 according to Example 4. Here, common reference numerals are used to designate members common to the semiconductor device 100, and differences will be mainly described.

[0138] 7C schematically shows the connection between the trench portions and electrodes of the semiconductor device 400 of this example. Of the multiple trench portions of this example, the dummy gate trench portions 45 of the multiple first trench portions arranged continuously in the trench arrangement direction (X-axis direction) and the gate trench portions 40 of the multiple second trench portions arranged continuously in the trench arrangement direction (X-axis direction) are connected to the gate pad G via gate runners 47. Here, the dummy gate trench portions 45 refer to trench portions that are set to gate potential and are not in contact with the emitter region 12. The dummy trench portions 30 are connected to the emitter electrode 52 and are set to emitter potential.

[0139] As described above, in the process of forming the trench bottom portion 75, the dose of P-type dopant implanted into the mesa portion (i.e., the first mesa portion) adjacent to the trench in which the trench bottom portion 75 is not formed (i.e., the first trench) is different from the dose of P-type dopant implanted into the mesa portion (i.e., the second mesa portion) adjacent to the trench in which the trench bottom portion 75 is formed (i.e., the second trench).

[0140] In the semiconductor device 400 of this example, the dummy gate trenches 45 of the multiple first trenches and the gate trenches 40 of the multiple second trenches are connected to a gate pad via gate runners. Because the first trenches are dummy gate trenches 45 that are not in contact with the emitter region 12, even if the base region 14 forms an inversion channel, electrons are not conducted from the front surface 21. Because the second trenches are gate trenches 40 that include the emitter region 12, the base region 14 forms an inversion channel and electrons are conducted from the front surface 21. As described above, by using only the trenches that are not in contact with the first mesa as gate trenches 40, the threshold voltages of the mesa portions in contact with the gate trenches 40 can be made uniform.

[0141] 7C , contact regions 15 are provided in contact with the dummy gate trench portions 45 instead of the emitter regions 12, but this is not limiting. A base region 14 may be provided instead of the contact regions 15. Furthermore, the emitter region 12 does not have to be formed adjacent to the dummy trench portions 30 of the first trench portions. In this example, similar to the semiconductor device 200 shown in FIG. 7A , the second trench portions adjacent to the first trench portions may be dummy trench portions 30 or dummy gate trench portions 45, or may be gate trench portions 40 when the concentration difference between the adjacent base regions 14 is small. Other second trench portions may include dummy gate trench portions 45.

[0142] In the above, an example has been described in which the P-type impurities implanted into each second trench diffuse over a width less than one mesa, forming trench bottom portions 75 that are connected to each other, but the present invention also applies to cases in which the P-type impurities have different diffusion widths.Even in cases in which the P-type impurities diffuse narrowly and do not connect to each other, and trench bottom portions 75 are formed discretely, the above invention can be similarly applied to make the threshold values ​​of each mesa portion uniform.

[0143] On the other hand, when diffusion is wider than the width of one mesa, trench bottom portion 75 is formed in the trench portion located at the end of trench bottom portion 75 even though P-type ions are not implanted into the bottom portion. In this case, too, by treating this trench portion (sometimes referred to as a third trench portion) as similar to the first trench portion, the threshold values ​​of the mesa portions can be made uniform.

[0144] 8A is a diagram showing an example of a manufacturing method of the semiconductor device 100 according to the first embodiment when a third trench is provided. Here, changes related to the third trench from the process shown in FIGS. 3A and 3B will be mainly described, and descriptions of other processes will be omitted.

[0145] In step S130, an oxide film having a thickness of 50 nm to 200 nm is formed in the third trench 73, similar to the first and second trenches. The trench etch mask 60 may be removed before the oxide film is formed. Furthermore, an implantation mask 62 is formed in the third trench 73, among the multiple trenches, similar to the first trench. In this example, the implantation mask 62 is a resist mask.

[0146] The upper surface of the implantation mask 62 is provided in the Z-axis direction at the same position as the front surface 21 of the semiconductor substrate 10 or at a position deeper than the front surface 21 of the semiconductor substrate 10. In other words, the implantation mask 62 of this example is not provided on the mesa portion, but is provided only in the first trench and the third trench 73.

[0147] In step S140, P-type dopants are ion-implanted to form trench bottom portions 75. The P-type dopants are implanted into the second trenches where the implantation mask 62 is not formed. Furthermore, the P-type dopants are also implanted into the mesa portions where the implantation mask 62 is not formed. For convenience, in this example, the mesa portions adjacent to the first trench and the third trench 73 may be referred to as the first mesa portion, and the mesa portion adjacent to the second trench may be referred to as the second mesa portion. In the mesa portion sandwiched between the third trench 73 and the second trench, the side of the third trench 73 may be considered the first mesa portion, and the side of the second trench may be considered the second mesa portion. The P-type dopants are also implanted into the first and second mesa portions. In FIG. 8A , the implantation depths of the P-type dopants in the first and second mesa portions are indicated by dashed lines.

[0148] 8A , in steps S150 and S160, dummy trench portions 30 and gate trench portions 40 may be formed in multiple trenches including the third trench 73 as shown in FIG. 3B . In step S170, dopants for forming the base region 14 and the like are ion-implanted into the front surface 21 of the semiconductor substrate 10, and then doped regions are formed by thermal diffusion. As a result, the P-type dopant implanted into the bottoms of the second trenches in step S140 diffuses in the trench arrangement direction (X-axis direction), forming trench bottom portions 75 that extend across the multiple second trenches in the trench arrangement direction (X-axis direction). At this time, trench bottom portions 75 are also formed at the bottoms of the third trenches 73. In Figure 8A, two third trenches are provided and formed as a gate trench portion 40 and a dummy trench portion 30, but three or more may be provided, and if only one is provided, it may be formed as a gate trench portion 40 or as a dummy trench portion 30.

[0149] 8B is a diagram showing another example of the method for manufacturing the semiconductor device 100 according to the first embodiment when a third trench is provided. Here, changes related to the third trench from the process shown in FIGS. 4A and 4B will be mainly described, and descriptions of other processes will be omitted.

[0150] In step S230, an implantation mask 62 is formed in those trenches (i.e., the first trench and the third trench 73) among the plurality of trenches into which a P-type dopant is not ion-implanted to form a trench bottom portion 75 at the bottom, and on the upper surface of a mesa portion (i.e., the first mesa portion) adjacent to the first trench and the upper surface of a mesa portion (i.e., the second mesa portion) adjacent to a trench (i.e., the second trench) into which a P-type dopant is ion-implanted to form a trench bottom portion 75 at the bottom (i.e., the second mesa portion and the first mesa portion).

[0151] In step S240, a P-type dopant is ion-implanted to form the trench bottom portion 75. The P-type dopant is implanted into the second trench where the implantation mask 62 is not formed. However, the P-type dopant is not implanted into the mesa portion where the implantation mask 62 is formed. That is, in this example, the P-type dopant is implanted only into the second trench.

[0152] 8B , in steps S250 and S260, dummy trench portions 30 and gate trench portions 40 may be formed in multiple trenches including the third trench 73 as shown in FIG. 4B . In step S270, dopants for forming the base region 14 and the like are ion-implanted into the front surface 21 of the semiconductor substrate 10, and then doped regions are formed by thermal diffusion. As a result, the P-type dopant implanted into the bottoms of the second trenches in step S240 diffuses in the trench arrangement direction (X-axis direction), forming trench bottom portions 75 that extend across the multiple second trenches in the trench arrangement direction (X-axis direction). At this time, trench bottom portions 75 are also formed at the bottoms of the third trenches 73. In Figure 8B, two third trenches are provided and formed as a gate trench portion 40 and a dummy trench portion 30, but three or more may be provided, and if only one is provided, it may be formed as a gate trench portion 40 or as a dummy trench portion 30.

[0153] 8C is a diagram showing another example of the method for manufacturing the semiconductor device 100 according to the first embodiment when a third trench is provided. Here, changes related to the third trench from the process shown in FIGS. 5A and 5B will be mainly described, and descriptions of other processes will be omitted.

[0154] In step S330, an implantation mask 62 is formed inside the third trench 73 and the first trench.

[0155] In step S340, a P-type dopant is ion-implanted to form trench bottom portion 75 using trench etch mask 60 and implantation mask 62. The P-type dopant is implanted into the second trench where implantation mask 62 is not formed. However, the P-type dopant is not implanted into the mesa portion where trench etch mask 60 remains. That is, in this example, the P-type dopant is implanted only into the second trench, and is not implanted into first mesa portion, second mesa portion, first trench, or third trench 73.

[0156] 8C , in steps S350 and S360, dummy trench portions 30 and gate trench portions 40 may be formed in multiple trenches including the third trench 73 as shown in FIG. 5B . In step S370, dopants for forming the base region 14 and the like are ion-implanted into the front surface 21 of the semiconductor substrate 10, and then doped regions are formed by thermal diffusion. As a result, the P-type dopant implanted into the bottoms of the second trenches in step S340 diffuses in the trench arrangement direction (X-axis direction), forming trench bottom portions 75 that extend across the multiple second trenches in the trench arrangement direction (X-axis direction). At this time, trench bottom portions 75 are also formed at the bottoms of the third trenches 73. In Figure 8C, two third trenches are provided and formed as a gate trench portion 40 and a dummy trench portion 30, but three or more may be provided, and if only one is provided, it may be formed as a gate trench portion 40 or as a dummy trench portion 30.

[0157] 8D is a diagram showing another example of the method for manufacturing the semiconductor device 100 according to Example 1 when a third trench is provided. Here, changes related to the third trench from the process shown in FIGS. 6A to 6C will be mainly described, and descriptions of other processes will be omitted.

[0158] In step S430, an implantation mask 62 is formed in the first region R1 on the inside of the third trench 73 and the first trench and on the first mesa portion.

[0159] 8D , in step S440, a P-type dopant is ion-implanted into the second region R2 to form the trench bottom portion 75. Although not shown in FIG. 8D , in steps S450 and S460, dummy trench portions 30 and gate trench portions 40 may be formed in a plurality of trenches including the third trench 73 as shown in FIG. 6B . In step S462, a P-type dopant is implanted into the first mesa portion adjacent to the first trench and the third trench in the first region R1 to form the base region 14.

[0160] Although not shown in FIG. 8D , in step S464, a P-type dopant is implanted into the second mesa portion adjacent to the second trench in the second region R2 to form the base region 14. In step S470, a doped region is formed by thermal diffusion. As a result, the P-type dopant implanted into the bottom of the second trench in step S440 diffuses in the trench arrangement direction (X-axis direction), forming trench bottom portions 75 that extend across multiple second trenches in the trench arrangement direction (X-axis direction). At this time, trench bottom portions 75 are also formed at the bottom of the third trench 73. Note that, although two third trenches are provided in FIG. 8D and formed as gate trench portions 40 and dummy trench portions 30, three or more third trenches may be provided. If only one third trench is provided, it may be formed as either a gate trench portion 40 or a dummy trench portion 30.

[0161] 9A is a diagram showing an example of a cross section of a semiconductor device 200 according to Example 2 when a third trench portion is included. Here, changes related to the third trench portion from the semiconductor device shown in FIG. 7A will be described, and descriptions of other structures will be omitted.

[0162] In FIG. 7A , the trench portion located at the end of the trench bottom portion 75 is the second trench. In FIG. 9A , the trench portion located at the end of the trench bottom portion 75 is the third trench 73, and ion implantation to form the trench bottom portion 75 is not performed on the adjacent first mesa portion. However, in this example, the third trench 73 is also formed as a dummy trench portion 30, so that no channel is formed in the first mesa portion adjacent to the third trench 73, and no deviation in the threshold voltage of each conductive mesa portion occurs. In FIG. 9A , two third trenches 73 are provided, but three or more third trenches 73 may be provided, or only one may be provided.

[0163] 9B is a diagram showing an example of a cross section of a semiconductor device 300 according to Example 3 when a third trench portion is included. Here, changes related to the third trench portion from the semiconductor device shown in FIG. 7B will be described, and descriptions of other structures will be omitted.

[0164] In FIG. 7B , the trench portion located at the end of the trench bottom portion 75 is the second trench. In FIG. 9B , the trench portion located at the end of the trench bottom portion 75 is the third trench 73, and ion implantation to form the trench bottom portion 75 is not performed on the adjacent first mesa portion. In this example, the third trench 73 is formed as the gate trench portion 40, but is connected to the gate runner 47-1, just like the first trench of the electron passage region 76. The first mesa portion adjacent to the third trench 73 also does not experience a shift in the on / off timing of the gates of the other mesa portions. The third trench 73 may also be formed as a dummy trench portion 30. In this case, no channel is formed in the first mesa portion adjacent to the third trench 73, and thus no shift in the threshold voltage of each conductive mesa portion occurs. In another example, the gate trench portion 40 formed from the third trench 73 may be connected to the first gate runner 47-1, and the other first trench portions may not be connected to the first gate runner 47-1 or the second gate runner 47-2. Although two third trenches 73 are provided in FIG. 9B, three or more third trenches 73 may be provided. When only one third trench is provided, it may be formed as a gate trench portion 40 or a dummy trench portion 30.

[0165] 9C is a diagram showing an example of a cross section of a semiconductor device 400 according to Example 4 when a third trench portion is included. Here, changes related to the third trench portion from the semiconductor device shown in FIG. 7C will be described, and descriptions of other structures will be omitted.

[0166] In FIG. 7C , the trench portion located at the end of the trench bottom portion 75 is the second trench. In FIG. 9C , the trench portion located at the end of the trench bottom portion 75 is the third trench 73, and ion implantation to form the trench bottom portion 75 is not performed on the adjacent first mesa portion. However, in this example, the third trench 73 is also formed as a dummy gate trench portion 45, so the channel formed in the first mesa portion adjacent to the third trench 73 is not connected to the emitter region 12 and electrons are not conducted. Therefore, there is no deviation in the threshold voltage of each conducting mesa portion. Alternatively, the third trench 73 may be formed as a dummy trench portion 30. In this case, there is also no channel formed in the first mesa portion adjacent to the third trench 73, and there is no deviation in the threshold voltage of each conducting mesa portion. 9C shows that two third trenches 73 are provided, three or more third trenches 73 may be provided, and when only one third trench is provided, it may be formed as a dummy gate trench portion 45 or as a dummy trench portion 30. Note that in the semiconductor devices 200 and 300 according to the second and third examples, the third trench 73 may be formed as a dummy gate trench portion 45.

[0167] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0168] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0169] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 18...Drift region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 29...Straight portion, 30...Dummy trench portion, 31...Tip portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 39...Straight portion, 40...Gate trench portion, 41...Tip portion, 42...Gate insulating film, 44...Gate conductive portion, 45...Dummy gate trench trench portion, 47...gate runner, 48...semiconductor gate runner, 49...contact hole, 50...gate metal layer, 52...emitter electrode, 54...contact hole, 56...contact hole, 60...trench etch mask, 62...implantation mask, 70...transistor portion, 73...third trench, 75...trench bottom portion, 76...electron passage region, 92...guard ring, 94...field plate, 100...semiconductor device, 160...active portion, 190...breakdown structure portion, 200...semiconductor device, 300...semiconductor device, 400...semiconductor device

Claims

1. forming a plurality of trenches in a front surface of a semiconductor substrate; forming an implant mask in a first of the plurality of trenches; implanting dopants of a second conductivity type into second trenches among the plurality of trenches, the second trenches being free of the implantation mask, to form trench bottom portions at the bottoms of the second trenches; Equipped with In the step of implanting the dopant, the second conductive type dopant is also implanted into a first mesa portion adjacent to the first trench and a second mesa portion adjacent to the second trench. A method for manufacturing a semiconductor device.

2. The step of forming the plurality of trenches further includes forming a third trench between the first trench and the second trench; The step of forming the implantation mask further includes forming the implantation mask in the third trench; In the step of implanting the dopant, the second conductivity type dopant is also implanted into the first mesa portion adjacent to the third trench; diffusing the dopant, and further forming a trench bottom portion at the bottom of the third trench. The method for manufacturing a semiconductor device according to claim 1 .

3. The upper surface of the implantation mask is provided at the same position as the front surface of the semiconductor substrate or at a position deeper than the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.

3. The method for manufacturing a semiconductor device according to claim 1.

4. The implantation mask is a resist mask.

3. The method for manufacturing a semiconductor device according to claim 1.

5. A step of forming a gate trench portion in the second trench.

3. The method for manufacturing a semiconductor device according to claim 1.

6. forming a plurality of trenches in a front surface of a semiconductor substrate; forming an implant mask in a first of the plurality of trenches; implanting dopants of a second conductivity type into second trenches among the plurality of trenches, the second trenches being free of the implantation mask, to form trench bottom portions at the bottoms of the second trenches; Equipped with In the step of forming the implantation mask, a mask is also formed on an upper surface of a first mesa portion adjacent to the first trench and an upper surface of a second mesa portion adjacent to the second trench. A method for manufacturing a semiconductor device.

7. The step of forming the plurality of trenches further includes forming a third trench between the first trench and the second trench; In the step of forming the implantation mask, the implantation mask is further formed in the third trench and on an upper surface of the first mesa portion adjacent to the third trench; diffusing the dopant, and further forming a trench bottom portion at the bottom of the third trench. The method for manufacturing a semiconductor device according to claim 6 .

8. In the step of forming the implantation mask, the implantation mask is formed so that an end portion of the implantation mask in a trench arrangement direction is aligned with a sidewall of the second trench. The method for manufacturing a semiconductor device according to claim 6 or 7.

9. The implantation mask is a resist mask. The method for manufacturing a semiconductor device according to claim 6 or 7.

10. A step of forming a gate trench portion in the second trench. The method for manufacturing a semiconductor device according to claim 6 or 7.

11. forming a trench etch mask on a front surface of a semiconductor substrate; forming a plurality of trenches in the front surface of the semiconductor substrate using the trench etch mask; forming an implant mask in a first of the plurality of trenches; implanting a dopant of a second conductivity type into the second trench using the trench etch mask and the implantation mask to form a trench bottom portion at a bottom of the second trench where the implantation mask is not formed; A method for manufacturing a semiconductor device comprising:

12. The step of forming the plurality of trenches further includes forming a third trench between the first trench and the second trench; The step of forming the implantation mask further includes forming the implantation mask in the third trench; diffusing the dopant, and further forming a trench bottom portion at the bottom of the third trench. The method for manufacturing a semiconductor device according to claim 11 .

13. The thickness of the trench etch mask is 0.3 μm or more and 1 μm or less. The method for manufacturing a semiconductor device according to claim 11 or 12.

14. The implantation mask is a resist mask. The method for manufacturing a semiconductor device according to claim 11 or 12.

15. A step of forming a gate trench portion in the second trench. The method for manufacturing a semiconductor device according to claim 11 or 12.

16. forming a plurality of trenches in a front surface of a semiconductor substrate; forming an implantation mask in a first region where a first of the plurality of trenches is formed; a trench bottom implantation step of implanting a second conductivity type dopant into a second trench of the plurality of trenches and a second mesa portion adjacent to the second trench in a second region where the implantation mask is not formed, to form a trench bottom portion at a bottom of the second trench; a first base implantation step of implanting a dopant of a second conductivity type into a first mesa portion adjacent to the first trench in the first region after removing the implantation mask from the first region; a second base implantation step of implanting a second conductivity type dopant into the second mesa portion to form a base region; Equipped with A method for manufacturing a semiconductor device.

17. The step of forming the plurality of trenches further includes forming a third trench between the first trench and the second trench; The step of forming the implantation mask further includes forming the implantation mask in the third trench in the first region; In the first base implantation step, the second conductivity type dopant is further implanted into the first mesa portion adjacent to the third trench; diffusing the dopant, and further forming a trench bottom portion at the bottom of the third trench. The method for manufacturing a semiconductor device according to claim 16.

18. The dose of the second base implant step is less than the dose of the first base implant step. The method for manufacturing a semiconductor device according to claim 16 or 17.

19. The dose of the dopant implanted in the second mesa portion is equal to the dose of the dopant implanted in the first mesa portion. The method for manufacturing a semiconductor device according to claim 16 or 17.

20. The implantation mask is a resist mask. The method for manufacturing a semiconductor device according to claim 16 or 17.

21. A step of forming a gate trench portion in the second trench. The method for manufacturing a semiconductor device according to claim 16 or 17.

22. a plurality of trench portions including a first trench portion and a second trench portion; a trench bottom portion of a second conductivity type provided at a bottom of the second trench portion; Equipped with The first trench portion in which the trench bottom portion is not provided is a dummy trench portion or a dummy gate trench portion. Semiconductor device.

23. a plurality of trench portions including a first trench portion and a second trench portion; a trench bottom portion of a second conductivity type provided at a bottom of the second trench portion; a first gate runner connected to the first trench portion where the trench bottom portion is not provided; a second gate runner connected to the second trench portion and different from the first gate runner; A semiconductor device comprising:

24. further comprising a third trench portion between the first trench portion and the second trench portion; the trench bottom portion is provided at the bottom of the third trench portion; The third trench portion is the dummy trench portion or the dummy gate trench portion.

23. The semiconductor device according to claim 22.

25. further comprising a third trench portion between the first trench portion and the second trench portion; the trench bottom portion is provided at the bottom of the third trench portion; The third trench portion is a dummy trench portion or a dummy gate trench portion.

24. The semiconductor device according to claim 23.

26. further comprising a third trench portion between the first trench portion and the second trench portion; the trench bottom portion is provided at the bottom of the third trench portion; the third trench portion and the first gate runner are connected; 24. The semiconductor device according to claim 23.

27. further comprising a third trench portion between the first trench portion and the second trench portion; the trench bottom portion is provided at the bottom of the third trench portion; a first gate runner connected to the third trench portion; a second gate runner connected to the second trench portion and different from the first gate runner; 23. The semiconductor device according to claim 22.

28. The first gate runner and the second gate runner are connected to different gate pads.

27. The semiconductor device according to claim 23, 25 or 26.

29. The first gate runner and the second gate runner have different gate wiring resistances.

28. The semiconductor device according to claim 23, 26 or 27.

30. The second trench portion adjacent to the first trench portion is the dummy trench portion or the dummy gate trench portion.

23. The semiconductor device according to claim 22.

31. The second trench portion adjacent to the first trench portion is a dummy trench portion or a dummy gate trench portion.

24. The semiconductor device according to claim 23.

32. The first trench portion adjacent to the second trench portion is a dummy trench portion or a dummy gate trench portion.

24. The semiconductor device according to claim 23.