Semiconductor substrate manufacturing method

Abstract

This semiconductor substrate comprises: a template substrate and a first semiconductor part located above the template substrate and including a nitride semiconductor. The first semiconductor part includes a first wing part. A gap is located between the first wing part and the template substrate. The first wing part has a plurality of projections that protrude downward. At least some of the plurality of projections have a tapered shape and have a sloping surface that is inclined with respect to the thickness direction of the template substrate.

Description

Semiconductor substrate, semiconductor substrate manufacturing method, semiconductor device manufacturing method, semiconductor device, light-emitting element

[0001] The present disclosure relates to semiconductor substrates and the like.

[0002] A mask pattern that prevents the growth of a nitride semiconductor layer is formed on a template substrate including a heterogeneous substrate and a seed layer, and the nitride semiconductor layer is grown laterally on the mask portion, starting from the seed layer exposed in the opening where there is no mask portion, thereby reducing the defect density of the nitride semiconductor layer on the mask portion (Patent Document 1).

[0003] Japanese Patent Publication No. 2013-251304

[0004] The semiconductor substrate comprises a template substrate and a first semiconductor portion located above the template substrate and including a nitride semiconductor, the first semiconductor portion including a first wing portion, a gap being located between the first wing portion and the template substrate, the first wing portion including a plurality of protrusions protruding downward, and at least some of the plurality of protrusions having a tapered shape and a slope inclined with respect to the thickness direction of the template substrate.

[0005] 1 is a plan view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 1 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 2 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 3 is a perspective view showing the configuration of a protrusion; FIG. 4 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 5 is a cross-sectional view showing the configuration of a semiconductor substrate according to the present embodiment; FIG. 6 is a flowchart showing a method for manufacturing a semiconductor substrate according to the present embodiment; FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to the present embodiment; FIG. 8 is a block diagram showing a semiconductor substrate manufacturing apparatus according to the present embodiment; FIG. 9 is a flowchart showing a method for manufacturing a semiconductor device according to the present embodiment; FIG. 10 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the present embodiment; FIG. 11 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the present embodiment; FIG. 12 is a cross-sectional view showing a method for manufacturing a template substrate; FIG. 13 is a cross-sectional view showing a method for forming a GaN crystal portion of an initial wing portion by ELO; FIG. 14 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1; FIG. 15 is a plan view showing a semiconductor substrate according to Example 1; FIG. 16 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 1; FIG. 17 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 1; FIG. 18 is a measurement result of a nitride semiconductor fabricated using the semiconductor substrate according to Example 1; FIG. 19 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 1; FIG. 20 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 2; FIG. 21 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 3; FIG. FIG. 10 is a cross-sectional view showing a manufacturing method of a semiconductor substrate according to Example 6. FIG. 11 is a schematic view showing the configuration of an electronic device according to Example 7. FIG. 12 is a cross-sectional view showing the configuration of a protrusion in each example. FIG. 13 is a flowchart showing a manufacturing method of a semiconductor substrate according to the present embodiment. FIG. 14 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the present embodiment. FIG. 15 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the present embodiment.

[0006] [Embodiment] Fig. 1 is a plan view showing the configuration of a semiconductor substrate according to this embodiment. Figs. 2 and 3 are cross-sectional views showing the configuration of a semiconductor substrate according to this embodiment. As shown in Figs. 1 to 3, a semiconductor substrate 10 includes a template substrate TS and a first semiconductor portion 8A located above the template substrate TS and including a nitride semiconductor. The first semiconductor portion 8A includes a first wing portion F1. A first gap J1 is located between the first wing portion F1 and the template substrate TS. The first wing portion F1 includes a plurality of protrusions Q protruding downward, and at least one of the plurality of protrusions (one of the protrusions) has a tapered shape and a slope W that is inclined with respect to the thickness direction Z of the template substrate TS.

[0007] The first wing portion F1 of the semiconductor substrate 10 is spaced apart from the template substrate TS and includes a plurality of protrusions Q that protrude downward. Therefore, when a light-emitting functional layer is formed above the first wing portion F1, the light extraction efficiency from the lower surface (rear surface) is improved. That is, compared to when the rear surface is flat, the amount of light reflected toward the functional layer is reduced, and the amount of light emitted to the outside is increased. Furthermore, because the first wing portion F1 of the semiconductor substrate 10 is spaced apart from the template substrate TS and includes a plurality of protrusions Q that protrude downward, internal stress is reduced. This allows a high-quality functional layer (including an active layer) to be formed above the first wing portion F1.

[0008] The first semiconductor portion (first semiconductor layer) 8A contains a nitride semiconductor as a main component. The nitride semiconductor can be expressed as AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), for example. Specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN.

[0009] The first semiconductor portion 8A may be doped (for example, n-type containing donors) or non-doped. １７ / cm３ The seed portion S1 may contain a higher concentration than the above, in which case the etching rate is increased. A semiconductor substrate refers to a substrate containing a semiconductor, and the main substrate 1 included in the template substrate TS may contain a semiconductor (e.g., silicon, silicon carbide) or may not contain a semiconductor. A sapphire substrate is an example of a main substrate 1 that does not contain a semiconductor. The template substrate TS is also sometimes called a growth substrate. The main substrate 1 may be a free-standing substrate (wafer). The seed portion S1 can be formed using a sputtering method. Of course, it may also be formed using a metal organic chemical vapor deposition (MOCVD) method, molecular beam epitaxy (MBE) method, or the like. The seed portion S1 can be formed using a gallium nitride film (GaN), an aluminum nitride film (AlN), or a mixed crystal film of gallium and aluminum (e.g., AlGaN, InGaN, AlInGaN). A buffer portion (e.g., a single layer of AlN or a multilayer of AlN and AlGaN) may be provided between the main substrate 1 and the seed portion S1. Examples of such a configuration include sapphire substrate (main substrate) / AlN / GaN (seed portion), sapphire substrate (main substrate) / AlN / AlGaN / GaN (seed portion), and silicon substrate (main substrate) / Al / AlN / GaN (seed portion).

[0010] The first direction X1 may be the a-axis direction (<11-20> direction) of the first semiconductor portion 8A (nitride semiconductor such as GaN). The second direction X2 may be the m-axis direction (<1-100> direction) of the first semiconductor portion 8A. The thickness direction Z of the semiconductor substrate 10 (thickness direction of the template substrate TS) may be the c-axis direction (<0001> direction) of the first semiconductor portion 8A.

[0011] The first semiconductor portion 8A may be formed by an epitaxial lateral overgrowth (ELO) method, starting from the seed portion S1, and may include a first protrusion R1 connected to the seed portion S1 and a first base B1 connected to the first protrusion R1 and the first wing F1. The base B1 of the first semiconductor portion 8A, located above the seed portion S1, becomes a dislocation inheritance portion with many threading dislocations, while the first wing F1, located above the growth inhibition region DA, becomes a low-defect portion with a lower threading dislocation density than the dislocation inheritance portion. The second semiconductor portion 8C may grow laterally over the growth inhibition region DA starting from the seed portion S2, and growth may be stopped before joining the first semiconductor portion 8A. The threading dislocation density of the first wing F1 may be 5×10 ６ [pcs / cm ２ ] or less. The first wing portion F1 may have an edge. Furthermore, after the first semiconductor portion 8A and the second semiconductor portion 8C are joined, the joining portion may be removed by etching or the like to form the gap GP.

[0012] As shown in FIG. 2 , in the semiconductor substrate 10, the first protrusion R1 and the first wing F1 may be composed of the same GaN-based semiconductor (e.g., GaN). As shown in FIG. 3 , in the semiconductor substrate 10, a GaN-based semiconductor alloy containing at least one of aluminum (Al) and indium (In) may be exposed below the first wing F1. The first protrusion R1 and the first wing F1 may be composed of different GaN-based semiconductors. For example, the first protrusion R1 may be a GaN crystal, and the first wing F1 may be a GaN-based alloy (ternary or quaternary alloy) containing at least one of Al and In. The first wing F1 may be an AlGaN base material, an AlInGaN base material, or an InGaN base material.

[0013] The +c plane of the nitride semiconductor may be exposed on the upper surface of the first wing portion F1, and the −c plane of the nitride semiconductor may be exposed on the lower surface of the first wing portion F1. The +c plane may be a gallium-polar plane, an aluminum-polar plane, or an indium-polar plane, and the −c plane may be a nitrogen-polar plane. For example, by visually observing a TEM image of the upper surface of the first wing portion F1, the arrangement of Ga particles and N particles resulting from the wurtzite structure and the spacing between the particles can be observed, thereby observing the shape of the (0001) plane (c-plane) polar plane crystal lattice. Alternatively, for example, by visually observing a TEM image of a cross section of the upper surface of the first wing portion F1 in the thickness direction (Z direction), it may be possible to determine that the upper surface is a Ga-polar plane by observing that Ga particles resulting from the wurtzite structure protrude toward the upper surface.

[0014] FIG. 4 is an image showing an example of the shape of the protrusions. As shown in FIG. 4, each of the multiple protrusions Q included on the lower surface (back surface) of the first wing portion F1 may be pyramidal (pyramidal). The inclined surface W included in the protrusions Q may be a (10-1-1) plane inclined with respect to the (0001) plane (c-plane). The first wing portion F1 may have a low-defect portion LA having a lower defect density than the first base portion B1, and a protrusion group QG including the multiple protrusions Q may be located across the entire area below the low-defect portion LA of the first wing portion F1. The upper surface roughness of the first wing portion F1 may be smaller than the lower surface roughness of the first wing portion F1. The side surface roughness of the first wing portion F1 may be smaller than the lower surface roughness of the first wing portion F1. The side surface roughness of the first raised portion R1 may be smaller than the lower surface roughness of the first wing portion F1.

[0015] Dislocations (defects) in the first wing portion F1 can be observed by CL (Cathodeluminescence) measurement or by mapping the peak shift of a Raman scattering spectrum. The dislocation density (defect density) of the first wing portion F1 can be calculated and compared by counting the number of dislocations (defects) observed by the above measurement. The roughness of the first wing portion F1 can be calculated and compared by counting the number of protrusions Q per any area, for example, from AFM measurement results or SEM drawings. The roughness of the first wing portion F1 may be, for example, the maximum height roughness Rz that can be measured by AFM. Rz may be, for example, a value between 200 nm and 300 nm, or may be a value greater than 300 nm. Roughness measurement can be performed in the same way on the top surface roughness, bottom surface roughness, and side surface roughness of the first wing portion F1.

[0016] The protrusions Q may have various shapes as long as they protrude downward and have a slope inclined with respect to the thickness direction of the template substrate TS. The protrusions Q may be pyramidal, and a pyramidal protrusion Q may have a trapezoidal cross section in the thickness direction (Z direction) of the template substrate TS. The protrusions Q may have a polygonal cross section in a direction perpendicular to the thickness direction of the template substrate TS (X1-X2 plane direction). In this case, the shape does not have to be strictly polygonal, and may include, for example, a polygon with rounded vertices. The protrusions Q may have a shape with a rounded bottom end.

[0017] At least one protrusion Q of the protrusion group QG may have a lower defect density than the first base portion B1. At least one protrusion Q of the protrusion group QG may have a lower defect density than the portion of the low-defect portion LA of the first wing portion F1 other than the protrusions. As shown in FIG. 29 , for example, when the protrusion Q has a conical shape, a linear defect DL present inside may be shaped so that one slant surface connects to the other slant surface. In this case, the linear defect DL within the protrusion Q may be inclined with respect to the planar direction of the template substrate TS (the X1-X2 plane direction). The linear defect DL within the protrusion Q may be shaped so that it slopes upward with increasing distance from the first base portion B1 (sloping with respect to the X1-X2 plane in a direction away from the template substrate TS).

[0018] In the protrusion group QG, the at least two protrusions Q may be located apart or adjacent to each other. In the protrusion group QG, the at least two protrusions Q may have different shapes, for example, different pyramidal shapes. In the protrusion group QG, the inclination angles of the slopes of the at least two protrusions Q may be different in a cross section in the up-down direction (along the c-axis). The inclination angle of the slope may be an angle with respect to the thickness direction of the template substrate TS. In the protrusion group QG, the at least two protrusions Q may have different heights. In the protrusion group QG, when comparing the heights of the at least two protrusions Q, the one closer to the first base B1 may be higher, or the one closer to the first base B1 may be higher.

[0019] The thickness of the first wing portion F1 may be 15 μm or less, or 8.0 μm or less. The height of each of the multiple protrusions Q may be 20 nm or more, 50 nm or more, or 100 nm or more. The ratio of the width (size in the X1 direction) to the height (size in the Z direction, thickness) of the gap J1 may be 5.0 or more. The height (thickness) of the gap J1 may be the distance from the growth inhibition region DA to the tip of the protrusion Q. The height (thickness) of the gap J1 may be greater, for example, on the first base portion B1 side than on the edge side. The ratio of the thickness of the first wing portion F1 to the thickness of the gap J1 may be less than 2.0.

[0020] The semiconductor substrate 10 is located above the template substrate TS and has a second semiconductor portion 8C including a nitride semiconductor, the second semiconductor portion 8C includes a second wing portion F2, a gap J2 is located between the second wing portion F2 and the template substrate TS, and the second wing portion F2 may have a plurality of protrusions Q protruding downward.

[0021] The upper surface of the template substrate TS may include a growth inhibition region DA and two seed regions S1 and S2 adjacent to each other via the growth inhibition region DA. The growth inhibition region DA and the seed regions S1 and S2 may or may not be coplanar. The first wing portion F1 and the second wing portion F2 may be located above the growth inhibition region DA. The first semiconductor portion F1 may include a first raised portion R1 coupled to the seed region S1 and a first base portion B1 located above the seed region S1. The semiconductor substrate 10 may include a growth inhibition film 7 (e.g., a silicon oxide film or a silicon nitride film), and the growth inhibition film 7 may be located between the first raised portion R1 and the first base portion B1, on a side surface of the first raised portion R1, or on the growth inhibition region DA.

[0022] The material of the growth inhibition region DA may be a modified version of the material of the two seed regions S1 and S2. The material of the growth inhibition region DA may be an oxide of the two seed regions S1 and S2. The material of the two seed regions S1 and S2 may be aluminum nitride. The material of the growth inhibition region DA may be aluminum oxynitride.

[0023] The template substrate TS includes a main substrate 1, which may be a heterogeneous substrate having a lattice constant different from that of the nitride semiconductor included in the first semiconductor portion 8 A. Examples of the heterogeneous substrate 1 include a silicon substrate, a silicon carbide substrate, and a sapphire substrate.

[0024] 5 and 6 are cross-sectional views showing the configuration of a semiconductor substrate according to this embodiment. As shown in FIGS. 5 and 6, the semiconductor substrate 10 may include an upper layer portion UL located above the first semiconductor portion 8A. The upper layer portion UL may have a functional layer 9 including an active layer. The functional layer 9 may include an n-type layer and a p-type layer in addition to the active layer. The active layer of the functional layer 9 may be a light-emitting layer and may have a GaN-based multiple quantum well structure. The upper layer portion UL may include electrodes E (e.g., an anode and a cathode) in addition to the functional layer 9.

[0025] FIG. 7 is a flowchart showing a method for manufacturing a semiconductor substrate according to this embodiment. FIGS. 8 and 9 are cross-sectional views showing the method for manufacturing a semiconductor substrate according to this embodiment. As shown in FIGS. 7 to 9 , the method for manufacturing a semiconductor substrate according to this embodiment includes the steps of: forming an initial wing portion PF located above a template substrate TS, not in contact with the template substrate TS, including a nitride semiconductor, and having a nitrogen-polar surface 8N exposed on its underside; introducing an etchant YE into a gap J0 between the nitrogen-polar surface 8N of the initial wing portion PF and the template substrate TS; and etching the initial wing portion PF primarily from the nitrogen-polar surface 8N (rear surface) to form a first wing portion F1 having a plurality of protrusions Q protruding downward.

[0026] The method for manufacturing a semiconductor substrate according to this embodiment may include a step of removing a mask portion that is formed on the template substrate TS as a growth suppression region DA. As shown in FIG. 29 , the mask removal step may be step S15 between step S10 of forming the initial wing portion PF and step S20 of introducing the etching liquid YE. The mask portion may be made of silicon nitride (SiN) or silicon oxide (SiO ２ ) In step S15, the mask portion can be removed by introducing, for example, a hydrogen fluoride (HF) liquid into the gap J0. By removing the mask portion using the hydrogen fluoride liquid or the like (as a result of mask removal), the nitrogen-polar surface 8N of the initial wing portion PF and the gap J0 on the template substrate TS may be formed. In this way, by removing the mask portion before introducing the etching liquid YE, the risk of silicon (Si) being taken into the initial wing portion PF is reduced, and the quality of the first wing portion F1 can be improved.

[0027] Furthermore, the removal step can increase the height (length in the Z direction) of the gap J0. This makes it easier to introduce the etchant YE deep into the gap J0 (up to the vicinity of the first protrusion R1) in the subsequent step S20, reducing uneven etching in the width direction (first direction X1) of the wing portion F1. This results in a more uniform light extraction effect, enabling the realization of a high-quality light-emitting device.

[0028] Furthermore, the method may include a step of introducing an oxidizing agent into the gap J0 before or simultaneously with step S20. This allows a fine oxide film to be formed on the nitrogen polar surface 8N, and the resulting local difference in etching rate can be used as a starting point to form the protrusion Q by etching.

[0029] The initial wing portion PF is simultaneously etched at its lower surface, which is a nitrogen-polar surface 8N, its upper surface, which is a Ga-polar surface, and its side surfaces. Among these surfaces, the etching rate of the nitrogen-polar surface 8N (lower surface and rear surface) is extremely high, resulting in the nitrogen-polar surface 8N being almost selectively etched. The Ga-polar surface (upper surface) is also etched at a very slow rate. Therefore, even if there are slight anomalies or irregularities on the Ga-polar surface of the initial wing portion PF, this etching can form a clean (0001) surface (the upper surface of the first wing portion F1). This makes it possible to form a highly flat regrowth layer on the first wing portion F1, for example, using an MOCVD method, or to form a high-quality functional layer (device layer including an active layer) with a high yield. Furthermore, because a thin first wing portion is obtained by etching the initial wing portion PF, light emission from the side surfaces is suppressed when a light-emitting functional layer is formed on the first wing portion F1. This allows for the production of a light-emitting device (semiconductor device) with high light extraction efficiency and reduced risk of color interference (color mixing).

[0030] As shown in FIG. 9 , the initial wing portion PF includes a GaN crystal portion 11 with an exposed nitrogen-polar plane 8N, and a GaN mixed crystal portion 12 located on the GaN crystal portion 11 and containing at least one of aluminum and indium. The lower GaN crystal portion 11 may be removed by wet etching to form a first wing portion F1 (e.g., an AlGaN substrate, an AlInGaN substrate, an InGaN substrate, etc.) including all or part of the GaN mixed crystal portion 12.

[0031] 9, a GaN alloy crystal portion such as AlGaN is more difficult to form into a film with good crystallinity by ELO than a GaN crystal portion, but by forming a GaN alloy crystal layer L2 on a GaN crystal layer L1 formed by ELO using a seed region S1 as a starting point and then removing the wing portions (GaN crystal portions 11) of the GaN crystal layer L1, a GaN alloy crystal portion 12 (wing portions of the GaN alloy crystal layer L2) with low defects and little internal stress can be obtained as a first wing portion F1. Because the first protrusion R1 is included in the GaN crystal layer L1, the first protrusion R1 and the first wing portion F1 (GaN alloy crystal portion 12) may be made of different GaN-based semiconductors. That is, in a semiconductor substrate 10 comprising a template substrate TS including a seed region S1 and a first semiconductor portion 8A located above the template substrate TS and including a nitride semiconductor, the first semiconductor portion 8A has a first raised portion R1 in contact with the seed region S1 and a first wing portion F1 facing the template substrate TS across a first gap J1, the first wing portion F1 including at least one of Al (aluminum) and In (indium), and the first raised portion R1 may be composed of a GaN-based semiconductor (e.g., GaN) different from the first wing portion F1.

[0032] Fig. 10 is a block diagram showing a semiconductor substrate manufacturing apparatus according to this embodiment. The semiconductor substrate manufacturing apparatus 50 includes an apparatus M10 that performs step S10 in Fig. 7, an apparatus M40 (wet etching apparatus) that performs steps S20 and S30 in Fig. 7, and a control device MC that controls the apparatuses M10 and M40.

[0033] FIG. 11 is a flowchart illustrating a method for manufacturing a semiconductor device according to this embodiment. FIGS. 12 and 13 are cross-sectional views illustrating the method for manufacturing a semiconductor device according to this embodiment. As illustrated in FIGS. 11 to 13, the method for manufacturing a semiconductor device according to this embodiment includes a step S70 of preparing a semiconductor substrate 10, a step S80 of forming an upper layer portion UL (including a functional layer 9) above a first wing portion F1 to form an element portion DS, and a step S90 of separating the element portion DS from the template substrate TS to form a light-emitting element 15 (semiconductor device). In step S90, the base of the first wing portion F1 (the portion connected to the first base portion B1) may be broken by applying a downward external force. In step S90, the element portion DS may also be transferred from the template substrate TS to a substrate (such as a transfer substrate, a support substrate, or a submount substrate) separate from the template substrate TS.

[0034] In step S90, the base of the first wing portion F1 may be cut by dry etching or wet etching. The first wing portion F1 may be cut between multiple protrusions Q. The protrusions Q located at the end of the cut surface may be taller than at least one other protrusion Q. The protrusions Q located at the cut surface (end surface) may have a higher defect density than at least one protrusion Q not located at the cut surface. The light-emitting element 15 has multiple protrusions Q protruding downward, and therefore has excellent light extraction efficiency to the back side (lower side).

[0035] This semiconductor device manufacturing method does not necessarily have to include step S90 (the step of separating the element portion DS from the template substrate TS). For example, after step S80, a step of forming an opening KT in a portion of the template substrate TS that overlaps the first wing portion F1, as shown in FIGS. 31 and 32 , may be included. This allows light to be extracted through the opening KT. In other words, the light emitting element 15 (semiconductor device) can be formed without performing the separation step S90.

[0036] The opening KT of the template substrate TS may be located, for example, in a portion overlapping the functional layer 9 (including the active layer). The opening KT may be located, for example, in a portion overlapping the center of the first wing portion in the first direction X1. This can improve the efficiency of extracting light to the back side (lower side) of the template substrate TS. As shown in FIGS. 31 and 32 , the opening KT may overlap the anode EA in a plan view. The template substrate TS may include a silicon substrate or a silicon carbide substrate.

[0037] The opening KT of the template substrate TS may or may not penetrate the template substrate TS in the Z direction. If the opening KT does not penetrate the template substrate TS in the Z direction, for example, the template substrate TS may be made of a light-transmitting material such as sapphire. An optical member such as a microlens may be provided inside the opening KT. This allows the directivity of the light-emitting element 15 (semiconductor device) to be controlled. A phosphor member may be provided inside the opening KT. This allows the emission wavelength of the light-emitting element 15 (semiconductor device) to be converted to suit the application.

[0038] Example 1: FIG. 14 is a cross-sectional view showing a method for manufacturing a template substrate. As shown in FIG. 14 , after forming an underlayer 4 containing an underlayer material on a main substrate 1, the following steps may be performed: forming a resist RZ on the underlayer 4, patterning the resist RZ, subjecting the exposed underlayer material to plasma treatment, and removing the resist RZ. The underlayer 4 may be formed by sputtering. For example, the plasma treatment involves irradiating the exposed surface 4D of the underlayer 4 with argon plasma to modify the surface of the irradiated area, thereby forming a growth-inhibited region DA. By introducing not only argon gas but also oxygen gas, nitrogen gas, hydrogen gas, or the like into the chamber, the plasma treatment can also use oxygen plasma, nitrogen plasma, hydrogen plasma, or a mixture thereof in addition to argon plasma. As a result, the growth-inhibited region DA may contain impurities such as argon, oxygen, or nitrogen. In such a case, the underlayer material may be aluminum nitride, and the growth-inhibited region DA may be aluminum oxynitride. Alternatively, the underlying material may be AlScN (aluminum scandium nitride), and the growth inhibiting region DA may be AlScON (aluminum scandium oxynitride).

[0039] The underlayer 4 can be optimized depending on the material of the main substrate 1. For example, if the main substrate 1 is a silicon substrate, aluminum nitride can be used for the underlayer 4. For example, if the main substrate 1 is a sapphire substrate or a silicon carbide substrate, aluminum nitride, aluminum oxynitride, or gallium nitride can be used for the underlayer 4.

[0040] 15 is a cross-sectional view showing a method for ELO deposition of a GaN crystal portion in an initial wing portion. As shown in FIG. 10, the method includes the steps of preparing a template substrate TS including seed regions S1 and S2 and a growth inhibition region DA, vertically growing a first protrusion R1 from the seed region S1, forming a growth inhibition film 7 in contact with the first protrusion R1, and forming a first base B1 located above the first protrusion R1, and a GaN crystal portion 11 connected to the first base B1, separated from the growth inhibition region DA, and located above the gap J0.

[0041] 15 , the first base portion B1 and the GaN crystal portion 11 may be formed using a corner RC where the top surface RT and side surface RS of the first protrusion R1 intersect as a growth starting point PG. In this way, the corner RC may be used as the growth starting point PG, but this is not limitative. A defect (e.g., a minute opening) may be formed in the growth inhibiting film 7 on the first protrusion R1, and the defect in the growth inhibiting film 7 may be used as a growth starting point for the first base portion B1 and the GaN crystal portion 11.

[0042] The first protrusion R1, the growth suppression film 7, the first base portion B1, and the GaN crystal portion 11 may be successively formed using an MOCVD apparatus. The first protrusion R1 includes a GaN-based semiconductor, the growth suppression film 7 is silicon nitride, and a gallium source material (organic material such as trimethylgallium (TMG) or triethylgallium (TEG)) and a nitrogen source material (ammonia gas (NH ３ )) to form the first protrusion R1, and while maintaining the supply of the nitrogen source material, the supply of the gallium source material is stopped to supply a silicon-based material (e.g., SiH ４ ) and ammonia gas (NH ３ ) to form the growth suppression film 7 (in this case, a silicon nitride film). Note that oxygen or carbon may be added, or the growth suppression film 7 may be formed of a different material. Thereafter, while maintaining the supply of the nitrogen source raw material, the supply of the silicon-based material may be stopped and a gallium source raw material may be supplied to form the first base portion B1 and the GaN crystal portion 11. Alternatively, the supply of a small amount of silicon-based material may be continued at a doping level.

[0043] By forming the growth suppression film 7 in this manner, continuous film formation is possible without removing the substrate from the MOCVD apparatus, while forming the void J0 below the GaN crystal portion 11, thereby reducing manufacturing time and costs. By forming the void J0 and forming the GaN crystal portion 11 so that it does not come into contact with the underlayer 4 (growth suppression region DA), stress from the main substrate 1 and underlayer 4 can be effectively alleviated.

[0044] Here, the growth of two GaN crystal layers growing in opposite directions above the growth-inhibited region DA is stopped before they meet. This forms a gap GP, which allows the etchant YE to easily permeate the back surface, and fresh etchant YE can be constantly circulated through the gap above the growth-inhibited region DA by stirring. This suppresses variation in the shape of the protrusion Q on the back surface of the first wing portion F1. The width of the gap GP may be 0.5 μm or more, or 1.0 μm or more.

[0045] 16 is a cross-sectional view showing a manufacturing method of a semiconductor substrate according to Example 1. As shown in Fig. 16, an initial wing portion PF is formed by growing a GaN alloy crystal portion 12 on a GaN crystal portion 11, and the initial wing portion PF is etched from its rear surface (nitrogen-polar surface 8M) using an etching solution YL introduced into the gap J0, thereby removing the GaN crystal portion 11 and etching the rear surface (nitrogen-polar surface) of the GaN alloy crystal portion 12, thereby forming a first wing portion F1. An upper layer portion UL is formed on the first wing portion F1, thereby forming a device portion DS.

[0046] Fig. 17 is a plan view showing a semiconductor substrate according to Example 1. As shown in Fig. 17 , the anode EA and the cathode EC may be arranged on the functional layer 9 in the second direction X2 (e.g., the m-axis direction of the GaN mixed crystal portion 12), and the element portion DS is formed including the anode EA and the cathode EC.

[0047] 18 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Example 1. In Example 1 (FIGS. 16 to 18), the ELO deposition of the GaN crystal layer L1 and the formation of the growth suppression film 7 by MOCVD, the deposition of the GaN alloy layer L2 by MOCVD, the removal of the template substrate TS on which the initial wing layers PF (11 and 12) are formed from MOCVD, the removal (wet etching) of the GaN crystal portion 11 of the initial wing layer PF, the wet etching of the back surface (nitrogen polarity face) of the GaN alloy layer 12, and the first The following steps are performed in this order: introducing the semiconductor substrate 10 including the first wing portion F1 (GaN alloy crystal portion 12) into MOCVD; depositing the functional layer 9 (including the active layer) on the first wing portion F1 (GaN alloy crystal portion 12); removing the semiconductor substrate 10 including the functional layer 9 from MOCVD; forming electrodes E and the like on the functional layer 9 (including the active layer) (forming the element portion DS); and separating the element portion DS from the template substrate TS (forming the light-emitting element 15 by singulation). As shown in FIG. 18 , the first semiconductor portion 8A may be vertically divided at the portion adjacent to the growth inhibiting film 7 while the first semiconductor portion 8A is held by the support substrate PS, thereby separating the element portion DS from the template substrate TS and obtaining the light-emitting element (semiconductor device) 15 or a semiconductor device 25 including the support substrate PS and the light-emitting element 15. The first semiconductor portion 8A may be divided by cleavage. A portion GZ of the GaN crystal layer L1 may remain below the light-emitting element 15.

[0048] The light emitting element 15 (semiconductor device) comprises a nitride semiconductor substrate (first wing portion) F1 having a light extraction surface LF, and a functional layer 9 including an active layer. The nitride semiconductor substrate F1 has a plurality of protrusions Q on the light extraction surface LF, and each of the plurality of protrusions Q has a slope W inclined with respect to the thickness direction of the nitride semiconductor substrate F1. The threading dislocation density of the nitride semiconductor substrate F1 is 5×10 ６ [pcs / cm ２] or less. The nitride semiconductor base material (F1) may include at least one of a GaN crystal portion 11 and a GaN mixed crystal portion 12, and the light extraction surface LF may be a GaN crystal portion 11 (GaN) or a GaN mixed crystal portion 12 (AlGaN, InGaN, AlInGaN, etc.). At the light extraction surface LF, the -c plane ((000-1) plane), which is a nitrogen polarity plane, may be exposed between adjacent protrusions Q. A protrusion group including a plurality of protrusions Q may be formed over the entire surface of the light extraction surface LF of the nitride semiconductor base material F1.

[0049] The nitride semiconductor substrate (F1) is a nitride semiconductor crystal having a thickness of 8.0 μm or less, and the light extraction surface LF includes a plurality of pyramidal protrusions Q having a height of 100 nm or more, and the light extraction surface LF may include the −c plane of the nitride semiconductor. ６ [pcs / cm ２ ] or less.

[0050] FIG. 19 shows the results of measurement of the multiple protrusions Q of the nitride semiconductor substrate (F1) produced by this manufacturing method using an AFM (Atomic Force Microscope: Jupiter X manufactured by Oxford Instruments). In FIG. 19, the horizontal axis represents the horizontal length (μm), and the vertical axis represents the length (nm) in the thickness direction (z direction). According to FIG. 19, for one of the multiple protrusions Q, two adjacent minimum values ​​form the base, and the maximum value located between the two adjacent minimum values ​​forms the apex. For example, the range X1L in FIG. 19 shows the case where there are two protrusions Q. The maximum height Rz can be used to represent the roughness of the multiple protrusions Q. According to this measurement, the Rz of the multiple protrusions Q of the nitride semiconductor (F1) was 200 nm to 300 nm.

[0051] 16 and 17 , the functional layer 9 can be formed on the GaN mixed crystal portion 12 that is not in contact with the template substrate TS, thereby providing a significant stress relaxation effect on the functional layer 9. Furthermore, before forming the functional layer 9, the upper surface (gallium polar surface) of the initial wing layer PF is also finely etched, resulting in a clean and flat upper surface (front surface) of the first wing portion F1. Forming the functional layer 9 on such a first wing portion F1 allows for a high-quality functional layer 9. The height of the gap J0 (the distance between the initial wing layer PF and the growth suppression region DA) may be 10 nm or more so that the etchant YE can penetrate deep within. A height of 100 nm or more effectively suppresses uneven etching within the back surface.

[0052] In the first embodiment, the thickness of the first wing portion F1 may be 0.1 μm to 5.0 μm or 0.2 μm to 3 μm, and the width of the first wing portion F1 in the first direction X1 may be 20 μm to 200 μm. The ratio of the width to the thickness of the first wing portion F1 may be 2.0 or more, 3.0 or more, 5.0 or more, 10.0 or more, or 20 or more. The ratio of the width to the thickness (height) of the gap J1 in the first direction X1 may be 2.0 or more, 3.0 or more, 5.0 or more, 10.0 or more, or 20 or more.

[0053] The GaN mixed crystal portion 12 may be, for example, a ternary mixed crystal of AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1) or a quaternary mixed crystal. The GaN mixed crystal portion 12 may contain an additive such as Sc, and may be doped with an n-type dopant such as Si or Ge, or a p-type dopant such as Mg. The dopant may be unintentionally doped.

[0054] When manufacturing a short wavelength light emitting device 15, the GaN mixed crystal portion 12 is ０．１ Ga ０．９ The first wing portion F1 may be an AlGaN base material with an Al composition of 10% by removing the GaN crystal portion 11 as N. In this case, the emission wavelength of the light emitting element 15 may be 380 nm or less.

[0055] When manufacturing a medium wavelength light emitting device 15, the GaN mixed crystal portion 12 is ０．１５ Ga０．８５ The first wing portion F1 may be an InGaN base material with an In composition of 15% by removing the GaN crystal portion 11 as N. In this case, the emission wavelength of the light emitting element 15 may be 500 nm or more.

[0056] In Example 1, once the GaN mixed crystal portion 12 is formed, the template substrate TS on which the initial wing portions PF have been formed is removed from the MOCVD apparatus, and the initial wing portions PF are wet-etched. Because adjacent initial wing portions PF are spaced apart from each other on the growth inhibition region DA and the initial wing portions PF float above the growth inhibition region DA, the etching solution easily reaches the back surfaces (nitrogen-polar surfaces 8N) of the initial wing portions PF, and etching proceeds quickly.

[0057] As the etching solution, an alkaline solution such as potassium hydroxide (KOH) or sodium hydroxide (NaOH) can be used. Although etching is possible at room temperature, the etching rate increases when the solution is heated to about 80° C. The etching rate may be controlled by adjusting the concentration and temperature of the etching solution.

[0058] By using a template substrate TS with a c-plane or a plane orientation off-angled from the c-plane, the rear surface (lower surface) of the initial wing portion PF is exposed as a nitrogen (nitride) polarity plane, while the opposing front surface (upper surface) of the initial wing portion PF is a Ga, Al, or In polarity plane. Because the etching rate of a nitrogen polarity plane is significantly higher than that of a Ga, Al, or In polarity plane, the front surface (upper surface) of the initial wing portion PF (the upper surface of the GaN alloy crystal portion 12) is hardly etched, while the nitrogen polarity plane of the rear surface (lower surface) is unilaterally etched. This allows the GaN crystal portion 11 of the initial wing portion PF to be efficiently removed, and the upper surface of the GaN alloy crystal portion 12 is also slightly etched, improving the surface morphology. The first protrusion R1 of the GaN crystal layer L1 is hardly etched because the exposed side surface is not a nitrogen polarity plane.

[0059] On the back surface (lower surface) of the first wing F1 obtained by etching the initial wing portion PF, for example, numerous pyramidal (pyramidal) protrusions Q (convex bodies as shown in FIG. 4 ) surrounded by the {10-1-1} plane of the GaN mixed crystal appear. The back surface of the first wing F1 serves as a light extraction surface in the form of a device (light-emitting element), and the numerous protrusions Q increase the light extraction efficiency. In Example 1, in which the GaN crystal portion 11 is etched away, the first wing F1 can be formed thin, and therefore side light emission (which causes optical interference between elements) can be reduced in the form of a device (light-emitting element).

[0060] In Example 1, the GaN crystal portion 11 of the initial wing portion PF is completely removed, but a portion of the GaN crystal portion 11 of the initial wing portion PF may be left in order to increase the strength of the first wing portion F1. When a functional layer 9 that emits light with a wavelength shorter than 380 nm is formed on the first wing F1, it is better to remove the GaN crystal portion 11 because leaving it will absorb light from the functional layer 9.

[0061] When forming the functional layer 9 that emits light of 365 nm, a regrowth layer (0.05 μm thick Al ０．１ Ga ０．９ N), 5 pairs of multiple quantum wells (barrier layer: 15 nm thick Al ０．０７ Ga ０．９３ N, well layer: 3 nm thick AlInGaN), carrier block layer (20 nm thick Al ０．２５ Ga ０．７５ N), and p-type layer (contact layer: 20 nm thick Al ０．０７ Ga ０．９３ Alternatively, a 1.5 μm thick heavily doped layer of GaN may be formed in this order.

[0062] When forming the functional layer 9 that emits light with a wavelength longer than 500 nm, a regrowth layer (GaN with a thickness of 0.1 μm), three pairs of multiple quantum wells (barrier layer: Al with a thickness of 15 nm) are formed on the GaN mixed crystal portion 12. ０．０７ Ga ０．９３ N, well layer: 3 nm thick In ０．３３ Ga ０．６７ N), a carrier blocking layer (20 nm thick Al ０．１ Ga ０．９Alternatively, a GaN layer (contact layer: 20 nm thick GaN, heavily doped layer: 1.5 μm thick GaN) and a p-type layer (contact layer: 20 nm thick GaN, heavily doped layer: 1.5 μm thick GaN) may be formed in this order.

[0063] The electrodes E (anode, cathode) are formed in predetermined regions on the functional layer 9 using a sputtering device or an EB deposition device.

[0064] Fig. 20 is a cross-sectional view showing the method for manufacturing the semiconductor substrate according to Example 1. When the GaN alloy layer L2 is formed so as to fill the gaps GP between the GaN crystal portions 11 and the spaces below them, the filled portions are removed by dry etching or the like to separate the GaN alloy layer L2 in the first direction X1 (to form the GaN alloy portions 12 and the gaps GP), as shown in Fig. 20 , and then an etchant is introduced through the gaps GP to wet-etch the back surfaces (nitrogen-polar faces) of the GaN crystal portions 11 and 12.

[0065] Example 2 Figure 21 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 2. As shown in Figure 21, after successively depositing the GaN crystal layer L1, the GaN mixed crystal layer L2, and the functional layer 9 (including the active layer), the GaN crystal portion 11 of the initial wing layer PF may be removed (wet etching). Thereafter, electrodes E and the like are formed on the functional layer 9 (including the active layer) (forming the element portion DS), and the element portion DS is separated from the template substrate TS (forming the light-emitting element 15 by singulation). In Example 2, productivity (throughput) is improved because the template substrate TS is not removed from the MOCVD during the deposition of the nitride semiconductor.

[0066] 22 is a cross-sectional view showing a semiconductor substrate manufacturing method according to Example 3. As shown in Fig. 22, when the GaN crystal layer L1 is formed by ELO, GaN crystals growing in opposite directions on the growth suppression area DA may be interlocked with each other to form the GaN crystal layer L1 and the GaN alloy layer L2 in a planar shape. In this case, a gap GP is formed between the initial wing portions PF by dry etching or the like of the planar GaN crystal layer L1 and the GaN alloy layer L2, and an etchant YL can be introduced through this gap GP.

[0067] 23 and 24 are cross-sectional views showing a semiconductor substrate manufacturing method according to Example 4. As shown in FIG. 23 , initial wing portions PF (GaN crystal portions 11 and GaN mixed crystal portions 12) may be formed on the growth inhibition regions DA from seed regions S1 and S2 located on the upper surface of a convex (ridge-shaped) seed portion SB, thereby forming a gap J0 between the template substrate TS and the initial wing portion PF. The GaN crystal portion 11 may then be etched away from the rear surface using an etchant YL introduced into the gap J0, thereby forming a first wing portion F1. In Example 4, the thickness of the gap J0 can be easily designed by adjusting the height of the seed portion SB. Increasing the thickness of the gap J0 facilitates the etchant's penetration to the rear surface, thereby improving etching efficiency. As shown in FIG. 24 , the GaN crystal layer L1, the GaN mixed crystal layer L2, and the functional layer 9 (including the active layer) may be successively formed, followed by etching away the GaN crystal portion 11 of the initial wing layer PF.

[0068] 25 and 26 are cross-sectional views showing a semiconductor substrate manufacturing method according to Example 5. As shown in Fig. 25 , a GaN alloy layer L2 may be formed on a GaN crystal layer L1 formed by ELO so as to contact a mask portion 5 (growth suppression region) through a mask opening K1 that functions as a seed region S. The mask portion 5 may then be removed to form a gap J0 between the template substrate TS and the initial wing portion PF. The GaN crystal portion 11 may then be etched using an etchant YL introduced into the gap J0 to form a first wing portion F1. As shown in Fig. 26 , after the GaN crystal layer L1, the GaN alloy layer L2, and the functional layer 9 (including the active layer) are successively formed, the GaN crystal portion 11 of the initial wing layer PF may be etched away.

[0069] Example 6 Figure 27 is a cross-sectional view showing a method for manufacturing a semiconductor substrate according to Example 6. In Figure 23, the GaN crystal portion 11 below the GaN mixed crystal portion 12 is completely removed by etching, but this is not limiting. As shown in Figure 27, the first wing portion F1 may be formed by etching the initial wing portion PF so that part of the GaN crystal portion 11 remains below the GaN mixed crystal portion 12.

[0070] Example 7 Fig. 28 is a schematic diagram showing the configuration of an electronic device according to Example 7. Electronic device 55 in Fig. 28 includes a light-emitting element (semiconductor device) 15, a drive substrate 23 on which light-emitting element 15 is mounted, and a control circuit 27 that controls drive substrate 23. Drive substrate 23 may include a CMOS. Examples of electronic device 55 include a light-emitting device, a display device, a laser emission device (including a Fabry-Perot type and a surface-emitting type), a measurement device, a lighting device, a communication device, an information processing device, and a power control device.

[0071] (Note) The above disclosure is intended to be illustrative and explanatory, and is not intended to be limiting. Based on these examples and explanations, many variations will be obvious to those skilled in the art, and it should be noted that these variations are also included in the embodiments.

[0072] REFERENCE SIGNS LIST 1 Main substrate 4 Underlayer 7 Growth suppression film 8A First semiconductor portion 8C Second semiconductor portion 10 Semiconductor substrate 11 GaN crystal portion 12 GaN mixed crystal portion 15 25 Light emitting element (semiconductor device) L1 GaN crystal layer L2 GaN mixed crystal layer R1 First protrusion B1 First base portion F1 First wing portion F2 Second wing portion J0, J1, J2 Void S1 Seed portion DA Growth suppression region TS Template substrate

Claims

1. A step of preparing a substrate comprising: a template substrate; a first semiconductor portion located above the template substrate and containing a nitride semiconductor, wherein the first semiconductor portion has a first initial wing portion having a nitrogen polar surface facing the template substrate via a gap; The process includes introducing an etching solution into the aforementioned void, A method for manufacturing a semiconductor substrate, wherein the nitrogen polar surface of the first initial wing portion is etched with the etching solution, and a first wing portion having a plurality of protrusions projecting downward is formed.

2. The upper surface of the template substrate is provided with a first seed region, The first semiconductor portion comprises a first raised portion extending upward from the first seed region and a first base portion located on the first raised portion. The method for manufacturing a semiconductor substrate according to claim 1, wherein the first initial wing portion extends from the first base portion in a direction along the upper surface of the template substrate.

3. The method for manufacturing a semiconductor substrate according to claim 2, wherein the side surface of the first raised portion is not a nitrogen polar surface.

4. The method for manufacturing a semiconductor substrate according to claim 2, wherein, after the step of introducing the etching solution, the side surface roughness of the first raised portion is smaller than the bottom surface roughness of the first wing portion.

5. The method for manufacturing a semiconductor substrate according to claim 1, further comprising the step of forming a functional layer above the first wing portion after the step of introducing the etching solution.

6. The method for manufacturing a semiconductor substrate according to claim 5, further comprising the step of separating the first wing portion and the functional layer from the template substrate after the step of forming the functional layer.

7. The method for manufacturing a semiconductor substrate according to claim 1, wherein the +c surface is exposed on the upper side of the first initial wing portion.

8. The method for manufacturing a semiconductor substrate according to claim 1, wherein the Ga polar surface is exposed on the upper side of the first initial wing portion.

9. The method for manufacturing a semiconductor substrate according to claim 1, wherein, after the step of introducing the etching solution, the side surface roughness of the first wing portion is smaller than the bottom surface roughness of the first wing portion.

10. The method for manufacturing a semiconductor substrate according to claim 1, wherein after the step of introducing the etching solution, the thickness of the first wing portion is 15 μm or less.

11. The template substrate comprises a mask portion adjacent to the first seed region, The method for manufacturing a semiconductor substrate according to claim 2, further comprising the step of removing the mask portion before the step of introducing the etching solution.

12. The method for manufacturing a semiconductor substrate according to claim 1, wherein the template substrate is a substrate with a C-plane or a surface orientation having an off-angle from the C-plane.

13. The method for manufacturing a semiconductor substrate according to claim 1, wherein the plurality of protrusions include an inclined surface that is a (10-1-1) plane.

14. The method for manufacturing a semiconductor substrate according to claim 1, wherein the upper surface of the first initial wing portion is also etched with the etching solution.