Semiconductor package and RF module

Abstract

This semiconductor package comprises an RFIC, a multilayer substrate, and an RF signal path. The RFIC has an RF pad for inputting and outputting an RF signal. The multilayer substrate has a first outer surface facing the RF pad and a second outer surface opposite to the first outer surface. The multilayer substrate includes three or more conductor layers. The RF signal path propagates the RF signal. The RF signal path includes an RF terminal, an RF external terminal, an RF redistribution wire, and a plurality of filled vias. The RF terminal electrically connects the RF pad and a conductor provided on the first outer surface. The RF external terminal is electrically connected to a conductor provided on the second outer surface. The RF redistribution wire has a first end part overlapping the RF terminal in a plan view, and a second end part overlapping the RF external terminal in the plan view. The RF redistribution wire is provided only in one of the conductor layers. The plurality of filled vias are located in the multilayer substrate.

Description

Semiconductor package and RF module

[0001] The present invention relates to a semiconductor package and an RF module. This application claims priority to Japanese Patent Application No. 2023-190555, filed on November 8, 2023, the contents of which are incorporated herein by reference.

[0002] Patent Document 1 discloses a semiconductor package including a semiconductor chip and a multilayer substrate (rewiring substrate). The multilayer substrate has a first outer surface on which terminals (bonding terminals) are provided and a second outer surface located opposite the first outer surface on which external terminals (conductive terminals) are provided. The terminals are connected to the semiconductor chip. The external terminals are connected to the mounting substrate when the semiconductor package is mounted on the mounting substrate.

[0003] This semiconductor package has a signal path formed therein that connects the terminals and the external terminals and propagates electrical signals input to and output from the semiconductor chip. This signal path includes a plurality of rewirings (first to fourth rewiring patterns). In the semiconductor package of Patent Document 1, the rewirings are provided on different conductive layers. Each of the rewirings extends in an in-plane direction.

[0004] Japanese Patent Application Publication No. 2022-138124

[0005] Incidentally, in the semiconductor package of Patent Document 1, for example, multiple rewirings are provided on different layers, and therefore the distance between each rewiring and the mounting substrate varies. In the case of a semiconductor package that handles RF signals (i.e., when the above-mentioned semiconductor chip is an RFIC), there is a possibility that RF signals may leak from each rewiring (RF rewiring) toward a wiring pattern or the like included in the mounting substrate. Therefore, it is preferable to provide an isolation structure on the mounting substrate or the like to prevent such RF signal leakage (i.e., to achieve RF signal isolation). However, when the distance to the mounting substrate varies for each rewiring, as in the semiconductor package of Patent Document 1, for example, it is difficult to provide such an isolation structure.

[0006] The present invention has been made in consideration of the above circumstances, and has as its object to provide a semiconductor package and an RF module that can easily achieve isolation of RF signals.

[0007] In order to solve the above problem, a semiconductor package according to a first aspect of the present invention comprises an RFIC having an RF pad for inputting and outputting an RF signal, a multilayer substrate having a first outer surface facing the RF pad and a second outer surface opposite the first outer surface and including three or more conductor layers, and an RF signal path for propagating the RF signal, wherein the RF signal path has an RF terminal electrically connecting the RF pad and a conductor provided on the first outer surface, an RF external terminal electrically connected to a conductor provided on the second outer surface, a first end overlapping with the RF terminal in a planar view, and a second end overlapping with the RF external terminal in a planar view, and includes RF rewiring provided only on a single conductor layer, and a plurality of filled vias located in the multilayer substrate, and the RF terminal and the RF external terminal are electrically connected via the RF rewiring and the plurality of filled vias.

[0008] According to the first aspect of the present invention, the RF redistribution lines are provided only on a single conductive layer. Therefore, when the semiconductor package is mounted on a mounting substrate, the distance between the RF redistribution lines and the mounting substrate is constant. This makes it easier to achieve isolation of RF signals between the RF redistribution lines and the mounting substrate.

[0009] In addition, according to a second aspect of the present invention, in the semiconductor package of the first aspect, the height of the RF terminal is equal to or greater than the thickness of the RF rewiring.

[0010] A third aspect of the present invention is the semiconductor package of the second aspect, wherein the RFIC has a high-frequency circuit block, and at least a portion of the RF rewiring overlaps with the high-frequency circuit block in a plan view.

[0011] Furthermore, in a fourth aspect of the present invention, the semiconductor package of the second or third aspect further includes a second signal path that propagates a second signal different from the RF signal, wherein the RFIC has a high-frequency circuit block and a second pad for inputting and outputting the second signal, and the second signal path includes a second terminal that electrically connects the second pad and a conductor provided on the first outer surface, a second external terminal that is electrically connected to the conductor provided on the second outer surface and is different from the RF external terminal, a second rewiring that is provided in the conductor layer and is different from the RF rewiring, and a plurality of second filled vias that are located in the multilayer substrate and are different from the plurality of filled vias, and the second terminal and the second external terminal are electrically connected via the second rewiring and the plurality of second filled vias, and at least a portion of the second rewiring overlaps with the high-frequency circuit block in a planar view.

[0012] A fifth aspect of the present invention is the semiconductor package of any one of the second to fourth aspects, wherein the RFIC has a high-frequency circuit block, and at least a portion of the RF external terminal overlaps with the high-frequency circuit block in a plan view.

[0013] Furthermore, a sixth aspect of the present invention relates to a semiconductor package according to any one of the second to fifth aspects, further comprising a second signal path that propagates a second signal different from the RF signal, wherein the RFIC has a high-frequency circuit block and a second pad for inputting and outputting the second signal, and the second signal path includes a second terminal that electrically connects the second pad and a conductor provided on the first outer surface, a second external terminal that is electrically connected to the conductor provided on the second outer surface and is different from the RF external terminal, a second rewiring that is provided in the conductor layer and is different from the RF rewiring, and a plurality of second filled vias that are located in the multilayer substrate and are different from the plurality of filled vias, and the second terminal and the second external terminal are electrically connected via the second rewiring and the plurality of second filled vias, and at least a portion of the second external terminal overlaps with the high-frequency circuit block in a planar view.

[0014] Furthermore, aspect 7 of the present invention is a semiconductor package according to any one of aspects 1 to 6, wherein the RFIC has a high-frequency circuit block, the multilayer substrate is provided with a first shield formed of metal, and at least a portion of the first shield overlaps with the high-frequency circuit block in a planar view.

[0015] Furthermore, aspect 8 of the present invention is a semiconductor package according to any one of aspects 1 to 7, in which a second shield formed of metal is provided on the multilayer substrate, and in the thickness direction of the multilayer substrate, the distance between the second shield and the first outer surface is shorter than the distance between the RF rewiring and the first outer surface, and at least a portion of the second shield overlaps with the RF rewiring in a planar view.

[0016] Furthermore, aspect 9 of the present invention is a semiconductor package according to any one of aspects 1 to 8, in which the multilayer substrate is provided with a third shield formed of metal, and in the thickness direction of the multilayer substrate, the distance between the third shield and the second outer surface is shorter than the distance between the RF rewiring and the second outer surface, and at least a portion of the third shield overlaps with the RF rewiring in a planar view.

[0017] A tenth aspect of the present invention is the semiconductor package of any one of the first to ninth aspects, wherein the RF signal path includes a stacked via portion in which a plurality of the filled vias are stacked.

[0018] Furthermore, in an eleventh aspect of the present invention, in the semiconductor package of any one of the first to tenth aspects, the rewiring is an impedance-matched wiring.

[0019] A twelfth aspect of the present invention is the semiconductor package of any one of the first to eleventh aspects, wherein the multilayer substrate is formed of a coreless material.

[0020] A thirteenth aspect of the present invention is the semiconductor package of any one of the first to twelfth aspects, wherein the multilayer substrate includes a plurality of dielectric layers formed from the same material.

[0021] A fourteenth aspect of the present invention is the semiconductor package of any one of the first to thirteenth aspects, wherein the RF external terminals are located on the outermost periphery of the semiconductor package in a plan view.

[0022] Furthermore, an RF module according to aspect 15 of the present invention comprises a plurality of semiconductor packages according to any one of aspects 1 to 14, and a mounting substrate having a plurality of antennas and on which the plurality of semiconductor packages are mounted.

[0023] According to the above aspects of the present invention, it is possible to provide a semiconductor package and an RF module that can easily achieve isolation of RF signals.

[0024] Fig. 5 is a plan view of a semiconductor package according to an embodiment of the present invention. Fig. 6 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 7 is a plan view of an RF module according to an embodiment of the present invention. Fig. 8 is a cross-sectional view of a semiconductor package according to a first modified example of the present invention. Fig. 9 is a cross-sectional view of a semiconductor package according to a second modified example of the present invention. Fig. 10 is a cross-sectional view taken along line VI-VI shown in Fig. 5.

[0025] Hereinafter, a semiconductor package and an RF module according to an embodiment of the present invention will be described with reference to the drawings.

[0026] 1 and 2 , the semiconductor package 1 according to this embodiment includes an RFIC 10, a molded resin 20, a multilayer substrate 30, a first shield 41, and a second shield 42. However, the semiconductor package 1 does not necessarily need to include the first shield 41 and the second shield 42.

[0027] 2, the RFIC 10 has a plurality of pads 11. The multilayer substrate 30 has a first outer surface 30a facing the plurality of pads 11 and a second outer surface 30b located on the opposite side to the first outer surface 30a.

[0028] 3 , the semiconductor package 1 is used as a component constituting an RF module 3. The RF module 3 includes a mounting substrate 2 and a plurality of (four in the illustrated example) semiconductor packages 1 mounted on the mounting substrate 2. Although detailed illustration is omitted, the semiconductor package 1 is mounted on the mounting substrate 2 by electrically connecting external terminals T2 (details of which will be described later) of the semiconductor package 1 to the mounting substrate 2.

[0029] Examples of materials that can be used to form the mounting substrate 2 include epoxy and PPE (modified polyphenylene ether). The mounting substrate 2 may be a build-up substrate that includes a core material such as glass cloth.

[0030] The mounting board 2 has a main surface 2s (the surface facing the page) and a mounting surface (the surface facing the back of the page). The mounting board 2 has a plurality of antennas 2a. The antennas 2a are arranged in a rectangular lattice pattern on the main surface 2s. The semiconductor package 1 is mounted on the mounting surface. The main surface 2s is the surface opposite to the mounting surface.

[0031] In the illustrated example, the multiple antennas 2a configure multiple subarrays 2c. Each subarray 2c includes two antennas 2a and a signal line 2b electrically connected to the two antennas 2a. However, the number, arrangement, and configuration of the antennas 2a are merely examples and can be changed as appropriate.

[0032] (Direction Definition) In this specification, the thickness direction of the semiconductor package 1 (multilayer substrate 30) is simply referred to as the "thickness direction Z." The direction from the second outer surface 30b to the first outer surface 30a along the thickness direction Z is referred to as the upward or +Z direction. The direction opposite to the +Z direction is referred to as the downward or -Z direction. Viewing from the thickness direction Z is referred to as a planar view. FIG. 1 is a plan view of the semiconductor package 1 viewed from above (the +Z side). FIG. 3 is a plan view of the RF module 3 viewed from below (the -Z side). Furthermore, each direction intersecting the thickness direction Z (i.e., a direction parallel to the multilayer substrate 30) is referred to as an in-plane direction. One of the in-plane directions is referred to as the first direction X. One direction in the first direction X is referred to as the +X direction or rightward. The direction opposite to the +X direction is referred to as the -X direction or leftward. Among the in-plane directions, a direction that intersects (for example, is perpendicular to) the first direction X is referred to as the second direction Y. One direction in the second direction Y is referred to as the +Y direction. The direction opposite to the +Y direction is referred to as the −Y direction.

[0033] The RFIC 10 is configured to process high-frequency signals (RF signals) of, for example, 28 GHz or 60 GHz. As shown in Figures 1 and 2, the RFIC 10 according to this embodiment has a plurality of pads 11, two high-frequency circuit blocks 12, and a plurality of terminals T1. Note that the numbers of pads 11, high-frequency circuit blocks 12, and terminals T1 of the RFIC 10 can be changed as appropriate.

[0034] 2, each pad 11 is provided on the lower surface of the RFIC 10. Each pad 11 is made of, for example, aluminum.

[0035] The multiple pads 11 can be classified into RF pads 11a, GND pads (detailed illustration omitted), digital signal pads (detailed illustration omitted), and power supply pads (detailed illustration omitted) according to their functions. The RF pads 11a are pads for inputting and outputting RF signals and are electrically connected to the high-frequency circuit block 12. The GND pads are pads electrically connected to a GND circuit (not shown) included in the RFIC 10 and function as a GND potential. The digital signal pads are pads for inputting and outputting digital signals and are electrically connected to a digital circuit (not shown) included in the RFIC 10. The power supply pads are pads for supplying driving power to each component of the RFIC 10. Note that the pads 11 (GND pads, digital signal pads, and power supply pads) other than the RF pads 11a may be collectively referred to as "second pads 11b" (detailed illustration omitted in this embodiment).

[0036] The multiple terminals T1 according to this embodiment are provided in one-to-one correspondence with the multiple pads 11. Each terminal T1 is electrically and mechanically connected to the lower surface of the corresponding pad 11 and protrudes downward from the lower surface of the corresponding pad 11. Each terminal T1 is made of a metal. Examples of metals that may be used to make the terminals T1 include SAC305, SAC405, Cu, Ti, and Cr, as well as combinations of these metals.

[0037] In this specification, the terminal T1 connected to the RF pad 11a is referred to as the RF terminal T1a. The terminal T1 connected to the GND pad is referred to as the GND terminal (detailed illustration omitted), the terminal T1 connected to the digital signal pad is referred to as the digital terminal (detailed illustration omitted), and the terminal T1 connected to the power supply pad is referred to as the power supply terminal (detailed illustration omitted). The terminals T1 (GND terminal, digital terminal, and power supply terminal) other than the RF terminal T1a may be collectively referred to as the "second terminal T1b."

[0038] The height of each terminal T1 (e.g., RF terminal T1a) may be equal to or greater than the thickness of the rewiring 31 (e.g., RF rewiring 31a; details will be described later) of the multilayer substrate 30. For example, the height of the terminal T1 may be 30 μm or greater. Note that the terms "height" and "thickness" in this specification refer to dimensions in the thickness direction Z. By making the height of the terminal T1 sufficiently large, a gap G1 is generated in the thickness direction Z between the lower surface of the RFIC 10 and the first outer surface 30a of the multilayer substrate 30.

[0039] The terminals T1 may be arranged at a pitch of, for example, about 0.2 mm in the in-plane direction.

[0040] The multiple terminals T1 may be arranged such that the RF terminals T1a are not adjacent to each other in the in-plane direction.

[0041] A passivation film (not shown) for protecting the RFIC 10 may be provided on the underside of the RFIC 10. However, an opening may be formed in the portion overlapping the pad 11 (terminal T1) to enable input and output of signals through the pad 11 (terminal T1). Examples of the passivation film include a nitride film and an oxide film.

[0042] The high-frequency circuit block 12 is an analog circuit that processes RF signals. RF signals are transmitted and received between the antenna 2 a and the high-frequency circuit block 12 via the pad 11, a signal path P (described later), and a conductive path (e.g., the above-mentioned signal line 2 b) within the mounting substrate 2.

[0043] 1, the mold resin 20 surrounds the RFIC 10 in a plan view. Epoxy or the like can be used as a specific example of the material of the mold resin 20. The mold resin 20 may also contain a filler such as silica.

[0044] 2 , in this embodiment, the molded resin 20 is filled in the gap G1 between the RFIC 10 and the multilayer substrate 30. As a result, the molded resin 20 according to this embodiment is in contact with the RFIC 10 from the outside in the in-plane directions (first direction X and second direction Y) and from the bottom side in the thickness direction Z. The molded resin 20 is also in contact with the first outer surface 30 a of the multilayer substrate 30.

[0045] Filling the gap G1 with the mold resin 20 can improve the strength and reliability of the electrical connection of the semiconductor package 1. However, the gap G1 does not have to be filled with the mold resin 20. For example, the gap G1 may be filled with an underfill resin (epoxy or the like) instead of the mold resin 20.

[0046] On the other hand, it is preferable to leave the upper surface of the RFIC 10 exposed without providing the mold resin 20 or the like on the upper surface of the RFIC 10. This can improve the heat dissipation of the RFIC 10. Alternatively, a structure for improving heat dissipation (a heat dissipation sheet, a heat dissipation fin, etc.) may be provided on the upper surface of the RFIC 10.

[0047] The multilayer substrate 30 includes a plurality (three in the illustrated example) of dielectric layers D (first dielectric layer D1 to third dielectric layer D3) and a plurality (four in the illustrated example) of conductor layers C (first conductor layer C1 to fourth conductor layer C4). However, the number of dielectric layers D included in the multilayer substrate 30 can be changed as appropriate, provided that it is two or more. Similarly, the number of conductor layers C included in the multilayer substrate 30 can be changed as appropriate, provided that it is three or more.

[0048] Each of the dielectric layers D1 to D3 is a layer formed from a dielectric material such as resin. The multiple dielectric layers D1 to D3 may be formed from the same material. Furthermore, the material forming each of the dielectric layers D1 to D3 may be a coreless material (i.e., a material that does not contain glass cloth). However, the material forming each of the dielectric layers D1 to D3 can be changed as appropriate.

[0049] The plurality of dielectric layers D1 to D3 are stacked in the thickness direction Z. Specifically, the plurality of dielectric layers D1 to D3 are stacked such that the first dielectric layer D1, the second dielectric layer D2, and the third dielectric layer D3 are arranged in this order from top to bottom. The upper surface of the first dielectric layer D1 corresponds to the first outer surface 30a, and the lower surface of the third dielectric layer D3 corresponds to the second outer surface 30b.

[0050] The conductor layers C1 to C4 are layers on which a conductor such as a metal may be disposed. The conductor layers C1 to C4 are located between the dielectric layers D1 to D3 in the thickness direction Z, on the first outer surface 30a, and on the second outer surface 30b. Specifically, the first conductor layer C1 is located on the upper surface (first outer surface 30a) of the first dielectric layer D1. The second conductor layer C2 is located between the lower surface of the first dielectric layer D1 and the upper surface of the second dielectric layer D2. The third conductor layer C3 is located between the lower surface of the second dielectric layer D2 and the upper surface of the third dielectric layer D3. The fourth conductor layer C4 is located on the lower surface (second outer surface 30b) of the third dielectric layer D3.

[0051] A plurality of external terminals T2 for external connection are provided on the lower surface (second outer surface 30b) of the fourth conductive layer C4. The external terminals T2 are connected to, for example, the mounting substrate 2 (for example, pads formed on the mounting substrate 2). The plurality of external terminals T2 are electrically connected to the plurality of terminals T1 through signal paths P, which will be described later.

[0052] In this specification, the external terminal T2 connected to the RF terminal T1a is referred to as the RF external terminal T2a. Also, the external terminal T2 connected to the GND terminal is referred to as the GND external terminal (detailed illustration omitted), the external terminal T2 connected to the digital terminal is referred to as the digital external terminal (detailed illustration omitted), and the external terminal T2 connected to the power terminal is referred to as the power external terminal (detailed illustration omitted). Note that the external terminals T2 other than the RF external terminal T2a (the GND external terminal, the digital external terminal, and the power external terminal) may be collectively referred to as the "second external terminal T2b."

[0053] Each external terminal T2 is, for example, a solder bump, and has a generally spherical shape that protrudes downward from the second outer surface 30b. Examples of materials for the external terminals T2 include SAC305 and SAC405. As shown in FIG. 2 , a metal layer M made of copper or the like may be provided on the base end (the end on the second outer surface 30b side; in the illustrated example, the upper end) of each external terminal T2. The metal layer M corresponds to the "conductor provided on the second outer surface 30b."

[0054] In particular, when the semiconductor package 1 is mounted on the mounting substrate 2 by SMT (Surface Mount Technology), it is preferable that the external terminals T2 be arranged at an in-plane pitch of, for example, 0.3 mm or more, which stabilizes the formation of pads on the mounting substrate 2 and improves the accuracy of alignment during SMT.

[0055] Furthermore, by increasing the arrangement pitch of the external terminals T2, it is possible to reduce the difficulty of designing the mounting substrate 2 and thereby reduce costs. It is more preferable that the arrangement pitch of the external terminals T2 is 0.4 mm or more. In this case, it is possible to further reduce the difficulty of mounting by SMT and further reduce the design costs of the mounting substrate 2.

[0056] 1, the RF external terminal T2a is located at the outermost periphery of the semiconductor package 1 in a plan view. In the illustrated example, the multiple external terminals T2 are arranged in a rectangular lattice pattern along the first direction X and the second direction Y. The RF external terminal T2a is included in the row CL that is located outermost in the first direction X among the multiple external terminals T2. As a result, no external terminals T2 are arranged outside the RF external terminal T2a in the first direction X. However, the arrangement of the external terminals T2 can be changed as appropriate.

[0057] 1 and 2 , at least a portion of some of the multiple external terminals T2 overlaps with the RFIC 10 in a planar view. For example, at least a portion of the RF external terminal T2a overlaps with the RFIC 10 in a planar view. Furthermore, at least a portion of some of the multiple external terminals T2 overlaps with the high-frequency circuit block 12 in a planar view.

[0058] The multiple external terminals T2 may be arranged such that the RF external terminals T2a are not adjacent to each other in the in-plane direction.

[0059] As shown in FIG. 2, the semiconductor package 1 has a plurality of signal paths P formed therein for electrically connecting a plurality of pads 11 (a plurality of terminals T1) and a plurality of external terminals T2.

[0060] In this specification, a signal path P that connects the RF terminal T1a and the RF external terminal T2a and propagates an RF signal is referred to as an RF signal path Pa. A signal path P that connects a GND terminal and a GND external terminal and sets the GND potential is referred to as a GND signal path (detailed illustration omitted). A signal path P that connects a digital terminal and a digital external terminal and propagates a digital signal is referred to as a digital signal path (detailed illustration omitted). A signal path P that connects a power supply terminal and a power supply external terminal and supplies drive power to each component of the RFIC 10 is referred to as a power supply signal path (detailed illustration omitted). Note that signal paths P (GND signal path, digital signal path, and power supply signal path) other than the RF signal path Pa may be collectively referred to as a "second signal path Pb" (detailed illustration omitted in this embodiment). The second signal path Pb propagates a second signal (such as a digital signal) that is different from the RF signal.

[0061] 2 and the following description, unless otherwise specified, the RF signal path Pa will be described as a representative of each signal path P, and the description of the RF signal path Pa will be substituted for the description of the signal path P. However, the in-plane positions of the terminal T1, the external terminal T2, the filled via 32 (described later), and the rewiring 31 (described later), as well as the conductor layer C on which the rewiring 31 is provided, may differ depending on the type of signal path P.

[0062] The signal path P (RF signal path Pa) according to this embodiment includes a terminal T1 (RF terminal T1a in the RF signal path Pa), an upper pad 33, a rewiring 31, an intermediate pad 34, an external terminal T2 (RF external terminal T2a in the RF signal path Pa), and a plurality of filled vias 32. In the illustrated example, the signal path P includes three filled vias 32. The three filled vias 32 are also referred to as an upper filled via 32A, an intermediate filled via 32B, and a lower filled via 32C.

[0063] Hereinafter, the rewiring 31 included in the RF signal path Pa will be particularly referred to as the "RF rewiring 31a," and the rewiring 31 included in a signal path P (second signal path Pb) other than the RF signal path Pa will be particularly referred to as the "second rewiring 31b" (detailed illustrations omitted in this embodiment). Furthermore, the filled via 32 included in the RF signal path Pa will be particularly referred to as the "RF filled via 32a," and the filled via 32 included in a signal path P (second signal path Pb) other than the RF signal path Pa will be particularly referred to as the "second filled via 32b" (detailed illustrations omitted in this embodiment). The upper filled via 32A, the intermediate filled via 32B, and the lower filled via 32C included in the RF signal path Pa will be particularly referred to as the "RF upper filled via 32Aa," the "RF intermediate filled via 32Ba," and the "RF lower filled via 32Ca." The upper filled via 32A, the intermediate filled via 32B, and the lower filled via 32C of the second signal path Pb may be referred to as the "second upper filled via 32Ab," "second intermediate filled via 32Bb," and "second lower filled via 32Cb" (detailed illustrations omitted in this embodiment). The upper pad 33 and the intermediate pad 34 of the RF signal path Pa may be referred to as the "RF upper pad 33a" and the "RF intermediate pad 34a." The upper pad 33 and the intermediate pad 34 of the second signal path Pb may be referred to as the "second upper pad 33b" and the "second intermediate pad 34b" (detailed illustrations omitted in this embodiment).

[0064] The upper pad 33 is a pad disposed on the upper surface (first outer surface 30a) of the first conductor layer C1. The upper pad 33 corresponds to a "conductor provided on the first outer surface 30a." The upper pad 33 is electrically and mechanically connected to the lower end of the terminal T1. In the RF signal path Pa, the RF upper pad 33a is electrically and mechanically connected to the lower end of the RF terminal T1a.

[0065] The upper filled via 32A is arranged in the first dielectric layer D1 so as to penetrate the first dielectric layer D1 in the thickness direction Z. The upper end of the upper filled via 32A is electrically and mechanically connected to the upper pad 33. The upper filled via 32A may be located so as to overlap the terminal T1 in a plan view. In other words, the upper filled via 32A may be located directly below the terminal T1 via the upper pad 33. In the RF signal path Pa, the upper end of the RF upper filled via 32Aa is electrically and mechanically connected to the RF upper pad 33a. The RF upper filled via 32Aa is located so as to overlap the RF terminal T1a in a plan view, and is located directly below the RF terminal T1a via the RF upper pad 33a.

[0066] The rewiring 31 is made of a metal such as Cu. The rewiring 31 extends in an in-plane direction (first direction X in the illustrated example). The RF rewiring 31a of the RF signal path Pa is preferably an impedance-matched wiring.

[0067] The RF redistribution lines 31a are provided only on a single conductive layer C. More specifically, in the illustrated example, the RF redistribution lines 31a are provided only on the second conductive layer C2, and the RF redistribution lines 31a are not provided on the other conductive layers C1, C3, and C4.

[0068] The rewiring 31 is electrically and mechanically connected to the lower end of the upper filled via 32A. In the RF signal path Pa, the RF rewiring 31a has a first end 31e1 that overlaps the RF terminal T1a in a plan view and a second end 31e2 that overlaps the RF external terminal T2a in a plan view. In the illustrated example, the second end 31e2 is located further outward in the first direction X than the first end 31e1. The first end 31e1 of the RF rewiring 31a is electrically and mechanically connected to the lower end of the RF upper filled via 32Aa.

[0069] The intermediate filled via 32B is arranged in the second dielectric layer D2 so as to penetrate the second dielectric layer D2 in the thickness direction Z. The upper end of the intermediate filled via 32B is electrically and mechanically connected to the rewiring 31. In the RF signal path Pa, the upper end of the RF intermediate filled via 32Ba is electrically and mechanically connected to the second end 31e2 of the RF rewiring 31a.

[0070] The intermediate pad 34 is a pad disposed on the third conductive layer C3. The intermediate pad 34 is electrically and mechanically connected to the lower end of the intermediate filled via 32B. In the RF signal path Pa, the RF intermediate pad 34a is electrically and mechanically connected to the lower end of the RF intermediate filled via 32Ba.

[0071] The lower filled via 32C is arranged in the third dielectric layer D3 so as to penetrate the third dielectric layer D3 in the thickness direction Z. The upper end of the lower filled via 32C is electrically and mechanically connected to the intermediate pad 34. The lower end of the lower filled via 32C is electrically and mechanically connected to the metal layer M. As a result, the lower end of the lower filled via 32C is electrically connected to the external terminal T2 via the metal layer M. In the RF signal path Pa, the upper end of the RF lower filled via 32Ca is electrically and mechanically connected to the RF intermediate pad 34a. The lower end of the RF lower filled via 32Ca is electrically connected to the RF external terminal T2a via the metal layer M.

[0072] The lower filled via 32C may be positioned so as to overlap the intermediate filled via 32B in a plan view. As a result, the intermediate filled via 32B and the lower filled via 32C may form a stacked via portion 32S in which multiple (two in the illustrated example) filled vias 32 are stacked in the thickness direction Z. In the RF signal path Pa, the RF lower filled via 32Ca is positioned so as to overlap the RF intermediate filled via 32Ba in a plan view, and the RF intermediate filled via 32Ba and the RF lower filled via 32Ca form the stacked via portion 32S.

[0073] The first shield 41 is made of metal. The first shield 41 is preferably connected to GND (details not shown). The first shield 41 is provided on the multilayer substrate 30 (the first conductor layer C1 in the illustrated example). At least a portion of the first shield 41 overlaps the high-frequency circuit block 12 of the RFIC 10 in a plan view (see also FIG. 1 ).

[0074] The second shield 42 is formed of metal. The second shield 42 is preferably connected to GND (detailed illustration omitted). The second shield 42 is provided on the multilayer substrate 30 (the first conductor layer C1 in the illustrated example). The second shield 42 is located above (closer to) the RF rewiring 31a. That is, the distance between the second shield 42 and the first outer surface 30a in the thickness direction Z is shorter than the distance between the RF rewiring 31a and the first outer surface 30a. Note that, in the illustrated example, because the second shield 42 is located on the first outer surface 30a, the distance between the second shield 42 and the first outer surface 30a is zero. At least a portion of the second shield 42 overlaps with the RF rewiring 31a in a plan view.

[0075] 1 , the first shield 41 according to this embodiment is located in the center of the semiconductor package 1 in a plan view. The second shield 42 according to this embodiment has an annular shape in a plan view and surrounds the first shield 41 from the outside in the in-plane directions (first direction X and second direction Y). A gap G2 is formed between the first shield 41 and the second shield 42 in the in-plane directions. A plurality of terminals T1 are provided in this gap G2.

[0076] Next, the operation of the semiconductor package 1 configured as above will be described.

[0077] Conventionally, a semiconductor package (see, for example, Patent Document 1) has been known in which multiple rewirings 31 provided in a signal path from a terminal T1 to an external terminal T2 are provided on different layers. When multiple rewirings are provided on different layers, the distance between each rewiring and the mounting substrate varies. Therefore, it has been difficult to realize an isolation structure on the mounting substrate to prevent RF signals from leaking from the rewirings formed on each layer toward the mounting substrate.

[0078] To address this issue, in the semiconductor package 1 according to this embodiment, the RF rewiring 31a, which is provided in the RF signal path Pa from the RF terminal T1a to the RF external terminal T2a and extends in the in-plane direction, is provided only on a single conductor layer C (the second conductor layer C2 in the illustrated example). This makes the distance between the RF rewiring 31a and the mounting substrate 2 constant, making it easier to achieve isolation of the RF signal between the RF rewiring 31a and the mounting substrate 2.

[0079] As described above, the semiconductor package 1 according to this embodiment includes the RFIC 10 having the RF pad 11a for inputting and outputting an RF signal, the multilayer substrate 30 having the first outer surface 30a facing the RF pad 11a and the second outer surface 30b opposite to the first outer surface 30a and including three or more conductor layers C, and the RF signal path Pa for propagating an RF signal, and the RF signal path Pa includes the RF terminal T1a that electrically connects the RF pad 11a and the conductor (RF upper pad 33a) provided on the first outer surface 30a. and an RF external terminal T2a electrically connected to a conductor (metal layer M) provided on the second outer surface 30b, a first end 31e1 overlapping the RF terminal T1a in a planar view, and a second end 31e2 overlapping the RF external terminal T2a in a planar view, and includes an RF rewiring 31a provided only on a single conductor layer C, and a plurality of filled vias 32 located within the multilayer substrate 30, and the RF terminal T1a and the RF external terminal T2a are electrically connected via the RF rewiring 31a and the plurality of filled vias 32.

[0080] According to this configuration, the RF rewiring 31a extending in the in-plane direction is provided only on a single conductor layer C, which makes it easier to achieve isolation of RF signals between the RF rewiring 31a and the mounting substrate 2.

[0081] Furthermore, the height of the RF terminal T1a may be equal to or greater than the thickness of the RF rewiring 31a. This configuration can increase the distance between the high-frequency circuit block 12 of the RFIC 10 and the multilayer substrate 30. This makes it easier to achieve isolation of RF signals between the high-frequency circuit block 12 and the signal path P (for example, the rewiring 31 or the RF external terminal T2a).

[0082] Furthermore, by setting the height of the RF terminal T1a in this manner, it is possible to maintain isolation of RF signals between the high-frequency circuit block 12 and the RF external terminal T2a even in a configuration in which at least a portion of the RF external terminal T2a overlaps with the RFIC 10 in a plan view. A configuration in which at least a portion of the RF external terminal T2a overlaps with the RFIC 10 is advantageous in that it enables the semiconductor package 1 to be made smaller and at a lower cost.

[0083] The RFIC 10 also includes a high-frequency circuit block 12, and the multilayer substrate 30 is provided with a first shield 41 made of metal, with at least a portion of the first shield 41 overlapping the high-frequency circuit block 12 in a plan view. This configuration suppresses leakage of RF signals downward from the high-frequency circuit block 12 (i.e., toward the multilayer substrate 30). This makes it easier to achieve isolation between the high-frequency circuit block 12 and the signal path P.

[0084] The multilayer substrate 30 is also provided with a second shield 42 made of metal, and the distance between the second shield 42 and the first outer surface 30a in the thickness direction Z is shorter than the distance between the RF rewiring 31a and the first outer surface 30a, and at least a portion of the second shield 42 overlaps with the RF rewiring 31a in a plan view. This configuration suppresses leakage of RF signals from the RF rewiring 31a upward (i.e., toward the mold resin 20).

[0085] Furthermore, the RF signal path Pa includes a stacked via portion 32S in which a plurality of filled vias 32 are stacked. This configuration reduces the number of bends in the RF signal path Pa in a cross section along the thickness direction Z, compared to a case in which all of the filled vias 32 are shifted from one another in the in-plane direction. In the illustrated example, the RF signal path Pa has only two bends: at the first end 31e1 and the second end 31e2 of the RF rewiring 31a. Including the stacked via portion 32S in the RF signal path Pa makes it possible to suppress reflection and loss of the RF signal caused by bending of the RF signal path Pa.

[0086] Furthermore, the RF rewiring 31a may be an impedance-matched wiring, which can suppress reflection and loss of RF signals caused by the RF rewiring 31a not being impedance-matched.

[0087] Furthermore, the multilayer substrate 30 (dielectric layer D) may be formed from a coreless material. When the multilayer substrate 30 includes a core material such as glass cloth, the presence of the core material may cause variations in the physical properties (dielectric characteristics, etc.) of the multilayer substrate 30. By forming the multilayer substrate 30 from a coreless material, variations in the physical properties of the multilayer substrate 30 can be suppressed, and RF signal transmission loss caused by such variations in the physical properties can be suppressed.

[0088] Furthermore, the multilayer substrate 30 may include multiple dielectric layers D formed from the same material. Using different materials for each dielectric layer D means that the physical properties (dielectric characteristics, etc.) of each dielectric layer D are different, which may result in transmission loss of RF signals. By forming the multiple dielectric layers D included in the multilayer substrate 30 from the same material, such transmission loss can be suppressed.

[0089] Furthermore, the RF external terminals T2a are located on the outermost periphery of the semiconductor package 1 in plan view. That is, no other external terminals T2 are arranged outside the RF external terminals T2a. This allows the semiconductor package 1 to be made smaller and less expensive.

[0090] The RF module 3 according to this embodiment includes a plurality of the above-described semiconductor packages 1, and a mounting substrate 2 having a plurality of antennas 2 a and on which the plurality of semiconductor packages 1 are mounted. This makes it possible to provide an RF module 3 that can easily achieve isolation of RF signals.

[0091] The technical scope of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

[0092] 4 is a cross-sectional view of a semiconductor package 1A according to a first modification of the present invention. The configuration of the semiconductor package 1A according to this modification is basically the same as the configuration of the semiconductor package 1 according to the above embodiment. Therefore, the same components are given the same reference numerals, and their description will be omitted, and only the differences will be described.

[0093] The semiconductor package 1A according to this modification has a smaller number of external terminals T2 than the semiconductor package 1 according to the above embodiment. The semiconductor package 1A according to this modification also includes two third shields 43A and 43B.

[0094] The third shields 43A and 43B are formed of metal. The third shields 43A and 43B are preferably connected to GND (detailed illustration omitted). Of the two third shields 43A and 43B, the third shield 43A is provided on the fourth conductor layer C4 of the multilayer substrate 30. The other of the two third shields 43A and 43B, the third shield 43B, is provided on the third conductor layer C3 of the multilayer substrate 30. The third shields 43A and 43B are located below the RF rewiring 31a (on the second outer surface 30b side). That is, in the thickness direction Z, the distance between the third shield 43A and the second outer surface 30b is shorter than the distance between the RF rewiring 31a and the second outer surface 30b. Similarly, in the thickness direction Z, the distance between the third shield 43B and the second outer surface 30b is shorter than the distance between the RF rewiring 31a and the second outer surface 30b. In the illustrated example, since the third shield 43A is located on the second outer surface 30b, the distance between the third shield 43A and the second outer surface 30b is zero. At least a portion of the third shields 43A and 43B overlaps with the RF rewiring 31a in a plan view.

[0095] Such third shields 43A and 43B suppress leakage of RF signals downward from the RF rewiring 31a (i.e., toward the mounting substrate 2).

[0096] <Second Modification> Fig. 5 is a plan view of a semiconductor package 1B according to a second modification of the present invention. Fig. 6 is a cross-sectional view of the semiconductor package 1B according to this modification. Note that the configuration of the semiconductor package 1B according to this modification is basically the same as the configuration of the semiconductor package 1 according to the first embodiment. Therefore, the same components are denoted by the same reference numerals, and their description will be omitted, and only the differences will be described.

[0097] Specifically, in the semiconductor package 1B according to this modification, the number and arrangement of the terminals T1 are different from those of the first embodiment, as shown in Fig. 5. Also, as shown in Fig. 5 and Fig. 6, the dimension (diameter) of each terminal T1 in the in-plane direction is smaller than that of the terminal T1 according to the first embodiment.

[0098] 5 and 6 , the RF signal path Pa and the second signal path Pb are located on the same cross section (a cross section parallel to the first direction X and the thickness direction Z). The second signal path Pb in this modification will be described in detail below. The shape of the RF signal path Pa in this modification is the same as the shape of the RF signal path Pa in the first embodiment, except that the first end 31e1 of the RF rewiring 31a, the RF upper filled via 32Aa, and the RF upper pad 33a are located further outward in the first direction X than those in the first embodiment. Therefore, a description of the RF signal path Pa will be omitted.

[0099] The second signal path Pb in this modified example includes a second terminal T1b, a second upper pad 33b, a second rewiring 31b, a second intermediate pad 34b, a second external terminal T2b, and multiple (three in the illustrated example) second filled vias 32b (upper filled via 32A, intermediate filled via 32B, and lower filled via 32C).

[0100] The second upper pad 33b is electrically and mechanically connected to the lower end of the second terminal T1b.

[0101] The upper end of the second upper filled via 32Ab is electrically and mechanically connected to the second upper pad 33b. The second upper filled via 32Ab is located so as to overlap the second terminal T1b in a plan view. In other words, the second upper filled via 32Ab is located directly below the second terminal T1b via the second upper pad 33b.

[0102] The second rewiring 31b has a third end 31e3 overlapping the second terminal T1b in a plan view and a fourth end 31e4 overlapping the second external terminal T2b in a plan view. In the illustrated example, the fourth end 31e4 is located more inward in the first direction X than the third end 31e3. The third end 31e3 of the second rewiring 31b is electrically and mechanically connected to the lower end of the second upper filled via 32Ab. Note that the second signal path Pb may include multiple second rewirings 31b formed on different conductor layers C (details not shown).

[0103] The upper end of the second intermediate filled via 32Bb is electrically and mechanically connected to the fourth end 31e4 of the second rewiring 31b.

[0104] The second intermediate pad 34b is electrically and mechanically connected to the lower end of the second intermediate filled via 32Bb.

[0105] The upper end of the second lower filled via 32Cb is electrically and mechanically connected to the second intermediate pad 34b, and the lower end of the second lower filled via 32Cb is electrically connected to the second external terminal T2b via the metal layer M.

[0106] The second lower filled via 32Cb is located at a position overlapping the second intermediate filled via 32Bb in a plan view, whereby the second intermediate filled via 32Bb and the second lower filled via 32Cb form a stacked via portion 32S.

[0107] 5 and 6, at least a portion of the second external terminal T2b overlaps, in plan view, with the high-frequency circuit block 12. As shown in Fig. 6, at least a portion of the second rewiring 31b overlaps, in plan view, with the high-frequency circuit block 12.

[0108] As in the above embodiment, if the height of the RF terminal T1a is equal to or greater than the thickness of the RF rewiring 31a, it is possible to maintain isolation of RF signals between the high-frequency circuit block 12 and the second external terminal T2b even in a configuration in which at least a portion of the second external terminal T2b (GND external terminal, digital external terminal, and power supply external terminal) overlaps in plan view with the high-frequency circuit block 12. A configuration in which at least a portion of the second external terminal T2b overlaps with the high-frequency circuit block 12 has the effect of realizing miniaturization and cost reduction of the semiconductor package 1.

[0109] Similarly, if the height of the RF terminal T1a is equal to or greater than the thickness of the RF rewiring 31a, even if at least a portion of the second rewiring 31b overlaps with the high-frequency circuit block 12 in a planar view, isolation of RF signals between the high-frequency circuit block 12 and the second rewiring 31b can be maintained.

[0110] <Other Modifications> The configuration of the signal path P can be modified as appropriate. For example, the rewiring 31 may be disposed on any of the conductor layers C1, C3, and C4 other than the second conductor layer C2. For example, the rewiring 31 may be disposed on the first conductor layer C1, and the rewiring 31 (RF rewiring 31a, second rewiring 31b) may contact the terminal T1 (RF terminal T1a, second terminal T1b), thereby electrically connecting the rewiring 31 to the terminal T1. In this case, the rewiring 31 corresponds to the "conductor disposed on the first outer surface 30a." Alternatively, the rewiring 31 may be disposed on the fourth conductor layer C4, and the rewiring 31 may contact the external terminal T2 (RF external terminal T2a, second external terminal T2b), thereby electrically connecting the rewiring 31 to the external terminal T2. In this case, the rewiring 31 corresponds to the "conductor disposed on the second outer surface 30b." The signal path P does not need to include the stacked via portion 32S (e.g., when the dielectric layer D is two layers). If the height of the RF terminal T1a is equal to or greater than the thickness of the RF rewiring 31a, at least a portion of the RF rewiring 31a may be located at a position overlapping the high-frequency circuit block 12 in a planar view (e.g., position A shown in FIG. 4 ). Even if at least a portion of the RF rewiring 31a overlaps the high-frequency circuit block 12 in a planar view, RF signal isolation between the high-frequency circuit block 12 and the RF rewiring 31a can be maintained by having the height of the RF terminal T1a equal to or greater than the thickness of the RF rewiring 31a. If the height of the RF terminal T1a is equal to or greater than the thickness of the RF rewiring 31a, at least a portion of the RF external terminal T2a may be located at a position overlapping the high-frequency circuit block 12 in a planar view. 5, six external terminals T2 overlap with the high-frequency circuit block 12 in plan view, and three of them (the external terminals T2 in the upper left column, the upper right column, and the middle left column on the paper) are second external terminals T2b. Here, at least one of the remaining three external terminals T2 (the external terminals T2 in the middle right column, the lower left column, and the lower right column on the paper) may be an RF external terminal T2a.Since the height of the RF terminal T1a is equal to or greater than the thickness of the RF rewiring 31a, isolation of RF signals between the high-frequency circuit block 12 and the RF external terminal T2a can be maintained even if at least a portion of the RF external terminal T2a overlaps with the high-frequency circuit block 12 in a planar view.

[0111] Furthermore, the RF external terminal T2a does not have to overlap with the high-frequency circuit block 12 in a plan view, and the second external terminal T2b does not have to overlap with the high-frequency circuit block 12 in a plan view.

[0112] Furthermore, the conductive layer C on which the shields 41 to 43 are provided can be changed as appropriate.

[0113] Even if the RF rewiring 31a is provided on multiple conductor layers C, the isolation of the RF signal between the high-frequency circuit block 12 and the RF signal path Pa can be improved by making the height of the RF terminal T1a equal to or greater than the thickness of the RF rewiring 31a (for example, equal to or greater than 30 μm).

[0114] In addition, it is possible to replace the components in the above-described embodiments with well-known components as appropriate, and the above-described embodiments and variations may be combined as appropriate, without departing from the spirit of the present invention.

[0115] REFERENCE SIGNS LIST 1, 1A...Semiconductor package 2...Mounting substrate 2a...Antenna 3...RF module 10...RFIC 11a...RF pad 11b...Second pad 12...High frequency circuit block 30...Multilayer substrate 30a...First outer surface 30b...Second outer surface 31a...RF rewiring 31b...Second rewiring 32a...RF filled via (filled via) 32b...Second filled via (filled via) 32S...Stacked via section 41...First shield 42...Second shield 43A, 43B...Third shield C...Conductive layer D...Dielectric layer Pa...RF signal path Pb...Second signal path T1a...RF terminal T1b...Second terminal T2a...RF external terminal T2b...Second external terminal

Claims

1. an RFIC having RF pads for inputting and outputting RF signals; a multilayer substrate having a first outer surface facing the RF pad and a second outer surface opposite the first outer surface, the multilayer substrate including three or more conductive layers; an RF signal path that propagates the RF signal; The RF signal path includes: an RF terminal that electrically connects the RF pad and the conductor provided on the first outer surface; an RF external terminal electrically connected to the conductor provided on the second outer surface; an RF rewiring having a first end portion overlapping the RF terminal in a plan view and a second end portion overlapping the RF external terminal in a plan view, the RF rewiring being provided only on the single conductive layer; a plurality of filled vias located within the multilayer substrate; the RF terminal and the RF external terminal are electrically connected via the RF rewiring and the plurality of filled vias. Semiconductor package.

2. The height of the RF terminal is equal to or greater than the thickness of the RF redistribution line. The semiconductor package of claim 1 .

3. the RFIC has a high-frequency circuit block, At least a portion of the RF rewiring overlaps with the high-frequency circuit block in a plan view. The semiconductor package according to claim 2 .

4. a second signal path that propagates a second signal different from the RF signal; the RFIC has a high-frequency circuit block and a second pad for inputting and outputting the second signal; The second signal path is a second terminal electrically connecting the second pad and a conductor provided on the first outer surface; a second external terminal electrically connected to the conductor provided on the second outer surface and different from the RF external terminal; a second redistribution line provided in the conductive layer and different from the RF redistribution line; a plurality of second filled vias different from the plurality of filled vias, the second filled vias being located within the multilayer substrate; the second terminal and the second external terminal are electrically connected via the second rewiring and the plurality of second filled vias; At least a portion of the second rewiring overlaps with the high-frequency circuit block in a plan view.

4. The semiconductor package according to claim 2.

5. the RFIC has a high-frequency circuit block, At least a portion of the RF external terminal overlaps with the high-frequency circuit block in a plan view.

4. The semiconductor package according to claim 2.

6. a second signal path that propagates a second signal different from the RF signal; the RFIC has a high-frequency circuit block and a second pad for inputting and outputting the second signal; The second signal path is a second terminal electrically connecting the second pad and a conductor provided on the first outer surface; a second external terminal electrically connected to the conductor provided on the second outer surface and different from the RF external terminal; a second redistribution line provided in the conductive layer and different from the RF redistribution line; a plurality of second filled vias different from the plurality of filled vias, the second filled vias being located within the multilayer substrate; the second terminal and the second external terminal are electrically connected via the second rewiring and the plurality of second filled vias; At least a portion of the second external terminal overlaps with the high-frequency circuit block in a plan view.

4. The semiconductor package according to claim 2.

7. the RFIC has a high-frequency circuit block, the multilayer substrate is provided with a first shield made of metal; At least a portion of the first shield overlaps with the high-frequency circuit block in a plan view. The semiconductor package according to claim 1 .

8. the multilayer substrate is provided with a second shield made of metal; a distance between the second shield and the first outer surface in a thickness direction of the multilayer substrate is shorter than a distance between the RF redistribution line and the first outer surface; At least a portion of the second shield overlaps with the RF rewiring in a plan view. The semiconductor package according to claim 1 .

9. the multilayer substrate is provided with a third shield made of metal; a distance between the third shield and the second outer surface in a thickness direction of the multilayer substrate is shorter than a distance between the RF redistribution line and the second outer surface; At least a portion of the third shield overlaps with the RF rewiring in a plan view. The semiconductor package according to claim 1 .

10. The RF signal path includes a stacked via portion in which a plurality of the filled vias are stacked. The semiconductor package according to claim 1 .

11. the RF rewiring is impedance-matched wiring; The semiconductor package according to claim 1 .

12. The multilayer substrate is formed of a coreless material. The semiconductor package according to claim 1 .

13. The multilayer substrate includes a plurality of dielectric layers formed of the same material. The semiconductor package according to claim 1 .

14. the RF external terminals are located on the outermost periphery of the semiconductor package in a plan view; The semiconductor package according to claim 1 .

15. a plurality of semiconductor packages according to any one of claims 1 to 3; a mounting substrate having a plurality of antennas and on which the plurality of semiconductor packages are mounted; RF module.