Semiconductor device

Abstract

The present invention provides a semiconductor device in which deterioration in pressure resistance performance is suppressed. This semiconductor device comprises: an active part (101); a terminal region (102) surrounding the active part in a plan view; a first conductivity type drift layer (3) provided over the active part and the terminal region; a second conductivity type base region (5) provided on the upper surface side of the drift layer in the active part; and a second conductivity type well region (12) provided on the upper surface side of the drift layer in the terminal region and surrounding the base region (5) in a plan view. The well region (12) has a recess (12a) on the lower side, and the dimension of the recess (12a) in the depth direction is 1 / 3 to 2 / 3 of the dimension of the well region (12) in the depth direction.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device, and more particularly to a high-voltage semiconductor device.

[0002] High-voltage semiconductor devices such as power MOSFETs and power IGBTs have a breakdown voltage support structure in a termination region surrounding an active region to ensure the breakdown voltage. There are various types of breakdown voltage support structures. For example, as described in Patent Documents 1 and 2, there are a field plate structure, a guard ring structure, a RESURF structure, and the like.

[0003] Patent Document 3 describes a diode in which the retreat length of the anode electrode in the region where the p+ conductivity type semiconductor layer and the anode electrode are not in contact is made longer than the diffusion length of holes in the n- conductivity type semiconductor layer.

[0004] Japanese Patent Application Publication No. 2003-197898 Japanese Patent Application Publication No. 2009-38356 Japanese Patent No. 3444081

[0005] In the termination region, the electric field tends to concentrate at the outer edge of the p-type region, which may result in a decrease in the breakdown voltage of the semiconductor device.

[0006] In view of the above-described problems, an object of the present disclosure is to provide a semiconductor device in which degradation of breakdown voltage performance is suppressed.

[0007] In order to achieve the above object, one aspect of the present disclosure is a semiconductor device including: (a) an active section; (b) a termination region surrounding the active section in a planar view; (c) a drift layer of a first conductivity type provided across the active section and the termination region; (d) a first region of a second conductivity type provided on an upper surface side of the drift layer in the active section; and (e) a second region of the second conductivity type provided on an upper surface side of the drift layer in the termination region and surrounding the first region in a planar view; (f) the second region has a recess on its lower side; and (g) the depth dimension of the recess is equal to or greater than one-third and equal to or less than two-thirds of the depth dimension of the second region.

[0008] The semiconductor device may further include a transistor provided in the active portion and having the first region as a base region, and a gate wiring electrode surrounding the active portion in a planar view and electrically connected to a gate electrode of the transistor, wherein the second region is a well region and has an upper surface facing the gate wiring electrode, with the active portion side being the inside and the termination region side being the outside, and the recess may be located outside the inside end of the gate wiring electrode.

[0009] The well region and the recess may be provided in a ring shape along the gate wiring electrode in a plan view.

[0010] The recess may be located outside the outer edge of the gate line electrode.

[0011] Furthermore, when the dimension from the inner end to the outer end of the gate wiring electrode along the outward direction is defined as W1, the dimension from the position of the inner end of the gate wiring electrode to the position of the recess is defined as W2, and the dimension in the depth direction of the well region is defined as d1, and the constant C is a value not less than 0.75 and not more than 0.85, the relationship W2≧W1+C×d1 may be satisfied.

[0012] A field plate may be provided in the region outside the recess of the well region.

[0013] The recess may be located inside the outer edge of the gate line electrode.

[0014] The well region may also have a plurality of recesses on the lower side.

[0015] The well region may have, as recesses, a first recess located outside the outer edge of the gate wiring electrode and a second recess located inside the outer edge of the gate wiring electrode.

[0016] The dimension of the second recess in the depth direction may be greater than the dimension of the first recess in the depth direction.

[0017] The semiconductor device may also have a second conductivity type breakdown voltage structure provided on the upper surface side of the drift layer and positioned outside the well region.

[0018] The breakdown voltage structure may also be a guard ring.

[0019] The well region may overlap the entire gate wiring electrode in plan view.

[0020] The transistor may also have a main electrode in contact with the top surface of the main region, and the well region may be electrically connected to the main electrode.

[0021] The gate electrode of the transistor may be a trench gate type.

[0022] The diode may also include a diode having the first region as a main region, the second region as an ineffective region, and an inner edge of the second region contacting an outer edge of the first region.

[0023] The semiconductor device may further include a third region of the first conductivity type that is the main region and is provided on the lower surface side of the drift layer.

[0024] Furthermore, when the active region side is the inside and the termination region side is the outside, the outer end of the third region may be located inside the outer end of the drift layer, and the recess may be located inside the outer end of the third region.

[0025] Furthermore, when the active region side is the inside and the termination region side is the outside, the outer end of the third region may be located inside the outer end of the drift layer, and the recess may be located outside the outer end of the third region.

[0026] Furthermore, when the lateral dimension along the outward direction from the position of the outer end of the third region to the position of the recess is W4, the depth dimension of the second region is d1, and the constant C is a value greater than or equal to 0.75 and less than or equal to 0.85, the relationship C × d1 < W4 < 20 μm may be satisfied.

[0027] The semiconductor device may further include a fourth region of the second conductivity type provided on the upper surface side of the third region, the outer end of the fourth region being located more inward than the outer end of the second region, and the recess being located more inward than the outer end of the fourth region.

[0028] The second region may also have a plurality of recesses on the lower side.

[0029] The dimension of the second region in the depth direction may be set to be the same as the dimension of the first region in the depth direction.

[0030] The recess may be provided in a ring shape along the second region in a plan view.

[0031] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0032] According to the present disclosure, it is possible to provide a semiconductor device in which degradation of breakdown voltage performance is suppressed.

[0033] 6 is an explanatory plan view showing the planar configuration of a semiconductor device according to a first embodiment and the position of a gate wiring electrode. FIG. 7 is a schematic cross-sectional view showing a longitudinal cross-sectional configuration when viewed in cross section along the A-A cutting line in FIG. 1. FIG. 8 is a partially enlarged view showing a part of the active element shown in FIG. 2. FIG. 9 is a schematic cross-sectional view showing a part of the longitudinal cross-sectional configuration of a semiconductor device according to a second embodiment. FIG. 10 is a schematic cross-sectional view showing a part of the longitudinal cross-sectional configuration of a semiconductor device according to a third embodiment. FIG. 11 is an explanatory plan view showing the planar configuration of a semiconductor device according to a fourth embodiment. FIG. 12 is a schematic cross-sectional view showing a longitudinal cross-sectional configuration when viewed in cross section along the A-A cutting line in FIG. 1. FIG. 13 is a schematic cross-sectional view showing a longitudinal cross-sectional configuration of a semiconductor device according to a seventh embodiment. FIG. 14 is a schematic cross-sectional view showing a longitudinal cross-sectional configuration of a semiconductor device according to an eighth embodiment. FIG. 15 is a schematic cross-sectional view showing a longitudinal cross-sectional configuration of a semiconductor device according to a comparative example. FIG. 16 is a view showing a simulation result of electric field intensity.

[0034] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present disclosure, and the technical idea of ​​the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0035] In this specification, the source region of a metal-oxide semiconductor field-effect transistor (MOSFET) is "one main region (first main region)" that can be selected as the emitter region of an insulated gate bipolar transistor (IGBT). In addition, in a thyristor such as a MOS-controlled static induction thyristor (SI thyristor), "one main region" can be selected as the cathode region. The drain region of a MOSFET is "the other main region (second main region)" of the semiconductor device that can be selected as the collector region in an IGBT or as the anode region in a thyristor. In this specification, the term "main region" simply refers to either the first main region or the second main region, as appropriate from the common technical knowledge of a person skilled in the art.

[0036] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are inverted and read as such. Furthermore, "top surface" may be read as "front surface" and "bottom surface" may be read as "rear surface."

[0037] In the following description, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example. However, the conductivity types may be selected in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. Furthermore, the + or - attached to n or p means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without the + or - attached. However, even if the semiconductor regions have the same n and n attached, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0038] First Embodiment <Structure of Semiconductor Device> In this embodiment, a semiconductor device (semiconductor chip) 100 according to the first embodiment will be described as an example, where the semiconductor device is an IGBT. As shown in FIG. 1 , a semiconductor device (semiconductor chip) 100 according to the first embodiment includes an active portion 101 having, for example, a rectangular planar shape, and a termination region 102 surrounding the active portion 101 in a planar view. FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1 , illustrating the cross-sectional configuration of the active portion 101 and the termination region 102. FIG. 3 is an enlarged view of a portion of an active element provided in the active portion 101 shown in FIG. 2 . As shown in FIGS. 2 and 3 , the active portion 101 of the semiconductor device 100 includes a trench-gate IGBT as an active element. Hereinafter, the active portion 101 and the termination region 102 will be described first. Note that, in the horizontal direction, the active portion 101 side is the inner side, and the termination region 102 is the outer side.

[0039] <Active section> As shown in FIG. 3, the first conductivity type (n － A base region 5 of the second conductivity type (p-type) is disposed on the drift layer 3 of the second conductivity type (p-type). ＋ The emitter region 6 has an impurity concentration of 1×10 １９ cm －３ That's it, 1 x 10 ２０ cm －３ or less. An n-type accumulation layer 4 having a higher impurity concentration than the drift layer 3 is provided below the base region 5. A trench 7 is provided from the upper surface of the emitter region 6 through the base region 5 and the accumulation layer 4. The emitter region 6, the base region 5, and the accumulation layer 4 contact the side of the trench 7, and a portion of the drift layer 3 also contacts the trench 7. The trench 7 extends from the emitter region 6 through the base region 5 and the accumulation layer 4 to reach the drift layer 3. The trench 7 extends in a direction perpendicular to the plane of the drawing, and although not shown, multiple trenches 7 are arranged in a stripe pattern in a plan view. As shown in FIG. 2, at least one dummy trench 7a is provided in the outer region of the active portion 101. In the example shown in FIG. 2, two dummy trenches 7a are provided in the outer region of the active portion 101. The dummy trenches 7a do not function as active elements.

[0040] Although not shown, the upper portion of the base region 5 shown in FIG. 2 is provided with a second conductivity type (p ＋ In the cross section passing through the contact regions, contact regions are provided which are semiconductor regions of a type (type 1). The contact regions are provided alternately with the emitter regions 6 along the direction in which the trenches 7 extend in parallel (the direction perpendicular to the paper surface of FIG. 3). That is, in a cross section passing through the contact regions, the emitter regions 6 in FIG. 3 become the contact regions.

[0041] A gate insulating film 8a is provided on the bottom and side surfaces of the trench 7. A gate electrode 9 is buried inside the trench 7 with the gate insulating film 8a interposed therebetween. The gate insulating film 8a and the gate electrode 9 form a trench gate type insulated gate electrode structure (8a, 9). The gate electrode 9 can be made of a polysilicon layer (doped polysilicon layer) doped with a high concentration of p-type or n-type impurities, or a high melting point metal such as titanium (Ti), tungsten (W), or nickel (Ni). In this embodiment, an example in which the gate electrode 9 is made of a polysilicon layer will be described. The gate insulating film 8a can be made of silicon dioxide (SiO ２ ) film, silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si ３ N ４ ) film, aluminum oxide (Al ２ O ３ ) film, magnesium oxide (MgO) film, yttrium oxide (Y ２ O ３ ) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO ２ ) film, tantalum oxide (Ta ２ O ５ ) film, bismuth oxide (Bi ２ O ３ ) membranes or composite membranes in which a plurality of these membranes are laminated can be used.

[0042] An interlayer insulating film 8b is disposed on the gate electrode 9. An emitter surface electrode 10 is provided so as to cover the interlayer insulating film 8b. The emitter surface electrode 10 is a main electrode that contacts the main region. The emitter surface electrode 10 is physically in contact with the emitter region 6 exposed from an opening provided in the interlayer insulating film 8b and a contact region (not shown). A silicon oxide film (BPSG) doped with boron (B) and phosphorus (P) is used as the interlayer insulating film 8b. A silicon oxide film (PSG) doped with phosphorus (P), or a non-doped SiO film called "NSG" that does not contain phosphorus (P) or boron (B) is also used as the interlayer insulating film 8b. ２ film, boron (B)-doped silicon dioxide film (BSG), Si ３ N ４ The emitter surface electrode 10 may be made of, for example, nickel silicide (NiSi ｘ The gate insulating film 8a and the interlayer insulating film 8b may be collectively referred to as the insulating film 8.

[0043] The lower surface of the drift layer 3 is ＋ A field stop layer (FS layer) 2 of a type is disposed on the bottom surface of the FS layer 2. ＋ A molded collector region 1 is disposed on the substrate. A collector backside electrode 11 is disposed on the underside of the collector region 1. As the collector backside electrode 11, for example, a single layer film made of gold (Au) or a metal film laminated in this order of Ti, nickel (Ni), and Au can be used.

[0044] During operation of the IGBT according to the first embodiment, for example, the emitter front surface electrode 10 is held at ground potential and a positive voltage is applied to the collector back surface electrode 11. When a positive voltage equal to or greater than a threshold is applied to the gate electrode 9, an inversion layer (channel) is formed on the side surface of the trench 7 in the base region 5, turning the IGBT on. In the on state, a current flows from the collector back surface electrode 11 to the emitter front surface electrode 10 via the collector region 1, FS layer 2, drift layer 3, accumulation layer 4, inversion layer in the base region 5, and emitter region 6. When the voltage applied to the gate electrode 9 is less than the threshold, no inversion layer is formed in the base region 5, and therefore no current flows from the collector back surface electrode 11 to the emitter front surface electrode 10.

[0045] <Termination Region> As shown in FIG. 2, the drift layer 3 is provided across the active section 101 and the termination region 102. The boundary between the active section 101 and the termination region 102 is the inner end of the gate wiring electrode 16. On the upper surface side of the drift layer 3, a well region 12, a guard ring (field limiting ring) 13 which is a voltage-resistant structure, and a stopper region 14 are provided. The well region 12, the guard ring 13, and the stopper region 14 are all of the second conductivity type (p ＋ The stopper region 14 is a floating diffusion region. The guard rings 13 are separated from each other by the drift layer 3, and their bottom surfaces contact the drift layer 3. The stopper region 14 is located outside the guard ring 13 and surrounds the guard ring 13 in a circular shape in a plan view. The guard ring 13 is located outside the well region 12 and surrounds the well region 12 in a circular shape in a plan view. The outer end of the well region 12 is located in the termination region 102. The guard ring 13 is a floating diffusion region. A plurality of guard rings 13 may be provided, for example, as shown in the figure, and the guard rings 13 are separated from each other by the drift layer 3. The top surfaces of the drift layer 3, well region 12, guard ring 13, and stopper region 14 are covered with an insulating film 8. A field plate 15a is connected to the top surface of the guard ring 13 via an opening 81 provided in the insulating film 8. The field plate 15a and the opening 81 are provided in a circular shape along the guard ring 13 in a plan view. The well region 12 and the guard ring 13 each have an impurity concentration of 1×10 １５ cm －３ That's it, 1 x 10 １９ cm－３ The impurity concentrations of the well region 12 and the guard ring 13 may be the same or different. The dimensions in the depth direction of the well region 12 and the guard ring 13 are the same, but may be different. Also, as shown in FIG. 1, a gate wiring electrode 16 is provided in the termination region 102. The well region 12 and the gate wiring electrode 16 will be described in detail below.

[0046] <Well Region and Gate Wiring Electrode> As shown in FIG. 1 , the gate wiring electrode 16 surrounds the active portion 101 in a circular shape in a plan view. The gate wiring electrode 16 is electrically connected to the gate electrode 9 of the IGBT shown in FIG. 3 and supplies a potential to the gate electrode 9. As shown in FIG. 2 , the gate wiring electrode 16 is provided on the upper surface side of the well region 12. The gate wiring electrode 16 can be made of, for example, a polysilicon layer (doped polysilicon layer) doped with a high impurity concentration of p-type or n-type impurities, or a high-melting-point metal such as titanium (Ti), tungsten (W), or nickel (Ni). In this embodiment, an example in which the gate wiring electrode 16 is made of a polysilicon layer will be described.

[0047] The well region 12 is an ineffective region having an emitter potential. The upper surface of the well region 12 faces the gate wiring electrode 16 via the insulating film 8. The insulating film 8 interposed between the well region 12 and the gate wiring electrode 16 can be made of the same material as the gate insulating film 8a and may be deposited together with the gate insulating film 8a. The well region 12 is provided in a ring shape along the gate electrode 9 in a plan view and overlaps the entire gate wiring electrode 16 in a plan view. By providing the well region 12 in this manner, the influence of the potential of the gate wiring electrode 16 on the semiconductor layer can be suppressed. For example, if the well region 12 is not provided in the semiconductor region facing the gate wiring electrode 16, electric field concentration may occur at the end of the active portion 101. Therefore, it is preferable to provide the well region 12 in the semiconductor region facing the gate wiring electrode 16. The upper surface of the gate wiring electrode 16 is covered with the insulating film 8, and a gate wiring 18 is provided on the upper surface of the insulating film 8 in a ring shape along the gate wiring electrode 16 in a plan view. The gate wiring electrode 16 is connected to the gate wiring 18 through an opening 82 provided in the insulating film 8. The opening 82 may also be provided in a ring shape along the gate wiring electrode 16. The gate wiring 18 is connected to an electrode pad (gate pad) 18A (FIG. 1), and a potential is supplied to the gate wiring electrode 16 through the electrode pad 18A and the gate wiring 18. The gate wiring 18 is made of, for example, nickel silicide (NiSi ｘ ) film, titanium nitride (TiN) film, titanium (Ti) film, aluminum (Al) film, aluminum-silicon (Al-Si) film, or aluminum-copper (Al-Cu) film.

[0048] The well region 12 has an inner portion electrically connected to the emitter surface electrode 10 and has an emitter potential. The inner end of the well region 12 is electrically connected to the emitter surface electrode 10 on each of the four sides of the rectangular semiconductor chip. For example, as shown in FIG. 2, the inner end of the well region 12 extends into the active portion 101 and is electrically connected to the emitter surface electrode 10 via a contact region 17 and an opening 83 provided in the insulating film 8. The contact region 17 is provided on the upper surface side of the inner end of the well region 12 and is made of a second conductivity type (p ＋type) region, and the impurity concentration is 1×10 １９ cm －３ That's it, 1 x 10 ２１ cm －３ The depth of the well region 12 is approximately 1.2 to 2.5 times the depth of the dummy trench 7a. d1 is the depth of the well region 12 at a position where a recess 12a (described later) is not provided. For example, d1 is the maximum depth of the well region 12.

[0049] The well region 12 has a recess 12a on its underside (lower surface). Providing the recess 12a in the well region 12 suppresses the concentration of an electric field at the outer edge of the well region 12. The recess 12a is located in the termination region 102. The recess 12a is located outside the inner edge of the gate wiring electrode 16 in a direction perpendicular to the depth direction (lateral direction). Although not shown, the recess 12a is provided in a ring shape along the well region 12 in a planar view. Providing the ring-shaped recess 12a suppresses the concentration of an electric field at the outer edge of the well region 12 on all four sides of the semiconductor chip. In this embodiment, the recess 12a is located outside the outer edge of the gate wiring electrode 16. It is desirable that the depth of the recess 12a is not too shallow. If the depth dimension of the recess 12a is d2, for example, d2 is set to a dimension of approximately 1 / 3 to 2 / 3 of the depth d1 of the well region 12. Furthermore, the dimension of the well region 12 from the recess 12a to the outer edge in the lateral direction is approximately two to four times the depth d1 of the well region 12. A field plate 15b is provided in the region of the well region 12 outside the recess 12a. The field plate 15b is connected to the well region 12 via an opening 84 provided in the insulating film 8. The field plate 15b and the opening 84 are provided in a ring shape along the well region 12 in a plan view. The field plates 15a and 15b are made of, for example, nickel silicide (NiSi ｘ ) film, titanium nitride (TiN) film, titanium (Ti) film, aluminum (Al) film, aluminum-silicon (Al-Si) film, or aluminum-copper (Al-Cu) film.

[0050] The well region 12 is formed by ion implanting an impurity element into the semiconductor layer and performing a heat treatment after the ion implantation. The impurity element is ion implanted into the region inside and outside the position where the recess 12a is formed, followed by a heat treatment. The heat treatment causes the impurity element to diffuse in both the depth direction and the lateral direction within the semiconductor layer, connecting the region inside the recess 12a with the region outside the recess 12a in the lateral direction, forming the recess 12a. In the lateral direction (e.g., the direction toward the outside), if W1 is the lateral dimension from the inner end to the outer end of the gate wiring electrode 16, and W2 is the lateral dimension from the position where the inner end of the gate wiring electrode 16 is located to the position where the recess 12a is located, then the relationship W2 ≥ W1 + C × d1 is satisfied. The constant C is a value approximately equal to or greater than 0.75 and equal to or less than 0.85, and "C × d1" represents the distance the implanted impurity diffuses laterally due to the heat treatment. Note that by ion-implanting impurities into a region that includes at least the range W1 shown in the figure, the well region 12 can be formed so as to reliably overlap the entire gate wiring electrode 16. In consideration of the above, by providing the recess 12a at a position that satisfies W2≧W1+C×d1, the well region 12 can be provided so as to reliably overlap the entire gate wiring electrode 16, and electric field concentration at the outer end of the well region 12 can be suppressed.

[0051] <<Major Effects of the First Embodiment>> The electric field tends to concentrate at the outer edge of the p-type region (e.g., well region) in the termination region 102. Furthermore, because the lateral dimension of the well region is determined in accordance with the lateral dimension of the gate wiring electrode 16, if a current filament occurs at the outer edge of the well region, it is difficult for the current to travel to the emitter surface electrode 10. More specifically, when the gate wiring electrode 16 is provided to surround the active portion 101 in a planar view, a well region is provided whose upper surface faces the gate wiring electrode 16 to suppress the influence of the potential of the gate wiring electrode 16 on the semiconductor layer. The lateral dimension of the well region is set to be at least larger than the lateral dimension of the gate wiring electrode 16. Therefore, the dimension from the outer edge of the well region to the inner edge electrically connected to the emitter surface electrode 10 is larger than in the case where the gate wiring electrode 16 is not provided, and the distance that holes travel to the emitter surface electrode 10 is longer. The longer the moving distance, the more difficult it becomes for the holes to flow to the emitter surface electrode 10. In this way, when the moving distance is long, the hole extraction characteristics are different from when the moving distance is short.

[0052] In the semiconductor device 100 according to the first embodiment, the recess 12a is provided below the well region 12, thereby preventing the electric field from concentrating at the outer edge of the well region 12 and shifting the position of the electric field concentration from the outer edge of the well region 12 to the inside of the active portion 101. This shifts the position of the electric field concentration from the termination region 102 to the inside of the active portion 101. This prevents a decrease in the breakdown voltage performance of the semiconductor device 100. For example, it improves the breakdown voltage performance of the semiconductor device 100. It is desirable that the current filament generated during electric field concentration and avalanche operation occurs in the active portion 101 of the active portion 101 and the termination region 102. When an electric field concentrates inside the active portion 101, even if a localized filament current is generated in a certain trench, a rise in the temperature of that trench can easily cause hopping, in which the current filament moves to another trench 7. In this way, when an electric field concentrates in the active portion 101, the current filament does not remain in one place, making breakdown less likely to occur.

[0053] Furthermore, in the semiconductor device 100 according to the first embodiment, the recess 12a is located laterally outward from the inner end of the gate wiring electrode 16. This ensures that a portion of the well region 12 extending inward from the inner end of the gate wiring electrode 16 can be provided. This ensures that the well region 12 covers the region from the inner end of the gate wiring electrode 16 to the outermost trench of the active portion 101, and also ensures that the well region 12 covers the region up to the connection position (opening 83) with the emitter surface electrode 10. This prevents a decrease in the breakdown voltage performance of the outer end of the active portion 101, and ensures that the well region 12 is electrically connected to the emitter surface electrode 10.

[0054] Furthermore, in the semiconductor device 100 according to the first embodiment, the recess 12 a is located laterally outside the outer end of the gate wiring electrode 16. Since the recess 12 a is located near the outer end of the well region 12 where the electric field is likely to concentrate, the electric field can be efficiently prevented from concentrating at the outer end of the well region 12.

[0055] Furthermore, in the semiconductor device 100 according to the first embodiment, the dimension W2 from the inner end of the gate wiring electrode 16 to the position of the recess 12a satisfies the relationship W2≧W1+C×d1. Therefore, the well region 12 can be provided so as to overlap the entire gate wiring electrode 16 without fail, and the electric field can be prevented from concentrating on the outer end of the well region 12.

[0056] In the semiconductor device 100 according to the first embodiment, the depth dimension d2 of the recess 12a is equal to or greater than ⅓ and equal to or less than ⅔ of the depth dimension d1 of the well region 12. By providing the recess 12a at a depth that is not too shallow, it is possible to efficiently prevent the electric field from concentrating at the outer end of the well region 12.

[0057] Furthermore, in the semiconductor device 100 according to the first embodiment, a field plate 15b is provided in a region outside the recess 12a of the well region 12. By providing the field plate 15b, it is possible to improve the breakdown voltage performance of the termination region 102 compared to a case where the field plate 15b is not provided.

[0058] Second Embodiment In the semiconductor device 100 according to the first embodiment, the recess 12a is located outside the outer edge of the gate wiring electrode 16 as shown in Fig. 2, but in the semiconductor device 100 according to the second embodiment, the recess 12a is located inside the outer edge of the gate wiring electrode 16 as shown in Fig. 4. In addition, in this embodiment, when the lateral dimension from the position of the inner edge of the gate wiring electrode 16 to the position of the outer edge of the well region 12 is defined as W3, the relationship W3 ≥ W1 + C × d1 is satisfied. Because the recess 12a is located inside the outer edge of the gate wiring electrode 16, W3 can be made smaller than in the first embodiment.

[0059] <<Major Effects of Second Embodiment>> The semiconductor device 100 according to the second embodiment also has the same effects as the semiconductor device 100 according to the first embodiment described above.

[0060] Furthermore, in the semiconductor device 100 according to the second embodiment, the recess 12a is located more inward than the outer end of the gate wiring electrode 16. Therefore, the recess 12a is closer to the active portion 101 than in the first embodiment. When the recess 12a is closer to the active portion 101, even if an electric field is concentrated near the recess 12a and a current filament is generated, the current is more likely to move to the active portion 101. Furthermore, when the recess 12a is closer to the active portion 101, holes are more likely to be extracted from the contact region 17.

[0061] Furthermore, in the semiconductor device 100 according to the second embodiment, the recess 12a is located inside the outer edge of the gate wiring electrode 16, so the dimension W3 can be made smaller than in the first embodiment. This reduces the lateral dimension of the well region 12, resulting in area savings. Furthermore, if the lateral dimension of the well region 12 can be reduced, the number of guard rings 13 can be increased, as shown in FIG. 4, and the breakdown voltage performance can be improved.

[0062] 2 and 4, the well region 12 has a single recess 12a on its lower side, but in the semiconductor device 100 according to the third embodiment shown in Fig. 5, the well region 12 has a plurality of recesses 12a on its lower side. One recess 12a is located outside the other recesses 12a.

[0063] In the example shown in FIG. 5 , the well region 12 according to the third embodiment has two recesses 12 a. One of the two recesses 12 a is located outside the other in the lateral direction. More specifically, one of the two recesses 12 a is located outside the outer edge of the gate wiring electrode 16, and the other is located inside the outer edge of the gate wiring electrode 16. In order to distinguish between the recess 12 a located outside the outer edge of the gate wiring electrode 16 and the recess 12 a located inside the outer edge of the gate wiring electrode 16, the recess located outside the outer edge of the gate wiring electrode 16 is referred to as a first recess 12 a1, and the recess located inside the outer edge of the gate wiring electrode 16 is referred to as a second recess 12 a2. When there is no need to distinguish between the first recess 12 a1 and the second recess 12 a2, they are simply referred to as recesses 12 a.

[0064] If the dimension of the second recess 12a2 in the depth direction is d3, then, for example, d3 is set to a dimension that is approximately ⅓ to ⅔ of the depth d1 of the well region 12. In this embodiment, d3 has the same dimension as d2, which is the dimension of the first recess 12a1 in the depth direction.

[0065] <<Main Effects of the Third Embodiment>> The semiconductor device 100 according to the third embodiment has the same effects as the semiconductor device 100 according to the first embodiment and the semiconductor device 100 according to the second embodiment.

[0066] The recess 12a may be located at any position outside the inner end of the gate wiring electrode 16 and inside the outer end of the well region 12. The number of recesses 12a is not limited to two, and may be three or more.

[0067] <<Modification of the Third Embodiment>> A modification of the third embodiment will be described below. In this modification of the third embodiment, the depth dimension d3 of the second recess 12a2 is set to be larger than the depth dimension d2 of the first recess 12a1 (d3 > d2). By forming the second recess 12a2, which is located on the inner side, deeper than the first recess 12a1, which is located on the outer side, the electric field is more likely to concentrate in the second recess 12a2, which is located on the inner side, than in the first recess 12a1, which is located on the outer side. When the electric field concentrates in the second recess 12a2, the current filament tends to move current to the active portion 101.

[0068] In the first to third embodiments described above, the position of the recess 12a in the lateral direction may be determined based on the deepest portion (center) of the recess 12a. For example, the deepest portion (center) of the recess 12a may be determined to be located outside the inner edge of the gate wiring electrode 16. Alternatively, for example, the deepest portion of the recess 12a may be determined to be located inside or outside the outer edge of the gate wiring electrode 16. Alternatively, for example, the lateral dimension from the position of the inner edge of the gate wiring electrode 16 to the position of the deepest portion of the recess 12a may be defined as W2.

[0069] In the first to third embodiments, the depth dimensions d2 and d3 of the recess 12a may be the depth dimensions at the deepest position (center) of the recess 12a.

[0070] In the first to third embodiments described above, in the heat treatment for forming the well region 12, the ends of the region inside and outside the position where the recess 12a is formed are connected to each other in a curvature state. The cross-sectional shape of the formed recess 12a may be, for example, a V-shape as shown in the drawing.

[0071] [Fourth Embodiment] In this specification, in a diode, "one main region" can be selected as a cathode region, and "the other main region (second main region)" can be selected as an anode region. When simply referring to a "main region" in this specification, it means either the first main region or the second main region, whichever is appropriate from the common technical knowledge of a person skilled in the art.

[0072] <Structure of Semiconductor Device> In this embodiment, a case where the semiconductor device is a diode will be described as an example. The diode is used, for example, as a free wheel diode. Examples of semiconductor devices include diodes with pn junctions, JBS diodes, MPS diodes, and Schottky diodes. As shown in FIG. 6 , a semiconductor device (semiconductor chip) 200 according to the fourth embodiment includes an active portion 291 having, for example, a rectangular planar shape, and a termination region 292 surrounding the active portion 291 in a planar view. In this embodiment, the boundary between the active portion 291 and the termination region 292 is the inner edge of an interlayer insulating film 208 (described later).

[0073] 7 is a cross-sectional view taken along line AA in FIG. 6, showing the cross-sectional configuration of the active section 291 and the termination region 292. In the horizontal direction, the active section 291 side is the inside and the termination region 292 is the outside. － The drift layer 203 , which is a semiconductor region of the MOSFET type, is provided across the active section 291 and the termination region 292 .

[0074] The upper surface of the drift layer 203 is provided with a second conductivity type (p ＋ anode region 205, which is a semiconductor region of the second conductivity type (p ＋ an ineffective region 212 which is a semiconductor region of the second conductivity type (p ＋ The anode region 205 is an example of a first region, and the ineffective region 212 is an example of a second region. The lower surfaces of the anode region 205, the ineffective region 212, and the guard ring 213 are in contact with the drift layer 203. The impurity concentration of the anode region 205 is 1.0×10 １３ cm －３ That's it, 1.0 x 10 １９ cm －３ The impurity concentration of the ineffective region 212 is about 1.0×10 １３ cm －３ That's it, 1.0 x 10 １９ cm －３ The impurity concentration of the guard ring 213 is about 1.0×10 １３ cm －３That's it, 1.0 x 10 １９ cm －３ A plurality of guard rings 213 may be provided.

[0075] The anode region 205 is provided in the active portion 291, and the ineffective region 212 and the guard ring 213 are provided in the termination region 292. The anode region 205 and the ineffective region 212 contact the drift layer 203 in the thickness direction, thereby forming a pn junction. An anode surface electrode 210 that is in physical contact with the anode region 205 is provided on the upper surface of the anode region 205. The anode region 205 is, for example, a contact region. In order to reduce contact resistance with the anode surface electrode 210, a high-concentration p-type region may be provided on the surface of the anode region 205. The anode surface electrode 210 is, for example, made of nickel silicide (NiSi ｘ ) film, titanium nitride (TiN) film, titanium (Ti) film, aluminum (Al) film, aluminum-silicon (Al-Si) film, or aluminum-copper (Al-Cu) film.

[0076] The ineffective region 212 is provided to improve the breakdown voltage performance of the semiconductor device 200. The ineffective region 212 surrounds the anode region 205 in a ring shape in a plan view. The inner edge of the ineffective region 212 contacts the outer edge of the anode region 205. For example, the ineffective region 212 may be formed integrally with the anode region 205. Furthermore, the dimension of the ineffective region 212 in the depth direction may be the same as the dimension of the anode region 205 in the depth direction. Charges in the ineffective region 212 are extracted to the anode surface electrode 210 via the anode region 205, for example.

[0077] The ineffective region 212 has a recess 212a on its lower side (lower surface). Providing the recess 212a in the ineffective region 212 suppresses the concentration of the electric field at the outer edge of the ineffective region 212. The recess 212a is located in the termination region 292. As shown in FIG. 6 , the recess 212a is annularly formed in the termination region 292 in a plan view. More specifically, the recess 212a is annularly formed along the ineffective region 212 provided in the termination region 292. Note that the recess 212a need only be annularly formed in a plan view, and is not limited to the shape shown in FIG. 6 . Providing the recess 212a annularly suppresses the concentration of the electric field at the outer edge of the ineffective region 212 on all four sides of the semiconductor chip. It is desirable that the depth of the recess 212a is not too shallow. If the depth of the recess 212a is too shallow, the effect of the recess 212a on the electric field will be too small, and the effect of changing the position where the electric field is concentrated will be too small. As shown in Figure 7, the depth dimension of the invalid region 212 at a position where the recess 212a is not provided is defined as d1, and the depth dimension of the recess 212a is defined as d2. More specifically, the depth dimension of the recess 212a at its deepest position (center) is defined as d2. Then, for example, d2 is set to a dimension greater than or equal to 1 / 3 and less than 2 / 3 of the depth d1 of the invalid region 212 (d1 / 3 ≤ d2 ≤ 2d1 / 3). As a result, the depth dimension d2 of the invalid region 212 at the deepest position of the recess 212a is greater than 1 / 3 and less than 2 / 3 of the depth d1.

[0078] In addition, in the horizontal direction, the recess 212a may be provided at a position closer to the outer edge of the invalid area 212. In addition, in the horizontal direction, the dimension from the recess 212a to the outer edge of the invalid area 212 may be approximately two to four times the depth d1 of the invalid area 212.

[0079] The invalid region 212 is formed by ion implanting an impurity element into the semiconductor layer and performing a heat treatment after the ion implantation. The impurity element is ion implanted into the region inside and outside the position where the recess 212a is to be formed, followed by a heat treatment. The heat treatment diffuses the impurity element in both the depth direction and the lateral direction within the semiconductor layer, connecting the region inside the recess 212a and the region outside the recess 212a in the lateral direction, thereby forming the recess 212a. At this time, the ends of the inner and outer regions are connected to each other with a curvature. The cross-sectional shape of the formed recess 212a may be, for example, V-shaped as shown in the figure. Furthermore, it is required that the diffusion variation during the ion implantation and heat treatment is small.

[0080] An interlayer insulating film 208 is provided on the upper surface of the ineffective region 212, and is in physical contact with the ineffective region 212. Although not shown, the interlayer insulating film 208 is provided so as to surround the active portion 291 in a plan view. The outer edge of the interlayer insulating film 208 extends to the chip edge of the semiconductor device 200, and is in contact with the upper surface of the guard ring 213 and the drift layer 203 in the termination region 292. A silicon oxide film (BPSG) doped with boron (B) and phosphorus (P) is used as the interlayer insulating film 208. A silicon oxide film (PSG) doped with phosphorus (P), or a non-doped SiO film called "NSG" that does not contain phosphorus (P) or boron (B) is also used as the interlayer insulating film 208. ２ film, boron (B)-doped silicon dioxide film (BSG), Si ３ N ４ The interlayer insulating film 208 may be a film or a laminated film of these. Note that the interlayer insulating film 208 may be simply called an insulating film.

[0081] A field plate 215b is provided in the region outside the recess 212a of the ineffective region 212. The field plate 215b is connected to the ineffective region 212 via an opening 284 provided in the interlayer insulating film 208. The configuration of the field plate 215b is similar to the configuration of the field plate 15b described in the first embodiment, and therefore a detailed description thereof will be omitted.

[0082] The guard ring 213 is located outside the ineffective region 212 and surrounds the ineffective region 212 in a ring shape in plan view. The guard ring 213 is a floating diffusion region and is separated from the ineffective region 212 by the drift layer 203. The configuration of the guard ring 213 is similar to that of the guard ring 13 described in the first embodiment, so a detailed description thereof will be omitted. A field plate 215a is connected to the upper surface of the guard ring 213 via an opening 281 provided in the interlayer insulating film 208. The configuration of the field plate 215a is similar to that of the field plate 15a described in the first embodiment, so a detailed description thereof will be omitted.

[0083] The lower surface of the drift layer 203 is provided with a first conductivity type (n ＋ The cathode region 201 is an example of a third region. The impurity concentration of the cathode region 201 is 1.0×10 １４ cm －３ That's it, 1.0 x 10 １８ cm －３ The cathode region 201 is provided over the entire lower surface of the drift layer 203. The upper surface of the cathode region 201 is in contact with the drift layer 203. A cathode back surface electrode 211 is disposed on the lower surface of the cathode region 201. The configuration of the cathode back surface electrode 211 is similar to that of the collector back surface electrode 11, and therefore a detailed description thereof will be omitted.

[0084] <<Major Effects of the Fourth Embodiment>> Below, we will describe the major effects of the semiconductor device 200 according to the fourth embodiment. Before that, we will provide an overview of the present technology. Vertical high-voltage semiconductor devices, such as diodes, have a breakdown voltage structure around the periphery of a semiconductor substrate to ensure their breakdown voltage. Under reverse bias, carriers below the diode's breakdown voltage structure concentrate at the anode edge. This increases the electric field strength at the anode edge, making avalanche (reverse recovery current) more likely to occur. To avoid this phenomenon, a HiRC structure (ineffective region) is described in Patent Document 3. In the HiRC structure, a p-type semiconductor region without a contact region is provided between the edge and the active region. This allows the HiRC structure to capture carriers below the breakdown voltage structure region and alleviate the electric field. This suppresses avalanche at the anode edge.

[0085] In this way, by providing a HiRC structure with a certain length in the lateral direction, the region that receives carriers can be expanded. However, even if the HiRC structure can reduce the electric field by extracting a certain amount of carriers, localized electric field concentration may occur at the periphery of the HiRC structure when avalanche occurs. For example, in the invalid region 212X of the comparative example shown in Figure 12, localized electric field concentration may occur at the position of the star X1 when avalanche occurs.

[0086] Furthermore, since the HiRC structure does not contribute to electron conduction, it is desirable to make it short to save space. However, shortening the HiRC structure narrows the region that extracts carriers, making it easier for the electric field to concentrate. This makes it difficult to shorten the HiRC structure.

[0087] In contrast, in the semiconductor device 200 according to the first embodiment, as shown in FIG. 7 , a recess 212a is provided below the ineffective region 212, which can prevent the electric field from concentrating locally at the outer edge of the ineffective region 212 during avalanche, thereby improving the reverse recovery resistance. This can prevent the breakdown voltage performance of the semiconductor device 200 from decreasing. For example, the breakdown voltage performance of the semiconductor device 200 can be improved. Furthermore, the position at which the electric field concentrates can be shifted from the outer edge of the ineffective region 212 toward the active portion 291. This allows the avalanche current to be generated in the active portion 291, which has a large area and therefore a relatively high resistance to the avalanche current.

[0088] Furthermore, the regions inside and outside the deepest position of the recess 212a in the ineffective region 212 are connected to each other with a curvature, so that equipotential lines extend toward the guard ring 213, and electric field concentration at the outer edge of the ineffective region 212 is alleviated.

[0089] Furthermore, in the semiconductor device 200 according to the first embodiment, by providing the recess 212a below the ineffective region 212, localized temperature concentration is less likely to occur, and the reverse recovery resistance can be improved. This makes it possible to shorten the lateral length of the ineffective region 212 while maintaining the same withstand voltage. This allows the width (edge ​​length) of the termination region 292 to be shortened, thereby reducing the chip size.

[0090] Furthermore, in the semiconductor device 200 according to the fourth embodiment, the recess 212a is provided near the outer edge of the ineffective region 212 where the electric field is likely to concentrate, thereby efficiently preventing the electric field from concentrating at the outer edge of the ineffective region 212. More specifically, even when the cathode region 201 is provided over the entire lower surface of the drift layer 203, the electric field can be efficiently prevented from concentrating at the outer edge of the ineffective region 212. The presence of the recess 212a reduces the area of ​​the ineffective region 212, increasing the resistance and raising the resistance value, thereby narrowing the current path flowing to the ineffective region 212.

[0091] Furthermore, in the semiconductor device 200 according to the fourth embodiment, the depth dimension d2 of the recess 212a is equal to or greater than one-third and equal to or less than two-thirds of the depth dimension d1 of the ineffective region 212. By providing the recess 212a at a depth that is not too shallow, the effect of the recess 212a on the electric field is not too small, and therefore, the electric field can be efficiently prevented from concentrating at the outer edge of the ineffective region 212.

[0092] Furthermore, in the semiconductor device 200 according to the fourth embodiment, a field plate 215b is provided in a region outside the recess 212a of the ineffective region 212. By providing the field plate 215b, it is possible to improve the breakdown voltage performance of the termination region 292 compared to a case where the field plate 215b is not provided.

[0093] Fifth Embodiment In the semiconductor device 200 according to the fourth embodiment, the cathode region 201 is provided over the entire lower surface of the drift layer 203 as shown in FIG. 7 , but the present technology is not limited to this. In the semiconductor device 200 according to the fifth embodiment, the cathode region 201 is provided only in the central portion of the semiconductor device 200 in a plan view. As shown in FIG. 8 , the cathode region 201 does not extend to the chip edge of the semiconductor device 200. More specifically, the outer edge of the cathode region 201 is located outward from the outer edge of the anode region 205 and inward from the outer edge of the drift layer 203. Furthermore, in the semiconductor device 200 according to the fifth embodiment, the recess 212 a is located inward from the outer edge of the cathode region 201 as shown in FIG. 8 . More specifically, the deepest portion of the recess 212 a is located inward from the outer edge of the cathode region 201.

[0094] The cathode region 201 is the main source of carriers (electrons). Therefore, many carriers enter the diode through the cathode region 201. In this embodiment, the cathode region 201 is not provided to the outer edge of the drift layer 203 in order to reduce carriers filling the outer periphery of the chip. In this manner, the configuration of the cathode region 201 in this embodiment allows carriers to be collected toward the active section 291. Furthermore, the outer edge of the ineffective region 212 may be located, for example, outside the outer edge of the cathode region 201, i.e., in a region where carriers are reduced.

[0095] In addition, in this embodiment, the recess 212a is provided inside the outer end of the cathode region 201. By bringing the recess 212a closer to the active portion 291, carriers collected by the cathode region 201 toward the active portion 291 can more easily move toward the active portion 291. This makes it easier to extract carriers from the anode region 205.

[0096] <<Major Effects of the Fifth Embodiment>> The semiconductor device 200 according to the fifth embodiment has the same effects as the semiconductor device 200 according to the fourth embodiment. Furthermore, in the semiconductor device 200 according to the fifth embodiment, the recess 212a is provided inside the outer edge of the cathode region 201, so that carriers collected by the cathode region 201 toward the active portion 291 can more easily move toward the active portion 291. In this way, by providing a singular point of electric field concentration and extracting current from it, a carrier path can be created as close to the active portion as possible. When an avalanche current occurs in the active portion 291, the current concentration point tends to move within the active portion 291 as the lattice temperature increases, making breakdown less likely.

[0097] Sixth Embodiment In the semiconductor device 200 according to the fifth embodiment shown in FIG. 8 , the recess 212 a is provided inside the outer edge of the cathode region 201, but the present technology is not limited to this. In the semiconductor device 200 according to the sixth embodiment, the recess 212 a is provided outside the outer edge of the cathode region 201 as shown in FIG. 9 . More specifically, the deepest portion of the recess 212 a is located outside the outer edge of the cathode region 201. Note that a description of the same configuration as that of the semiconductor device 200 according to the fifth embodiment will be omitted.

[0098] The outer edge of the cathode region 201 is located more inward than the outer edge of the drift layer 203. The outer edge of the cathode region 201 may also be located more outward than the outer edge of the anode region 205, for example. The outer edge of the ineffective region 212 is located more outward than the outer edge of the cathode region 201. The distance of the recess 212a from the outer edge of the cathode region 201 will be described in detail below.

[0099] When the horizontal dimension from the outer edge of the cathode region 201 to the recess 212a is W4, the relationship C×d1<W4<20 ​​μm is satisfied. The constant C is a value of approximately 0.75 to 0.85, and "C×d1" represents the distance that the ion-implanted impurities diffuse laterally due to heat treatment. By ion-implanting impurities into at least the area of ​​the drift layer 203 that overlaps the cathode region 201, the ineffective region 212 can be reliably formed up to the outer edge of the cathode region 201 in a planar view. Furthermore, by providing the recess 12a at a position that satisfies C×d1<W4<20 ​​μm, carriers supplied from the cathode region 201 can be received by the ineffective region 212 while suppressing electric field concentration at the outer edge of the ineffective region 212. The dimension W4 may be the dimension from the position of the outer edge of the cathode region 201 to the deepest position (center) of the recess 212a.

[0100] <<Major Effects of Sixth Embodiment>> The semiconductor device 200 according to the sixth embodiment also has the same effects as the semiconductor device 200 according to the fourth embodiment described above.

[0101] Furthermore, in the semiconductor device 200 according to the sixth embodiment, the dimension W4 from the position of the outer edge of the cathode region 201 to the position of the recess 212a satisfies the relationship C×d1<W4<20 ​​μm. This allows the ineffective region 212 to be reliably formed up to the position of the outer edge of the cathode region 201, and allows the ineffective region 212 to receive carriers supplied from the cathode region 201 while preventing the electric field from concentrating at the outer edge of the ineffective region 212.

[0102] 10 , a semiconductor device 200 according to a seventh embodiment includes a p-type region 202 that is a semiconductor region of a second conductivity type (p-type) and is provided in a layer shape on the upper surface side of a cathode region 201. The recess 212 a is located inside the outer edge of the p-type region 202.

[0103] The p-type region 202 is provided to suppress surge voltages and has the function of reducing current in the event of a short circuit. The p-type region 202 may be in a floating state or may be in contact with the cathode back surface electrode 211. A drift layer 203 is interposed between the p-type region 202 and the ineffective region 212. The outer edge of the p-type region 202 is located outward from the outer edge of the anode region 205, and is located inward from the outer edge of the ineffective region 212 and the outer edge of the cathode region 201. The p-type region 202 is an example of a fourth region. The impurity concentration of the p-type region 202 is 1.0×10 １５ cm －３ That's it, 1.0 x 10 １８ cm －３ It is about the following.

[0104] It has been found that when a semiconductor region is provided below the drift layer 203 and the boundary of the semiconductor region overlaps the ineffective region 212 in a planar view, the electric field concentrates at the position overlapping the boundary of the ineffective region 212. For example, when a p-type region 202 is provided on the underside of the drift layer 203, it has been found that a large amount of the electric field concentrates at the portion of the ineffective region 212 that overlaps the outer edge of the p-type region 202 in a planar view. More specifically, it has been found that the electric field concentrates at the position indicated by the star X2 in FIG. 12. Therefore, as shown in FIG. 10, the position of the recess 212a is adjusted so that the recess 212a is located inside the outer edge of the p-type region 202 and outside the outer edge of the anode region 205. More specifically, the deepest portion (center) of the recess 212a is located inside the outer edge of the p-type region 202 and outside the outer edge of the anode region 205. This allows at least a portion of the current concentrating in the portion of the ineffective region 212 directly above the outer edge of the p-type region 202 to be dispersed to other portions. More specifically, a portion of the current can be dispersed to a position closer to the active portion 291 than the outer edge of the p-type region 202.

[0105] <<Major Effects of the Seventh Embodiment>> The semiconductor device 200 according to the seventh embodiment has the same effects as the semiconductor device 200 according to the fourth embodiment. Furthermore, in the semiconductor device 200 according to the seventh embodiment, the recess 212a is provided inside the portion of the ineffective region 212 directly above the outer edge of the p-type region 202 where current tends to concentrate. This disperses the current concentration toward the active portion 291, making it easier for the current to move toward the active portion 291. In this way, by providing a singular point of electric field concentration and extracting current from it, a carrier path can be created as close to the active portion as possible.

[0106] Eighth Embodiment In a semiconductor device 200 according to an eighth embodiment, an ineffective region 212 has a plurality of recesses 212a on its lower side. One recess 12a is positioned more outward than another recess 12a. The relationship in size between the depth dimension of one recess 12a and the depth dimension of another recess 12a may be the same as the relationship in size between the dimension d2 and the dimension d3 described in the third embodiment and its modified example.

[0107] For example, the invalid area 212 may have a plurality of recesses 212a as shown in Fig. 11. Furthermore, for example, the invalid area 212 may have both the recesses 212a shown in Fig. 8 and the recesses 212a shown in Fig. 9.

[0108] <<Major Effects of Eighth Embodiment>> The semiconductor device 200 according to the eighth embodiment also has the same effects as the semiconductor device 200 according to the fourth embodiment described above.

[0109] [Simulation Results] The following describes the results of a simulation of the electric field strength performed on the IGBT well region 12. In the conventional example, the electric field tends to concentrate at the ends of the guard ring and the well region, more specifically, at the locations where there is curvature in the semiconductor region.

[0110] The simulation was performed only on the well region 12 and the guard ring 13, excluding the active region 101. FIGS. 13 and 14 show the electric field intensity in the well region 12, the guard ring 13, and the drift layer 3. The well region 12 has a recess 12a on its lower side. The recess 12a shown in FIG. 13 is referred to as a recess 12X, and the recess 12a shown in FIG. 14 is referred to as a recess 12Y, and may be distinguished from each other. The difference between FIGS. 13 and 14 is the depth dimension of the recess 12a. More specifically, the depth dimension of the recess 12Y shown in FIG. 14 is set deeper than the depth dimension of the recess 12X shown in FIG. 13.

[0111] The simulation results shown in FIG. 13 reveal that a current filament is generated at the outer edge (e.g., a curvature) of the well region 12. In the simulation results shown in FIG. 13, the depth dimension of the recess 12X is shallower than in the simulation results shown in FIG. 14. It is believed that the recess in FIG. 13 is too shallow, resulting in a distribution of electric field strength as if the well region 12 did not have a recess. In contrast, the simulation results shown in FIG. 14 reveal that the electric field at the outer edge of the well region 12 is relaxed, resulting in localized current generation near the bottom (lower side) of the well region 12. In the simulation results shown in FIG. 14, it is believed that the recess 12Y is sufficiently deep, thereby relaxing the electric field at the outer edge of the well region 12. Thus, if the depth of the recess 12a is too shallow, the recess 12a's effect on the electric field becomes too small, resulting in too little effect on changing the position where the electric field is concentrated.

[0112] Furthermore, if the recess 12a is too deep, the well region 12 may be divided into two, resulting in a state where the recess 12a is not present. When the well region 12 is divided into two, an equipotential line extends between the divided well regions 12. This may result in an electric field concentrating at the outer end of the inner well region 12 among the divided well regions.

[0113] As a result of further investigation, it was found that in order to suppress electric field concentration at the outer edge, it is desirable to set the depth dimensions d2 and d3 of the recess 12a according to the first to third embodiments to approximately one-third to two-thirds of the depth dimension d1 of the well region 12. By setting the depth of the recess 12a to an appropriate value, the position of the well region 12 where the recess 12a is provided functions as if it were an edge, and can attract an electric field.

[0114] Furthermore, when the active region 101 is miniaturized to improve loss, the size relationship between the area of ​​the active region 101 and the area of ​​the termination region 102 is easily affected by manufacturing variations. This can result in a decrease in the breakdown voltage of the breakdown voltage holding structure provided in the termination region 102. In response to this, by providing the recess 12a below the well region 12, the breakdown voltage performance of the well region 12 can be improved without being affected by manufacturing variations. Therefore, it is possible to suppress variations in the avalanche breakdown voltage due to manufacturing variations.

[0115] The effect of the depth dimension of the recess 12a on the electric field is the same in the case of a diode. Therefore, it is desirable that the depth dimension d2 of the recess 12a in the fourth to eighth embodiments described above is set to a dimension of about 1 / 3 to 2 / 3 of the depth d1 of the ineffective region 212. This provides the same effect as in the case of an IGBT.

[0116] [Other Embodiments] As described above, the first to eighth embodiments of the present disclosure have been described, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0117] For example, although an IGBT has been exemplified as the semiconductor device according to the first to third embodiments, the present invention can also be applied to a reverse conducting IGBT (RC-IGBT) or a reverse blocking insulated gate bipolar transistor (RB-IGBT). ＋ Instead of the collector region 1 of the n type ＋ The present invention can also be applied to a MOSFET having a drain region of the same type.

[0118] In the first to eighth embodiments, silicon (Si) is used as the material of the semiconductor substrate, but the semiconductor material is not limited thereto and may be a wide bandgap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN). Furthermore, while the transistors according to the first to third embodiments are trench gate type, they are not limited thereto and may be planar type. Furthermore, the breakdown voltage structures according to the first to eighth embodiments do not need to be guard ring structures and may be JTE structures, RESURF structures, VLD structures, or the like.

[0119] Furthermore, the configurations disclosed in the first to eighth embodiments can be combined as appropriate within the scope of not causing any contradictions. As such, the present disclosure naturally includes various embodiments not described here. Therefore, the technical scope of the present disclosure is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description.

[0120] The planar shape of the gate wiring electrode 16 may be any known shape and is not limited to the shape shown in Fig. 1. The dimension W4 may satisfy the relationship C x d1 ≤ W4 ≤ 20 µm.

[0121] 3, 203 Drift layer 5 Base region (first region) 6 Emitter region 7 Trench 8, 208 Insulating film 9 Gate electrode 10 Emitter front surface electrode 11 Collector back surface electrode 12 Well region (second region) 12a, 212a Recess 12a1 First recess 12a2 Second recess 13, 213 Guard ring 15a, 15b, 215a, 215b Field plate 16 Gate wiring electrode 18 Gate wiring 100, 200 Semiconductor device 101, 291 Active portion 102, 292 Termination region d1, d2, d3, W1, W2, W4 Dimensions 201 Cathode region (third region) 202 P-type region (fourth region) 205 Anode region (first region) 208 Interlayer insulating film (insulating film) 210 Anode surface electrode 211 Cathode back surface electrode 212 Ineffective region (second region) C Constant

Claims

1. an active portion; a termination region surrounding the active portion in a plan view; a drift layer of a first conductivity type provided across the active portion and the termination region; a first region of a second conductivity type provided on an upper surface side of the drift layer in the active portion; a second region of a second conductivity type provided on an upper surface side of the drift layer in the termination region and surrounding the first region in a plan view; Equipped with the second region has a recess on the underside; a depth dimension of the recessed portion is 1 / 3 or more and 2 / 3 or less of a depth dimension of the second region; Semiconductor device.

2. a transistor provided in the active portion and having the first region as a base region; a gate wiring electrode surrounding the active portion in a plan view and electrically connected to a gate electrode of the transistor; Furthermore, the second region is a well region, the upper part of which faces the gate wiring electrode; the bottom # of the well region is deeper than the bottom # of the first region; When the active portion side is defined as an inner side and the termination region side is defined as an outer side, the recess is located outside an inner end of the gate wiring electrode. The semiconductor device according to claim 1 .

3. the well region and the recess are provided in a ring shape along the gate wiring electrode in a plan view; The semiconductor device according to claim 2 .

4. the recess is located outside the outer end of the gate line electrode; 4. The semiconductor device according to claim 2 or 3.

5. When the dimension from the inner end to the outer end of the gate wiring electrode along the outward direction is W1, the dimension from the position of the inner end of the gate wiring electrode to the position of the recess is W2, and the dimension in the depth direction of the well region is d1, and constant C is a value of 0.75 or more and 0.85 or less, the relationship W2≧W1+C×d1 is satisfied. The semiconductor device according to claim 4 .

6. a field plate electrically connected to the second region is provided in a region of the second region outside the recess; The semiconductor device according to claim 1 .

7. the recess is located inside the outer edge of the gate line electrode; 4. The semiconductor device according to claim 2 or 3.

8. The well region has a plurality of the recesses on the underside.

4. The semiconductor device according to claim 2 or 3.

9. The well region has, as the recess, a first recess located outside an outer end of the gate wiring electrode and a second recess located inside the outer end of the gate wiring electrode. The semiconductor device according to claim 8 .

10. The dimension of the second recess in the depth direction is greater than the dimension of the first recess in the depth direction. The semiconductor device according to claim 9 .

11. a second conductivity type breakdown voltage structure provided on the upper surface side of the drift layer and positioned outside the well region; 4. The semiconductor device according to claim 2 or 3.

12. the pressure-resistant structure is a guard ring; The semiconductor device according to claim 11.

13. the well region overlaps the entire gate wiring electrode in a plan view; 4. The semiconductor device according to claim 2 or 3.

14. a main electrode in contact with an upper surface of a main region of the transistor; the well region is electrically connected to the main electrode; 4. The semiconductor device according to claim 2 or 3.

15. The gate electrode of the transistor is a trench gate type.

4. The semiconductor device according to claim 2 or 3.

16. a diode having the first region as a main region; the second region is an invalid region, and an inner edge of the second region is in contact with an outer edge of the first region; The second region is formed integrally and continuously with the first region, and the dimension of the second region in the depth direction is set to be the same dimension as the dimension of the first region in the depth direction. The semiconductor device according to claim 1 .

17. a third region of the first conductivity type that is a main region and is provided on the lower surface side of the drift layer; The semiconductor device according to claim 16.

18. when the active region side is defined as an inner side and the termination region side is defined as an outer side, an outer end of the third region is located more inner than an outer end of the drift layer, the recess is located inside the outer end of the third region.

18. The semiconductor device according to claim 17.

19. when the active region side is defined as an inner side and the termination region side is defined as an outer side, an outer end of the third region is located more inner than an outer end of the drift layer, the recess is located outside the outer end of the third region.

18. The semiconductor device according to claim 17.

20. When a lateral dimension from a position of an outer end of the third region to a position of the recess along an outward direction is defined as W4, a depth dimension of the second region is defined as d1, and a constant C is a value of 0.75 or more and 0.85 or less, the relationship C × d1 < W4 < 20 μm is satisfied.

20. The semiconductor device according to claim 19.

21. a fourth region of the second conductivity type provided on an upper surface side of the third region, an outer end of the fourth region is located more inward than an outer end of the second region; the recess is located inside the outer end of the fourth region.

19. The semiconductor device according to claim 17 or 18.

22. The second region has a plurality of the recesses on a lower side thereof.

21. The semiconductor device according to claim 16.

23. The recess is provided in an annular shape along the second region in a plan view.

21. The semiconductor device according to claim 16.

24. (delete)