Imaging device

Abstract

The present invention makes it possible to drive a pulse of a capacitor provided in a pixel while suppressing a decrease in a frame rate.　This imaging device comprises: a photoelectric conversion unit; a transfer transistor connected to the photoelectric conversion unit; a reset transistor having one terminal connected to the transfer transistor and the other terminal connected to a power supply voltage; a capacitor having one terminal connected to the photoelectric conversion unit and the other terminal connected to a control voltage; a voltage control line for transmitting the control voltage; and a control line for transmitting a transfer signal to the transfer transistor. The voltage control line is orthogonal to the control line. A signal line for transmitting the signal read from the photoelectric conversion unit may be further provided, and the voltage control line may be arranged in parallel with the signal line.

Description

Imaging device

[0001] The present technology relates to an imaging device, and more particularly, to an imaging device in which a capacitor is provided in each pixel.

[0002] In order to expand the dynamic range of imaging, a capacitor for storing charge overflowing from a photodiode is sometimes provided in each pixel. For example, an imaging device has been proposed that includes a first switch that connects a first light receiving element to a first charge storage unit and a second switch that connects a second light receiving element to a second charge storage unit (see, for example, Patent Document 1).

[0003] International Publication No. 2019 / 82614

[0004] However, in the above-mentioned conventional technology, when the capacitor electrodes are pulse-driven to reduce the dark current of the capacitor, the load capacitance seen from the voltage control line used for the pulse driving increases, which increases the settling time when shuttering and reading the pixel, potentially resulting in a decrease in frame rate.

[0005] This technology was developed in light of these circumstances, and aims to enable pulse driving of capacitors provided in pixels while suppressing a decrease in frame rate.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an imaging device including: a photoelectric conversion unit; a transfer transistor connected to the photoelectric conversion unit; a reset transistor having one terminal connected to the transfer transistor and the other terminal connected to a power supply voltage; a capacitor having one terminal connected to the photoelectric conversion unit and the other terminal connected to a control voltage; a voltage control line that transmits the control voltage; and a control line that transmits a transfer signal to the transfer transistor, the voltage control line intersecting the control line at right angles. This brings about an effect that a capacitive load of a non-selected row connected to the voltage control line is not visible from a selected row.

[0007] In the first aspect, the pixel may further include a signal line for transmitting a signal read from the photoelectric conversion unit, and the voltage control line may be parallel to the signal line. This brings about an effect that the control line and the voltage control line are orthogonal to the signal line.

[0008] In the first aspect, the pixel may further include a floating diffusion connected between the reset transistor and the transfer transistor, thereby providing an effect that a signal is read out based on charges transferred from the photoelectric conversion unit to the floating diffusion.

[0009] In the first aspect, the semiconductor device may further include a first layer on which the control lines are formed, a second layer on which the voltage control lines are formed, and a power supply line formed in an intermediate layer between the first layer and the second layer, thereby providing an effect of shielding the control lines and the voltage control lines via the power supply line.

[0010] In the first aspect, the capacitor may include a plurality of capacitors each connected to a different voltage control line, thereby providing an effect that charges overflowing from the photoelectric conversion unit are read out.

[0011] In the first aspect, the capacitor may have a three-dimensional MIM (Metal Insulation Metal) structure, which increases the capacitance of the capacitor without increasing the planar size of the capacitor.

[0012] In the first aspect, the photoelectric conversion unit may include a plurality of photoelectric conversion units having different sensitivities and connected to different transfer transistors, thereby providing an effect of expanding the dynamic range of imaging.

[0013] In the first aspect, the photoelectric conversion unit may include a first photoelectric conversion unit and a second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit, and the capacitor may store charge overflowing from the second photoelectric conversion unit, thereby expanding the dynamic range of imaging.

[0014] In addition, in the first aspect, the pixel array unit may include pixels each having the photoelectric conversion unit, the transfer transistor, the reset transistor, and the capacitor, the pixels being arranged in a matrix in a row direction and a column direction, the control lines being wired in the row direction, and the voltage control lines being wired in the column direction, thereby reducing the capacitance load on the selected row and the dark current of the capacitor.

[0015] In addition, in the first aspect, the liquid crystal display device may further include a drive circuit that drives the voltage control line for each column, thereby providing an effect that the load of the drive circuit is distributed among the columns.

[0016] In the first aspect, the drive circuit may pulse-drive the voltage control lines for each of the columns at the same timing, thereby providing an effect of controlling the potential of the voltage control lines.

[0017] In the first aspect, the drive circuit may set the potential of the voltage control line to a high level during a shutter period and a read period of the pixel, and set the potential of the voltage control line to a low level during an accumulation period of the pixel, thereby making the capacitive load of the non-selected row invisible to the selected row during the shutter period and the read period.

[0018] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment. FIG. 2 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment. FIG. 3 is a diagram showing an example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 4 is a timing chart showing an example of the relationship between a readout operation and a shutter operation of the solid-state imaging device according to the first embodiment. FIG. 5 is a timing chart showing an example of waveforms at each unit in a readout operation, a shutter operation, and a storage operation of the solid-state imaging device according to the first embodiment. FIG. 6 is a cross-sectional view showing an example of the configuration of a capacitor applied to a solid-state imaging device according to a second embodiment. FIG. 7 is a cross-sectional view showing an example of the configuration of wiring applied to a solid-state imaging device according to a third embodiment. FIG. 8 is a block diagram showing an example of the configuration of a solid-state imaging device according to a fourth embodiment. FIG. 9 is a diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to the fourth embodiment. FIG. 10 is a timing chart showing an example of waveforms at each unit in a readout operation, a shutter operation, and a storage operation of the solid-state imaging device according to the fifth embodiment. FIG. 11 is a timing chart showing an example of waveforms at each unit in a readout operation, a shutter operation, and a storage operation of the solid-state imaging device according to the fifth embodiment. FIG. 12 is a diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to a sixth embodiment. 13 is a timing chart showing an example of waveforms of each part in a readout operation, a shutter operation, and an accumulation operation of a solid-state imaging device according to a sixth embodiment. FIG. 14 is a perspective view showing an example of a stack of pixel array parts according to a seventh embodiment. FIG. 15 is a block diagram showing a schematic configuration example of a vehicle control system. FIG. 16 is an explanatory diagram showing an example of an installation position of an imaging part.

[0019] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which a voltage control line transmitting a control voltage for a capacitor provided in a pixel and a horizontal drive line driving each pixel row by row are orthogonalized) 2. Second embodiment (an example in which capacitors provided in a pixel have a three-dimensional MIM (Metal Insulation Metal) configuration) 3. Third embodiment (an example in which horizontal drive lines driving each pixel row by row are formed in a first layer, voltage control lines transmitting control voltages for capacitors provided in a pixel are formed in a second layer, and power lines are formed in an intermediate layer between the first layer and the second layer) 4. Fourth embodiment (an example in which multiple voltage control lines transmitting control voltages for multiple capacitors provided in a pixel are orthogonalized to horizontal drive lines driving each pixel row by row) 5. Fifth embodiment (an example in which multiple photoelectric conversion units with different sensitivities are provided in a pixel) 6. 6. Sixth embodiment (example in which different transfer transistors are connected to a plurality of photoelectric conversion units having different sensitivities) 7. Seventh embodiment (example in which pixel array units are stacked) 8. Example of application to a moving body

[0020] 1. First Embodiment FIG. 1 is a diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0021] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0022] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0023] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. The solid-state imaging device 102 is, for example, a complementary metal oxide semiconductor (CMOS) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may also be a lateral overflow integration capacitor (LOFIC) image sensor.

[0024] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0025] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0026] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0027] The display unit 106 displays captured images and various information that supports the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0028] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0029] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0030] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0031] In the figure, the solid-state imaging device 102 includes a pixel array section 111 , a vertical scanning circuit 112 , a column readout circuit 113 , a column signal processing section 114 , a horizontal scanning circuit 115 , a control circuit 116 , and a voltage control line driving circuit 117 .

[0032] The pixel array unit 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel 120 includes a capacitor that accumulates charge overflowing from a photodiode. This capacitor may be a horizontal overflow accumulation capacitor. Each pixel 120 may include a plurality of photodiodes with different sensitivities. Furthermore, each pixel 120 can form a source follower with the column readout circuit 113 when reading out a signal.

[0033] Each pixel 120 is connected to a horizontal drive line 131 for each row, and to a vertical signal line 132 and a voltage control line 133 for each column. The horizontal drive line 131 drives each pixel 120 for each row when reading out a signal from each pixel 120. The vertical signal line 132 transmits a potential based on a current that flows when reading out a signal from the pixel 120 to the column signal processing unit 114 for each column. The voltage control line 133 transmits a control voltage to be applied to a capacitor provided in each pixel 120. The voltage control line 133 intersects the horizontal drive line 131 at right angles. In this case, the voltage control line 133 can be parallel to the vertical signal line 132.

[0034] Each pixel 120 may be a single pixel, a four-pixel shared pixel, or an eight-pixel shared pixel. The pixels 120 may be arranged in a Bayer array or a quad-Bayer array. The light received by each pixel 120 may be visible light, near-infrared light (NIR), short-wavelength infrared light (SWIR), ultraviolet light, or X-rays. The horizontal drive line 131 is an example of a control line recited in the claims. The vertical signal line 132 is an example of a signal line recited in the claims.

[0035] The vertical scanning circuit 112 scans the pixels 120 to be read in the column direction. The vertical scanning circuit 112 may be configured using vertical registers. The vertical scanning circuit 112 may also include a decoder that specifies the pixels 120 to be read.

[0036] The column readout circuit 113 can form a source follower between itself and each pixel 120 when reading out a signal from the pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120.

[0037] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel 120. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 120. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 120, and output an imaging signal Gout.

[0038] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel 120 and the reference signal.

[0039] The horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0040] The voltage control line drive circuit 117 drives the voltage control lines 133 for each column. At this time, the voltage control line drive circuit 117 can pulse-drive the voltage control lines 133 for each column at the same timing. For example, the voltage control line drive circuit 117 can set the potential of the voltage control line 133 to a high level during the shutter period and read period of the pixel 120, and to a low level during the accumulation period of the pixel 120. Note that the low level of the potential of the voltage control line 133 is a potential lower than the high level, and for example, a combination of a high level of 3.3 V and a low level of 2.4 V may be used. The voltage control line drive circuit 117 is an example of a drive circuit as defined in the claims.

[0041] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, the horizontal scanning circuit 115, and the voltage control line driving circuit 117. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. The control circuit 116 can also control the driving timing of the voltage control line driving circuit 117. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, the horizontal scanning circuit 115, and the voltage control line driving circuit 117 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0042] 3 is a diagram showing an example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment, where "a" in the figure indicates the state of a non-selected row, and "b" in the figure indicates the state of a shutter row and a lead row.

[0043] In the figure, the pixel 120 includes a photodiode PD1, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. The pixel 120 also includes a capacitor 126, a pass transistor 127, a switching transistor 128, and an overflow control transistor 130. The transfer transistor 122, the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 may be MOS (Metal Oxide Semiconductor) transistors. The capacitor 126 may be a metal-insulation-metal (MIM) capacitor. The capacitor 126 may also be a three-dimensional MIM capacitor.

[0044] The photodiode PD1 performs photoelectric conversion and accumulates the photoelectrically converted charge. The capacitor 126 accumulates charge that overflows from the photodiode PD1. The capacitor 126 may be light-shielded. One end of the capacitor 126 is connected to a control voltage MVDD, and the other end of the capacitor 126 is connected to the cathode of the photodiode PD1 via the overflow control transistor 130. The capacitor 126 may be a high-dielectric capacitor.

[0045] The transfer transistor 122 transfers the charge accumulated in the photodiode PD1 to the floating diffusion FD. The reset transistor 123 resets the floating diffusion FD. The amplification transistor 124 outputs a signal according to the potential of the floating diffusion FD. The selection transistor 125 selects the output of the amplification transistor 124. The pass transistor 127 sets a path for the charge accumulated in the capacitor 126 to be transferred to the floating diffusion FD. The switching transistor 128 switches the conversion efficiency of the amplification transistor 124. The overflow control transistor 130 controls the overflow of charge from the photodiode PD1 to the capacitor 126.

[0046] The transfer transistor 122 is connected between the cathode of the photodiode PD1 and the floating diffusion FD. The amplification transistor 124 and the selection transistor 125 are connected in series. The drain of the amplification transistor 124 is connected to the power supply voltage VDD. The gate of the amplification transistor 124 is connected to the floating diffusion FD. The source of the selection transistor 125 is connected to the vertical signal line 132.

[0047] The pass transistor 127 is connected between the connection point of the overflow control transistor 130 and the capacitor 126 and the connection point of the reset transistor 123 and the switching transistor 128. The switching transistor 128 is connected between the reset transistor 123 and the floating diffusion FD. The reset transistor 123 is connected between the switching transistor 128 and the power supply voltage VDD. At this time, the reset transistor 123 and the switching transistor 128 are connected in series. The overflow control transistor 130 is connected between the photodiode PD1 and the capacitor 126.

[0048] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A select signal SEL is applied to the gate of the select transistor 125. A pass setting signal FCG is applied to the gate of the pass transistor 127. A switching signal FDG is applied to the gate of the switching transistor 128. An overflow control voltage OFG is applied to the gate of the overflow control transistor 130. A control voltage MVDD is applied to the capacitor 126. The transfer signal TGL, reset signal RST, select signal SEL, pass setting signal FCG, switching signal FDG, and overflow control voltage OFG can be transmitted to each pixel 120 via a horizontal drive line 131 in FIG. 2. The overflow control voltage OFG may be a fixed voltage. The control voltage MVDD can be transmitted to each pixel 120 via a voltage control line 133 in FIG. 2.

[0049] In the unselected rows, the reset transistor 123 and the pass transistor 127 are turned off, as shown by a in the figure. At this time, the capacitor 126 is in a floating state, and the pixels 120 in the unselected rows can be made invisible as load capacitance when viewed from the voltage control line 133.

[0050] On the other hand, in the shutter row and the read row, the reset transistor 123 and the pass transistor 127 are turned on, as shown by b in the figure. At this time, since the voltage control line 133 is perpendicular to the horizontal drive line 131, in the shutter row and the read row, the pixels 120 in the non-selected rows can be made invisible as load capacitance when viewed from the voltage control line 133, and the settling period can be shortened.

[0051] FIG. 4 is a timing chart showing an example of the relationship between the readout operation and the shutter operation of the solid-state imaging device according to the first embodiment.

[0052] In the figure, the solid-state imaging device repeats a shutter operation SH for each frame F1. At this time, the solid-state imaging device performs a read operation RD between the shutter operations SH in each frame F1.

[0053] In the target row ROI, an accumulation period P1 is set from the shutter operation SH of each frame F1 to the readout operation RD, and a non-accumulation period P2 is set from the readout operation RD to the shutter operation SH of the next frame F1.

[0054] In the shutter operation SH and the read operation RD, the potential of the voltage control line 133 is set to a high level. In the accumulation operation between the shutter operation SH and the read operation RD, the potential of the voltage control line 133 is set to a low level.

[0055] FIG. 5 is a timing chart showing an example of waveforms at various parts in the readout operation, shutter operation, and accumulation operation of the solid-state imaging device according to the first embodiment.

[0056] In the figure, during shutter period K11, the control voltage MVDD is set to a high level. The selection signal SEL is set to a low level. At this time, the switching signal FDG, transfer signal TGL, reset signal RST, and path setting signal FCG rise, the charges in the photodiode PD1 and floating diffusion FD are discharged, and the conversion efficiency of the amplification transistor 124 is reduced. Then, after the switching signal FDG, transfer signal TGL, and reset signal RST fall, the control voltage MVDD falls.

[0057] During the accumulation period K12, the path setting signal FCG falls. Then, charge is accumulated in each photodiode PD1 based on the incidence of light on the photodiode PD1. Charge overflowing from the photodiode PD1 is accumulated in the capacitor 126 via the overflow control transistor 130. Here, during the accumulation period K12, the dark current of the capacitor 126 can be reduced by setting the control voltage MVDD to a low level.

[0058] Next, in the low-efficiency P-phase single read period K13, the switching signal FDG and the control voltage MVDD rise, and then the selection signal SEL rises. At this time, the switching transistor 128 turns on, reducing the conversion efficiency of the amplification transistor 124. The selection transistor 125 turns on, and the potential of the vertical signal line 132 is set based on the source-follower operation when the low-efficiency P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the low-efficiency P-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0059] Next, in a high-efficiency P-phase single read period K14, the switching signal FDG falls. At this time, the switching transistor 128 is turned off, and the conversion efficiency of the amplification transistor 124 increases. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the high-efficiency P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the high-efficiency P-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0060] Next, during the high-efficiency D-phase single readout period K15, the selection signal SEL falls and the transfer signal TGL rises. At this time, the selection transistor 125 turns off and the transfer transistor 122 turns on, transferring the charge stored in the photodiode PD1 to the floating diffusion FD. Then, the selection signal SEL rises and the transfer signal TGL falls. At this time, the selection transistor 125 turns on and the transfer transistor 122 turns off, and the potential of the vertical signal line 132 is set based on the source-follower operation when the high-efficiency D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the high-efficiency D-phase level is AD-converted based on the potential of the vertical signal line 132 at that time. After that, the switching signal FDG rises and the switching transistor 128 turns on. At this time, the conversion efficiency of the amplification transistor 124 decreases.

[0061] Next, in the low-efficiency D-phase single readout period K16, the selection signal SEL falls and the transfer signal TGL rises. At this time, the selection transistor 125 turns off and the transfer transistor 122 turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD. Then, the selection signal SEL rises and the transfer signal TGL falls. At this time, the selection transistor 125 turns on and the transfer transistor 122 turns off, and the potential of the vertical signal line 132 is set based on the source follower operation when the low-efficiency D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the low-efficiency D-phase level is AD converted based on the potential of the vertical signal line 132 at that time.

[0062] CDS readout RDA can be performed in the low-efficiency P-phase single readout period K13, the high-efficiency P-phase single readout period K14, the high-efficiency D-phase single readout period K15, and the low-efficiency D-phase single readout period K16.

[0063] Next, in a D-phase batch read period K17, the selection signal SEL falls, and then the path setting signal FCG rises. Then, the selection signal SEL rises. At this time, the path transistor 127 is turned on, the selection transistor 125 is turned on, and the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the D-phase level is AD converted based on the potential of the vertical signal line 132 at that time.

[0064] Next, in a P-phase batch readout period K18, the selection signal SEL falls and the reset signal RST rises. At this time, the selection transistor 125 turns off and the reset transistor 123 turns on, and the charge in the floating diffusion FD is discharged. Then, the reset signal RST falls and the selection signal SEL rises. At this time, the reset transistor 123 turns off and the selection transistor 125 turns on, and the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the P-phase level is AD converted based on the potential of the vertical signal line 132 at that time.

[0065] When the P-phase batch read period K18 is completed, the control voltage MVDD falls. After that, the selection signal SEL, the switching transistor 128, and the path setting signal FCG fall. At this time, the control voltage MVDD is set to a low level, and the selection transistor 125, the switching transistor 128, and the path transistor 127 are turned off.

[0066] During the D-phase batch read period K17 and the P-phase batch read period K18, a DDS (Double Data Sampling) read RDB can be performed.

[0067] As described above, in the first embodiment, the voltage control line 133 that pulse-drives the capacitor 126 is made to intersect at right angles with the horizontal drive line 131. This makes it possible to make the pixels 120 in the non-selected rows invisible as load capacitances when viewed from the voltage control line 133 in the shutter row and the read row, thereby shortening the settling period.

[0068] 2. Second Embodiment In the first embodiment described above, the voltage control line 133 that pulse-drives the capacitor 126 is made perpendicular to the horizontal drive line 131. In this second embodiment, the capacitor 126 provided in the pixel 120 has a three-dimensional MIM configuration.

[0069] 6 is a cross-sectional view showing an example of the configuration of a capacitor applied to a solid-state imaging device according to the second embodiment. Note that the drawings used in the following description may differ in scale and shape from the actual structure in order to make each component easier to understand.

[0070] In the figure, a wiring layer 161 is embedded in an interlayer insulating layer 151. A passivation layer 152 is laminated on the wiring layer 161, and an interlayer insulating layer 153 is laminated on the passivation layer 152.

[0071] An opening KA exposing the wiring layer 161 is formed in the passivation layer 152 and the interlayer insulating layer 153. A capacitance electrode 154 is formed on the interlayer insulating layer 153 so as to cover the bottom and side surfaces of the opening KA. A dielectric layer 155 is formed on the capacitance electrode 154 so as to cover the bottom and side surfaces of the capacitance electrode 154. A capacitance electrode 156 is formed on the dielectric layer 155 so as to cover the bottom and side surfaces of the dielectric layer 155. The capacitance electrodes 154, 156 and the dielectric layer 155 can be used as a capacitor 126. In this case, the capacitor 126 can constitute a three-dimensional metal-insulating metal (MIM) structure. A passivation layer 157 is formed on the dielectric layer 155 so as to cover the capacitance electrode 156. An interlayer insulating layer 158 is stacked on the passivation layer 157. A wiring layer 162 is embedded in the interlayer insulating layer 158. The wiring layer 162 is connected to the capacitance electrode 156 through a via 163 .

[0072] The wiring layers 161, 162, via 163 and capacitance electrodes 154, 156 may be made of, for example, Cu, Ti, Ta, Al, W, Ni, Ru, Co, TiN, TaN, or WN, or may have a layered structure of multiple materials.

[0073] The material of the dielectric layer 155 is, for example, SiO ２ , SiON, Si ３ N ４ , hafnium oxide (HfO ２ ), aluminum oxide (Al ２ O ３ ), zirconium oxide (ZrO), tantalum oxide (Ta ２ O ５ ), titanium oxide (TiO ２ ), lanthanum oxide (LaO ３ ), yttrium oxide (Y ２ O ３ , aluminum nitride (AlN), hafnium oxynitride (HfON), aluminum oxynitride (AlON)) can be used, and a laminate structure of a plurality of materials may also be used.

[0074] The material of the interlayer insulating layers 151 and 158 is, for example, SiO ２ , SiON, SiOC, Si ３ N ４ Inorganic materials such as SiCO, polyimide, acrylic, silicone, and organic materials having an epoxy group as a skeleton can be used, and a laminate structure of a plurality of materials may also be used.

[0075] The materials of the passivation layers 152 and 157 are polyimide, acrylic, silicone, organic materials with an epoxy group as a skeleton, and SiO ２ , Al ２ O ３ The passivation layers 152 and 157 may be made of a material containing a filler such as SiO 2 , AlN, BN, etc. The passivation layers 152 and 157 may be made of a CVD (Chemical Vapor Deposition) film or a sputtered film.

[0076] As described above, in the second embodiment, the capacitor 126 provided in the pixel 120 has a three-dimensional MIM configuration. This allows the capacitance of the capacitor 126 to be increased without increasing the planar size of the capacitor 126.

[0077] 3. Third Embodiment In the first embodiment described above, the voltage control line 133 that pulse-drives the capacitor 126 is made to intersect at right angles with the horizontal drive line 131. In this third embodiment, the horizontal drive line 131 and the voltage control line 133 are formed on separate layers, and a power supply line is formed between these layers.

[0078] FIG. 7 is a cross-sectional view showing an example of the configuration of wiring applied to a solid-state imaging device according to the third embodiment.

[0079] In the figure, an element isolation layer 172 is formed on a semiconductor substrate 171. The element isolation layer 172 may be STI (Shallow Trench Isolation). A photoelectric conversion layer 173 and impurity diffusion layers 178 to 181 are formed on the semiconductor substrate 171 and are isolated from each other. Gate electrodes 174 to 176 are formed on the semiconductor substrate 171 with a gate insulating film interposed therebetween. A channel region formed under the gate electrode 174 is disposed between the photoelectric conversion layer 173 and the impurity diffusion layer 178. A channel region formed under the gate electrode 175 is disposed between the impurity diffusion layers 179 and 180. A channel region formed under the gate electrode 176 is disposed between the impurity diffusion layers 180 and 181.

[0080] The photoelectric conversion layer 173 can be used for the photodiode PD1. The impurity diffusion layer 178 can be used for the floating diffusion FD. The gate electrode 174 can be used for the transfer transistor 122. The gate electrode 175 can be used for the amplification transistor 124. The gate electrode 176 can be used for the selection transistor 125.

[0081] Furthermore, an insulating layer 182 is formed on the semiconductor substrate 171 so as to cover the photoelectric conversion layer 173 and the gate electrodes 174 to 176. At this time, multi-layer wiring can be formed in the insulating layer 182. For example, wirings 183 to 191, a power supply line 192, and a capacitor 126 can be embedded in the insulating layer 182. The wiring 183 can be arranged in the first layer. The wirings 184 to 190 can be arranged in the second layer. The power supply line 192 can be arranged in the third layer. The wiring 191 can be arranged in the fourth layer. The wiring 183 is connected to the impurity diffusion layer 181 through a via 193. One end of the capacitor 126 is connected to the wiring 185 through a via 194. The other end of the capacitor 126 is connected to the wiring 191 through a via 195.

[0082] The wiring 183 can be used for the vertical signal line 132. The wiring 184 can be connected to the gate of the overflow control transistor 130. The wiring 185 can be connected to the impurity diffusion layer 178. The wiring 186 can be connected to the gate of the transfer transistor 122. The wiring 187 can be connected to the gate of the switching transistor 128. The wiring 188 can be connected to the gate of the pass transistor 127. The wiring 189 can be connected to the gate of the reset transistor 123. The wiring 190 can be connected to the gate of the selection transistor 125. The wiring 191 can be used for the voltage control line 133. The power supply line 192 can be used to supply the power supply voltage VDD. A gap may be formed in part of the power supply line 192.

[0083] The wirings 183 and 191 extend in the column direction, and the wirings 184 to 190 extend in the row direction. In this case, the wirings 184 to 190 can be used as horizontal drive lines 131. The wiring 191 is formed in a layer different from the layer of the wirings 184 to 190. The wiring 191 and the wirings 184 to 190 are shielded by a power supply line 192.

[0084] The semiconductor substrate 171 may be made of Si, InGaAs, InP, or the like, depending on the sensitivity band of the photoelectric conversion layer 173. The gate electrodes 174 to 176 may be made of polycrystalline silicon or the like.

[0085] The materials of the wiring 183 to 191, the power supply line 192 and the vias 193 to 195 may be, for example, Cu, Ti, Ta, Al, W, Ni, Ru, Co, TiN, TaN, or WN, and may also be a laminate structure of multiple materials.

[0086] The material of the insulating layer 182 is, for example, SiO ２ , SiON, SiOC, Si ３ N ４ Inorganic materials such as SiCO, polyimide, acrylic, silicone, and organic materials having an epoxy group as a skeleton can be used, and a laminate structure of a plurality of materials may also be used.

[0087] In this way, in the third embodiment described above, the horizontal drive line 131 and the voltage control line 133 are formed on separate layers, and the power supply line 192 is formed between these layers, thereby making it possible to suppress coupling between the voltage control line 133 and the horizontal drive line 131 and vertical signal line 132.

[0088] 4. Fourth Embodiment In the first embodiment described above, the voltage control line 133 that pulse-drives the capacitor 126 provided in the pixel 120 is made to intersect at right angles with the horizontal drive line 131. In this fourth embodiment, a plurality of voltage control lines that transmit control voltages for a plurality of capacitors provided in the pixel are made to intersect at right angles with the horizontal drive line 131.

[0089] FIG. 8 is a block diagram showing an example of the configuration of a solid-state imaging device according to the fourth embodiment.

[0090] In the figure, the solid-state imaging device 502 includes a pixel array section 511, a control circuit 516, and a voltage control line drive circuit 517 instead of the pixel array section 111, the control circuit 116, and the voltage control line drive circuit 117 of the above-described first embodiment. Furthermore, the solid-state imaging device 502 additionally includes a voltage control line 134 in addition to the components of the solid-state imaging device 102 of the above-described first embodiment. Other configurations of the solid-state imaging device 502 of the fourth embodiment are similar to the configuration of the solid-state imaging device 102 of the above-described first embodiment.

[0091] The pixel array unit 511 includes a plurality of pixels 520. The pixels 520 are arranged in a matrix along the row and column directions. Each pixel 520 includes a plurality of capacitors that store charge overflowing from a photodiode. These capacitors may be horizontal overflow storage capacitors. Each pixel 520 may include a plurality of photodiodes with different sensitivities. Furthermore, each pixel 520 can form a source follower with the column readout circuit 113 when reading out a signal.

[0092] Each pixel 520 is connected to a horizontal drive line 131 for each row, and to a vertical signal line 132 and multiple voltage control lines 133 and 134 for each column. Each voltage control line 133 and 134 transmits a control voltage to be applied to multiple capacitors provided in each pixel 120. Each voltage control line 133 and 134 intersects the horizontal drive line 131 at right angles. In this case, each voltage control line 133 and 134 can be parallel to the vertical signal line 132.

[0093] The voltage control line drive circuit 517 drives the multiple voltage control lines 133, 134 for each column. At this time, the voltage control line drive circuit 517 can pulse-drive the multiple voltage control lines 133, 134 for each column at the same timing. For example, the voltage control line drive circuit 517 can set the potential of each voltage control line 133, 134 to a high level during the shutter period and read period of the pixel 520, and set the potential of each voltage control line 133, 134 to a low level during the accumulation period of the pixel 520.

[0094] The control circuit 516 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, the horizontal scanning circuit 115, and the voltage control line driving circuit 517. At this time, the control circuit 516 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, the horizontal scanning circuit 115, and the voltage control line driving circuit 517 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0095] FIG. 9 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fourth embodiment.

[0096] In the figure, pixel 520 is the same as pixel 120 of the first embodiment described above, except that it further includes a pass transistor 527 and a capacitor 526. The other configuration of pixel 520 of the fourth embodiment is the same as the configuration of pixel 120 of the first embodiment described above.

[0097] The capacitor 526 accumulates the charge that overflows from the photodiode PD1. The capacitor 526 may be light-shielded. One end of the capacitor 526 is connected to a control voltage MVDD2, and the other end of the capacitor 526 is connected to the overflow control transistor 130 via a pass transistor 527. At this time, the control voltage MVDD2 is applied to the capacitor 526.

[0098] The pass transistor 527 sets a path for transferring the charge stored in the capacitor 526 to the floating diffusion FD. The pass transistor 527 is connected between the capacitor 526 and the connection point between the overflow control transistor 130 and the capacitor 126. A pass setting signal FCG2 is applied to the gate of the pass transistor 527. The pass setting signal FCG2 can be transmitted to each pixel 520 via the horizontal drive line 131 in FIG. 2. The control voltage MVDD2 can be transmitted to each pixel 520 via the voltage control line 134.

[0099] FIG. 10 is a timing chart showing an example of waveforms at various parts in the readout operation, shutter operation, and accumulation operation of the solid-state imaging device according to the fourth embodiment.

[0100] In the figure, during shutter period K21, the control voltages MVDD and MVDD2 are set to a high level. The selection signal SEL is set to a low level. At this time, the switching signal FDG, transfer signal TGL, reset signal RST, and path setting signals FCG and FCG2 rise, the charges in the photodiode PD1 and floating diffusion FD are discharged, and the conversion efficiency of the amplification transistor 124 is reduced. Then, after the switching signal FDG, transfer signal TGL, and reset signal RST fall, the control voltage MVDD falls.

[0101] During the accumulation period K22, the path setting signals FCG and FCG2 fall. Then, charge is accumulated in each photodiode PD1 based on the incidence of light on the photodiode PD1. Charge overflowing from the photodiode PD1 is accumulated in the capacitors 126 and 526 via the overflow control transistor 130. Here, during the accumulation period K12, the dark current of each capacitor 126 and 526 can be reduced by setting the control voltages MVDD and MVDD2 to a low level.

[0102] Next, in the low-efficiency P-phase single read period K23, the switching signal FDG and the control voltages MVDD and MVDD2 rise, and then the selection signal SEL rises. At this time, the switching transistor 128 turns on, reducing the conversion efficiency of the amplification transistor 124. Furthermore, the selection transistor 125 turns on, and the potential of the vertical signal line 132 is set based on the source follower operation when the low-efficiency P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the low-efficiency P-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0103] Next, in a high-efficiency P-phase single read period K24, the switching signal FDG falls. At this time, the switching transistor 128 is turned off, and the conversion efficiency of the amplification transistor 124 increases. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the high-efficiency P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the high-efficiency P-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0104] Next, during the high-efficiency D-phase single readout period K25, the selection signal SEL falls and the transfer signal TGL rises. At this time, the selection transistor 125 turns off and the transfer transistor 122 turns on, transferring the charge stored in the photodiode PD1 to the floating diffusion FD. Then, the selection signal SEL rises and the transfer signal TGL falls. At this time, the selection transistor 125 turns on and the transfer transistor 122 turns off, and the potential of the vertical signal line 132 is set based on the source-follower operation when the high-efficiency D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the high-efficiency D-phase level is AD-converted based on the potential of the vertical signal line 132 at that time. After that, the switching signal FDG rises and the switching transistor 128 turns on. At this time, the conversion efficiency of the amplification transistor 124 decreases.

[0105] Next, in a low-efficiency D-phase single readout period K26, the selection signal SEL falls and the transfer signal TGL rises. At this time, the selection transistor 125 turns off and the transfer transistor 122 turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD. Then, the selection signal SEL rises and the transfer signal TGL falls. At this time, the selection transistor 125 turns on and the transfer transistor 122 turns off, and the potential of the vertical signal line 132 is set based on the source follower operation when the low-efficiency D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the low-efficiency D-phase level is AD converted based on the potential of the vertical signal line 132 at that time.

[0106] CDS readout RDA can be performed in the low-efficiency P-phase single readout period K23, the high-efficiency P-phase single readout period K24, the high-efficiency D-phase single readout period K25, and the low-efficiency D-phase single readout period K26.

[0107] Next, in the first D-phase batch readout period K27, the path setting signal FCG rises, turning on the path transistor 127. At this time, the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the D-phase level is AD converted based on the potential of the vertical signal line 132 at that time.

[0108] Next, during the first D-phase batch readout period K28, the selection signal SEL falls and the path setting signal FCG2 rises. Then, the selection signal SEL rises. At this time, the path transistor 527 is on, the selection transistor 125 is on, and the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the D-phase level is AD converted based on the potential of the vertical signal line 132 at that time. Then, the reset signal RST rises. At this time, the reset transistor 123 is on, and the charge of the floating diffusion FD is discharged.

[0109] Next, in the first P-phase batch readout period K29, the reset signal RST falls, turning off the reset transistor 123. At this time, the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, based on the potential of the vertical signal line 132 at that time, the P-phase level is AD converted.

[0110] Next, in the second P-phase batch readout period K30, the selection signal SEL falls, and the path setting signal FCG2 falls. Then, the selection signal SEL rises, and the selection transistor 125 turns on. At this time, the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 124. Then, the P-phase level is AD converted based on the potential of the vertical signal line 132 at that time.

[0111] In the first D-phase batch read period K27, the second D-phase batch read period K28, the first P-phase batch read period K29, and the second P-phase batch read period K30, the DDS read RDB can be performed.

[0112] As described above, in the fourth embodiment, the plurality of voltage control lines 133, 134 that transmit the control voltages MVDD, MVDD2 for the plurality of capacitors 126, 526 provided in the pixels 520 are orthogonal to the horizontal drive line 131. This makes it possible to make the pixels 520 in the non-selected rows invisible as load capacitances seen from the voltage control lines 133, 134 in the shutter row and the read row, and it is possible to shorten the settling period while expanding the dynamic range.

[0113] 5. Fifth Embodiment In the first embodiment described above, the voltage control line 133 that pulse-drives the capacitor 126 provided in the pixel 120 is made to intersect at right angles with the horizontal drive line 131. In this fifth embodiment, a pixel is provided with a plurality of photoelectric conversion units having different sensitivities.

[0114] FIG. 11 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the fifth embodiment.

[0115] In the figure, the pixel 220 is obtained by adding a photodiode PD2 to the pixel 120 of the first embodiment described above. Furthermore, the pixel 220 is obtained by removing the overflow control transistor 130 from the pixel 120 of the first embodiment described above. Other configurations of the pixel 220 of the fifth embodiment are the same as the configuration of the pixel 120 of the first embodiment described above.

[0116] The photodiode PD2 performs photoelectric conversion and accumulates the photoelectrically converted charge. The sensitivity of the photodiode PD2 can be made smaller than that of the photodiode PD1. The cathode of the photodiode PD2 is connected to the connection point between the capacitor 126 and the pass transistor 127.

[0117] Furthermore, a floating diffusion FD1 is provided at the connection point between the transfer transistor 122 and the switching transistor 128. A floating diffusion FD2 is provided at the connection point between the reset transistor 123 and the switching transistor 128. A floating diffusion FD3 is provided at the connection point between the capacitor 126 and the pass transistor 127.

[0118] FIG. 12 is a timing chart showing an example of waveforms at various parts in the readout operation, shutter operation, and accumulation operation of the solid-state imaging device according to the fifth embodiment.

[0119] In the figure, during shutter period K41, the control voltage MVDD, switching signal FDG, and reset signal RST are set to high level. The selection signal SEL is set to low level. At this time, when the path setting signal FCG is high level, the transfer signal TGL rises, the charges in the photodiodes PD1 and PD2 and the floating diffusions FD1 to FD3 are discharged, and the conversion efficiency of the amplification transistor 124 is reduced. Then, after the transfer signal TGL and the path setting signal FCG fall, the control voltage MVDD falls.

[0120] During the accumulation period K42, charges are accumulated in the photodiodes PD1 and PD2 based on the incidence of light on the photodiodes PD1 and PD2. Charges that overflow from the photodiode PD2 are accumulated in the capacitor 126. Here, during the accumulation period K42, the dark current of the capacitor 126 can be reduced by setting the control voltage MVDD to a low level.

[0121] Next, in the low-efficiency P-phase single read period K43, the selection signal SEL and the control voltage MVDD rise, and the reset signal RST falls. At this time, the switching transistor 128 turns on, reducing the conversion efficiency of the amplification transistor 124. The reset transistor 123 turns off, the selection transistor 125 turns on, and the potential of the vertical signal line 132 is set based on the source-follower operation when the low-efficiency P-phase level of the floating diffusions FD1 and FD2 is applied to the gate of the amplification transistor 124. Then, the low-efficiency P-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0122] Next, in a high-efficiency P-phase single read period K44, the switching signal FDG falls. At this time, the switching transistor 128 is turned off, and the conversion efficiency of the amplification transistor 124 increases. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the high-efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 124. Then, the high-efficiency P-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0123] Thereafter, the selection signal SEL falls and the transfer signal TGL rises. At this time, the selection transistor 125 turns off and the transfer transistor 122 turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.

[0124] Next, in a high-efficiency D-phase individual read period K45, the selection signal SEL rises and the transfer signal TGL falls. At this time, the selection transistor 125 turns on and the transfer transistor 122 turns off, and the potential of the vertical signal line 132 is set based on the source follower operation when the high-efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 124. Then, the high-efficiency D-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0125] Then, the selection signal SEL falls, and the transfer signal TGL and the switching signal FDG rise. At this time, the selection transistor 125 turns off, and the transfer transistor 122 and the switching transistor 128 turn on, so that the charge stored in the photodiode PD1 is transferred to the floating diffusions FD1 and FD2. At this time, the conversion efficiency of the amplification transistor 124 decreases.

[0126] Next, in a low-efficiency D-phase single read period K46, the selection signal SEL rises and the transfer signal TGL falls. At this time, the selection transistor 125 turns on and the transfer transistor 122 turns off, and the potential of the vertical signal line 132 is set based on the source follower operation when the low-efficiency D-phase level of the floating diffusions FD1 and FD2 is applied to the gate of the amplification transistor 124. Then, the low-efficiency D-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0127] CDS readout RDA can be performed in the low-efficiency P-phase single readout period K43, the high-efficiency P-phase single readout period K44, the high-efficiency D-phase single readout period K45, and the low-efficiency D-phase single readout period K46.

[0128] After that, the reset signal RST rises, turning on the reset transistor 123 and discharging the charges from the floating diffusions FD1 and FD2.

[0129] Next, in a D-phase batch read period K47, the reset signal RST falls and the path setting signal FCG rises. At this time, the path transistor 127 turns on, and the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase levels of the floating diffusions FD1 to FD3 are applied to the gate of the amplification transistor 124. Then, the D-phase level is AD converted based on the potential of the vertical signal line 132 at that time.

[0130] After that, the reset signal RST rises and the selection signal SEL falls. At this time, the reset transistor 123 turns on and the selection transistor 125 turns off, and the charges in the floating diffusions FD1 to FD3 are discharged. After that, the reset signal RST falls and the reset transistor 123 turns off.

[0131] Next, in a P-phase batch readout period K48, the selection signal SEL rises. At this time, the selection transistor 125 turns on, and the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase levels of the floating diffusions FD1 to FD3 are applied to the gates of the amplification transistors 124. Then, based on the potential of the vertical signal line 132 at that time, the P-phase level is AD converted.

[0132] During the D-phase batch read period K47 and the P-phase batch read period K48, the DDS read RDB can be performed.

[0133] As described above, in the fifth embodiment, a plurality of photodiodes PD1 and PD2 having different sensitivities are provided in the pixel 220, and the voltage control line 133 that pulse-drives the capacitor 126 is made perpendicular to the horizontal drive line 131. This makes it possible to reduce the dark current of the capacitor 126, expand the dynamic range, and shorten the settling period.

[0134] 6. Sixth Embodiment In the above-described fifth embodiment, a plurality of photodiodes PD1, PD2 having different sensitivities are provided in the pixel 220. In this sixth embodiment, different transfer transistors are connected to the plurality of photodiodes PD1, PD2 having different sensitivities, respectively.

[0135] FIG. 13 is a diagram showing an example of a circuit configuration of a pixel provided in a solid-state imaging device according to the sixth embodiment.

[0136] In the figure, a pixel 320 is the same as the pixel 220 of the fifth embodiment described above, except that a transfer transistor 129 is added. Other configurations of the pixel 320 of the sixth embodiment are the same as the configurations of the pixel 220 of the fifth embodiment described above.

[0137] The transfer transistor 129 transfers the charge accumulated in the photodiode PD2 to the floating diffusion FD3. The transfer transistor 129 is connected between the connection point of the capacitor 126 and the pass transistor 127 and the cathode of the photodiode PD2. A transfer signal TGS is applied to the gate of the transfer transistor 129. The transfer signal TGS can be transmitted to each pixel 120 via the horizontal drive line 131 in FIG. 2 .

[0138] FIG. 14 is a timing chart showing an example of waveforms at various parts in the readout operation, shutter operation, and accumulation operation of the solid-state imaging device according to the sixth embodiment.

[0139] In the figure, during shutter period K51, the control voltage MVDD, switching signal FDG, path setting signal FCG, and reset signal RST are set to high level. The selection signal SEL is set to low level. At this time, the transfer signals TGL and TGS rise, the charges in the photodiodes PD1 and PD2 and the floating diffusions FD1 to FD3 are discharged, and the conversion efficiency of the amplification transistor 124 is reduced. Then, the transfer signals TGL and TGS and the path setting signal FCG fall.

[0140] During the accumulation period K52, the control voltage MVDD falls. At this time, charges are accumulated in the photodiodes PD1 and PD2 based on the incidence of light on the photodiodes PD1 and PD2. Here, during the accumulation period K52, the control voltage MVDD is set to a low level, thereby reducing the dark current of the capacitor 126.

[0141] Next, in the low-efficiency first P-phase single read period K53, the selection signal SEL and the control voltage MVDD rise, and the reset signal RST falls. At this time, the switching transistor 128 turns on, reducing the conversion efficiency of the amplification transistor 124. The reset transistor 123 turns off, the selection transistor 125 turns on, and the potential of the vertical signal line 132 is set based on the source-follower operation when the low-efficiency P-phase level of the floating diffusions FD1 and FD2 is applied to the gate of the amplification transistor 124. Then, the low-efficiency first P-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0142] Next, in the high-efficiency first P-phase single read period K54, the switching signal FDG falls. At this time, the switching transistor 128 is turned off, and the conversion efficiency of the amplification transistor 124 increases. Then, the potential of the vertical signal line 132 is set based on the source follower operation when the high-efficiency P-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 124. Then, the high-efficiency first P-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0143] Thereafter, the selection signal SEL falls and the transfer signal TGL rises. At this time, the selection transistor 125 turns off and the transfer transistor 122 turns on, and the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD1.

[0144] Next, in a high-efficiency first D-phase individual read period K55, the selection signal SEL rises and the transfer signal TGL falls. At this time, the selection transistor 125 turns on and the transfer transistor 122 turns off, and the potential of the vertical signal line 132 is set based on the source follower operation when the high-efficiency D-phase level of the floating diffusion FD1 is applied to the gate of the amplification transistor 124. Then, the high-efficiency first D-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0145] Then, the selection signal SEL falls, and the transfer signal TGL and the switching signal FDG rise. At this time, the selection transistor 125 turns off, and the transfer transistor 122 and the switching transistor 128 turn on, so that the charge stored in the photodiode PD1 is transferred to the floating diffusions FD1 and FD2. At this time, the conversion efficiency of the amplification transistor 124 decreases.

[0146] Next, in a low-efficiency first D-phase individual read period K56, the selection signal SEL rises and the transfer signal TGL falls. At this time, the selection transistor 125 turns on and the transfer transistor 122 turns off, and the potential of the vertical signal line 132 is set based on the source follower operation when the low-efficiency D-phase levels of the floating diffusions FD1 and FD2 are applied to the gates of the amplification transistors 124. Then, the low-efficiency first D-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0147] CDS readout RDA can be performed in the low-efficiency first P-phase individual readout period K53, the high-efficiency first P-phase individual readout period K54, the high-efficiency first D-phase individual readout period K55, and the low-efficiency first D-phase individual readout period K56.

[0148] Thereafter, the selection signal SEL falls and the reset signal RST rises, turning on the reset transistor 123 and discharging the charges in the floating diffusions FD1 and FD2.

[0149] Furthermore, after the reset signal RST falls, the path setting signal FCG rises, turning the reset transistor 123 off and the path transistor 127 on.

[0150] Next, in a second P-phase individual readout period K57, the selection signal SEL rises. At this time, the selection transistor 125 turns on, and the potential of the vertical signal line 132 is set based on the source follower operation when the second P-phase levels of the floating diffusions FD1 to FD3 are applied to the gates of the amplification transistors 124. Then, the second P-phase level is AD converted based on the potential of the vertical signal line 132 at that time.

[0151] Thereafter, the selection signal SEL falls and the transfer signal TGS rises. At this time, the selection transistor 125 turns off and the transfer transistor 129 turns on, and the charge accumulated in the photodiode PD2 is transferred from the floating diffusion FD1 to FD3.

[0152] Next, in a second D-phase individual read period K58, the selection signal SEL rises and the transfer signal TGS falls. At this time, the potential of the vertical signal line 132 is set based on the source follower operation when the second D-phase levels of the floating diffusions FD1 to FD3 are applied to the gates of the amplification transistors 124. Then, the second D-phase level is AD-converted based on the potential of the vertical signal line 132 at that time.

[0153] Next, in a D-phase batch readout period K59, the potential of the vertical signal line 132 is set based on the source follower operation when the D-phase levels of the floating diffusions FD1 to FD3 are applied to the gates of the amplification transistors 124. Then, based on the potential of the vertical signal line 132 at that time, the D-phase level is AD converted.

[0154] After that, the reset signal RST rises and the selection signal SEL falls. At this time, the reset transistor 123 turns on and the selection transistor 125 turns off, and the charges in the floating diffusions FD1 to FD3 are discharged. After that, the reset signal RST falls and the reset transistor 123 turns off.

[0155] Next, in a P-phase batch readout period K60, the selection signal SEL rises. At this time, the selection transistor 125 turns on, and the potential of the vertical signal line 132 is set based on the source follower operation when the P-phase levels of the floating diffusions FD1 to FD3 are applied to the gate of the amplification transistor 124. Then, based on the potential of the vertical signal line 132 at that time, the P-phase level is AD converted.

[0156] During the D-phase batch read period K59 and the P-phase batch read period K60, the DDS read RDB can be performed.

[0157] In this way, in the sixth embodiment, the photodiodes PD1 and PD2 having different sensitivities are connected to the different transfer transistors 122 and 129. This makes it possible to reduce the dark current of the capacitor 126, expand the dynamic range, and shorten the settling period.

[0158] 7. Seventh Embodiment In the first embodiment described above, the voltage control line 133 that pulse-drives the capacitor 126 is made to intersect at right angles with the horizontal drive line 131. In this seventh embodiment, semiconductor chips each having a pixel array section in which pixels are arranged in a matrix are stacked.

[0159] FIG. 15 is a perspective view showing an example of a stack of pixel array units according to the seventh embodiment.

[0160] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0161] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. The pixels 931 may be any of the pixels in the first and fourth to sixth embodiments described above. In the first, fifth, and sixth embodiments described above, horizontal drive lines 131, vertical signal lines 132, and voltage control lines 133 are formed in the pixel array section 923. In the fourth embodiment described above, horizontal drive lines 131, vertical signal lines 132, and voltage control lines 133 and 134 are formed in the pixel array section 923. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0162] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and a control circuit 928 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction.

[0163] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0164] As described above, in the seventh embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0165] 7. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0166] FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0167] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 16, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0168] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0169] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0170] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0171] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0172] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0173] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0174] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0175] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0176] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 16, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0177] FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031.

[0178] In FIG. 17, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0179] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0180] 17 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0181] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0182] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0183] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0184] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0185] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, the imaging device according to the above-described embodiment can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to shorten the settling period and expand the dynamic range.

[0186] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0187] The present technology may also be configured as follows: (1) An imaging device including a photoelectric conversion unit, a transfer transistor connected to the photoelectric conversion unit, a reset transistor having one terminal connected to the transfer transistor and the other terminal connected to a power supply voltage, a capacitor having one terminal connected to the photoelectric conversion unit and the other terminal connected to a control voltage, a voltage control line transmitting the control voltage, and a control line transmitting a transfer signal to the transfer transistor, the voltage control line intersecting the control line. (2) The imaging device according to (1), further including a signal line transmitting a signal read from the photoelectric conversion unit, the voltage control line being parallel to the signal line. (3) The imaging device according to claim 1 in (1) or (2), further including a floating diffusion connected between the reset transistor and the transfer transistor. (4) The imaging device according to any one of (1) to (3), further including a first layer on which the control line is formed, a second layer on which the voltage control line is formed, and a power supply line formed in an intermediate layer between the first layer and the second layer. (5) The imaging device according to any one of (1) to (4), wherein the capacitor comprises a plurality of capacitors each connected to a different voltage control line. (6) The imaging device according to any one of (1) to (5), wherein the capacitor comprises a three-dimensional MIM (Metal Insulation Metal) structure. (7) The imaging device according to any one of (1) to (6), wherein the photoelectric conversion unit comprises a plurality of photoelectric conversion units each connected to a different transfer transistor and having different sensitivities. (8) The imaging device according to any one of (1) to (7), wherein the photoelectric conversion unit comprises: a first photoelectric conversion unit; and a second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit, and the capacitor accumulates charge overflowing from the second photoelectric conversion unit. (9) An imaging device according to any one of (1) to (8), comprising a pixel array section in which pixels each having the photoelectric conversion section, the transfer transistor, the reset transistor, and the capacitor are arranged in a matrix in row and column directions, the control lines are wired in the row direction, and the voltage control lines are wired in the column direction.(10) The imaging device according to (9), further comprising: a drive circuit that drives the voltage control lines for each column. (11) The imaging device according to (10), wherein the drive circuit pulse-drives the voltage control lines for each column at the same timing. (12) The imaging device according to (11), wherein the drive circuit sets the potential of the voltage control line to a high level during a shutter period and a read period of the pixel, and sets the potential of the voltage control line to a low level during an accumulation period of the pixel.

[0188] REFERENCE SIGNS LIST 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 115 Horizontal scanning circuit 116 Control circuit 117 Voltage control line driving circuit PD1 Photodiode 122 Transfer transistor 123 Reset transistor 124 Amplifying transistor 125 Selection transistor 126 Capacitor 127 Pass transistor 128 Switching transistor FD Floating diffusion 131 Horizontal driving line 132 Vertical signal line 133 Voltage control line

Claims

1. An imaging device comprising: a photoelectric conversion unit; a transfer transistor connected to the photoelectric conversion unit; a reset transistor having one terminal connected to the transfer transistor and the other terminal connected to a power supply voltage; a capacitor having one terminal connected to the photoelectric conversion unit and the other terminal connected to a control voltage; a voltage control line that transmits the control voltage; and a control line that transmits a transfer signal to the transfer transistor, the voltage control line being perpendicular to the control line.

2. The imaging device according to claim 1, further comprising a signal line for transmitting a signal read out from said photoelectric conversion section, said voltage control line being parallel to said signal line.

3. The imaging device according to claim 1, further comprising a floating diffusion connected between the reset transistor and the transfer transistor.

4. The imaging device of claim 1, further comprising: a first layer in which the control line is formed; a second layer in which the voltage control line is formed; and a power supply line formed in an intermediate layer between the first layer and the second layer.

5. The imaging device according to claim 1, wherein the capacitor comprises a plurality of capacitors each connected to a different voltage control line.

6. The imaging device according to claim 1, wherein the capacitor has a three-dimensional MIM (Metal Insulation Metal) structure.

7. The imaging device according to claim 1, wherein the photoelectric conversion section comprises a plurality of photoelectric conversion sections having different sensitivities and each of which is connected to a different transfer transistor.

8. The imaging device according to claim 1, wherein the photoelectric conversion unit comprises a first photoelectric conversion unit and a second photoelectric conversion unit having a lower sensitivity than the first photoelectric conversion unit, and the capacitor accumulates electric charges overflowing from the second photoelectric conversion unit.

9. The imaging device according to claim 1, further comprising a pixel array section in which pixels each having the photoelectric conversion section, the transfer transistor, the reset transistor and the capacitor are arranged in a matrix in row and column directions, the control lines being wired in the row direction, and the voltage control lines being wired in the column direction.

10. The imaging device according to claim 9, further comprising a drive circuit for driving the voltage control lines for each column.

11. The imaging device according to claim 10, wherein the drive circuit pulse-drives the voltage control lines for each of the columns at the same timing.

12. The imaging device according to claim 11, wherein the drive circuit sets the potential of the voltage control line to a high level during a shutter period and a read period of the pixel, and sets the potential of the voltage control line to a low level during a storage period of the pixel.