Semiconductor memory device

Abstract

This semiconductor memory device comprises: a semiconductor substrate that contains a thin film transistor and extends along a first surface; a capacitor that is provided on the semiconductor substrate, connects to the thin film transistor, and contains a hole that extends in a first direction that intersects with the first surface; and a first insulating film provided in the hole of the capacitor. The capacitor has a laminated structure in which the following are stacked in a direction that intersects an inner surface of the hole: a first electrode film having a first recessed part; a ferroelectric film provided along an inner surface of the first recessed part and having a second recessed part; and a second electrode film provided along an inner surface of the second recessed part and having a third recessed part.

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device including a capacitor.

[0002] A CMOS (Complementary MOS) circuit composed of an n-type field effect transistor (nMOSFET) and a p-type field effect transistor (pMOSFET) provided on the same substrate is known as a circuit that consumes little power, is capable of high-speed operation, and is easy to miniaturize and highly integrate.

[0003] For this reason, CMOS circuits are used in many LSI (Large Scale Integration) devices. In recent years, such LSI devices have been commercialized as SoCs (System on a Chip), which integrate analog circuits, memories, logic circuits, and the like on a single chip.

[0004] For example, static random access memory (SRAM) is used as a memory mounted on an LSI device. In recent years, in order to further reduce the cost and power consumption of LSI devices, the use of dynamic RAM (DRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), or the like instead of SRAM has been considered. Here, FeRAM is a semiconductor memory device that stores information using the direction of remanent polarization of a ferroelectric. A semiconductor memory device that functions as an FeRAM using such a ferroelectric capacitor has already been proposed (for example, Patent Document 1).

[0005] JP 2019-160841 A

[0006] In the field of electronic devices such as semiconductor memory devices, there is a demand for miniaturization of dimensions as well as improvement of operational reliability.

[0007] Therefore, a semiconductor memory device with excellent operational reliability is desired.

[0008] A semiconductor memory device according to an embodiment of the present disclosure includes a semiconductor substrate including a thin film transistor and extending along a first surface, a capacitor provided on the semiconductor substrate and connected to the thin film transistor, the capacitor including a hole dug in a first direction intersecting the first surface, and a first insulating film provided in the hole of the capacitor. The capacitor has a layered structure in which a first electrode film having a first recess, a ferroelectric film provided along the inner surface of the first recess and having a second recess, and a second electrode film provided along the inner surface of the second recess and having a third recess are stacked in a direction intersecting the inner surface of the hole.

[0009] In the semiconductor memory device according to the embodiment of the present disclosure, the first insulating film is provided in the hole of the capacitor, and therefore foreign matter is prevented from entering the hole of the capacitor during the manufacturing process.

[0010] FIG. 1 is a circuit diagram showing an example of an equivalent circuit of a semiconductor memory device according to a first embodiment of the present disclosure. FIG. 2 is a schematic diagram showing an example of a cross-sectional configuration of the semiconductor memory device shown in FIG. 1 along the stacking direction. FIG. 3 is a schematic diagram showing an example of a planar configuration of the semiconductor memory device shown in FIG. 1. FIG. 4 is a schematic diagram showing an example of a cross-sectional configuration of the semiconductor memory device shown in FIG. 1 along the in-plane direction. FIG. 5A is a schematic diagram of a stacking cross section illustrating a step of a method for manufacturing the semiconductor memory device shown in FIG. 1. FIG. 5B is a schematic diagram of a horizontal cross section illustrating a step shown in FIG. 5A. FIG. 6A is a schematic diagram of a stacking cross section illustrating a step subsequent to FIG. 5A. FIG. 6B is a schematic diagram of a horizontal cross section illustrating a step shown in FIG. 6A. FIG. 7A is a schematic diagram of a stacking cross section illustrating a step subsequent to FIG. 6A. FIG. 7B is a schematic diagram of a horizontal cross section illustrating a step shown in FIG. 7A. FIG. 8A is a schematic diagram of a stacking cross section illustrating a step subsequent to FIG. 7A. FIG. 8B is a schematic diagram of a horizontal cross section illustrating a step shown in FIG. 8A. FIG. 9A is a schematic view of a stacked layer cross section illustrating a step subsequent to FIG. 8A . FIG. 9B is a schematic view of a horizontal cross section illustrating a step shown in FIG. 9A . FIG. 10A is a schematic view of a stacked layer cross section illustrating a step subsequent to FIG. 9A . FIG. 10B is a schematic view of a horizontal cross section illustrating a step shown in FIG. 10A . FIG. 11A is a schematic view of a stacked layer cross section illustrating a step subsequent to FIG. 10A . FIG. 11B is a schematic view of a horizontal cross section illustrating a step shown in FIG. 11A . FIG. 12 is a schematic view showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a first modified example of the first embodiment of the present disclosure. FIG. 13 is a schematic view showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a second modified example of the first embodiment of the present disclosure. FIG. 14 is a schematic view showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a third modified example of the first embodiment of the present disclosure. FIG. 15A is a schematic view showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a fourth modified example of the first embodiment of the present disclosure. Fig. 15B is a schematic diagram showing an example of a cross-sectional configuration along an in-plane direction of the semiconductor memory device shown in Fig. 15A. Fig. 16 is a schematic diagram showing an example of a cross-sectional configuration along a stacking direction of a semiconductor memory device according to a fifth modification of the first embodiment of the present disclosure.17 is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a second embodiment of the present disclosure. FIG. 18 is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to a first modified example of the second embodiment of the present disclosure. FIG. 19 is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to another first modified example of the present disclosure. FIG. 20A is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to another second modified example of the present disclosure. FIG. 20B is a schematic diagram showing an example of a cross-sectional configuration along the in-plane direction of the semiconductor memory device shown in FIG. 20A. FIG. 21 is a schematic diagram showing an example of a cross-sectional configuration along the stacking direction of a semiconductor memory device according to another third modified example of the present disclosure.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiment described below is a specific example of the present disclosure, and the technology according to the present disclosure is not limited to the following aspects. Furthermore, the arrangement, dimensions, dimensional ratios, etc. of each component of the present disclosure are not limited to the aspects shown in the drawings.

[0012] The description will be given in the following order: 1. First embodiment 1.1. Overview 1.2. Configuration example 1.3. Manufacturing method 1.4. Actions and effects 1.5. Modifications 2. Second embodiment 2.1. Configuration example 2.2. Actions and effects 2.3. Modifications 3. Other modifications

[0013] 1. First Embodiment [1.1. Overview] First, an overview of a semiconductor memory device 100 according to a first embodiment of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an example of an equivalent circuit of the semiconductor memory device 100 according to this embodiment.

[0014] As shown in FIG. 1, the semiconductor memory device 100 according to this embodiment includes a capacitor C for storing information and a transistor T for controlling whether the capacitor C is selected or not.

[0015] The capacitor C is a ferroelectric capacitor including a first electrode, a second electrode, and a ferroelectric film sandwiched between the first and second electrodes. The capacitor C can store one bit of information depending on the direction of remanent polarization of the ferroelectric film. The capacitor C is electrically connected to the source line SL at the first electrode and to the source of the transistor T at the second electrode.

[0016] The transistor T is a field effect transistor that controls the application of voltage to the capacitor C. The source of the transistor T is electrically connected to the other electrode of the capacitor C, and the drain is electrically connected to the bit line BL. The gate of the transistor T is also electrically connected to the word line WL, so that the state of the channel can be controlled by the voltage applied from the word line WL.

[0017] When writing information to the capacitor C, in the semiconductor memory device 100, a voltage is first applied to the word line WL, causing the channel of the transistor T to transition to an ON state. Then, a potential is applied to each of the source line SL and the bit line BL, causing an electric field corresponding to the information to be written to be applied to the ferroelectric film of the capacitor C. This allows the semiconductor memory device 100 to write information to the capacitor C by controlling the direction of the remanent polarization of the ferroelectric film of the capacitor C with an external electric field.

[0018] On the other hand, when reading information from the capacitor C, in the semiconductor memory device 100, a voltage is first applied to the word line WL, causing the channel of the transistor T to transition to an ON state. Then, a predetermined potential is applied to each of the source line SL and the bit line BL, causing the polarization direction of the ferroelectric film of the capacitor C to transition to a predetermined direction. At this time, the magnitude of the current flowing into the capacitor C during the transition varies depending on the polarization direction of the ferroelectric film before the transition. Therefore, the semiconductor memory device 100 can read the information stored in the capacitor C by measuring the magnitude of the current flowing into the capacitor C.

[0019] The semiconductor memory device 100 can operate as an FeRAM (Ferroelectric Random Access Memory) that stores information in a capacitor C including a ferroelectric film.

[0020] [1.2. Configuration Example] Next, a specific configuration example of the semiconductor memory device 100 according to this embodiment will be described with reference to FIGS. 2 to 4. FIG. 2 shows an example of a cross-sectional configuration of the semiconductor memory device 100 taken along the stacking direction. FIG. 3 shows an example of a planar configuration of the semiconductor memory device 100. FIG. 4 is an enlarged in-plane cross-sectional view of a portion of the semiconductor memory device 100. Note that in FIG. 3, in order to clarify the arrangement of each component, the insulating films Z1 and Z2 formed over the entire surface of the semiconductor substrate 2, which will be described later, are omitted. The cross-sectional view of FIG. 2 shows a cross-section taken along line II-II in FIG. 3 as viewed from the arrow. Note that in this specification, the direction along the plane on which the semiconductor substrate 2 extends is referred to as the in-plane direction, and the direction perpendicular to the in-plane direction is referred to as the height direction or stacking direction. Furthermore, FIG. 4 shows a cross-section taken along line II-II in FIG. 2 taken along the in-plane direction. In FIGS. 2 to 4, the in-plane direction is the XY plane, and the height direction (stacking direction) is the Z-axis direction.

[0021] 2, the semiconductor memory device 100 includes a semiconductor substrate 2, a first interconnection 4, a second interconnection 5, a contact plug 10, a capacitor 20 serving as a capacitor C, and an insulating film 24. The second interconnection 5 is provided on the opposite side of the capacitor 20 from the semiconductor substrate 2 in the Z-axis direction, and is electrically connected to an upper electrode film 23 (described later) of the capacitor 20.

[0022] The semiconductor substrate 2 is made of a semiconductor material and extends along the XY plane. The semiconductor substrate 2 may be a silicon substrate or a silicon substrate with SiO ２ The semiconductor substrate 2 may be an SOI (Silicon On Insulator) substrate sandwiching an insulating film such as silicon dioxide or silicon nitride. The semiconductor substrate 2 may also be a substrate formed of other semiconductor elements such as germanium, or a substrate formed of a compound semiconductor such as GaAs (gallium arsenide), GaN (gallium nitride), or SiC (silicon carbide).

[0023] The semiconductor substrate 2 is provided with, for example, a plurality of thin film transistors 1 as a plurality of transistors T, and an element isolation layer 3. The element isolation layer 3 is made of an insulating material and electrically isolates the plurality of thin film transistors 1 provided in the active region of the semiconductor substrate 2. The element isolation layer 3 can be made of an insulating material such as SiOx (silicon oxide), SiNx (silicon nitride), or SiON (silicon oxynitride).

[0024] For example, the element isolation layer 3 can be formed by using an STI (Shallow Trench Isolation) method to remove a portion of the semiconductor substrate 2 in a predetermined region by etching or the like, and then filling the opening formed by etching or the like with SiOx (silicon oxide). Alternatively, the element isolation layer 3 may be formed by thermally oxidizing a predetermined region of the semiconductor substrate 2 by a LOCOS (Local Oxidation of Silicon) method.

[0025] The region isolated from the surroundings by the element isolation layer 3 becomes an active region in which the thin film transistor 1 is provided. Into the active region, for example, a first conductivity type impurity (for example, a p-type impurity such as boron (B) or aluminum (Al)) is introduced.

[0026] A plurality of thin film transistors 1 are provided near the surface of a semiconductor substrate 2. As shown in Fig. 2, the thin film transistor 1 is a MOS (Metal Oxide Semiconductor)-FET (Field-Effect Transistor) including, for example, a gate electrode 1G, a sidewall insulating film 1W, a gate insulating film 1Z, a drain region 1D, and a source region 1S.

[0027] The gate insulating film 1Z is made of an insulating material and is provided on the active region of the semiconductor substrate 2. The gate insulating film 1Z may be made of an insulating material known as a gate insulating film for a field effect transistor. For example, the gate insulating film 1Z may be made of an oxide such as silicon oxide (SiOx).

[0028] The gate electrode 1G is made of a conductive material and is provided on the gate insulating film 1Z. Specifically, the gate electrode 1G extends, for example, in a diagonal direction (hereinafter referred to as the first direction) relative to the plane of the paper in FIG. 3. The gate electrode 1G extends in the first direction beyond the element isolation layer 3 and is provided so as to span multiple active regions, thereby forming a word line WL (FIG. 1) that electrically connects the gates of multiple thin film transistors 1.

[0029] The gate electrode 1G may be formed of, for example, polysilicon or the like, or may be formed of a metal, alloy, metal compound, or alloy of a metal (such as Ni) and polysilicon, i.e., a so-called silicide. Specifically, the gate electrode 1G may be formed of a laminated structure of a metal layer made of TiN or TaN and a polysilicon layer provided on the gate insulating film 1Z. Such a laminated structure allows the gate electrode 1G to have a lower wiring resistance than when it is formed of only a polysilicon layer.

[0030] The drain region 1D and the source region 1S are second conductivity type regions formed in the semiconductor substrate 2. Specifically, the drain region 1D and the source region 1S are provided so as to face each other with the gate electrode 1G interposed therebetween. The drain region 1D and the source region 1S are formed, for example, by doping a second conductivity type impurity (e.g., an n-type impurity such as phosphorus (P) or arsenic (As)) into an active region of the semiconductor substrate 2. Furthermore, a silicide layer 6 is formed in each of the drain region 1D and the source region 1S on a portion of the surface 2FS of the semiconductor substrate 2.

[0031] The drain region 1D is electrically connected to a first wiring 4, e.g., a bit line BL (FIG. 1), via a contact plug 10. The source region 1S is electrically connected to a second wiring 5, e.g., a source line SL (FIG. 1), via a capacitor 20.

[0032] The sidewall insulating film 1W is made of an insulating material and is provided as a sidewall on the side surface of the gate electrode 1G. The sidewall insulating film 1W can be formed by uniformly depositing an insulating film in a region including the gate electrode 130 and then vertically anisotropically etching the insulating film. For example, the sidewall insulating film 1W can be made of silicon oxide (SiO ｘ ), silicon nitride (SiN ｘ ), or may be formed in a single layer or multiple layers of an insulating oxynitride such as silicon oxynitride (SiON).

[0033] 2, an insulating film Z1 and an insulating layer Z2 are stacked in this order on the thin film transistor 1. The insulating films Z1 and Z2 are, for example, silicon oxide films.

[0034] As shown in FIG. 2 , the contact plug 10 is a columnar member extending in the Z-axis direction, penetrating the insulating film Z1, from the height position of the surface 2FS of the semiconductor substrate 2 to the height position of the upper surface of the insulating film Z1. The contact plug 10 is located between the semiconductor substrate 2 and the first wiring 4 in the Z-axis direction and electrically connects the thin-film transistor 1 and the first wiring 4. As shown in FIGS. 2 to 4 , the contact plug 10 includes, for example, a substantially cylindrical conductor layer 11 and a substantially cylindrical barrier metal layer 12 surrounding the conductor layer 11. The conductor layer 11 may be made of a conductive material such as W (tungsten) or polysilicon. The barrier metal layer 12 may be made of a metal material such as Ti (titanium), TiN (titanium nitride), or Ru (ruthenium).

[0035] As shown in FIG. 2 , the lower end of the contact plug 10 contacts the silicide layer 6 provided in the drain region 1D. An upper end 10UT of the contact plug 10, opposite the semiconductor substrate 2, contacts, for example, the lower surface of the first interconnect 4. The first interconnect 4 is provided at the same level as the insulating film Z2. The first interconnect 4 includes, for example, a barrier layer 4A and a buried layer 4B. The barrier layer 4A can be composed of, for example, a single element selected from Co (cobalt), W (tungsten), Mo (molybdenum), Ru (ruthenium), Ta (tantalum), and Cu (copper), or a compound containing at least one of these elements. The buried layer 4B can be composed of a conductive material containing Cu (copper) and Ru (ruthenium).

[0036] As shown in FIGS. 2 and 4 , the capacitor 20 has a stacked structure of a lower electrode film 21, a ferroelectric film 22, and an upper electrode film 23. The ferroelectric film 22 is sandwiched between the lower electrode film 21 and the upper electrode film 23. The capacitor 20 includes a hole 20H dug in the Z-axis direction. An insulating film 24 is provided in the hole 20H. The lower electrode film 21 has a first recess 21U. The ferroelectric film 22 is provided along the inner surface of the first recess 21U and has a second recess 22U. The second electrode film 23 is provided along the inner surface of the second recess 22U and has a third recess 23U. The inner surface of the third recess 23U forms the hole 20H. In the stacked structure of the lower electrode film 21, the ferroelectric film 22, and the upper electrode film 23, the lower electrode film 21, the ferroelectric film 22, and the upper electrode film 23 are stacked in a direction intersecting the inner surface of the hole 20H. The laminated structure has a bottom portion B20 and a cylindrical sidewall portion W20 standing on the bottom portion B20. The second wiring 5 is electrically connected to the upper electrode film 23 that constitutes the sidewall portion W20.

[0037] The lower electrode film 21 may be made of a conductive material such as W (tungsten) or polysilicon. The material of the lower electrode film 21 may be the same as the material of the conductive layer 11. The material of the ferroelectric film 22 may be HfO ２The upper electrode film 24 may be made of a ferroelectric material containing at least one of hafnium oxide (HfO), silicon (Si), zirconium (Zr), lanthanum (La), niobium (Nb), yttrium (Y), germanium (Ge), and scandium (Sc). The ferroelectric film 22 may also be made of lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), or BLT. The upper electrode film 24 may be made of a metal material such as titanium (Ti), titanium nitride (TiN), or ruthenium (Ru).

[0038] The capacitor 20 extends in the Z-axis direction, penetrating the insulating film Z1, from the surface 2FS of the semiconductor substrate 2 to the upper surface of the insulating film Z1. Therefore, in the example of FIG. 2 , the height of the upper end 10UT of the contact plug 10 and the height of the upper end 20UT of the capacitor 20 are substantially the same. However, the present disclosure is not limited to this, and the height of the upper end 10UT of the contact plug 10 and the height of the upper end 20UT of the capacitor 20 may be different. The capacitor 20 electrically connects the thin-film transistor 1 and the second wiring 5. The lower electrode film 21 located at the lower end of the capacitor 20 is in contact with the silicide layer 6 provided in the source region 1S. The upper end of the capacitor 20 abuts against the lower surface of the second wiring 5. The second wiring 5 is provided at the same level as the insulating film Z2. The second wiring 5 includes, for example, a barrier layer 5A and a buried layer 5B. The barrier layer 5A can be composed of, for example, a single element selected from Co (cobalt), W (tungsten), Mo (molybdenum), Ru (ruthenium), Ta (tantalum), and Cu (copper), or a compound containing at least one of these elements. The buried layer 5B can be composed of a conductive material containing Cu (copper) and Ru (ruthenium). The material of the barrier layer 5A may be the same as the material of the barrier layer 4A. The material of the buried layer 5B may be the same as the material of the buried layer 4B.

[0039] In the semiconductor memory device 100, the width of the capacitor 20 in the X-axis direction is preferably equal to or less than the width of the second wiring 5. This makes it possible to realize a more compact configuration.

[0040] The insulating film 24 is provided in the region surrounded by the inner surface of the hole 20H and the second wiring 5 so as to contact the inner surface of the hole 20H and the second wiring 5. The insulating film 24 may be filled without gaps in the region surrounded by the inner surface of the hole 20H and the second wiring 5. The material of the insulating film 24 may be the same as the material of the insulating film Z1 provided around the capacitor 20, or may be different from the material of the insulating film Z1. The insulating film 24 is preferably made of an insulating material that can be deposited by an ALD (Atomic Layer Deposition) apparatus, for example. Specifically, the insulating film 24 may be made of SiO ２ silicon oxides such as Al ２ O ３ Aluminum oxides such as HfO ２ Hafnium oxides such as ZrO ２ Zirconium oxide films such as Ta ２ O ５ Examples of the insulating film 24 that fills the hole 20H include a tantalum oxide film such as tantalum nitride, and a silicon nitride film such as SiN. Note that the insulating film 24 that fills the hole 20H may be a mixture of a plurality of types of insulating materials.

[0041] [1.3. Manufacturing Method] Next, a manufacturing method of the semiconductor memory device 100 according to this embodiment will be described with reference to FIGS. 5A to 11B. FIGS. 5A to 11B are cross-sectional schematic views illustrating a step in the manufacturing method of the semiconductor memory device 100. In particular, FIGS. 5A, 6A, 7A, 8A, 9A, 10A, and 11A are XZ cross-sectional schematic views, and FIGS. 5B, 6B, 7B, 8B, 9B, 10B, and 11B are XY cross-sectional schematic views. FIG. 5A shows an XZ cross-section taken along line VA-VA in FIG. 5B, and FIG. 5B shows an XY cross-section taken along line VB-VB in FIG. 5A. FIG. 6A shows an XZ cross-section taken along line VIA-VIA in FIG. 6B, and FIG. 6B shows an XY cross-section taken along line VIB-VIB in FIG. 6A. Fig. 7A shows an XZ cross section taken along line VIIA-VIIA shown in Fig. 7B, and Fig. 7B shows an XY cross section taken along line VIIB-VIIB shown in Fig. 7A. Fig. 8A shows an XZ cross section taken along line VIIIA-VIIIA shown in Fig. 8B, and Fig. 8B shows an XY cross section taken along line VIIIB-VIIIB shown in Fig. 8A. Fig. 9A shows an XZ cross section taken along line IXA-IXA shown in Fig. 9B, and Fig. 9B shows an XY cross section taken along line IXB-IXB shown in Fig. 9A. Fig. 10A shows an XZ cross section taken along line XA-XA shown in Fig. 6B, and Fig. 10B shows an XY cross section taken along line XB-XB shown in Fig. 10A. 11A shows an XZ cross section taken along line XIA-XIA shown in FIG. 11B, and FIG. 11B shows an XY cross section taken along line XIB-XIB shown in FIG. 11A.

[0042] 5A, an element isolation layer 3 is formed on a semiconductor substrate 2. Specifically, after preparing a semiconductor substrate 2 made of Si, an SiO ２ Then, a Si film is formed by low pressure CVD or the like. ３ N ４ Next, a resist layer patterned to protect the area where the active region is to be formed is formed on the Si substrate. ３ N ４ After forming on the film, SiO ２ Membrane, Si ３ N ４The film and the semiconductor substrate 2 are etched to a depth of 350 nm to 400 nm. ２ The element isolation layer 3 can be formed by depositing SiO and filling the opening formed by etching. ２ For example, a dense SiO ２ High density plasma CVD, which can form a film, may also be used.

[0043] Subsequently, the excess SiO 2 is removed by using CMP (Chemical Mechanical Polishing) or the like. ２ By removing the film, the surface of the semiconductor substrate 2 is planarized. ２ The film is removed by, for example, Si ３ N ４ This may be continued until the film is exposed.

[0044] Furthermore, Si was removed using hot phosphoric acid or the like. ３ N ４ Next, the surface of the region corresponding to the active region of the semiconductor substrate 2 is oxidized to a thickness of about 10 nm to form an oxide film, and then a first conductivity type impurity (e.g., boron (B) or the like) is ion-implanted to convert the semiconductor substrate 2 in the active region AA into a first conductivity type well.

[0045] Furthermore, after depositing a gate insulating film 1Z, a gate electrode 1G is formed on the gate insulating film 1Z.

[0046] Specifically, first, the oxide film covering the surface of the semiconductor substrate 2 is removed using a hydrofluoric acid solution or the like. ２ SiO 2 is formed on the semiconductor substrate 2 by dry oxidation or RTA (Rapid Thermal Anneal) processing using ２ The gate insulating film 1Z is formed to a thickness of 1.5 nm to 10 nm. ２ In addition to that, H ２ / O ２ , N ２ A mixed gas of O or NO may be used. When forming the gate insulating film 1Z, plasma nitridation is used to form SiO ２It is also possible to dope nitrogen into the film.

[0047] Next, SiH ４ Using the gas as a source gas, polysilicon is deposited to a thickness of 50 nm to 150 nm by low-pressure CVD at a deposition temperature of 580° C. to 620° C. Thereafter, the deposited polysilicon is anisotropically etched using the patterned resist as a mask to form the gate electrode 1G. For example, an HBr-based gas or a Cl-based gas can be used for the anisotropic etching.

[0048] Next, a drain region 1D and a source region 1S are formed in the active region of the semiconductor substrate 2. At this time, sidewall insulating films 1W are formed on both side surfaces of the gate electrode 1G.

[0049] Specifically, SiO ２ After depositing a film thickness of 10 nm to 30 nm, Si is deposited by plasma CVD. ３ N ４ is deposited to a thickness of 30 nm to 50 nm to form an insulating film for the sidewalls, and then anisotropic etching is performed on the insulating film for the sidewalls to form sidewall insulating films 1W on both side surfaces of the gate electrode 11G.

[0050] Then, arsenic (As), a second conductivity type impurity, is introduced at 20 keV to 50 keV at a dose of 1 to 2×10 １５ pieces / cm ２ Ion implantation is performed at a concentration of 0.1 to 1.0 V, thereby introducing second conductivity type impurities into both sides of the gate electrode 1G. As a result, a drain region 1D and a source region 1S are formed in the active region on both sides of the gate electrode 1G. The ion-implanted impurities are then activated by RTA (Rapid Thermal Annealing) at 1000°C for 5 seconds, thereby forming the thin-film transistor 1. Note that spike RTA can also be used to activate the introduced impurities and suppress their diffusion.

[0051] Subsequently, an insulating film Z1 is formed over the entire surface of the semiconductor substrate 2 so as to bury the thin film transistor 1. Specifically, a SiO.sub.2 film is formed on the semiconductor substrate 2 on which the thin film transistor 1 is formed by using CVD or the like. ２ After depositing the insulating film Z1, the insulating film Z1 is planarized by, for example, CMP.

[0052] After forming the insulating film Z1, an opening 10K (FIGS. 5A and 5B) is formed through the insulating film Z1. At this time, the silicide layer 6 provided in the drain region 1D is exposed at the bottom of the opening 10K. Next, a contact plug 10 is formed to fill the interior of the opening 10K. To form the contact plug 10, the inner surface of the opening 10K is covered with a barrier metal layer 12, and then a conductor layer 11 is formed to fill the opening 10K covered with the barrier metal layer 12. The barrier metal layer 12 and the conductor layer 11 can be formed, for example, using an ALD (Atomic Layer Deposition) apparatus. After forming the barrier metal layer 12 and the conductor layer 11, excess deposited barrier metal layer 12 and conductor layer 11 are removed by CMP, thereby obtaining a planarized upper surface Z1US of the insulating film Z1 and an upper end 10UT of the contact plug 10.

[0053] Subsequently, an opening 20K is formed through the insulating film Z1 so that the silicide layer 6 provided in the source region 1S is exposed at the bottom of the opening 20K.

[0054] 6A and 6B, a conductive film 21Z is formed along the inner surface 20KS of the opening 20K. At this time, the upper surface Z1US of the insulating film Z1 is also covered with the conductive film 21Z.

[0055] 7A and 7B, the conductive film 21Z covering the upper surface Z1US of the insulating film Z1 is removed. As a result, the lower electrode film 21 having the recess 21U is formed inside the opening 20K. At this time, a portion of the conductive film 21Z covering the vicinity of the upper end of the inner surface 20KS of the opening 20K is removed. As a result, the height position of the upper end 21UT of the lower electrode film 21 becomes lower than the height position of the upper surface Z1US of the insulating film Z1.

[0056] 8A and 8B, a ferroelectric film 22Z is ​​formed along the inner surface 21S of the recess 21U. At this time, the upper surface Z1US of the insulating film Z1 is also covered with the ferroelectric film 22Z. In addition, a recess 22U is formed inside the recess 21U.

[0057] 9A and 9B, a conductive film 23Z is formed along the inner surface 22S of the recess 22U. At this time, the ferroelectric film 22Z covering the upper surface Z1US of the insulating film Z1 is also covered with the conductive film 23Z. Furthermore, a recess 23U is formed inside the recess 22U.

[0058] 10A and 10B, an insulating film 24Z is formed so as to fill the recess 23U. At this time, the conductive film 23Z covering the upper surface Z1US of the insulating film Z1 is also covered with the insulating film 24Z.

[0059] Next, the ferroelectric film 22Z, the conductive film 23Z, and the insulating film 24Z covering the upper surface Z1US of the insulating film Z1 are removed by CMP. As a result, as shown in FIGS. 11A and 11B, the upper end 10UT of the contact plug 10 is exposed and the upper end 20UT of the capacitor 20 is formed. The ferroelectric film 22 and the upper electrode film 23 are exposed at the upper end 20UT. As a result, the capacitor 20 having the hole 20H filled with the insulating film 24 is completed.

[0060] After the capacitor 20 is formed, an insulating film Z2 is formed so as to cover the insulating film Z1, the contact plug 10, and the capacitor 20, and then the first wiring 4 and the second wiring 5 are formed by, for example, a damascene method.

[0061] Through the above steps, the semiconductor memory device 100 shown in FIG. 2 and other figures can be manufactured.

[0062] [1.4. Effects] In the semiconductor memory device 100, an insulating film 24 is provided in the hole 20H of the capacitor 20. This prevents foreign matter from entering the hole 20H of the capacitor 20 during the manufacturing process after the capacitor 20 is formed, such as during the process of forming the second interconnect 5. Examples of foreign matter include abrasives and metal powder. While the inclusion of such foreign matter may degrade the characteristics of the capacitor, the semiconductor memory device 100 of this embodiment can prevent such deterioration of characteristics.

[0063] [1.5. Modifications] (Modification 1-1) A semiconductor memory device 100A according to a first modification (Modification 1-1) of the first embodiment of the present disclosure will be described with reference to Fig. 12. Fig. 12 is a schematic diagram showing an example cross-sectional configuration of the semiconductor memory device 100A. Note that Fig. 12 corresponds to Fig. 2, which shows an example cross-sectional configuration of the semiconductor memory device 100 according to the first embodiment.

[0064] In the semiconductor memory device 100, the lower electrode film 21 located at the lower end of the capacitor 20 is directly connected to the silicide layer 6 provided in the source region 1S, but the present disclosure is not limited to this. As in the semiconductor memory device 100A shown in FIG. 12 , the lower electrode film 21 of the capacitor 20 may be connected to the silicide layer 6 through a via 25 and a wiring layer 26 stacked in the Z-axis direction. The via 25 and the wiring layer 26 arranged between the thin-film transistor 1 and the capacitor 20 in the Z-axis direction are connection layers connecting the thin-film transistor 1 and the capacitor 20. Furthermore, in the semiconductor memory device 100, the lower end of the contact plug 10 is directly connected to the silicide layer 6 provided in the drain region 1D, but the present disclosure is not limited to this. As in the semiconductor memory device 100A shown in FIG. 12 , the contact plug 10 may be connected to the silicide layer 6 through a via 13 and a wiring layer 14 stacked in the Z-axis direction.

[0065] In the semiconductor memory device 100A of the modified example 1-1, for example, the via 13 and the via 25 are provided in the same layer, and the periphery thereof is filled with the insulating film Z3. Furthermore, in the semiconductor memory device 100A, for example, the wiring layer 14 and the wiring layer 26 are provided in the same layer, and the periphery thereof is filled with the insulating film Z4. Also in the semiconductor memory device 100A of the modified example 1-1, the insulating film 24 and the insulating film Z1 are formed of, for example, SiO ２ The insulating film 24 and the insulating film Z1 may be formed from the same insulating material. In this case, the insulating films Z2 to Z4 may be formed from the same insulating material as the insulating film 24. Although FIG. 12 illustrates an example in which one via 25 and one wiring layer 26 are provided, the present disclosure is not limited to this. For example, a structure in which two or more vias 25 and two or more wiring layers 26 are alternately stacked between the thin-film transistor 1 and the capacitor 20 in the Z-axis direction may be provided. The via 25 may have the same structure as the contact plug 10. Furthermore, the via 25 may be formed simultaneously with the wiring layer 26 using a dual damascene process.

[0066] 13 is a schematic diagram showing an example cross-sectional configuration of a semiconductor memory device 100B according to a second modification (modification 1-2) of the first embodiment of the present disclosure. In the semiconductor memory device 100A of FIG. 12, the lower electrode film 21 located at the lower end of the capacitor 20 is connected to the wiring layer 26, but the present disclosure is not limited to this. For example, as in the semiconductor memory device 100B shown in FIG. 13, the capacitor 20 may be provided directly on the via 25 without the wiring layer 26 interposed therebetween.

[0067] (Variation 1-3) Figure 14 is a schematic diagram showing an example cross-sectional configuration of a semiconductor memory device 100C according to a third variation (variation 1-3) of the first embodiment of the present disclosure. In the semiconductor memory device 100A of Figure 12, the lower electrode film 21 located at the lower end of the capacitor 20 is connected to the wiring layer 26, but the present disclosure is not limited to this. For example, as in the semiconductor memory device 100C shown in Figure 14, a via 31 may be provided on the wiring layer 26, and the capacitor 20 may be formed so as to contact the upper end of the via 31. Note that the via 31 may have a structure similar to that of the contact plug 10. The periphery of the via 31 is filled with an insulating film Z5.

[0068] (Variation 1-4) A semiconductor memory device 100D according to a fourth variation (variation 1-4) of the first embodiment of the present disclosure will be described with reference to FIGS. 15A and 15B. FIG. 15A is a schematic diagram illustrating an example cross-sectional configuration of the semiconductor memory device 100D. Note that FIG. 15A corresponds to FIG. 2, which illustrates the example cross-sectional configuration of the semiconductor memory device 100 according to the first embodiment. Also, FIG. 15B is an enlarged in-plane cross-sectional view of a portion of the semiconductor memory device 100D, illustrating a cross section along line XV-XV in FIG. 15A. Note that FIG. 15B corresponds to FIG. 4, which illustrates the example cross-sectional configuration of the semiconductor memory device 100 according to the first embodiment.

[0069] As shown in FIGS. 15A and 15B , in the semiconductor memory device 100D of modification 1-4, the lower electrode film 21 has an electrode bottom portion B21 including an electrode bottom surface B21S, and a cylindrical electrode wall portion W21. The electrode wall portion W21 stands on the electrode bottom portion B21 and includes an electrode inner wall surface W21S1 and an electrode outer wall surface W21S2. Furthermore, a ferroelectric film 22 and an upper electrode film 23 are stacked so as to cover the electrode bottom surface B21S, the electrode inner wall surface W21S1, and the electrode outer wall surface W21S2. The semiconductor memory device 100B further has an insulating film 27 located between the insulating film Z1 and the capacitor 20 and covering the outer surface of the capacitor 20. The insulating film 27 can be formed using the same type of constituent material as the insulating film 24.

[0070] According to the semiconductor memory device 100D of variant 1-4, the effective overlap area of ​​the lower electrode film 21, the ferroelectric film 22, and the upper electrode film 23 is increased compared to the semiconductor memory device 100 of the first embodiment, thereby obtaining a larger capacitance.

[0071] Also in the semiconductor memory device 100D of the modification 1-4, the insulating films 24 and 27 and the insulating film Z1 are made of, for example, SiO ２ In this case, the insulating films 24 and 27 and the insulating film Z1 may be formed together. Furthermore, the insulating films Z2 to Z4 may be formed from the same insulating material as the insulating films 24 and 27.

[0072] (Variation 1-5) FIG. 16 is a schematic diagram illustrating an example cross-sectional configuration of a semiconductor memory device 100E according to a fifth variation (variation 1-5) of the first embodiment of the present disclosure. In the semiconductor memory device 100D of FIGS. 15A and 15B, the lower electrode film 21 located at the lower end of the capacitor 20 is connected to the wiring layer 26, but the present disclosure is not limited to this. For example, as in the semiconductor memory device 100E shown in FIG. 16, a via 31 may be provided on the wiring layer 26, and the capacitor 20 may be formed so as to contact the upper end of the via 31. The via 31 may have a structure similar to that of the contact plug 10. The periphery of the via 31 is filled with an insulating film Z5.

[0073] 2. Second Embodiment [2.1. Configuration Example] Next, a semiconductor memory device 200 according to a second embodiment of the present disclosure will be described with reference to Fig. 17. Fig. 17 is a schematic diagram showing a cross-sectional configuration example of the semiconductor memory device 200. Note that Fig. 17 corresponds to Fig. 2 which shows the cross-sectional configuration example of the semiconductor memory device 100 according to the first embodiment.

[0074] 17 , in the semiconductor memory device 200, the stacked structure of the capacitor 20, which is made up of the lower electrode film 21, the ferroelectric film 22, and the upper electrode film 23, further includes a flange portion F20. The flange portion F20 is a portion of the stacked structure of the capacitor 20 that extends in the X-axis direction along the XY plane, starting from the upper end of the sidewall portion W20, i.e., the end of the sidewall portion W20 opposite the bottom portion B20. An insulating film F24 is provided on top of the flange portion F20. Except for the above points, the configuration of the semiconductor memory device 200 is substantially the same as the configuration of the semiconductor memory device 100.

[0075] [2.2. Effects] In the semiconductor memory device 200, since the flange portion F20 is provided, alignment of the second wiring 5 with the upper electrode film 23 is easier when forming the second wiring 5 than in the semiconductor memory device 100 ( FIG. 2 ) of the first embodiment. Furthermore, in the semiconductor memory device 200, the manufacturing process can be simplified compared to when manufacturing the semiconductor memory device 100. This is because the laminated structure can be patterned using the insulating film F24, which is formed simultaneously with the insulating film 24, as a hard mask, and a subsequent planarization process is not required.

[0076] [2.3. Modifications] (Modification 2-1) A semiconductor memory device 200A according to a first modification (Modification 2-1) of the second embodiment of the present disclosure will be described with reference to Fig. 18. Fig. 18 is a schematic diagram showing an example cross-sectional configuration of the semiconductor memory device 200A. Note that Fig. 18 corresponds to Fig. 2, which shows an example cross-sectional configuration of the semiconductor memory device 100 according to the first embodiment.

[0077] 18, the flange portion F20 is formed of a ferroelectric film 22 and an upper electrode film 23. That is, the lower electrode film 21 in the flange portion F20 is removed.

[0078] The semiconductor memory device 200A of Modification 2-1 can also be expected to have the same effects as the semiconductor memory device 200 of the second embodiment (FIG. 17). Furthermore, in the semiconductor memory device 200A of Modification 2-1, the flange portion F20 is thinner than in the semiconductor memory device 200 of the second embodiment (FIG. 17), so that the overall thickness can be reduced.

[0079] 3. Other Modifications The technology according to the present disclosure has been described above using several embodiments and modifications. However, the technology according to the present disclosure is not limited to the above-described embodiments, and various modifications are possible.

[0080] For example, like a semiconductor memory device 100F shown in FIG. 19, the capacitor 20 may be connected to the second wiring 5 at a position other than the upper end 20UT.

[0081] Furthermore, for example, like a semiconductor memory device 100G shown in FIGS. 20A and 20B, the hole 20H of the capacitor 20 may not be filled with the insulating film 24 but may be a cavity V.

[0082] 21 , the capacitor 20 may be provided to cover the tip of the pillar 28 penetrating the insulating film Z3. The pillar 28 includes, for example, a substantially cylindrical conductive layer 28A and a substantially cylindrical barrier metal layer 28B surrounding the conductive layer 28A. The lower end of the pillar 28 contacts the silicide layer 6 provided in the source region 1S. The upper end 28UT of the pillar 28 opposite the semiconductor substrate 2 contacts the lower electrode film 21 of the capacitor 20. The capacitor 20 has a structure in which a lower electrode film 21, a ferroelectric film 22, and an upper electrode film 23 are stacked in this order to cover the tip of the pillar 28 protruding from the insulating film Z3 in the +Z direction. The upper electrode film 23 is covered with an insulating film 29. The insulating film 29 may be made of the same material as the insulating film 24. The insulating film 29 is surrounded by the insulating film Z1. Furthermore, a second wiring 5 is provided in a layer above the capacitor 20. The second wiring 5 is surrounded by an insulating film Z2. In the semiconductor memory device 100H of Fig. 21, the capacitor 20 is covered with the insulating film 29, so that the capacitor 20 can be protected during the manufacturing process, for example, when the second wiring 5 is formed after the capacitor 20 is formed.

[0083] Terms used throughout this specification and the appended claims should be interpreted as "open-ended" terms. For example, the terms "including" or "including" should be interpreted as "not limited to the manner described as including." The term "having" should be interpreted as "not limited to the manner described as having."

[0084] The terms used in this specification include terms that are used merely for the convenience of description and are not intended to limit the configuration or operation. For example, terms such as "right," "left," "upper," and "lower" merely indicate directions in the drawings to which reference is made. Furthermore, the terms "inner" and "outer" merely indicate directions toward and away from the center of a focused element, respectively. The same applies to similar terms and terms of a similar meaning.

[0085] The technology according to the present disclosure may also be configured as follows. A semiconductor memory device according to the present disclosure having the following configuration has excellent operational reliability. The effects achieved by the technology according to the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described in the present disclosure. <1> A semiconductor memory device comprising: a semiconductor substrate including a thin film transistor and extending along a first surface; a capacitor provided on the semiconductor substrate and connected to the thin film transistor, the capacitor including a hole dug in a first direction intersecting the first surface; and a first insulating film provided in the hole of the capacitor, the capacitor having a stacked structure in which a first electrode film having a first recess, a ferroelectric film provided along an inner surface of the first recess and having a second recess, and a second electrode film provided along the inner surface of the second recess and having a third recess are stacked in a direction intersecting the inner surface of the hole. <2> The semiconductor memory device according to <1> above, further comprising: a wiring layer provided on the opposite side of the semiconductor substrate from the capacitor in the first direction, and electrically connected to the second electrode film, wherein the first insulating film is provided in a region surrounded by the inner surface of the hole and the wiring layer so as to contact the inner surface of the hole and the wiring layer. <3> The semiconductor memory device according to <1> or <2> above, further comprising: a wiring layer provided on the opposite side of the semiconductor substrate from the capacitor in the first direction, and electrically connected to the second electrode film, wherein the first insulating film fills the region surrounded by the inner surface of the hole and the wiring layer without any gaps. <4> The semiconductor memory device according to any one of <1> to <3> above, further comprising: a wiring layer provided on the opposite side of the semiconductor substrate from the capacitor in the first direction, wherein the stacked structure includes a bottom and a cylindrical sidewall portion standing on the bottom, and the wiring layer is electrically connected to the second electrode film constituting the sidewall portion. <5> The semiconductor memory device according to <4>, wherein the stacked structure further includes a flange portion extending in a second direction along the first surface from an upper end of the sidewall portion as a starting point.<6> The semiconductor memory device according to any one of <1> to <5>, further including a wiring layer provided on the opposite side of the semiconductor substrate as seen from the capacitor in the first direction and electrically connected to the second electrode film, wherein the capacitor has a width equal to or less than a width of the wiring layer in a second direction along the first surface. <7> The semiconductor memory device according to any one of <1> to <6>, further including a connection layer arranged between the thin film transistor and the capacitor in the first direction and connecting the thin film transistor and the capacitor. <8> The semiconductor memory device according to any one of <1> to <7>, wherein the first electrode film has an electrode bottom including an electrode bottom surface, and a cylindrical electrode wall portion erected on the electrode bottom and including an electrode inner wall surface and an electrode outer wall surface, wherein the ferroelectric film and the second electrode film are stacked so as to cover the electrode bottom surface, the electrode inner wall surface, and the electrode outer wall surface. <9> The semiconductor memory device according to any one of <1> to <8> above, further comprising an interlayer insulating film provided around the capacitor, wherein a constituent material of the first insulating film is different from a constituent material of the interlayer insulating film. <10> The semiconductor memory device according to any one of <1> to <9> above, further comprising an interlayer insulating film provided around the capacitor, wherein a constituent material of the first insulating film is the same as a constituent material of the interlayer insulating film. <11> The semiconductor memory device according to any one of <1> to <10> above, further comprising: an interlayer insulating film provided around the capacitor; and a second insulating film located between the interlayer insulating film and the capacitor and covering an outer surface of the capacitor. <12> The first insulating film is made of SiO. ２ , Al ２ O ３ , HfO ２ , ZrO ２ , Ta ２ O ５ , and SiN. ２ The semiconductor memory device according to any one of <1> to <12> above,

[0086] This application claims priority based on Japanese Patent Application No. 2023-192285, filed on November 10, 2023, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0087] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor memory device comprising: a semiconductor substrate including a thin film transistor and extending along a first surface; a capacitor provided on the semiconductor substrate and connected to the thin film transistor, the capacitor including a hole dug in a first direction intersecting the first surface; and a first insulating film provided in the hole of the capacitor, wherein the capacitor has a layered structure in which a first electrode film having a first recess, a ferroelectric film provided along the inner surface of the first recess and having a second recess, and a second electrode film provided along the inner surface of the second recess and having a third recess are stacked in a direction intersecting the inner surface of the hole.

2. The semiconductor memory device according to claim 1, further comprising a wiring layer provided on the opposite side of the semiconductor substrate from the capacitor in the first direction and electrically connected to the second electrode film, wherein the first insulating film is provided in a region surrounded by the inner surface of the hole and the wiring layer so as to contact both the inner surface of the hole and the wiring layer.

3. The semiconductor memory device according to claim 1, further comprising a wiring layer provided on the opposite side of the semiconductor substrate from the capacitor in the first direction and electrically connected to the second electrode film, wherein the first insulating film fills the area surrounded by the inner surface of the hole and the wiring layer without any gaps.

4. A semiconductor memory device as described in claim 1, further comprising a wiring layer provided on the opposite side of the semiconductor substrate as viewed from the capacitor in the first direction, the laminated structure including a bottom and a cylindrical sidewall portion erected on the bottom, and the wiring layer being electrically connected to the second electrode film constituting the sidewall portion.

5. The semiconductor memory device according to claim 4, wherein said laminated structure further includes a flange portion extending in a second direction along said first surface from an upper end of said sidewall portion as a starting point.

6. The semiconductor memory device according to claim 1, further comprising a wiring layer provided on the opposite side of the semiconductor substrate from the capacitor in the first direction and electrically connected to the second electrode film, wherein in a second direction along the first surface, the capacitor has a width equal to or smaller than the width of the wiring layer.

7. The semiconductor memory device according to claim 1, further comprising a connection layer disposed between said thin film transistor and said capacitor in said first direction, connecting said thin film transistor and said capacitor.

8. The semiconductor memory device according to claim 1, wherein the first electrode film has an electrode bottom including an electrode bottom surface, and a cylindrical electrode wall portion standing on the electrode bottom and including an electrode inner wall surface and an electrode outer wall surface, and the ferroelectric film and the second electrode film are laminated so as to cover the electrode bottom surface, the electrode inner wall surface, and the electrode outer wall surface.

9. The semiconductor memory device according to claim 1, further comprising an interlayer insulating film provided around the capacitor, the first insulating film being made of a material different from that of the interlayer insulating film.

10. The semiconductor memory device according to claim 1, further comprising an interlayer insulating film provided around the capacitor, the first insulating film and the interlayer insulating film being made of the same material.

11. The semiconductor memory device according to claim 1, further comprising: an interlayer insulating film provided around the capacitor; and a second insulating film located between the interlayer insulating film and the capacitor, covering an outer surface of the capacitor.

12. The first insulating film is made of SiO ２ , Al ２ O ３ , HfO ２ , ZrO ２ , Ta ２ O ５ The semiconductor memory device according to claim 1 , comprising at least one of the following: SiO 2 , and SiN.

13. The ferroelectric film is HfO ２ The semiconductor memory device according to claim 1 ,