Super junction silicon carbide semiconductor device and method for manufacturing super junction silicon carbide semiconductor device

Abstract

This super junction silicon carbide semiconductor device comprises: a silicon carbide semiconductor substrate (1); a first semiconductor layer (17) of a first conductivity type; a parallel pn region (21) in which a first column region (4) of the first conductivity type and a second column region (3) of a second conductivity type are alternately arranged repeatedly; a second semiconductor layer (5) of the first conductivity type; a first semiconductor region (7) of the first conductivity type; a trench (16); a gate electrode (10); a first electrode (12); and a second electrode (18). A second semiconductor region (19) of the second conductivity type which is doped with impurities of the second conductivity type is provided in the first semiconductor layer (1) on the bottom surface of the second column region (3) so as to be in contact with the second column region (3). At the boundary between the second semiconductor region (19) and the second column region (3), the concentration of the impurities of the second conductivity type has a concentration spike that decreases to 1 / 10 or less with respect to the maximum concentration of the impurities of the second conductivity type in the second semiconductor region (19).

Description

Super-junction silicon carbide semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to super junction silicon carbide semiconductor devices and methods for manufacturing super junction silicon carbide semiconductor devices.

[0002] Patent Document 1 describes a technology for forming a superjunction structure in a silicon semiconductor MOSFET semiconductor device by burying a reverse conductivity type semiconductor layer in a trench. More specifically, the technology describes a technology for forming a relatively shallow trench in a one conductivity type semiconductor layer, forming a reverse conductivity type impurity region at the bottom of the trench, burying the reverse conductivity type semiconductor layer in the trench to form a substrate with a superjunction structure, and forming an element region having at least one pn junction on the surface of the substrate. Patent Document 2 also describes a similar technology.

[0003] Patent Document 3 describes a technique for forming a superjunction structure in a silicon carbide semiconductor MOSFET semiconductor device by a multi-epi implantation method, in which a relatively thin epitaxial growth layer is formed and dopants are selectively ion-implanted repeatedly into the layer to impart an opposite conductivity type.

[0004] Patent Document 4 describes a technique for forming a superjunction structure in a silicon carbide semiconductor MOSFET semiconductor device by a trench backfilling method, in which a deep trench is formed in a relatively thick epitaxial growth layer and a semiconductor layer of the opposite conductivity type is buried in the trench.

[0005] JP 2011-176157 A JP 2010-045245 A International Publication No. 2020 / 110514 JP 2018-019053 A

[0006] An object of this disclosure is to provide a super junction silicon carbide semiconductor device and a method for manufacturing a super junction silicon carbide semiconductor device that can suppress degradation during conduction of a body diode formed parasitically in a MOSFET and reduce process costs.

[0007] A super-junction silicon carbide semiconductor device according to one aspect of the present disclosure is as follows: A first semiconductor layer of a first conductivity type is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A parallel p-n region is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, in which first column regions of a first conductivity type and second column regions of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. A second semiconductor layer of a second conductivity type is provided on a surface of the parallel p-n region opposite to the silicon carbide semiconductor substrate side. A first semiconductor region of the first conductivity type having an impurity concentration higher than that of the first semiconductor layer is selectively provided within the second semiconductor layer. A gate electrode is provided via a gate insulating film in contact with a portion of the second semiconductor layer and a portion of the first semiconductor region. A first electrode is provided in contact with the first semiconductor region and the second semiconductor layer. A second electrode is provided on a rear surface of the silicon carbide semiconductor substrate. A second semiconductor region of a second conductivity type, which is in contact with the second column region and doped with an impurity of a second conductivity type, is provided in the first semiconductor layer at a bottom surface of the second column region. At the boundary between the second semiconductor region and the second column region, the concentration of the impurity of the second conductivity type has a concentration spike that decreases to 1 / 10 or less of the maximum concentration of the impurity of the second conductivity type in the second semiconductor region.

[0008] The super junction silicon carbide semiconductor device and the method for manufacturing the super junction silicon carbide semiconductor device according to the present disclosure have the advantage of being able to suppress degradation during conduction of the body diode and reduce process costs.

[0009] FIG. 1 is a cross-sectional view showing the cross-sectional structure of an SJ-MOSFET according to an embodiment. FIG. 2 is a cross-sectional view (part 1) that schematically shows an SJ-MOSFET according to an embodiment in a state during manufacture. FIG. 3 is a cross-sectional view (part 2) that schematically shows an SJ-MOSFET according to an embodiment in a state during manufacture. FIG. 4 is a cross-sectional view (part 3) that schematically shows an SJ-MOSFET according to an embodiment in a state during manufacture. FIG. 5 is a cross-sectional view (part 4) that schematically shows an SJ-MOSFET according to an embodiment in a state during manufacture. FIG. 6 is a cross-sectional view (part 5) that schematically shows an SJ-MOSFET according to an embodiment in a state during manufacture. FIG. 7 is a cross-sectional view (part 6) that schematically shows an SJ-MOSFET according to an embodiment in a state during manufacture. FIG. 8 is a cross-sectional view (part 7) that schematically shows an SJ-MOSFET according to an embodiment in a state during manufacture. FIG. 9 is a graph showing calculated values ​​of Al concentration profiles in the p-type region of an SJ-MOSFET according to an embodiment. FIG. 10 is a graph showing calculated values ​​of Al and P concentration profiles in the p-type region of an SJ-MOSFET according to an embodiment. Fig. 11 is a graph showing calculated values ​​of Al and Ar concentration profiles in the p-type region of the SJ-MOSFET according to the embodiment. Fig. 12 is an experimental result showing fluctuations in the on-voltage of a conventional SJ-MOSFET. Fig. 13 is a plan view schematically showing the growth of stacking faults in a conventional SJ-MOSFET.

[0010] Overview of Embodiments of the Present Disclosure (1) A super-junction silicon carbide semiconductor device according to one aspect of the present disclosure is as follows: A first semiconductor layer of a first conductivity type is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A parallel p-n region is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate side, in which first column regions of a first conductivity type and second column regions of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. A second semiconductor layer of a second conductivity type is provided on a surface of the parallel p-n region opposite to the silicon carbide semiconductor substrate side. A first semiconductor region of the first conductivity type having an impurity concentration higher than that of the first semiconductor layer is selectively provided within the second semiconductor layer. A gate electrode is provided via a gate insulating film in contact with a portion of the second semiconductor layer and a portion of the first semiconductor region. A first electrode is provided in contact with the first semiconductor region and the second semiconductor layer. A second electrode is provided on a rear surface of the silicon carbide semiconductor substrate. A second semiconductor region of a second conductivity type, which is in contact with the second column region and doped with an impurity of a second conductivity type, is provided in the first semiconductor layer at a bottom surface of the second column region. At the boundary between the second semiconductor region and the second column region, the concentration of the impurity of the second conductivity type has a concentration spike that decreases to 1 / 10 or less of the maximum concentration of the impurity of the second conductivity type in the second semiconductor region.

[0011] According to the above disclosure, after the SJ trench is formed, ions such as p-type impurities are implanted into the bottom of the SJ trench, and defects are introduced into the drift layer (first semiconductor layer of the first conductivity type) by the ion implantation. These defects diffuse during epitaxial growth of the p-type epitaxial layer (third semiconductor layer of the second conductivity type) and spread throughout the drift layer, thereby reducing the lifetime of the drift layer. This makes it possible to suppress degradation of current flow when the body diode is conducting.

[0012] (2) In the above-mentioned (1), the second semiconductor region may be a region in which the first semiconductor layer is doped with the second conductivity type impurity, the second conductivity type impurity and the first conductivity type impurity, or the second conductivity type impurity and a rare gas element.

[0013] (3) In the above (2), the second conductivity type impurity may be aluminum or boron, the first conductivity type impurity may be phosphorus or nitrogen, and the rare gas element may be neon, argon, krypton, or xenon.

[0014] (4) In any one of the above (1) to (3), the second semiconductor region has a compensation concentration of 1×10 16 / cm 3 1x10 or more 17 / cm 3 and the maximum total concentration of the implanted elements is 2 × 10 17 / cm 3 The following may also be used.

[0015] (5) In any one of the above (1) to (4), the second semiconductor region may have a thickness in the range of 0.1 μm to 1 μm.

[0016] (6) In the above-mentioned (1), the gate electrode provided via the gate insulating film may be provided inside a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer.

[0017] According to the above disclosure, it is possible to prevent the p-type region into which ions have been implanted from disappearing due to hydrogen etching during epitaxial growth of the p-type epitaxial layer, and to introduce defects.

[0018] (7) A method for manufacturing a super-junction silicon carbide semiconductor device according to one aspect of this disclosure is as follows: first, a first step of forming a first semiconductor layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate of a first conductivity type is performed; next, a second step of forming an SJ trench in a surface of the first semiconductor layer opposite the silicon carbide semiconductor substrate, the SJ trench not reaching the silicon carbide semiconductor substrate is performed; next, a third step of forming a second semiconductor region of a second conductivity type by ion implanting impurities into the bottom of the SJ trench; next, a fourth step of epitaxially growing a third semiconductor layer of a second conductivity type so as to fill the SJ trench; next, a fifth step of polishing the surface of the third semiconductor layer to leave the third semiconductor layer inside the SJ trench, thereby forming a parallel pn region in the surface of the first semiconductor layer opposite the silicon carbide semiconductor substrate, in which first column regions of a first conductivity type and second column regions of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. Next, a sixth step is performed to form a second semiconductor layer of a second conductivity type on the surface of the parallel pn region opposite the silicon carbide semiconductor substrate. Next, a seventh step is performed to selectively form a first semiconductor region of a first conductivity type having an impurity concentration higher than that of the first semiconductor layer within the second semiconductor layer. Next, an eighth step is performed to form a gate electrode via a gate insulating film in contact with a portion of the second semiconductor layer and a portion of the first semiconductor region. Next, a ninth step is performed to form a first electrode in contact with the first semiconductor region and the second semiconductor layer. Next, a tenth step is performed to form a second electrode on the back surface of the silicon carbide semiconductor substrate.

[0019] (8) In the above (7), the impurities may be impurities of the second conductivity type, impurities of the second conductivity type and impurities of the first conductivity type, or impurities of the second conductivity type and a rare gas element.

[0020] (9) In the above-mentioned (7), the eighth step may also include forming a trench that penetrates the first semiconductor region and the second semiconductor layer and reaches the first semiconductor layer, and forming a gate electrode inside the trench via a gate insulating film.

[0021] <Findings underlying the present disclosure> First, the problems with conventional super-junction silicon carbide semiconductor devices will be described. In a typical n-channel vertical MOSFET, of the multiple semiconductor layers formed in a semiconductor substrate, the n-type conduction layer (drift layer) is the semiconductor layer with the highest resistance. The electrical resistance of this n-type drift layer significantly affects the on-resistance of the entire vertical MOSFET. Reducing the on-resistance of the entire vertical MOSFET can be achieved by reducing the thickness of the n-type drift layer and shortening the current path.

[0022] However, vertical MOSFETs also have the function of maintaining a breakdown voltage by extending the depletion layer to the high-resistance n-type drift layer in the off-state. Therefore, if the n-type drift layer is thinned to reduce the on-resistance, the extension of the depletion layer in the off-state becomes shorter, making it easier to reach a breakdown field strength at a low applied voltage, resulting in a decrease in the breakdown voltage. On the other hand, to increase the breakdown voltage of a vertical MOSFET, the thickness of the n-type drift layer must be increased, which increases the on-resistance. This relationship between on-resistance and breakdown voltage is called a trade-off relationship, and it is generally difficult to improve both of these trade-off relationships. It is known that this trade-off relationship between on-resistance and breakdown voltage also holds true in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), bipolar transistors, and diodes.

[0023] A super junction (SJ) structure is known as a semiconductor device structure that solves the above-mentioned problems (see Patent Documents 3 and 4 mentioned above).

[0024] A MOSFET with a super-junction structure (hereinafter referred to as SJ-MOSFET) is a high-impurity-concentration n + The wafer is made of a silicon carbide semiconductor substrate on which an n-type buffer layer and an n-type drift layer are grown. + A p-type column region that does not reach the n-type silicon carbide semiconductor substrate is provided. + Even if it does not reach the silicon carbide semiconductor substrate, +The silicon carbide semiconductor substrate may be formed by the silicon carbide semiconductor layer.

[0025] The n-type drift layer has a parallel structure (hereinafter referred to as a parallel pn structure) that forms an SJ structure in which p-type regions (p-type column regions) and n-type regions (portions of the n-type drift layer sandwiched between p-type column regions, hereinafter referred to as n-type column regions) that extend in a direction perpendicular to the substrate main surface and have narrow widths in a plane parallel to the substrate main surface are alternately arranged in a plane parallel to the substrate main surface. The parallel pn structure may also be called a parallel pn region. The p-type column regions and n-type column regions that make up the parallel pn structure are regions with increased impurity concentrations corresponding to the n-type drift layer. In the parallel pn structure, by achieving a charge balance such that the amount of impurities contained in the p-type column regions and the n-type column regions, which is the product of the impurity concentration and area, is approximately equal, the depletion layer is expanded in the off state to maintain the breakdown voltage, and a high impurity concentration can be used to achieve both low on-resistance and high breakdown voltage.

[0026] One method for manufacturing super-junction silicon carbide semiconductor devices is the multi-epi implantation method (see Patent Document 3), which combines epitaxial growth and ion implantation to form an SJ structure. However, forming a deep SJ structure for high-voltage devices is costly. This is because deep ion implantation is difficult for silicon carbide semiconductors, and the thermal diffusion of dopants is also small, so the thickness of the epitaxially grown layer per implantation is significantly more limited than for silicon semiconductors. Therefore, a method for forming an SJ structure by forming a deep trench in a relatively thick n-type drift layer and filling it with a p-type epitaxial layer (trench backfilling method) has been proposed (see Patent Document 4).

[0027] Figure 12 shows the experimental results showing the fluctuation of the on-state voltage of a conventional SJ-MOSFET. Three conventional structures, a non-SJ structure, a multi-epi implant, and a trench backfill, are compared. In Figure 12, the horizontal axis represents the current stress of the body diode, in A / cm. 2 The vertical axis indicates the rate of change of the on-state voltage from the initial value, and the unit is %. In this figure, the same structure (e.g., non-SJ structure) and the same current stress value (e.g., 500 A / cm 213 is a plan view of a device showing the growth of stacking faults in a conventional SJ-MOSFET formed by the trench backfilling method, and shows the experimental results of peeling off the surface electrode of a device whose on-state voltage had fluctuated and performing PL (photoluminescence) mapping measurements at the emission wavelength of stacking faults (420 nm).

[0028] In the trench backfilling method, defects due to ion implantation are not introduced into the n-type drift layer when the SJ structure is fabricated, as is the case with the multi-epi implantation method. Therefore, a large amount of carriers are injected when the body diode of the SJ-MOSFET is energized, and the body diode is prone to degradation during energization. For this reason, the inventors of the present application have found that, when formed using the trench backfilling method, stacking faults 126 expand with energization, as shown in FIG. 13, and there is a problem that fluctuations in on-state voltage become large with low energization stress, as shown in FIG. 12. This degradation during energization due to stacking faults is a phenomenon specific to silicon carbide semiconductors. For example, when the current stress in FIG. 12 is 500 A / cm 2 Looking at the data, it can be seen that the fluctuation rate of on-state voltage is greater for trench backfilling (△) than for multi-epi implantation (◯). Furthermore, since a large amount of carriers is injected when the body diode is conducting, there is the issue of larger reverse recovery loss and turn-on loss during switching.

[0029] (Details of the Embodiments) Preferred embodiments of a super-junction silicon carbide semiconductor device and a method for manufacturing a super-junction silicon carbide semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, + and - appended to n or p indicate higher and lower impurity concentrations than layers and regions without these prefixes, respectively. When the notation of n or p including + and - is the same, it indicates that the concentrations are close, including variations, and does not necessarily mean that the concentrations are equivalent. Note that in the following description of the embodiments and the accompanying drawings, similar components are assigned the same reference numerals, and redundant explanations will be omitted. Furthermore, the terms "same" or "equivalent" should preferably be interpreted as including a range of ±5%, taking into account variations in manufacturing.

[0030] A super-junction semiconductor device according to an embodiment that solves the above-mentioned problems will be described below. FIG. 1 is a cross-sectional view showing the cross-sectional structure of an SJ-MOSFET according to an embodiment. A super-junction silicon carbide semiconductor device according to the present disclosure will be described using an SJ-MOSFET 50 as an example. The SJ-MOSFET 50 shown in FIG. 1 is an SJ-MOSFET 50 that includes a MOS (Metal Oxide Semiconductor) gate on the front surface (the surface on the side of a p-type base layer 6, described later) of a semiconductor substrate (silicon carbide substrate: semiconductor chip) made of silicon carbide. FIG. 1 shows only one unit cell (functional unit of an element), and other unit cells adjacent to it are not shown.

[0031] As shown in FIG. 1, an SJ-MOSFET 50 according to the embodiment has n + A drift layer 64 is provided on a first main surface (front surface), for example, a (0001) surface (Si surface) of a silicon carbide substrate (a silicon carbide semiconductor substrate of a first conductivity type) 1. + The silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The drift layer 64 includes an n-type buffer layer (first semiconductor layer of a first conductivity type) 17 that serves as a bulk drift layer 61, and an SJ structure 62 provided on the front surface of the n-type buffer layer 17. The SJ structure 62 includes a p-type column region 3 and an n-type column region 4.

[0032] n-type column region 4 + An n-type heavily doped region 5 is selectively provided in a surface layer on the side opposite to the silicon carbide substrate 1 side. The n-type heavily doped region 5 is + The n-type high-concentration region 5 is a high-concentration n-type drift layer having an impurity concentration lower than that of the silicon carbide substrate 1 and higher than that of the n-type column region 4. The n-type high-concentration region 5 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers.

[0033] The n + A p-type base layer (second semiconductor layer of a second conductivity type) 6 is provided on the surface opposite to the n-type silicon carbide substrate 1 side. + The silicon carbide substrate 1, the bulk drift layer 61, the SJ structure 62, the n-type high concentration region 5, and the p-type base layer 6 constitute a silicon carbide semiconductor base. The n-type buffer layer 17 has a thickness of about 4.4 μm and an impurity concentration of 1.8×10 16 / cm 3 The bulk drift layer 61 is approximately 1000 nm thick.

[0034] A parallel pn structure 21, which becomes the SJ structure 62, is provided in the drift layer 64 of the SJ-MOSFET 50. The parallel pn structure 21 is formed by an n-type column region (first column of a first conductivity type) 4 and a p-type column region (second column of a second conductivity type) 3. + The n-type column regions 4 are alternately arranged in a plane parallel to the front surface of the silicon carbide substrate 1. The n-type column regions 4 are provided so as to extend from the surface of the n-type buffer layer 17 to the high concentration n-type regions 5. The p-type column regions 3 have an impurity concentration of 6×10 16 / cm 3 The n-type column region 4 has an impurity concentration of about 3×10 16 / cm 3 1, the solid line (boundary line) between the n-type buffer layer 17 and the n-type column region 4 means that the n-type impurity concentration of the n-type column region 4 is higher than that of the n-type buffer layer 17. Note that the n-type buffer layer 17 and the n-type column region 4 may be formed of epitaxially grown layers doped with n-type impurities at the same concentration. In this case, the boundary line between the n-type buffer layer 17 and the n-type column region 4 is unnecessary.

[0035] In the embodiment, a p-type region (second semiconductor region of the second conductivity type) 19 is provided in the n-type buffer layer 17 on the bottom surface of the p-type column region 3 so as to be in contact with the p-type column region 3. Although details will be described later, in the embodiment, when forming the SJ structure 62, after the SJ trench 24 (see FIG. 4 ) is formed, the p-type region 19 is formed by ion implantation of, for example, Al into the bottom of the SJ trench 24. The p-type region 19 is formed by implanting Al into the n-type buffer layer 17 containing N, and the impurity concentration of Al is higher than the impurity concentration of N, making it p-type.

[0036] The p-type region 19 introduces ion implantation defects (crystal defects, ion implantation damage) into the drift layer 64. These crystal defects diffuse during epitaxial growth when the SJ structure 62 is formed and the subsequent p-type epitaxial layer 22 (see FIG. 6 ) is formed. These crystal defects extend from the p-type region 19 to at least a portion of the drift layer 64, thereby reducing the lifetime of the drift layer 64. It is particularly important to reduce the lifetime of the n-type buffer layer 17 and the n-type column region 4 adjacent to the p-type region 19. This reduces degradation of the conduction of the body diode during conduction. Furthermore, using the p-type region 19 as the ion implantation region allows the depth of the SJ trench 24 to be shallower, thereby shortening the etching time for the SJ trench 24 and the time required to fill the SJ trench 24 with the p-type epitaxial layer 22. This is expected to reduce process costs. In silicon carbide semiconductors, even if heat treatment is performed after ion implantation of impurities that serve as dopants, the impurities themselves hardly diffuse, but it has been observed that crystal defects (lattice defects) formed by ion implantation diffuse due to heat treatment. Note that Figure 1 does not show the defects caused by ion implantation or their distribution after diffusion.

[0037] Furthermore, as a charge balance of the parallel pn structure 21, the product (amount of impurities) of the width of the p-type column region 3 and the impurity concentration of the p-type column region 3 is approximately equal to the product (amount of impurities) of the width of the n-type column region 4 and the impurity concentration of the n-type column region 4. Specifically, this is set to within ±5%. For this reason, the parallel pn structure 21 is known as a structure that can simultaneously obtain both low on-resistance and high breakdown voltage characteristics.

[0038] As shown in FIG. + A drain electrode (second electrode) 18 is provided on a second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor base) of the silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the drain electrode 18.

[0039] A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate. The SJ-MOSFET 50 includes an n-type high concentration region 5, a p-type base layer 6, an n-type high concentration region 5, a n-type high concentration region 5, a n-type high concentration region 5, a p-type base layer 6, a n-type high concentration region 5, a n-type high concentration region 5, a n-type high concentration region 5, a n-type high concentration region 5, a n-type high concentration region 5, a p ... + type source region 7, p + The semiconductor device has a MOS structure 63 that is composed of a p-type contact region 8, a gate insulating film 9, a gate electrode 10, and a trench 16. Specifically, the trench 16 is formed in the n-type region of the p-type base layer 6. + The gate electrode 10 extends from the surface opposite to the silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor base) through the p-type base layer 6 to reach the n-type high concentration region 5. A gate insulating film 9 is formed on the bottom and side walls of the trench 16 along the inner wall of the trench 16, and a gate electrode 10 is formed inside the gate insulating film 9 within the trench 16. The gate insulating film 9 insulates the gate electrode 10 from the n-type high concentration region 5 and the p-type base layer 6. A portion of the gate electrode 10 may protrude from above the trench 16 toward the source electrode 12, which will be described later.

[0040] The n-type heavily doped region 5 contains a first p + The base region 14 and the second p + The first p-type base regions 15 are selectively provided. + The mold base region 14 covers at least the bottom surface of the trench 16. The bottom corners of the trench 16 are the boundaries between the bottom surface and the sidewalls of the trench 16.+ The n-type base region 15 is provided between the trenches 16 and extends from the surface of the n-type high concentration region 5 on the p-type base layer 6 side to the first p-type + It is provided to the same depth as the mold base region 14 .

[0041] 1st p. + The base region 14 and the second p + The pn junction between the first p-type base region 15 and the n-type column region 4 is formed at a position deeper than the bottom surface of the trench 16 on the drain side. + The base region 14 and the second p + The depth position of the drain side end of the base region 15 is the first p + The base region 14 and the second p + It is sufficient that the pn junction between the first p-type base region 15 and the n-type column region 4 is located deeper on the drain side than the bottom surface of the trench 16, and this can be changed in various ways according to design conditions. + The base region 14 and the second p + The mold base region 15 can prevent a high electric field from being applied to the gate insulating film 9 along the bottom surface of the trench 16 .

[0042] The surface layer of the p-type base layer 6 has an n-type + A p-type source region (first semiconductor region of the first conductivity type) 7 is selectively provided. + A contact region 8 may be provided. + The n-type source region 7 is in contact with the trench 16. + type source region 7 and p + The contact regions 8 are in contact with each other. + "Provided on the surface of the semiconductor layer" refers to a semiconductor region / semiconductor layer provided above the surface of the semiconductor layer, and "provided in the surface layer of the semiconductor layer" refers to a semiconductor region / semiconductor layer provided inside the semiconductor layer and exposed on the surface of the semiconductor layer.

[0043] The interlayer insulating film 11 is provided on the entire first main surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 10 embedded in the trench 16. The source electrode 12 is connected to the n-type silicon carbide semiconductor substrate 10 via a contact hole opened in the interlayer insulating film 11. + The p-type source region 7 and the p-type base layer 6 are in contact with each other. + When the n-type contact region 8 is provided, + type source region 7 and p + The source electrode 12 is in contact with the gate electrode 10 through the gate insulating film 11. The source electrode 12 is made of, for example, a NiSi film. The source electrode 12 is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad (not shown) made of Al or AlSi is provided on the source electrode 12. A barrier metal (not shown) made of, for example, Ti and TiN may be provided between the source electrode 12 and the interlayer insulating film 11 to prevent diffusion of metal atoms from the source electrode 12 toward the gate electrode 10.

[0044] 1, the body diode of the SJ-MOSFET in question is a parasitic pn diode between the p-type base layer 6 and the n-type high concentration region 5. The p-type base layer 6 is + The n-type high concentration region 5 is connected to the source electrode 12 via the n-type contact region 8. The n-type high concentration region 5 is connected to the n-type column region 4, the n-type buffer layer 17, and the n-type + The body diode is connected to the drain electrode 18 via the silicon carbide substrate 1. In the freewheeling mode of the SJ-MOSFET, the potential of the source electrode 12 becomes higher than that of the drain electrode 18, and when the threshold voltage of the body diode is exceeded, current flows and carriers are injected. As described above, part of the current path of the body diode overlaps with the source-drain current path of the SJ-MOSFET, and therefore degradation of the current flow in the body diode leads to degradation of the characteristics of the SJ-MOSFET.

[0045] (Method of Manufacturing Super-Junction Silicon Carbide Semiconductor Device According to an Embodiment) Next, a method of manufacturing a super-junction silicon carbide semiconductor device according to an embodiment will be described. Figures 2 to 8 are cross-sectional views schematically showing states during the manufacturing process of a super-junction silicon carbide semiconductor device according to an embodiment.

[0046] First, n-type single crystal 4H-SiC + A silicon carbide substrate 1 is prepared. + An n-type buffer layer 17 and an n-type drift layer 2 are epitaxially grown in this order on the first main surface of silicon carbide substrate 1. As described above, n-type buffer layer 17 and n-type drift layer 2 are assumed to have slightly different n-type impurity concentrations. The state up to this point is shown in FIG.

[0047] Next, a SiO2 mask 23 having predetermined openings and serving as a trench etching mask is formed by photolithography on the surface of the n-type drift layer 2. The state up to this point is shown in FIG.

[0048] Next, n-type drift layer 2 is formed by dry etching. + An SJ trench 24 is formed that does not reach the silicon carbide substrate 1 and has a depth substantially equal to the film thickness of the n-type drift layer 2. The state up to this point is shown in FIG.

[0049] Next, p-type impurities or the like are ion-implanted into the bottom of the SJ trench 24 to form a p-type region 19. By ion-implanting p-type impurities or the like into the bottom of the SJ trench 24, crystal defects due to the ion implantation are introduced into the n-type buffer layer 17. The state up to this point is shown in FIG. 5 . The elements to be ion-implanted include, for example, Al, Al and n-type impurities (phosphorus (P), nitrogen (N), etc.), and Al and rare gas elements (neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), etc.). In the case of Al and n-type impurities or Al and rare gas elements, the concentration of the ion-implanted elements can be higher than in the case of Al alone, thereby increasing the number of defects. Boron (B) may be used as a p-type impurity instead of Al. In this case, B alone, B and n-type impurities, or B and rare gas elements may also be ion-implanted. The ion implantation temperature is preferably room temperature to prevent the crystal defects due to the ion implantation from being repaired.

[0050] The compensation concentration of the p-type region 19 (difference in concentration between p-type impurities and n-type impurities) is set to the same level as the impurity concentration (1×10 16 / cm 3 1x10 or more17 / cm 3 The maximum total concentration of the ion implantation elements is within the range of 2 × 10 17 / cm 3 If the compensation concentration of the p-type region 19 is higher than this, the JFET resistance increases, and if it is lower than this, there are fewer defects due to ion implantation, and the effect of suppressing degradation due to current flow is reduced.

[0051] The thickness of p-type region 19 is preferably in the range of 0.1 μm to 1 μm, because if p-type region 19 is thinner than this, it will be lost by hydrogen etching during the subsequent epitaxial growth of p-type epitaxial layer 22, and if it is thicker than this, high-acceleration ion implantation will be required, which will increase the cost of implantation.

[0052] Next, the SiO2 mask 23 for trench formation is removed. Next, a p-type epitaxial layer 22 made of silicon carbide is epitaxially grown on the front surface side of the n-type buffer layer 17 while doping it with p-type impurities such as aluminum, and the SJ trench 24 is backfilled with the p-type epitaxial layer 22. The impurity concentration of the p-type epitaxial layer 22 is 1×10 16 1x10 or more 17 / cm 3 The state up to this point is shown in FIG.

[0053] Crystal defects caused by ion implantation diffuse during epitaxial growth and spread into the n-type buffer layer 17, thereby reducing the lifetime of the drift layer and suppressing degradation in conduction when the body diode is conducting.

[0054] Next, the surface of this p-type epitaxial layer 22 is polished, leaving the p-type epitaxial layer 22 inside the SJ trench 24, thereby forming a parallel pn structure 21 consisting of p-type column regions 3 and n-type column regions 4. The p-type epitaxial layer 22 inside the SJ trench 24 becomes the p-type column regions 3, and the region of the n-type drift layer 2 sandwiched between the p-type column regions 3 becomes the n-type column regions 4. This is the meaning behind the 2 → 4 in Figure 7. The state up to this point is shown in Figure 7.

[0055] Next, the first p+ After forming the n-type base region 14, the lower n-type high concentration region 5a made of silicon carbide is epitaxially grown on the front surface side of the n-type drift layer 2 while doping with nitrogen atoms. Next, the lower second p + The n-type base region 15a is formed. An upper n-type high concentration region 5b made of silicon carbide is epitaxially grown thereon while being doped with nitrogen atoms. Next, a second p-type high concentration region 5b is formed thereon by selective ion implantation. + The lower n-type heavily doped region 5a and the upper n-type heavily doped region 5b form the n-type heavily doped region 5. The lower second p + The mold base region 15a and the upper second p + The mold base region 15b is the second p + A mold base region 15 is formed.

[0056] Next, a p-type base layer 6 doped with p-type impurities such as aluminum is formed on the surface of the n-type high concentration region 5. Next, an ion implantation mask having predetermined openings is formed on the surface of the p-type base layer 6 by photolithography, using, for example, an oxide film. N-type impurities such as phosphorus (P) are ion-implanted into this opening, and n-type impurities are implanted into a portion of the surface of the p-type base layer 6. + Next, the n-type source region 7 is formed. + The ion implantation mask used to form the p-type source region 7 is removed, and a new ion implantation mask having a predetermined opening is formed in the same manner, and p-type impurities such as aluminum are ion-implanted into a portion of the surface of the p-type base layer 6, thereby forming p + A contact region 8 may be formed. + The impurity concentration of the p-type contact region 8 is set to be higher than the impurity concentration of the p-type base layer 6 .

[0057] Next, a heat treatment (annealing) is carried out in an inert gas atmosphere at about 1700° C. to form the first p + Mold base region 14, second p + Mold base region 1, n + type source region 7, p +An activation process is then carried out for the mold contact region 8, etc. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or activation may be carried out by performing a heat treatment each time an ion implantation is carried out.

[0058] Next, a trench forming mask having a predetermined opening is formed by photolithography on the surface of the p-type base layer 6, using, for example, an oxide film. Next, a trench 16 is formed by dry etching, penetrating the p-type base layer 6 and reaching the n-type high concentration region 5. The bottom of the trench 16 is connected to the first p-type high concentration region 5 formed in the n-type high concentration region 5. + This may reach the mold base region 14. The trench mask is then removed, as shown in FIG.

[0059] Next, n + A gate insulating film 9 is formed along the surface of the source region 7 and the bottom and sidewalls of the trench 16. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000° C. in an oxygen atmosphere. Alternatively, this gate insulating film 9 may be formed by a deposition method using a chemical reaction such as high temperature oxidation (HTO).

[0060] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon layer may be formed so as to fill the trench 16. This polycrystalline silicon layer is patterned by photolithography and left inside the trench 16 to form the gate electrode 10.

[0061] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm to cover the gate insulating film 9 and the gate electrode 10, forming an interlayer insulating film 11. Next, a barrier metal (not shown) made of titanium (Ti) or titanium nitride (TiN) may be formed to cover the interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography, and n + A contact hole is formed to expose the source region 7. + When the n-type contact region 8 is formed, + type source region 7 and n +A contact hole is formed to expose the source region 7 .

[0062] Next, a conductive film (not shown) is provided in the contact holes and on the interlayer insulating film 11. This conductive film is selectively removed to leave the conductive film only in the contact holes, and n + The source region 7 is brought into contact with the conductive film. + When the n-type contact region 8 is formed, + type source region 7 and p + The mold contact region 8 is brought into contact with a conductive film, which may be nickel silicide, for example, and then a source electrode 12 made of aluminum or the like is provided.

[0063] Next, n + A back electrode made of nickel or the like is provided on the second main surface of the silicon carbide semiconductor substrate 1. After that, a heat treatment is performed in an inert gas atmosphere at about 1000° C. to form an n-type silicon carbide semiconductor substrate. + A drain electrode 18 is formed to form an ohmic junction with the silicon carbide semiconductor substrate 1 .

[0064] Next, an electrode pad to serve as a source electrode pad (not shown) for soldering a terminal is deposited by, for example, sputtering on source electrode 12 on the front surface of the silicon carbide semiconductor substrate and on top of interlayer insulating film 11. In this manner, the super junction silicon carbide semiconductor device shown in FIG.

[0065] 1 shows an example of a trench-structured MOSFET, but in the case of a planar-structured MOSFET in which no trench 16 is formed, the following modifications may be made: an n-type well region is formed in a part of the surface region of the p-type base layer 6, the front surface side of the silicon carbide semiconductor substrate is thermally oxidized to form a gate insulating film 9, the p-type base layer 6 and each region formed on the surface of the p-type base layer 6 are covered with the gate insulating film 9, a polycrystalline silicon layer is formed as a gate electrode 10 on the gate insulating film 9, the polycrystalline silicon layer is patterned and selectively removed, and the n-type well region of the p-type base layer 6 is formed. + An interlayer insulating film 11 is formed to cover the gate electrode 7, leaving the polycrystalline silicon layer on the portion sandwiched between the n-type source region 7 and the n-type well region.

[0066] 9 is a graph showing the results of a simulation (Monte Carlo method) of the Al concentration profile in the p-type region of the SJ-MOSFET according to the embodiment. + The vertical axis indicates the depth from the surface of the contact region 8, and the unit is μm. The vertical axis indicates the impurity concentration of Al, and the unit is cm. -3 As shown in FIG. 9, the impurity concentration of Al at the boundary between the p-type column region 3 and the p-type region 19 is 2×10 15 / cm 3 In other words, at this boundary, the Al impurity concentration drops sharply to the maximum Al concentration in the p-type region 19 (in this example, about 8×10 16 / cm 3 ) or less. This is a structural feature of the SJ-MOSFET manufacturing method according to the embodiment, and occurs because when ions are implanted into the trench bottom, the concentration at the top surface of the trench bottom is low due to the influence of the ion implantation range. The impurity concentrations of the p-type column region 3 and the p-type region 19 are approximately the same, 1×10 16 / cm 3 1x10 or more 17 / cm 3 The following is the result.

[0067] 10 is a graph showing the results of simulating the Al and P concentration profiles in the p-type region of the SJ-MOSFET according to the embodiment. + The vertical axis indicates the depth from the surface of the contact region 8, and the unit is μm. The vertical axis indicates the impurity concentration of Al and P, and the unit is cm. -3 As shown in FIG. 10, the impurity concentration of Al at the boundary between the p-type column region 3 and the p-type region 19 is 2×10 15 / cm 3 9, there is a concentration spike at the boundary between the p-type column region 3 and the p-type region 19. In other words, in FIG. 10, as in FIG. 9, there is a maximum Al concentration in the p-type region 19 (in this example, about 1×10 17 / cm 3 At least a part of the p-type region 19 has a region where both Al and P are implanted.

[0068] The compensation concentration of the p-type column region 3 and the impurity concentration of the p-type region 19 are approximately 1×10 16 / cm 3 1x10 or more 17 / cm 3 To prevent the destruction of the crystal structure during ion implantation, the maximum concentration of the total implanted elements is 2 × 10 17 / cm 3 It is preferable that the following is true: FIG. 10 shows an example of P, but the same is true for N.

[0069] 11 is a graph showing the results of simulating the Al and Ar concentration profiles in the p-type region of the SJ-MOSFET according to the embodiment. + The vertical axis indicates the depth from the surface of the contact region 8, and the unit is μm. The vertical axis indicates the impurity concentration of Al and Ar, and the unit is cm. -3 As shown in FIG. 11, the impurity concentration of Al at the boundary between the p-type column region 3 and the p-type region 19 is 2×10 15 / cm 3 9, there is a concentration spike at the boundary between the p-type column region 3 and the p-type region 19. In other words, in FIG. 11, as in FIG. 9, there is a maximum Al concentration (in this example, about 8×10 16 / cm 3 At least a part of the p-type region 19 has a region where both Al and Ar are implanted.

[0070] The impurity concentrations of the p-type column region 3 and the p-type region 19 are approximately the same, 1×10 16 / cm 3 1x10 or more 17 / cm 3 To prevent the destruction of the crystal structure during ion implantation, the maximum concentration of the total implanted elements is 2 × 10 17 / cm 3 11 shows an example of Ar, but the same applies to the other inert elements (Ne, Kr, Xe).

[0071] As described above, according to the super-junction silicon carbide semiconductor device and the method for manufacturing the super-junction silicon carbide semiconductor device according to the embodiments, after forming the SJ trench, ions of p-type impurities or the like are implanted into the bottom of the SJ trench, and defects due to the ion implantation are introduced into the drift layer. These crystal defects diffuse during epitaxial growth of the p-type epitaxial layer and extend to at least a portion of the drift layer, thereby reducing the lifetime of the drift layer. This reduces degradation of conduction during conduction of the body diode. A structural feature achieved by ion implanting p-type impurities or the like into the bottom of the SJ trench corresponds to a concentration spike at the boundary between the p-type column region 3 and the p-type region 19, where the Al impurity concentration is equal to or less than 1 / 10 of the maximum Al concentration in the p-type region 19.

[0072] The suppression of degradation of the body diode due to conduction will be explained in more detail below. The crystal defects in the p-type region 19 formed by ion implantation also diffuse into the adjacent n-type buffer layer 17 and n-type column region 4, shortening the carrier lifetime in these regions. The main cause of degradation of the body diode due to conduction degradation is the diffusion of minority carriers, i.e., holes, into the n-type buffer layer 17 and n-type column region 4. + When the electrons reach the silicon carbide substrate 1 and reach a certain density, the energy generated by recombination with the electrons causes n + The reason is that stacking faults (basal plane dislocations) remaining in the silicon carbide substrate 1 expand. Even if a large amount of minority carriers (holes) are injected into the n-type column region 4 when the body diode is energized, if there is a region in the n-type buffer layer 17 or the n-type column region 4 where the carrier lifetime is short, the minority carriers (holes) will not be able to pass through the n-type buffer layer 17 or the n-type column region 4. + This prevents the electrons from reaching the n-type silicon carbide substrate 1. + This makes it possible to suppress the spread of stacking faults from the silicon carbide substrate 1 .

[0073] In the above, the present disclosure has been described with reference to an example in which the main surface of a silicon carbide substrate made of silicon carbide is a (0001) plane and a MOS is constructed on the (0001) plane, but this is not limiting and various changes are possible for wide band gap semiconductors, the plane orientation of the substrate main surface, etc. Also, in the embodiments of the present disclosure, a trench MOSFET has been described as an example, but this is not limiting and the present disclosure is applicable to semiconductor devices with various configurations, such as MOS-type semiconductor devices such as planar MOSFETs. Also, FIG. 1 illustrates a so-called semi-SJ structure in which the drift layer 64 is constructed of a bulk drift layer 61 and an SJ structure 62. Alternatively, the bulk drift layer 61 may be omitted and the bottom surface of the p-type region 19 may be n-type. + Alternatively, a full SJ structure in contact with the silicon carbide substrate 1 may be employed.

[0074] INDUSTRIAL APPLICABILITY As described above, the super junction silicon carbide semiconductor device and method for manufacturing a super junction silicon carbide semiconductor device according to the present disclosure are useful for high voltage semiconductor devices used in power conversion devices and power supply devices for various industrial machines and the like.

[0075] 1n + Silicon carbide substrate 2 n-type drift layer 3 p-type column region 4 n-type column region 5 n-type high concentration region 6 p-type base layer 7 n + Type source region 8p + Type contact region 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 12 Source electrode 14 First p + Mold base region 15 2nd p + Type base region 16 Trench 17 N-type buffer layer 18 Drain electrode 19 P-type region 21 Parallel pn structure 22 P-type epitaxial layer 23 SiO2 mask 24 SJ trench 50 SJ-MOSFET 61 Bulk drift layer 62 SJ structure 63 MOS structure 64 Drift layer 126 Stacking fault

Claims

a first semiconductor layer of a first conductivity type provided on a front surface of the silicon carbide semiconductor substrate; a parallel pn region provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate, the parallel pn region having first column regions of a first conductivity type and second column regions of a second conductivity type repeatedly arranged alternately in a plane parallel to the front surface; a second semiconductor layer of a second conductivity type provided on a surface of the parallel pn region opposite to the silicon carbide semiconductor substrate; a first semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor layer selectively provided within the second semiconductor layer; a gate electrode provided via a gate insulating film in contact with a part of the second semiconductor layer and a part of the first semiconductor region; a first electrode in contact with the first semiconductor region and the second semiconductor layer; and a second electrode provided on a rear surface of the silicon carbide semiconductor substrate, a second semiconductor region of a second conductivity type doped with an impurity of a second conductivity type is provided in the first semiconductor layer at a bottom surface of the second column region and in contact with the second column region, and a concentration of the impurity of the second conductivity type at a boundary between the second semiconductor region and the second column region has a concentration spike that is reduced to 1 / 10 or less of a maximum concentration of the impurity of the second conductivity type in the second semiconductor region.

2. The super junction silicon carbide semiconductor device according to claim 1, characterized in that the second semiconductor region is a region formed by doping the first semiconductor layer with impurities of the second conductivity type, impurities of the second conductivity type and impurities of the first conductivity type, or impurities of the second conductivity type and a rare gas element.

3. The superjunction silicon carbide semiconductor device according to claim 2, characterized in that the second conductivity type impurity is aluminum or boron, the first conductivity type impurity is phosphorus or nitrogen, and the rare gas element is neon, argon, krypton or xenon.

4. The second semiconductor region has a compensation concentration of 1×10 16 / cm 3 Above 1 x 10 17 / cm 3 The maximum total concentration of the implanted elements is 2×10 17 / cm 3 2. The super junction silicon carbide semiconductor device according to claim 1, wherein:

5. The super junction silicon carbide semiconductor device according to claim 1, wherein the second semiconductor region has a thickness in the range of 0.1 μm or more and 1 μm or less.

6. The super junction silicon carbide semiconductor device according to claim 1, characterized in that the gate electrode provided via the gate insulating film is provided inside a trench that penetrates the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer.

7. A first step of forming a first semiconductor layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate of a first conductivity type; a second step of forming an SJ trench not reaching the silicon carbide semiconductor substrate from a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a third step of forming a second semiconductor region of a second conductivity type by ion implanting impurities into the bottom of the SJ trench; a fourth step of epitaxially growing a third semiconductor layer of a second conductivity type so as to fill the SJ trench; a fifth step of polishing a surface of the third semiconductor layer and leaving the third semiconductor layer inside the SJ trench to form a parallel pn region in the surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate, in which first column regions of a first conductivity type and second column regions of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface; and a sixth step of forming a second semiconductor layer of a second conductivity type on the surface of the parallel pn region opposite to the silicon carbide semiconductor substrate. a seventh step of selectively forming a first semiconductor region of a first conductivity type, the first semiconductor region having an impurity concentration higher than that of the first semiconductor layer, inside the second semiconductor layer; an eighth step of forming a gate electrode via a gate insulating film in contact with a part of the second semiconductor layer and a part of the first semiconductor region; a ninth step of forming a first electrode in contact with the first semiconductor region and the second semiconductor layer; and a tenth step of forming a second electrode on a back surface of the silicon carbide semiconductor substrate.

8. The method for manufacturing a super junction silicon carbide semiconductor device according to claim 7, wherein the impurities are impurities of the second conductivity type, impurities of the second conductivity type and impurities of the first conductivity type, or impurities of the second conductivity type and a rare gas element.

9. A method for manufacturing a super junction silicon carbide semiconductor device as described in claim 7, characterized in that the eighth step forms a trench penetrating the first semiconductor region and the second semiconductor layer to reach the first semiconductor layer, and forms a gate electrode inside the trench via a gate insulating film.