Chip component

Abstract

This chip component includes a substrate, a first capacitor structure that is formed on the substrate, and a second capacitor structure that is formed on the substrate. The first capacitor structure and the second capacitor structure are electrically connected in parallel to each other. The first capacitor structure is a trench capacitor. For example, the capacitance of the first capacitor structure is higher than the capacitance of the second capacitor structure. The substrate contains a semiconductor. For example, the substrate contains silicon.

Description

Chip parts

[0001] The present disclosure relates to chip components.

[0002] Japanese Patent Application Laid-Open No. 2006-129994 discloses a chip capacitor including a substrate, a first conductive film and a first pad film formed on the substrate, a dielectric film formed on the first conductive film, and a second conductive film formed on the dielectric film and including a second connection region and a second capacitor formation region. The first conductive film includes the first connection region and the first capacitor formation region. A first external electrode is bonded to the first connection region of the first conductive film, and a second external electrode is bonded to the second connection region of the second conductive film.

[0003] Japanese Patent Application Laid-Open No. 2017-195322

[0004] [Summary] The capacitance of a chip capacitor can be set in various ways depending on the application of the chip capacitor.

[0005] An object of the present disclosure is to provide an improved chip component compared to conventional chip components. In particular, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a chip component that allows the capacitance to be set in a variety of ways.

[0006] A chip component provided by a first aspect of the present disclosure includes a substrate, a first capacitor structure formed on the substrate, and a second capacitor structure formed on the substrate. The first capacitor structure and the second capacitor structure are electrically connected in parallel. The substrate has a substrate main surface and a plurality of trenches recessed from the substrate main surface in a first direction. The first capacitor structure is a trench capacitor partially housed in the plurality of trenches.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0008] FIG. 1 is a schematic perspective view showing a chip component according to a first embodiment of the present disclosure. FIG. 2 is a schematic exploded perspective view showing the chip component according to the first embodiment of the present disclosure. FIG. 3 is a schematic partial plan view showing the chip component according to the first embodiment of the present disclosure. FIG. 4 is a circuit diagram showing the chip component according to the first embodiment of the present disclosure. FIG. 5 is a schematic partial enlarged plan view showing the chip component according to the first embodiment of the present disclosure. FIG. 6 is a schematic partial enlarged plan view showing the chip component according to the first embodiment of the present disclosure. FIG. 7 is a schematic partial enlarged plan view showing the chip component according to the first embodiment of the present disclosure. FIG. 8 is a schematic partial cross-sectional view showing the chip component according to the first embodiment of the present disclosure. FIG. 9 is a schematic partial cross-sectional view showing the chip component according to the first embodiment of the present disclosure. FIG. 10 is a schematic partial plan view showing a first modified example of the chip component according to the first embodiment of the present disclosure. FIG. 11 is a schematic partial plan view showing a second modified example of the chip component according to the first embodiment of the present disclosure.

[0009] DETAILED DESCRIPTION Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0010] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." In the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0012] 1 to 9 show a chip component according to a first embodiment of the present disclosure. FIG. 1 is a schematic perspective view of a chip component A1 according to this embodiment. FIG. 2 is a schematic exploded perspective view of the chip component A1. In FIGS. 1 and 2, the longitudinal direction of the rectangular parallelepiped chip component A1 is defined as the second direction x, the width direction of the chip component A1 is defined as the third direction y, and the thickness direction of the chip component A1 is defined as the first direction z.

[0013] The chip component A1 is formed in a rectangular parallelepiped shape. The length along the second direction x may be, for example, 0.4 mm or more and 2 mm or less. The width along the third direction y may be, for example, 0.2 mm or more and 2 mm or less. The thickness along the first direction z may be, for example, 0.05 mm or more and 0.5 mm or less.

[0014] The chip component A1 may be a small electronic component designated by its size (length (mm) along the second direction x) x width (mm) along the third direction y), such as a 1608 (1.6 mm x 0.8 mm) chip, a 1005 (1.0 mm x 0.5 mm) chip, a 0603 (0.6 mm x 0.3 mm) chip, a 0402 (0.4 mm x 0.2 mm) chip, or a 03015 (0.3 mm x 0.15 mm) chip.

[0015] The chip component A1 includes a substrate 1, a first external electrode 2A, and a second external electrode 2B.

[0016] The substrate 1 forms the base of the chip component A1. The chip component A1 is formed by supporting a plurality of insulating films and metal films, etc., stacked on top of each other, on the substrate 1. The substrate 1 has a rectangular parallelepiped shape having approximately the same size as the chip component A1. The substrate 1 has a main surface 11, a rear surface 12, and four side surfaces 13 to 16. The main surface 11 is the so-called front surface of the chip component A1, and the rear surface 12 is the rear surface of the chip component A1. The four side surfaces 13 to 16 surround the main surface 11 in a plan view seen from the z direction (hereinafter simply referred to as "plan view"). The four side surfaces 13 to 16 may include a side surface 13 and a side surface 14 that are separated from each other in the second direction x, and a side surface 15 and a side surface 16 that are separated from each other in the third direction y. In other words, the side surfaces extending parallel to each other along the third direction y may be the substrate side surface 13 and the substrate side surface 14, and the side surfaces extending parallel to each other along the second direction x may be the substrate side surface 15 and the substrate side surface 16. The substrate side surface 13, the substrate side surface 14, the substrate side surface 15, and the substrate side surface 16 may be rephrased as the first end surface, the second end surface, the third end surface, and the fourth end surface, respectively.

[0017] The first external electrode 2A and the second external electrode 2B are formed on the substrate main surface 11. The first external electrode 2A and the second external electrode 2B are spaced apart from each other in the second direction x. In this embodiment, the first external electrode 2A and the second external electrode 2B form both terminals of the chip component A1, and a current flows between the first external electrode 2A and the second external electrode 2B in the horizontal direction along the substrate main surface 11 of the substrate 1. Therefore, the chip component A1 may be referred to as a horizontal chip component. The horizontal chip component A1 can be used, for example, by flip-chip bonding to a mounting substrate. The first external electrode 2A and the second external electrode 2B may be referred to as a first terminal electrode and a second terminal electrode, or a first external terminal and a second external terminal, respectively. The first external electrode 2A and the second external electrode 2B are formed, for example, by electroless plating.

[0018] The first external electrode 2A is formed in a region on the substrate main surface 11 of the substrate 1, spaced inward from the four substrate side surfaces 13 to 16. In a plan view, the first external electrode 2A is formed in a rectangular shape with its longitudinal direction aligned with the substrate side surface 13. The first external electrode 2A is positioned spaced apart from the substrate side surfaces 13, 14, 15, and 16 of the substrate 1. The first external electrode 2A may overlap the substrate side surfaces 13, 15, and 16 of the substrate 1, thereby partially covering the substrate side surfaces 13, 15, and 16 of the substrate 1.

[0019] The second external electrode 2B is formed in a region on the substrate main surface 11 of the substrate 1, spaced inward from the four substrate side surfaces 13 to 16. In a plan view, the second external electrode 2B is formed in a rectangular shape with its longitudinal direction aligned with the substrate side surface 14. The second external electrode 2B is positioned spaced apart from the substrate side surfaces 14, 13, 15, and 16 of the substrate 1. The second external electrode 2B may overlap the substrate side surfaces 14, 15, and 16 of the substrate 1, thereby partially covering the substrate side surfaces 14, 15, and 16 of the substrate 1.

[0020] Fig. 2 is a schematic exploded view of the chip part A1. Fig. 3 shows only the main elements constituting the chip part A1. Therefore, the chip part A1 may include elements other than the components shown in Fig. 3.

[0021] 2 , the chip component A1 includes a substrate 1, a first capacitor structure 3A, a second capacitor structure 3B, a first electrode film 4A, a first external electrode 2A, and a second external electrode 2B. The number of first capacitor structures 3A and second capacitor structures 3B is not limited in any way. The number of first capacitor structures 3A may be one or more. The number of second capacitor structures 3B may be one or more. In this embodiment, there are two first capacitor structures 3A and one second capacitor structure 3B. The two first capacitor structures 3A are spaced apart in the third direction y, sandwiching one second capacitor structure 3B therebetween.

[0022] 4 is a circuit diagram showing a chip component A1. In the chip component A1, a first capacitor structure 3A and a second capacitor structure 3B are electrically connected in parallel. In this embodiment, two first capacitor structures 3A and one second capacitor structure 3B are electrically connected in parallel. The two first capacitor structures 3A and one second capacitor structure 3B are electrically connected via a first external electrode 2A. The two first capacitor structures 3A and one second capacitor structure 3B are electrically connected via a second external electrode 2B.

[0023] [First Capacitor Structure 3A] A first capacitor portion 30A is formed on the substrate principal surface 11 of the substrate 1. The first capacitor portion 30A is a region of the substrate 1 in which the main portion of the first capacitor structure 3A (a portion having a three-layer structure of electrode-capacitive film-electrode that functions as a passive element) is formed, and may be referred to as a capacitor region. In FIGS. 2 and 3, the first capacitor portion 30A is shown as a closed region surrounded by a two-dot chain line and is clearly distinguished from the portion of the substrate principal surface 11 other than the capacitor portion. However, the first capacitor portion 30A may be defined as a portion that is not clearly defined on the substrate principal surface 11 in a plan view, for example, and is visually recognized as the portion where the main portion of the first capacitor structure 3A is located. The first capacitor structure 3A of this embodiment is configured as a trench capacitor. The capacitance of the first capacitor structure 3A configured as a trench capacitor may be, for example, 100 pF or more and 1 μF or less.

[0024] The two first capacitor portions 30A are formed on both sides of the substrate main surface 11 in the third direction y. As shown in FIG. 3 , the first capacitor portion 30A may be defined as a rectangular region having a longitudinal direction along the second direction x. The first capacitor portion 30A may include a plurality of first capacitor portions 30A. The plurality of first capacitor portions 30A may be arranged adjacent to each other. In this embodiment, the first capacitor portion 30A includes a first region 301A and a second region 302A adjacent to each other in the second direction x.

[0025] In addition to the first capacitor portion 30A, a functional element portion including functional elements other than capacitors is formed on the substrate main surface 11 of the substrate 1. The functional element portion is a region of the substrate 1 in which functional elements such as diodes, resistors, and inductors are formed, and may be referred to as a functional element region. As shown in FIG. 8 , in this embodiment, the functional element portion is a portion that mainly includes diodes, and therefore may be referred to as a first diode portion 7A. Hereinafter, the functional element portion will be described as the first diode portion 7A.

[0026] The first diode portion 7A is formed at both ends of the substrate main surface 11 so as to sandwich the first capacitor portion 30A in a plan view. The first diode portion 7A may be formed at both ends of the substrate 1 in the third direction y (ends close to the substrate side surface 15 and the substrate side surface 16, respectively). The first diode portion 7A may include a plurality of first diode portions 7A. The plurality of first diode portions 7A may be arranged apart from each other via the first capacitor portion 30A. In this embodiment, the first diode portion 7A includes a first region 71A and a second region 72A. The first region 71A is formed in a region between the first capacitor portion 30A and the substrate side surface 13 of the substrate 1. The second region 72A is formed in a region between the first capacitor portion 30A and the substrate side surface 14 of the substrate 1. The first region 71A and the second region 72A extend along the substrate side surface 13 and the substrate side surface 14, respectively, and have, for example, approximately the same length as the length of the first capacitor section 30A in the third direction y.

[0027] As shown in FIG. 8 , the first capacitor structure 3A is formed on the substrate main surface 11 of the substrate 1 and covers the first capacitor portion 30A. The first capacitor structure 3A includes a first internal electrode 31A, a first capacitance film 33A, and a second internal electrode 32A. The first capacitance film 33A is sandwiched between the second internal electrode 32A and the first internal electrode 31A in the first direction z. The first internal electrode 31A, the first capacitance film 33A, and the second internal electrode 32A may each be formed in a film or plate shape. The first internal electrode 31A is smaller (planar size) than the substrate 1 and larger (planar size) than the second internal electrode 32A. A first capacitor contact hole 510A for contacting the first internal electrode 31A is formed in the peripheral portion of the first capacitance film 33A. The first internal electrode 31A, the second internal electrode 32A and the first capacitance film 33A are formed by, for example, sputtering, CVD or the like.

[0028] The first electrode film 4A includes a first electrode film 41A and a second electrode film 42A. The first electrode film 41A and the second electrode film 42A are formed by, for example, sputtering.

[0029] The first electrode film 41A has contact portions with the first internal electrode 31A and the first region 71A. The first electrode film 41A electrically connects the first external electrode 2A to the first internal electrode 31A and the first region 71A. A lower contact portion 311A ​​and a first diode contact portion 511A are shown as contact portions of the first electrode film 41A with the first internal electrode 31A and the first region 71A, respectively. The first electrode film 41A includes a first pad 411A. The first pad 411A is a portion that is electrically connected to the first external electrode 2A.

[0030] The second electrode film 42A has a contact portion for the second region 72A. The second electrode film 42A electrically connects the second external electrode 2B and the second region 72A. In Fig. 2, second diode contact portions 517A are shown as the contact portions of the second electrode film 42A for the second internal electrode 32A and the second region 72A, respectively. The second electrode film 42A includes a base portion 421A.

[0031] The base portion 421A is a portion of the second electrode film 42A to which the second external electrode 2B is connected. In Fig. 3, a first external contact portion 381A (an area surrounded by a two-dot chain line) is shown as a contact portion of the second external electrode 2B with the second electrode film 42A. The base portion 421A is formed in a substantially rectangular shape with its longitudinal direction aligned with the third direction y.

[0032] In this embodiment, the second electrode film 42A and the second internal electrode 32A are integrally formed to form one layer.

[0033] The first external electrode 2A and the second external electrode 2B are formed on the first electrode film 4A. The first external electrode 2A has a first external contact portion 381A and is connected to the first electrode film 41A via the first external contact portion 381A. The second external electrode 2B has a second external contact portion 423A and is connected to the second electrode film 42A via the second external contact portion 423A.

[0034] Next, as shown in Figures 2, 3, 5, and 8, two first capacitor units 30A are formed on both sides of the substrate main surface 11 of the substrate 1 in the third direction y. The portion of the substrate 1 other than the first capacitor units 30A may be defined as a substrate main body 10. In this embodiment, the substrate main body 10 is a substantially quadrangular annular (closed annular) portion that surrounds the first capacitor unit 30A in a plan view. The substrate main body 10 is frame-shaped and surrounds the first capacitor unit 30A, and may be referred to as a frame portion of the substrate 1.

[0035] The first internal electrode 31A includes a first body portion 315A and a first peripheral portion 316A. The first body portion 315A is formed within the first capacitor portion 30A. The first peripheral portion 316A is formed integrally with the first body portion 315A on the substrate body portion 10 (frame portion of the substrate 1) around the first capacitor portion 30A. The first peripheral portion 316A is a portion that is drawn out from the first body portion 315A to the periphery of the first capacitor portion 30A, and may be referred to as a drawn-out portion of the first internal electrode 31A.

[0036] The first peripheral portion 316A may further include a plurality of portions that are separately defined based on their relative positional relationship with the first capacitor portion 30A. The first capacitor portion 30A is surrounded by the first peripheral portion 316A as a closed region.

[0037] The first capacitance film 33A includes a second body portion 335A and a second peripheral portion 336A. The second body portion 335A is formed within the first capacitor portion 30A. The second peripheral portion 336A is formed integrally with the second body portion 335A on the first peripheral portion 316A around the first capacitor portion 30A. The second peripheral portion 336A is a portion that is drawn out from the second body portion 335A to the periphery of the first capacitor portion 30A, and may be referred to as a drawn-out portion of the first capacitance film 33A.

[0038] The second internal electrode 32A is formed in a shape that covers the first capacitor portion 30A. In this embodiment, the second internal electrode 32A is formed in a rectangular shape that covers the entire first capacitor portion 30A. The second internal electrode 32A integrally includes a main body portion 325A and a peripheral edge portion 326A. The main body portion 325A may be a portion that faces the first capacitor portion 30A in the first direction z.

[0039] The peripheral portion 326A may be a portion that extends from the main body portion 325A to the periphery of the first capacitor portion 30A and surrounds the first capacitor portion 30A. In this embodiment, the first peripheral portion 316A and the second peripheral portion 336A are formed outside the peripheral portion 326A of the second internal electrode 32A in a plan view, and have a shape that further surrounds the peripheral portion 326A that surrounds the first capacitor portion 30A.

[0040] The lower contact portion 311A ​​is a contact portion of the first electrode film 41A with the first internal electrode 31A, and is formed in a first peripheral portion 316A of the first internal electrode 31A. The lower contact portion 311A ​​may be formed in an open ring shape surrounding the first capacitor portion 30A, with one side of the first capacitor portion 30A open and the other side closed in the second direction x.

[0041] The first diode contact portion 511A is a contact portion of the first electrode film 41A with the first region 71A. The first diode contact portion 511A overlaps the first external electrode 2A. The first diode contact portion 511A may be formed in a region below the first external electrode 2A. The first diode contact portion 511A extends along the substrate side surface 13 of the substrate 1 in the second direction x and is formed in a strip shape parallel to the substrate side surface 13.

[0042] The second diode contact portion 517A is a contact portion of the second electrode film 42A with the second region 72A. The second diode contact portion 517A overlaps the second external electrode 2B. The second diode contact portion 517A may be formed in a region below the second external electrode 2B. The second diode contact portion 517A extends along the substrate side surface 14 of the substrate 1 in the second direction x and is formed in a strip shape parallel to the substrate side surface 14.

[0043] The first electrode film 41A is located on one side of the first capacitor section 30A in the x direction.

[0044] [First Capacitor Section 30A] FIG. 5 is an enlarged view of a main portion of the chip component A1, including the first capacitor section 30A. FIG. 8 is a schematic cross-sectional view of the chip component A1. For clarity, the trench 112 is hatched in FIG. 5, and the first external electrode 2A and the second external electrode 2B are shown in perspective with dashed lines. FIG. 5 shows only extracted components necessary for explanation and their reference numerals. FIG. 8 is a diagram schematically illustrating the layer structure on the substrate main surface 11 of the chip component A1, and does not show a cross section taken along a specific cutting line in FIG. 5. However, FIG. 8 is a diagram for explaining the cross-sectional structure of the first capacitor section 30A of FIG. 5.

[0045] The chip component A1 is a composite element in which the first capacitor structure 3A, the second capacitor structure 3B, and the first diode portion 7A are mounted on a common substrate 1. The substrate 1 may be a semiconductor substrate such as a silicon plate, or may be an insulating substrate such as a ceramic substrate or a glass substrate. The thickness of the substrate 1 may be, for example, 200 μm or more and 1000 μm or less.

[0046] In the first capacitor section 30A, a portion of the substrate 1 on the substrate main surface 11 side is selectively removed, thereby forming a plurality of wall sections 111 using a portion of the substrate 1. Each of the plurality of wall sections 111 has a longitudinal direction and is formed in a stripe pattern in a plan view. The plurality of wall sections 111 are formed over the entire first capacitor section 30A.

[0047] The first region 301A and the second region 302A are formed one by one and are adjacent to each other. In this embodiment, the first region 301A and the second region 302A are formed adjacent to each other in the second direction x. More specifically, the first region 301A is formed across the first overlap portion 313A and the intermediate portion 82A, and the second region 302A is formed across the second overlap portion 314A and the intermediate portion 82A.

[0048] In the first region 301A, the multiple wall portions 111 are arranged at intervals from one another in the third direction y. In the second region 302A, the multiple wall portions 111 are arranged at intervals from one another in the second direction x. As a result, in each of the first region 301A and the second region 302A, the multiple wall portions 111 are formed in a striped pattern in a plan view. The shape of the multiple wall portions 111 is not limited in any way.

[0049] A plurality of trenches 112 are formed between the plurality of wall portions 111. The trenches 112 are portions where material of the substrate 1 has been removed and are partitioned by the wall portions 111. The width of the trenches 112 may be, for example, 2 μm or more and 8 μm or less. The trenches 112 are formed, for example, by dry etching the substrate 1.

[0050] In this embodiment, as shown in FIG. 8, the height of the wall portion 111 (the depth in the first direction z from the substrate main surface 11 to the bottom surface 1121 of the trench 112) may be 50 μm or more and 400 μm or less.

[0051] A p-type base region 113 is formed in the substrate 1 so as to be exposed from the substrate main surface 11 of the substrate 1. In this embodiment, p-type impurities are introduced into the entire thickness of the substrate 1, from the substrate main surface 11 to the substrate back surface 12. As a result, the base region 113 is formed throughout the substrate 1, and the substrate 1 can be considered a p-type substrate. The introduction of the p-type impurities may set the resistivity of the substrate 1 to approximately 5 mΩ·cm. This base region 113 is not selectively formed in the first diode portion 7A, but is formed throughout the entire substrate 1 including the first capacitor portion 30A. Therefore, the wall portion 111 of the first capacitor portion 30A and the substrate main body portion 10 are formed of the p-type base region 113.

[0052] In the first region 71A, a plurality of first impurity regions 114A are formed in the surface portion of the base region 113. The first impurity regions 114A are n-type impurity regions. As shown in FIG. 5 , the plurality of first impurity regions 114A are arranged at intervals in the third direction y (the direction along the substrate side surface 13 of the substrate 1). In the second region 72A, a plurality of second impurity regions 115A (six in FIG. 5 ) are formed in the surface portion of the base region 113. The second impurity regions 115A are n-type impurity regions. The plurality of second impurity regions 115A are arranged at intervals in the third direction y (the direction along the substrate side surface 14 of the substrate 1).

[0053] The first impurity region 114A and the second impurity region 115A may be formed to the same depth and with the same n-type impurity concentration. The n-type impurity concentration of each of the first impurity region 114A and the second impurity region 115A may be, for example, 1.0×10 １９ cm －３ Above 1.0 x 10 ２１ cm －３ The first impurity region 114A and the second impurity region 115A may be formed to have the same shape and the same area in a plan view. The first impurity region 114A and the second impurity region 115A extend in the third direction y in a plan view and are formed in a rectangular shape with the four corners removed (rectangles with rounded corners).

[0054] The first impurity region 114A forms a pn junction with the base region 113. The pn junction between the first impurity region 114A and the base region 113 forms a first Zener diode Di1A. On the other hand, the second impurity region 115A forms a pn junction with the base region 113. The pn junction between the second impurity region 115A and the base region 113 forms a second Zener diode Di2A. The first Zener diode Di1A and the second Zener diode Di2A are connected in anti-series via the base region 113. The first impurity region 114A and the second impurity region 115A are formed below the first external electrode 2A and the second external electrode 2B, respectively, so as to overlap with the first external electrode 2A and the second external electrode 2B in a plan view. As a result, the depletion layer extending from the pn junction between the first impurity region 114A and the base region 113 does not overlap with the depletion layer extending from the pn junction between the second impurity region 115A and the base region 113. Therefore, a bidirectional Zener diode consisting of the first Zener diode Di1A and the second Zener diode Di2A is formed in the substrate 1.

[0055] An insulating film 59 is formed on the substrate main surface 11 of the substrate 1 so as to cover the entire substrate main surface 11 of the substrate 1. The insulating film 59 is formed not only on the substrate main surface 11, which is the flat surface of the substrate 1, but also on the entire surfaces (top surface 1111 and side surface 1112) of the wall portions 111. The insulating film 59 has end faces that coincide with the substrate side surfaces 13 to 16 of the substrate 1. The insulating film 59 may be, for example, a SiO2 film or a SiN film. The thickness of the insulating film 59 may be, for example, 20,000 Å or more and 40,000 Å or less (2 μm or more and 4 μm or less). The insulating film 59 is formed, for example, by thermally oxidizing the substrate 1.

[0056] In the first capacitor section 30A, a first capacitor structure 3A is formed on the insulating film 59. The first capacitor structure 3A is formed to conform to the upper surface 1111 and the side surface 1112 of the wall portion 111. In other words, the first capacitor structure 3A has at least a first internal electrode 31A that matches the uneven shape of the wall portion 111 in each of the width direction and the height direction. In this embodiment, the first internal electrode 31A is formed on the insulating film 59 and is formed as an electrode film having one surface in contact with the upper surface 1111 and the side surface 1112 of the wall portion 111 and the other surface equidistant from the upper surface 1111 and the side surface 1112 of the wall portion 111. In other words, the first internal electrode 31A has a constant thickness along the upper surface 1111 and the side surface 1112 of the wall portion 111.

[0057] A first capacitance film 33A is formed on the first internal electrode 31A, and a second internal electrode 32A is formed on the first capacitance film 33A. A first main body portion 315A of the first internal electrode 31A faces the upper surface 1111 and side surface 1112 of the wall portion 111 and the bottom surface 1121 of the trench 112, and includes a counter electrode for the second internal electrode 32A. A first peripheral portion 316A of the first internal electrode 31A extends from the first main body portion 315A onto the substrate main surface 11 of the substrate 1 and includes a contact portion for the first external electrode 2A. The first internal electrode 31A may be made of, for example, a semiconductor material such as polysilicon, or a metallic material containing Cu or Al. In the case of a metallic material, it may be made of, for example, Cu, Al, AlSi, or AlCu. The thickness of the first internal electrode 31A may be, for example, 1,000 Å to 30,000 Å (100 nm to 3,000 nm).

[0058] The first capacitance film 33A is formed following the shape of the first internal electrode 31A, and matches the uneven shapes in the width direction and height direction of the wall portion 111 and the trench 112. The first capacitance film 33A includes a second body portion 335A that covers the first body portion 315A of the first internal electrode 31A, and a second peripheral portion 336A that covers the first peripheral portion 316A of the first internal electrode 31A. The first capacitance film 33A is made of, for example, SiO ２ The film may be a silicon nitride film or a silicon nitride film, or a laminated film thereof. ２ / SiN laminated film, SiO ２ / SiN / SiO ２ The first capacitance film 33A may be an ON film or an ONO film, or may be a laminated film of these. Furthermore, the first capacitance film 33A may be an insulating film made of a high dielectric material (high-k material). For example, the high dielectric material may be aluminum oxide (Al ２ O ３ ), tantalum pentoxide (Ta ２ O ５ ), titanium pentoxide (Ti ３ O ５ ), hafnium oxide (HfO ２ ), as well as strontium titanate (SrTiO ３ ), barium strontium titanate (BaxSr １－ｘ ) TiO ３ The thickness of the first capacitance film 33A may be, for example, 100 Å or more and 10,000 Å or less (10 nm or more and 1000 nm or less).

[0059] The second internal electrode 32A is embedded in the trench 112 and formed along the main surface 11 of the substrate 1. The second internal electrode 32A integrally includes a buried portion 321A embedded in the trench 112 and a flat portion 322A connected to the upper end of the buried portion 321A and formed flat along the main surface 11 of the substrate 1. The flat portion 322A forms a peripheral portion 326A of the second internal electrode 32A that extends outward from the first capacitor portion 30A. The flat portion 322A is integrally connected to the second electrode film 42A. The second internal electrode 32A may be made of a semiconductor material such as polysilicon, or a metal material containing Cu or Al. In the case of a metal material, it may be made of, for example, Cu, Al, AlSi, or AlCu. The thickness of the second internal electrode 32A (flat portion 322A) may be, for example, 4,000 Å or more and 30,000 Å or less (400 nm or more and 3,000 nm or less).

[0060] A first insulating film 58 is further formed on the substrate 1. The first insulating film 58 covers the insulating film 59, the first internal electrode 31A, the first capacitance film 33A, the second internal electrode 32A, and the third internal electrode 31B, the second capacitance film 33B, and the fourth internal electrode 32B (described later), and is laminated thereon. The first insulating film 58 has end faces that coincide with the substrate side surfaces 13 to 16 of the substrate 1. Therefore, the insulating film 59, the first insulating film 58, and the second insulating film 57 may have laminated interfaces that are exposed on extensions of the substrate side surfaces 13 to 16 of the substrate 1 in the cross-sectional view shown in FIG. 8 . The first insulating film 58 is formed, for example, by a CVD method.

[0061] A first capacitor contact hole 510A exposing the first peripheral portion 316A of the first internal electrode 31A is formed in the first insulating film 58. The first capacitor contact hole 510A is also formed in the first capacitance film 33A.

[0062] The insulating film 59 and the first insulating film 58 are further formed with a first diode contact hole 513A exposing the first region 71A and a second diode contact hole 514A exposing the second region 72A. Referring to Fig. 5, the first diode contact hole 513A is formed in a strip shape with its longitudinal direction aligned with the third direction y, and collectively exposes the multiple first Zener diodes Di1A. The second diode contact hole 514A is formed in a strip shape with its longitudinal direction aligned with the third direction y, and collectively exposes the multiple second Zener diodes Di2A.

[0063] A first electrode film 41A and a second electrode film 42A are formed on the first insulating film 58 with a gap between them.

[0064] 8, a portion of the base portion 421A of the first electrode film 41A is formed as a first diode contact portion 511A in the first diode contact hole 513A, and is also formed in the first capacitor contact hole 510A. A portion of the first internal electrode 31A is formed as a lower contact portion 311A ​​in the first capacitor contact hole 510A.

[0065] A part of the base portion 421A of the second electrode film 42A is formed as a second diode contact portion 517A in the second diode contact hole 514A.

[0066] A material containing Al may be used as the electrode material for the first electrode film 41A and the second electrode film 42A. Examples of such a material include AlCu and AlSiCu, with AlCu being preferred.

[0067] A surface insulating film 56 is further formed on the substrate 1. The surface insulating film 56 covers the first electrode film 41A, the second electrode film 42A, and the first electrode film 41B and the second electrode film 42B described below. The surface insulating film 56 is made of, for example, SiO ２ The surface insulating film 56 may be a silicon nitride film or a silicon nitride film. The thickness of the surface insulating film 56 may be, for example, 3000 Å or more and 30000 Å or less (0.3 μm or more and 3 μm or less). The surface insulating film 56 integrally includes a first portion 561 that covers an area on the substrate main surface 11 of the substrate 1, and a second portion 562 that covers the substrate side surfaces 13 to 16 of the substrate 1. As a result, the substrate 1 has a surface on which the substrate back surface 12 is exposed, while the other surfaces are entirely covered with the surface insulating film 56.

[0068] A surface protection film 55 is formed on the first portion 561 of the surface insulating film 56. The surface protection film 55 may be, for example, a resin film such as a polyimide film. The thickness of the surface protection film 55 may be, for example, 5,000 Å to 100,000 Å (0.5 μm to 10 μm). The surface insulating film 56 is formed, for example, by a CVD method. The surface protection film 55 is formed, for example, by spraying. The surface insulating film 56 is formed, for example, by a CVD method.

[0069] A first pad opening 515A exposing the base portion 421A of the first electrode film 41A as the first pad 411A is formed in the surface insulating film 56 and the surface protective film 55. A second pad opening 516A exposing the base portion 421A of the second electrode film 42A as the second pad 412A is formed in the surface insulating film 56 and the surface protective film 55.

[0070] A first covering portion 561A is formed on the first pad 411A to selectively cover the first pad 411A. A second covering portion 562A is formed on the second pad 412A to selectively cover the second pad 412A. The first covering portion 561A and the second covering portion 562A may be made of the same material as the surface insulating film 56.

[0071] A first external electrode 2A is formed in the first pad opening 515A. The first external electrode 2A is connected to the first pad 411A as a first external contact portion 381A in the first pad opening 515A. This electrically connects the first external electrode 2A to the first internal electrode 31A and the first impurity region 114A via the first electrode film 41A.

[0072] A second external electrode 2B is formed in the second pad opening 516A. The second external electrode 2B is connected to the second pad 412A as a second external contact portion 423A in the second pad opening 516A. This electrically connects the second external electrode 2B to the second internal electrode 32A and the second impurity region 115A via the second electrode film 42A.

[0073] The first external electrode 2A and the second external electrode 2B may be, for example, a Ni / Pd / Au laminated film including a Ni film, a Pd film, and an Au film laminated in this order from the substrate 1 side. These laminated films may be plating layers formed by plating growth.

[0074] [Second Capacitor Structure 3B] A second capacitor portion 30B is formed on the substrate principal surface 11 of the substrate 1. The second capacitor portion 30B is a region of the substrate 1 in which the main portion of the second capacitor structure 3B (a portion having a three-layer structure of electrode-capacitive film-electrode that functions as a passive element) is formed, and may be referred to as a capacitor region. In FIGS. 2 and 3, the second capacitor portion 30B is shown as a closed region surrounded by a two-dot chain line and is clearly distinguished from the portion of the substrate principal surface 11 other than the capacitor portion. However, the second capacitor portion 30B may be defined as a portion that is not clearly defined on the substrate principal surface 11 in a planar view, for example, and is visually recognized as the portion where the main portion of the second capacitor structure 3B is located. The second capacitor structure 3B of this embodiment is configured as a planar capacitor along the substrate principal surface 11. The capacitance of the second capacitor structure 3B configured as a planar capacitor may be, for example, 1 pF or more and 100 pF or less.

[0075] The second capacitor portion 30B is formed approximately in the center of the substrate main surface 11. As shown in Fig. 3, the second capacitor portion 30B may be defined as a rectangular region having a longitudinal direction along the second direction x.

[0076] A functional element portion is formed on the substrate main surface 11 of the substrate 1. As shown in FIG. 9 , the functional element portion may be referred to as a second diode portion 7B. The second diode portion 7B will be described below. The chip component A1 is not limited to a configuration having both the first diode portion 7A and the second diode portion 7B, and may have only one of the first diode portion 7A and the second diode portion 7B. A configuration not including both the first diode portion 7A and the second diode portion 7B is also possible.

[0077] The second diode portion 7B is formed at both ends of the substrate main surface 11 so as to sandwich the second capacitor portion 30B in a plan view. The second diode portion 7B may be formed at both ends of the substrate 1 in the third direction y (ends close to the substrate side surface 15 and the substrate side surface 16, respectively). The second diode portion 7B may include multiple second diode portions 7B. The multiple second diode portions 7B may be arranged apart from each other via the second capacitor portion 30B. In this embodiment, the second diode portion 7B includes a first region 71B and a second region 72B. The first region 71B is formed in a region between the second capacitor portion 30B and the substrate side surface 13 of the substrate 1. The second region 72B is formed in a region between the second capacitor portion 30B and the substrate side surface 14 of the substrate 1. The first region 71B and the second region 72B extend along the substrate side surface 13 and the substrate side surface 14, respectively, and have, for example, approximately the same length as the length of the second capacitor section 30B in the third direction y.

[0078] As shown in FIG. 9 , the second capacitor structure 3B is formed on the substrate main surface 11 of the substrate 1 and covers the second capacitor portion 30B. The second capacitor structure 3B includes a third internal electrode 31B, a second capacitance film 33B, and a fourth internal electrode 32B. The second capacitance film 33B is sandwiched between the fourth internal electrode 32B and the third internal electrode 31B in the first direction z. The third internal electrode 31B, the second capacitance film 33B, and the fourth internal electrode 32B may each be formed in a film or plate shape. The third internal electrode 31B and the second capacitance film 33B are smaller (planar size) than the substrate 1 and larger (planar size) than the fourth internal electrode 32B. A first capacitor contact hole 510B for contacting the third internal electrode 31B is formed in the peripheral portion of the second capacitance film 33B. The third internal electrode 31B, the fourth internal electrode 32B, and the second capacitance film 33B are formed by, for example, a CVD method. In this embodiment, the first capacitance film 33A and the second capacitance film 33B are configured as a single layer that is integrally formed.

[0079] The second electrode film 4B is formed on the second capacitor structure 3B and covers the second capacitor structure 3B. The second electrode film 4B may be formed in the form of a conductive film. The second electrode film 4B includes a first electrode film 41B and a second electrode film 42B. The first electrode film 41B and the second electrode film 42B are formed by, for example, a sputtering method.

[0080] The first electrode film 41B has contact portions with the third internal electrode 31B and the first region 71B. The first electrode film 41B electrically connects the first external electrode 2A with the third internal electrode 31B and the first region 71B. A lower contact portion 311B and a first diode contact portion 511B are shown as contact portions of the first electrode film 41B with the third internal electrode 31B and the first region 71B, respectively. The first electrode film 41B includes a first pad 411B. The first pad 411B is a portion that is electrically connected to the first external electrode 2A.

[0081] The second electrode film 42B has contact portions with the fourth internal electrode 32B and the second region 72B. The second electrode film 42B electrically connects the second external electrode 2B with the fourth internal electrode 32B and the second region 72B. In FIG. 3 , second diode contact portions 517B are shown as the contact portions of the second electrode film 42B with the fourth internal electrode 32B and the second region 72B. The second electrode film 42B includes a base portion 421B. In this embodiment, the second electrode films 42A and 42B are integrally formed and connected to each other.

[0082] The base portion 421B is a portion of the second electrode film 42B to which the second external electrode 2B is connected. In Fig. 3, a first external contact portion 381B (an area surrounded by a two-dot chain line) is shown as a contact portion of the second external electrode 2B with the second electrode film 42B. The base portion 421B is formed in a substantially rectangular shape with its longitudinal direction aligned with the third direction y.

[0083] In this embodiment, the second electrode film 42B and the fourth internal electrode 32B are integrally formed to form one layer.

[0084] The first external electrode 2A and the second external electrode 2B are formed on the second electrode film 4B. The first external electrode 2A has a first external contact portion 381B and is connected to the first electrode film 41B via the first external contact portion 381B. The second external electrode 2B has a second external contact portion 423B and is connected to the second electrode film 42B via the second external contact portion 423B.

[0085] 2, 3, 5, and 9, a second capacitor portion 30B is formed approximately in the center of the substrate main surface 11 of the substrate 1. The portion of the substrate 1 other than the second capacitor portion 30B may be defined as a substrate main body portion 10. In this embodiment, the substrate main body portion 10 is a substantially quadrangular annular (closed annular) portion that surrounds the second capacitor portion 30B in a plan view. The substrate main body portion 10 is frame-shaped and surrounds the second capacitor portion 30B, and may be referred to as a frame portion of the substrate 1.

[0086] The third internal electrode 31B and the second capacitance film 33B have the same shape in a plan view. The third internal electrode 31B includes a first body portion 315B and a first peripheral portion 316B. The first body portion 315B is formed within the second capacitor portion 30B. The first peripheral portion 316B is formed integrally with the first body portion 315B on the substrate body portion 10 (frame portion of the substrate 1) around the second capacitor portion 30B. The first peripheral portion 316B is a portion that extends from the first body portion 315B to the periphery of the second capacitor portion 30B, and may be referred to as an extension portion of the third internal electrode 31B.

[0087] The first peripheral portion 316B may further include a plurality of portions that are separately defined based on their relative positional relationship with the second capacitor portion 30B. The second capacitor portion 30B is surrounded by the first peripheral portion 316B as a closed region.

[0088] The second capacitance film 33B includes a second body portion 335B and a second peripheral portion 336B. The second body portion 335B is formed within the second capacitor portion 30B. The second peripheral portion 336B is formed integrally with the second body portion 335B on the first peripheral portion 316B around the second capacitor portion 30B. The second peripheral portion 336B is a portion that extends from the second body portion 335B to the periphery of the second capacitor portion 30B, and may be referred to as an extended portion of the second capacitance film 33B.

[0089] The fourth internal electrode 32B is formed in a shape that covers the second capacitor portion 30B. In this embodiment, the fourth internal electrode 32B is formed in a rectangular shape that covers the entire second capacitor portion 30B. The fourth internal electrode 32B integrally includes a main body portion 325B and a peripheral edge portion 326B. The main body portion 325B may be a portion that faces the second capacitor portion 30B in the first direction z.

[0090] The peripheral portion 326B may be a portion that extends from the main body portion 325B to the periphery of the second capacitor portion 30B and surrounds the second capacitor portion 30B. In this embodiment, the first peripheral portion 316B and the second peripheral portion 336B are formed outside the peripheral portion 326B of the fourth internal electrode 32B in a plan view, and have a shape that further surrounds the peripheral portion 326B that surrounds the second capacitor portion 30B.

[0091] The lower contact portion 311B is a contact portion of the first electrode film 41B with the third internal electrode 31B, and is formed in a first peripheral portion 316B of the third internal electrode 31B. The lower contact portion 311B may be formed in an open ring shape surrounding the second capacitor portion 30B, with one side of the second capacitor portion 30B open and the other side closed in the second direction x.

[0092] The first diode contact portion 511B is a contact portion of the first electrode film 41B with the first region 71B. The first diode contact portion 511B overlaps the first external electrode 2A. The first diode contact portion 511B may be formed in a region below the first external electrode 2A. The first diode contact portion 511B extends along the substrate side surface 13 of the substrate 1 in the second direction x and is formed in a strip shape parallel to the substrate side surface 13.

[0093] The second diode contact portion 517B is a contact portion of the second electrode film 42B with the second region 72B. The second diode contact portion 517B overlaps the second external electrode 2B. The second diode contact portion 517B may be formed in a region below the second external electrode 2B. The second diode contact portion 517B extends along the substrate side surface 14 of the substrate 1 in the second direction x and is formed in a strip shape parallel to the substrate side surface 14.

[0094] The first electrode film 41B is located on one side of the second capacitor section 30B in the x direction.

[0095] In the second capacitor section 30B, the substrate main surface 11 of the substrate 1 may be, for example, smooth.

[0096] The base region 113 is not formed selectively in the second diode portion 7B, but is formed over the entire substrate 1 including the second capacitor portion 30B.

[0097] In the first region 71B, a plurality of first impurity regions 114B are formed in the surface portion of the base region 113. The first impurity regions 114B are n-type impurity regions. As shown in FIG. 5 , the plurality of first impurity regions 114B are arranged at intervals in the third direction y (the direction along the substrate side surface 13 of the substrate 1). In the second region 72B, a plurality of second impurity regions 115B (six in FIG. 5 ) are formed in the surface portion of the base region 113. The second impurity regions 115B are n-type impurity regions. The plurality of second impurity regions 115B are arranged at intervals in the third direction y (the direction along the substrate side surface 14 of the substrate 1).

[0098] The first impurity region 114B and the second impurity region 115B may be formed to the same depth and with the same n-type impurity concentration. The n-type impurity concentration of each of the first impurity region 114B and the second impurity region 115B may be, for example, 1.0×10 １９ cm －３ Above 1.0 x 10 ２１ cm －３ The first impurity region 114B and the second impurity region 115B may be formed to have the same shape and the same area in a plan view. The first impurity region 114B and the second impurity region 115B extend in the third direction y in a plan view and are formed in a rectangular shape with the four corners removed (rectangles with rounded corners).

[0099] The first impurity region 114B forms a pn junction with the base region 113. The pn junction between the first impurity region 114B and the base region 113 forms a first Zener diode Di1B. On the other hand, the second impurity region 115B forms a pn junction with the base region 113. The pn junction between the second impurity region 115B and the base region 113 forms a second Zener diode Di2B. The first Zener diode Di1B and the second Zener diode Di2B are connected in anti-series via the base region 113. The first impurity region 114B and the second impurity region 115B are formed below the first external electrode 2A and the second external electrode 2B, respectively, so as to overlap with the first external electrode 2A and the second external electrode 2B in a plan view. As a result, the depletion layer extending from the pn junction between the first impurity region 114B and the base region 113 does not overlap with the depletion layer extending from the pn junction between the second impurity region 115B and the base region 113. Therefore, a bidirectional Zener diode consisting of the first Zener diode Di1B and the second Zener diode Di2B is formed in the substrate 1.

[0100] A second capacitance film 33B is formed on the third internal electrode 31B, and a fourth internal electrode 32B is formed on the second capacitance film 33B. The third internal electrode 31B may be made of a semiconductor material such as polysilicon, or a metal material containing Cu or Al. If the metal material is Cu, Al, AlSi, or AlCu, for example. The thickness of the third internal electrode 31B may be, for example, 1,000 Å to 3,000 Å (100 nm to 300 nm).

[0101] The second capacitance film 33B is formed on the third internal electrode 31B. The second capacitance film 33B is made of, for example, SiO ２ The film may be a silicon nitride film or a silicon nitride film, or a laminated film thereof. ２ / SiN laminated film, SiO ２ / SiN / SiO ２ The second capacitance film 33B may be an ON film or an ONO film, or may be a laminated film of these. Furthermore, the second capacitance film 33B may be an insulating film made of a high dielectric material (high-k material). Examples of high dielectric materials include aluminum oxide (Al ２ O ３ ), tantalum pentoxide (Ta ２ O ５ ), titanium pentoxide (Ti ３ O ５ ), hafnium oxide (HfO ２ ), as well as strontium titanate (SrTiO ３ ), barium strontium titanate (BaxSr １－ｘ ) TiO ３ The thickness of the second capacitance film 33B may be, for example, 100 Å or more and 30,000 Å or less (10 nm or more and 3000 nm or less).

[0102] The fourth internal electrode 32B is formed on the second capacitance film 33B. The flat portion 322A forms a peripheral portion 326B of the fourth internal electrode 32B that is extended further outward than the second capacitor portion 30B. The fourth internal electrode 32B may be made of, for example, a semiconductor material such as polysilicon, or a metal material containing Cu or Al. In the case of a metal material, it may be made of, for example, Cu, Al, AlSi, or AlCu. The thickness of the fourth internal electrode 32B (flat portion 322A) may be, for example, 1,000 Å or more and 30,000 Å or less (100 nm or more and 3,000 nm or less).

[0103] A first capacitor contact hole 510B exposing the first peripheral portion 316B of the third internal electrode 31B is formed in the first insulating film 58. The first capacitor contact hole 510B is also formed in the second capacitance film 33B.

[0104] The insulating film 59 and the first insulating film 58 are further formed with a first diode contact hole 513B exposing the first region 71B and a second diode contact hole 514B exposing the second region 72B. Referring to Fig. 5, the first diode contact hole 513B is formed in a strip shape with its longitudinal direction aligned with the third direction y, and collectively exposes the multiple first Zener diodes Di1B. The second diode contact hole 514B is formed in a strip shape with its longitudinal direction aligned with the third direction y, and collectively exposes the multiple second Zener diodes Di2B.

[0105] A first electrode film 41B and a second electrode film 42B are formed on the first insulating film 58 with a gap between them.

[0106] 9, a portion of the base portion 421B of the first electrode film 41B is formed as a first diode contact portion 511B in the first diode contact hole 513B, and is also formed in the first capacitor contact hole 510B. A portion of the third internal electrode 31B is formed as a lower contact portion 311B in the first capacitor contact hole 510B.

[0107] A part of the base portion 421B of the second electrode film 42B is formed as a second diode contact portion 517B in the second diode contact hole 514B.

[0108] The first electrode film 41B and the second electrode film 42B may be made of a material containing Al, such as AlCu or AlSiCu, with AlCu being preferred.

[0109] A first pad opening 515B exposing the base portion 421B of the first electrode film 41B as a first pad 411B is formed in the surface insulating film 56 and the surface protective film 55. A second pad opening 516B exposing the base portion 421B of the second electrode film 42B as a second pad 412B is formed in the surface insulating film 56 and the surface protective film 55.

[0110] A first covering portion 561B is formed on the first pad 411B to selectively cover the first pad 411B. A second covering portion 562B is formed on the second pad 412B to selectively cover the second pad 412B. The first covering portion 561B and the second covering portion 562B may be made of the same material as the surface insulating film 56.

[0111] A first external electrode 2A is formed in the first pad opening 515B. The first external electrode 2A is connected to the first pad 411B as a first external contact portion 381B in the first pad opening 515B. This electrically connects the first external electrode 2A to the third internal electrode 31B and the first impurity region 114B via the first electrode film 41B.

[0112] A second external electrode 2B is formed in the second pad opening 516B. The second external electrode 2B is connected to the second pad 412B as a second external contact portion 423B in the second pad opening 516B. As a result, the second external electrode 2B is electrically connected to the fourth internal electrode 32B and the second impurity region 115B via the second electrode film 42B.

[0113] As shown in Figures 6, 7, and 9, the second capacitor structure 3B includes a plurality of capacitor elements 300B. The plurality of capacitor elements 300B are electrically connected in parallel to one another. The capacitance of each of the plurality of capacitor elements 300B is not limited in any way. The capacitances of the plurality of capacitor elements 300B may be the same as or different from one another. In this embodiment, the capacitances of the plurality of capacitor elements 300B are different from one another. When the capacitances of the plurality of capacitor elements 300B are arranged in order of magnitude, the capacitance of adjacent capacitor elements 300B may be an integer multiple, such as twice.

[0114] In this embodiment, the second electrode film 42B and the fourth internal electrode 32B are integrally formed to form one layer.

[0115] In this embodiment, the fourth internal electrode 32B includes a plurality of individual parts 321B. The plurality of individual parts 321B are formed corresponding to the plurality of capacitor elements 300B, and each is a component of a capacitor element 300B. The plurality of individual parts 321B are integrally connected to a base portion 421B of the second electrode film 42B. In this embodiment, the capacitance of each of the plurality of capacitor elements 300B can be determined by the area of ​​the plurality of individual parts 321B. That is, when the plurality of individual parts 321B are arranged in order of size, the area of ​​adjacent individual parts 321B may be an integer multiple, such as twice.

[0116] The second electrode film 42B includes a plurality of fuse portions 429B. The fuse portions 429B are individually arranged between the capacitor elements 300B and the second external electrode 2B. In other words, the fuse portions 429B are individually electrically interposed between the capacitor elements 300B and the second external electrode 2B. Each fuse portion 429B is a locally constricted portion of the second electrode film 42B in a plan view. In the illustrated example, the fuse portion 429B has a smaller dimension in the third direction y than the individual portion 321B and the base portion 421B. A plurality of fuse portions 429B may be interposed between one individual portion 321B and the base portion 421B. The fuse portions 429B can be cut, for example, by laser irradiation during the manufacture of the chip component A1. The individual part 321B (capacitor element 300B) in which the fuse part 429B has been cut off is no longer electrically connected to the second external electrode 2B, and becomes a part that does not contribute to the capacitance of the second capacitor structure 3B.

[0117] In this embodiment, the first internal electrode 31A and the third internal electrode 31B are made of the same material and have the same thickness. The second internal electrode 32A and the fourth internal electrode 32B are made of the same material and have the same thickness. The first capacitance film 33A and the second capacitance film 33B are made of the same material and have the same thickness. The first electrode film 41A and the first electrode film 41B are made of the same material and have the same thickness. The second electrode film 42A and the second electrode film 42B are made of the same material and have the same thickness.

[0118] Next, the function of the chip part A1 will be described.

[0119] The chip component A1 includes a first capacitor structure 3A and a second capacitor structure 3B. This reduces the mounting area compared to when a chip component corresponding to the first capacitor structure 3A and another chip component corresponding to the second capacitor structure 3B are separately prepared and mounted on a circuit board or the like. There is no need to provide wiring or the like for electrically connecting the first capacitor structure 3A and the second capacitor structure 3B.

[0120] One application of the chip component A1 is the removal of noise present in the power supply line of a high-frequency circuit. To achieve sufficient charging and discharging during noise removal, the capacitance of the chip capacitor is desirably several hundred pF to several nF. To remove noise from high-frequency signals of several hundred MHz or higher, a capacitor with a relatively small capacitance and a resonant frequency close to the desired frequency is desired. The chip component A1 includes a first capacitor structure 3A and a second capacitor structure 3B. By being able to individually set the configurations of the first capacitor structure 3A and the second capacitor structure 3B, it is possible to more accurately achieve the specifications required of the chip component A1.

[0121] By using a trench capacitor as the first capacitor structure 3A, the capacitance of the first capacitor structure 3A can be reliably increased. By using a planar capacitor as the second capacitor structure 3B, the capacitance is smaller than that of the first capacitor structure 3A and can be set more accurately to a desired value. By appropriately configuring the multiple walls 111 and multiple trenches 112 of the trench capacitor that make up the first capacitor structure 3A, the series resistance component of the first capacitor structure 3A can be reduced.

[0122] By providing the first capacitor structure 3A with a large capacitance, it is possible to ensure the electrostatic withstand capability of the second capacitor structure 3B even if the second capacitance film 33B of the second capacitor structure 3B is thinned.

[0123] By using a planar capacitor as the second capacitor structure 3B, it is possible to reduce the inductance component and resistance component of the second capacitor structure 3B. Because the first capacitor structure 3A and the second capacitor structure 3B are electrically connected in parallel, even if the inductance component and resistance component of the first capacitor structure 3A increase, it is possible to suppress an increase in the inductance component and resistance component of the chip component A1 as a whole.

[0124] The second capacitor structure 3B includes a plurality of capacitor elements 300B. The plurality of capacitor elements 300B can be arbitrarily disconnected from the second external electrode 2B by cutting the fuse portion 429B. This allows the capacitance of the second capacitor structure 3B to be set more precisely, which is advantageous for removing noise from high-frequency signals.

[0125] When the capacitances of the plurality of capacitor elements 300B are arranged in order of magnitude, if the capacitances of adjacent capacitor elements 300B are an integer multiple, such as twice, the capacitances of the plurality of capacitor elements 300B will be configured as 1:2:4:8:16:32:.... As a result, by appropriately selecting the capacitor elements 300B that cut off electrical continuity with the second external electrode 2B, a wider variety of capacitance values ​​can be set more accurately.

[0126] In this embodiment, the first internal electrode 31A and the third internal electrode 31B are made of the same material and have the same thickness. This allows the first internal electrode 31A and the third internal electrode 31B to be formed in the same process in the manufacturing method of the chip component A1. The second internal electrode 32A and the fourth internal electrode 32B are made of the same material and have the same thickness. This allows the second internal electrode 32A and the fourth internal electrode 32B to be formed in the same process in the manufacturing method of the chip component A1. The first capacitive film 33A and the second capacitive film 33B are made of the same material and have the same thickness. This allows the first capacitive film 33A and the second capacitive film 33B to be formed in the same process in the manufacturing method of the chip component A1. The first electrode film 41A and the first electrode film 41B are made of the same material and have the same thickness. This allows the first electrode film 41A and the first electrode film 41B to be formed in the same process in the manufacturing method of the chip component A1. The second electrode films 42A and 42B are made of the same material and have the same thickness, which allows the second electrode films 42A and 42B to be formed in the same process in the method for manufacturing the chip component A1.

[0127] 10 and 11 show modified examples of the present disclosure. In these figures, elements that are the same as or similar to those in the above embodiment are given the same reference numerals. The configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0128] 10 shows a first modified example of the chip part A1. The chip part A11 of this modified example includes one first capacitor structure 3A and one second capacitor structure 3B.

[0129] The first capacitor structure 3A and the second capacitor structure 3B are aligned in the third direction y. In this modification, the first capacitor structure 3A and the second capacitor structure 3B are also electrically connected in parallel. The first capacitor structure 3A and the second capacitor structure 3B are electrically connected via the first external electrode 2A. The first capacitor structure 3A and the second capacitor structure 3B are electrically connected via the second external electrode 2B.

[0130] As can be seen from this modification, the number of each second capacitor structure 3B is not limited in any way.

[0131] 11 shows a second modified example of the chip part A12. The chip part A12 of this modified example differs from the above-described example in the configuration of the second capacitor structure 3B.

[0132] The second capacitor structure 3B of this modification does not have the plurality of capacitor elements 300B described above. It can be said that the second capacitor structure 3B is configured to include only one capacitor element 300B. The second electrode film 42B does not include the fuse portion 429 described above.

[0133] As can be seen from this modification, the second capacitor structure 3B is not limited to a configuration including a plurality of capacitor elements 300B.

[0134] The chip component according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the chip component according to the present disclosure can be freely modified in various ways. The present disclosure includes the embodiments described in the following appendices.

[0135] Supplementary Note 1. A chip component (A1) comprising: a substrate (1); a first capacitor structure (3A) formed on the substrate (1); and a second capacitor structure (3B) formed on the substrate (1), wherein the first capacitor structure (3A) and the second capacitor structure (3B) are electrically connected in parallel, and the first capacitor structure (3A) is a trench capacitor. Supplementary Note 2. The chip component (A1) according to Supplementary Note 1, wherein the capacitance of the first capacitor structure (3A) is greater than the capacitance of the second capacitor structure (3B). Supplementary Note 3. The chip component (A1) according to Supplementary Note 1 or 2, wherein the substrate (1) includes a semiconductor. Supplementary Note 4. The chip component (A1) according to Supplementary Note 3, wherein the substrate (1) includes silicon. Supplementary Note 5. The chip component (A1) according to any one of Supplementary Notes 1 to 4, wherein the substrate (1) has a substrate main surface (11) perpendicular to the first direction (z), and the second capacitor structure (3B) is a planar capacitor along the substrate main surface (11). Supplementary Note 6: The chip component (A1) according to Supplementary Note 5, wherein the first capacitor structure (3A) includes a first internal electrode (31A) and a second internal electrode (32A), and a first capacitance film (33A) interposed between the first internal electrode (31A) and the second internal electrode (32A). Supplementary Note 7: The chip component (A1) according to Supplementary Note 6, wherein the second capacitor structure (3B) includes a third internal electrode (31B) and a fourth internal electrode (32B), and a second capacitance film (33B) interposed between the third internal electrode (31B) and the fourth internal electrode (32B). Supplementary Note 8: A chip component (A1) according to Supplementary Note 7, wherein the material of the first internal electrode (31A) and the material of the third internal electrode (31B) are the same. Supplementary Note 9. A chip component (A1) according to Supplementary Note 7 or 8, wherein the material of the second internal electrode (32A) and the material of the fourth internal electrode (32B) are the same. Supplementary Note 10. A chip component (A1) according to any of Supplementary Notes 7 to 9, wherein the material of the first capacitive film (33A) and the material of the second capacitive film (33B) are the same. Supplementary Note 11. A chip component (A1) according to any of Supplementary Notes 1 to 10, further comprising a first external electrode (2A) and a second external electrode (2B).Supplementary Note 12: The chip component (A1) according to Supplementary Note 11, wherein the first capacitor structure (3A) and the second capacitor structure (3B) are electrically connected via the first external electrode (2A). Supplementary Note 13: The chip component (A1) according to Supplementary Note 11 or 12, wherein the first capacitor structure (3A) and the second capacitor structure (3B) are electrically connected via the second external electrode (2B). Supplementary Note 14: The chip component (A1) according to any one of Supplements 11 to 13, wherein the second capacitor structure (3B) includes a plurality of capacitor elements (300B) electrically connected in parallel with each other and a plurality of fuse portions (429B) individually arranged between the plurality of capacitor elements (300B) and the second external electrode (2B). Supplementary Note 15: The chip component (A1) according to any one of Supplements 1 to 14, comprising two of the first capacitor structures (3A) located on both sides of the second capacitor structure (3B) in a plan view.

[0136] 1: Substrate 2A: First external electrode 2B: Second external electrode 3A: First capacitor structure 3B: Second capacitor structure 4A: First electrode film 4B: Second electrode film 7A: First diode portion 7B: Second diode portion 10: Substrate main body portion 11: Substrate main surface 12, 13, 14, 15, 16: Substrate side surface 30A: First capacitor portion 30B: Second capacitor portion 31A: First internal electrode 31B: Third internal electrode 32A: Second internal electrode 32B: Fourth internal electrode 33A: First capacitance film 33B: Second capacitance film 41A, 41B: First electrode film 42A, 42B: Second electrode film 55: Surface protective film 56: Surface insulating film 57: Second insulating film 58: First insulating film 59: Insulating film 71A, 71B: First region 72A, 72B: Second region 82A: Intermediate portion 111: Wall portion 112: Trench 113: Base region 114A, 114B: First impurity region 115A, 115B: Second impurity region 300B: Capacitor element 301A: First region 302A: Second region 311A, 311B: Lower contact portion 313A: First overlap portion 314A: Second overlap portion 315A, 315B: First body portion 316A, 316B: First peripheral portion 321A: Buried portion 321B: Individual portion 322A: Flat portion 325A, 325B: Body portion 326A, 326B: Peripheral portion 335A, 335B: Second body portion 336A, 336B: Second peripheral portion 381A, 381B: First external contact portion 411A, 411B: First pad 412A, 412B: Second pad 421A, 421B: Base portion 422A, 422B: Extension portion 423A, 423B: Second external contact portion 429B: Fuse portion 510A, 510B: First capacitor contact hole 511A, 511B: First diode contact portion 512A, 512B: Second capacitor contact hole 513A, 513B: First diode contact hole 514A, 514B: Second diode contact hole 515A, 515B: First pad opening 516A, 516B: Second pad opening 517A, 517B: Second diode contact portion 561: First portion 561A,561B: First covering portion 562: Second portion 562A, 562B: Second covering portion 811A, 811B: Upper contact portion 1111: Top surface 1112: Side surface 1121: Bottom surface A1: Chip component Di1A, Di1B: First Zener diode Di2A, Di2B: Second Zener diode x: Second direction y: Third direction z: First direction

Claims

1. circuit board and A first capacitor structure formed on the substrate, The substrate comprises a second capacitor structure formed on the substrate, The first capacitor structure and the second capacitor structure are electrically connected in parallel. The first capacitor structure is a trench capacitor, a chip component.

2. The chip component according to claim 1, wherein the capacitance of the first capacitor structure is greater than the capacitance of the second capacitor structure.

3. The substrate is a chip component according to claim 1 or 2, comprising a semiconductor.

4. The substrate is a chip component according to claim 3, comprising silicon.

5. The substrate has a main substrate surface that is perpendicular to the first direction, The chip component according to claim 1 or 2, wherein the second capacitor structure is a planar capacitor along the main surface of the substrate.

6. The chip component according to claim 5, wherein the first capacitor structure includes a first internal electrode and a second internal electrode, and a first capacitive film interposed between the first internal electrode and the second internal electrode.

7. The chip component according to claim 6, wherein the second capacitor structure includes a third internal electrode and a fourth internal electrode, and a second capacitance film interposed between the third internal electrode and the fourth internal electrode.

8. The chip component according to claim 7, wherein the material of the first internal electrode and the material of the third internal electrode are the same.

9. The chip component according to claim 7, wherein the material of the second internal electrode and the material of the fourth internal electrode are the same.

10. The chip component according to claim 7, wherein the material of the first capacitance film and the material of the second capacitance film are the same.

11. The chip component according to claim 1 or 2, further comprising a first external electrode and a second external electrode.

12. The chip component according to claim 11, wherein the first capacitor structure and the second capacitor structure are electrically connected via the first external electrode.

13. The chip component according to claim 11, wherein the first capacitor structure and the second capacitor structure are electrically connected via the second external electrode.

14. The second capacitor structure includes a plurality of capacitor elements electrically connected in parallel with each other. The chip component according to claim 11, further comprising a plurality of fuse sections individually arranged between the plurality of capacitor elements and the second external electrode.

15. The chip component according to claim 1 or 2, comprising two first capacitor structures located on either side of the second capacitor structure in a plan view.

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