Semiconductor device, semiconductor module, and method for manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device, a semiconductor module, and a method for manufacturing a semiconductor device which make it possible to suppress a decrease in Vth due to a front surface electrode deficiency or a defect on a gate insulating film. This semiconductor device is provided with: a semiconductor substrate (10); an interlayer insulating film (9) provided over a first main surface of the semiconductor substrate (10); a contact hole (20) penetrating the interlayer insulating film (9) and reaching the semiconductor substrate (10); a plug electrode (15) filled in the contact hole (20); a first barrier metal (25a) provided over the plug electrode (15) and the interlayer insulating film (9); and a front surface electrode (11) provided over the first barrier metal (25a).

Description

Semiconductor device, semiconductor module, and method of manufacturing the semiconductor device

[0001] The present invention relates to a semiconductor device, a semiconductor module, and a method for manufacturing a semiconductor device.

[0002] Conventionally, semiconductor devices have been known in which an opening is provided in a barrier metal layer on an interlayer insulating film to increase the amount of hydrogen that reaches the substrate and suppress a decrease in threshold voltage (see, for example, Patent Document 1 below). Also known is a semiconductor device in which a first metal film of the barrier metal is made of a Group VIII metal material such as nickel (Ni) or cobalt (Co) so that hydrogen reaches a silicon surface that has been damaged by electron beam irradiation or the like during hydrogen annealing (see, for example, Patent Document 2 below).

[0003] JP 2005-327799 A Japanese Patent No. 5672719 A

[0004] Conventional semiconductor devices have had problems with front-surface electrode defects, which allow ions to reach the gate insulating film through the front-surface electrode defects, or defects formed on the gate insulating film, resulting in a decrease in Vth. An object of the present invention is to provide a semiconductor device, a semiconductor module, and a method for manufacturing a semiconductor device that can suppress the decrease in Vth due to front-surface electrode defects and defects on the gate insulating film.

[0005] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: The semiconductor device includes a semiconductor substrate, an interlayer insulating film provided on a first main surface of the semiconductor substrate, a contact hole that penetrates the interlayer insulating film to reach the semiconductor substrate, a plug electrode filled in the contact hole, a first barrier metal provided on the plug electrode and the interlayer insulating film, and a front surface electrode provided on the first barrier metal.

[0006] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: The semiconductor device includes a semiconductor substrate, an interlayer insulating film provided on a first main surface of the semiconductor substrate, a contact hole that penetrates the interlayer insulating film to reach the semiconductor substrate, a plug electrode that fills the contact hole and is further provided on the interlayer insulating film, a first barrier metal provided on the plug electrode, and a front surface electrode provided on the first barrier metal.

[0007] Furthermore, in the semiconductor device according to the present invention, a second barrier metal is provided between a side surface of the plug electrode and the interlayer insulating film.

[0008] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a third barrier metal is provided between the plug electrode and the semiconductor substrate.

[0009] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: The semiconductor device includes a semiconductor substrate, an interlayer insulating film provided on a first main surface of the semiconductor substrate, a contact hole penetrating the interlayer insulating film to reach the semiconductor substrate, a plug electrode filled in the contact hole, a first barrier metal provided on the interlayer insulating film, a second barrier metal provided between a side surface of the plug electrode and the interlayer insulating film, a third barrier metal provided between the plug electrode and the semiconductor substrate, and a front surface electrode provided on the first barrier metal, wherein the first barrier metal, the second barrier metal, and the third barrier metal are each composed of a different composition.

[0010] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the first barrier metal is provided between the front surface electrode and the plug electrode.

[0011] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a back electrode is provided on a second main surface opposite to the first main surface.

[0012] Furthermore, the semiconductor device according to the present invention, in the above-described invention, further comprises, on the first main surface side, a gate electrode insulated from the semiconductor substrate by a gate insulating film and insulated from the front surface electrode by the interlayer insulating film, and a first impurity layer of a conductivity type complementary to that of the semiconductor substrate, selectively provided in contact with the gate insulating film within the semiconductor substrate, wherein the first impurity layer is electrically connected to the front surface electrode via the contact hole.

[0013] In addition, in the semiconductor device according to the present invention, the gate electrode is provided in a trench dug from the first main surface of the semiconductor substrate.

[0014] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a second impurity layer having a higher impurity concentration than the semiconductor substrate is selectively provided within the first impurity layer, and the second impurity layer is in contact with the gate insulating film and is electrically connected to the front surface electrode via the contact hole.

[0015] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a lifetime control region in which a lifetime is controlled is provided inside the semiconductor substrate.

[0016] In addition, in the semiconductor device according to the present invention, the front surface electrode is made of a metal containing Al as a main component.

[0017] In addition, in the semiconductor device according to the present invention, the front surface electrode includes a laminated structure of W and a metal containing Al as a main component from the first barrier metal side.

[0018] In addition, in the semiconductor device according to the present invention, the first barrier metal is TiN.

[0019] In addition, in the semiconductor device according to the present invention, the plug electrode is made of W.

[0020] In addition, in the semiconductor device according to the present invention, the second barrier metal is a laminate of Ti and TiN.

[0021] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor module according to the present invention has the following features: The semiconductor module includes the semiconductor device described above, in which a conductive wire is bonded to the front surface electrode.

[0022] In addition, in the semiconductor module according to the present invention, the conductive wires are made of a metal containing Cu as a main component.

[0023] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor module according to the present invention has the following features: In the semiconductor module, the semiconductor device of the above-mentioned semiconductor device is sealed with resin.

[0024] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. First, a first step is performed in which an interlayer insulating film is laminated on a first main surface of a semiconductor substrate. Next, a second step is performed in which a contact hole is formed that penetrates the interlayer insulating film and reaches the semiconductor substrate. Next, a third step is performed in which a plug electrode is laminated on the interlayer insulating film and in the contact hole. Next, a fourth step is performed in which the plug electrode on the interlayer insulating film is removed and the plug electrode remains only in the contact hole. Next, a fifth step is performed in which a first barrier metal is laminated on the plug electrode and the interlayer insulating film. Next, a sixth step is performed in which a front surface electrode is laminated on the first barrier metal. Each step is performed in this order.

[0025] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. First, a first step is performed in which an interlayer insulating film is laminated on a first main surface of a semiconductor substrate. Next, a second step is performed in which contact holes are formed that penetrate the interlayer insulating film and reach the semiconductor substrate. Next, a third step is performed in which plug electrodes are laminated on the interlayer insulating film and in the contact holes. Next, a fourth step is performed in which a first barrier metal is laminated on the plug electrode and the interlayer insulating film. Next, a fifth step is performed in which a front surface electrode is laminated on the first barrier metal. Each step is performed in this order.

[0026] To solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. First, a first step is performed in which an interlayer insulating film is deposited on a first main surface of a semiconductor substrate. Next, a second step is performed in which a contact hole is formed through the interlayer insulating film to reach the semiconductor substrate. Next, a third step is performed in which an initial barrier metal is deposited on the interlayer insulating film and in the contact hole. Next, a fourth step is performed in which the initial barrier metal in contact with the semiconductor substrate is chemically transformed by heat treatment to form a third barrier metal, and a second barrier metal is formed from the initial barrier metal that has not been chemically transformed. Next, a fifth step is performed in which a plug electrode is deposited on the second barrier metal and the third barrier metal. Next, a sixth step is performed in which the plug electrode on the interlayer insulating film is removed, leaving the plug electrode only in the contact hole. Next, a seventh step is performed in which the second barrier metal on the interlayer insulating film is removed, leaving the second barrier metal only in the contact hole. Next, an eighth step is performed in which a first barrier metal is deposited on the plug electrode and the interlayer insulating film. Next, a ninth step is performed in which a front surface electrode is laminated on the first barrier metal. Each step is performed in this order.

[0027] In addition, the manufacturing method of a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, it further includes a tenth step after the eighth step, of removing the first barrier metal on the plug electrode and leaving the first barrier metal only on the interlayer insulating film.

[0028] In addition, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, it further includes an eleventh step of forming a lifetime control region, the lifetime of which is controlled, inside the semiconductor substrate by irradiation with a particle beam.

[0029] Furthermore, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal element contained in the first barrier metal is different from the metal element contained in the second barrier metal.

[0030] In addition, in the semiconductor device according to the present invention, the metal element contained in the first barrier metal is different from the metal element contained in the third barrier metal.

[0031] In addition, in the semiconductor device according to the present invention, the first barrier metal is formed by stacking a plurality of layers.

[0032] In addition, in the semiconductor device according to the present invention, the plug electrode and the surface electrode have different metal elements, and the first barrier metal contains the same metal element as the plug electrode.

[0033] In addition, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the first barrier metal is formed by stacking a layer containing a metal element contained in the second barrier metal and a layer containing the same metal element as the plug electrode.

[0034] In addition, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the first barrier metal is formed by stacking a layer containing a metal element contained in the third barrier metal and a layer containing the same metal element as the plug electrode.

[0035] In addition, the manufacturing method of a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, in the eighth step, the first barrier metal is stacked on the plug electrode and the interlayer insulating film as a film containing a metal element different from the metal element contained in the initial barrier metal.

[0036] In addition, the manufacturing method of a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, in the eighth step, the first barrier metal is formed by stacking a layer containing a metal element contained in the initial barrier metal and a layer consisting of a different metal element on the plug electrode and the interlayer insulating film.

[0037] In addition, the manufacturing method of a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, in the eighth step, the first barrier metal is stacked on the plug electrode and the interlayer insulating film as a film containing the same metal element as the plug electrode, and in the ninth step, the front surface electrode is stacked on the first barrier metal as a film containing a metal element different from that of the plug electrode.

[0038] In addition, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, in the eighth step, the first barrier metal is stacked on the plug electrode and the interlayer insulating film by stacking a layer containing a metal element contained in the initial barrier metal and a layer containing the same metal element as the plug electrode, and in the ninth step, the front surface electrode is stacked on the first barrier metal as a film containing a metal element different from that of the plug electrode.

[0039] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: The semiconductor device includes a semiconductor substrate, a polycrystalline portion provided above or within a first main surface of the semiconductor substrate, an interlayer insulating film provided on the polycrystalline portion, a contact hole that penetrates the interlayer insulating film to reach the polycrystalline portion, a plug electrode filled in the contact hole, a first barrier metal provided on the plug electrode and the interlayer insulating film, and a front surface electrode provided on the first barrier metal.

[0040] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: The semiconductor device includes a semiconductor substrate, a polycrystalline portion provided above or within a first main surface of the semiconductor substrate, an interlayer insulating film provided on the polycrystalline portion, a contact hole that penetrates the interlayer insulating film to reach the polycrystalline portion, a plug electrode that fills the contact hole and is further provided on the interlayer insulating film, a first barrier metal provided on the plug electrode, and a front surface electrode provided on the first barrier metal.

[0041] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: The semiconductor device includes a semiconductor substrate, a polycrystalline portion provided above or within a first main surface of the semiconductor substrate, an interlayer insulating film provided on the polycrystalline portion, a contact hole that penetrates the interlayer insulating film to reach the polycrystalline portion, a plug electrode filled in the contact hole, a first barrier metal provided on the interlayer insulating film, a second barrier metal provided between a side surface of the plug electrode and the interlayer insulating film, a third barrier metal provided between the plug electrode and the polycrystalline portion, and a front surface electrode provided on the first barrier metal, wherein the first barrier metal, the second barrier metal, and the third barrier metal are each composed of a different composition.

[0042] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. First, a twelfth step is performed in which a polycrystalline portion is formed above or within a first main surface of a semiconductor substrate. Next, a first step is performed in which an interlayer insulating film is stacked on the polycrystalline portion. Next, a second step is performed in which a contact hole is formed that penetrates the interlayer insulating film and reaches the polycrystalline portion. Next, a third step is performed in which a plug electrode is stacked on the interlayer insulating film and in the contact hole. Next, a fourth step is performed in which the plug electrode on the interlayer insulating film is removed, leaving the plug electrode only in the contact hole. Next, a fifth step is performed in which a first barrier metal is stacked on the plug electrode and the interlayer insulating film. Next, a sixth step is performed in which a front surface electrode is stacked on the first barrier metal. Each step is performed in this order.

[0043] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. First, a twelfth step is performed in which a polycrystalline portion is formed above or within a first main surface of a semiconductor substrate. Next, a first step is performed in which an interlayer insulating film is stacked on the polycrystalline portion. Next, a second step is performed in which a contact hole is formed that penetrates the interlayer insulating film and reaches the polycrystalline portion. Next, a third step is performed in which a plug electrode is stacked on the interlayer insulating film and in the contact hole. Next, a fourth step is performed in which a first barrier metal is stacked on the plug electrode and the interlayer insulating film. Next, a fifth step is performed in which a front surface electrode is stacked on the first barrier metal. Each step is performed in this order.

[0044] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. First, a twelfth step is performed in which a polycrystalline portion is formed above or within a first main surface of a semiconductor substrate. Next, a first step is performed in which an interlayer insulating film is stacked on the polycrystalline portion. Next, a second step is performed in which a contact hole is formed through the interlayer insulating film to reach the polycrystalline portion. Next, a third step is performed in which an initial barrier metal is stacked on the interlayer insulating film and within the contact hole. Next, a fourth step is performed in which the initial barrier metal in contact with the polycrystalline portion is chemically transformed by heat treatment to form a third barrier metal, and a second barrier metal is formed from the initial barrier metal that has not been chemically transformed. Next, a fifth step is performed in which a plug electrode is stacked on the second barrier metal and the third barrier metal. Next, a sixth step is performed in which the plug electrode on the interlayer insulating film is removed, leaving the plug electrode only in the contact hole. Next, a seventh step is performed in which the second barrier metal on the interlayer insulating film is removed, leaving the second barrier metal only in the contact hole. Next, an eighth step is performed in which a first barrier metal is deposited on the plug electrode and the interlayer insulating film. Next, a ninth step is performed in which a front surface electrode is deposited on the first barrier metal. Each step is performed in this order.

[0045] The semiconductor device, semiconductor module, and method for manufacturing a semiconductor device according to the present invention have the effect of suppressing a decrease in Vth due to defects in the front surface electrode or defects on the gate insulating film.

[0046] FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view showing a structure of an electrode of the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing a structure of a semiconductor module according to the first embodiment. FIG. 4 is a cross-sectional view showing an effect of the semiconductor device according to the first embodiment (part 1). FIG. 5 is a cross-sectional view showing an effect of the semiconductor device according to the first embodiment (part 2). FIG. 6 is a cross-sectional view showing an effect of the semiconductor device according to the first embodiment (part 3). FIG. 7 is a cross-sectional view showing a schematic diagram of electrode formation in a method for manufacturing a semiconductor device according to the first embodiment (part 1). FIG. 8 is a cross-sectional view showing a schematic diagram of electrode formation in a method for manufacturing a semiconductor device according to the first embodiment (part 2). FIG. 9 is a cross-sectional view showing a schematic diagram of electrode formation in a method for manufacturing a semiconductor device according to the first embodiment (part 3). FIG. 10 is a cross-sectional view showing a schematic diagram of electrode formation in a method for manufacturing a semiconductor device according to the first embodiment (part 4). FIG. 11 is a cross-sectional view showing a schematic diagram of electrode formation in a method for manufacturing a semiconductor device according to the first embodiment (part 5). FIG. 12 is a cross-sectional view showing another structure of an electrode of the semiconductor device according to the first embodiment (part 1). FIG. 13 is a cross-sectional view showing another structure of an electrode of the semiconductor device according to the first embodiment (part 2). FIG. 14 is a cross-sectional view (part 3) showing another structure of an electrode of the semiconductor device according to the first embodiment. FIG. 15 is a cross-sectional view (part 4) showing another structure of an electrode of the semiconductor device according to the first embodiment. FIG. 16 is a cross-sectional view (part 5) showing another structure of an electrode of the semiconductor device according to the first embodiment. FIG. 17 is a cross-sectional view (part 6) showing another structure of an electrode of the semiconductor device according to the first embodiment. FIG. 18 is a cross-sectional view (part 7) showing another structure of an electrode of the semiconductor device according to the first embodiment. FIG. 19 is a cross-sectional view showing a structure of an electrode of the semiconductor device according to the second embodiment. FIG. 20 is a cross-sectional view showing another structure of an electrode of the semiconductor device according to the second embodiment. FIG. 21 is a cross-sectional view showing a structure in the vicinity of a signal electrode pad of the semiconductor device according to the third embodiment. FIG. 22 is a cross-sectional view showing another structure in the vicinity of a signal electrode pad of the semiconductor device according to the third embodiment. FIG. 23 is a cross-sectional view showing another structure in the vicinity of a signal electrode pad of the semiconductor device according to the third embodiment.FIG. 24 is a cross-sectional view (part 1) showing electrode formation in a conventional semiconductor device manufacturing method. FIG. 25 is a cross-sectional view (part 2) showing electrode formation in a conventional semiconductor device manufacturing method. FIG. 26 is a cross-sectional view (part 3) showing electrode formation in a conventional semiconductor device manufacturing method. FIG. 27 is a cross-sectional view (part 4) showing electrode formation in a conventional semiconductor device manufacturing method. FIG. 28 is a cross-sectional view (part 5) showing electrode formation in a conventional semiconductor device manufacturing method. FIG. 29 is a cross-sectional view (part 6) showing electrode formation in a conventional semiconductor device manufacturing method. FIG. 30 is a cross-sectional view (part 7) showing electrode formation in a conventional semiconductor device manufacturing method. FIG. 31 is a cross-sectional view showing a Vth decrease in a conventional semiconductor device using a partial barrier metal removal method. FIG. 32 is a cross-sectional view (part 1) showing Vth decrease in a conventional semiconductor device using a full-surface barrier metal leaving method. FIG. 33 is a cross-sectional view (part 2) showing Vth decrease in a conventional semiconductor device using a full-surface barrier metal leaving method. FIG. 34 is a cross-sectional view showing a structure in the vicinity of a signal electrode pad in a conventional semiconductor device.

[0047] Preferred embodiments of a semiconductor device, a semiconductor module, and a method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. Furthermore, descriptions of "same" or "equivalent" should preferably include a range of ±5% to take into account variations in manufacturing.

[0048] First Embodiment First, a conventional method for manufacturing a semiconductor device will be described. The conventional method for manufacturing a semiconductor device will be described using an RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) as an example. The RC-IGBT is formed by integrating, for example, an IGBT with a trench gate structure and an FWD (Free Wheeling Diode) connected in anti-parallel to the IGBT on the same semiconductor substrate (semiconductor chip).

[0049] First, the thick n - A semiconductor substrate (semiconductor wafer) is prepared. Next, a surface device structure such as a MOS (Metal Oxide Semiconductor) gate (an insulating gate made of a metal-oxide-semiconductor) is formed by a general method. For example, - n-type semiconductor substrate - On the front surface of the n-type drift layer, an n-type accumulation layer, a p-type base region, a trench, and an n-type + type emitter region, p + A contact region, a gate insulating film, a gate electrode, etc. are formed. - The surface device structure formed on the semiconductor substrate is referred to as a semiconductor substrate 110. Next, an interlayer insulating film 109 made of two layers, for example, a BPSG film and an HTO film, is deposited (formed) on the surface of the semiconductor substrate 110 so as to cover the gate electrode.

[0050] 24 to 30 are cross-sectional views schematically illustrating electrode formation in a conventional semiconductor device manufacturing method. Next, as shown in FIG. 24, interlayer insulating film 109 is patterned to form contact holes 120. Next, as shown in FIG. 25, a Ti (titanium) film 117 and a TiN (titanium nitride) film 118, which serve as barrier metals, are formed in this order on interlayer insulating film 109 by sputtering. Next, as shown in FIG. 26, a contact plug 115 made of a tungsten (W) film is formed on the barrier metal. Next, as shown in FIG. 27, the Ti film 117, the TiN film 118, and the contact plug 115 in contact hole 120 are etched and removed. Next, as shown in FIG. 28, a front surface metal film 126 made of Al-Si (aluminum silicon alloy) or the like is formed by sputtering, for example, to cover the entire surface of interlayer insulating film 109 and contact plug 115 inside contact hole 120.

[0051] In addition to the method of removing the barrier metal (Ti film 117, TiN film 118) on the interlayer insulating film 109 (hereinafter referred to as the partial barrier metal removal method), there is also a method of leaving the barrier metal (Ti film 117, TiN film 118) on the interlayer insulating film 109 (hereinafter referred to as the entire barrier metal leaving method). In this case, as shown in FIG. 26, contact plugs 115 are formed on the barrier metal, and then, as shown in FIG. 29, contact plugs 115 other than those in contact holes 120 are removed by etching. Next, as shown in FIG. 30, a front surface metal film 126 is formed by, for example, sputtering to cover the entire surface of the interlayer insulating film 109 so as to be in contact with the contact plugs 115 inside the contact holes 120.

[0052] Next, the front surface metal film 126 is patterned. Next, the front surface metal film 126 is annealed to form the front surface electrodes 111 (the emitter electrode, the anode electrode, and each signal electrode pad). Next, n - The n-type semiconductor substrate is ground from the back side to a thickness corresponding to the thickness of the product to be used as a semiconductor device. -A backside device structure is formed on the backside of the polished semiconductor substrate. Next, a passivation film is formed on the front side of the semiconductor wafer so as to cover the edge termination region. Next, the passivation film is patterned to expose the emitter electrode, the anode electrode, and each signal electrode pad. Next, - A lifetime killer control region is formed by introducing hydrogen or helium defects, which act as lifetime killers, into the mold drift region.

[0053] Next, n - A rear electrode (collector electrode and cathode electrode) is formed on the rear surface of the n-type semiconductor substrate. - The mold semiconductor substrate is cut (diced) into individual chips, thereby completing the RC-IGBT chips (semiconductor chips).

[0054] In a conventional semiconductor device manufacturing method, when a surface electrode is formed by a partial barrier metal removal method, Vth (threshold voltage) may decrease. Figure 31 is a cross-sectional view showing the decrease in Vth caused by the conventional partial barrier metal removal method for a semiconductor device. In the conventional semiconductor device, a front surface electrode defect 132 occurs in the front surface electrode 111 due to stress migration or the like, and when this front surface electrode defect 132 reaches the interlayer insulating film 109 as shown in Figure 31, ions 134 in the package resin 116 pass through the front surface electrode defect 132 and reach the gate insulating film 107, causing a problem of a decrease in Vth.

[0055] Furthermore, when the surface electrode is formed by the barrier metal leaving method in a conventional semiconductor device manufacturing method, ions 134 from package resin 116 do not reach gate insulating film 107 because the barrier metal is present on the entire surface, and a decrease in Vth due to front surface electrode defect 132 does not occur. However, even when the barrier metal is formed by the barrier metal leaving method, a decrease in Vth may occur. Figures 32 and 33 are cross-sectional views showing a decrease in Vth when the barrier metal is left on the entire surface of a conventional semiconductor device.

[0056] As shown in FIG. 32, charged particles (H + , He + , e -When hydrogen ions 130 are implanted into the gate insulating film 107, the gate insulating film 107 is damaged, resulting in the formation of defects 133. When the gate insulating film 107 is formed by the partial barrier metal removal method, the defects 133 are repaired by supplying heat and hydrogen (H) to the defective portions during subsequent annealing. However, in the full barrier metal leaving method, in which the barrier metal is left on the entire surface of the interlayer insulating film 109, as shown in FIG. 33, hydrogen 131 that should be supplied to the defective portions during annealing is absorbed by Ti in the barrier metal and does not reach the defects 133 on the gate insulating film 107, preventing the defects 133 from repairing and resulting in a decrease in Vth.

[0057] Furthermore, even if a lifetime control region is not formed, if a defect 133 is generated in the gate insulating film 107 during the manufacturing flow, the defect 133 may not be repaired by annealing, as described above, resulting in a decrease in Vth.

[0058] 34 is a cross-sectional view showing the structure in the vicinity of a signal electrode pad of a conventional semiconductor device. The signal electrode pad is, for example, a gate pad. As shown in FIG. 34, a passivation film 139 is provided on the front surface electrode 111, and a signal electrode pad 160 is exposed through an opening in the passivation film 139. Under the signal electrode pad 160, n - An insulating film 137 is provided on the n-type drift region 101 and the p-type base region 102. - The p-type drift region 101 and the p-type base region 102 are electrically insulated from the connection portion 138. For example, in the case of a gate pad, the insulating film 137 may be formed simultaneously with the gate oxide film 107, the connection portion 138 may be formed simultaneously with the gate electrode 108, and the insulating film 137 may be connected to the gate oxide film 107, and the connection portion 138 may be connected to the gate electrode 108.

[0059] Here, when the barrier metal 125 is left on the interlayer insulating film 109 in the active region, the barrier metal 125 is also left between the front surface electrode 111 and the interlayer insulating film 109 around the signal electrode pad 160. In this case, when a conductive wire is connected to the signal electrode pad 160 during mounting, the barrier metal 125 may peel off, causing the front surface electrode 111 to peel off. For this reason, a polysilicon connection portion 138 is left below the electrode pad 160, and the barrier metal 125 is anchored by the connection portion 138 and the contact plug 115, preventing the barrier metal 125 from peeling off. However, if a defect 133 is generated in the gate insulating film 107 in the active region, the barrier metal 125 on the interlayer insulating film 109 below the signal electrode pad 160 contains Ti, which may prevent the defect 133 from recovering by annealing, resulting in a decrease in Vth.

[0060] A semiconductor device, a semiconductor module, and a method for manufacturing a semiconductor device according to a first embodiment that solves the above-mentioned problems will be described below. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. The structure of the semiconductor device according to the first embodiment will be described using a trench-type RC-IGBT 150 as an example. The semiconductor device according to the first embodiment shown in FIG. 1 is an RC-IGBT 150 in which an IGBT with a trench gate structure and a diode connected in anti-parallel to the IGBT are integrated on the same semiconductor substrate (semiconductor chip). The RC-IGBT 150 includes an active region, which is a region through which current flows when the RC-IGBT 150 is on, and an edge termination region that surrounds the active region; however, FIG. 1 illustrates only the active region.

[0061] The RC-IGBT 150 has an IGBT region (transistor portion) 21 that serves as the operating region of the IGBT and an FWD region (diode portion) 22 that serves as the operating region of the diode, which are arranged in parallel on the same semiconductor substrate as the active region.

[0062] Within the semiconductor wafer 10 in the active region, n -An n-type accumulation layer 5 may be provided in the surface layer of the front surface (first main surface) of the n-type drift layer 1. The n-type accumulation layer 5 is a so-called charge storage layer (CSL) that reduces the spreading resistance of carriers. A p-type base region (first impurity layer) 2 is provided on the n-type accumulation layer 5, extending from the IGBT region 21 to the FWD region 22. The p-type base region 2 functions as a p-type anode region in the FWD region 22. An n-type impurity layer 2 is formed through the p-type base region 2. - A trench 6 is provided in the IGBT region 21 and the FWD region 22, and in the IGBT region 21, n-type + In the edge termination region 2, a p-type emitter region (second impurity layer) 3 is provided. The trenches 6 are arranged at predetermined intervals in, for example, a striped planar layout, and separate the p-type base region 2 into a plurality of regions (mesa portions). A gate insulating film 7 is provided inside the trench 6 along the inner wall of the trench 6, and a gate electrode 8 is provided inside the gate insulating film 7. At least a portion of the gate electrodes 8 may be connected to a gate runner that is wired from the gate electrode pad to a portion of the edge termination region outside the scope of FIG. 1 .

[0063] In the IGBT region 21, inside the p-type base region 2, n-type + The n-type emitter region 3 is selectively provided. + The emitter region 3 faces the gate electrode 8 across a gate insulating film 7 provided on the inner wall of the trench 6. + In this case, n + type emitter region 3 and p + In the FWD region 22, the p-type base region 2 has n + type emitter region 3 and p + The n-type contact region 4 is not provided. The front surface electrode 11 is connected to the n-type contact region 4 via the contact hole 20. + The n-type emitter region 3 is in contact with the n-type emitter region 3 and is electrically insulated from the gate electrode 8 by an interlayer insulating film 9. +An opening may be selectively provided in the p-type emitter region 3, and the front surface electrode 11 and the p-type base region 2 may be electrically connected through the opening. + When the contact region 4 is provided, the front electrode 11 and the p + The front surface electrode 11 functions as an emitter electrode in the IGBT region 21 and as an anode electrode in the FWD region 22. A Ti film 17 and a first TiN film 18 are provided between the front surface electrode 11 and the interlayer insulating film 9 as barrier metal for preventing diffusion of metal atoms from the front surface electrode 11 toward the gate electrode 8. A second TiN film 19 is also provided as barrier metal between the interlayer insulating film 9 and the front surface electrode 11. Note that some of the gate electrodes 8 may be connected to the front surface electrode 11 in the active region or the edge termination region without being connected to the gate runner.

[0064] Alternatively, a contact plug may be embedded in the contact hole 20 formed in the interlayer insulating film 9. The contact plug may be formed, for example, of a metal film made of tungsten (W), which has high embedding properties. The front surface electrode 11 may be formed of an Al film or an Al alloy film such as Al-Si. The front surface electrode 11 may also have a laminated structure of W and Al or Al alloy films from the second TiN film 19 side. By providing W on the second TiN film 19 in this way, mechanical strength can be improved. In cases such as when the cell pitch is wide, a structure in which the contact hole 20 is filled with the front surface electrode 11 without forming a contact plug may be used. Alternatively, the front surface electrode 11 may be made of copper (Cu) or an alloy containing Cu, or a metal film such as Ni or gold (Au) may be laminated on an Al or Al alloy film. Hereinafter, the contact plug or front surface electrode 11 in the contact hole 20 will be referred to as a plug electrode 15. 1 and the following figures, the shape of plug electrode 15 is depicted as being rectangular in cross section and the top surface flush with interlayer insulating film 9, but this is not limiting. The side surfaces may be tapered. The top surface may not be flush with interlayer insulating film 9 and may be recessed. The bottom surface may be a so-called trench contact structure in which the semiconductor wafer 10 is dug below the bottom surface of interlayer insulating film 9.

[0065] 2 is a cross-sectional view showing the structure of an electrode of a semiconductor device according to embodiment 1. In embodiment 1, barrier metal 25 is composed of first barrier metal 25a formed on plug electrode 15 and interlayer insulating film 9, second barrier metal 25b formed between the side surface of plug electrode 15 and interlayer insulating film 9, and third barrier metal 25c formed between plug electrode 15 and semiconductor wafer 10.

[0066] The first barrier metal 25a is, for example, a second TiN film 19, and the second barrier metal 25b and the third barrier metal 25c are, for example, two-layer films formed by stacking a Ti film 17 and a first TiN film 18 in this order. The Ti film 17 ensures contact and adhesion to Si. The first TiN film 18 and the second TiN film 19 prevent Al diffusion from the front electrode 11, prevent erosion by WF gas used in W-CVD, and ensure adhesion to W of the plug electrode 15. Instead of the first TiN film 18 and the second TiN film 19, a Ni (nickel) film or a Ta (tantalum) film may be used. The first TiN film 18 and the second TiN film 19 have a thickness of, for example, 1 nm to 400 nm, preferably 1 nm to 200 nm. The third barrier metal 25c may also include a material formed by chemically changing the barrier metal (initial barrier metal) after film formation that contacts the semiconductor wafer 10 through heat treatment. Here, the chemical change may refer to the formation of an alloy with the underlying Si. On the other hand, the second barrier metal 25b may not undergo a chemical change through heat treatment. Here, "not undergoing a chemical change" does not mean "no reaction at all." It may also include a slight reaction compared to the reaction of the third barrier metal 25c, in which most of the Ti film forms an alloy with Si. For example, the heat treatment may be performed after the formation of the first TiN film 18, and this heat treatment may make the first TiN film 18 of the second barrier metal 25b denser than before the heat treatment. Furthermore, this heat treatment may be performed, for example, after the formation of the Ti film 17 and before the formation of the first TiN film 18. This heat treatment may chemically change the surface of the Ti film 17, for example, forming a thin TiN film on the surface of the Ti film 17. That is, nitridation may occur as a chemical change. The first barrier metal 25a may be the second TiN film 19, the second barrier metal 25b may be the Ti film 17 and the first TiN film 18, and the third barrier metal 25c may be formed by chemically changing the Ti film 17 and the first TiN film 18, with each having a different composition. In particular, if the reaction progresses due to heat treatment, the Ti film 17 may be nitrided to a TiN film. In this case, the first barrier metal 25a and the second barrier metal 25b may have the same composition. Even in this case, the first barrier metal 25a and the second barrier metal 25b may have different film thicknesses.

[0067] Now, let us return to the explanation of FIG. - An n-type field stop (FS) layer 12 is provided on the rear surface of the substrate inside the drift layer 1. The n-type FS layer 12 is connected to the p-type base region 2 and the n-type - The pn junction between the p-type drift layer 1 and the + This has the function of suppressing the extension of the depletion layer toward the collector region 13 .

[0068] Also, n - In the n-type drift layer 1, the FWD region 22 has a larger n-type conductivity than the n-type FS layer 12. - A lifetime control region 26 may be provided at a shallow position from the front surface of the type drift layer 1. The lifetime control region 26 is formed by introducing lattice defects (indicated by cross marks) such as vacancies (V), which act as lifetime killers, by irradiation with hydrogen (H) or helium (He). Forming the lifetime control region 26 can reduce losses in the device. The lifetime control region 26 may extend to the vicinity of the boundary between the IGBT region 21 and the FWD region 22. The lifetime control region 26 may also extend to the chip edge of the edge termination region. When the lifetime control region 26 is formed by irradiation with a highly penetrating particle beam, such as an electron beam, lattice defects are formed substantially uniformly from the front surface to the back surface of the substrate. Even in this case, the depth position of the lifetime control region 26 may be considered to be located on the front surface side of the substrate.

[0069] n - The surface layer on the rear surface (second main surface) side of the n-type drift layer 1 is more n-type than the n-type FS layer 12. - At a shallow position from the rear surface of the drift layer 1, p + The collector region 13 is provided in the FWD region 22. + A cathode region 14 is provided. + The cathode region 14 is p + The back electrode 24 is adjacent to the p-type collector region 13. + collector region 13 and n +The back electrode 24 functions as a collector electrode in the IGBT region 21 and as a cathode electrode in the FWD region 22.

[0070] 3 is a cross-sectional view showing the structure of a semiconductor module according to the first embodiment. In this specification, a semiconductor device refers to a device formed on a semiconductor wafer 10 and cut (diced) into chips, while a semiconductor module refers to a device that has been processed further and is stored in a case or the like and is ready for shipment. As shown in FIG. 3, the semiconductor module 250 includes a semiconductor element 41, which is a semiconductor chip, an insulating substrate 42, bonding materials 43b and 43c, an electrode pattern 44, a metal substrate 45, conductive wires 46, a resin case 47, a sealing resin 16, metal terminals 49, and conductive wires 50.

[0071] The semiconductor element 41 is a semiconductor element such as an RC-IGBT, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor with an insulated gate having a three-layer structure of metal-oxide-semiconductor), or a diode chip. The semiconductor element 41 may be a vertical semiconductor element in which a main current flows in the thickness direction of the chip. An insulating substrate 42, such as a ceramic substrate, is provided with electrode patterns 44 made of a copper plate or the like on its front surface (semiconductor element 41 side) and back surface (metal substrate 45 side). A substrate having electrode patterns 44 on at least one surface of the insulating substrate 42 is referred to as a laminated substrate 52. The semiconductor element 41 is bonded to the electrode pattern 44 on the front surface with a bonding material 43b such as solder. A metal substrate 45 provided with heat dissipation fins (not shown) is bonded to the electrode pattern 44 on the back surface with a bonding material 43c such as solder. Furthermore, one end of a conductive wire 46 made of a metal primarily composed of Al, Cu, Au, or the like is ultrasonically bonded to the top surface of the semiconductor element 41 (the surface opposite to the surface in contact with the bonding material 43b) as wiring for electrical connection. The other end of the conductive wire 46 is ultrasonically bonded to the electrode pattern 44 using the bonding material 43b. The conductive wire 46 may be a wire having a circular cross section, or may be a flat ribbon or the like. The conductive wire 46 may be bonded to the top surface of the semiconductor element 41 or the electrode pattern 44 by laser bonding. In another example, instead of the conductive wire 46, a lead frame may be bonded to the top surface of the semiconductor element 41 or the electrode pattern 44 using a bonding material such as solder.

[0072] The resin case 47 is combined with a laminated assembly in which the semiconductor element 41, the laminated substrate 52, and the metal substrate 45 are laminated. For example, the resin case 47 is bonded to the laminated assembly via an adhesive such as silicone. The interior of the resin case 47 is filled with a sealing resin 16 such as a hard resin such as epoxy, or a gel to insulate and protect the semiconductor element 41 on the laminated substrate 52. A conductive wire 50 that carries a signal current connects the semiconductor device 150 and a metal terminal 49. The metal terminal 49 penetrates the resin case 47 and protrudes to the outside. The electrode pattern 44 may also be connected to the metal terminal 49 by a conductive wire or the like in a region not shown.

[0073] Alternatively, the semiconductor module may be a caseless semiconductor module. While not shown, the caseless semiconductor module may include, for example, implant pins and a printed circuit board bonded to the implant pins instead of the conductive wires 46 and 50 shown in FIG. 3 , and the components including these are sealed with a thermosetting resin sealing layer. In this case, the sealed components including the laminated substrate 52, the semiconductor element 41, the implant pins, and the printed circuit board are assembled, placed in an appropriate mold, and a thermosetting resin composition constituting the thermosetting resin sealing layer is filled into the mold and cured. Examples of molding methods for such a sealed body include vacuum casting, transfer molding, liquid transfer molding, and potting, but the specific molding method is not limited thereto.

[0074] 4 to 6 are cross-sectional views showing the effects of the semiconductor device according to the first embodiment. As shown in FIG. 4, charged particles (H + , He + , e -When charged particles 30 are implanted into the interlayer insulating film 9, the gate insulating film 7 through which the charged particles 30 pass is damaged, resulting in the generation of defects. Furthermore, when charged particles 30 are implanted from the back surface side to create the lifetime control region 26, defects are also generated by the charged particles 30 that pass through the lifetime control region 26 and reach the gate insulating film 7. In the semiconductor device according to the first embodiment, as shown in FIG. 5, the absence of the Ti film on the interlayer insulating film 9 suppresses the absorption of hydrogen (H), and subsequent annealing supplies heat and hydrogen 31 to the defective portions, thereby recovering the defects. This makes it possible to suppress a decrease in Vth due to defects.

[0075] Furthermore, as shown in FIG. 6 , even if a front-surface electrode defect 32 occurs in the front-surface electrode 11 due to stress migration or the like, by sandwiching the second TiN film 19 between the interlayer insulating film 9 and the plug electrode 15 and the front-surface electrode 11, it is possible to prevent ions in the package resin 16 from reaching the gate insulating film 7 through the front-surface electrode defect 32, and it is possible to prevent a decrease in Vth due to the front-surface electrode defect 32.

[0076] (Method of Manufacturing a Semiconductor Device According to the First Embodiment) Next, a method of manufacturing a semiconductor device according to the first embodiment will be described. Note that the method of manufacturing a semiconductor device described below may be carried out by appropriately changing the content and order. First, n - n-type drift region 1 - A mold semiconductor wafer 10 is prepared. The material of the semiconductor wafer 10 may be silicon (Si), silicon carbide (SiC), gallium nitride (GaN), diamond (C), or gallium oxide (Ga2O3), and may be either an element or a compound. The following description will be given taking the case where the semiconductor wafer 10 is a silicon wafer as an example.

[0077] Next, a set of steps of photolithography and ion implantation is repeatedly performed under different conditions to form a surface device structure including a MOS structure on the front surface side of the semiconductor wafer 10. For example, first, the p-type base region 2 of the IGBT, n + type emitter region 3 and p +The p-type contact region 4 is formed on the n-type semiconductor layer 1. The p-type base region 2 is formed on the entire surface of the active region, from the IGBT region 21 to the FWD region 22. The p-type base region 2 also serves as a p-type anode region in the FWD region 22. + type emitter region 3 and p + The p-type contact region 4 is selectively formed inside the p-type base region 2 in the IGBT region 21 .

[0078] The semiconductor wafer 10 has a p-type base region 2 and an n-type field stop (FS) layer 12 (described later), + collector region 13 and n + The portion other than the cathode region 14 is n - In the IGBT region 21, - An n-type accumulation layer 5 may be formed between the n-type drift region 1 and the p-type base region 2. The n-type accumulation layer 5 is an n-type accumulation layer when the IGBT is conductive. - It acts as a barrier to minority carriers (holes) in the n-type drift region 1, - The type drift region 1 has a function of accumulating minority carriers.

[0079] Next, the front surface of the semiconductor wafer 10 is thermally oxidized to form a field oxide film covering the front surface of the semiconductor wafer 10 in the edge termination region. Next, n-type oxide films are formed in the IGBT region 21 by photolithography and etching. + The n-type emitter region 3, the p-type base region 2, and the n-type accumulation layer 5 are - Trenches 6 are formed so as to reach the type drift region 1. When viewed from the front surface side of the semiconductor wafer 10, the trenches 6 are arranged in a stripe-like layout extending in a direction (depth direction in FIG. 1 ) perpendicular to the direction in which the IGBT region 21 and the FWD region 22 are aligned (horizontal direction in FIG. 1 ).

[0080] The trenches 6 are also formed in the FWD region 22 in the same layout as in the IGBT region 21. In the FWD region 22, the trenches 6 penetrate the p-type base region 2 (p-type anode region) to form n-type trenches. -The gate electrode 8 is then formed on the front surface of the semiconductor wafer 10, and the gate insulating film 7 is then formed on the front surface of the semiconductor wafer 10, so as to fill the trench 6. The gate electrode 8 then reaches the mold drift region 1. Next, a gate insulating film 7 is formed along the inner wall of the trench 6, for example, by thermal oxidation. Next, a polysilicon (poly-Si) layer is formed on the front surface of the semiconductor wafer 10, so as to fill the trench 6. Next, this polysilicon layer is etched back, for example, to leave a portion that will become the gate electrode 8 inside the trench 6.

[0081] These p-type base regions 2, n + type emitter region 3, p + The contact region 4, the trench 6, the gate insulating film 7, and the gate electrode 8 constitute a MOS gate having a trench gate structure. + type emitter region 3, p + An n-type contact region 4 and an n-type accumulation layer 5 may be formed. + The n-type emitter region 3 may be disposed in at least one mesa region between adjacent trenches 6 (mesa portion). + There may be a mesa portion where the n-type emitter region 3 is not disposed. + The emitter regions 3 may be selectively arranged at predetermined intervals in the direction in which the trenches 6 extend in a stripe shape.

[0082] 7 to 11 are cross-sectional views schematically showing electrode formation in the semiconductor device manufacturing method according to the first embodiment. After the surface device structure is formed, an interlayer insulating film 9 made of two layers, for example, a BPSG film and an HTO film, is formed on the front surface of the semiconductor wafer 10 so as to cover the gate electrode 8. Next, the interlayer insulating film 9 is patterned to form a plurality of contact holes 20 penetrating the interlayer insulating film 9 in the depth direction. The state up to this point is shown in FIG. 7. The depth direction is the direction from the front surface to the back surface of the semiconductor wafer 10. The contact holes 20 in the IGBT region 21 are provided with n + type emitter region 3 and p + The p-type contact region 4 is exposed. The p-type base region 2 is exposed in the contact hole 20 of the FWD region 22. In FIGS. + type emitter region 3, p +The p-type contact region 4 and the p-type base region 2 are not shown, and only the semiconductor wafer 10 is shown.

[0083] Next, a Ti film (initial barrier metal) 17 is uniformly formed in the contact hole 20 and on the surface of the interlayer insulating film 9 by sputtering. Next, a first TiN film (initial barrier metal) 18 is formed on the surface of the Ti film 17 by sputtering. The state up to this point is shown in FIG. 8 . Next, a third barrier metal 25c may be formed by chemically changing the initial barrier metal in contact with the semiconductor wafer 10 by heat treatment. Here, the chemical change may refer to the formation of an alloy with the underlying Si. Meanwhile, the second barrier metal 25b is formed in contact with the interlayer insulating film 9 by the initial barrier metal that has not been chemically changed by the heat treatment. Here, "no chemical change" does not mean no reaction at all, but may also include a slight reaction compared to the reaction of the third barrier metal 25c, in which most of the Ti film forms an alloy with Si. For example, heat treatment may be performed after the formation of the first TiN film 18, and this heat treatment may make the first TiN film 18 of the second barrier metal 25b denser than before the heat treatment. This heat treatment may be performed, for example, after the formation of the Ti film 17 and before the formation of the first TiN film 18. This heat treatment may cause a chemical change on the surface of the Ti film 17, for example, a TiN film may be formed on the surface of the Ti film 17 by reaction with the atmosphere. That is, nitridation may occur as a chemical change.

[0084] Next, the surface of the first TiN film 18 (second barrier metal 25b and third barrier metal 25c) and the inside of the contact hole 20 are filled with the plug electrode 15 by, for example, CVD. The state up to this point is shown in FIG. 9. Next, the plug electrode 15 outside the contact hole 20 is removed by etching, and the plug electrode 15 is formed inside the contact hole 20. Next, the Ti film 17 and the first TiN film 18 (second barrier metal 25b) outside the contact hole 20 that are not covered by the plug electrode 15 are removed by etching, and the second barrier metal 25b is left between the plug electrode 15 and the interlayer insulating film 9 inside the contact hole 20. The state up to this point is shown in FIG. 10.

[0085] Next, for example, a second TiN film 19, which will become the first barrier metal 25a, is uniformly formed on the surfaces of the interlayer insulating film 9 and the plug electrode 15 by sputtering. The state up to this point is shown in FIG. 11 . After this, the second TiN film 19 on the plug electrode 15 may be removed, leaving only the second TiN film 19 on the interlayer insulating film 9. Next, a front-surface metal film, which will become the front-surface electrode 11, is formed by sputtering, for example. The front-surface metal film may be made of aluminum containing 1% silicon (Al-Si), for example. Next, the front-surface metal film is patterned. The patterned front-surface metal film is then annealed in a hydrogen atmosphere to form the front-surface electrode 11. This completes the formation of the electrode shown in FIG. 2 .

[0086] The front surface electrode 11 is connected to the p-type base region 2 and the n-type + type emitter region 3 and p + The front surface electrode 11 is electrically connected to the p-type contact region 4 and functions as an emitter electrode. The front surface electrode 11 is electrically connected to the p-type base region 2 in the FWD region 22 and functions as an anode electrode. + The p-type emitter region 3 may be electrically connected to the p-type base region 2 in the mesa portion where the p-type emitter region 3 is not disposed.

[0087] Next, the semiconductor wafer 10 is ground from the backside to a thickness corresponding to the thickness of the semiconductor device. Next, a set of photolithography and ion implantation processes is repeatedly performed under different conditions to form a backside device structure on the backside of the semiconductor wafer 10. For example, an n-type field stop (FS) layer 12, an n-type field stop (FS) layer 13, and an n-type field stop (FS) layer 14 are formed on the backside of the semiconductor wafer 10. + type cathode region 14 and p + A mold collector region 13 is formed.

[0088] n + The n-type cathode region 14 is formed over the entire back surface of the semiconductor wafer 10 in a surface layer on the back surface of the semiconductor wafer 10 after grinding. The n-type field stop layer 12 is formed on the n-type field stop layer 12 from the back surface of the semiconductor wafer 10 after grinding. +The n-type field stop layer 12 is formed at a position deeper than the n-type cathode region 14. The n-type field stop layer 12 is formed at least from the IGBT region 21 to the FWD region 22. The n-type field stop layer 12 is + The cathode region 14 may be in contact with the cathode region 14 .

[0089] Next, photolithography and ion implantation are performed to form n + The portion of the cathode region 14 corresponding to the IGBT region 21 is p + By changing it to the type p + A p-type collector region 13 is formed. + The collector region 13 is n-type in the direction in which the IGBT region 21 and the FWD region 22 are aligned. + The cathode region 14 is in contact with the + The n-type collector region 13 may be in contact with the n-type field stop layer 12 in the depth direction.

[0090] Next, by heat treatment (annealing), p + collector region 13 and n + The FS layer 12 is activated. Next, a passivation film is formed on the front surface of the semiconductor wafer 10 so as to cover the edge termination region. Next, the passivation film is patterned to expose the emitter electrode, the anode electrode, and each signal electrode pad.

[0091] Next, a photoresist film (not shown) having an opening corresponding to the FWD region 22 is formed on the front surface of the semiconductor wafer 10. The opening may include the IGBT region 21. Using this photoresist film as a mask (shielding film), helium is irradiated with high acceleration energy and a deep range to form n - A lifetime control region 26 may be formed by introducing (forming) helium defects that act as lifetime killers inside the mold drift region 1 .

[0092] Then, the photoresist film is removed by ashing. Next, a back surface electrode 24 is formed on the entire back surface of the semiconductor wafer 10. The back surface electrode 24 is p + collector region 13 and n +The back electrode 24 functions as a collector electrode and also as a cathode electrode. The semiconductor wafer 10 is then cut (diced) into individual chips, thereby completing the RC-IGBT chips 150 (semiconductor chips).

[0093] Furthermore, the electrodes of the semiconductor device according to the first embodiment are not limited to the structure shown in Fig. 2. Figs. 12 to 18 are cross-sectional views showing other structures of the electrodes of the semiconductor device according to the first embodiment. These other electrode structures also have the same effect as the electrode structure shown in Fig. 2. These structures are manufactured by appropriately modifying the manufacturing method described with reference to Figs. 7 to 11.

[0094] 12 shows a case where the barrier metal 25 is only a first barrier metal 25a made of a second TiN film 19. In other words, the second barrier metal 25b and the third barrier metal 25c are not provided inside the contact hole 20. In addition, the first barrier metal 25a (second TiN film 19) is provided on the surfaces of the interlayer insulating film 9 and the plug electrode 15.

[0095] 13 shows a configuration in which the barrier metal 25 consists only of a first barrier metal 25a made of a second TiN film 19, and the plug electrode 15 is also provided on the surface of the interlayer insulating film 9. The first barrier metal 25a is provided on the surface of the plug electrode 15, and the front surface electrode 11 is provided on the surface of the first barrier metal 25a.

[0096] 14 shows the case where the barrier metal 25 is made up of a first barrier metal 25a composed of a second TiN film 19 and a second barrier metal 25b composed of a Ti film 17 and a first TiN film 18. In other words, a third barrier metal 25c is not provided between the plug electrode 15 and the semiconductor wafer 10. In addition, the first barrier metal 25a is provided on the surfaces of the interlayer insulating film 9 and the plug electrode 15.

[0097] 15 shows a configuration in which the barrier metal 25 is made up of a first barrier metal 25a composed of a second TiN film 19 and a second barrier metal 25b composed of a Ti film 17 and a first TiN film 18, and the plug electrode 15 is also provided on the surface of the interlayer insulating film 9. The first barrier metal 25a is provided on the surface of the plug electrode 15, and a front surface electrode 11 is provided on the surface of the first barrier metal 25a.

[0098] 16 shows the case where the barrier metal 25 is made up of a first barrier metal 25a composed of a second TiN film 19 and a third barrier metal 25c composed of a Ti film 17 and a first TiN film 18. In other words, the second barrier metal 25b is not provided between the side surface of the plug electrode 15 and the interlayer insulating film 9. In addition, the first barrier metal 25a is provided on the surfaces of the interlayer insulating film 9 and the plug electrode 15.

[0099] 17 shows a configuration in which the barrier metal 25 is made up of a first barrier metal 25a composed of a second TiN film 19 and a third barrier metal 25a composed of a Ti film 17 and a first TiN film 18, and the plug electrode 15 is also provided on the surface of the interlayer insulating film 9. The first barrier metal 25a is provided on the surface of the plug electrode 15, and a front surface electrode 11 is provided on the surface of the first barrier metal 25a.

[0100] 18 shows a case where a third barrier metal 25c and a second barrier metal 25b are formed from a Ti film 17 and a first TiN film 18, and the first barrier metal 25a (second TiN film 19) is not provided on the surface of the plug electrode 15. In other words, a front surface electrode 11 is provided on the surface of the plug electrode 15. The structure shown in FIG. 18 is a configuration in which the first barrier metal 25a on the surface of the plug electrode 15 is selectively removed from the structure shown in FIG. 2. This improves the adhesion between the plug electrode 15 and the front surface electrode 11. However, the structure shown in FIG. 18 requires more steps and costs than the configuration shown in FIG. 2, and therefore the structure shown in FIG. 2 is preferable.

[0101] As described above, according to the first embodiment, the absence of a Ti film on the interlayer insulating film suppresses hydrogen absorption. This allows heat and hydrogen to be supplied to defective portions of the gate insulating film by annealing, thereby repairing the defects. This makes it possible to suppress a decrease in Vth due to defects in the gate insulating film. Furthermore, by sandwiching a second TiN film between the interlayer insulating film and the front electrode, it is possible to prevent ions in the package resin from reaching the gate insulating film through defects in the front electrode. This makes it possible to suppress a decrease in Vth due to defects in the front electrode.

[0102] 19 is a cross-sectional view showing the structure of an electrode of a semiconductor device according to a second embodiment. In the second embodiment, the structure is the same as that of the first embodiment except for the electrode structure, and therefore a description of the element structure will be omitted (see FIG. 1). The second embodiment differs from the first embodiment in the first barrier metal 25a, while the structures of the second barrier metal 25b and the third barrier metal 25c are the same as those of the first embodiment.

[0103] In the second embodiment, the metal element contained in first barrier metal 25a formed on plug electrode 15 and interlayer insulating film 9 is different from the metal elements contained in second barrier metal 25b and third barrier metal 25c. For example, in the structure of Fig. 19, first barrier metal 25a is made of W film 27 containing tungsten (W) that is not contained in second barrier metal 25b and third barrier metal 25c, and does not contain Ti that is not contained in second barrier metal 25b and third barrier metal 25c.

[0104] Also, as shown in FIG. 19 , in the second embodiment, the plug electrode 15 is made of W, which has a metal element different from the Al of the front surface electrode 11, and the first barrier metal 25 a has a W film 27 which contains the same metal element as the plug electrode 15.

[0105] (Method of Manufacturing a Semiconductor Device According to Embodiment 2) The semiconductor device according to embodiment 2 is formed in the same manner as the semiconductor device according to embodiment 1. First, as in embodiment 1, a surface device structure is formed, and then an interlayer insulating film 9 made of two layers, for example, a BPSG film and an HTO film, is formed on the front surface of the semiconductor wafer 10 so as to cover the gate electrode 8. Next, the interlayer insulating film 9 is patterned to form a plurality of contact holes 20 that penetrate the interlayer insulating film 9 in the depth direction.

[0106] Next, a Ti film (initial barrier metal) 17 and a first TiN film (initial barrier metal) 18 are uniformly formed by sputtering inside the contact hole 20 and on the surface of the interlayer insulating film 9. Next, a third barrier metal 25c including a material formed by chemically changing the initial barrier metal in contact with the semiconductor wafer 10 may be formed by heat treatment. Furthermore, a second barrier metal 25b is formed in contact with the interlayer insulating film 9 from the initial barrier metal that was not chemically changed by the heat treatment.

[0107] Next, for example, by CVD, a plug electrode 15 is stacked on the second barrier metal 25b and the third barrier metal 25c to fill the inside of the contact hole 20 with the plug electrode 15. Next, the plug electrode 15 above the upper surface of the interlayer insulating film 9 is removed, and then the second barrier metal 25b exposed above the upper surface of the interlayer insulating film 9 is removed to leave the second barrier metal 25b in the contact hole 20.

[0108] 19, a W film 27 is then formed uniformly on the surfaces of the interlayer insulating film 9 and the plug electrode 15 by, for example, sputtering, thereby forming the electrode structure shown in FIG. 19. The subsequent steps are the same as those in the first embodiment.

[0109] In the semiconductor device according to the second embodiment, a W film 27 is provided on the interlayer insulating film 9 and the plug electrode 15. The W prevents ions contained in the package resin 16 from reaching the gate oxide film 7, thereby preventing a decrease in Vth due to defects in the front surface electrode during packaging. Furthermore, because W does not occlude hydrogen, a decrease in Vth due to defects in the gate insulating film after wafer processing is prevented. Similar effects can be achieved by using a tungsten nitride (WN) film, or a simple film or nitride film of tantalum (Ta), nickel (Ni), cobalt (Co), molybdenum (Mo), or the like, instead of the W film 27. While FIG. 19 shows a structure comparable to that shown in FIG. 2, the second embodiment may be combined with the structures shown in FIGS. 12 to 18. 12 and 13 show examples in which the second barrier metal 25b and the third barrier metal 25c are not provided, but as explained above, even when the first barrier metal 25a does not contain Ti, the same effect as when the second barrier metal 25b and the third barrier metal 25c are provided is achieved.

[0110] As described above, according to the second embodiment, the absence of a Ti film on the interlayer insulating film suppresses hydrogen absorption. As a result, heat and hydrogen are supplied to defective portions of the gate insulating film by annealing, allowing the defects to be repaired. This makes it possible to suppress a decrease in Vth due to defects in the gate insulating film. Furthermore, by sandwiching a W film between the interlayer insulating film and the front electrode, it is possible to prevent ions in the package resin from reaching the gate insulating film through defects in the front electrode. This makes it possible to suppress a decrease in Vth due to defects in the front electrode.

[0111] Third Embodiment FIG. 20 is a cross-sectional view showing another electrode structure of a semiconductor device according to a third embodiment. The third embodiment differs from the first embodiment in that the first barrier metal 25a is composed of a stack of multiple films, while the second barrier metal 25b and the third barrier metal 25c have the same structures as those of the first embodiment. For example, in the structure shown in FIG. 20 , the first barrier metal 25a is composed of two layers: a second TiN film 19 containing the metal elements contained in the second barrier metal 25b and the third barrier metal 25c, and a W film 27 containing a different metal element. The two-layer structure of the second TiN film 19 and the W film 27 shown in FIG. 20 is more effective at trapping ions than TiN alone. Furthermore, W formed by CVD has poor adhesion to the interlayer insulating film 9 and may react with Ti exposed on the sidewall, causing defects. Therefore, forming the second TiN film 19 facilitates the formation of the W film 27. Furthermore, the multi-layer structure improves ion trapping and mechanical strength.

[0112] Furthermore, the first barrier metal 25a may be not only TiN / W but also a multilayer film such as Ti / TiN, TiN / Ti / TiN, Ti / TiN / W, or TiN / Ti / TiN / W. Although Ti is disadvantageous in terms of hydrogen absorption, it may be formed thinner than necessary for silicide formation to improve the ion trapping performance of the package resin 16 and suppress the Vth decrease due to front-surface electrode defects within a range where the Vth decrease due to defects in the gate insulating film is not a problem. If the Ti is thinned during the deposition of the initial barrier metal that will become the third barrier metal 25c, the silicide formation at the bottom of the contact hole 20 will be insufficient, resulting in high contact resistance. Therefore, it is preferable to form a thick Ti film and a thin Ti film twice, once during the deposition of the initial barrier metal (Ti film 17) and once during the deposition of the first barrier metal 25a. A structure in which Ti is covered with TiN can prevent the Ti from being oxidized immediately when exposed to the atmosphere after film formation, and if a structure in which Ti is covered with W is used, the Ti can be protected from WF6 and other materials used in W-CVD. On the other hand, a structure in which TiN is placed under Ti can improve mechanical strength because TiN has better adhesion to BPSG. Note that while Figure 20 shows a structure that is contrasted with the structure shown in Figure 2, the third embodiment may be applied in combination with the structures shown in Figures 12 to 18.

[0113] (Method of Manufacturing Semiconductor Device According to Embodiment 3) The semiconductor device according to Embodiment 3 is formed in the same manner as the semiconductor device according to Embodiment 1 or 2. After the semiconductor device according to Embodiment 1 is similarly manufactured up to the state shown in Fig. 10 , a second TiN film 19 may be formed uniformly on the surfaces of interlayer insulating film 9 and plug electrode 15 by, for example, sputtering, and then a W film 27 may be formed on second TiN film 19 by, for example, CVD or sputtering.

[0114] As described above, according to the third embodiment, a stacked film of multiple films is provided on the interlayer insulating film and the plug electrode. The absence or reduction of the Ti film on the interlayer insulating film suppresses hydrogen absorption. This allows heat and hydrogen to be supplied to defective portions of the gate insulating film by annealing, thereby repairing the defects. This makes it possible to suppress a decrease in Vth due to defects on the gate insulating film. Furthermore, it is possible to prevent ions in the package resin from reaching the gate insulating film through defects in the front surface electrode. This makes it possible to suppress a decrease in Vth due to defects in the front surface electrode.

[0115] Fourth Embodiment FIG. 21 is a cross-sectional view showing the structure near the signal electrode pad of the semiconductor device according to the third embodiment. As shown in FIG. 21 , in the semiconductor device according to the fourth embodiment, the structure below the signal electrode pad is the same as the structure of the active region. That is, the barrier metal 25 is composed of a first barrier metal 25a formed on the plug electrode 15 and the interlayer insulating film 9, a second barrier metal 25b formed between the side surface of the plug electrode 15 and the interlayer insulating film 9, and a third barrier metal 25c formed between the plug electrode 15 and a connecting portion 38. A connecting portion 38 is provided below the contact hole 20 and the interlayer insulating film 9. If the signal electrode pad does not have the emitter electrode potential, the connecting portion 38 is configured so as not to have the emitter electrode potential. For example, an insulating film 37 may be provided below the connecting portion 38. For example, in the case of a gate pad, the connecting portion 38 may be a polycrystalline portion such as polysilicon, and may be formed simultaneously with the gate electrode 8 or may be connected to the gate electrode 8. The insulating film 37 may also be formed simultaneously with the gate insulating film 7. Furthermore, for example, in the case of an anode / cathode electrode pad of a temperature-sensitive diode, the connection portion 38 may be a polycrystalline portion such as polysilicon, may be formed simultaneously with the temperature-sensitive diode, and may be connected to the temperature-sensitive diode. Alternatively, the connection portion 38 may be formed simultaneously with the gate electrode 8, and may not be connected to the temperature-sensitive diode. In FIG. 21 , the connection portion 38 and the insulating film 37 are provided continuously in a planar shape, but they may also be provided discretely. Furthermore, although the base region 2 is provided in the semiconductor wafer 10 below the insulating film 37, this is not limiting, and other impurity regions, trenches, etc. may also be present.

[0116] The first barrier metal 25a may be the second TiN film 19 as shown in Fig. 2, or the W film 27 as shown in Fig. 19, or a laminate of the second TiN film 19 and the W film 27 as shown in Fig. 20. Furthermore, the structure of the barrier metal 25 may be other structures shown in Figs. 12 to 18. Moreover, the structures of the second barrier metal 25b and the third barrier metal 25c are the same as those in the first embodiment.

[0117] 22 is another cross-sectional view showing the structure near the signal electrode pad of the semiconductor device according to the fourth embodiment. In FIG. 22, the structure differs from the example shown in FIG. 21 in that a contact hole 20 provided in the interlayer insulating film 9 is present above the trench 6 below the signal electrode pad 60. That is, in FIG. 22, an insulating film 37 is formed on the sidewall of the trench 6 formed on the first main surface side of the semiconductor wafer 10, and a connection portion 38 is provided inside the trench 6. The width of the bottom of the contact hole 20 is narrower than the width of the top surface of the trench 6, and may be wider or narrower than the width of the top surface of the connection portion 38.

[0118] The trench 6 may be formed simultaneously with the active region, i.e., the trench 6 shown in FIG. 1 , or may be formed separately. The insulating film 37 may be formed simultaneously with the gate insulating film 7, or may be formed separately. The connection portion 38 may be a polycrystalline portion such as polysilicon, and may be formed simultaneously with the gate electrode 8 or may be formed separately. For example, in the case of a gate pad, the connection portion 38 may be connected to the gate electrode 8, and the trench 6 may extend to the active region and function as a gate. Alternatively, the connection portion 38 may not be directly connected to the gate electrode 8. Furthermore, in the case of an anode / cathode electrode pad for a temperature-sensitive diode, the connection portion 38 may be a polycrystalline portion such as polysilicon, and may be formed simultaneously with the temperature-sensitive diode, and may be connected to the temperature-sensitive diode or may not be directly connected. Alternatively, the connection portion 38 may be formed simultaneously with the gate electrode 8, but not connected to the temperature-sensitive diode.

[0119] A connecting portion 38 is formed in the trench 6 below the passivation film 39, similar to the connecting portion 38 below the signal electrode pad 60, and is connected to the front surface electrode 11 through a contact hole 20 including a plug electrode 15, a second barrier metal 25b, and a third barrier metal 25c provided in the interlayer insulating film 9. For example, in the case of a gate pad, the front surface electrode 11 below the passivation film 39 may be a gate runner connecting the gate electrode 8 to the gate pad, and the connecting portion 38 may be a gate runner connecting the gate electrode 8 to the gate pad or the gate electrode 8. In the case of an anode / cathode electrode pad of a temperature-sensitive diode, the front surface electrode 11 below the passivation film 39 may be a runner connecting the temperature-sensitive diode to the anode / cathode electrode pad, and the connecting portion 38 may be the temperature-sensitive diode. In another example, the connecting portion 38, the contact hole 20 connecting to the connecting portion 38, the insulating film 37, etc. may not be present below the passivation film 39. 21, an insulating film 37, a connecting portion 38, and a contact hole 20 may be provided above the semiconductor wafer 10.

[0120] 23 is another cross-sectional view showing the structure in the vicinity of the signal electrode pad of the semiconductor device according to the fourth embodiment. Fig. 23 differs from the examples shown in Figs. 21 and 22 in that there is no contact hole 20 in the interlayer insulating film 9 below the signal electrode pad 60. That is, in Fig. 23, a first barrier metal 25a is formed on the upper surface of the interlayer insulating film 9 below the signal electrode pad 60. Note that there is no connection portion 38 below the signal electrode pad 60 in Fig. 23, but in other examples, the connection portion 38 may be present below the interlayer insulating film 9.

[0121] 21 or 22. In FIG. 23, similar to FIG. 21, below the passivation film 39, a connection portion 38 is located under the interlayer insulating film 9 having a first barrier metal 25a on its upper surface, and is connected to the front surface electrode 11 through a contact hole 20 having a plug electrode 15, a second barrier metal 25b, and a third barrier metal 25c. For example, in the case of a gate pad, the front surface electrode 11 below the passivation film 39 may be a gate runner connecting the gate electrode 8 and the gate pad, and the connection portion 38 may be a gate runner connecting the gate electrode 8 and the gate pad, or the gate electrode 8. In the case of an anode / cathode electrode pad of a temperature-sensitive diode, the front surface electrode 11 below the passivation film 39 may be a runner connecting the temperature-sensitive diode and the anode / cathode electrode pad, and the connection portion 38 may be a temperature-sensitive diode. In another example, the connection portion 38, the contact hole 20 connecting to the connection portion 38, the insulating film 37, etc. may not be present below the passivation film 39. Alternatively, as shown in FIG. 22 , the contact hole 20 connecting to the connection portion 38 formed in the trench 6 below the interlayer insulating film 9 may be provided in the interlayer insulating film 9.

[0122] In the semiconductor device according to the fourth embodiment, a first barrier metal 25a such as a second TiN film 19 or a W film 27 is provided on the interlayer insulating film 9, as in the first, second, or third embodiment. The absence or reduction of the Ti film on the interlayer insulating film suppresses hydrogen absorption. This allows heat and hydrogen to be supplied to defective portions by annealing, allowing the defects to be repaired. This suppresses a decrease in Vth due to defects. Furthermore, when a Ti film is not formed directly on the interlayer insulating film, mechanical strength is improved, preventing peeling of the front surface electrode.

[0123] (Method for manufacturing a semiconductor device according to embodiment 4) The semiconductor device according to embodiment 4 can be manufactured by fabricating the structure below and the structure above the barrier metal 25 using a conventional manufacturing method, and fabricating the barrier metal 25 using the manufacturing method of embodiment 1, 2 or 3.

[0124] That is, an insulating film 37 is formed on the upper surface or inside of the semiconductor wafer 10. Next, a polycrystalline portion such as polysilicon is formed on the insulating film 37 and patterned to form the connection portion 38 and shape the insulating film 37. Next, an interlayer insulating film 9 is formed above the connection portion 38 and the semiconductor wafer 10. Next, a contact hole 20 is formed to expose the connection portion 38. Next, a Ti film (initial barrier metal) 17 is uniformly formed in the contact hole 20 and on the surface of the interlayer insulating film 9 by sputtering. Next, a first TiN film (initial barrier metal) 18 is formed on the surface of the Ti film 17 by sputtering. Next, a third barrier metal 25c including a material formed by chemically changing the initial barrier metal in contact with the connection portion 38 may be formed by heat treatment. A second barrier metal 25b is formed in contact with the interlayer insulating film 9 by the initial barrier metal that is not chemically changed by the heat treatment.

[0125] Next, the surface of the first TiN film 18 (second barrier metal 25b and third barrier metal 25c) and the inside of the contact hole 20 are filled with a plug electrode 15 by, for example, sputtering. Next, the plug electrode 15 outside the contact hole 20 is removed by etching, and the plug electrode 15 is formed inside the contact hole 20. Next, the Ti film 17 and the first TiN film 18 (second barrier metal 25b) outside the contact hole 20 that are not covered by the plug electrode 15 are removed by etching, leaving the second barrier metal 25b between the plug electrode 15 and the interlayer insulating film 9 inside the contact hole 20. Next, the first barrier metal 25a is formed uniformly on the surfaces of the interlayer insulating film 9 and the plug electrode 15, for example. That is, the second TiN film 19 is formed by sputtering, and the W film 27 is formed by sputtering, or the second TiN film 19 and the W film 27 are formed by sputtering and CVD. After this, the first barrier metal 25a on the plug electrode 15 may be removed, leaving the first barrier metal 25a only on the interlayer insulating film 9. Next, a front surface metal film that will become the front surface electrode 11 is formed by, for example, sputtering. Next, the front surface metal film is patterned. Next, the patterned front surface metal film is annealed in a hydrogen atmosphere to form the front surface electrode 11. In a later process, a passivation film 39 is formed on the front surface of the semiconductor wafer 10, and the passivation film 39 is patterned to expose the signal electrode pad 60. This forms the signal electrode pad 60 and the structure in its vicinity shown in FIGS. 21, 22, and 23. Some or all of the above processes may be performed in common with the process of forming the active region shown in FIG. 1. In addition, if there is no contact hole 20 below the signal electrode pad 60 shown in Figure 23, the contents related to the inside of the contact hole 20, i.e., the formation of the contact hole 20 and the formation of the third barrier metal 25c, may be performed below the passivation film 39 or in the active region outside the range of the signal electrode pad 60, and the second barrier metal 25b and plug electrode 15 may be provided below the signal electrode pad 60 during manufacturing but may be removed when completed.

[0126] As described above, according to the fourth embodiment, a first barrier metal such as a second TiN film or a W film is provided on the interlayer insulating film, as in the first, second, and third embodiments. The absence or reduction of the Ti film on the interlayer insulating film suppresses hydrogen absorption. This allows heat and hydrogen to be supplied to defective portions of the gate insulating film by annealing, thereby repairing the defects. This suppresses a decrease in Vth due to defects on the gate insulating film. Furthermore, this also prevents ions in the package resin from reaching the gate insulating film through defects in the front electrode. This also suppresses a decrease in Vth due to defects in the front electrode. Furthermore, when a Ti film is not formed directly on the interlayer insulating film, mechanical strength is improved, and peeling of the front electrode is prevented.

[0127] While the present invention has been described above with reference to an example in which a MOS gate structure is formed on the first main surface of a silicon substrate, the present invention is not limited to this example and various modifications are possible, including the type of semiconductor (e.g., silicon carbide (SiC)), the surface orientation of the substrate main surface, and the like. Furthermore, while the embodiments of the present invention have been described with reference to a trench-type IGBT, the present invention is not limited to this example and is applicable to semiconductor devices with various configurations, such as planar-type IGBTs and MOS semiconductor devices such as MOSFETs. The barrier metal structure of the present invention is not limited to the mesa portion of the active region in FIG. 1 or below or near the signal electrode pads in FIGS. 21, 22, and 23, but may also be applied to other interlayer insulating films and contact holes. In this case, the front surface electrode above the first barrier metal is not limited to being exposed or carrying power. For example, the present invention may be applied to a contact hole provided in an interlayer insulating film connecting a gate runner or emitter electrode to a gate electrode in a trench, a field plate in an edge termination region, or a Zener diode. Furthermore, in the present invention, the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, but the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type.

[0128] As described above, the semiconductor device, semiconductor module and method for manufacturing a semiconductor device according to the present invention are useful for high-voltage semiconductor devices used in power conversion devices and power supply devices for various industrial machines.

[0129] 1, 101 n - n-type drift region 2, 102 p-type base region 3 + Type emitter region 4p + 1. Type contact region 5: n-type accumulation layer 6, 106: trench 7, 107: gate insulating film 8, 108: gate electrode 9, 109: interlayer insulating film 10, 110: semiconductor wafer 11, 111: front electrode 12: n-type field stop layer 13: p + Mold collector region 14 n + REFERENCE SIGNS LIST 15 Plug electrode 16, 116 Package resin (sealing resin) 17, 117 Ti film 18 First TiN film 19 Second TiN film 20, 120 Contact hole 21 IGBT region 22 FWD region 24 Back electrode 25, 125 Barrier metal 25a First barrier metal 25b Second barrier metal 25c Third barrier metal 26 Lifetime control region 27 W film 30, 130 Charged particle 31, 131 H molecule 32, 132 Front electrode defect 37, 137 Insulating film 38, 138 Connection portion 39, 139 Passivation film 41 Semiconductor element 42 Insulating substrate 43b, 43c Bonding material 44 Electrode pattern 45 Metal substrate 46 Conductive wire 47 Resin case 49 Metal terminal 50 Conductive wire 52 Laminated substrate 60, 160 Gate pad 115 Contact plug 118 TiN film 126 Front surface metal film 133 Defect 134 Ion 150 RC-IGBT 250 Semiconductor module

Claims

1. a semiconductor substrate; an interlayer insulating film provided on a first main surface of the semiconductor substrate; a contact hole that penetrates the interlayer insulating film and reaches the semiconductor substrate; a plug electrode filled in the contact hole; a first barrier metal that is not provided on the plug electrode but is provided on the interlayer insulating film; a front surface electrode provided on the first barrier metal and the plug electrode; A semiconductor device comprising:

2. (delete)

3. 2. The semiconductor device according to claim 1, further comprising a second barrier metal between a side surface of the plug electrode and the interlayer insulating film.

4. 2. The semiconductor device according to claim 1, further comprising a third barrier metal between the plug electrode and the semiconductor substrate.

5. a semiconductor substrate; an interlayer insulating film provided on a first main surface of the semiconductor substrate; a contact hole that penetrates the interlayer insulating film and reaches the semiconductor substrate; a plug electrode filled in the contact hole; a first barrier metal provided on the interlayer insulating film; a second barrier metal provided between a side surface of the plug electrode and the interlayer insulating film; a third barrier metal provided between the plug electrode and the semiconductor substrate; a front surface electrode provided on the first barrier metal; Equipped with the first barrier metal is not provided on the plug electrode, The semiconductor device is characterized in that the first barrier metal, the second barrier metal, and the third barrier metal are each composed of a different composition.

6. 6. The semiconductor device according to claim 5, wherein the first barrier metal is provided between the front surface electrode and the plug electrode.

7. 10. The semiconductor device according to claim 1, further comprising a back electrode on a second main surface opposite to the first main surface.

8. a gate electrode on the first principal surface side, the gate electrode being insulated from the semiconductor substrate by a gate insulating film and insulated from the front surface electrode by the interlayer insulating film; a first impurity layer having a conductivity type complementary to that of the semiconductor substrate, the first impurity layer being selectively provided in contact with the gate insulating film within the semiconductor substrate; Equipped with 6. The semiconductor device according to claim 1, wherein the first impurity layer is electrically connected to the front electrode through the contact hole.

9. 9. The semiconductor device according to claim 8, wherein the gate electrode is provided in a trench dug from the first main surface of the semiconductor substrate.

10. a second impurity layer having an impurity concentration higher than that of the semiconductor substrate is selectively provided within the first impurity layer; 9. The semiconductor device according to claim 8, wherein the second impurity layer is in contact with the gate insulating film and is electrically connected to the front electrode through the contact hole.

11. 10. The semiconductor device according to claim 1, further comprising a lifetime control region in the semiconductor substrate, the lifetime of which is controlled.

12. 10. The semiconductor device according to claim 1, wherein the front electrode is made of a metal containing Al as a main component.

13. 6. The semiconductor device according to claim 1, wherein the front electrode includes a laminated structure of a metal containing W and Al as a main component from the first barrier metal side.

14. 10. The semiconductor device according to claim 1, wherein the first barrier metal is TiN.

15. 10. The semiconductor device according to claim 1, wherein the plug electrode is made of W.

16. 6. The semiconductor device according to claim 5, wherein the second barrier metal is a laminate of Ti and TiN.

17. 10. A semiconductor module comprising the semiconductor device according to claim 1, wherein a conductive wire is bonded to the front surface electrode.

18. 18. The semiconductor module according to claim 17, wherein the conductive wires are made of a metal containing Cu as a main component.

19. 10. A semiconductor module comprising the semiconductor device according to claim 1 or 5 sealed with resin.

20. a first step of laminating an interlayer insulating film on a first main surface of a semiconductor substrate; and a second step of forming a contact hole that penetrates the interlayer insulating film and reaches the semiconductor substrate; a third step of laminating a plug electrode on the interlayer insulating film and in the contact hole; a fourth step of removing the plug electrode on the interlayer insulating film to leave the plug electrode only in the contact hole; a fifth step of depositing a first barrier metal on the plug electrode and the interlayer insulating film; a tenth step of removing the first barrier metal on the plug electrode and leaving the first barrier metal only on the interlayer insulating film; a sixth step of stacking a front surface electrode on the first barrier metal; and performing each step in the order listed.

21. a first step of laminating an interlayer insulating film on a first main surface of a semiconductor substrate; a second step of forming a contact hole that penetrates the interlayer insulating film and reaches the semiconductor substrate; a third step of laminating a plug electrode on the interlayer insulating film and in the contact hole; a fourth step of depositing a first barrier metal on the plug electrode and the interlayer insulating film; a tenth step of removing the first barrier metal on the plug electrode and leaving the first barrier metal only on the interlayer insulating film; a fifth step of stacking a front surface electrode on the first barrier metal; and performing each step in the order listed.

22. a first step of laminating an interlayer insulating film on a first main surface of a semiconductor substrate; a second step of forming a contact hole that penetrates the interlayer insulating film and reaches the semiconductor substrate; a third step of depositing an initial barrier metal on the interlayer insulating film and in the contact hole; a fourth step of chemically changing the initial barrier metal in contact with the semiconductor substrate by heat treatment to form a third barrier metal, and forming a second barrier metal from the initial barrier metal that has not been chemically changed; a fifth step of stacking a plug electrode on the second barrier metal and the third barrier metal; a sixth step of removing the plug electrode on the interlayer insulating film to leave the plug electrode only in the contact hole; a seventh step of removing the second barrier metal on the interlayer insulating film and leaving the second barrier metal only in the contact hole; an eighth step of depositing a first barrier metal on the plug electrode and the interlayer insulating film; a tenth step of removing the first barrier metal on the plug electrode and leaving the first barrier metal only on the interlayer insulating film; a ninth step of stacking a front surface electrode on the first barrier metal; and performing each step in the order listed.

23. (delete)

24. 23. The method for manufacturing a semiconductor device according to claim 20, further comprising an eleventh step of forming a lifetime control region, the lifetime of which is controlled, inside the semiconductor substrate by irradiation with a particle beam.

25. 6. The semiconductor device according to claim 5, wherein the metal element contained in the first barrier metal is different from the metal element contained in the second barrier metal.

26. 6. The semiconductor device according to claim 5, wherein the metal element contained in the first barrier metal is different from the metal element contained in the third barrier metal.

27. 6. The semiconductor device according to claim 1, wherein the first barrier metal is formed by stacking a plurality of layers.

28. 27. The semiconductor device according to claim 25, wherein the plug electrode and the surface electrode contain different metal elements, and the first barrier metal contains the same metal element as the plug electrode.

29. 26. The semiconductor device according to claim 25, wherein the first barrier metal is formed by stacking a layer containing a metal element contained in the second barrier metal and a layer containing the same metal element as the plug electrode.

30. 27. The semiconductor device according to claim 26, wherein the first barrier metal is formed by stacking a layer containing a metal element contained in the third barrier metal and a layer containing the same metal element as the plug electrode.

31. 23. The method for manufacturing a semiconductor device according to claim 22, wherein in the eighth step, the first barrier metal is stacked on the plug electrode and the interlayer insulating film as a film containing a metal element different from the metal element contained in the initial barrier metal.

32. 23. The method for manufacturing a semiconductor device according to claim 22, wherein in the eighth step, the first barrier metal is formed by stacking a layer containing a metal element contained in the initial barrier metal and a layer consisting of a different metal element on the plug electrode and the interlayer insulating film.

33. 23. The method for manufacturing a semiconductor device according to claim 22, wherein in the eighth step, the first barrier metal is stacked on the plug electrode and the interlayer insulating film as a film containing the same metal element as the plug electrode, and in the ninth step, the front surface electrode is stacked on the first barrier metal as a film containing a metal element different from that of the plug electrode.

34. 23. The method for manufacturing a semiconductor device according to claim 22, wherein in the eighth step, the first barrier metal is stacked on the plug electrode and the interlayer insulating film by stacking a layer containing a metal element contained in the initial barrier metal and a layer containing the same metal element as the plug electrode, and in the ninth step, the front surface electrode is stacked on the first barrier metal as a film containing a metal element different from that of the plug electrode.

35. a semiconductor substrate; a polycrystalline portion provided above or within the first main surface of the semiconductor substrate; an interlayer insulating film provided on the polycrystalline portion; a contact hole that penetrates the interlayer insulating film and reaches the polycrystalline portion; a plug electrode filled in the contact hole; a first barrier metal that is not provided on the plug electrode but is provided on the interlayer insulating film; a front surface electrode provided on the first barrier metal and the plug electrode; A semiconductor device comprising:

36. (delete)

37. a semiconductor substrate; a polycrystalline portion provided above or within the first main surface of the semiconductor substrate; an interlayer insulating film provided on the polycrystalline portion; a contact hole that penetrates the interlayer insulating film and reaches the polycrystalline portion; a plug electrode filled in the contact hole; a first barrier metal provided on the interlayer insulating film; a second barrier metal provided between a side surface of the plug electrode and the interlayer insulating film; a third barrier metal provided between the plug electrode and the polycrystalline portion; a front surface electrode provided on the first barrier metal; Equipped with the first barrier metal is not provided on the plug electrode, The semiconductor device is characterized in that the first barrier metal, the second barrier metal, and the third barrier metal are each composed of a different composition.

38. a twelfth step of forming a polycrystalline portion above or within the first main surface of the semiconductor substrate; a first step of depositing an interlayer insulating film on the polycrystalline portion; a second step of forming a contact hole that penetrates the interlayer insulating film and reaches the polycrystalline portion; a third step of laminating a plug electrode on the interlayer insulating film and in the contact hole; a fourth step of removing the plug electrode on the interlayer insulating film to leave the plug electrode only in the contact hole; a fifth step of depositing a first barrier metal on the plug electrode and the interlayer insulating film; a tenth step of removing the first barrier metal on the plug electrode and leaving the first barrier metal only on the interlayer insulating film; a sixth step of stacking a front surface electrode on the first barrier metal; and performing each step in the order listed.

39. a twelfth step of forming a polycrystalline portion above or within the first main surface of the semiconductor substrate; a first step of depositing an interlayer insulating film on the polycrystalline portion; a second step of forming a contact hole that penetrates the interlayer insulating film and reaches the polycrystalline portion; a third step of laminating a plug electrode on the interlayer insulating film and in the contact hole; a fourth step of depositing a first barrier metal on the plug electrode and the interlayer insulating film; a tenth step of removing the first barrier metal on the plug electrode and leaving the first barrier metal only on the interlayer insulating film; a fifth step of stacking a front surface electrode on the first barrier metal; and performing each step in the order listed.

40. a twelfth step of forming a polycrystalline portion above or within the first main surface of the semiconductor substrate; a first step of depositing an interlayer insulating film on the polycrystalline portion; a second step of forming a contact hole that penetrates the interlayer insulating film and reaches the polycrystalline portion; a third step of depositing an initial barrier metal on the interlayer insulating film and in the contact hole; a fourth step of chemically changing the initial barrier metal in contact with the polycrystalline portion by heat treatment to form a third barrier metal, and forming a second barrier metal from the initial barrier metal that has not been chemically changed; a fifth step of stacking a plug electrode on the second barrier metal and the third barrier metal; a sixth step of removing the plug electrode on the interlayer insulating film to leave the plug electrode only in the contact hole; a seventh step of removing the second barrier metal on the interlayer insulating film and leaving the second barrier metal only in the contact hole; an eighth step of depositing a first barrier metal on the plug electrode and the interlayer insulating film; a tenth step of removing the first barrier metal on the plug electrode and leaving the first barrier metal only on the interlayer insulating film; a ninth step of stacking a front surface electrode on the first barrier metal; and performing each step in the order listed.