Semiconductor package, module, and method for manufacturing semiconductor package

Abstract

The present invention reduces the number of processes in a component in which a plurality of semiconductor chips are provided on a substrate.　This semiconductor package includes a silicon substrate, a plurality of semiconductor chips, an organic substrate, and a wiring layer. In the semiconductor package, recesses are formed in the silicon substrate. In addition, in the semiconductor package, the plurality of semiconductor chips are arranged in the recesses. Furthermore, in the semiconductor package, the wiring layer is disposed between the organic substrate and the silicon substrate to electrically connect the plurality of semiconductor chips.

Description

Semiconductor package, module, and method for manufacturing semiconductor package

[0001] The present technology relates to a semiconductor package, and more particularly to a semiconductor package including a plurality of semiconductor chips, a module, and a method for manufacturing the semiconductor package.

[0002] In recent years, research and development of MCMs (Multi-Chip Modules), which mount multiple semiconductor chips on a single substrate, has been progressing. When mounting chips requiring multiple wiring, such as HBMs (High Bandwidth Memory), on these MCMs, it is necessary to form fine wiring at the wafer process level between the chips. Therefore, a semiconductor package structure in which an interposer is provided between the substrate and the semiconductor chip has been proposed (see, for example, Non-Patent Document 1).

[0003] Akira Fukuda, "CoWoS: High-Performance Packaging Technology That Has Evolved Five Generations in 10 Years (Part 1)," [online], published November 22, 2021, EE Times Japan, [Retrieved October 26, 2023], Internet <URL: https: / / eetimes.itmedia.co.jp / ee / articles / 2111 / 22 / news031.html>

[0004] In the above-mentioned conventional technology, electrical connection between chips is achieved by providing a silicon (Si) interposer between the substrate and the semiconductor chip. However, the above-mentioned conventional technology requires an organic interposer in addition to the Si interposer. Furthermore, bonding and forming the Si interposer and the semiconductor chip requires embedding and planarization of the chip mounting surface with molding resin. When embedding with molding resin, if the total chip area is too small compared to the interposer area, warping will occur, making it necessary to mount a dummy chip. As a result, the number of processes increases due to the formation of TSVs (Through Silicon Vias) and the mounting of dummy chips.

[0005] This technology was developed in light of these circumstances, and aims to reduce the number of processes required for components in which multiple semiconductor chips are mounted on a substrate.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a semiconductor package including a silicon substrate having a recess formed therein, a plurality of semiconductor chips arranged in the recess, an organic substrate, and a wiring layer arranged between the organic substrate and the silicon substrate and electrically connecting the plurality of semiconductor chips, and a manufacturing method thereof. This eliminates the need for a Si interposer in a semiconductor package that uses a Si interposer, thereby reducing the number of manufacturing steps.

[0007] In addition, in this first aspect, the silicon substrate may include a perforated member having an opening, and a support substrate to which the perforated member is attached, thereby eliminating the need for countersinking.

[0008] In addition, in the first aspect, a molding resin may be further provided embedded in the recess, thereby providing the effect of reducing the amount of module resin.

[0009] A second aspect of the present technology is a module including a silicon substrate having a recess formed therein, a plurality of semiconductor chips arranged in the recess, an organic substrate, and a wiring layer arranged between the organic substrate and the silicon substrate and electrically connecting the plurality of semiconductor chips, thereby reducing the number of steps in manufacturing the module.

[0010] FIG. 1 is a cross-sectional view showing an example of a configuration of a semiconductor package according to a first embodiment of the present technology; FIG. 2 is a cross-sectional view showing an example of a configuration of a semiconductor package in a comparative example; FIG. 3 is a view for explaining a procedure up to mounting a semiconductor chip according to the first embodiment of the present technology; FIG. 4 is a view for explaining a procedure up to forming bumps according to the first embodiment of the present technology; FIG. 5 is a flowchart showing an example of a manufacturing method of a semiconductor package according to the first embodiment of the present technology; FIG. 6 is a cross-sectional view showing an example of a configuration of a semiconductor package according to a second embodiment of the present technology; FIG. 7 is a view for explaining a procedure up to mounting a semiconductor chip according to the second embodiment of the present technology; FIG. 8 is a view for explaining a procedure up to forming bumps according to the second embodiment of the present technology; and FIG. 9 is a flowchart showing an example of a manufacturing method of a semiconductor package according to the second embodiment of the present technology.

[0011] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be given in the following order: 1. First embodiment (an example in which a recess is formed in a silicon substrate by spot facing) 2. Second embodiment (an example in which a recess is formed by attaching a wafer)

[0012] 1 is a cross-sectional view showing a configuration example of a semiconductor package 100 according to a first embodiment of the present technology. The semiconductor package 100 includes a silicon substrate 110, a plurality of chips such as semiconductor chips 121 and 122, a wiring layer 130, and an organic substrate 140. The semiconductor package 100 can be provided in various semiconductor devices such as smartphones and digital still cameras.

[0013] The component having the structure shown in the figure can also be called a module. A semiconductor package or module in which multiple semiconductor chips are mounted on a single substrate, as shown in the figure, is called an HBM.

[0014] Hereinafter, a predetermined axis parallel to the substrate plane of the organic substrate 140 will be referred to as the "X-axis," and a predetermined axis perpendicular to the substrate plane will be referred to as the "Z-axis." An axis perpendicular to the X-axis and Z-axis will be referred to as the "Y-axis." The figure is a cross-sectional view seen from the Y-axis direction. In addition, in the Z-axis direction, the direction from the organic substrate 140 to the silicon substrate 110 will be referred to as the "up" direction.

[0015] An upwardly recessed recess is formed by spot facing on the lower surface of the silicon substrate 110. In the figure, the area surrounded by coordinates (X1, Y1), (X1, Y2), (X2, Y1), and (X2, Y2) corresponds to the recess.

[0016] A plurality of semiconductor chips, such as semiconductor chips 121 and 122, are placed in a recess in silicon substrate 110, and mold resin 151 is embedded in the recess. Various semiconductor chips, such as memory chips such as HBMs and logic chips, can be placed in this recess. Each chip is placed with its bumps facing downward, and the top surface of the chip contacts the bottom of the recess. The height from the bumps to the top surface of each chip is the same as the depth of the recess (i.e., the distance from Y1 to Y2).

[0017] The wiring layer 130 is disposed between the silicon substrate 110 and the organic substrate 140. Inter-chip wiring is formed in the wiring layer 130, and multiple semiconductor chips are electrically connected by this wiring. Bumps are also formed on the lower surface of the wiring layer 130, and these are used for flip-chip mounting on the upper surface of the organic substrate 140. A predetermined number of bumps 154 are formed on the lower surface of the organic substrate 140 for connecting the semiconductor package 100 to the outside.

[0018] Here, a configuration in which an interposer is disposed between the chip and the organic substrate 140 is assumed as a comparative example.

[0019] 2 is a cross-sectional view showing an example of the configuration of a semiconductor package according to a comparative example, in which an interposer 160 is disposed between a plurality of semiconductor chips and an organic substrate 140.

[0020] The interposer 160 electrically connects multiple semiconductor chips. Bumps are formed on the bottom surface of the interposer 160, and the interposer 160 is flip-chip mounted on the top surface of the organic substrate 140. A predetermined number of TSVs 161 are formed in the interposer 160 for electrical connection of the bumps.

[0021] Furthermore, chips such as semiconductor chips 121 and 122 are flip-chip mounted on the upper surface of interposer 160. Furthermore, molding resin 151 is embedded between the chips.

[0022] In the comparative example, since molding resin 151 is embedded between the chips, if the total chip area is too small (for example, less than 80 percent) compared to the area of ​​interposer 160, warping may occur in interposer 160. To suppress this warping, the comparative example requires the mounting of a dummy chip.

[0023] As described above, in the comparative example, the TSV 161 and the dummy chip are required, and therefore the number of manufacturing steps increases by the steps of forming the TSV and mounting the dummy chip.

[0024] In contrast, as shown in FIG. 1, when recesses are formed in a silicon substrate 110 and multiple semiconductor chips are placed in the recesses, the chips can be connected by wiring in a wiring layer 130 formed at the wafer process level. This eliminates the need for an interposer 160. Furthermore, since the recesses are filled with mold resin 151, the amount of mold resin 151 can be reduced compared to the comparative example, thereby suppressing the effects of warping. As a result, a dummy chip is no longer necessary. Because the interposer 160 and dummy chip are no longer necessary, the number of processes can be significantly reduced compared to the comparative example. This reduction in the number of processes allows for lower manufacturing costs than the comparative example.

[0025] [Method of Manufacturing Semiconductor Package] Next, a method of manufacturing the semiconductor package 100 according to the first embodiment will be described with reference to FIGS.

[0026] First, as shown in Fig. 3A, a predetermined number of recesses 210 are formed in a silicon wafer 200 by spot boring. The dotted lines after A in the figure indicate the locations to be cut by dicing, which will be described later. Then, multiple chips, such as semiconductor chips 121 and 122, are placed in the recesses 210 with their bumps 152 facing upward.

[0027] FIG. 1C is an example of a plan view of the silicon wafer 200 in the step indicated by the symbol b in the figure. A plurality of recesses are formed in the circular silicon wafer 200, and semiconductor chips 121, 122, and 123 are disposed in each of the recesses. FIG. 1B corresponds to a cross-sectional view of FIG. 1C taken along the line Xa-Xb.

[0028] The depth of the recess is, for example, 500 micrometers (μm), and the height of the chip is the same. However, if the height of the chip is greater than the depth of the recess, for example, two silicon wafers may be stacked. In this case, a recess is formed in the first silicon wafer, and an opening having the same shape as the recess when viewed from the Z direction is provided in the second silicon wafer.

[0029] Next, as shown in FIG. 4A, the recesses are filled with molding resin 151, and as shown in FIG. 4B, the molding resin 151 is polished and flattened until the bumps are exposed.

[0030] Then, as illustrated in c in the figure, wiring is performed between chips at the wafer process level, forming a wiring layer 130. Since fine wiring is performed at the wafer process level, even when using chips that require multiple wiring connections such as HBM, the interposer 160 is not required.

[0031] Then, as shown in d in the figure, a predetermined number of bumps 153 are formed on the wiring layer 130. Then, the silicon wafer is diced into a plurality of silicon substrates 110, each of which is flip-chip mounted on an organic substrate 140.

[0032] FIG. 5 is a flowchart showing an example of a method for manufacturing the semiconductor package 100 according to the first embodiment of the present technology.

[0033] A predetermined number of recesses are formed in the silicon wafer 200 by spot-boring (step S901), and multiple semiconductor chips are mounted in each of the recesses (step S902). Then, a molding resin 151 is embedded in the recesses (step S903), and the molding resin 151 is polished until the bumps are exposed (step S904). Finally, a wiring layer 130 is formed at the wafer process level (step S905), and a predetermined number of bumps 153 are formed on the wiring layer 130 (step S906).

[0034] The silicon wafer is then diced into a plurality of silicon substrates 110 (step S907), and each silicon substrate 110 is flip-chip mounted on the organic substrate 140 (step S908). After step S908, various processes are performed, and the manufacturing process for the semiconductor package 100 is completed.

[0035] As described above, according to the first embodiment of the present technology, since a plurality of semiconductor chips are arranged in the recessed portion provided in the silicon substrate 110, the interposer 160 and the dummy chip are not required, and the number of processes can be reduced, thereby reducing the manufacturing cost.

[0036] 2. Second Embodiment In the first embodiment described above, the recess is formed in the silicon substrate 110 by spot facing, but this manufacturing method is not limited to this. The manufacturing method of the semiconductor package 100 in this second embodiment differs from the first embodiment in that the recess is formed by attaching a wafer.

[0037] 6 is a cross-sectional view showing a configuration example of a semiconductor package 100 according to a second embodiment of the present technology. The semiconductor package 100 according to the second embodiment differs from the first embodiment in that the silicon substrate 110 includes a support substrate 112 and a perforated member 111.

[0038] An opening is formed in the perforated member 111, and a support substrate 112 is attached to the upper surface of the perforated member 111. The space surrounded by the opening of the perforated member 111 and the support substrate 112 corresponds to a recess in the silicon substrate 110, and multiple semiconductor chips are arranged in this recess.

[0039] Next, a method for manufacturing the semiconductor package 100 according to the second embodiment will be described with reference to FIGS.

[0040] 7A, a pressure-bonding tape 302 is attached to the top surface of a support wafer 301, and a silicon perforated wafer 201 is pressure-bonded to the support wafer 301 by UV (UltraViolet) pressure bonding or thermocompression bonding. A silicon wafer or a glass wafer can be used as the support wafer 301.

[0041] 1B is an example of a plan view of the perforated wafer 201 in the step of 1A in the same figure. As illustrated in the figure, a plurality of openings are formed in the circular perforated wafer 201, and the lower pressure-sensitive adhesive tape 302 is exposed in each of the openings.

[0042] Then, as shown in FIG. 1C, a plurality of chips such as semiconductor chips 121 and 122 are placed in the opening with the bumps 152 facing downward.

[0043] 8A, the opening is filled with molding resin 151. Then, as shown in FIG. 8B, the molding resin 151 is polished and flattened until the top surface of the semiconductor chip is exposed.

[0044] Then, the support wafer 301 is removed, and a silicon support wafer 202 is attached to the upper surface of the perforated wafer 201 with an adhesive or the like, thereby forming recesses.

[0045] Then, as shown in Fig. 1C, a wiring layer 130 is formed on the bump side of the semiconductor chip at the wafer process level. In reality, the step c in Fig. 1C is performed with the wafer turned over.

[0046] Then, as illustrated in d in the figure, a predetermined number of bumps 153 are formed on the wiring layer 130. Then, the silicon wafer including the perforated wafer 201 and the support wafer 202 is diced into a plurality of silicon substrates 110, each of which is flip-chip mounted on the organic substrate 140.

[0047] FIG. 9 is a flowchart showing an example of a method for manufacturing the semiconductor package 100 according to the second embodiment of the present technology.

[0048] The perforated wafer 201 is pressure-bonded to the upper surface of the support wafer 301 (step S911), and multiple semiconductor chips are mounted in the openings (step S912). Then, the openings are filled with molding resin 151 (step S913), and the molding resin 151 is polished (step S914). Then, the support wafer 301 is removed, and a silicon support wafer 202 is attached to the upper surface of the perforated wafer 201 with an adhesive or the like (step S915).

[0049] Then, the wiring layer 130 is formed at the wafer process level (step S916), and a predetermined number of bumps 153 are formed on the wiring layer 130 (step S917). The silicon wafer is then diced into a plurality of silicon substrates 110 (step S918), each of which is flip-chip mounted on the organic substrate 140 (step S919). After step S919, various processes are performed, and the manufacturing process for the semiconductor package 100 is completed.

[0050] As described above, according to the second embodiment of the present technology, the recess is formed by attaching the silicon support wafer 202 to the perforated wafer 201, so that countersinking is not required.

[0051] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0052] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0053] The present technology can also be configured as follows: (1) A semiconductor package comprising: a silicon substrate having a recess formed therein; a plurality of semiconductor chips arranged in the recess; an organic substrate; and a wiring layer arranged between the organic substrate and the silicon substrate and electrically connecting the plurality of semiconductor chips. (2) The semiconductor package according to (1), wherein the silicon substrate comprises: a perforated member having an opening; and a support substrate to which the perforated member is attached. (3) The semiconductor package according to (1) or (2), further comprising a molding resin embedded in the recess. (4) A module comprising: a silicon substrate having a recess formed therein; a plurality of semiconductor chips arranged in the recess; an organic substrate; and a wiring layer arranged between the organic substrate and the silicon substrate and electrically connecting the plurality of semiconductor chips. (5) A method for manufacturing a semiconductor package, comprising the steps of: forming a recess in a silicon wafer, arranging a plurality of semiconductor chips in the recess, forming a wiring layer that electrically connects the plurality of semiconductor chips, singulating the silicon wafer into a predetermined number of silicon substrates, and mounting the silicon substrates on an organic substrate. (6) A method for manufacturing a semiconductor package, comprising the steps of: pressing a predetermined surface of a perforated wafer, having openings, to a support wafer, arranging a plurality of semiconductor chips in the openings, removing the support wafer and attaching a support wafer to one of both surfaces of the perforated wafer facing the predetermined surface, forming a wiring layer that electrically connects the plurality of semiconductor chips, singulating the perforated wafer and the support wafer into a predetermined number of silicon substrates, and mounting the silicon substrates on an organic substrate.

[0054] REFERENCE SIGNS LIST 100 semiconductor package 110 silicon substrate 111 perforated member 112 support substrate 121, 122 semiconductor chip 130 wiring layer 140 organic substrate 151 molding resin 152 to 154 bumps 160 interposer 161 TSV 200 silicon wafer 201 perforated wafer 202 support wafer 210 recess 301 support wafer 302 pressure-bonding tape

Claims

1. A semiconductor package comprising: a silicon substrate having a recess formed therein; a plurality of semiconductor chips arranged in the recess; an organic substrate; and a wiring layer arranged between the organic substrate and the silicon substrate for electrically connecting the plurality of semiconductor chips.

2. The semiconductor package according to claim 1, wherein the silicon substrate comprises: a perforated member having an opening; and a support substrate to which the perforated member is attached.

3. The semiconductor package according to claim 1, further comprising a molding resin embedded in said recess.

4. A module comprising: a silicon substrate having a recess formed therein; a plurality of semiconductor chips arranged in the recess; an organic substrate; and a wiring layer arranged between the organic substrate and the silicon substrate for electrically connecting the plurality of semiconductor chips.

5. A method for manufacturing a semiconductor package, comprising the steps of: forming a recess in a silicon wafer; arranging a plurality of semiconductor chips in the recess; forming a wiring layer that electrically connects the plurality of semiconductor chips; dicing the silicon wafer into a predetermined number of silicon substrates; and mounting the silicon substrates on an organic substrate.

6. A method for manufacturing a semiconductor package, comprising the steps of: pressing a predetermined surface of a perforated wafer having openings formed therein onto a support wafer; arranging a plurality of semiconductor chips in the openings; removing the support wafer and attaching a support wafer to one of both surfaces of the perforated wafer facing the predetermined surface; forming a wiring layer that electrically connects the plurality of semiconductor chips; dicing the perforated wafer and the support wafer into a predetermined number of silicon substrates; and mounting the silicon substrates on an organic substrate.