Diamond semiconductor device and method for manufacturing diamond semiconductor device

Abstract

Provided is a diamond semiconductor device having a trench part in the front surface thereof, the diamond semiconductor device comprising: a diamond layer; a diamond epitaxial layer provided on the diamond layer; a front surface-side insulating film provided above the epitaxial layer; and a front surface-side electrode provided on the front surface-side insulating film. The front surface-side insulating film has an embedded insulating part which is in contact with trench side walls of the trench part and with which the inside of the trench part is filled.

Description

Diamond semiconductor device and method for manufacturing diamond semiconductor device

[0001] The present invention relates to a diamond semiconductor device and a method for manufacturing a diamond semiconductor device.

[0002] Patent Document 1 discloses a diamond semiconductor device having a trench structure. [Prior art documents] [Patent documents] Patent Document 1: JP 2017-092398 A

[0003] It is desirable to reduce the on-resistance of diamond semiconductor devices. General disclosure

[0004] A first aspect of the present invention provides a diamond semiconductor device having a trench portion on its front surface. The diamond semiconductor device may include a diamond layer, a diamond epitaxial layer provided on the diamond layer, a front-side insulating film provided above the epitaxial layer, and a front-side electrode provided on the front-side insulating film. The front-side insulating film may have a buried insulating portion that contacts a trench sidewall of the trench portion and fills the interior of the trench portion.

[0005] In a second aspect of the present invention, there is provided a method for manufacturing a diamond semiconductor device having a trench portion on its front surface. The method for manufacturing a diamond semiconductor device may include the steps of providing a diamond layer, forming an epitaxial layer of diamond on the diamond layer, forming a front-side insulating film above the epitaxial layer, and forming a front-side electrode on the front-side insulating film. The step of forming the front-side insulating film may include the step of forming a buried insulating portion that contacts the trench sidewall and fills the interior of the trench.

[0006] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0007] 1A shows an example of the configuration of the diamond semiconductor device 100. FIG. 1B shows a modified example of the diamond semiconductor device 100. FIG. 1C shows a modified example of the diamond semiconductor device 100. FIG. 1D shows a modified example of the diamond semiconductor device 100. FIG. 1E shows a modified example of the diamond semiconductor device 100. FIG. 1F shows a modified example of the diamond semiconductor device 100. FIG. 1G shows a modified example of the diamond semiconductor device 100. FIG. 1H shows a modified example of the diamond semiconductor device 100. FIG. 1H shows a modified example of the diamond semiconductor device 100. FIG. 1I shows a modified example of the diamond semiconductor device 100. FIG. 1J shows a modified example of the diamond semiconductor device 100. FIG. 1J shows a modified example of the diamond semiconductor device 100. FIG. 1J shows a modified example of the diamond semiconductor device 100. FIG. 1J shows a modified example of the diamond semiconductor device 100. FIG. 1J shows a modified example of the diamond semiconductor device 100. FIG. 1J shows a modified example of the diamond semiconductor device 100. FIG. 1J shows a modified example of the diamond semiconductor device 100. FIG. 1J shows a modified example of the diamond semiconductor device 100.

[0008] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0009] 1A shows an example of the configuration of a diamond semiconductor device 100. The diamond semiconductor device 100 of this example is an example of a semiconductor device that functions as a MOSFET (metal oxide semiconductor field effect transistor). The diamond semiconductor device 100 includes a diamond layer 15. The diamond layer 15 has a diamond substrate 10 and a doped region 20. The diamond layer 15 has the diamond substrate 10 on the back surface 12 side, and the doped region 20 on the front surface 11 side.

[0010] The diamond substrate 10 is a P-type substrate made of diamond. The doping concentration of the P-type dopant in the diamond substrate 10 is 1×10 １９ cm－３ The diamond substrate 10 may be of the above type. The diamond substrate 10 may contain a P-type dopant. In one example, the P-type dopant is a Group III element such as boron (B), aluminum (Al), or gallium (Ga). The diamond substrate 10 in this example is P+ type, but is not limited to this. The diamond semiconductor device 100 in this example has a gate structure on the front surface 11 side.

[0011] In this specification, one side in a direction parallel to the depth direction of the diamond substrate 10 is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface, and the other surface is referred to as the lower surface. The directions of "upper," "lower," "front," and "back" are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device.

[0012] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. In this specification, the orthogonal axes parallel to the upper and lower surfaces of the diamond substrate 10 are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the upper and lower surfaces of the diamond substrate 10 is referred to as the Z-axis. The Z-axis direction is the depth direction of the diamond substrate 10. In this specification, a top view refers to a viewpoint seen from the positive side to the negative side in the Z-axis direction.

[0013] In this specification, the doping concentration of a dopant may refer to the concentration of a dopant that is intentionally introduced. That is, the doping concentration of a dopant does not necessarily include the doping concentration of unintentionally remaining impurities. The dopant may be introduced during epitaxial growth or may be implanted after growth.

[0014] The doped region 20 is provided above the diamond substrate 10. In this example, the doped region 20 contains an N-type dopant. The N-type dopant may be a Group V element such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb). In this example, the N-type dopant is nitrogen. The doping concentration of the N-type dopant in the doped region 20 is 1×10 １５ cm －３ That's it, 1 x 10 ２３ cm －３ It may be the following:

[0015] The doped region 20 may be a region epitaxially grown on the diamond substrate 10. The doped region 20 may be formed by microwave plasma chemical vapor deposition (MPCVD). The N-type dopant may be introduced during epitaxial growth or by other methods such as ion implantation after epitaxial growth of an undoped diamond layer.

[0016] The doped region 20 of this example has a first region 21 and a second region 22. By making the doped region 20 a stacked structure, it is possible to alleviate electric field concentration in the diamond semiconductor device 100. The doped region 20 may have a region containing a P-type dopant. The doped region 20 of this example has a P-type doped layer 25.

[0017] The doped layer 25 is provided above the diamond substrate 10. In this example, the doped layer 25 is provided in contact with the upper surface of the diamond substrate 10. The doped layer 25 in this example contains a P-type dopant. The doped layer 25 in this example is P-type, but is not limited to this. The doping concentration of the P-type dopant in the doped layer 25 is 1×10 １６ cm －３ That's it, 1 x 10 ２１ cm －３ The thickness of the doped layer 25 may be less than the thickness of the diamond substrate 10. The thickness of the doped layer 25 may be greater than the thickness of the first region 21 and may be greater than the thickness of the second region 22.

[0018] The doped layer 25 is a P-type region in contact with the epitaxial layer 30. The doped layer 25 may be in contact with the epitaxial layer 30 provided on the sidewall of the trench portion 50, or may be in contact with the epitaxial layer 30 provided on the bottom surface of the trench portion 50. The upper end of the doped layer 25 may be provided above the bottom surface of the trench portion 50. The lower end of the doped layer 25 may be provided below the bottom surface of the trench portion 50.

[0019] The first region 21 is provided above the diamond substrate 10. In this example, the first region 21 is provided in contact with the upper surface of the doped layer 25. In this example, the first region 21 contains an N-type dopant. The doping concentration of the N-type dopant in the first region 21 is 1×10 １５ cm －３ That's it, 1 x 10 １８ cm －３ The thickness of the first region 21 may be thinner than the thickness of the diamond substrate 10 and may be thinner than the thickness of the doped layer 25. The doping concentration of the N-type dopant and the thickness of the first region 21 may be determined taking into consideration the withstand voltage of the diamond semiconductor device 100.

[0020] The second region 22 is provided by stacking with the first region 21. In this example, the second region 22 is provided above the first region 21. In this example, the second region 22 contains an N-type dopant. The doping concentration of the N-type dopant in the second region 22 is different from that in the first region 21. In this example, the doping concentration of the N-type dopant in the second region 22 is higher than that in the first region 21. However, the doping concentration of the N-type dopant in the second region 22 may be lower than that in the first region 21. The doping concentration of the N-type dopant in the second region 22 is 1×10 １８ cm －３ That's it, 1 x 10 ２１ cm －３ The doping concentration of the N-type dopant and the thickness of the second region 22 may be determined in consideration of the withstand voltage of the diamond semiconductor device 100. Furthermore, by setting the doping concentration of the N-type dopant in the second region 22 to a high concentration, it becomes easier to suppress leakage current in the off state.

[0021] The thickness of the second region 22 may be the same as or different from the thickness of the first region 21. The thickness of the second region 22 may be thinner than the thickness of the first region 21. By reducing the thickness of the second region 22, it is possible to reduce the on-resistance while suppressing the leakage current in the off state.

[0022] The epitaxial layer 30 is provided on the diamond layer 15. In this example, the epitaxial layer 30 is provided on the doped region 20, but it may also be provided on the diamond substrate 10. The epitaxial layer 30 is made of diamond. The epitaxial layer 30 may be formed after a recess for providing the trench portion 50 is formed in the doped region 20. The epitaxial layer 30 may be provided on the sidewalls and bottom surface of the recess for providing the trench portion 50. The epitaxial layer 30 is in contact with the doped layer 25 at the bottom surface of the recess, but may also be in contact with the diamond substrate 10. In this specification, the recess may be a depression formed by etching the diamond layer 15. The sidewalls and bottom surface of the recess may be made of the diamond layer 15.

[0023] The thickness of the epitaxial layer 30 may be 10 nm or more and less than 200 nm. The thickness of the epitaxial layer 30 may be 10 nm or more and 100 nm or less. The thickness of the epitaxial layer 30 may be 30 nm or more and 100 nm or less. By reducing the thickness of the epitaxial layer 30, the distance that holes penetrate through the epitaxial layer 30 when the diamond semiconductor device 100 is on is shortened, and the on-resistance can be reduced.

[0024] The epitaxial layer 30 may include an N-type dopant. The N-type dopant may be nitrogen. The epitaxial layer 30 may have a lower doping concentration of the N-type dopant than the doped region 20. The doping concentration of the N-type dopant in the epitaxial layer 30 may be 1×10 １６ cm －３ By reducing the doping concentration of the N-type dopant in the epitaxial layer 30, when holes from the termination layer 40 flow into the epitaxial layer 30, pass through the epitaxial layer 30 to the doped layer 25, and then flow to the diamond substrate 10, the potential barrier in the epitaxial layer 30 becomes smaller, thereby reducing the on-resistance.

[0025] The epitaxial layer 30 may contain a P-type dopant. The doping concentration of the P-type dopant in the epitaxial layer 30 may be set to a range that allows the gate to be turned on and off. In one example, the doping concentration of the P-type dopant in the epitaxial layer 30 is 1×10 １５ cm －３ That's it, 1 x 10 １９ cm －３ The following is the result.

[0026] The termination layer 40 is provided on the epitaxial layer 30. In this example, the termination layer 40 is provided between the epitaxial layer 30 and the front surface-side insulating film 70. The termination layer 40 may be a layer that induces a two-dimensional hole gas (2DHG) in the epitaxial layer 30. The termination layer 40 may be a layer that has almost no conductivity when no gate voltage is applied, in order to achieve normally-off characteristics. The thickness of the termination layer 40 may be 20 nm or less, or 0.1 nm or more.

[0027] Termination layer 40 may be a hydrogen-terminated layer, a silicon oxide-terminated layer, or may include both a hydrogen-terminated region and a silicon oxide-terminated region. Termination layer 40 may be hydrogen-terminated by hydrogen radical irradiation, or may be silicon oxide-terminated by a reduction reaction of silicon dioxide and diamond in a high-temperature atmosphere.

[0028] The termination layer 40 includes a C-H bond, a C-O bond, a C-Si bond, a C-Si-O bond, a C-F bond, a C-OH bond, a C-N bond, or a C-NH bond. ２ The termination layer 40 may include at least one of the following bonds. The termination layer 40 may have the same bonds throughout the entire region of the termination layer 40, or different bonds in different regions. The termination layer 40 may have the same bonds over the entire surface between the epitaxial layer 30 and the front-side insulating film 70. The termination layer 40 may have C—H bonds over the entire surface between the epitaxial layer 30 and the front-side insulating film 70.

[0029] The front surface side insulating film 70 is provided above the epitaxial layer 30. The front surface side insulating film 70 is provided on the front surface 11 side of the diamond layer 15. The front surface side insulating film 70 may be provided above the epitaxial layer 30, or may be provided on the termination layer 40. The front surface side insulating film 70 may be provided on the sidewalls and bottom surface of the trench in the gate trench portion 50. The thickness of the front surface side insulating film 70 may be 50 nm or more and 200 nm or less. The thickness of the front surface side insulating film 70 may be 50 nm or more and 100 nm or less. The thickness of the front surface side insulating film 70 is, for example, 100 nm.

[0030] The front surface insulating film 70 is made of aluminum oxide (Al ２ O ３ ), silicon oxide (SiO ２ ), silicon nitride (SiNx), hafnium oxide (HfO ２ ), hafnium silicate (HfSiO ４ ) or boron nitride (BN). ２ O ３ The composition of the insulating film 70 does not necessarily have to be Al:O=2:3. The insulating film 70 on the front surface side may be a single layer, or may have a laminated structure in which different materials are laminated. The insulating film 70 on the front surface side in this example is a single layer of Al formed by atomic layer deposition (ALD). ２ O ３ is.

[0031] The front surface side insulating film 70 of this example has a buried insulating portion 170 and a non-buried insulating portion 270. However, the non-buried insulating portion 270 may be omitted.

[0032] The buried insulating portion 170 contacts the trench sidewall of the trench portion 50 and fills the inside of the trench portion 50. The buried insulating portion 170 may fill the entire inside of the trench portion 50, or may fill only a portion of the inside of the trench portion 50. The buried insulating portion 170 may fill 50% or more of the inside of the trench portion 50, 75% or more, or 90% or more.

[0033] The non-buried insulating portion 270 is provided above the mesa portion 152 adjacent to the trench portion 50. The non-buried insulating portion 270 may be provided above the contact region 60, or above the source electrode 120.

[0034] The buried insulating portion 170 and the non-buried insulating portion 270 may be formed in the same process or in different processes. In this example, the buried insulating portion 170 and the non-buried insulating portion 270 are formed simultaneously in the same process. When the buried insulating portion 170 and the non-buried insulating portion 270 are formed simultaneously, the buried insulating portion 170 and the non-buried insulating portion 270 may be integrated. When the buried insulating portion 170 and the non-buried insulating portion 270 are formed simultaneously, the region inside the trench of the trench portion 50 becomes the buried insulating portion 170, and the region provided above the mesa portion 152 becomes the non-buried insulating portion 270.

[0035] The material of the buried insulating portion 170 may be the same as or different from the material of the non-buried insulating portion 270. In this example, the material of the buried insulating portion 170 is the same as the material of the non-buried insulating portion 270. For example, the material of the buried insulating portion 170 and the non-buried insulating portion 270 is Al. ２ O ３ If there are dangling bonds on the surface of the epitaxial layer 30, electrons are trapped. ２ O ３ By bonding with the dangling bonds, electron trapping can be suppressed, thereby improving the conductivity of the termination layer 40 .

[0036] The material of the buried insulating portion 170 is SiO ２ , SiNx, HfO ２ , HfSiO ４ or BN, and the material of the non-buried insulating portion 270 is Al ２ O ３ , SiO ２ , SiNx, HfO ２ , HfSiO ４ The material of the buried insulating portion 170 may include at least one of Al, BN, or BN. ２ O ３ , SiO ２, SiNx, HfO ２ , HfSiO ４ or BN, and the material of the non-buried insulating portion 270 is SiO ２ , SiNx, HfO ２ , HfSiO ４ Or, it may include at least one of BN.

[0037] The trench portion 50 is provided so as to extend in the depth direction of the diamond layer 15. The trench portion 50 includes a front surface-side insulating film 70 provided in the trench. The trench portion 50 may be composed of only the front surface-side insulating film 70. The trench portion 50 of this example does not include the epitaxial layer 30 and the termination layer 40. The trench portion 50 may be in contact with the termination layer 40 on its sidewalls and bottom surface. The lower end of the trench portion 50 may be deeper than the upper end of the doped layer 25. In other words, the trench portion 50 may extend to the inside of the doped layer 25. The lower end of the trench portion 50 may be deeper than the upper end of the diamond substrate 10. The symbol T indicates the region of the trench portion 50.

[0038] The trench width of the trench portion 50 may be 100 nm or more and 1.5 μm or less. The trench width of the trench portion 50 may be the width of the trench portion 50 at the upper end of the trench portion 50. The upper end of the trench portion 50 is the upper end of the buried insulating portion 170. The upper end of the trench portion 50 may be at the same height as the upper end of the termination layer 40. The trench depth may be 60 nm or more and 20 μm or less. The aspect ratio of the trench portion 50 may be 2 or more and 5 or less.

[0039] The contact region 60 is provided above the epitaxial layer 30. The contact region 60 may be provided in contact with the source electrode 120. The contact region 60 may contain a P-type dopant. In this example, the contact region 60 is P+ type, but is not limited to this. The doping concentration of the contact region 60 in this example may be the same as or different from the doping concentration of the diamond substrate 10. The doping concentration of the contact region 60 may be higher or lower than the doping concentration of the diamond substrate 10. The P-type dopant may be a Group III element such as boron (B), aluminum (Al), or gallium (Ga). The P-type dopant may be introduced during epitaxial growth or by other methods such as ion implantation after epitaxial growth of an undoped diamond layer. The thickness of the contact region 60 may be thicker than the thickness of the epitaxial layer 30. The thickness of the contact region 60 may be less than the thickness of the epitaxial layer 30 .

[0040] The front surface side electrode 110 is provided above the diamond layer 15. In this example, the front surface side electrode 110 is provided on the front surface side insulating film 70. The front surface side electrode 110 may function as a gate electrode, and the front surface side insulating film 70 may function as a gate insulating film. In this example, the front surface side electrode 110 is located above the front surface 11 and is not provided inside the trench portion 50. In this example, the front surface side electrode 110 is provided above the trench portion 50 and the mesa portion 152. The front surface side electrode 110 may be provided in a region inside the region where the front surface side insulating film 70 is provided in a top view. That is, the front surface side electrode 110 may be provided so as to overlap the front surface side insulating film 70 in a top view. The front surface side electrode 110 may include any electrode material, such as aluminum (Al). The symbol G indicates the region of the front surface side electrode 110 which is the gate electrode.

[0041] The front surface side electrode 110 may extend from above one side wall of the trench portion 50 to above the other side wall, and may be provided so as to cover the upper part of the buried insulating portion 170. The front surface side electrode 110 may be provided so as to cover the entire upper surface of the trench portion 50, or may be provided so as to cover a part of the upper surface of the trench portion 50. The front surface side electrode 110 may terminate without extending from above one side wall of the trench portion 50 to above the other side wall, and may be provided so as not to completely cover the upper part of the buried insulating portion 170.

[0042] The source electrode 120 is provided above the diamond layer 15. The source electrode 120 may be provided on the front surface 11 side of the diamond layer 15. The source electrode 120 may be provided on the contact region 60. The source electrode 120 may be provided in the same region as the contact region 60 when viewed from above, or may be provided inside the contact region 60. The source electrode 120 may be a laminated film formed by laminating titanium (Ti) and gold (Au). The source electrode 120 may be a laminated film formed by laminating titanium (Ti), platinum (Pt), and gold (Au). A source voltage may be applied to the source electrode 120 provided on the front surface 11 side of the diamond layer 15. The symbol S indicates the region of the source electrode 120.

[0043] The back side electrode 130 is provided in contact with the diamond substrate 10. In this example, the back side electrode 130 functions as a drain electrode. The back side electrode 130 is provided on the back side 12 of the diamond layer 15. The back side electrode 130 may be provided on the entire back side 12, or on a part of the back side 12. The back side electrode 130 may be a laminated film formed by laminating titanium (Ti) and gold (Au). The back side electrode 130 may be a laminated film formed by laminating titanium (Ti), platinum (Pt), and gold (Au). The back side electrode 130 is provided in contact with the back side 12 of the diamond substrate 10. A drain-source voltage may be applied to the back side electrode 130 provided on the back side 12 of the diamond layer 15. The symbol D indicates the region of the back side electrode 130, which serves as the drain electrode.

[0044] Diamond semiconductor device 100 of this example is provided with front surface side electrode 110 and source electrode 120 on the front surface 11 side of diamond layer 15, and with back surface side electrode 130 on the back surface 12 side of diamond layer 15. When diamond semiconductor device 100 is turned on, current flows from source electrode 120 to contact region 60 and termination layer 40 in this order, and holes pass through epitaxial layer 30 and move into diamond substrate 10, causing current to flow to back surface side electrode 130.

[0045] In this example, the case where the diamond semiconductor device 100 is a P-type channel field effect transistor has been described, but the diamond semiconductor device 100 may be an N-type channel field effect transistor. When the diamond semiconductor device 100 functions as an N-type channel field effect transistor, the P-type dopant may be replaced with an N-type dopant, and the N-type dopant may be replaced with a P-type dopant.

[0046] Figure 1B is a modified example of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example differs from the diamond semiconductor device 100 of Figure 1A in that the buried insulating portion 170 and the non-buried insulating portion 270 are formed of different materials. In this example, the differences from the diamond semiconductor device 100 of Figure 1A will be particularly described.

[0047] The dielectric constant of the buried insulating portion 170 may be lower than the dielectric constant of the non-buried insulating portion 270. By lowering the dielectric constant of the buried insulating portion 170, the breakdown voltage of the diamond semiconductor device 100 is likely to be improved. In one example, the material of the buried insulating portion 170 is SiO ２ , SiNx, or BN, and the material of the non-buried insulating portion 270 is Al ２ O ３ , HfO ２ or HfSiO ４ It includes at least one of the following.

[0048] The non-buried insulating portion 270 may be formed by a method that has a faster deposition rate than the buried insulating portion 170. The non-buried insulating portion 270 may be formed by a CVD method. In one example, the material of the buried insulating portion 170 is Al. ２ O３ , HfO ２ , HfSiO ４ or BN, and the material of the non-buried insulating portion 270 is SiO ２ Alternatively, it may contain at least one of SiNx.

[0049] The buried insulating portion 170 is made of Al formed by the ALD method. ２ O ３ SiO by CVD method or the like. ２ When forming a thin film, Al is deposited by the ALD method. ２ O ３ For example, when the resistivity of the trench sidewall becomes dominant due to miniaturization of the diamond semiconductor device 100, the buried insulating portion 170 can be formed by forming Al ２ O ３ By forming the termination layer 40 from the above, the resistivity of the termination layer 40 on the trench sidewall can be reduced.

[0050] Figure 1C is a modified example of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example differs from the diamond semiconductor device 100 of Figure 1A in the position where the front surface side electrode 110 is provided. In this example, differences from the diamond semiconductor device 100 of Figure 1A will be particularly described.

[0051] The front surface side electrode 110 is provided so as to cover both the trench portion 50 and the mesa portion 152. The front surface side electrode 110 may be provided so as to completely cover the source electrode 120 in the mesa portion 152 between two adjacent trench portions 50. The front surface side electrode 110 may be provided so as to extend from above one side wall of the trench portion 50 to above the other side wall, and to cover the top of the trench portion 50.

[0052] In the diamond semiconductor device 100 of this example, even when the trench structure and source electrode 120 are miniaturized, it is easy to form the front surface side electrode 110. The diamond semiconductor device 100 of this example has the buried insulating portion 170 and the non-buried insulating portion 270 made of the same material, but may have the buried insulating portion 170 and the non-buried insulating portion 270 made of different materials. The structure of the front surface side electrode 110 of this example may be applied as appropriate to the front surface side electrode 110 of other embodiments.

[0053] Figure 1D shows a modified example of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example differs from the diamond semiconductor device 100 of Figure 1A in that it is provided with a plurality of layers of front surface-side insulating films 70. In this example, the differences from the diamond semiconductor device 100 of Figure 1A will be particularly described.

[0054] The buried insulating portion 170 of this example has a two-layer structure of a first buried insulating film 171 and a second buried insulating film 172. The unburied insulating portion 270 of this example has a two-layer structure of a first unburied insulating film 271 and a second unburied insulating film 272. The first buried insulating film 171 may be formed simultaneously with the first unburied insulating film 271. The second buried insulating film 172 may be formed simultaneously with the second unburied insulating film 272.

[0055] The first buried insulating film 171 is provided in contact with the trench sidewall of the trench portion 50. That is, the first buried insulating film 171 is provided on the trench sidewall in contact with the termination layer 40. When the termination layer 40 is not present, the first buried insulating film 171 may be provided in contact with the epitaxial layer 30.

[0056] The second buried insulating film 172 is provided by stacking it with the first buried insulating film 171 in the trench portion 50. That is, the second buried insulating film 172 is provided inside the first buried insulating film 171 in the trench portion 50. The second buried insulating film 172 may fill the entire inside of the first buried insulating film 171 in the trench portion 50. The material of the second buried insulating film 172 may be the same as or different from the material of the buried insulating portion 170.

[0057] The thickness of the first buried insulating film 171 may be thinner than the second buried insulating film 172. As will be described later, the first buried insulating film 171 may have any thickness taking into consideration improving the characteristics at the interface between the first buried insulating film 171 and the epitaxial layer 30. The thickness of the first buried insulating film 171 may be 10 nm or more and 100 nm or less. The second buried insulating film 172 may be formed by a method with a faster film formation rate than the first buried insulating film 171. This makes it easier to shorten the film formation time required to form the front surface-side insulating film 70. In one example, the first buried insulating film 171 is formed by the ALD method, and the second buried insulating film 172 is formed by the CVD method.

[0058] The non-buried insulating portion 270 may be provided above the trench portion 50 , may be provided above the mesa portion 152 , or may be provided above the source electrode 120 .

[0059] The first unburied insulating film 271 may be provided on the upper surface of the trench portion 50, on the upper surface of the termination layer 40, or on the upper surface of the source electrode 120. The second unburied insulating film 272 is provided by stacking with the first unburied insulating film 271. The thickness of the second unburied insulating film 272 may be the same as or different from the thickness of the first unburied insulating film 271. The thickness of the second unburied insulating film 272 may be thicker than the thickness of the first unburied insulating film 271. The second unburied insulating film 272 may be formed by a method having a faster film formation rate than the first unburied insulating film 271.

[0060] The thickness of the first non-buried insulating film 271 may be the same as or different from the thickness of the first buried insulating film 171 inside the trench. The thickness of the first non-buried insulating film 271 may be 10 nm or more and 100 nm or less, similar to the first buried insulating film 171. The method for forming the first non-buried insulating film 271 in this example is the same as the method for forming the first buried insulating film 171, but may be different.

[0061] The thickness of the second non-buried insulating film 272 may be the same as or different from the thickness of the second buried insulating film 172 inside the trench. The method for forming the second non-buried insulating film 272 in this example is the same as the method for forming the second buried insulating film 172, but may be different.

[0062] The front surface side electrode 110 is provided above the mesa portion 152 and above the unburied insulating portion 270. The front surface side electrode 110 of this example is provided on the second unburied insulating film 272. The front surface side electrode 110 may also be provided above the source electrode 120. The front surface side electrode 110 of this example is provided so that at least a portion thereof overlaps with the source electrode 120. By providing the front surface side electrode 110 also above the source electrode 120, the front surface side electrode 110 and the source electrode 120 can be arranged to overlap, which facilitates further miniaturization.

[0063] Figure 1E shows a modified example of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example differs from the diamond semiconductor device 100 of Figure 1A in that the trench portion 50 has a taper. In this example, the differences from the diamond semiconductor device 100 of Figure 1A will be particularly described.

[0064] The trench portion 50 is tapered, and has a predetermined taper angle θt. The trench portion 50 may have a forward taper with a taper angle θt greater than 0 degrees and less than 90 degrees, or may have a reverse taper with a taper angle θt greater than 90 degrees and less than 180 degrees. The trench portion 50 in this example has a forward taper. When the trench portion 50 has a taper angle θt, the degree of filling of the front surface-side insulating film 70 changes, and the shape of the recess Re of the front surface-side insulating film 70 changes.

[0065] When the degree of embedding changes depending on the taper angle θt, the penetration depth of the front surface side electrode 110 into the trench portion 50 changes. By changing the penetration depth of the front surface side electrode 110, it is possible to adjust the gate control region where the front surface side electrode 110 contacts the front surface side insulating film 70 and where the front surface side electrode 110 functions as a gate. Furthermore, by changing the penetration depth of the front surface side electrode 110, it is possible to adjust the breakdown voltage of the diamond semiconductor device 100. For example, by adjusting the penetration depth of the front surface side electrode 110, it is possible to suppress a decrease in breakdown voltage. The taper angle θt may be 60 degrees or more and 100 degrees or less.

[0066] The tapered structure of the trench portion 50 of this example may be applied as appropriate to other embodiments of the diamond semiconductor device 100. The front surface side insulating film 70 of this example has a single-layer structure of the buried insulating portion 170 and the non-buried insulating portion 270, but may have a stacked structure of the buried insulating portion 170 and the non-buried insulating portion 270. The material of the buried insulating portion 170 of this example is the same as the material of the non-buried insulating portion 270, but may be different. The diamond semiconductor device 100 can adjust the penetration depth of the front surface side electrode 110 by changing the shape of the recess Re by changing the taper angle θt and the method of forming the front surface side insulating film 70.

[0067] Figure 1F is a modified example of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example differs from the diamond semiconductor device 100 of Figure 1E in the position where the front surface side electrode 110 is provided. In this example, differences from the diamond semiconductor device 100 of Figure 1E will be particularly described.

[0068] The front surface side electrode 110 is not provided above the trench portion 50, but is provided above the mesa portion 152 adjacent to the trench portion 50. The front surface side electrode 110 may be provided above each of the mesa portions 152 on both ends of the trench portion 50. In this example, the front surface side electrode 110 is provided so as not to overlap the source electrode 120 in top view, but may be provided so as to overlap the source electrode 120.

[0069] In this example, the front surface side electrode 110 is not provided above the trench portion 50, so it is possible to prevent the front surface side electrode 110 from filling the recess Re in the front surface side insulating film 70. If a recess Re occurs in the front surface side insulating film 70 in the trench portion 50 and the front surface side electrode 110 is provided in the recess Re, the distance between the diamond substrate 10 and the front surface side electrode 110 may become shorter, resulting in a decrease in the breakdown voltage. In this example, the diamond semiconductor device 100 is provided with the front surface side electrode 110 spaced apart from the recess Re, which makes it easier to prevent a decrease in the breakdown voltage. In this example, the front surface side electrode 110 is arranged so as not to overlap with the source electrode 120, but it may be arranged so as to overlap with the source electrode 120.

[0070] 1G is a modified example of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example has a diode structure. The diamond semiconductor device 100 of this example has a diamond layer 15, an epitaxial layer 30, a trench portion 50, a front surface side electrode 110, and a back surface side electrode 130. The front surface side electrode 110 may function as a cathode. The back surface side electrode 130 may function as an anode.

[0071] The diamond substrate 10 is a P+ type substrate made of diamond. The diamond substrate 10 may have the same dopants and doping concentrations as those described in the embodiment in which the diamond semiconductor device 100 functions as a MOSFET.

[0072] A doped region 20 is provided on the diamond substrate 10. The doped region 20 includes a P-type dopant. In this example, the doped region 20 is P-type, but is not limited to this.

[0073] The epitaxial layer 30 may include an N-type dopant. The epitaxial layer 30 may be N+ type. A termination layer 40 may be provided between the epitaxial layer 30 and the front surface-side insulating film 70. The termination layer 40 between the epitaxial layer 30 and the front surface-side insulating film 70 may be N+ type.

[0074] The trench portion 50 has a front surface-side insulating film 70. The front surface-side insulating film 70 fills the trench of the trench portion 50. That is, the front surface-side insulating film 70 of this example has a buried insulating portion 170. The front surface-side insulating film 70 may have a plurality of insulating films in the trench portion 50. The front surface-side insulating film 70 may be a stack of a plurality of films of different types, or may be a stack of films of the same type.

[0075] The front surface side insulating film 70 of this example is not provided on the mesa portion 152. In other words, the front surface side insulating film 70 does not need to have the non-buried insulating portion 270.

[0076] Fig. 2A shows an example of a method for manufacturing the diamond semiconductor device 100 of Fig. 1A. In step S100, a P-type diamond substrate 10 is prepared.

[0077] In step S102, a doped region 20 containing an N-type dopant is formed above the diamond substrate 10. In this example, the doped region 20 is formed by epitaxial growth on the diamond substrate 10. In this example, the doped layer 25 is formed by introducing a P-type dopant during epitaxial growth. In this example, the first region 21 and the second region 22 are formed by introducing an N-type dopant during epitaxial growth. The first region 21 and the second region 22 may be formed by successive epitaxial growth after the epitaxial growth of the doped layer 25. The first region 21 and the second region 22 may have different doping concentrations by changing the amount of N-type dopant during epitaxial growth.

[0078] In step S104, the diamond layer 15 is etched to form a recess. In this example, the recess is formed by etching the second region 22, the first region 21, and the doped layer 25. After the recess is formed, the epitaxial layer 30 is formed. The epitaxial layer 30 may be formed on the sidewalls and bottom surface of the recess, or on the top surface of the second region 22. The epitaxial layer 30 may be formed on the diamond layer 15 by epitaxial growth.

[0079] Fig. 2B shows an example of a method for manufacturing the diamond semiconductor device 100 of Fig. 1A. This figure shows a process subsequent to step S104 of Fig. 2A.

[0080] In step S106, a contact region 60 and a source electrode 120 are formed on the epitaxial layer 30. The contact region 60 may be formed by epitaxial growth on the epitaxial layer 30. The contact region 60 may be P+ type. The contact region 60 may be omitted. In step S106, a termination layer 40 may be formed. The termination layer 40 may be formed after the source electrode 120 is formed. The termination layer 40 may be formed on the epitaxial layer 30 by introducing any gas during annealing. The termination layer 40 may be formed by hydrogen terminating the epitaxial layer 30 or by terminating the epitaxial layer 30 with silicon oxide.

[0081] In step S108, a front-side insulating film 70 is formed. The front-side insulating film 70 is formed above the epitaxial layer 30. In this example, the front-side insulating film 70 is formed above the termination layer 40. The front-side insulating film 70 may be formed by a method such as an ALD method or a CVD method. The step of forming the front-side insulating film 70 includes a step of forming a buried insulating portion 170 that contacts the trench sidewall of the trench portion 50 and fills the interior of the trench portion 50. The step of forming the front-side insulating film 70 may include a step of forming a non-buried insulating portion 270 outside the trench portion 50. After forming the front-side insulating film 70, the interface between the termination layer 40 and the front-side insulating film 70 may be improved by annealing or the like.

[0082] In this example, the termination layer 40 is formed on the epitaxial layer 30 before forming the front-side insulating film 70. However, the termination layer 40 may be formed between the front-side insulating film 70 and the epitaxial layer 30 after the front-side insulating film 70 is formed on the epitaxial layer 30.

[0083] Fig. 2C shows an example of a method for manufacturing the diamond semiconductor device 100 of Fig. 1A. This figure shows a process subsequent to step S108 of Fig. 2B.

[0084] In step S110, the front surface side insulating film 70 is etched. In this example, only the non-buried insulating portion 270 outside the trench of the front surface side insulating film 70 is etched, but the buried insulating portion 170 inside the trench may also be etched. The front surface side insulating film 70 may be etched to a thickness that allows gate control by the front surface side electrode 110. The entire front surface side insulating film 70 may be etched, or only the front surface side insulating film 70 in the region where the front surface side electrode 110 is to be formed may be etched. The etching step of the front surface side insulating film 70 may be omitted.

[0085] In step S112, the front surface side electrode 110 is formed on the front surface side insulating film 70. The front surface side electrode 110 may be formed above the etched front surface side insulating film 70. The back surface side electrode 130 may be formed on the back surface 12 of the diamond substrate 10.

[0086] 3A shows an example of a manufacturing method for the diamond semiconductor device 100. In this example, the description will begin with the process of forming the front surface side insulating film 70. The process up to the process of forming the source electrode 120 may be the same as other manufacturing methods. The front surface side insulating film 70 in this example may be formed by stacking a first insulating film 71 and a second insulating film 72.

[0087] In step S206, a first insulating film 71 is formed above the epitaxial layer 30. The first insulating film 71 may be partially hollow and not fill the entire trench. In this example, the first insulating film 71 is formed in contact with the trench sidewall of the trench portion 50. As a result, a first buried insulating film 171 is provided in contact with the trench sidewall of the trench portion 50.

[0088] In step S208, the diamond semiconductor device 100 is annealed to form the termination layer 40. In this example, the diamond semiconductor device 100 is annealed after the step of forming the first buried insulating film 171 and before the step of forming the second buried insulating film 172. The step of forming the first buried insulating film 171 may be the step of forming the first insulating film 71 to form the first buried insulating film 171. The step of forming the second buried insulating film 172 may be the step of forming the second insulating film 72 to form the second buried insulating film 172. Since the trench is not completely filled with the first insulating film 71 during the annealing process and gas is also supplied to the interior of the trench, the quality of the interface of the termination layer 40 is improved. The diamond semiconductor device 100 may be annealed in a nitrogen atmosphere or a hydrogen atmosphere. The interface between the termination layer 40 and the first insulating film 71 may be improved by annealing the diamond semiconductor device 100, for example.

[0089] In this example, the termination layer 40 is formed after the step of forming the first buried insulating film 171 and before the step of forming the second buried insulating film 172, but the termination layer 40 may be formed before the step of forming the first buried insulating film 171. Alternatively, the termination layer 40 may be formed after the first buried insulating film 171 and the second buried insulating film 172 are formed.

[0090] Fig. 3B shows an example of a method for manufacturing the diamond semiconductor device 100. This figure shows a process subsequent to step S208 in Fig. 3A.

[0091] In step S210, a second insulating film 72 is formed as the front surface-side insulating film 70. The second insulating film 72 may be formed on the upper surface of the first insulating film 71. The thickness of the second insulating film 72 may be the same as or different from the thickness of the first insulating film 71. The thickness of the second insulating film 72 may be thicker than the thickness of the first insulating film 71. The second insulating film 72 may be formed by the same manufacturing method as the first insulating film 71, or may be formed by a different manufacturing method. The second insulating film 72 may be formed under the same film formation conditions as the first insulating film 71, or may be formed under different film formation conditions.

[0092] The second insulating film 72 may be formed by stacking with the first insulating film 71 inside the trench. As a result, the first buried insulating film 171 and the second buried insulating film 172 are provided in a stacked state in the trench portion 50. In this way, the first buried insulating film 171 and the first unburied insulating film 271 may be regions where the first insulating film 71 remains. The second buried insulating film 172 and the second unburied insulating film 272 may be regions where the second insulating film 72 remains. The second insulating film 72 may be formed by stacking with the first insulating film 71 outside the trench. As a result, the first unburied insulating film 271 and the second unburied insulating film 272 are provided in a stacked state.

[0093] In step S212, the front surface side electrode 110 and the rear surface side electrode 130 are formed.

[0094] Figure 4A shows an example of a manufacturing method for the diamond semiconductor device 100. In this example, the description will begin with the step of forming the first insulating film 71. The steps up to the step of forming the termination layer 40 may be the same as other manufacturing methods. The method of forming the termination layer 40 in this example is the same as the method of forming the termination layer 40 in Figure 2B.

[0095] In step S306, a first insulating film 71 is formed. The first insulating film 71 may be formed before the source electrode 120 is formed. The first insulating film 71 may be formed above both the trench portion 50 and the mesa portion 152. The first insulating film 71 may be formed to fill the entire trench. The first insulating film 71 may also be formed above the contact region 60. After the first insulating film 71 is formed, the interface between the termination layer 40 and the first insulating film 71 may be improved by annealing or the like. Note that after the first insulating film 71 is formed, the termination layer 40 may be formed between the first insulating film 71 and the epitaxial layer 30.

[0096] In step S308, the first insulating film 71 is etched. The first insulating film 71 outside the trench may be removed by etching. In this example, the first insulating film 71 above both the trench portion 50 and the mesa portion 152 is etched. As a result, the first insulating film 71 may be provided only inside the trench. The step of etching the first insulating film 71 may be performed by any method, such as chemical etching or chemical mechanical polishing (CMP). The source electrode 120 may be formed after the first insulating film 71 is formed or after the first insulating film 71 is etched.

[0097] Fig. 4B shows an example of a method for manufacturing the diamond semiconductor device 100. This figure shows a process subsequent to step S308 in Fig. 4A.

[0098] In step S310, the second insulating film 72 is formed. The second insulating film 72 may be formed on the upper surface of the first insulating film 71, or may be formed on the upper surface of the source electrode 120. In this example, the second insulating film 72 is formed on the upper surface of the etched first insulating film 71. The buried insulating portion 170 may be a region where the first insulating film 71 remains. The non-buried insulating portion 270 may be a region where the second insulating film 72 remains.

[0099] The front surface side electrode 110 is formed on the upper surface of the second insulating film 72. The front surface side electrode 110 may be formed in a region where the first insulating film 71 is etched. This makes it possible to adjust the thickness of the front surface side insulating film 70 that exists between the front surface side electrode 110 and the diamond layer 15.

[0100] 5 shows an example of a top view of the diamond semiconductor device 100. This figure shows a top view of the diamond semiconductor device 100 functioning as a MOSFET. In this figure, only representative components such as the trench portion 50 and the source electrode 120 are shown, and other components are omitted.

[0101] The diamond semiconductor device 100 of this example comprises a plurality of trench portions 50 extending in a predetermined extension direction (Y-axis direction). The diamond semiconductor device 100 of this example also comprises a plurality of source electrodes 120 extending in a predetermined extension direction (Y-axis direction). That is, the trench portions 50 and the source electrodes 120 of this example extend in the same direction. The plurality of source electrodes 120 may be electrically connected to a common source pad.

[0102] The pitch Pm indicates the pitch of the repeating unit structure of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example has unit structures repeated in a predetermined repeating direction (X-axis direction). The pitch Pm may be the distance from the center of a source electrode 120 to the center of an adjacent source electrode 120.

[0103] The trench width Wt may be the width of the trench portion 50. That is, the trench width Wt may be the width of the front surface-side insulating film 70 in the trench portion 50. The trench width Wt may be the width of the front surface-side insulating film 70 at the upper end of the trench portion 50.

[0104] 6A shows an example of a top view and a cross-sectional view of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example comprises a trench portion 50 surrounded by a source electrode 120. In the top view, only representative components such as the trench portion 50 and the source electrode 120 are shown, and other components are omitted.

[0105] The source electrode 120 has a ring-shaped configuration in top view. The source electrode 120 in this example has a square ring shape. That is, both the outer and inner peripheries of the source electrode 120 are square in top view. However, the shape of the source electrode 120 may be a ring-shaped configuration of other shapes, such as a rectangle, a polygon, a circle, or an ellipse, in top view. If the shape of the source electrode 120 has corners, the vertices of the corners may be rounded. For example, the polygonal source electrode 120 may be a polygon with rounded vertices.

[0106] The pitch Pm indicates the pitch of the repeating unit structure of the diamond semiconductor device 100. The pitch Pm may be the distance from the center of one side of the source electrode 120 to the center of the opposing side. The pitch Pm may be 1 μm or more and 15 μm or less. The pitch Pm is, for example, 4 μm. The diamond semiconductor device 100 of this example has the same pitch Pm in the X-axis direction and the Y-axis direction, but may have different pitches Pm in the X-axis direction and the Y-axis direction.

[0107] The trench width Wt may be the width of the trench portion 50 in the repeating direction. The shape of the trench portion 50 in this example is a square, with the lengths of the four sides equal to the trench width Wt, when viewed from above. The shape of the trench portion 50 may be other shapes, such as a rectangle, a polygon, a circle, or an ellipse, when viewed from above. If the shape of the trench portion 50 has corners, the vertices of the corners may be rounded. For example, a polygonal trench portion 50 may be a polygon with rounded vertices. The trench width Wt may be 50 nm or more and 2.0 μm or less, or 100 nm or more and 1.5 μm or less. The trench width Wt is, for example, 500 nm.

[0108] The trench depth Dt is the width in the depth direction of the trench portion 50. The trench depth Dt may be the distance from the upper surface of the termination layer 40 to the lower end of the front surface side insulating film 70. The trench depth Dt may be 60 nm or more and 20 μm or less. The trench depth Dt may be the same in the diamond semiconductor device 100 of other embodiments.

[0109] 6B shows an example of a top view of the integrated structure of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example has a trench portion 50 surrounded by a mesa portion 152. In this figure, only representative components such as the trench portion 50 and the mesa portion 152 are shown, and other components are omitted. The symbol Ms indicates the region of the mesa portion 152.

[0110] The diamond semiconductor device 100 of this example has a plurality of trench portions 50 repeatedly arranged at a pitch Pm. The plurality of trench portions 50 may be arranged at equal intervals in each of the X-axis direction and the Y-axis direction. The plurality of trench portions 50 may be arranged in an oblique direction at any angle. The plurality of trench portions 50 of this example are provided periodically, but may also be provided randomly at any density.

[0111] 7A shows an example of a top view and a cross-sectional view of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example comprises a mesa portion 152 surrounded by a trench portion 50. In the top view, only representative components such as the trench portion 50, the source electrode 120, and the mesa portion 152 are shown, and other components are omitted.

[0112] The trench portion 50 has a ring-shaped configuration in top view. In this example, the trench portion 50 has a square ring shape. That is, both the outer and inner peripheries of the trench portion 50 are square in top view. However, the shape of the trench portion 50 may be a ring-shaped configuration of other shapes, such as a rectangle, a polygon, a circle, or an ellipse, in top view. If the trench portion 50 has corners, the vertices of the corners may be rounded. For example, the polygonal trench portion 50 may be a polygon with rounded vertices.

[0113] The pitch Pm indicates the pitch of the repeating unit structure of the diamond semiconductor device 100. The pitch Pm may be the distance from the center of one side of the trench portion 50 to the center of the opposing side. The pitch Pm may be 1 μm or more and 15 μm or less. The pitch Pm is, for example, 4 μm. The diamond semiconductor device 100 of this example has the same pitch Pm in the X-axis direction and the Y-axis direction, but may have different pitches Pm in the X-axis direction and the Y-axis direction.

[0114] The trench width Wt may be the width of one side of the trench portion 50. The trench width Wt may be 50 nm or more and 2.0 μm or less, or 100 nm or more and 1.5 μm or less. The trench width Wt is, for example, 500 nm.

[0115] The source electrode 120 in this example has a square shape when viewed from above. The source electrode 120 may have other shapes, such as a rectangle, a polygon, a circle, or an ellipse, when viewed from above. When the shape of the source electrode 120 has corners, the vertices of the corners may be rounded. For example, the polygonal source electrode 120 may have a polygon with rounded vertices.

[0116] 7B shows an example of a top view of the integrated structure of the diamond semiconductor device 100. The diamond semiconductor device 100 of this example comprises a mesa portion 152 surrounded by a trench portion 50. In this figure, only representative components such as the trench portion 50 and the mesa portion 152 are shown, and other components are omitted.

[0117] The diamond semiconductor device 100 of this example has a plurality of mesas 152 repeatedly arranged at a pitch Pm. The plurality of mesas 152 may be arranged at equal intervals in both the X-axis direction and the Y-axis direction. The plurality of mesas 152 may be arranged in an oblique direction at any angle. The plurality of mesas 152 of this example are arranged periodically, but may also be arranged randomly at any density.

[0118] 8 shows an outline of the configuration of the semiconductor module 200. The semiconductor module 200 includes the diamond semiconductor device 100 that functions as a MOSFET. The semiconductor module 200 includes a gate terminal 210, a source terminal 220, and a drain terminal 230. The gate terminal 210, the source terminal 220, and the drain terminal 230 may be external connection terminals for electrically connecting the semiconductor module 200 to the outside.

[0119] The gate terminal 210 is connected to the front surface side electrode 110 of the diamond semiconductor device 100. The source terminal 220 is connected to the source electrode 120 of the diamond semiconductor device 100. The drain terminal 230 is connected to the back surface side electrode 130 of the diamond semiconductor device 100. The diamond semiconductor device 100 may be provided on the insulating substrate of the semiconductor module 200 with the back surface side electrode 130 facing downward. The back surface side electrode 130 may be electrically connected to the drain terminal 230 via metal wiring on the insulating substrate.

[0120] The semiconductor module 200 may have a single diamond semiconductor device 100, or may have a plurality of diamond semiconductor devices 100. The semiconductor module 200 may have an inverter circuit. The semiconductor module 200 may have an inverter circuit that combines a P-type channel diamond semiconductor device 100 and an N-type channel semiconductor element. The N-type channel semiconductor element may be the N-type channel diamond semiconductor device 100, or may be another semiconductor element such as GaN or SiC.

[0121] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0122] 10: Diamond substrate, 11: Front surface, 12: Back surface, 15: Diamond layer, 20: Doped region, 21: First region, 22: Second region, 25: Doped layer, 30: Epitaxial layer, 40: Termination layer, 50: Trench portion, 60: Contact region, 70: Front surface side insulating film, 71: First insulating film, 72: Second insulating film, 110: Front surface side electrode, 120: Source electrode, 130: Back surface side electrode, 152: Mesa portion, 100: Diamond semiconductor device, 170: Buried insulating portion, 171: First buried insulating film, 172: Second buried insulating film, 200: Semiconductor module, 210: Gate terminal, 220: Source terminal, 230: Drain terminal, 270: Non-buried insulating portion, 271: First non-buried insulating film, 272: Second non-buried insulating film

Claims

1. A diamond semiconductor device having a trench portion on its front surface, Diamond layer and A diamond epitaxial layer provided on the diamond layer, A front-side insulating film provided above the epitaxial layer, The front-side electrode provided on the front-side insulating film, Equipped with, The aforementioned front-side insulating film has an embedded insulating portion that is in contact with the trench side wall of the trench portion and filled inside the trench portion. The embedded insulating portion fills 50% or more of the inside of the trench in the trench portion. Diamond semiconductor device.

2. The aforementioned front-side insulating film has a non-embedded insulating portion provided above the trench portion and the adjacent mesa portion. The diamond semiconductor device according to claim 1.

3. The material of the embedded insulating portion is the same as the material of the non-embedded insulating portion. The diamond semiconductor device according to claim 2.

4. The aforementioned embedded insulating portion is A first embedded insulating film is provided in contact with the trench side wall of the trench portion, In the trench portion, a second embedded insulating film is provided laminated with the first embedded insulating film, has The diamond semiconductor device according to claim 1.

5. The thickness of the first embedded insulating film is thinner than that of the second embedded insulating film. The diamond semiconductor device according to claim 4.

6. A diamond semiconductor device having a trench portion on its front surface, Diamond layer and An epitaxial layer of diamond provided on the diamond layer, A front-side insulating film provided above the epitaxial layer, The front-side electrode provided on the front-side insulating film, Equipped with, The aforementioned front-side insulating film has an embedded insulating portion that is in contact with the trench side wall of the trench portion and filled inside the trench portion. The aforementioned embedded insulating portion is A first embedded insulating film is provided in contact with the trench side wall of the trench portion, In the trench portion, a second embedded insulating film is provided laminated with the first embedded insulating film, It has, The thickness of the first embedded insulating film is 10 nm or more and 100 nm or less. Diamond semiconductor device.

7. A diamond semiconductor device having a trench portion on its front surface, Diamond layer and An epitaxial layer of diamond provided on the diamond layer, A front-side insulating film provided above the epitaxial layer, The front-side electrode provided on the front-side insulating film, Equipped with, The aforementioned front-side insulating film has an embedded insulating portion that is in contact with the trench side wall of the trench portion and filled inside the trench portion. The aforementioned front-side insulating film has a non-embedded insulating portion provided above the trench portion and the adjacent mesa portion. The material of the embedded insulating portion is different from the material of the non-embedded insulating portion. Diamond semiconductor device.

8. The dielectric constant of the embedded insulating portion is lower than that of the non-embedded insulating portion. The diamond semiconductor device according to claim 7.

9. A diamond semiconductor device having a trench portion on its front surface, Diamond layer and An epitaxial layer of diamond provided on the diamond layer, A front-side insulating film provided above the epitaxial layer, The front-side electrode provided on the front-side insulating film, Equipped with, The aforementioned front-side insulating film has an embedded insulating portion that is in contact with the trench side wall of the trench portion and filled inside the trench portion. The aforementioned front-side insulating film has a non-embedded insulating portion provided above the trench portion and the adjacent mesa portion. The material of the embedded insulating part is SiO ２ SiNx, HfO ２ , HfSiO ４ or including at least one of BN, The material of the non-embedded insulating part is Al ２ O ３ SiO ２ SiNx, HfO ２ , HfSiO ４ or including at least one of BN Diamond semiconductor device.

10. A diamond semiconductor device having a trench portion on its front surface, Diamond layer and An epitaxial layer of diamond provided on the diamond layer, A front-side insulating film provided above the epitaxial layer, The front-side electrode provided on the front-side insulating film, Equipped with, The aforementioned front-side insulating film has an embedded insulating portion that is in contact with the trench side wall of the trench portion and filled inside the trench portion. The aforementioned front-side insulating film has a non-embedded insulating portion provided above the trench portion and the adjacent mesa portion. The material of the embedded insulating part is Al ２ O ３ , SiO ２ , SiNx, HfO ２ , HfSiO ４ or at least one of BN, and The material of the non-embedded insulating part is SiO ２ SiNx, HfO ２ , HfSiO ４ or including at least one of BN, Diamond semiconductor device.

11. The material of the embedded insulating portion and the non-embedded insulating portion is Al ２ O ３ That is The diamond semiconductor device according to claim 2.

12. The aforementioned front-side electrode extends from above one side wall of the trench portion to above the other side wall, covering the upper part of the embedded insulating portion. The diamond semiconductor device according to any one of claims 1 to 11.

13. The aforementioned front-side electrode is not provided above the trench portion, but rather above the mesa portion adjacent to the trench portion. The diamond semiconductor device according to any one of claims 1 to 11.

14. The diamond layer is provided above the source electrode, The aforementioned front-side electrode is a gate electrode and is also provided above the source electrode. The diamond semiconductor device according to any one of claims 1 to 11.

15. The system includes an end layer provided between the epitaxial layer and the trench portion. The diamond semiconductor device according to any one of claims 1 to 11.

16. A diamond semiconductor device having a trench portion on its front surface, Diamond layer and An epitaxial layer of diamond provided on the diamond layer, A front-side insulating film provided above the epitaxial layer, The front-side electrode provided on the front-side insulating film, Equipped with, The aforementioned front-side insulating film has an embedded insulating portion that is in contact with the trench side wall of the trench portion and filled inside the trench portion. The trench width of the trench portion is 100 nm or more and 1.5 μm or less. The trench depth of the trench portion is 60 nm or more and 20 μm or less. Diamond semiconductor device.

17. The trench portion has a taper, The taper angle of the aforementioned taper is 60 degrees or more and 100 degrees or less. The diamond semiconductor device according to any one of claims 1 to 11.

18. The front side electrode is provided above the trench portion. The diamond semiconductor device according to any one of claims 1 to 11.

19. The inside of the trench portion is filled with the embedded insulating portion made of the same material. The diamond semiconductor device according to any one of claims 1 to 3.

20. A method for manufacturing a diamond semiconductor device having a trench portion on its front surface, The stage of creating the diamond layer, The steps include forming an epitaxial layer of diamond on the aforementioned diamond layer, The steps include forming a front-side insulating film above the epitaxial layer, The steps include forming the front-side electrode on the front-side insulating film, Equipped with, The step of forming the insulating film on the front side includes the step of forming an embedded insulating portion that is in contact with the trench side wall of the trench portion and filled inside the trench portion, The embedded insulating portion fills 50% or more of the inside of the trench in the trench portion. A method for manufacturing a diamond semiconductor device.

21. The step of forming the aforementioned embedded insulating portion is: The steps include forming a first embedded insulating film in contact with the trench side wall of the trench portion, The steps include forming a second embedded insulating film by laminating it with the first embedded insulating film in the trench portion, has The method for manufacturing a diamond semiconductor device according to claim 20.

22. A method for manufacturing a diamond semiconductor device having a trench portion on its front surface, The stage of creating the diamond layer, The steps include forming an epitaxial layer of diamond on the aforementioned diamond layer, The steps include forming a front-side insulating film above the epitaxial layer, The steps include forming the front-side electrode on the front-side insulating film, Equipped with, The step of forming the insulating film on the front side includes the step of forming an embedded insulating portion that is in contact with the trench side wall of the trench portion and filled inside the trench portion. The step of forming the aforementioned embedded insulating portion is: The steps include forming a first embedded insulating film in contact with the trench side wall of the trench portion, The steps include forming a second embedded insulating film by laminating it with the first embedded insulating film in the trench portion, It has, The step of forming the embedded insulating portion includes a step of annealing the diamond semiconductor device, which occurs after the step of forming the first embedded insulating film and before the step of forming the second embedded insulating film. A method for manufacturing a diamond semiconductor device.