Silicon carbide substrate, method for manufacturing silicon carbide substrate, silicon carbide semiconductor device, and method for manufacturing silicon carbide semiconductor device

Abstract

Before epitaxial growth of an epitaxial layer (40) including a buffer layer (11), a crystal defect introduction region (41) is formed by introducing point defects (42) at high density from a front surface (1a) of a starting substrate (1). Since an Si core partial dislocation of a BPD (30) becomes less likely to move in the vicinity of the front surface (1a) of the starting substrate (1) due to the crystal defect introduction region (41), even if the in-plane temperature distribution of the front surface (1a) of the starting substrate (1) is unstable during the epitaxial growth of the epitaxial layer (40), the distance between two Shockley partial dislocations constituting the BPD (30) in the starting substrate is less likely to increase, and the BPD (30) in the starting substrate (1) is converted into a TED (31) with high efficiency at an interface (12) between the starting substrate (1) and the buffer layer (11), and is less likely to propagate to the epitaxial layer (40). Consequently, the propagation of the BPD (30) in the starting substrate (1) to the epitaxial layer (40) can be suppressed.

Description

Silicon carbide substrate, method for manufacturing silicon carbide substrate, silicon carbide semiconductor device, and method for manufacturing silicon carbide semiconductor device

[0001] The present disclosure relates to a silicon carbide substrate, a method for manufacturing a silicon carbide substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide semiconductor device.

[0002] Patent Document 1 listed below describes a technology for suppressing bipolar degradation of a semiconductor device by ion-implanting impurities or crystal defects that act as minority carrier lifetime killers into a portion of a silicon carbide (SiC) semiconductor body from a first surface to a certain depth, then epitaxially growing a SiC layer on the first surface of the SiC semiconductor body, and forming a semiconductor device in or on the SiC layer. Non-Patent Document 1 listed below describes a technology for suppressing bipolar degradation by introducing point defects or hydrogen into a SiC epitaxial layer formed on a SiC starting substrate.

[0003] Japanese Patent Application Laid-Open No. 2021-15978

[0004] S.Harada et al., Suppression of stacking fault expansion in a 4H-SiC epitaxial layer by proton irradiation, Scientific Reports, 2002, 12:13542

[0005] In the above-mentioned Patent Document 1, the higher the density of the impurity that acts as a lifetime killer of minority carriers is introduced into the SiC semiconductor body, or the deeper the impurity is introduced from the first surface of the SiC semiconductor body, the higher the dose and acceleration energy of the ion implantation required, resulting in higher manufacturing costs.In the above-mentioned Non-Patent Document 1, the extension of stacking faults (SFs) from basal plane dislocations (BPDs) already present in the SiC epitaxial layer is suppressed, but the propagation of BPDs from the SiC starting substrate to the epitaxial layer during epitaxial growth cannot be suppressed.

[0006] An object of the present disclosure is to provide a silicon carbide substrate, a method for manufacturing a silicon carbide substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide semiconductor device that are capable of suppressing the propagation of BPDs in a starting substrate.

[0007] A silicon carbide substrate according to one aspect of the present disclosure is as follows: an epitaxial layer having a lower impurity concentration than the semiconductor substrate is provided on a front surface of a semiconductor substrate made of silicon carbide; a crystal defect introduction region containing a relatively large number of point defects is provided within the semiconductor substrate and in contact with the epitaxial layer; the crystal defect introduction region has a predetermined depth from the front surface of the semiconductor substrate.

[0008] A silicon carbide semiconductor device according to one aspect of the present disclosure is as follows. A silicon carbide base has a semiconductor substrate made of silicon carbide, an epitaxial layer having a lower impurity concentration than the semiconductor substrate, a crystal defect introduction region containing a relatively large number of point defects, a first main surface, and a second main surface. The epitaxial layer is provided on a front surface of the semiconductor substrate. The crystal defect introduction region is provided inside the semiconductor substrate and in contact with the epitaxial layer. The crystal defect introduction region has a predetermined depth from the front surface of the semiconductor substrate.

[0009] The first main surface is formed on the outermost surface on the epitaxial layer side. The second main surface is formed on the back surface of the semiconductor substrate. An element structure is provided on the first main surface side of the silicon carbide substrate. A first electrode is provided on the first main surface and electrically connected to the element structure. A second electrode is provided on the second main surface. A pn ​​junction that operates bipolarly between the first electrode and the second electrode is provided inside the silicon carbide substrate.

[0010] A method for manufacturing a silicon carbide substrate according to one aspect of the present disclosure is as follows: An introduction step is performed in which point defects are introduced from the front surface of a semiconductor substrate made of silicon carbide to a predetermined depth to form a crystal defect introduction region; A film formation step is performed in which an epitaxial layer having an impurity concentration lower than that of the semiconductor substrate is epitaxially grown on the front surface of the semiconductor substrate in contact with the crystal defect introduction region.

[0011] A method for manufacturing a silicon carbide semiconductor device according to one aspect of the present disclosure is as follows: a first step of fabricating a silicon carbide substrate made of silicon carbide is performed; a second step of forming an element structure on a first main surface side of the silicon carbide substrate is performed; a third step of forming a first electrode on the first main surface, the first electrode being electrically connected to the element structure; and a fourth step of forming a second electrode on a second main surface of the silicon carbide substrate. Prior to the third step, a pn junction that operates bipolarly is formed between the first electrode and the second electrode inside the silicon carbide substrate.

[0012] In the first step, an introduction step and a film formation step are performed to fabricate the silicon carbide substrate, with the outermost surface on the epitaxial layer side serving as the first main surface and the back surface of the semiconductor substrate serving as the second main surface. In the introduction step, point defects are introduced from the front surface of the semiconductor substrate to a predetermined depth to form a crystal defect introduction region. In the film formation step, an epitaxial layer having an impurity concentration lower than that of the semiconductor substrate is epitaxially grown on the front surface of the semiconductor substrate in contact with the crystal defect introduction region.

[0013] The silicon carbide substrate, method for manufacturing a silicon carbide substrate, silicon carbide semiconductor device, and method for manufacturing a silicon carbide semiconductor device according to the present disclosure have the effect of being able to suppress propagation of BPDs within the starting substrate.

[0014] FIG. 1 is a cross-sectional view (part 1) showing an example structure of a silicon carbide substrate used in a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view (part 2) showing an example structure of a silicon carbide substrate used in a silicon carbide semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view (part 1) schematically showing a state during manufacture of a silicon carbide substrate used in a silicon carbide semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view (part 2) schematically showing a state during manufacture of a silicon carbide substrate used in a silicon carbide semiconductor device according to an embodiment. FIG. 5 is a cross-sectional view (part 6) schematically showing another example state during manufacture of a silicon carbide substrate used in a silicon carbide semiconductor device according to an embodiment. FIG. 6 is an explanatory diagram schematically showing the principle of BPD-TED conversion during manufacture of a silicon carbide substrate used in a silicon carbide semiconductor device according to an embodiment. FIG. 7 is a cross-sectional view (part 1) showing an example structure of a silicon carbide semiconductor device according to an embodiment. FIG. 8 is a cross-sectional view (part 1) showing an example structure of a silicon carbide substrate used in a silicon carbide semiconductor device of a reference example. FIG. 9 is a cross-sectional view (part 2) showing an example structure of a silicon carbide substrate used in a silicon carbide semiconductor device of a reference example. FIG. 10 is a cross-sectional view (part 3) showing an example structure of a silicon carbide substrate used in a silicon carbide semiconductor device of a reference example. FIG. 11 is an explanatory diagram schematically showing the principle of BPD propagation in an SiC substrate to an epitaxial layer epitaxially grown on the SiC substrate of a reference example. FIG. 12 is a graph showing a typical temperature profile when epitaxially growing epitaxial layers that become a buffer layer and a drift layer. FIG. 13 is a graph showing the relationship between annealing time and the total number of through-hole BPDs in a silicon carbide substrate obtained by an experiment. FIG. 14 is a top view schematically showing the temperature distribution at a location where through-hole BPDs increase in the surface of the silicon carbide substrate. FIG. 15 is a characteristic diagram showing the shear stress distribution in an epitaxial growth furnace in the surface of the silicon carbide substrate of FIG. 14.

[0015] <Summary of Embodiments of the Present Disclosure> (1) A silicon carbide base according to one aspect of the present disclosure is as follows: An epitaxial layer having a lower impurity concentration than the semiconductor substrate is provided on a front surface of a semiconductor substrate made of silicon carbide; A crystal defect introduction region containing a relatively large number of point defects is provided within the semiconductor substrate and in contact with the epitaxial layer; The crystal defect introduction region has a predetermined depth from the front surface of the semiconductor substrate.

[0016] According to the above disclosure, it is possible to provide a silicon carbide substrate in which BPDs in a semiconductor substrate are converted to TEDs with high efficiency at the interface with the epitaxial layer, and the number of BPDs in the epitaxial layer is small.

[0017] (2) In the silicon carbide substrate according to the present disclosure, in the above-mentioned (1), the semiconductor substrate may contain more point defects than the epitaxial layer.

[0018] According to the above disclosure, it is possible to provide a silicon carbide substrate containing minority carrier lifetime killers at a high density.

[0019] (3) In the silicon carbide substrate according to the present disclosure, in the above-mentioned (1) or (2), the crystal defect introduction region may be provided only in a surface region of the front surface of the semiconductor substrate.

[0020] According to the above disclosure, it is possible to provide a silicon carbide substrate in which BPDs in a semiconductor substrate are converted to TEDs with high efficiency at the interface with the epitaxial layer, and the number of BPDs in the epitaxial layer is small.

[0021] (4) In the silicon carbide substrate according to the present disclosure, in the above-mentioned (3), the semiconductor substrate may contain a relatively large amount of hydrogen or nitrogen in the crystal defect introduction region.

[0022] According to the above disclosure, it is possible to provide a silicon carbide substrate containing minority carrier lifetime killers at a high density.

[0023] (5) A silicon carbide semiconductor device according to one aspect of this disclosure is as follows. A silicon carbide base includes a semiconductor substrate made of silicon carbide, an epitaxial layer having an impurity concentration lower than that of the semiconductor substrate, a crystal defect introduction region containing a relatively large number of point defects, a first main surface, and a second main surface. The epitaxial layer is provided on a front surface of the semiconductor substrate. The crystal defect introduction region is provided inside the semiconductor substrate and in contact with the epitaxial layer. The crystal defect introduction region has a predetermined depth from the front surface of the semiconductor substrate.

[0024] The first main surface is formed on the outermost surface on the epitaxial layer side. The second main surface is formed on the back surface of the semiconductor substrate. An element structure is provided on the first main surface side of the silicon carbide substrate. A first electrode is provided on the first main surface and electrically connected to the element structure. A second electrode is provided on the second main surface. A pn ​​junction that operates bipolarly between the first electrode and the second electrode is provided inside the silicon carbide substrate.

[0025] According to the above disclosure, BPDs in the semiconductor substrate are converted to TEDs with high efficiency at the interface with the epitaxial layer, making it possible to use a silicon carbide substrate with a small number of BPDs in the epitaxial layer, thereby suppressing an increase in forward voltage (bipolar degradation) of the silicon carbide semiconductor device.

[0026] (6) A method for manufacturing a silicon carbide substrate according to one aspect of the present disclosure includes: an introduction step of introducing point defects from a front surface of a semiconductor substrate made of silicon carbide to a predetermined depth to form a crystal defect introduction region; and a film formation step of epitaxially growing an epitaxial layer having an impurity concentration lower than that of the semiconductor substrate on the front surface of the semiconductor substrate in contact with the crystal defect introduction region.

[0027] According to the above disclosure, the Si core partial dislocations of BPDs are less likely to move near the front surface of the semiconductor substrate, and the efficiency of conversion of BPDs to TEDs in the starting substrate (BPD-TED conversion efficiency) can be stabilized, thereby enabling the propagation of BPDs in the starting substrate to be suppressed with high efficiency.

[0028] (7) Furthermore, in the method for manufacturing a silicon carbide substrate according to the present disclosure described above in (6), the film formation step may include raising the temperature inside an epitaxial growth furnace to an epitaxial growth temperature with the semiconductor substrate inserted in the epitaxial growth furnace, and epitaxially growing the epitaxial layer at the epitaxial growth temperature.

[0029] According to the above disclosure, even if the temperature of the front surface of the semiconductor substrate, the temperature distribution within the surface of the semiconductor substrate, or the heating time of the semiconductor substrate fluctuates and becomes unstable, the BPD-TED conversion efficiency can be stabilized.

[0030] (8) A method for manufacturing a silicon carbide semiconductor device according to one aspect of the present disclosure is as follows: a first step of fabricating a silicon carbide substrate made of silicon carbide is performed; a second step of forming an element structure on a first main surface side of the silicon carbide substrate is performed; a third step of forming a first electrode on the first main surface, the first electrode being electrically connected to the element structure; and a fourth step of forming a second electrode on a second main surface of the silicon carbide substrate. Prior to the third step, a pn junction operating in bipolar mode is formed inside the silicon carbide substrate between the first electrode and the second electrode.

[0031] In the first step, an introduction step and a film formation step are performed to fabricate the silicon carbide substrate, with the outermost surface on the epitaxial layer side serving as the first main surface and the back surface of the semiconductor substrate serving as the second main surface. In the introduction step, point defects are introduced from the front surface of the semiconductor substrate to a predetermined depth to form a crystal defect introduction region. In the film formation step, an epitaxial layer having an impurity concentration lower than that of the semiconductor substrate is epitaxially grown on the front surface of the semiconductor substrate in contact with the crystal defect introduction region.

[0032] According to the above disclosure, it is possible to manufacture a silicon carbide semiconductor device using a silicon carbide substrate in which BPDs in a semiconductor substrate are converted to TEDs with high efficiency at the interface with the epitaxial layer, and the number of BPDs in the epitaxial layer is small, thereby suppressing bipolar degradation of the silicon carbide semiconductor device.

[0033] 8 to 10 are cross-sectional views showing examples of the structure of a silicon carbide substrate used in a silicon carbide semiconductor device of a reference example. In the silicon carbide semiconductor device of the reference example, a starting substrate 101 (n ++ On the front surface 101a of the n-type semiconductor substrate 100 (shown as n-type semiconductor substrate 100b), a n-type semiconductor substrate 100b is formed. - type epitaxial layer (n - epitaxially grown SiC substrate 100 (FIG. 8), or one or more epitaxial layers (n + epi, n +++ In this example, SiC substrates 110 and 120 (FIGS. 9 and 10: epitaxial wafers) are used, each of which has a SiC substrate 110 or 120 provided thereon with a SiC layer (denoted as epi).

[0034] The starting substrate 101 is made of, for example, a single crystal of 4H—SiC (four-layer hexagonal silicon carbide). ++ The starting substrate 101 is a bulk substrate of the type. The front surface 101a of the starting substrate 101 is, for example, a (0001) plane, a so-called Si plane, having a predetermined off-angle (for example, about 4°) in the <11-20> direction. Basal plane dislocations (BPDs) 130 exist within the starting substrate 101. The drift layer 102 and buffer layers 111 and 121 are epitaxially grown successively on the front surface 101a of the starting substrate 101 in an epitaxial growth furnace heated to a predetermined temperature, with the impurity concentrations and thicknesses appropriately controlled.

[0035] An element structure of a bipolar device such as an IGBT (Insulated Gate Bipolar Transistor) or an element structure that performs parasitically bipolar operation such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor with an insulated gate made of a three-layer structure of metal-oxide film-semiconductor) is formed inside the drift layer 102, or on the surface of the drift layer 102 opposite to the starting substrate 101 side, or both.

[0036] In the SiC substrate 100 shown in Fig. 8, basal plane dislocations (BPDs) 130 in the starting substrate 101 propagate (are inherited) to the drift layer 102 during epitaxial growth of the drift layer 102. When a certain amount of recombination energy is supplied to the BPDs 130 in the drift layer 102, which is generated by the recombination of carriers (electrons and holes) in the drift layer 102 during bipolar operation (forward conduction) of the silicon carbide semiconductor device, the BPDs 130 expand while forming Shockley stacking faults (SFs) (not shown). The forward voltage of the silicon carbide semiconductor device increases in proportion to the area of ​​the SFs, which are planar defects generated in the drift layer 102 (bipolar degradation).

[0037] Therefore, as shown in FIGS. 9 and 10, a n-type silicon dioxide film having a higher impurity concentration than the drift layer 102 is formed on the front surface 101a of the starting substrate 101. + The epitaxial growth of the buffer layer 111 suppresses the propagation of BPDs 130 in the starting substrate 101 to the epitaxial layers (the buffer layers 111 and 121 and the drift layer 102) during epitaxial growth. The buffer layer 111 is a dislocation conversion layer that converts BPDs 130 in the starting substrate 101 into threading edge dislocations (TEDs) 131 during its own epitaxial growth.

[0038] When BPDs 130 in the starting substrate 101 are converted into TEDs 131, the TEDs 131 also propagate to the drift layer 102 epitaxially grown on the buffer layer 111. The TEDs 131 do not generate SFs 132 (see FIG. 11 described later) even when recombination energy is supplied. +++ A buffer layer 121 of a type may be provided. The buffer layer 121 causes holes supplied from the drift layer 102 to disappear through recombination during bipolar operation of the silicon carbide semiconductor device, and suppresses the expansion of SFs 132 from BPDs 130 in the starting substrate 101.

[0039] However, even if a buffer layer 111 is provided between the starting substrate 101 and the drift layer 102, the BPDs 130 in the starting substrate 101 cannot be efficiently converted to TEDs 131. The reason for this is as follows. FIG. 11 is an explanatory diagram schematically showing the principle of propagation of BPDs in a SiC substrate to an epitaxial layer epitaxially grown on the SiC substrate of the reference example. FIG. 12 is a graph showing a typical temperature profile when epitaxially growing epitaxial layers that become a buffer layer and a drift layer. The horizontal axis of FIG. 12 represents the annealing time [minutes (min)], and the vertical axis represents the annealing (heat treatment) temperature [°C].

[0040] 11 shows a cross-sectional view of starting substrate 101 before being inserted into an epitaxial growth furnace (hereinafter referred to as the initial stage), a cross-sectional view of starting substrate 101 during temperature rise and hydrogen (H2) etching before epitaxial growth, and a cross-sectional view of starting substrate 101 during epitaxial growth (denoted as "epitaxial growth" in FIGS. 11 and 12). In FIG. 11, the [11-20] direction is the step-flow growth direction of epitaxial layer 140 epitaxially grown on front surface 101a of starting substrate 101, and the [1-100] direction is the direction parallel to front surface 101a of starting substrate 101. Times T2 to T5, T ex corresponds to the annealing time in FIG.

[0041] To epitaxially grow epitaxial layer 140 on front surface 101a of starting substrate 101, the temperature inside an epitaxial growth furnace containing starting substrate 101 is increased or decreased according to the temperature profile shown in Fig. 12. Specifically, after starting substrate 101 is first inserted into an epitaxial growth furnace (not shown), the temperature inside the epitaxial growth furnace is increased to the epitaxial growth temperature (1600°C in this example) in two stages. That is, the temperature inside the epitaxial growth furnace is increased to, for example, 900°C in a predetermined time T1 (first stage of heating), maintained at that temperature for a predetermined time T2, and then further increased to a temperature close to the epitaxial growth temperature in a predetermined time T3 (second stage of heating).

[0042] With the temperature inside the epitaxial growth furnace maintained near the epitaxial growth temperature, front surface 101a of starting substrate 101 is cleaned by dry etching (hydrogen etching) 141 using hydrogen (H) gas for a predetermined time T. Then, with the temperature inside the epitaxial growth furnace maintained at the epitaxial growth temperature, epitaxial layers 140 that will become buffer layers 111 and 121 and drift layer 102 (see FIGS. 9 and 10) are epitaxially grown continuously on front surface 101a of starting substrate 101 for a predetermined time T with the impurity concentrations and thicknesses appropriately controlled. After the epitaxial growth, the temperature inside the epitaxial growth furnace is lowered to room temperature (for example, by natural cooling).

[0043] The starting substrate 101 is a SiC wafer sliced ​​from a SiC ingot grown by sublimation. As shown in FIG. 11 , a perfect dislocation, BPD 130, exists on the basal plane of the starting substrate 101, with a predetermined off-angle. The BPD 130 is decomposed into two parallel Shockley partial dislocations, Si(g) and C(g). A Shockley stacking fault (SF: the hatched portion of the initial starting substrate 101 in FIG. 11 ) 132 exists between the two Shockley partial dislocations, Si(g) and C(g). FIG. 11 shows a BPD 130 with a Burgers vector parallel to the step-flow growth direction of the epitaxial layer 140.

[0044] The Si (silicon) core partial dislocations Si(g) of the BPDs 130 are in a state where they can move freely near the front surface 101a of the starting substrate 101. Therefore, when the temperature in the epitaxial growth furnace is increased (the temperature increase in FIG. 11 ), the Si core partial dislocations Si(g) of the BPDs 130 in the starting substrate 101 are subjected to thermal stress F in the [1-100] direction perpendicular to the step flow growth direction of the epitaxial layer 140 near the front surface 101a of the starting substrate 101. thermal As a result, the distance between the two Shockley partial dislocations Si(g) and C(g) of the BPD 130 partially increases, and the SF 132 expands (increases in area) only near the front surface 101 a of the starting substrate 101.

[0045] The enlarged portion of SF 132 is subsequently removed by hydrogen etching 141 on the front surface 101a of the starting substrate 101. However, even during hydrogen etching 141, the Si core partial dislocations Si(g) are still oxidized by the thermal stress F thermal Since the starting substrate 101 continues to receive hydrogen, the expanded portion of the SF 132 is removed by hydrogen etching 141, and at the same time, the SF 132 expands again near the newly exposed surface on the front surface 101 a of the starting substrate 101 (during hydrogen etching in FIG. 11 ). The expansion of the SF 132 occurs in BPDs 130, among the multiple BPDs 130 in the starting substrate 101, that have a Burgers vector parallel to the step-flow growth direction of the epitaxial layer 140.

[0046] When the epitaxial layer 140 that becomes the buffer layer 111 is epitaxially grown on the front surface 101a of the starting substrate 101, the Si core partial dislocations Si(g) are displaced by the thermal stress F thermal The direction of pushing back (thermal stress F thermal The stress F epi The buffer layer 111 exerts a stress F epi The apparent thermal stress F in the vicinity of the front surface 101a of the starting substrate 101 is thermal becomes smaller, the distance between the two Shockley partial dislocations Si(g) and C(g) of the BPD 130 in the starting substrate 101 is reduced.

[0047] When the distance between two Shockley partial dislocations Si(g), C(g) is reduced to a certain value or less near the interface 112 between the starting substrate 101 and the buffer layer 111, the BPD 130 is transformed into a TED 131 at the interface 112 between the starting substrate 101 and the buffer layer 111 (see normal TED 131 in FIGS. 9 and 10 ). Furthermore, the BPD 130 having a Burgers vector that is not parallel to the step-flow growth direction of the epitaxial layer 140 is transformed into a TED 131 at the interface 112 between the starting substrate 101 and the buffer layer 111 (not shown). The TED 131 propagates through the epitaxial layer 140 in a direction perpendicular to the front surface 101 a of the starting substrate 101.

[0048] On the other hand, before the epitaxial growth of the epitaxial layer 140, the thermal stress F thermalIf the SF 132 is expanded too much by the stress F epi Even if the starting substrate 101 is subjected to the ion beam irradiation, the distance between the two Shockley partial dislocations Si(g) and C(g) does not decrease sufficiently. As a result, the BPDs 130 in the starting substrate 101 are not converted to TEDs 131 at the interface 112 between the starting substrate 101 and the buffer layer 111, but continue to propagate in the step-flow growth direction in the epitaxial layer 140 (Abnormal BPDs 130 in FIGS. 9 and 10 ), or are converted to TEDs 131 later in the epitaxial layer 140 (Abnormal BPDs 130 in FIGS. 9 and 10 ).

[0049] Fig. 13 is a graph showing the experimental relationship between annealing time and the total number of through-hole BPDs in a silicon carbide substrate. The horizontal axis of Fig. 13 represents annealing time (minutes), and the vertical axis represents the total number of through-hole BPDs in the silicon carbide substrate (number / wafer). The silicon carbide substrate in Fig. 13 is an epitaxial wafer (corresponding to SiC substrate 110 in Fig. 9 ) formed by depositing an epitaxial layer 140 on the front surface 101a of a starting substrate 101. Fig. 13 shows the number of BPDs 130 (hereinafter referred to as "through-hole BPDs") propagating from starting substrate 101 to epitaxial layer 140 when starting substrate 101 is annealed at different annealing temperatures and times before epitaxial growth.

[0050] As shown in Fig. 13, the longer the annealing time of the starting substrate 101 before epitaxial growth, the more the number of through-hole BPDs in the silicon carbide substrate increases. Furthermore, from the results shown in Fig. 13, it is inferred that the higher the annealing temperature of the starting substrate 101 before epitaxial growth, the more the number of through-hole BPDs in the silicon carbide substrate increases. That is, the thermal stress F that the starting substrate 101 receives during the temperature rise in the epitaxial growth furnace in the temperature profile shown in Fig. 11 thermal The higher the annealing temperature during heating in the epitaxial growth furnace is (the higher the annealing temperature is and the longer the annealing time is), the more BPDs 130 are formed in the epitaxial layer 140 .

[0051] Among the silicon carbide substrates (SiC substrates 110) shown in FIG. 13, the through-hole BPD density and thermal stress F of the sample in which the annealing temperature and annealing time of the starting substrate 101 before epitaxial growth were 1250° C. and 30 minutes, respectively, were measured.thermal 14 and 15 show the relationship between the temperature distribution and the number of through-hole BPDs. Fig. 14 is a top view schematically showing the temperature distribution at the location where the number of through-hole BPDs has increased within the surface of the silicon carbide substrate (SiC substrate 110). In Fig. 14, for the silicon carbide substrate in which the starting substrate 101 was annealed before epitaxial growth, locations where the number of through-hole BPDs increased by two or more within a rectangle of a predetermined area are surrounded by dashed lines, compared to the silicon carbide substrate in which the starting substrate 101 was not annealed before epitaxial growth.

[0052] 15 is a characteristic diagram showing the shear stress distribution in the epitaxial growth furnace within the plane of the silicon carbide substrate (SiC substrate 110) of FIG. 14. FIG. 15 is a characteristic diagram showing the shear stress distribution in the epitaxial growth furnace within the plane of the silicon carbide substrate (SiC substrate 110) in the <1-100> direction. thermal 14 and 15, the distribution (shear stress distribution) of the thermal stress F applied to the silicon carbide substrate (SiC substrate 110) in the epitaxial growth furnace is shown in the concentrated area of ​​the through-hole BPDs (the area surrounded by the broken line in FIG. 14 where the through-hole BPDs are increased). thermal It was confirmed that the starting substrate 101 had a high thermal stress F thermal It can be seen that the more the silicon carbide substrate (SiC substrate 110) is subjected to the stress, the more the total number of penetrating BPDs increases.

[0053] Therefore, in the temperature profile shown in FIG. 11, the time T ex In the vicinity of the front surface 101a of the starting substrate 101, the distance between two Shockley partial dislocations Si(g) and C(g) of the BPD 130 in the starting substrate 101 increases, and the SF 132 tends to expand. ex This refers to the time T2 to T4, excluding the first-stage temperature rise time T1, of the total annealing time for raising the temperature in the epitaxial growth furnace. SF132 is particularly likely to expand within the starting substrate 101 during the second-stage temperature rise time T4, in which the temperature rises to 1500° C. or higher.

[0054] The increase in the distance between two Shockley partial dislocations Si(g), C(g) of BPDs 130 in starting substrate 101 is proportional to the temperature of the wafer surface (front surface 101a of starting substrate 101) in an environment (temperature environment in an epitaxial growth furnace) where the temperature is raised at a relatively large temperature gradient to a high temperature of approximately 1500°C or higher, the magnitude of the difference in temperature distribution within the wafer surface, and the length of heating time of starting substrate 101. If the temperature environment in the epitaxial growth furnace deteriorates before the epitaxial growth of epitaxial layer 140, the efficiency with which BPDs 130 in starting substrate 101 are converted to TEDs 131 (hereinafter referred to as BPD-TED conversion efficiency) becomes unstable.

[0055] A problem to be solved in this embodiment is to suppress the propagation of BPDs in the starting substrate by stabilizing the BPD-TED conversion efficiency.

[0056] Preferred embodiments of a silicon carbide substrate, a method for manufacturing a silicon carbide substrate, a silicon carbide semiconductor device, and a method for manufacturing a silicon carbide semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, + and - appended to n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with these, respectively. In the following description of the embodiments and the accompanying drawings, similar components are given the same reference numerals, and redundant explanations will be omitted. Furthermore, in the notation of Miller indices in this specification, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index.

[0057] (Details of the embodiment) The structure of a silicon carbide substrate according to the embodiment that solves the above-mentioned problems will be described below. Figures 1 and 2 are cross-sectional views showing examples of the structure of a silicon carbide substrate used in a silicon carbide semiconductor device according to the embodiment. The silicon carbide semiconductor device according to the embodiment includes a starting substrate 1 (n ++On the front surface (main surface) 1a of a semiconductor substrate (shown as "substrate"), one or more n-type epitaxial layers 40 (n + epi, n +++ epi) and n which becomes the drift layer 2 - type epitaxial layer 40 (n - The SiC substrates 10 and 20 (FIGS. 1 and 2: epitaxial wafers) are used, which are formed by epitaxially growing a SiC substrate 10 and a SiC substrate 20 (FIGS. 1 and 2: epitaxial wafers) in this order.

[0058] The starting substrate 1 is a bulk substrate made of a single crystal of, for example, 4H-SiC (four-layer hexagonal silicon carbide). The front surface 1a of the starting substrate 1 is, for example, a (0001) plane, a so-called Si plane, having a predetermined off-angle in the <11-20> direction. Although not particularly limited, the off-angle of the front surface 1a of the starting substrate 1 is, for example, about 4°±0.5°. The conductivity type of the starting substrate 1 can be set appropriately. For example, when the silicon carbide semiconductor device according to the embodiment is a MOSFET or a pin (p-intrinsic-n) diode, the starting substrate 1 is an n-type substrate having a higher impurity concentration than the buffer layers 11 and 21. ++ When the silicon carbide semiconductor device according to the embodiment is an IGBT, the starting substrate 1 is a p ++ It is a type.

[0059] The starting substrate 1 is a SiC starting wafer sliced ​​from a SiC ingot produced by a typical sublimation method. Sublimation is a method in which a SiC raw material is heated to, for example, approximately 2200°C to 2500°C to sublimate it, and the resulting gas species is recrystallized into a seed crystal controlled at a low temperature. Inside the starting substrate 1, a basal plane dislocation (BPD) 30, which is a perfect dislocation, exists on the basal plane of the starting substrate 1 having a predetermined off-angle, and is decomposed into two parallel Shockley partial dislocations Si(g) and C(g). Between the two Shockley partial dislocations Si(g) and C(g), a Shockley stacking fault (SF: the hatched portion of the initial starting substrate 1 in FIG. 6 ) 32 exists.

[0060] The distance between two Shockley partial dislocations Si(g), C(g) of the BPD 30 in the starting substrate 1 fabricated by a general sublimation method is determined by the stress F epi The gap is narrow enough that the BPDs 30 can be converted into TEDs 31 at the interface 12 between the starting substrate 1 and the buffer layer 11 when the starting substrate 1 is subjected to a thermal shock (see FIG. 6 described later). Specifically, the distance between two Shockley partial dislocations Si(g), C(g) of the BPDs 30 in the starting substrate 1 at the initial stage (before being heated by the annealing process for raising the temperature inside the epitaxial growth furnace) is, for example, about 40 nm. The density of the BPDs 30 in the starting substrate 1 is, for example, 100 / cm. 2 Approximately ~3000 / cm 2 That's about it.

[0061] Within the starting substrate 1, point defects 42 (indicated by x marks in FIGS. 1 and 2 and in FIGS. 4, 5, and 7 described below) are introduced into a surface region 41 extending from the front surface 1 a of the starting substrate 1 to a predetermined depth (hereinafter referred to as a crystal defect introduction region) at a higher density than in the remaining region (region excluding the crystal defect introduction region 41) of the starting substrate 1. The crystal defect introduction region 41 may be provided in a portion of the starting substrate 1 where the distance between two Shockley partial dislocations Si(g), C(g) of BPDs 30 is likely to increase during (pretreatment), and specifically, it is preferable that the crystal defect introduction region 41 extend to a depth of at least about 0.5 μm from the front surface 1 a of the starting substrate 1.

[0062] The point defects 42 are carbon vacancy defects (Z ) that are generated by bombarding the front surface 1 a of the starting substrate 1 with atoms, molecules, electron beams, or particle beams to destroy the SiC crystal structure of the starting substrate 1. 1 / 2 Specifically, the point defects 42 are formed by protons (H + The point defects 42 are introduced by ion implantation, hydrogen (H) ion implantation, electron beam irradiation, particle beam irradiation, or nitrogen (N) ion implantation. The point defects 42 function as a lifetime killer for minority carriers (holes). The crystal defect-introduced region 41 may contain hydrogen or nitrogen together with the point defects 42 at a higher density than the remaining region of the starting substrate 1.

[0063] When point defects 42 are introduced by proton irradiation or hydrogen ion implantation, the crystal defect induced region 41 contains hydrogen atoms (H) or hydrogen molecules (H) that function as minority carrier lifetime killers, together with the point defects 42, in at least the surface region of the front surface 1a of the starting substrate 1. When point defects 42 are introduced by nitrogen ion implantation, the crystal defect induced region 41 contains nitrogen atoms that function as minority carrier lifetime killers, together with the point defects 42, in at least the surface region of the front surface 1a of the starting substrate 1. Because the entire starting substrate 1 is irradiated with electron beam irradiation or particle beam irradiation, the entire starting substrate 1 becomes the crystal defect induced region 41 (see FIG. 5 described later).

[0064] In a method such as ion implantation, in which point defects 42 are introduced only to a certain depth from the front surface 1a of the starting substrate 1, the manufacturing cost increases as the point defects 42 are introduced to a greater depth and at a higher density. 18 / cm 3 2 x 10 or more 19 / cm 3 When the crystal defect introduction region 41 having a nitrogen concentration of about 1000 kJ / cm or less is formed, both point defects 42 and nitrogen are introduced into the crystal defect introduction region 41. Therefore, both the energy level formed by nitrogen and the point defects 42 function as minority carrier lifetime killers. On the other hand, when the point defects 42 are introduced by electron beam irradiation, the point defects 42 can be introduced into the entire starting substrate 1 with a uniform density distribution in the depth direction without increasing the manufacturing cost.

[0065] The crystal defect introduction region 41 may be provided only in the portion of the SiC substrate 10, 20 facing the bipolar operating portion in the depth direction. The bipolar operating portion is a portion where a pn junction electrically connected to a surface electrode such as a source electrode 75 is formed. The crystal defect introduction region 41 has the function of making it difficult for the Si core partial dislocations Si(g) of the BPD 30 in the starting substrate 1 to move. The density of point defects 42 in the crystal defect introduction region 41 is, for example, 1×10 11 / cm 3 3x10 or more 18 / cm 3The density of the point defects 42 in the crystal defect introduction region 41 is preferably highest at the interface 12 between the starting substrate 1 and the buffer layer 11. The density of the point defects 42 in the crystal defect introduction region 41 may be uniform in the depth direction.

[0066] Before epitaxial growth of the epitaxial layer 40 that will become the buffer layers 11, 21 and the drift layer 2, etc., point defects 42 are introduced 51, 52 into the starting substrate 1 (see FIGS. 3 to 6 described later). Therefore, the point defects 42 are introduced only into the starting substrate 1, and not into the epitaxial layer 40. By not introducing the point defects 42 into the drift layer 2, it is possible to prevent the point defects 42 from adversely affecting the electrical characteristics of the silicon carbide semiconductor device. The starting substrate 1 contains more point defects 42 than the epitaxial layer 40. The starting substrate 1 may contain more impurities that act as minority carrier lifetime killers than the epitaxial layer 40.

[0067] The buffer layers 11 and 21 and the drift layer 2 are epitaxially grown successively in the same epitaxial growth furnace while appropriately controlling the impurity concentration and thickness. This prevents degradation of the film quality at the interface between the buffer layer 11 and the drift layer 2. The buffer layer 11 is n - n-type impurity concentration is higher than that of the n-type drift layer 2 + The buffer layer 11 is provided between the drift layer 2 and the starting substrate 1 in contact with them, and is in contact with the crystal defect introduced region 41 on the front surface 1 a of the starting substrate 1. The buffer layer 11 is a dislocation conversion layer that converts BPDs 30 in the starting substrate 1 into threading edge dislocations (TEDs) 31 during the epitaxial growth of the buffer layer 11 itself.

[0068] By epitaxially growing the buffer layer 11 on the front surface 1a of the starting substrate 1, it is possible to suppress the propagation of BPDs 30 in the starting substrate 1 to the epitaxial layer. A buffer layer 21 may be provided between the buffer layer 11 and the drift layer 2 (FIG. 2). In this case, the buffer layer 21 contacts the drift layer 2. The buffer layer 21 has an n + The n-type impurity concentration is higher than that of the n-type buffer layer 11. +++The buffer layer 21 has a function of suppressing the expansion of SF 32 from BPD 30 in the starting substrate 1 by eliminating holes supplied from the drift layer 2 through recombination during bipolar operation of the silicon carbide semiconductor device.

[0069] An element structure of a bipolar device such as an IGBT, or an element structure that parasitically operates as a bipolar device such as a MOSFET or a pin diode, is formed inside the drift layer 2, or on the surface of the drift layer 2 opposite to the starting substrate 1, or both. When the silicon carbide semiconductor device is an IGBT, the buffer layer 11 is formed as a p ++ The n-type buffer layer 21 is made to have a lower n-type impurity content than the starting substrate 1. + The buffer layer 11 and the p ++ p-type starting substrate 1 having a higher p-type impurity than the starting substrate 1 +++ An example of the structure of the silicon carbide semiconductor device according to the embodiment will be described later (see FIG. 7).

[0070] A method for manufacturing a silicon carbide semiconductor device according to an embodiment and a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Figures 3 and 4 are cross-sectional views schematically showing a state during the manufacturing of a silicon carbide substrate used in a silicon carbide semiconductor device according to an embodiment. Figure 5 is a cross-sectional view schematically showing another example of a state during the manufacturing of a silicon carbide substrate used in a silicon carbide semiconductor device according to an embodiment. First, a starting substrate 1 made of SiC as a semiconductor material is prepared (Figure 3). Starting substrate 1 contains BPDs 30 on a basal plane of starting substrate 1 having a predetermined off-angle.

[0071] Next, point defects 42 are introduced into the front surface 1a of the starting substrate 1 by proton irradiation, hydrogen ion implantation, electron beam irradiation, particle beam irradiation, or nitrogen ion implantation, thereby forming a crystal defect introduction region 41 inside the starting substrate 1. When point defects 42 are introduced 51 by proton irradiation, hydrogen ion implantation, or nitrogen ion implantation, a crystal defect introduction region 41 is formed at a predetermined depth from the front surface 1a of the starting substrate 1 ( FIG. 4 : introduction step). When point defects 42 are introduced 52 by electron beam irradiation or particle beam irradiation, the entire starting substrate 1 becomes a crystal defect introduction region 41 ( FIG. 5 : introduction step).

[0072] Next, the starting substrate 1 is inserted into an epitaxial growth furnace (not shown), and the temperature inside the epitaxial growth furnace is raised to a predetermined epitaxial growth temperature. Then, while the temperature inside the epitaxial growth furnace is maintained near the epitaxial growth temperature, hydrogen etching 53 (see FIG. 6 , described later) is performed to clean the front surface 1 a of the starting substrate 1. Then, while the temperature inside the epitaxial growth furnace is maintained at the epitaxial growth temperature, an epitaxial layer 40 is epitaxially grown on the front surface 1 a of the starting substrate 1 (film formation process).

[0073] Specifically, in the same epitaxial growth furnace, epitaxial layers 40 that will become buffer layer 11 and drift layer 2 are successively epitaxially grown in this order on the front surface 1a of starting substrate 1 while being doped with impurities of a predetermined conductivity type, thereby completing SiC substrate 10 shown in FIG. 1 (first step). Nitrogen (N) can be used as the n-type impurity doped into epitaxial layer 40. Aluminum (Al) can be used as the p-type impurity doped into epitaxial layer 40.

[0074] At this time, the buffer layers 11 and 21 and the epitaxial layer 40 that will become the drift layer 2 are epitaxially grown in this order in the same epitaxial growth furnace, thereby completing the SiC base 20 shown in Fig. 2 (Step 1). The temperature profile in the epitaxial growth furnace can be the general temperature profile shown in Fig. 12. Thereafter, a predetermined element structure of a silicon carbide semiconductor device is formed inside the epitaxial layer 40 (either inside the drift layer 2, on the surface of the drift layer 2, or both) by a general method (Step 2).

[0075] The SiC substrates 10 and 20 may include, as the epitaxial layer 40, a SiC layer constituting the element structure of the silicon carbide semiconductor device, which is epitaxially grown continuously on the drift layer 2 in the same epitaxial growth furnace, or epitaxially grown on the surface of the drift layer 2 with an appropriate step of forming a diffusion region of a predetermined conductivity type by ion implantation sandwiched therebetween. Then, by forming surface electrodes on the first and second main surfaces (front and back surfaces) of the SiC substrates 10 and 20, respectively, by a general method (third and fourth steps), the silicon carbide semiconductor device according to the embodiment is completed.

[0076] When producing the SiC substrates 10 and 20, the efficiency with which BPDs 30 in the starting substrate 1 are converted to TEDs 31 (BPD-TED conversion efficiency) is stabilized by forming a crystal defect introduction region 41 inside the starting substrate 1 before epitaxial growth of the epitaxial layer 40. The reason for this is as follows. Fig. 6 is an explanatory diagram that schematically shows the principle of BPD-TED conversion during production of a silicon carbide substrate according to an embodiment. An example will be described in which the interior of an epitaxial growth furnace is heated according to a general temperature profile shown in Fig. 12.

[0077] 6 shows a cross-sectional view of the starting substrate 1 before (initial stage) insertion into the epitaxial growth furnace, a cross-sectional view of the starting substrate 1 during temperature rise and hydrogen etching before epitaxial growth, and a cross-sectional view of the starting substrate 1 during epitaxial growth (epi-growth). In FIG. 6, the [11-20] direction is the step-flow growth direction of the epitaxial layer 40 epitaxially grown on the front surface 1a of the starting substrate 1, and the [1-100] direction is the direction parallel to the front surface 1a of the starting substrate 1. ex corresponds to the annealing time in FIG.

[0078] As described above, when epitaxially growing epitaxial layer 40 on front surface 1a of starting substrate 1, the temperature inside an epitaxial growth furnace containing starting substrate 1 is increased or decreased according to the temperature profile shown in Fig. 12. Specifically, after starting substrate 1 is first inserted into an epitaxial growth furnace (not shown), the temperature inside the epitaxial growth furnace is increased to, for example, 900°C in a predetermined time T1 (first-stage heating), maintained at that temperature for a predetermined time T2, and then further increased to a temperature close to the epitaxial growth temperature in a predetermined time T3 (second-stage heating).

[0079] With the temperature inside the epitaxial growth furnace maintained near the epitaxial growth temperature, the front surface 1 a of the starting substrate 1 is cleaned by hydrogen etching 53 for a predetermined time T. Then, with the temperature inside the epitaxial growth furnace maintained at the epitaxial growth temperature, epitaxial layers 40 that will become buffer layers 11 and 21 and drift layer 2 (see FIGS. 1 and 2) are epitaxially grown continuously on the front surface 1 a of the starting substrate 1 for a predetermined time T with the impurity concentrations and thicknesses appropriately controlled, and after the epitaxial growth, the temperature inside the epitaxial growth furnace is lowered to room temperature.

[0080] The starting substrate 1 has an internal stress F due to a crystal defect introduction region 41 formed in advance inside the starting substrate 1. defect During the temperature rise in the epitaxial growth furnace (temperature rise in FIG. 6), the Si core partial dislocations Si(g) of the BPDs 30 in the starting substrate 1 are subjected to thermal stress F in the [1-100] direction perpendicular to the step-flow growth direction of the epitaxial layer 40. thermal However, the crystal defect introduction region 41 reduces the thermal stress F thermal Thermal stress F in the direction pushing back thermal The internal stress F is equal to defect This makes it difficult to move around.

[0081] This makes it difficult for the distance between the two Shockley partial dislocations Si(g), C(g) of BPD 30 to widen when the temperature in the epitaxial growth furnace is increased, and it is possible to suppress the expansion (area increase) of SF 32. During hydrogen etching 53, thermal stress F thermalHowever, the internal stress F due to the crystal defect introduction region 41 is not increased as in the case of temperature rise in the epitaxial growth furnace. defect and thermal stress F thermal Since these are almost balanced, the expansion of SF32 is suppressed.

[0082] During epitaxial growth of the epitaxial layer 40 that will become the buffer layer 11, a thermal stress F is applied to the Si core partial dislocation Si(g) in the vicinity of the front surface 1a of the starting substrate 1. thermal The buffer layer 11 exerts a stress F epi This reduces the distance between the two Shockley partial dislocations Si(g) and C(g) to a certain value or less, which is necessary for the BPD-TED conversion. Therefore, the BPD 30 is converted into the TED 31 at the interface 12 between the starting substrate 1 and the buffer layer 11 (see FIGS. 1 and 2).

[0083] Among the plurality of BPDs 30 in the starting substrate 1, the thermal stress F thermal The BPDs 30 having a Burgers vector parallel to the step-flow growth direction of the epitaxial layer 40, which are adversely affected by the crystal defect introduction region 41, can be stably converted into the TEDs 31. The BPDs 30 (not shown) having a Burgers vector not parallel to the step-flow growth direction of the epitaxial layer 40 are stably converted into the TEDs 31. defect Regardless of the presence or absence of , it is converted into TED 31 at the interface 12 between the starting substrate 1 and the buffer layer 11 .

[0084] TEDs 31 converted at the interface 12 between the starting substrate 1 and the buffer layer 11 propagate through the epitaxial layer 40 (the buffer layers 11 and 21 and the drift layer 2). This makes it possible to suppress the occurrence of abnormal BPDs 130 (see FIGS. 9 and 10 ) as seen in the SiC substrates 110 and 120 of the reference example, thereby improving the BPD-TED conversion efficiency. TEDs 31 do not generate SFs 32 even when recombination energy is supplied. This makes it possible to suppress bipolar degradation of the silicon carbide semiconductor device.

[0085] The structure of a silicon carbide semiconductor device according to an embodiment will be described using a trench gate MOSFET as an example. FIG. 7 is a cross-sectional view showing an example of the structure of a silicon carbide semiconductor device according to an embodiment. The silicon carbide semiconductor device 60 shown in FIG. 7 is a vertical MOSFET having a trench gate structure (device structure) on the front surface side of a SiC substrate 80. The SiC substrate 80 is an n-channel MOSFET using SiC as a semiconductor material. ++ On the front surface of the starting substrate 81, + Mold buffer area 62,n - The epitaxial layers 82 to 84 that will become the p-type drift region 63 and the p-type base region 64 are epitaxially grown in this order.

[0086] The SiC substrate 80 corresponds to the SiC substrate 10 in Fig. 1. The SiC substrate 80 has a first main surface on the p-type epitaxial layer 84 side as the front surface, and an n-type epitaxial layer 84 as the ++ The second main surface (n ++ The back surface of the starting substrate 81 is referred to as the back surface. ++ The starting substrate 81 is, for example, a nitrogen-doped n ++ The substrate is a bulk SiC single crystal substrate of the type n, which corresponds to the starting substrate 1 in FIG. ++ The starting substrate 81 is ++ The n-type drain region 61. ++ The starting substrate 81 has a crystal defect introduction region 41 formed by introducing point defects 42 (see FIG. 4) 51 therein. ++ The entire starting mold substrate 81 may be used as the crystal defect introduction region 41 (see FIG. 5).

[0087] Epitaxial layers 82-84 correspond to epitaxial layer 40 in FIG. + type epitaxial layer 82 and n - The n-type epitaxial layer 83 corresponds to the buffer layer 11 and the drift layer 2 in FIG. + type epitaxial layer 82 and n - The n-type epitaxial layer 83 is doped with, for example, nitrogen. + The n-type epitaxial layer 82 + This is the type buffer area 62. + The type buffer area 62 is ++type drain region 61 and n - It contacts the mold drift region 63. - The p type epitaxial layer 83 is + The portion excluding the n-type regions 71 and 72 and the n-type current diffusion region 73 is n - This is the type drift region 63 .

[0088] n + Type buffer area 62 and n - Between the n-type drift region 63, +++ n which becomes a type buffer area (not shown) +++ A n-type epitaxial layer may be provided. +++ n, which will be the type buffer area +++ The epitaxial layer corresponds to the buffer layer 21 in FIG. +++ When a p-type buffer region is provided, the SiC substrate 80 corresponds to the SiC substrate 20 in Fig. 2. The p-type epitaxial layer 84 is doped with p-type impurities, for example, aluminum. + type source region 65, p ++ The portion excluding the contact region 66 is a p-type base region 64 .

[0089] The trench gate structure includes a p-type base region 64, an n + type source region 65, p ++ The p-type base region 64 is formed by a contact region 66, a trench 67, a gate insulating film 68, and a gate electrode 69. The p-type base region 64 is connected to the front surface of the SiC substrate 80 and the n-type - The n-type drift region 63 is provided between the n-type drift region 63 and the n-type drift region 63. + type source region 65 and p ++ The n-type contact region 66 is a diffusion region formed in the p-type epitaxial layer 84 by ion implantation. + type source region 65 and p ++ The contact regions 66 are selectively provided between the front surface of the SiC substrate 80 and the p-type base region 64 in contact with the p-type base region 64 .

[0090] n + type source region 65 and p ++The contact region 66 contacts the source electrode 75 on the front surface of the SiC substrate 80. ++ The p-type contact region 66 may not be provided. ++ Instead of the p-type contact region 66, the p-type base region 64 reaches the front surface of the SiC substrate 80. The trench 67 extends from the front surface of the SiC substrate 80 to the n-type + The current flows through the p-type source region 65 and the p-type base region 64 to the inside of an n-type current diffusion region 73 (or through the n-type current diffusion region 73) which will be described later. + The trench 67 terminates at the inside of the mold region 71. A gate electrode 69 is provided inside the trench 67 with a gate insulating film 68 interposed therebetween.

[0091] p-type base region 64 and n - Between the trench 67 and the n-type drift region 63, + At a deep position on the side of the p-type drain region 61 + A p-type region 71 and an n-type current diffusion region 73 are selectively provided. + The p-type regions 71 are provided separately in a portion facing the bottom surface of the trench 67 and between adjacent trenches 67, and are connected in, for example, a depth direction of the paper (not shown). + Between the mold region 71, p + A mold area 72 is provided. + The n-type regions 71 and 72 and the n-type current diffusion region 73 are - The diffusion region is formed in the epitaxial layer 83 by ion implantation.

[0092] All p + The n-type regions 71 and 72 are fixed to the potential of the source electrode 75, and have the function of depleting when the MOSFET is turned off (or depleting the n-type current diffusion region 73, or both), thereby mitigating the electric field applied to the gate insulating film 68. + The p-type region 71 is provided apart from the p-type base region 64. + p type drain region 61 side) +The type region 71 may be in contact with the gate insulating film 68 at the bottom of the trench 67, or may be spaced apart from the trench 67. + The mold regions 71 and 72 are provided apart from the trench 67 .

[0093] The n-type current diffusion region 73 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. + adjacent to the mold regions 71, 72 and the trench 67, and + The bottom surface (n-type source region 65 side surface) contacts the p-type base region 64, and the bottom surface (n-type source region 65 side surface) contacts the p-type base region 64. + the surface on the side of the n-type drain region 61 - The n-type current diffusion region 73 may not be provided. In this case, the n-type current diffusion region 73 may be replaced by an n - The p-type drift regions 63 are adjacent to each other. + The insulating layer 71 extends between the p-type regions 71 to the p-type base region 64 , and also extends in a direction parallel to the front surface of the SiC substrate 80 to the trench 67 .

[0094] The interlayer insulating film 74 is provided on almost the entire front surface of the SiC substrate 80, and covers the gate electrode 69. The source electrode (first electrode) 75 is in ohmic contact with the SiC substrate 80 inside the contact hole of the interlayer insulating film 74, and + type source region 65, p ++ The drain electrode (second electrode) 76 is electrically connected to the back surface (n ++ The drain electrode 76 is in ohmic contact with the back surface of the SiC substrate 80 and is provided on the entire surface of the back surface of the SiC substrate 81. + type drain region 61 (n ++ The mold is electrically connected to the starting substrate 81.

[0095] In the silicon carbide semiconductor device (MOSFET) according to the above-described embodiment, in addition to a mode (synchronous rectification mode) in which a current flows through a channel (an n-type inversion layer formed along the sidewall of the trench 67 in the p-type base region 64), there is also a mode (bipolar mode) in which a current I flows forward through a body diode. ++ the p-type contact region 66, the p-type base region 64 and the p + n-type regions 71 and 72, and n-type current diffusion regions 73 and - type drift region 63, n + The mold buffer area 62 and n + The pn junction between the first and second pn regions 61 and 62 is a parasitic pn junction diode.

[0096] During bipolar operation (bipolar mode) of a silicon carbide semiconductor device, n - The BPD 30 in the n-type drift region 63 - When a certain level of recombination energy is supplied to the silicon carbide semiconductor device 60, the recombination energy is increased by the recombination of carriers (electrons and holes) in the silicon carbide semiconductor drift region 63, and the recombination energy expands while forming a Shockley type SF. As a result, the on-state voltage increases over time, which causes an increase in the forward voltage of the silicon carbide semiconductor device (bipolar degradation). The silicon carbide semiconductor device according to this embodiment has a n-type MOSFET with high BPD-TED conversion efficiency due to the crystal defect introduction region 41 being formed in advance. ++ It is fabricated using a mold starting substrate 81 .

[0097] n ++ By forming the crystal defect introduction region 41 inside the starting substrate 81, n + Mold buffer area 62(n + During epitaxial growth of the n-type epitaxial layer 82, ++ The BPD 30 in the mold starting substrate 81 is n ++ Starting substrate 81 and n + At the interface with the n-type buffer region 62, the n-type buffer region 62 can be converted into the n-type TED 31 with high efficiency and stability (see FIG. 6). - TED 31 propagates in the n-type drift region 63, ++The BPDs 30 in the starting mold substrate 81 are unlikely to be inherited. The TEDs 31 do not generate SF 32 even when supplied with recombination energy. This makes it possible to suppress bipolar degradation of the silicon carbide semiconductor device.

[0098] When the silicon carbide semiconductor device according to the embodiment shown in FIG. 7 is applied to an IGBT, n ++ Instead of the starting substrate 81, a p ++ In this case, n + n which becomes the type buffer area 62 + type epitaxial layer 82 and n +++ n, which will be the type buffer area +++ When the silicon carbide semiconductor device according to the above-described embodiment is applied to a pin diode, the p-type epitaxial layer 84 may be used as a p-type anode region without providing a trench gate structure.

[0099] As described above, according to the embodiment, a crystal defect-introduced region is formed by introducing point defects at a high density into at least the surface region of the front surface of the starting substrate before epitaxial growth of an epitaxial layer including a buffer layer (a transition conversion layer that converts BPDs in the starting substrate to TEDs during the epitaxial growth of the buffer layer itself). The crystal defect-introduced region makes it difficult for Si core partial dislocations of BPDs to move near the front surface of the starting substrate. Therefore, even if the temperature of the front surface of the starting substrate, the temperature distribution within the starting substrate, and the heating time of the starting substrate vary and become unstable under the temperature environment during annealing treatment (a pretreatment in which the starting substrate is heated with a temperature profile with a high temperature gradient before epitaxial growth) to increase the temperature inside the epitaxial growth furnace, the distance between the two Shockley partial dislocations that make up the BPDs in the starting substrate is unlikely to increase.

[0100] Since the distance between two Shockley partial dislocations of BPDs in the starting substrate remains almost unchanged even after the pretreatment, stress from the buffer layer during the subsequent epitaxial growth of the buffer layer can be applied, reducing the distance between two Shockley partial dislocations of BPDs in the starting substrate to a certain level or less. This allows BPDs in the starting substrate to be stably and efficiently converted to TEDs at the interface between the starting substrate and the buffer layer, making them less likely to propagate to the buffer layer. In other words, the crystal defect-introduced region within the starting substrate stabilizes the BPD-TED conversion efficiency, suppressing the propagation of BPDs in the starting substrate and reducing the number of BPDs in the drift layer. Therefore, the increase in on-state voltage over time can be suppressed, and the increase in forward voltage (bipolar degradation) of the silicon carbide semiconductor device can be suppressed.

[0101] Furthermore, according to the embodiment, the BPD-TED conversion efficiency can be improved regardless of the temperature profile during epitaxial growth, and no setting changes or special control mechanisms are required to control the temperature distribution within the starting substrate surface during epitaxial growth, which makes it possible to suppress increases in manufacturing costs.

[0102] In the above, the present disclosure is not limited to the above-described embodiment, and various modifications are possible within the scope of the present disclosure. In the above-described embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type.

[0103] As described above, the silicon carbide substrate, method for manufacturing a silicon carbide substrate, silicon carbide semiconductor device, and method for manufacturing a silicon carbide semiconductor device according to the present disclosure are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and are particularly suitable for bipolar devices and silicon carbide semiconductor devices having an element structure that parasitically operates in a bipolar manner.

[0104] 1, 81, 101 Starting substrate 1a, 101a Front surface of starting substrate 2, 102 Drift layer 10, 20, 80, 100, 110, 120 SiC substrate 11, 21, 111, 121 Buffer layer 12, 112 Interface between starting substrate and buffer layer 40, 82 to 84, 140 Epitaxial layer 41 Crystal defect introduced region 42 Point defect 60 Silicon carbide semiconductor device 61 n ++ Type drain region 62 n + Type buffer area 63 n - n-type drift region 64 p-type base region 65 + Type source region 66p ++ Type contact region 67 Trench 68 Gate insulating film 69 Gate electrode 71, 72 p + Type region 73 n-type current diffusion region 74 interlayer insulating film 75 source electrode 76 drain electrode F defect , F epi , F thermal Stress Si(g), C(g) Shockley partial dislocation

Claims

1. a semiconductor substrate made of silicon carbide; an epitaxial layer provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate; a crystal defect introduction region that includes a relatively large number of point defects and is provided inside the semiconductor substrate in contact with the epitaxial layer and at a predetermined depth from the front surface of the semiconductor substrate; Equipped with The silicon carbide substrate, wherein the point defects are atomic vacancies caused by electron beam irradiation of the semiconductor substrate.

2. 2. The silicon carbide substrate according to claim 1, wherein the semiconductor substrate contains more point defects than the epitaxial layer.

3. 2. The silicon carbide substrate according to claim 1, wherein the crystal defect introduction region is provided only in a surface region of the front surface of the semiconductor substrate.

4. 4. The silicon carbide substrate according to claim 3, wherein the semiconductor substrate contains a relatively large amount of hydrogen or nitrogen in the crystal defect introduction region.

5. a semiconductor substrate made of silicon carbide; an epitaxial layer provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate; a crystal defect introduction region that includes a relatively large number of point defects and is provided inside the semiconductor substrate in contact with the epitaxial layer and at a predetermined depth from the front surface of the semiconductor substrate; a first main surface formed on the outermost surface on the epitaxial layer side; a silicon carbide substrate having a second main surface formed by the back surface of the semiconductor substrate; an element structure provided on the first main surface side of the silicon carbide substrate; a first electrode provided on the first main surface and electrically connected to the element structure; a second electrode provided on the second main surface; a pn junction provided inside the silicon carbide substrate and operating bipolarly between the first electrode and the second electrode; Equipped with 2. A silicon carbide semiconductor device, wherein the point defects are atomic vacancies caused by electron beam irradiation of the semiconductor substrate.

6. an introduction step of introducing atomic vacancies, which are point defects, from the front surface of a semiconductor substrate made of silicon carbide to a predetermined depth by irradiating the front surface of the semiconductor substrate with an electron beam to form a crystal defect introduction region; a film formation step of epitaxially growing an epitaxial layer having an impurity concentration lower than that of the semiconductor substrate on the front surface of the semiconductor substrate in contact with the crystal defect introduction region; 2. A method for manufacturing a silicon carbide substrate, comprising:

7. 7. The method for producing a silicon carbide substrate according to claim 6, wherein in the film formation step, a temperature inside the epitaxial growth furnace is raised to an epitaxial growth temperature with the semiconductor substrate inserted in the epitaxial growth furnace, and the epitaxial layer is epitaxially grown at the epitaxial growth temperature.

8. A first step of preparing a silicon carbide substrate made of silicon carbide; a second step of forming an element structure on a first main surface side of the silicon carbide substrate; a third step of forming a first electrode on the first main surface, the first electrode being electrically connected to the element structure; a fourth step of forming a second electrode on a second main surface of the silicon carbide substrate; Including, before the third step, a pn junction that operates in bipolar fashion is formed between the first electrode and the second electrode inside the silicon carbide substrate; In the first step, an introduction step of introducing atomic vacancies, which are point defects, from the front surface of a semiconductor substrate made of silicon carbide to a predetermined depth by irradiating the front surface of the semiconductor substrate with an electron beam to form a crystal defect introduction region; and a film formation step of epitaxially growing an epitaxial layer having an impurity concentration lower than that of the semiconductor substrate on the front surface of the semiconductor substrate in contact with the crystal defect introduction region, thereby fabricating the silicon carbide base having an outermost surface on the epitaxial layer side as the first main surface and a back surface of the semiconductor substrate as the second main surface.