Semiconductor device

Abstract

This semiconductor device is provided with a transistor part and a diode part. The semiconductor device is provided with: a drift region of a first conductivity type provided on a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction on a front surface side of the semiconductor substrate; and a collector region of a second conductivity type provided below the drift region. The transistor part may include: a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type having a doping concentration higher than that of the drift region; a first contact region of the second conductivity type having a doping concentration higher than that of the base region; a plurality of trench bottom regions of the second conductivity type provided repeatedly in the trench extension direction below the base region; and a plurality of trench bottomless regions provided repeatedly in the trench extension direction and sandwiched between the plurality of trench bottom regions. The diode part may have an anode region of the second conductivity type provided above the drift region and a rear surface-side region provided below the drift region. The rear surface-side region may include a first conductivity type part of the first conductivity type and a second conductivity type part of the second conductivity type. The first conductivity type part and the second conductivity type part may be provided in a manner so as to form, as seen from a top view, a repetitive structure in which a second conductivity type formation region in which the second conductivity type part is formed and a second conductivity type non-formation region in which the second conductivity type part is not formed are alternately and repeatedly arranged in a predetermined direction. As seen from the top view, the shortest distance from an end of each of the plurality of trench bottomless regions to the second conductivity type non-formation region may be 85-115% of a predetermined reference value.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Patent Document 1 describes that "a plurality of doping regions (e.g., implantation regions) 1059 of a second conductivity type (complementary to the first conductivity type) are created below the bottoms of the exposed trenches 14, 15, and 16." Patent Document 2 describes providing a "narrow FWD region 19a" and a "wide FWD region 19b." [Prior art documents] [Patent documents] [Patent document 1] JP 2019-110288 A [Patent document 2] JP 5637175 A General disclosure

[0003] (Problem to be Solved) It is desirable to make the electron current uniform in the initial stage of operation of a semiconductor device.

[0004] A first aspect of the present invention provides a semiconductor device including a transistor portion and a diode portion, the semiconductor device including a first conductivity type drift region provided in a semiconductor substrate, a plurality of trench portions extending on a front surface side of the semiconductor substrate in a predetermined trench extension direction, and a second conductivity type collector region provided below the drift region. The transistor portion may include a second conductivity type base region provided above the drift region, an emitter region of the first conductivity type having a doping concentration higher than that of the drift region, a first conductivity type contact region having a doping concentration higher than that of the base region, a plurality of second conductivity type trench bottom regions repeatedly provided below the base region in the trench extension direction, and a plurality of trench bottomless regions repeatedly provided in the trench extension direction and sandwiched between the plurality of trench bottom regions. The diode portion may include a second conductivity type anode region provided above the drift region and a back side region provided below the drift region. The back surface-side region may include a first-conductivity-type portion of a first conductivity type and a second-conductivity-type portion of a second conductivity type. The first-conductivity-type portion and the second-conductivity-type portion may be provided to form a repeating structure in which, in a top view, second-conductivity-type-forming regions in which the second-conductivity-type portions are formed and second-conductivity-type-non-forming regions in which the second-conductivity-type portions are not formed are alternately and repeatedly arranged in a predetermined direction. In a top view, the shortest distance from each end of the plurality of trench bottomless regions to the second-conductivity-type-non-forming region may be 85% or more and 115% or less of a predetermined reference value.

[0005] In the semiconductor device, the second-conductivity-type non-forming regions and the second-conductivity-type forming regions may extend in the trench extension direction in a top view and be arranged alternately in the trench arrangement direction of the plurality of trench portions.

[0006] In any of the above semiconductor devices, the second-conductivity-type non-forming regions and the second-conductivity-type forming regions may extend in a trench arrangement direction of the plurality of trench portions in a top view and be arranged alternately in the trench extension direction.

[0007] In any of the above semiconductor devices, the area of ​​the second conductivity type non-forming region may be 30% or more and 70% or less of the area of ​​the back surface side region when viewed from above.

[0008] In any of the semiconductor devices described above, the back surface-side region may have a plurality of the second-conductivity-type non-forming regions, and each of the plurality of trench bottomless regions may face one of the plurality of second-conductivity-type non-forming regions in a trench arrangement direction of the plurality of trench portions.

[0009] In any of the semiconductor devices described above, the back surface-side region may have a plurality of the second-conductivity-type non-forming regions, and each of the plurality of trench bottomless regions may face two or more of the plurality of second-conductivity-type non-forming regions in a trench arrangement direction of the plurality of trench portions.

[0010] In any of the semiconductor devices described above, the back surface side region may have a plurality of the second-conductivity-type forming regions, and each of the plurality of trench bottomless regions may face one of the plurality of second-conductivity-type forming regions in a trench arrangement direction of the plurality of trench portions.

[0011] In any of the semiconductor devices described above, the back surface side region may have a plurality of the second-conductivity-type forming regions, and each of the plurality of trench bottomless regions may face two or more of the plurality of second-conductivity-type forming regions in a trench arrangement direction of the plurality of trench portions.

[0012] In any of the above semiconductor devices, the areas of the plurality of trench bottomless regions sandwiched between the plurality of trench bottom regions may be 85% or more and 115% or less of a predetermined reference value, respectively.

[0013] In any of the above semiconductor devices, the transistor section may be adjacent to the diode section and may have a first boundary portion above the drift region where the first contact region is not provided. The diode section may have a second contact region of a second conductivity type having a doping concentration higher than that of the anode region and provided above the drift region, and a second boundary portion adjacent to the transistor section and where the second contact region is not provided. At the second boundary portion, the back surface of the semiconductor substrate may include the first conductivity type portion.

[0014] In any of the above semiconductor devices, the second conductivity type non-forming region and the second conductivity type forming region may be arranged symmetrically with respect to a center line of one of the plurality of trench bottomless regions in the trench extension direction.

[0015] In any of the above semiconductor devices, the second-conductivity-type non-forming regions and the second-conductivity-type forming regions may be alternately arranged at a predetermined back-surface-side repetition period. The plurality of trench bottom regions may be repeatedly arranged at a predetermined trench bottom repetition period. The trench bottom repetition period may be larger than the back-surface-side repetition period.

[0016] In any of the above semiconductor devices, the rear surface side repetition period may be not less than 10 μm and not more than 100 μm.

[0017] In any of the above semiconductor devices, the trench bottom repetition period may be an integer multiple of the back surface side repetition period.

[0018] In any of the above semiconductor devices, the first conductivity type portion may be provided in contact with a rear surface of the semiconductor substrate, and the second conductivity type portion may be provided in contact with the rear surface of the semiconductor substrate and adjacent to the first conductivity type portion.

[0019] In any of the above semiconductor devices, the first conductivity type portion may be provided in contact with a rear surface of the semiconductor substrate, and the second conductivity type portion may be provided above the first conductivity type portion.

[0020] In any of the above semiconductor devices, the depth positions of the lower ends of the plurality of trench bottom regions in the depth direction of the semiconductor substrate may be located closer to the front surface than the depth positions of the trench bottoms of the plurality of trench portions.

[0021] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0022] 1B shows an example of a top view of the semiconductor device 100. 1C shows an enlarged view of an end portion of the active region 110 in the top view of the semiconductor device 100. 1D shows an example of an aa' cross section in FIG. 1B. 1E shows a modified example of the aa' cross section in FIG. 1B. 1F shows a modified example of the aa' cross section in FIG. 1B. 1G shows an example of a top view of the semiconductor device 100. 1H shows a modified example of the ... an example of a top view of a semiconductor device 500 of a comparative example. 1H shows an example of a top view of a semiconductor device 200. 1H shows an example of a top view of the semiconductor device 200.

[0023] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0024] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface, and the other surface is referred to as the lower surface. The directions of "upper," "lower," "front," and "back" are not limited to the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.

[0025] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0026] In this specification, a plane parallel to the top surface of the semiconductor substrate is referred to as the XY plane, and orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. An axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. The depth direction of the semiconductor substrate may be referred to as the Z-axis. In this specification, a view of the semiconductor substrate in the Z-axis direction is referred to as a planar view. In this specification, a direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as a horizontal direction.

[0027] In each embodiment, an example is shown in which the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will be opposite polarities.

[0028] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0029] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0030] In this specification, doping concentration means the concentration of donors or acceptors at thermal equilibrium.

[0031] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type.

[0032] 1A shows an example of a top view of a semiconductor device 100. The semiconductor device 100 is a semiconductor chip including a transistor section 70 and a diode section 80.

[0033] The transistor section 70 includes a transistor such as an insulated gate bipolar transistor (IGBT). The diode section 80 includes a diode such as a free wheel diode (FWD). The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT) that has the transistor section 70 and the diode section 80 on the same chip.

[0034] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. In this example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an active region 110 and a peripheral region 120.

[0035] The transistor section 70 is a region obtained by projecting a collector region 22 (described later) provided on the lower surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The diode section 80 is a region obtained by projecting a back surface side region 82 (described later) provided on the lower surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10.

[0036] The transistor sections 70 and the diode sections 80 may be alternately and periodically arranged in the XY plane. In this example, the transistor sections 70 and the diode sections 80 include a plurality of transistor sections and a plurality of diode sections. A gate metal layer 50 may be provided above the semiconductor substrate 10 in a region between the transistor sections 70 and the diode sections 80.

[0037] In this example, the transistor section 70 and the diode section 80 have trench sections extending in the Y-axis direction. However, the transistor section 70 and the diode section 80 may also have trench sections extending in the X-axis direction.

[0038] The active region 110 has a transistor portion 70 and a diode portion 80. The active region 110 is a region through which a main current flows between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. That is, the active region 110 is a region through which a current flows in the depth direction inside the semiconductor substrate 10, from the upper surface to the lower surface or from the lower surface to the upper surface of the semiconductor substrate 10. In this specification, the transistor portion 70 and the diode portion 80 are referred to as an element portion or an element region, respectively.

[0039] In addition, when viewed from above, the region sandwiched between the two element portions is also defined as the active region 110. In this example, the active region 110 also includes the region sandwiched between the element portions and where the gate metal layer 50 is provided.

[0040] The gate metal layer 50 is formed of a material containing metal. For example, the gate metal layer 50 is formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The gate metal layer 50 is electrically connected to the gate conductive portion of the transistor portion 70 and supplies a gate voltage to the transistor portion 70. The gate metal layer 50 is provided so as to surround the periphery of the active region 110 in a top view. The gate metal layer 50 is electrically connected to a gate pad 130 provided in the peripheral region 120. The gate metal layer 50 may be provided along the peripheral edge of the semiconductor substrate 10. The gate metal layer 50 may have a barrier metal formed of titanium, a titanium compound, or the like below a region formed of aluminum or the like. Furthermore, the gate metal layer 50 may be provided between the transistor portion 70 and the diode portion 80 in a top view.

[0041] The peripheral region 120 is a region between the active region 110 and the peripheral edge of the semiconductor substrate 10 in a top view. The peripheral region 120 is provided to surround the active region 110 in a top view. One or more metal pads may be arranged in the peripheral region 120 to connect the semiconductor device 100 to an external device via wires or the like. The peripheral region 120 may have an edge termination structure. The edge termination structure relieves electric field concentration on the top surface side of the semiconductor substrate 10. For example, the edge termination structure may have a guard ring, a field plate, a resurf structure, or a combination of these structures.

[0042] The gate pad 130 is electrically connected to the gate conductive portion of the transistor section 70 via the gate metal layer 50. The gate pad 130 is set to a gate potential. The gate pad 130 in this example has a rectangular shape when viewed from above.

[0043] 1B shows an example of a top view of the semiconductor device 100. In this example, an enlarged view of region A in FIG. 1A is shown.

[0044] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an anode region 11, an emitter region 12, a base region 14, a first contact region 15, a well region 17, and a second contact region 19 on a front surface 21 of a semiconductor substrate 10. The front surface 21 will be described later. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0045] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the anode region 11, the emitter region 12, the base region 14, the first contact region 15, the well region 17, and the second contact region 19. The gate metal layer 50 is provided above the gate trench portion 40 and the well region 17.

[0046] The emitter electrode 52 is formed of a material containing metal. The emitter electrode 52 may be formed of the same material as the gate metal layer, or may be formed of a different material. The emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, or the like below a region formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0047] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in FIG. 1B. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0048] The contact hole 55 connects the gate metal layer 50 to the gate conductive portion in the transistor portion 70. A plug made of tungsten or the like may be formed inside the contact hole 55.

[0049] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. A plug made of tungsten or the like may be formed inside the contact hole 56.

[0050] The connection portion 25 electrically connects a front surface electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material, such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film, such as an oxide film.

[0051] The gate trench portion 40 is an example of a plurality of trench portions extending in a predetermined trench extension direction on the front surface 21 side of the semiconductor substrate 10. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 of this example may have two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 that connects the two extension portions 41.

[0052] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0053] The dummy trenches 30 are trenches electrically connected to the emitter electrode 52. Similar to the gate trenches 40, the dummy trenches 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). Similar to the gate trenches 40, the dummy trenches 30 in this example may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trenches 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.

[0054] The transistor section 70 of this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has gate trench sections 40 and dummy trench sections 30 in a ratio of 2:3. For example, the transistor section 70 has one extension section 31 between two extension sections 41. The transistor section 70 also has two extension sections 31 adjacent to the gate trench section 40.

[0055] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 1:1 or 2:4. Furthermore, the transistor portion 70 may have a so-called full gate structure in which the dummy trench portions 30 are not provided and the entire portion is made up of gate trench portions 40.

[0056] The well region 17 is a second conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18 described below. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. The well region 17 is, for example, P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0057] In the transistor section 70, the contact holes 54 are formed above the emitter region 12, the base region 14, and the first contact region 15. In addition, in the diode section 80, the contact holes 54 are provided above the anode region 11 and the second contact region 19. In the diode section 80, the contact holes 54 are provided above the base region 14. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction. In this way, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0058] The trench contact portion 27 electrically connects the emitter electrode 52 and the semiconductor substrate 10. The trench contact portion 27 is provided in the contact hole 54. The trench contact portion 27 is provided to extend in the extension direction.

[0059] The first boundary 190 is a region provided in the transistor section 70 and adjacent to the diode section 80. The first boundary 190 may include the base region 14. The first boundary 190 may not include either the emitter region 12 or the first contact region 15. In one example, the trench portion of the first boundary 190 is a dummy trench portion 30. The first boundary 190 in this example is arranged so that both ends in the X-axis direction are dummy trench portions 30.

[0060] The second boundary 290 is a region provided in the diode section 80 and adjacent to the transistor section 70. The second boundary 290 has the anode region 11. The second boundary 290 does not have the second contact region 19. In one example, the trench portion of the second boundary 290 is a dummy trench portion 30. The second boundary 290 in this example is arranged so that both ends in the X-axis direction are dummy trench portions 30.

[0061] Mesa portion 71, mesa portion 81, mesa portion 191, and mesa portion 291 are mesa portions provided adjacent to trench portions in a plane parallel to front surface 21 of semiconductor substrate 10. A mesa portion is a portion of semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from front surface 21 of semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. An extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0062] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a first contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the first contact regions 15 are provided alternately in the extension direction.

[0063] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a second contact region 19 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0064] The mesa portion 191 is provided in the first boundary portion 190. The mesa portion 191 has a base region 14 on the front surface 21 of the semiconductor substrate 10. The mesa portion 191 of this example has the base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0065] The mesa portion 291 is provided in the second boundary portion 290. The mesa portion 291 has an anode region 11 on the front surface 21 of the semiconductor substrate 10. The mesa portion 291 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0066] The anode region 11 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10 in the diode section 80. The anode region 11 is, for example, a P-type. The anode region 11 may be formed with the same dopant as the base region 14, or may be formed with a different dopant. The doping concentration of the anode region 11 may be the same as or different from the doping concentration of the base region 14.

[0067] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10 in the transistor portion 70 and the diode portion 80. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends in the Y-axis direction of the mesa portion 71, the mesa portion 81, the mesa portion 191, and the mesa portion 291. Note that FIG. 1B shows only one end of the base region 14 in the Y-axis direction.

[0068] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71, in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0069] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30. The emitter region 12 does not have to be provided in the mesa portion 81, the mesa portion 191, and the mesa portion 291.

[0070] The first contact region 15 is a region of a second conductivity type having a higher doping concentration than the base region 14. In this example, the first contact region 15 is a P+ type, for example. The first contact region 15 in this example is provided on the front surface 21 of the mesa portion 71.

[0071] The first contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The first contact region 15 may or may not be in contact with the gate trench portion 40. The first contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the first contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The first contact region 15 may also be provided below the contact hole 54.

[0072] The second contact region 19 is a region of a second conductivity type having a higher doping concentration than the anode region 11. In this example, the second contact region 19 is of P type, for example. The doping concentration of the second contact region 19 may be the same as or different from the doping concentration of the first contact region 15. The doping concentration of the second contact region 19 in this example is lower than the doping concentration of the first contact region 15. The second contact region 19 in this example is provided on the front surface 21 of the mesa portion 81.

[0073] The second contact region 19 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 81 to the other. The second contact region 19 may or may not be in contact with the dummy trench portion 30. In this example, the second contact region 19 is in contact with the dummy trench portion 30. The second contact region 19 may also be provided below the contact hole 54.

[0074] 1C is a diagram showing an example of the aa' cross section in FIG. 1B. The aa' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the aa' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10 including an accumulation region 16 and a trench bottom region 65, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0075] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0076] The buffer region 20 is a region of a first conductivity type provided below the drift region 18. In this example, the buffer region 20 is, for example, an N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the back surface side region 82 of the first conductivity type.

[0077] The collector region 22 is provided in the transistor section 70 below the drift region 18. The collector region 22 has the second conductivity type. For example, the collector region 22 is of the P+ type.

[0078] The back side region 82 is provided below the drift region 18 in the diode section 80. In this example, the back side region 82 has a first conductivity type portion 82-1 and a second conductivity type portion 82-2. The boundary between the collector region 22 and the back side region 82 is the boundary between the transistor section 70 and the diode section 80.

[0079] The first conductivity type section 82-1 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the first conductivity type section 82-1 is provided in contact with the rear surface 23 of the semiconductor substrate 10. The doping concentration of the first conductivity type section 82-1 may be higher than the doping concentration of the buffer region 20. The doping concentration of the first conductivity type section 82-1 is 1E15 cm －３ Above, 1E21cm －３ In one example, the first conductivity type portion 82-1 is N+ type.

[0080] The second conductivity type section 82-2 is a region of the second conductivity type having a higher doping concentration than the base region 14. The doping concentration of the second conductivity type section 82-2 is 1E16 cm －３ Above, 1E21cm －３The second conductivity type portion 82-2 may be of the P+ type. In one example, the second conductivity type portion 82-2 is of P+ type. The doping concentration of the second conductivity type portion 82-2 may be the same as or different from the doping concentration of the collector region 22. The second conductivity type portion 82-2 in this example is in contact with the rear surface 23 of the semiconductor substrate 10 and is provided adjacent to the first conductivity type portion 82-1. The second conductivity type portion 82-2 may be in direct contact with the first conductivity type portion 82-1.

[0081] The first conductivity type portion 82-1 may be formed by ion-implanting a P-type dopant and then further implanting an N-type dopant in the ion implantation step for forming the second conductivity type portion 82-2. Conversely, the second conductivity type portion 82-2 may be formed by ion-implanting an N-type dopant and then further implanting a P-type dopant in the ion implantation step for forming the first conductivity type portion 82-1.

[0082] The first conductivity type portion 82-1 and the second conductivity type portion 82-2 are provided to form a repeating structure in which second conductivity type non-forming regions 181 and second conductivity type forming regions 182 are alternately and repeatedly arranged in a predetermined direction. The second conductivity type non-forming regions 181 are regions in which the second conductivity type portions 82-2 are not formed on the back surface 23 side of the semiconductor substrate 10 in top view. The second conductivity type forming regions 182 are regions in which the second conductivity type portions 82-2 are formed on the back surface 23 side of the semiconductor substrate 10 in top view.

[0083] The second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 may be arranged alternately in the trench arrangement direction (e.g., the X-axis direction) or in the trench extension direction (e.g., the Y-axis direction). The second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 may be arranged in a striped pattern in a top view. This allows the forward voltage Vf of the diode section 80 to be reduced. The arrangement of the second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 will be described in detail below.

[0084] At the second boundary 290, the rear surface 23 of the semiconductor substrate 10 has a first conductivity type portion 82-1. By providing the first conductivity type portion 82-1 on the rear surface 23 at the second boundary 290, the current during switching of the semiconductor device 100 is made uniform, and switching efficiency is improved.

[0085] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52 and the gate metal layer 50.

[0086] The accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. In this example, the accumulation region 16 is, for example, an N+ type. The accumulation region 16 is provided in the transistor section 70. However, the accumulation region 16 does not necessarily have to be provided.

[0087] The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0088] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided so as to penetrate the interlayer insulating film 38.

[0089] The trench contact portion 27 has a conductive material filled in the contact hole 54. The trench contact portion 27 is provided between two adjacent trench portions among the plurality of trench portions. In this example, the trench contact portion 27 is provided so as to penetrate from the front surface 21 through the emitter region 12. The trench contact portion 27 may have the same material as the emitter electrode 52.

[0090] The bottom end of the trench contact portion 27 is deeper than the bottom end of the emitter region 12. By providing the trench contact portion 27, the resistance of the base region 14 is reduced, and minority carriers (e.g., holes) can be easily extracted. This improves the breakdown resistance, such as the latch-up resistance, caused by minority carriers.

[0091] The trench contact portion 27 has a bottom surface that is substantially planar. The bottom surface of the trench contact portion 27 may be covered with a plug layer of the second conductivity type or the like. The trench contact portion 27 in this example has a tapered shape with inclined sidewalls. However, the sidewalls of the trench contact portion 27 may be provided substantially perpendicular to the front surface 21.

[0092] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In regions where at least one of the anode region 11, the emitter region 12, the base region 14, the first contact region 15, the accumulation region 16, and the second contact region 19 is provided, each trench portion also penetrates these regions to reach the drift region 18. The trench portion penetrating the doped region is not limited to a case where the trench portion is formed in the order of forming the doped region and then the trench portion. A case where the doped region is formed between the trench portions after the trench portions are formed is also included in the trench portion penetrating the doped region.

[0093] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0094] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0095] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38.

[0096] The trench bottom region 65 is a region of the second conductivity type provided below the base region 14. In this example, the doping concentration of the trench bottom region 65 is higher than the doping concentration of the base region 14. In this example, the trench bottom region 65 is, for example, a P+ type. The doping concentration of the trench bottom region 65 is 1E14 cm －３ Above, 1E18cm －３ By forming the trench bottom region 65, the on-loss Eon of the semiconductor device 100 can be reduced.

[0097] In this example, the trench bottom region 65 is provided so that its upper end does not come into contact with the accumulation region 16. That is, the drift region 18 is formed between the trench bottom region 65 and the accumulation region 16 in the depth direction of the semiconductor substrate 10. The trench bottom region 65 may also be provided so that its upper end comes into contact with the lower end of the accumulation region 16.

[0098] In this example, the trench bottom region 65 extends from the lower end of one of the trench portions to the lower end of the other opposing trench portion in the trench arrangement direction of the multiple trench portions. The trench bottom region 65 may extend from the lower end of one of the multiple trench portions, beyond the lower end of the other opposing trench portion, to the lower end of the trench portion adjacent to the other opposing trench portion. In other words, the trench bottom region 65 may extend beyond the lower ends of two or more multiple trench portions.

[0099] The first lifetime control region 151 is provided in the diode portion 80. This enables the semiconductor device 100 of this example to speed up recovery in the diode portion 80 and reduce switching loss. The first lifetime control region 151 may be provided in the transistor portion 70.

[0100] The first lifetime control region 151 may be formed by implanting impurities from the front surface 21 side, or from the back surface 23 side. The first lifetime control region 151 may be formed by implanting helium ions into the semiconductor substrate 10.

[0101] The second lifetime control region 152 is provided closer to the front surface 21 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the second lifetime control region 152 is provided in the drift region 18. The second lifetime control region 152 is provided in both the transistor section 70 and the diode section 80. The second lifetime control region 152 may be formed by implanting impurities from the front surface 21 side, or may be formed by implanting impurities from the back surface 23 side. The second lifetime control region 152 is provided in the diode section 80, the first boundary section 190, and the second boundary section 290, and may not be provided in a part of the transistor section 70.

[0102] The second lifetime control region 152 may be formed by any method among the methods for forming the first lifetime control region 151. The elements and dose amounts for forming the first lifetime control region 151 and the second lifetime control region 152 may be the same or different.

[0103] Fig. 1D is a diagram showing a modified example of the cross section taken along the line aa' in Fig. 1B. Differences from Fig. 1C will be described using Fig. 1D.

[0104] In this example, the first conductivity type section 82-1 is provided on the rear surface 23 of the semiconductor substrate 10. The first conductivity type section 82-1 may function as the cathode of the diode section 80.

[0105] In this example, the second conductivity type portion 82-2 is provided above the first conductivity type portion 82-1. In this example, the second conductivity type portion 82-2 is provided in contact with the first conductivity type portion 82-1, but this is not limiting. The second conductivity type portion 82-2 may be provided spaced apart from the first conductivity type portion 82-1.

[0106] In this example, the second conductivity type portion 82-2 has the same thickness as the first conductivity type portion 82-1. The second conductivity type portion 82-2 may be thinner than the first conductivity type portion 82-1. The second conductivity type portion 82-2 may have a thickness equal to or less than the length from the upper end of the first conductivity type portion 82-1 to the lower end of the first lifetime control region 151.

[0107] In this example, the second conductivity type portion 82-2 is provided closer to the back surface 23 of the semiconductor substrate 10 than the first lifetime control region 151. The second conductivity type portion 82-2 may be provided closer to the front surface 21 of the semiconductor substrate 10 than the first lifetime control region 151.

[0108] The second-conductivity-type non-forming region 181 is a region in which the second-conductivity-type portion 82-2 is not formed on the back surface 23 side of the semiconductor substrate 10 in top view. The second-conductivity-type forming region 182 is a region in which the second-conductivity-type portion 82-2 is formed on the back surface 23 side of the semiconductor substrate 10 in top view. Even in the case where the second-conductivity-type portion 82-2 is formed above the first-conductivity-type portion 82-1 as in this example, it is possible to form a repeating structure in which the second-conductivity-type non-forming region 181 and the second-conductivity-type forming region 182 are alternately and repeatedly arranged in top view.

[0109] Fig. 1E is a diagram showing a modified example of the cross section taken along the line aa' in Fig. 1B. Differences from Fig. 1C will be described using Fig. 1E.

[0110] 1E , the depth position of the lower end of the trench bottom region 65 is located closer to the front surface 21 than the depth positions of the trench bottoms of the multiple trench portions. The depth position of the upper end of the trench bottom region 65 is located deeper than the base region 14. The depth position of the upper end of the trench bottom region 65 may be located deeper than the accumulation region 16. A drift region 18 may be provided between the trench bottom region 65 and the accumulation region 16.

[0111] The trench bottom region 65 is provided such that the depth position of its lower end is shallower than the depth positions of the lower ends of the gate trench portion 40 and the dummy trench portion 30. In other words, the trench bottom region 65 does not have to cover the trench bottoms of the gate trench portion 40 and the dummy trench portion 30. Even in such a case, it is possible to increase the gate capacitance of the transistor portion 70 and reduce the on-loss Eon of the semiconductor device 100.

[0112] 2A shows an example of a top view of the semiconductor device 100. The positional relationship between the trench bottom region 65, the second-conductivity-type non-forming region 181, and the second-conductivity-type forming region 182 in the semiconductor device 100 of this example will be described using FIG. 2A. For simplicity, only the components necessary for the description are shown in the subsequent figures, and other components are omitted.

[0113] The transistor section 70 has a plurality of trench bottom regions 65 repeatedly provided in the trench extension direction of the plurality of trench sections (in this example, the Y-axis direction). The transistor section 70 has a plurality of trench bottomless regions 66 repeatedly provided in the trench extension direction and sandwiched between the plurality of trench bottom regions 65. The trench bottom regions 65 and the trench bottomless regions 66 are provided extending from the transistor section 70 toward the diode section 80 in the trench arrangement direction, but do not reach the diode section 80, terminating at the first boundary section 190.

[0114] A width W65 of the trench bottom region 65 in the trench arrangement direction may be the same as the width of the transistor section 70 in the trench arrangement direction, or may be smaller than the width of the transistor section 70 in the trench arrangement direction. The trench bottom region 65 may be provided extending from one end to the other end of the transistor section 70 in the trench arrangement direction.

[0115] The multiple trench bottom regions 65 are repeatedly arranged at a predetermined trench bottom repetition period P65. The trench bottom repetition period P65 may be the distance from one end of one trench bottom region 65 in the trench extension direction, beyond the other end of the trench bottom region, to an adjacent trench bottom region 65. In one example, the trench bottom repetition period P65 is the distance from the end edge on the negative Y-axis side of trench bottom region 65b to the end edge on the negative Y-axis side of trench bottom region 65c.

[0116] The trench bottom repetition period P65 is larger than the back surface side repetition period P82 described below. The trench bottom repetition period P65 may be an integer multiple of the back surface side repetition period P82. In one example, the trench bottom repetition period P65 is 5 μm or more and 200 μm or less.

[0117] In a top view, the area of ​​the trench bottom region 65 is larger than the area of ​​the trench bottomless region 66. In one example, in one trench bottom repetition period P65, the width L65 of the trench bottom region 65 in the trench extension direction is larger than the width L66 of the trench bottomless region 66 in the trench extension direction. In one example, in one trench bottom repetition period P65, the width L65 of the trench bottom region 65 in the trench extension direction is not less than 1 time and not more than 10 times the width L66 of the trench bottomless region 66. Furthermore, the width L65 of the trench bottom region 65 in the trench extension direction may be larger than the width L181 of the second-conductivity-type non-forming region 181 in the trench extension direction and may be larger than the width L182 of the second-conductivity-type forming region 182 in the trench extension direction.

[0118] The areas of the multiple trench bottomless regions 66 sandwiched between the multiple trench bottom regions 65 may be approximately the same. In one example, the areas of the multiple trench bottomless regions 66 sandwiched between the multiple trench bottom regions 65 are each 85% or more and 115% or less of a predetermined reference value. In one example, the area of ​​trench bottomless region 66a in top view is the same as the area of ​​trench bottomless region 66b. By making the areas of the multiple trench bottomless regions 66 uniform, the magnitude of the electron current that flows when the semiconductor device 100 is switched on can be made uniform.

[0119] The predetermined reference value may be the area of ​​any one of the areas of the plurality of trench bottomless regions 66. The predetermined reference value may be the average value, the minimum value, or the maximum value of the areas of the plurality of trench bottomless regions 66.

[0120] 2A , the second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 extend in the trench arrangement direction (the X-axis direction in this example) and are alternately arranged in the trench extension direction. The second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 extend from the diode section 80 toward the transistor section 70 in the trench arrangement direction, but terminate at a second boundary section 290 without reaching the transistor section 70.

[0121] The width W181 of the second-conductivity-type non-forming region 181 in the trench arrangement direction may be the same as the width of the diode section 80 in the trench arrangement direction, or may be smaller than the width of the diode section 80 in the trench arrangement direction. The second-conductivity-type non-forming region 181 may be provided extending from one end to the other end of the diode section 80 in the trench arrangement direction.

[0122] The second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 are alternately arranged at a predetermined back-surface-side repetition period P82. The back-surface-side repetition period P82 may be the distance from one end of one second-conductivity-type non-forming region 181 in the trench extension direction, beyond the other end of the second-conductivity-type non-forming region 181, to the adjacent second-conductivity-type non-forming region 181. In one example, the back-surface-side repetition period P82 is the distance from the end edge on the Y-axis positive side of the second-conductivity-type non-forming region 181a to the end edge on the Y-axis positive side of the second-conductivity-type non-forming region 181b.

[0123] The back surface side repetition period P82 is smaller than the trench bottom repetition period P65. The back surface side repetition period P82 may be 20 μm, 30 μm, or 50 μm. In one example, the back surface side repetition period P82 is 10 μm or more and 100 μm or less.

[0124] The second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 may be alternately arranged in the trench extension direction or alternately arranged in the trench arrangement direction. In the example shown in FIG. 2A , the second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 extend in the trench arrangement direction and are alternately arranged in the trench extension direction. By alternately arranging the second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 in the trench extension direction, alignment during manufacturing of the semiconductor device 100 is facilitated, and variation in the characteristics of the semiconductor device 100 can be reduced.

[0125] 2A, in each back-surface-side repetitive period P82, the areas of the second-conductivity-type non-forming region 181 and the second-conductivity-type forming region 182 are the same. In the example of FIG. 2A, the areas of the second-conductivity-type non-forming region 181a and the second-conductivity-type forming region 182a are the same.

[0126] In the back-surface-side repetition period P82, the areas of the second-conductivity-type non-forming region 181 and the second-conductivity-type forming region 182 may be different. In one back-surface-side repetition period P82, the width L181 of the second-conductivity-type non-forming region 181 in the trench extension direction may be different from the width L182 of the second-conductivity-type forming region in the trench extension direction. In one example, the width L181 of the second-conductivity-type non-forming region 181 in the trench extension direction is 30% to 70% of the sum of the width L181 of the second-conductivity-type non-forming region 181 and the width L182 of the second-conductivity-type forming region 182 in the trench extension direction. In other words, the area of ​​the second-conductivity-type non-forming region 181 may be 30% to 70% of the area of ​​the back-surface-side region 82. The difference between the width L181 of the second conductivity type non-forming region 181 in the trench extension direction and the width L182 of the second conductivity type forming region 182 in the trench extension direction makes it easier to uniformize the electron current when the semiconductor device 100 is on.

[0127] In the top view, the shortest distance from each end 166 of the plurality of trench bottomless regions 66 to the second-conductivity-type non-forming region 181 is 85% or more and 115% or less of a predetermined reference value. In this example, each end 166 of the plurality of trench bottomless regions 66 is a corner of the trench bottomless region 66.

[0128] The predetermined reference value may be the shortest distance from any one of the multiple end portions 166 to the second-conductivity-type non-forming region 181. The predetermined reference value may be the average value, minimum value, or maximum value of the shortest distances from the multiple end portions 166 to the second-conductivity-type non-forming region 181.

[0129] In the example shown in FIG. 2A , d1 denotes the shortest distance from the end 166a on the positive side of the Y-axis of the trench bottomless region 66a to the second-conductivity-type non-forming region 181c. Also, d2 to d6 are the shortest distances from the end 166b of the trench bottomless region 66a, the end 166c and end 166d of the trench bottomless region 66b, and the end 166e and end 166f of the trench bottomless region 66c to the second-conductivity-type non-forming region 181. The shortest distances d1 to d6 from the end 166 of each of the multiple trench bottomless regions 66 to the multiple second-conductivity-type non-forming regions 181 are all substantially the same. In this example, the distance from the end 166 of each of the multiple trench bottomless regions 66 to the second-conductivity-type non-forming region 181 is uniform for each of the multiple trench bottomless regions 66. This uniformizes the electron current that flows when the semiconductor device 100 is switched on, thereby reducing on-loss Eon.

[0130] In the trench arrangement direction of the multiple trench portions, each of the multiple trench bottomless regions 66 faces one of the multiple second-conductivity type non-forming regions 181. In the example shown in Figure 2A, the trench bottomless region 66a faces the second-conductivity type non-forming region 181c, the trench bottomless region 66b faces the second-conductivity type non-forming region 181e, and the trench bottomless region 66c faces the second-conductivity type non-forming region 181g. By arranging them in this manner, the length of the path through which electron current flows when the semiconductor device 100 is switched on can be made uniform in each trench bottomless region 66, thereby reducing on-loss Eon.

[0131] The second-conductivity-type non-forming region 181 and the second-conductivity-type forming region 182 may be provided symmetrically with respect to the center line of one of the multiple trench bottomless regions 66 in the trench extension direction. In one example, the trench bottomless region 66b and the second-conductivity-type non-forming region 181e are provided so that their center lines coincide, and the second-conductivity-type forming region 182d and the second-conductivity-type non-forming region 181d are provided in this order on the positive side of the Y-axis based on the center line, and the second-conductivity-type forming region 182e and the second-conductivity-type non-forming region 181f are provided in this order on the negative side of the Y-axis based on the center line. By arranging them in this manner, the length of the path through which electron current flows when the semiconductor device 100 is switched on can be made uniform in each trench bottomless region 66, thereby reducing on-loss Eon.

[0132] 2B shows a modified top view of the semiconductor device 100. Differences from FIG. 2A will be described with reference to FIG.

[0133] In the example shown in Figure 2B, the trench bottom repeat period P65 is the same as in the example shown in Figure 2A. However, the width L65 of the trench bottom region is smaller than in the example shown in Figure 2A, and the width L66 of the trench bottomless region is larger than in the example shown in Figure 2A. In other words, the area occupied by the trench bottomless region 66 in one trench bottom repeat period P65 is larger than in the example shown in Figure 2A.

[0134] 2B, the width L181 of the second-conductivity-type non-forming region 181 and the width L182 of the second-conductivity-type forming region 182 are smaller than those in the example shown in Fig. 2A. That is, the back-surface-side repetition period P82 is smaller than that in the example shown in Fig. 2A. As a result, each of the multiple trench bottomless regions 66 faces two or more of the multiple second-conductivity-type non-forming regions 181 in the trench arrangement direction of the multiple trench portions.

[0135] 2B , a total of three second-conductivity-type non-forming regions 181 are provided to face one trench bottomless region 66: one second-conductivity-type non-forming region 181 having the same center line as one trench bottomless region 66, and two second-conductivity-type non-forming regions 181 provided line-symmetrically on both sides of the center line of the second-conductivity-type non-forming region 181. Even in this case, the shortest distances d1 to d6 from the respective ends 166 of the multiple trench bottomless regions 66 to the second-conductivity-type non-forming regions 181 are all substantially the same. This allows the electron current from the trench bottomless region 66 to be uniformly dispersed, thereby reducing the on-loss Eon of the semiconductor device 100.

[0136] It should be noted that the number of second-conductivity-type non-forming regions 181 facing one trench bottomless region 66 is not limited to this example. One trench bottomless region 66 may face two second-conductivity-type non-forming regions 181, or may face four or more second-conductivity-type non-forming regions 181.

[0137] 2C shows a modified top view of the semiconductor device 100. Differences from FIG. 2A will be described with reference to FIG.

[0138] In this example, the second-conductivity-type non-forming region 181 has a predetermined length L181x in the trench arrangement direction of the multiple trench portions (in this example, the X direction) and a predetermined width L181y in the trench extension direction of the multiple trench portions (in this example, the Y direction). The length L181x and the width L181y may be approximately the same, so that the second-conductivity-type non-forming region 181 may be provided in a substantially square shape in top view. The length L181x and the width L181y may be different.

[0139] 2C , the second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 are arranged alternately and repeatedly in two directions. The second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 may have an arrangement direction period P82x in the trench arrangement direction of the multiple trench portions (in this example, the X direction) and an extension direction period P82y in the trench extension direction of the multiple trench portions (in this example, the Y direction).

[0140] The arrangement direction period P82x and the extension direction period P82y may be substantially the same, whereby the second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 may be provided in a dot shape in a top view. Even in such a case, the distance from each end 166 of each trench bottomless region 66 to the second-conductivity-type non-forming region 181 can be made uniform, thereby reducing the on-loss Eon. The arrangement direction period P82x and the extension direction period P82y may be different.

[0141] 2D shows a modified top view of the semiconductor device 100. Fig. 2D is an example of a top view in the case where the depth positions of the lower ends of the plurality of trench bottom regions 65 are located closer to the front surface 21 of the semiconductor substrate 10 than the depth positions of the trench bottoms of the plurality of trench portions, as in Fig. 1E.

[0142] 2D , the multiple trench bottom regions 65 do not cover the trench bottoms of the multiple trench portions. Therefore, in a top view, the multiple trench bottom regions 65 are provided only in the mesa portion of the transistor portion 70. In the example of FIG. 2D , the electron current also flows through the trench bottomless region 66, and therefore, as in the cases described with reference to FIGS. 2A to 2C , the distance from each end 166 of each trench bottomless region 66 to the second-conductivity-type non-forming region 181 can be made uniform, thereby reducing the on-loss Eon.

[0143] 3A shows a modified top view of the semiconductor device 100. In the example of Fig. 3A, the trench bottom repetition period P65 and the back surface side repetition period P82 are the same as those in the example of Fig. 2A. The example of Fig. 3A differs from the example of Fig. 2A in that the trench bottomless region 66 faces the second conductivity type forming region 182 in the trench arrangement direction.

[0144] In the trench arrangement direction of the multiple trench portions, each of the multiple trench bottomless regions 66 may face one of the multiple second-conductivity type-forming regions 182. In other words, in the trench arrangement direction, each of the multiple trench bottomless regions 66 does not have to face one of the multiple second-conductivity type non-forming regions 181. In the example shown in FIG. 3A , the trench bottomless region 66a faces the second-conductivity type-forming region 182a, the trench bottomless region 66b faces the second-conductivity type-forming region 182c, the trench bottomless region 66c faces the second-conductivity type-forming region 182e, and the trench bottomless region 66d faces the second-conductivity type-forming region 182g.

[0145] 2A , the shortest distances d1 to d6 from the end 166 of each of the plurality of trench bottomless regions 66 to the second-conductivity-type non-forming region 181 are all substantially the same. Therefore, the length of the path through which the electron current flows when the semiconductor device 100 is switched on can be made uniform in each trench bottomless region 66, thereby reducing the on-loss Eon.

[0146] The distance W indicates the deviation width between the end 166 of the trench bottomless region 66 in the trench extension direction and the second-conductivity-type non-forming region 181 in a top view. In this example, the end 166 does not face the second-conductivity-type non-forming region 181, so the distance W is greater than 0. The distance W may be greater than 0 and equal to or less than 50% of the width of the trench bottom region 65 in the trench extension direction.

[0147] 3B shows a modified top view of the semiconductor device 100. Differences from FIG. 2B will be described with reference to FIG.

[0148] In the trench arrangement direction of the multiple trench portions, each of the multiple trench bottomless regions 66 may face two or more of the multiple second-conductivity-type-forming regions 182. In the example of FIG. 3B , a total of three second-conductivity-type-forming regions 182 are provided to face one trench bottomless region 66: one second-conductivity-type-forming region 182 having the same center line as one trench bottomless region 66, and two second-conductivity-type-forming regions 182 provided line-symmetrically on both sides of the center line of the second-conductivity-type-forming region 182. Even in this case, the shortest distances d1 to d6 from the respective ends 166 of the multiple trench bottomless regions 66 to the second-conductivity-type non-forming regions 181 are all substantially the same. This allows the electron current from the trench bottomless region 66 to be uniformly dispersed, thereby reducing the on-loss Eon of the semiconductor device 100.

[0149] 4 shows a modified top view of the semiconductor device 100. Differences from FIG. 2A will be described with reference to FIG.

[0150] 4, the second-conductivity-type non-forming regions 181 and the second-conductivity-type forming regions 182 extend in the trench extension direction and are alternately arranged in the trench arrangement direction. In the example of Fig. 4, the second-conductivity-type non-forming regions 181 are provided perpendicular to the arrangement direction of the plurality of trench bottomless regions 66, so that the shortest distances d1 to d6 from the end portions 166 of the plurality of trench bottomless regions 66 to the second-conductivity-type non-forming regions 181 are all the same. This allows the electron current from the trench bottomless regions 66 to be uniformly dispersed, thereby reducing the on-loss Eon of the semiconductor device 100.

[0151] 5 shows an example of a top view of a semiconductor device 500 of the comparative example. The semiconductor device 500 of the comparative example has a plurality of trench bottom regions 565 repeatedly provided in the trench extension direction of a plurality of trench portions, and a plurality of trench bottomless regions 566 repeatedly provided in the trench extension direction and sandwiched between the plurality of trench bottom regions 565. The semiconductor device 500 of the comparative example has second-conductivity-type non-forming regions 581 and second-conductivity-type forming regions 582 extending in the trench arrangement direction and arranged alternately in the trench extension direction.

[0152] In the semiconductor device 500 of the comparative example, there is no restriction on the position at which the trench bottomless region 566 is provided and the position at which the second-conductivity-type non-forming region 581 is provided. That is, in the semiconductor device 500 of the comparative example, the second-conductivity-type non-forming region 581 and the second-conductivity-type forming region 582 are not provided line-symmetrically with respect to the center line of one trench bottomless region 566.

[0153] In the semiconductor device 500 of the comparative example, there are no restrictions on the positions at which the trench bottomless regions 566 are provided and the positions at which the second-conductivity-type non-forming regions 581 are provided, and therefore the shortest distance from the end of each trench bottomless region 566 to the second-conductivity-type non-forming region 581 varies for each trench bottomless region 566. That is, in the semiconductor device 500 of the comparative example, the shortest distances d1 to d6 are not approximately the same.

[0154] In the semiconductor device 100 of this example, there are certain restrictions on the positions at which the trench bottomless regions are provided and the positions at which the second-conductivity-type non-forming regions are provided, so the shortest distances from the ends of each of the plurality of trench bottomless regions to the second-conductivity-type non-forming regions can be made uniform, i.e., the shortest distances d1 to d6 from the ends of each of the plurality of trench bottomless regions to the second-conductivity-type non-forming regions can all be made substantially the same.

[0155] 6A shows an example of a top view of the semiconductor device 200. The semiconductor device 200 is a semiconductor chip having a transistor section 70 and a diode section 80.

[0156] The semiconductor device 200 differs from the semiconductor device 100 in the shapes of the transistor section 70 and the diode section 80. In the semiconductor device 200, the diode section 80 is provided so as to surround the outer periphery of the transistor section 70. The semiconductor device 200 may include a plurality of unit structures, each of which has the outer periphery of the transistor section 70 surrounded by the diode section 80. The semiconductor device 200 of this example includes a total of nine unit structures, each of which is repeated three times in the X-axis direction and three times in the Y-axis direction.

[0157] 6B shows an example of a top view of the semiconductor device 200. In this example, an enlarged view of region B in FIG. 6A is shown.

[0158] The transistor section 70 has a plurality of trench sections including the gate trench section 40 and the dummy trench section 30. The diode section 80 has a plurality of trench sections including the dummy trench section 30. Note that the diode section 80 does not necessarily have to have a trench section.

[0159] The transistor section 70 has a plurality of trench bottom regions 65 repeatedly provided in the trench extension direction of the plurality of trench sections (in this example, the Y-axis direction). The transistor section 70 has a plurality of trench bottomless regions 66 repeatedly provided in the trench extension direction and sandwiched between the plurality of trench bottom regions 65. The trench bottom regions 65 and the trench bottomless regions 66 are provided extending from the transistor section 70 toward the diode section 80 in the trench arrangement direction, and terminate without reaching the diode section 80.

[0160] The diode section 80 of the present example has second-conductivity-type non-forming regions 181 and second-conductivity-type forming regions 182 that are alternately provided in the trench extension direction of the plurality of trench sections in a region facing the plurality of trench bottomless regions 66. As a result, even when the diode section 80 surrounds the outer periphery of the transistor section 70, the electron current that flows when the semiconductor device 200 is switched on can be made uniform, and the on-loss Eon can be reduced.

[0161] The diode section 80 may not have the second-conductivity-type-forming region 182 in a region that does not face the plurality of trench bottomless regions 66. In this example, the second-conductivity-type-forming region 182 is not provided in the diode section 80 that is adjacent to the transistor section 70 in the trench extension direction of the plurality of trench sections. In this example, the trench bottom of the gate trench section 40 in the trench extension direction is covered with the trench bottom region 65, so that no electron current flows. Therefore, in the region that does not face the plurality of trench bottomless regions 66, even if a structure in which the second-conductivity-type non-forming regions 181 and the second-conductivity-type-forming regions 182 are not alternately arranged is not used, and the on-loss Eon of the semiconductor device 200 is not affected.

[0162] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0163] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0164] 10...Semiconductor substrate, 11...Anode region, 12...Emitter region, 14...Base region, 15...First contact region, 16...Accumulation region, 17...Well region, 18...Drift region, 19...Second contact region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 27...Trench contact portion, 30...Dummy trench portion, 31...Extended portion, 32...Dummy insulating film, 33...Connection portion, 34...Dummy conductive portion, 38...Interlayer insulating film, 40...Gate trench portion, 41...Extended portion, 42...Gate insulating film, 43...Connection portion, 44...Gate conductive portion, 50...Gate metal layer, 52...Emitter electrode, 54...Contact hole, 55...Contact hole, 56...Contact hole 160... semiconductor device, 65... trench bottom region, 66... ​​trench bottomless region, 70... transistor portion, 71... mesa portion, 80... diode portion, 81... mesa portion, 82... back surface side region, 82-1... first conductivity type portion, 82-2... second conductivity type portion, 100... semiconductor device, 110... active region, 120... peripheral region, 130... gate pad, 151... first lifetime control region, 152... second lifetime control region, 166... ​​end portion, 181... second conductivity type non-forming region, 182... second conductivity type forming region, 190... first boundary portion, 191... mesa portion, 200... semiconductor device, 290... second boundary portion, 291... mesa portion, 500... semiconductor device, 565... trench bottom region, 566... ​​trench bottomless region, 581... second conductivity type non-forming region, 582... second conductivity type forming region

Claims

1. A semiconductor device including a transistor portion and a diode portion, a first conductivity type drift region provided in a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate; a collector region of a second conductivity type provided below the drift region; Equipped with The transistor section a second conductivity type base region provided above the drift region; an emitter region of a first conductivity type having a doping concentration higher than that of the drift region; a first contact region of a second conductivity type having a doping concentration higher than that of the base region; a plurality of trench bottom regions of a second conductivity type repeatedly provided below the base region in the trench extension direction; a plurality of trench bottomless regions that are repeatedly provided in the trench extension direction and are sandwiched between the plurality of trench bottom regions; and The diode section an anode region of a second conductivity type provided above the drift region; a back surface side region provided below the drift region; and the back surface side region includes a first conductivity type portion of a first conductivity type and a second conductivity type portion of a second conductivity type, the first conductivity type portion and the second conductivity type portion are provided to form a repeating structure in which second conductivity type forming regions in which the second conductivity type portions are formed and second conductivity type non-forming regions in which the second conductivity type portions are not formed are alternately and repeatedly arranged in a predetermined direction in a top view, When viewed from above, the shortest distance from each end of the plurality of trench bottomless regions to the second conductivity type non-forming region is 85% or more and 115% or less of a predetermined reference value. Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein the second-conductivity-type non-forming regions and the second-conductivity-type forming regions extend in the trench extension direction in a top view and are alternately arranged in the trench arrangement direction of the plurality of trench portions.

3. 2. The semiconductor device according to claim 1, wherein the second-conductivity-type non-forming regions and the second-conductivity-type forming regions extend in a trench arrangement direction of the plurality of trench portions in a top view and are alternately arranged in the trench extension direction.

4. 2. The semiconductor device according to claim 1, wherein an area of ​​said second-conductivity-type non-forming region is 30% or more and 70% or less of an area of ​​said back-surface-side region when viewed from above.

5. the back surface side region has a plurality of the second conductivity type non-forming regions, 2 . The semiconductor device according to claim 1 , wherein each of the plurality of trench bottomless regions faces one of the plurality of second-conductivity-type non-forming regions in a trench arrangement direction of the plurality of trench portions.

6. the back surface side region has a plurality of the second conductivity type non-forming regions, 2 . The semiconductor device according to claim 1 , wherein each of the plurality of trench bottomless regions faces two or more of the plurality of second-conductivity-type non-forming regions in a trench arrangement direction of the plurality of trench portions.

7. the back surface side region has a plurality of the second conductivity type forming regions, 2 . The semiconductor device according to claim 1 , wherein each of the plurality of trench bottomless regions faces one of the plurality of second conductivity type forming regions in a trench arrangement direction of the plurality of trench portions.

8. the back surface side region has a plurality of the second conductivity type forming regions, 2 . The semiconductor device according to claim 1 , wherein each of the plurality of trench bottomless regions faces two or more of the plurality of second conductivity type forming regions in a trench arrangement direction of the plurality of trench portions.

9. 2. The semiconductor device according to claim 1, wherein the areas of the plurality of trench bottomless regions sandwiched between the plurality of trench bottom regions are 85% or more and 115% or less of a predetermined reference value, respectively.

10. the transistor portion is provided adjacent to the diode portion and has a first boundary portion above the drift region where the first contact region is not provided; The diode section a second contact region of a second conductivity type provided above the drift region and having a doping concentration higher than that of the anode region; a second boundary portion provided adjacent to the transistor portion and in which the second contact region is not provided; and The semiconductor device according to claim 1 , wherein the rear surface of the semiconductor substrate has the first conductivity type portion at the second boundary portion.

11. 11. The semiconductor device according to claim 1, wherein the second-conductivity-type non-forming region and the second-conductivity-type forming region are arranged symmetrically with respect to a center line of one of the plurality of trench bottomless regions in the trench extension direction.

12. the second-conductivity-type non-forming regions and the second-conductivity-type forming regions are alternately arranged at a predetermined rear-surface-side repetition period; the plurality of trench bottom regions are repeatedly arranged at a predetermined trench bottom repeating period; The semiconductor device according to claim 1 , wherein the trench bottom repetition period is greater than the back surface side repetition period.

13. The semiconductor device according to claim 12 , wherein the rear surface side repetition period is not less than 10 μm and not more than 100 μm.

14. The semiconductor device according to claim 12 , wherein the trench bottom repetition period is an integer multiple of the back surface side repetition period.

15. the first conductivity type portion is provided in contact with a rear surface of the semiconductor substrate, The semiconductor device according to claim 1 , wherein the second conductivity type portion is provided in contact with a rear surface of the semiconductor substrate and adjacent to the first conductivity type portion.

16. the first conductivity type portion is provided in contact with a rear surface of the semiconductor substrate, The semiconductor device according to claim 1 , wherein the second conductivity type portion is provided above the first conductivity type portion.

17. 11. The semiconductor device according to claim 1, wherein, in a depth direction of the semiconductor substrate, depth positions of lower ends of the plurality of trench bottom regions are provided closer to the front surface than depth positions of trench bottoms of the plurality of trench portions.

18. A semiconductor device described in any one of claims 1 to 10, wherein the diode portion is arranged surrounding the outer periphery of the transistor portion.

19. A semiconductor device described in any one of claims 1 to 10, wherein the second conductivity type forming region is not provided in the diode portion adjacent to the transistor portion in the trench extension direction.

20. A semiconductor device described in any one of claims 1 to 10, wherein the second conductivity type non-forming regions and the second conductivity type forming regions are arranged alternately in the trench arrangement direction of the multiple trench portions and the trench extension direction when viewed from above.