Method for manufacturing semiconductor light-receiving element

Abstract

A plurality of semiconductor light-receiving elements (2) are formed on a wafer-form semiconductor substrate (1). A wafer test is performed for inspecting electrical characteristics of each of the plurality of semiconductor light-receiving elements (2). An ink (22) is applied to the semiconductor light receiving element (2) that has failed in the wafer test. When forming the semiconductor light-receiving element (2), a semiconductor layer (4) having at least a light absorbing layer (8) is formed on the semiconductor substrate (1), an annular upper surface electrode (13) in which a light receiving part (12) is opened is formed on the semiconductor layer (4), and a first groove (15) and a second groove (16) penetrating the semiconductor layer (4) and reaching the semiconductor substrate (1) are formed. The first groove (15) surrounds the upper surface electrode (13) in plan view. The second groove (16) surrounds the first groove (15) in plan view.

Description

Manufacturing method of semiconductor light receiving element

[0001] The present disclosure relates to a method for manufacturing a semiconductor light-receiving element.

[0002] In the manufacture of semiconductor light-receiving elements, a wafer test is typically performed to inspect the electrical characteristics of each chip in the wafer state. Chips that fail the wafer test are typically coated with ink to distinguish them as passing chips. If this ink leaks out of the target chip and covers the light-receiving area or electrodes of an adjacent chip, the adjacent chip will fail in visual inspection, resulting in a decrease in yield. Meanwhile, a semiconductor light-receiving element has been proposed in which a circular groove is formed down to the light-absorbing layer in order to reduce dark current (see, for example, Patent Document 1).

[0003] Japanese Patent No. 5045436

[0004] However, the grooves in conventional semiconductor light-receiving elements are not designed to prevent ink outflow, and shallow grooves that reach the light-absorbing layer cannot prevent ink outflow. Even if the grooves were made deeper, a single groove alone would not be enough to prevent ink outflow.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its object is to provide a method for manufacturing a semiconductor light-receiving element that can prevent a decrease in yield.

[0006] The method for manufacturing a semiconductor light-receiving element according to the present disclosure comprises the steps of forming a plurality of semiconductor light-receiving elements on a wafer-shaped semiconductor substrate, conducting a wafer test to inspect the electrical characteristics of each of the plurality of semiconductor light-receiving elements, and applying ink to the semiconductor light-receiving elements that have failed the wafer test, and is characterized in that, when forming the semiconductor light-receiving elements, a semiconductor layer having at least a light-absorbing layer is formed on the semiconductor substrate, a ring-shaped upper electrode having an opening at a light-receiving portion is formed on the semiconductor layer, and first and second grooves are formed that penetrate the semiconductor layer and reach the semiconductor substrate, the first groove surrounding the upper electrode in a planar view, and the second groove surrounding the first groove in a planar view.

[0007] In the present disclosure, when forming a semiconductor light-receiving element, a first groove and a second groove are formed that penetrate the semiconductor layer and reach the semiconductor substrate. The first groove surrounds the top electrode in a plan view, and the second groove surrounds the first groove. This increases the number of times that surface tension acts on the ink, making it easier to dam the ink. Furthermore, since ink can be flowed not only into the first groove but also into the second groove, the amount of ink that flows to the outer periphery of the top surface of the semiconductor light-receiving element can be reduced. This prevents ink from flowing onto adjacent chips, preventing a decrease in yield.

[0008] 1 is a plan view showing a wafer on which a semiconductor light receiving element according to a first embodiment is formed; FIG. 2 is a cross-sectional view showing a semiconductor light receiving element according to a first embodiment; FIG. 3 is a top view showing a semiconductor light receiving element according to a first embodiment; FIG. 4 is a cross-sectional view showing a state in which semiconductor light receiving elements according to a first embodiment are adjacent to each other; FIG. 5 is a cross-sectional view showing a state in which a wafer is being tested; FIG. 6 is a cross-sectional view showing a state in which ink has been applied to a semiconductor light receiving element according to a first embodiment; FIG. 7 is a cross-sectional view showing a state in which ink has been applied to a semiconductor light receiving element according to a second embodiment; FIG. 8 is a cross-sectional view showing a semiconductor light receiving element according to a third embodiment; and FIG. 9 is a top view showing a semiconductor light receiving element according to a third embodiment.

[0009] A method for manufacturing a semiconductor light receiving element according to an embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0010] 1 is a plan view showing a wafer on which semiconductor light-receiving elements according to embodiment 1 are formed. A plurality of semiconductor light-receiving elements 2 are formed in a matrix on a wafer-shaped semiconductor substrate 1. Dicing lines 3 are formed between adjacent semiconductor light-receiving elements 2.

[0011] FIG. 2 is a cross-sectional view showing a semiconductor light-receiving element according to the first embodiment. FIG. 3 is a top view showing the semiconductor light-receiving element according to the first embodiment. A multilayer reflective layer 5, a multiplication layer 6, an electric field relaxation layer 7, a light-absorbing layer 8, a BDR layer 9, a window layer 10, and a contact layer 11 are formed in this order as semiconductor layers 4 on a semiconductor substrate 1. The semiconductor substrate 1 is, for example, n-type InP. The multilayer reflective layer 5 is formed by stacking 8 to 20 pairs of low-refractive-index layers, such as n-type InP or AlInAs, and high-refractive-index layers, such as n-type GaInAs, GaInAsP, or AlGaInAs. The multiplication layer 6 is made of i-type AlInAs or the like. The electric field relaxation layer 7 is made of p-type InP, AlInAs or the like. The light-absorbing layer 8 is made of n-type InGaAs, InGaAsP, InGaAsSb or the like. The BDR layer 9 is made of n-type InGaAsP, AlGaInAs or the like. The window layer 10 is made of p-type InP, InGaAsP, AlInAs, AlGaInAs, or a combination thereof. The contact layer 11 is made of p-type InGaAs, InP, InGaAsP, AlInAs, AlGaInAs, or a combination thereof.

[0012] An annular upper electrode 13 having an opening for a light-receiving portion 12 is formed on the contact layer 11. The upper electrode 13 is made of Ti, Pt, Au, or the like. The opening in the annular upper electrode 13 becomes the light-receiving portion 12 of the semiconductor light-receiving element 2. A lower electrode 14 is formed on the lower surface of the semiconductor substrate 1. The lower electrode 14 is made of Ti, Pt, Ni, Au, or the like.

[0013] A first groove 15 and a second groove 16 are formed penetrating the semiconductor layer 4 and reaching the semiconductor substrate 1. The first groove 15 surrounds the top electrode 13 in a plan view. The second groove 16 surrounds the first groove 15 in a plan view. Note that the second groove 16 is not limited to one groove, and a plurality of grooves may be formed concentrically as the second groove 16.

[0014] To prevent moisture and physical damage, the upper surface of the semiconductor layer 4 and the inner walls of the first groove 15 and the second groove 16 are covered with a protective film 17. However, the first groove 15 and the second groove 16 are not filled with the protective film 17, and there are cavities inside. The protective film 17 is made of SiO ２ , SiN, SiON, etc.

[0015] A peripheral barrier 18 is formed on the periphery of the upper surface of the semiconductor light-receiving element 2. The peripheral barrier 18 is made of SiO ２ The peripheral barrier 18 is made of an insulating film such as SiN or SiON, or a metal such as Ti, Pt, Ni or Au. Even if the peripheral barrier 18 is made of a metal, the peripheral barrier 18 is not connected to the electrodes of the device. Since the peripheral barrier 18 is not a semiconductor, it does not need to be covered with the protective film 17.

[0016] 4 is a cross-sectional view showing adjacent semiconductor light-receiving elements 2 according to the first embodiment. Dicing lines 3 are formed between adjacent semiconductor light-receiving elements 2. The dicing lines 3 are recessed, with no contact layer 11, protective film 17, peripheral barrier 18, electrodes, etc. formed therein. If the recesses of the dicing lines 3 are made deeper, the wafer becomes more susceptible to cracking, making handling difficult. Therefore, ink leakage cannot be prevented in shallow recesses of the dicing lines 3. Note that forming first grooves 15 and second grooves 16 in the semiconductor light-receiving elements 2 does not affect handling.

[0017] Next, a method for manufacturing a semiconductor light-receiving element according to this embodiment will be described. First, a semiconductor layer 4 including a multilayer reflective layer 5, a multiplication layer 6, an electric field relaxation layer 7, a light absorption layer 8, a BDR layer 9, a window layer 10, and a contact layer 11 is formed in this order on a semiconductor substrate 1. Next, a first groove 15 and a second groove 16 are formed by dry etching using photoresist or the like, penetrating the semiconductor layer 4 and reaching the semiconductor substrate 1. Next, a protective film 17, an upper electrode 13, a peripheral barrier 18, a lower electrode 14, and the like are formed. The peripheral barrier 18 is formed on the peripheral portion of the upper surface of the semiconductor layer 4. As a result, a plurality of semiconductor light-receiving elements 2 are formed in a matrix on the wafer-like semiconductor substrate 1.

[0018] Next, a wafer test is performed. FIG. 5 is a cross-sectional view showing the wafer test. The wafer is placed on a conductive stage 19. At this time, the bottom electrode 14 of the semiconductor light-receiving element 2 is brought into contact with the stage 19, which is connected to GND. A probe 20 is brought into contact with the top electrode 13, and a voltage is applied between the top electrode 13 and the bottom electrode 14. In this way, the current-voltage characteristics of each of the multiple semiconductor light-receiving elements 2 are inspected. A pass / fail judgment is made by checking whether the desired electrical characteristics have been obtained as a result of the inspection. The electrical characteristics of the semiconductor light-receiving element 2 may also be measured while light is incident on the light-receiving section 12.

[0019] Next, ink 22 is applied from a nozzle 21 to the semiconductor light-receiving element 2 that failed the wafer test. FIGS. 6 and 7 are cross-sectional views showing the state after ink has been applied to the semiconductor light-receiving element according to the first embodiment. The ink 22 is applied to the light-receiving portion 12, the upper surface electrode 13, and the surrounding area of ​​the semiconductor light-receiving element 2. When the amount of ink 22 is not large, the ink 22 is restricted by surface tension to the inner periphery of the first groove 15 on the upper surface of the chip, as shown in FIG. 6. When the amount of ink 22 is large, the ink 22 enters the first groove 15, but is restricted by surface tension to the inner periphery of the second groove 16 on the upper surface of the chip, as shown in FIG. 7. Even if the amount of ink 22 is large and the ink 22 flows outside the second groove 16, it is blocked by the outer barrier 18.

[0020] As described above, in this embodiment, when forming the semiconductor light-receiving element 2, the first groove 15 and the second groove 16 are formed, penetrating the semiconductor layer 4 and reaching the semiconductor substrate 1. The first groove 15 surrounds the top electrode 13 in a plan view, and the second groove 16 surrounds the first groove 15. This increases the number of times that surface tension acts on the ink 22, making it easier to dam up the ink 22. Furthermore, since the ink 22 can be poured not only into the first groove 15 but also into the second groove 16, the amount of ink 22 that flows to the outer periphery of the top surface of the semiconductor light-receiving element 2 can be reduced. This prevents the ink 22 from flowing onto adjacent chips, preventing a decrease in yield.

[0021] In addition, a peripheral barrier 18 is formed on the outer periphery of the upper surface of the semiconductor layer 4. The peripheral barrier 18 can block the ink 22 that was not blocked by the first groove 15 and the second groove 16. The thicker the peripheral barrier 18, the easier it is to block the ink 22. While forming a thick semiconductor layer increases costs, the peripheral barrier 18 made of an insulating film or metal can be formed thick. However, if the peripheral barrier 18 is made too thick, problems such as warping of the wafer occur. Therefore, it is necessary to form not only the peripheral barrier 18 but also the first groove 15 and the second groove 16.

[0022] 8 is a cross-sectional view showing a semiconductor light-receiving element according to a second embodiment. In this embodiment, when the semiconductor light-receiving element 2 is formed, a first barrier 23 and a second barrier 24 are formed on the upper surface of the semiconductor layer 4. The first barrier 23 and the second barrier 24 are made of a semiconductor such as InP, SiO ２ , SiN, SiON, or other insulating film, or a metal such as Ti, Pt, Ni, Au, etc. Although the first barrier 23 and the second barrier 24 are covered with a protective film 17, if the first barrier 23 and the second barrier 24 are not semiconductors, they do not need to be covered with the protective film 17.

[0023] The first barrier 23 surrounds the top electrode 13 in a plan view and is taller than the top electrode 13. The second barrier 24 surrounds the first barrier 23 in a plan view and is taller than the first barrier 23. More specifically, the first barrier 23 is formed between the first groove 15 and the second groove 16 in a plan view. The second barrier 24 is formed on the outer periphery of the second groove 16 in a plan view. Note that a barrier taller than the second barrier 24 may be formed on the outer periphery of the second barrier 24, thereby increasing the number of barriers to three or more. A peripheral barrier 18 is formed on the outer periphery of the top surface of the second barrier 24. The rest of the configuration of the semiconductor light-receiving element 2 is the same as in embodiment 1, and a wafer test and application of ink 22 are performed in the same manner as in embodiment 1.

[0024] As described above, in this embodiment, the first barrier 23 and the second barrier 24 are formed so as to surround the top electrode 13 in a plan view and are taller than the top electrode 13. This makes it possible to block the ink 22. Furthermore, the second barrier 24 is taller than the first barrier 23. By making the barriers taller toward the outer periphery in this way, the top surface of the chip becomes cone-shaped. This makes it easier for the ink 22 to accumulate and prevents it from spreading outward. Furthermore, even when the droplet position of the ink 22 is shifted outward from the center of the chip, the ink 22 is more likely to move toward the center of the chip. As a result, it is possible to prevent the ink 22 from flowing out to adjacent chips and prevent a decrease in yield.

[0025] Third Embodiment Fig. 9 is a cross-sectional view showing a semiconductor light-receiving element according to a third embodiment. Fig. 10 is a top view showing a semiconductor light-receiving element according to a third embodiment. In this embodiment, when forming the semiconductor light-receiving element 2, instead of forming the first groove 15 and the second groove 16 as in the first embodiment, a stepped barrier 25 is formed on the semiconductor layer 4. The stepped barrier 25 is made of a semiconductor such as InP, SiO ２ The window layer 10 is made of an insulating film such as Ti, Pt, Ni, Au, etc. Since the window layer 10 is not conductive, there is no problem even if the stepped barrier 25 is in direct contact with the window layer 10.

[0026] The stepped barrier 25 surrounds the top electrode 13 in a plan view, is taller than the top electrode 13, and increases in height toward the periphery of the top surface of the semiconductor layer 4. The stepped barrier 25 may have three or more steps. A peripheral barrier 18 is formed on the periphery of the top surface of the stepped barrier 25. The rest of the configuration of the semiconductor light-receiving element 2 is the same as in embodiment 1, and a wafer test and application of ink 22 are performed in the same manner as in embodiment 1.

[0027] As described above, in this embodiment, a stepped barrier 25 that is taller than the top electrode 13 is formed so as to surround the top electrode 13 in a plan view. This makes it possible to block the ink 22. Furthermore, the stepped barrier 25 becomes taller towards the periphery. By making the barrier taller towards the periphery in this way, the top surface of the chip becomes cone-shaped. This makes it easier for the ink 22 to accumulate and prevents it from spreading outward. Furthermore, even if the droplet position of the ink 22 is shifted outward from the center of the chip, the ink 22 is more likely to move towards the center of the chip. As a result, it is possible to prevent the ink 22 from flowing out to adjacent chips, thereby preventing a decrease in yield.

[0028] REFERENCE SIGNS LIST 1 semiconductor substrate, 2 semiconductor light receiving element, 4 semiconductor layer, 8 light absorption layer, 12 light receiving portion, 13 upper electrode, 15 first groove, 16 second groove, 18 peripheral barrier, 22 ink, 23 first barrier, 24 second barrier, 25 stepped barrier

Claims

1. A step of forming a plurality of semiconductor light-receiving elements on a wafer-shaped semiconductor substrate, a step of performing a wafer test for inspecting the electrical characteristics of each of the plurality of semiconductor light-receiving elements, and a step of applying ink to the semiconductor light-receiving elements that failed the wafer test. When forming the semiconductor light-receiving elements, a semiconductor layer having at least a light absorption layer is formed on the semiconductor substrate, an annular top electrode with an opening for a light-receiving portion is formed on the semiconductor layer, and first and second grooves are formed that penetrate the semiconductor layer and reach the semiconductor substrate. The first groove surrounds the top electrode in a plan view, and the second groove surrounds the first groove in a plan view. A method for manufacturing a semiconductor light-receiving element, characterized by the above.

2. The method for manufacturing a semiconductor light-receiving element according to claim 1, characterized in that an outer peripheral barrier is formed on the outer peripheral portion of the upper surface of the semiconductor layer when forming the semiconductor light-receiving element.

3. The method for manufacturing a semiconductor light-receiving element according to claim 1, characterized in that a first barrier and a second barrier are formed on the upper surface of the semiconductor layer when forming the semiconductor light-receiving element. The first barrier surrounds the top electrode in a plan view and has a higher height than the top electrode. The second barrier surrounds the first barrier in a plan view and has a higher height than the first barrier.

4. The method for manufacturing a semiconductor light-receiving element according to claim 3, characterized in that the first barrier is formed between the first groove and the second groove in a plan view, and the second barrier is formed on the outer peripheral side of the second groove in a plan view.

5. The method for manufacturing a semiconductor light-receiving element according to claim 3 or 4, characterized in that an outer peripheral barrier is formed on the outer peripheral portion of the upper surface of the second barrier when forming the semiconductor light-receiving element.

6. A step of forming a plurality of semiconductor light-receiving elements on a wafer-shaped semiconductor substrate, a step of performing a wafer test for inspecting the electrical characteristics of each of the plurality of semiconductor light-receiving elements, and a step of applying ink to the semiconductor light-receiving elements that failed in the wafer test. When forming the semiconductor light-receiving elements, a semiconductor layer having at least a light absorption layer is formed on the semiconductor substrate, an annular top surface electrode with an opening for a light-receiving portion is formed on the semiconductor layer, and a stepped barrier is formed on the semiconductor layer. The stepped barrier surrounds the top surface electrode in a plan view, has a height higher than that of the top surface electrode, and has a height that increases toward the outer periphery of the top surface of the semiconductor layer. A method for manufacturing a semiconductor light-receiving element characterized by this.

7. The method for manufacturing a semiconductor light-receiving element according to claim 6, wherein an outer peripheral barrier is formed on the outer peripheral portion of the top surface of the stepped barrier when forming the semiconductor light-receiving element.