Semiconductor integrated circuit device

Abstract

In the present invention, a standard cell comprises: an active region (2N1) that has an overlap with an active region (2P1) in plan view; power supply wiring (11) that is formed in a back surface wiring layer; and a via (61) that is formed in a region where a region serving as a source of a transistor (P1) in the active region (2P1) and the power supply wiring (11) overlap and connects the source in the active region (2P1) and the power supply wiring (11). Nanosheets (21), (22) have each a surface exposed from gate wiring (31) on a first side that is one side in a second direction, and are disposed close to an end on the first side of the standard cell.